Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
5,501 | data/full_repos/permissive/114421971/clb_bused/top.v | 114,421,971 | top.v | v | 87 | 83 | [] | [] | [] | null | line:41: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_bused/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_bused/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,273 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
clb_FF clb_FF (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
clb_OUT clb_OUT (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
clb_FF clb_FF (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
clb_OUT clb_OUT (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
endmodule | 2 |
5,502 | data/full_repos/permissive/114421971/clb_bused/top.v | 114,421,971 | top.v | v | 87 | 83 | [] | [] | [] | null | line:41: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_bused/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_bused/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,273 | module | module clb_FF (input clk, input [7:0] din, output [7:0] dout);
wire o6;
(* LOC="SLICE_X18Y100", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y100", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule | module clb_FF (input clk, input [7:0] din, output [7:0] dout); |
wire o6;
(* LOC="SLICE_X18Y100", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y100", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule | 2 |
5,503 | data/full_repos/permissive/114421971/clb_bused/top.v | 114,421,971 | top.v | v | 87 | 83 | [] | [] | [] | null | line:41: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_bused/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_bused/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,273 | module | module clb_OUT (input clk, input [7:0] din, output [7:0] dout);
wire o6;
assign dout[0] = o6;
(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y101", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule | module clb_OUT (input clk, input [7:0] din, output [7:0] dout); |
wire o6;
assign dout[0] = o6;
(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O(o6));
(* LOC="SLICE_X18Y101", BEL="BFF" *)
FDPE ff (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(o6));
endmodule | 2 |
5,504 | data/full_repos/permissive/114421971/clb_n5ffmux/top.v | 114,421,971 | top.v | v | 175 | 79 | [] | [] | [] | null | line:53: before: "=" | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:53: syntax error, unexpected '=', expecting ',' or ';'\n wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};\n ^\n%Error: Exiting due to 3 error(s)\n" | 6,275 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,505 | data/full_repos/permissive/114421971/clb_n5ffmux/top.v | 114,421,971 | top.v | v | 175 | 79 | [] | [] | [] | null | line:53: before: "=" | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:53: syntax error, unexpected '=', expecting ',' or ';'\n wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};\n ^\n%Error: Exiting due to 3 error(s)\n" | 6,275 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
clb_N5FFMUX # (.LOC("SLICE_X22Y100"), .N(0))
clb_N5FFMUX_0 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y101"), .N(1))
clb_N5FFMUX_1 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y102"), .N(2))
clb_N5FFMUX_2 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y103"), .N(3))
clb_N5FFMUX_3 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
clb_N5FFMUX # (.LOC("SLICE_X22Y100"), .N(0))
clb_N5FFMUX_0 (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y101"), .N(1))
clb_N5FFMUX_1 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y102"), .N(2))
clb_N5FFMUX_2 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_N5FFMUX # (.LOC("SLICE_X22Y103"), .N(3))
clb_N5FFMUX_3 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
endmodule | 2 |
5,506 | data/full_repos/permissive/114421971/clb_n5ffmux/top.v | 114,421,971 | top.v | v | 175 | 79 | [] | [] | [] | null | line:53: before: "=" | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clb_n5ffmux/top.v:53: syntax error, unexpected '=', expecting ',' or ';'\n wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};\n ^\n%Error: Exiting due to 3 error(s)\n" | 6,275 | module | module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X22Y100";
parameter N=-1;
parameter DEF_A=1;
wire lutdo, lutco, lutbo, lutao;
wire lut7bo, lut7ao;
wire lut8o;
reg [3:0] ffds;
wire lutdo5, lutco5, lutbo5, lutao5;
wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};
always @(*) begin
if (DEF_A) begin
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[N] = din[6];
end else begin
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
ffds[N] = lutno5[N];
end
end
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutdo5),
.O6(lutdo));
(* LOC=LOC, BEL="D5FF" *)
FDPE ffd (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutco5),
.O6(lutco));
(* LOC=LOC, BEL="C5FF" *)
FDPE ffc (
.C(clk),
.Q(dout[2]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutbo5),
.O6(lutbo));
(* LOC=LOC, BEL="B5FF" *)
FDPE ffb (
.C(clk),
.Q(dout[3]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutao5),
.O6(lutao));
(* LOC=LOC, BEL="A5FF" *)
FDPE ffa (
.C(clk),
.Q(dout[4]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[0]));
endmodule | module clb_N5FFMUX (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_X22Y100";
parameter N=-1;
parameter DEF_A=1;
wire lutdo, lutco, lutbo, lutao;
wire lut7bo, lut7ao;
wire lut8o;
reg [3:0] ffds;
wire lutdo5, lutco5, lutbo5, lutao5;
wire lutno5 [3:0] = {lutdo5, lutco5, lutbo5, lutao5};
always @(*) begin
if (DEF_A) begin
ffds[3] = lutdo5;
ffds[2] = lutco5;
ffds[1] = lutbo5;
ffds[0] = lutao5;
ffds[N] = din[6];
end else begin
ffds[3] = din[6];
ffds[2] = din[6];
ffds[1] = din[6];
ffds[0] = din[6];
ffds[N] = lutno5[N];
end
end
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutdo), .I1(lutco), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutbo), .I1(lutao), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutdo5),
.O6(lutdo));
(* LOC=LOC, BEL="D5FF" *)
FDPE ffd (
.C(clk),
.Q(dout[1]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutco5),
.O6(lutco));
(* LOC=LOC, BEL="C5FF" *)
FDPE ffc (
.C(clk),
.Q(dout[2]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutbo5),
.O6(lutbo));
(* LOC=LOC, BEL="B5FF" *)
FDPE ffb (
.C(clk),
.Q(dout[3]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutao5),
.O6(lutao));
(* LOC=LOC, BEL="A5FF" *)
FDPE ffa (
.C(clk),
.Q(dout[4]),
.CE(din[0]),
.PRE(din[1]),
.D(ffds[0]));
endmodule | 2 |
5,507 | data/full_repos/permissive/114421971/clb_ncy0/top.v | 114,421,971 | top.v | v | 119 | 77 | [] | [] | [] | null | line:66: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:1: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:20: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,276 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,508 | data/full_repos/permissive/114421971/clb_ncy0/top.v | 114,421,971 | top.v | v | 119 | 77 | [] | [] | [] | null | line:66: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:1: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:20: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,276 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
endmodule | 2 |
5,509 | data/full_repos/permissive/114421971/clb_ncy0/top.v | 114,421,971 | top.v | v | 119 | 77 | [] | [] | [] | null | line:66: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:1: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:20: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,276 | module | module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
always @(*) begin
s = din[7:4];
s[N] = o6;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule | module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
always @(*) begin
s = din[7:4];
s[N] = o6;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
endmodule | 2 |
5,510 | data/full_repos/permissive/114421971/clb_ncy0/top.v | 114,421,971 | top.v | v | 119 | 77 | [] | [] | [] | null | line:66: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:1: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ncy0/top.v:20: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,276 | module | module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[N] = o6;
di = {din[3:0]};
di[N] = o5;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
endmodule | module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_X16Y129_FIXME";
parameter BEL="A6LUT_FIXME";
parameter N=-1;
wire [3:0] o;
assign dout[0] = o[1];
wire o6, o5;
reg [3:0] s;
reg [3:0] di;
always @(*) begin
s = din[7:4];
s[N] = o6;
di = {din[3:0]};
di[N] = o5;
end
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_0000_0000_0001)
) lut (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(o5),
.O6(o6));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
endmodule | 2 |
5,519 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,520 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
parameter N=3;
clb_NOUTMUX_CY #(.LOC("SLICE_X18Y100"), .N(N))
clb_NOUTMUX_CY (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
generate
if (N != 3) begin
clb_NOUTMUX_F78 #(.LOC("SLICE_X18Y101"), .N(N))
clb_NOUTMUX_F78 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
end
endgenerate
clb_NOUTMUX_O5 #(.LOC("SLICE_X18Y102"), .N(N))
clb_NOUTMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
clb_NOUTMUX_XOR #(.LOC("SLICE_X18Y104"), .N(N))
clb_NOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ]));
clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N))
clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
parameter N=3;
clb_NOUTMUX_CY #(.LOC("SLICE_X18Y100"), .N(N))
clb_NOUTMUX_CY (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
generate
if (N != 3) begin
clb_NOUTMUX_F78 #(.LOC("SLICE_X18Y101"), .N(N))
clb_NOUTMUX_F78 (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
end
endgenerate
clb_NOUTMUX_O5 #(.LOC("SLICE_X18Y102"), .N(N))
clb_NOUTMUX_O5 (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
clb_NOUTMUX_XOR #(.LOC("SLICE_X18Y104"), .N(N))
clb_NOUTMUX_XOR (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8 ]));
clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N))
clb_NOUTMUX_B5Q (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8 ]));
endmodule | 2 |
5,521 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module myLUT8 (input clk, input [7:0] din,
output lut8o, output lut7bo, output lut7ao,
output caro, output carco,
output bo5, output bo6,
output wire ff_q);
parameter N=-1;
parameter LOC="SLICE_FIXME";
wire [3:0] caro_all;
assign caro = caro_all[N];
wire [3:0] carco_all;
assign carco = carco_all[N];
wire [3:0] lutno6;
assign bo6 = lutno6[N];
wire [3:0] lutno5;
assign bo5 = lutno5[N];
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[3]),
.O6(lutno6[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[2]),
.O6(lutno6[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[1]),
.O6(lutno6[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[0]),
.O6(lutno6[0]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
generate
if (N == 3) begin
(* LOC=LOC, BEL="D5FF", KEEP, DONT_TOUCH *)
FDPE d5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[3]));
end
if (N == 2) begin
(* LOC=LOC, BEL="C5FF", KEEP, DONT_TOUCH *)
FDPE c5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[2]));
end
if (N == 1) begin
(* LOC=LOC, BEL="B5FF", KEEP, DONT_TOUCH *)
FDPE b5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[1]));
end
if (N == 0) begin
(* LOC=LOC, BEL="A5FF", KEEP, DONT_TOUCH *)
FDPE a5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[0]));
end
endgenerate
endmodule | module myLUT8 (input clk, input [7:0] din,
output lut8o, output lut7bo, output lut7ao,
output caro, output carco,
output bo5, output bo6,
output wire ff_q); |
parameter N=-1;
parameter LOC="SLICE_FIXME";
wire [3:0] caro_all;
assign caro = caro_all[N];
wire [3:0] carco_all;
assign carco = carco_all[N];
wire [3:0] lutno6;
assign bo6 = lutno6[N];
wire [3:0] lutno5;
assign bo5 = lutno5[N];
(* LOC=LOC, BEL="F8MUX", KEEP, DONT_TOUCH *)
MUXF8 mux8 (.O(lut8o), .I0(lut7bo), .I1(lut7ao), .S(din[6]));
(* LOC=LOC, BEL="F7BMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7b (.O(lut7bo), .I0(lutno6[3]), .I1(lutno6[2]), .S(din[6]));
(* LOC=LOC, BEL="F7AMUX", KEEP, DONT_TOUCH *)
MUXF7 mux7a (.O(lut7ao), .I0(lutno6[1]), .I1(lutno6[0]), .S(din[6]));
(* LOC=LOC, BEL="D6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_DEAD_0000_0001)
) lutd (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[3]),
.O6(lutno6[3]));
(* LOC=LOC, BEL="C6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_BEEF_0000_0001)
) lutc (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[2]),
.O6(lutno6[2]));
(* LOC=LOC, BEL="B6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_CAFE_0000_0001)
) lutb (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[1]),
.O6(lutno6[1]));
(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
LUT6_2 #(
.INIT(64'h8000_1CE0_0000_0001)
) luta (
.I0(din[0]),
.I1(din[1]),
.I2(din[2]),
.I3(din[3]),
.I4(din[4]),
.I5(din[5]),
.O5(lutno5[0]),
.O6(lutno6[0]));
(* LOC=LOC, KEEP, DONT_TOUCH *)
CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
generate
if (N == 3) begin
(* LOC=LOC, BEL="D5FF", KEEP, DONT_TOUCH *)
FDPE d5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[3]));
end
if (N == 2) begin
(* LOC=LOC, BEL="C5FF", KEEP, DONT_TOUCH *)
FDPE c5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[2]));
end
if (N == 1) begin
(* LOC=LOC, BEL="B5FF", KEEP, DONT_TOUCH *)
FDPE b5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[1]));
end
if (N == 0) begin
(* LOC=LOC, BEL="A5FF", KEEP, DONT_TOUCH *)
FDPE a5ff (
.C(clk),
.Q(ff_q),
.CE(1'b1),
.PRE(1'b0),
.D(lutno5[0]));
end
endgenerate
endmodule | 2 |
5,522 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module clb_NOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(), .carco(),
.bo5(dout[0]), .bo6(),
.ff_q());
endmodule | module clb_NOUTMUX_O5 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(), .carco(),
.bo5(dout[0]), .bo6(),
.ff_q());
endmodule | 2 |
5,523 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module clb_NOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(dout[0]), .carco(),
.bo5(), .bo6(),
.ff_q());
endmodule | module clb_NOUTMUX_XOR (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din), .lut8o(),
.caro(dout[0]), .carco(),
.bo5(), .bo6(),
.ff_q());
endmodule | 2 |
5,524 | data/full_repos/permissive/114421971/clb_noutmux/top.v | 114,421,971 | top.v | v | 275 | 101 | [] | [] | [] | null | line:81: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_noutmux/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,279 | module | module clb_NOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din),
.lut8o(),
.caro(), .carco(),
.bo5(), .bo6(),
.ff_q(dout[0]));
endmodule | module clb_NOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
parameter N=1;
myLUT8 #(.LOC(LOC), .N(N))
myLUT8(.clk(clk), .din(din),
.lut8o(),
.caro(), .carco(),
.bo5(), .bo6(),
.ff_q(dout[0]));
endmodule | 2 |
5,525 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,526 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
my_RAM64X1D2 #(.LOC("SLICE_X6Y100"))
dut0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X6Y127"))
dut1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y100"))
dut2(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y127"))
dut3(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
my_RAM64X1D2 #(.LOC("SLICE_X6Y100"))
dut0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X6Y127"))
dut1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y100"))
dut2(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
my_RAM64X1D2 #(.LOC("SLICE_X12Y127"))
dut3(.clk(clk), .din(din[ 128 +: 8]), .dout(dout[ 128 +: 8]));
endmodule | 2 |
5,527 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) ramb (
.DPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) rama (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule | module my_RAM64X1D2 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) ramb (
.DPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) rama (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule | 2 |
5,528 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
wire mc31c;
(* LOC=LOC, BEL=BEL *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lut (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule | module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
parameter BEL="A6LUT";
wire mc31c;
(* LOC=LOC, BEL=BEL *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lut (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule | 2 |
5,529 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_SRL16E (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
SRL16E #(
) SRL16E (
.Q(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule | module my_SRL16E (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
SRL16E #(
) SRL16E (
.Q(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.CE(din[4]),
.CLK(din[5]),
.D(din[6]));
endmodule | 2 |
5,530 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64M (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64M #(
) RAM64M (
.DOA(dout[0]),
.DOB(dout[1]),
.DOC(dout[2]),
.DOD(dout[3]),
.ADDRA(din[0]),
.ADDRB(din[1]),
.ADDRC(din[2]),
.ADDRD(din[3]),
.DIA(din[4]),
.DIB(din[5]),
.DIC(din[6]),
.DID(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule | module my_RAM64M (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64M #(
) RAM64M (
.DOA(dout[0]),
.DOB(dout[1]),
.DOC(dout[2]),
.DOD(dout[3]),
.ADDRA(din[0]),
.ADDRB(din[1]),
.ADDRC(din[2]),
.ADDRD(din[3]),
.DIA(din[4]),
.DIB(din[5]),
.DIC(din[6]),
.DID(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule | 2 |
5,531 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64X1S #(
) RAM64X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule | module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
parameter BEL="A6LUT";
(* LOC=LOC, BEL=BEL *)
RAM64X1S #(
) RAM64X1S (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule | 2 |
5,532 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S_1 #(
) RAM64X1S_1 (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule | module my_RAM64X1S_1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
(* LOC=LOC *)
RAM64X1S_1 #(
) RAM64X1S_1 (
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D(din[6]),
.WCLK(clk),
.WE(din[0]));
endmodule | 2 |
5,533 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X2S #(
) RAM64X2S (
.O0(dout[0]),
.O1(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D0(din[6]),
.D1(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule | module my_RAM64X2S (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
(* LOC=LOC *)
RAM64X2S #(
) RAM64X2S (
.O0(dout[0]),
.O1(dout[1]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.D0(din[6]),
.D1(din[7]),
.WCLK(clk),
.WE(din[1]));
endmodule | 2 |
5,534 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM64X1D (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule | module my_RAM64X1D (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
(* LOC=LOC *)
RAM64X1D #(
.INIT(64'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM64X1D (
.DPO(dout[0]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]),
.A0(din[3]),
.A1(din[4]),
.A2(din[5]),
.A3(din[6]),
.A4(din[7]),
.A5(din[0]),
.DPRA0(din[1]),
.DPRA1(din[2]),
.DPRA2(din[3]),
.DPRA3(din[4]),
.DPRA4(din[5]),
.DPRA5(din[6]));
endmodule | 2 |
5,535 | data/full_repos/permissive/114421971/clb_ram/top.v | 114,421,971 | top.v | v | 325 | 84 | [] | [] | [] | null | line:170: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_ram/top.v:15: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_ram/top.v:34: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,280 | module | module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
(* LOC=LOC *)
RAM128X1D #(
.INIT(128'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM128X1D (
.DPO(dout[0]),
.SPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]));
endmodule | module my_RAM128X1D (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
(* LOC=LOC *)
RAM128X1D #(
.INIT(128'h0),
.IS_WCLK_INVERTED(1'b0)
) RAM128X1D (
.DPO(dout[0]),
.SPO(dout[1]),
.D(din[0]),
.WCLK(clk),
.WE(din[2]));
endmodule | 2 |
5,536 | data/full_repos/permissive/114421971/clkbuf/top.v | 114,421,971 | top.v | v | 11 | 50 | [] | [] | [] | null | line:2: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clkbuf/top.v:3: Cannot find file containing module: 'FDRE'\n FDRE ff (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clkbuf,data/full_repos/permissive/114421971/FDRE\n data/full_repos/permissive/114421971/clkbuf,data/full_repos/permissive/114421971/FDRE.v\n data/full_repos/permissive/114421971/clkbuf,data/full_repos/permissive/114421971/FDRE.sv\n FDRE\n FDRE.v\n FDRE.sv\n obj_dir/FDRE\n obj_dir/FDRE.v\n obj_dir/FDRE.sv\n%Error: Exiting due to 1 error(s)\n" | 6,281 | module | module top (input c, d, output q);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C(c),
.CE(1'b1),
.R(1'b0),
.D(d),
.Q(q)
);
endmodule | module top (input c, d, output q); |
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C(c),
.CE(1'b1),
.R(1'b0),
.D(d),
.Q(q)
);
endmodule | 2 |
5,582 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,583 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
rom_ROM128X1 #(.LOC("XXX"))
rom_ROM128X1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
rom_ROM256X1 #(.LOC("XXX"))
rom_ROM256X1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
rom_ROM32X1 #(.LOC("XXX"))
rom_ROM32X1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
rom_ROM64X1 #(.LOC("XXX"))
rom_ROM64X1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
rom_ROM128X1 #(.LOC("XXX"))
rom_ROM128X1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
rom_ROM256X1 #(.LOC("XXX"))
rom_ROM256X1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
rom_ROM32X1 #(.LOC("XXX"))
rom_ROM32X1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
rom_ROM64X1 #(.LOC("XXX"))
rom_ROM64X1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
endmodule | 2 |
5,584 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM128X1 #(.INIT(128'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]));
endmodule | module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
ROM128X1 #(.INIT(128'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]));
endmodule | 2 |
5,585 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module rom_ROM256X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM256X1 #(.INIT(256'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.A7(din[7]));
endmodule | module rom_ROM256X1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
ROM256X1 #(.INIT(256'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.A7(din[7]));
endmodule | 2 |
5,586 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module rom_ROM32X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM32X1 #(.INIT(32'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]));
endmodule | module rom_ROM32X1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
ROM32X1 #(.INIT(32'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]));
endmodule | 2 |
5,587 | data/full_repos/permissive/114421971/rom/top.v | 114,421,971 | top.v | v | 112 | 82 | [] | [] | [] | [(8, 34), (36, 45), (53, 67), (69, 83), (85, 96), (98, 110)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,302 | module | module rom_ROM64X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM64X1 #(.INIT(64'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]));
endmodule | module rom_ROM64X1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC="SLICE_FIXME";
ROM64X1 #(.INIT(64'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]));
endmodule | 2 |
5,588 | data/full_repos/permissive/114459345/srcCache/cache.v | 114,459,345 | cache.v | v | 133 | 123 | [] | [] | [] | null | line:305: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/cache.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:11: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`ValidBitBus] wvalid_bit,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:12: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:13: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:17: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:18: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:19: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`DataAddrBus] miss_addr,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:23: Define or directive not defined: \'`DataAddrBus\'\n output reg[`DataAddrBus] miss_addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:25: Define or directive not defined: \'`CacheBus\'\n input wire[`CacheBus] rewrite_data\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:28: Define or directive not defined: \'`PowIndexBus\'\n reg Pres[`PowIndexBus];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] Tags[`PowIndexBus];\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] Tags[`PowIndexBus];\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:29: Define or directive not defined: \'`PowIndexBus\'\n reg[`TagBus] Tags[`PowIndexBus];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: Define or directive not defined: \'`CacheBus\'\n reg[`CacheBus] data_cache[`PowIndexBus];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`CacheBus] data_cache[`PowIndexBus];\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:30: Define or directive not defined: \'`PowIndexBus\'\n reg[`CacheBus] data_cache[`PowIndexBus];\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:32: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] rtag;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] rtag;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:33: Define or directive not defined: \'`IndexBus\'\n reg[`IndexBus] rindex;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`IndexBus] rindex;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:34: Define or directive not defined: \'`SelectBus\'\n reg[`SelectBus] rselect;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`SelectBus] rselect;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:36: Define or directive not defined: \'`TagBus\'\n reg[`TagBus] wtag;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`TagBus] wtag;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:37: Define or directive not defined: \'`IndexBus\'\n reg[`IndexBus] windex;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`IndexBus] windex;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:38: Define or directive not defined: \'`SelectBus\'\n reg[`SelectBus] wselect;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`SelectBus] wselect;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:42: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:44: Define or directive not defined: \'`NotPresent\'\n Pres[i] = `NotPresent;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:57: Define or directive not defined: \'`ChipDisable\'\n if(cache_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:58: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:60: Define or directive not defined: \'`WriteEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:60: Define or directive not defined: \'`ReadEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:63: Define or directive not defined: \'`ReadEnable\'\n else if(re == `ReadEnable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:64: Define or directive not defined: \'`NotPresent\'\n if(Pres[rindex] == `NotPresent) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:65: Define or directive not defined: \'`Miss\'\n miss = `Miss;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:71: Define or directive not defined: \'`Byte\'\n `Byte : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:79: Define or directive not defined: \'`Half\'\n `Half : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:87: Define or directive not defined: \'`Word\'\n `Word : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:96: Define or directive not defined: \'`Miss\'\n miss = `Miss;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:110: Define or directive not defined: \'`Present\'\n Pres[rindex] <= `Present;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:122: Define or directive not defined: \'`ChipDisable\'\n if(cache_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:125: Define or directive not defined: \'`WriteEnable\'\n else if(we == `WriteEnable) begin \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/cache.v:126: Define or directive not defined: \'`NotPresent\'\n Pres[windex[11:2]] <= `NotPresent; \n ^~~~~~~~~~~\n%Error: Exiting due to 48 error(s)\n' | 6,305 | module | module cache(
input wire cache_ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o,
output reg miss,
output reg[`DataAddrBus] miss_addr,
input wire[`CacheBus] rewrite_data
);
reg Pres[`PowIndexBus];
reg[`TagBus] Tags[`PowIndexBus];
reg[`CacheBus] data_cache[`PowIndexBus];
reg[`TagBus] rtag;
reg[`IndexBus] rindex;
reg[`SelectBus] rselect;
reg[`TagBus] wtag;
reg[`IndexBus] windex;
reg[`SelectBus] wselect;
integer i;
initial begin
for(i = 0; i < 1024; i = i + 1) begin
Pres[i] = `NotPresent;
end
end
always @(*) begin
rtag <= raddr[31:12];
rindex <= raddr[11:2];
rselect <= raddr[1:0];
end
always @ (*) begin
if(cache_ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= {data_i[7:0],data_i[15:8],data_i[23:16],data_i[31:24]};
end
else if(re == `ReadEnable) begin
if(Pres[rindex] == `NotPresent) begin
miss = `Miss;
miss_addr <= raddr;
end
else begin
if(Tags[rindex] == rtag) begin
case(rvalid_bit)
`Byte : begin
case(rselect)
2'b00 : data_o <= {{24{1'b0}}, data_cache[rindex][7:0]};
2'b01 : data_o <= {{24{1'b0}}, data_cache[rindex][15:8]};
2'b10 : data_o <= {{24{1'b0}}, data_cache[rindex][23:16]};
2'b11 : data_o <= {{24{1'b0}}, data_cache[rindex][31:24]};
endcase
end
`Half : begin
case(rselect)
2'b00 : data_o <= {{16{1'b0}}, data_cache[rindex][7:0],data_cache[rindex][15:8]};
2'b10 : data_o <= {{16{1'b0}}, data_cache[rindex][23:16],data_cache[rindex][31:24]};
endcase
end
`Word : begin
data_o <= {data_cache[rindex][7:0], data_cache[rindex][15:8], data_cache[rindex][23:16],data_cache[rindex][31:24]};
end
default begin
end
endcase
end
else begin
miss = `Miss;
miss_addr <= raddr;
end
end
end
else begin
end
end
always @ (*) begin
data_cache[rindex] <= rewrite_data;
Tags[rindex] <= rtag;
Pres[rindex] <= `Present;
end
always @(*) begin
wtag <= waddr[31:12];
windex <= waddr[11:2];
wselect <= waddr[1:0];
end
always @ (*) begin
if(cache_ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
Pres[windex[11:2]] <= `NotPresent;
end
else begin
end
end
endmodule | module cache(
input wire cache_ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o,
output reg miss,
output reg[`DataAddrBus] miss_addr,
input wire[`CacheBus] rewrite_data
); |
reg Pres[`PowIndexBus];
reg[`TagBus] Tags[`PowIndexBus];
reg[`CacheBus] data_cache[`PowIndexBus];
reg[`TagBus] rtag;
reg[`IndexBus] rindex;
reg[`SelectBus] rselect;
reg[`TagBus] wtag;
reg[`IndexBus] windex;
reg[`SelectBus] wselect;
integer i;
initial begin
for(i = 0; i < 1024; i = i + 1) begin
Pres[i] = `NotPresent;
end
end
always @(*) begin
rtag <= raddr[31:12];
rindex <= raddr[11:2];
rselect <= raddr[1:0];
end
always @ (*) begin
if(cache_ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= {data_i[7:0],data_i[15:8],data_i[23:16],data_i[31:24]};
end
else if(re == `ReadEnable) begin
if(Pres[rindex] == `NotPresent) begin
miss = `Miss;
miss_addr <= raddr;
end
else begin
if(Tags[rindex] == rtag) begin
case(rvalid_bit)
`Byte : begin
case(rselect)
2'b00 : data_o <= {{24{1'b0}}, data_cache[rindex][7:0]};
2'b01 : data_o <= {{24{1'b0}}, data_cache[rindex][15:8]};
2'b10 : data_o <= {{24{1'b0}}, data_cache[rindex][23:16]};
2'b11 : data_o <= {{24{1'b0}}, data_cache[rindex][31:24]};
endcase
end
`Half : begin
case(rselect)
2'b00 : data_o <= {{16{1'b0}}, data_cache[rindex][7:0],data_cache[rindex][15:8]};
2'b10 : data_o <= {{16{1'b0}}, data_cache[rindex][23:16],data_cache[rindex][31:24]};
endcase
end
`Word : begin
data_o <= {data_cache[rindex][7:0], data_cache[rindex][15:8], data_cache[rindex][23:16],data_cache[rindex][31:24]};
end
default begin
end
endcase
end
else begin
miss = `Miss;
miss_addr <= raddr;
end
end
end
else begin
end
end
always @ (*) begin
data_cache[rindex] <= rewrite_data;
Tags[rindex] <= rtag;
Pres[rindex] <= `Present;
end
always @(*) begin
wtag <= waddr[31:12];
windex <= waddr[11:2];
wselect <= waddr[1:0];
end
always @ (*) begin
if(cache_ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
Pres[windex[11:2]] <= `NotPresent;
end
else begin
end
end
endmodule | 0 |
5,589 | data/full_repos/permissive/114459345/srcCache/ctrl.v | 114,459,345 | ctrl.v | v | 39 | 38 | [] | [] | [] | [(223, 252)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:6: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:19: Define or directive not defined: \'`CtrlWidth\'\n output reg[`CtrlWidth] stall\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output reg[`CtrlWidth] stall\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:23: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:26: Define or directive not defined: \'`Stop\'\n else if(req_id == `Stop) begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ctrl.v:29: Define or directive not defined: \'`Stop\'\n else if(req_if == `Stop) begin\n ^~~~~\n%Error: Exiting due to 6 error(s)\n' | 6,306 | module | module ctrl(
input wire rst,
input wire req_id,
input wire req_if,
output reg[`CtrlWidth] stall
);
always @ (*) begin
if(rst == `RstEnable) begin
stall <= 6'b000000;
end
else if(req_id == `Stop) begin
stall <= 6'b000111;
end
else if(req_if == `Stop) begin
stall <= 6'b000011;
end
else begin
stall <= 6'b000000;
end
end
endmodule | module ctrl(
input wire rst,
input wire req_id,
input wire req_if,
output reg[`CtrlWidth] stall
); |
always @ (*) begin
if(rst == `RstEnable) begin
stall <= 6'b000000;
end
else if(req_id == `Stop) begin
stall <= 6'b000111;
end
else if(req_if == `Stop) begin
stall <= 6'b000011;
end
else begin
stall <= 6'b000000;
end
end
endmodule | 0 |
5,590 | data/full_repos/permissive/114459345/srcCache/data_ram.v | 114,459,345 | data_ram.v | v | 94 | 132 | [] | [] | [] | [(219, 309)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:10: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`ValidBitBus] wvalid_bit,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:11: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:12: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:16: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:17: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:18: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:22: Define or directive not defined: \'`DataMemNum\'\n reg[7:0] data_mem[0:`DataMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:25: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:26: Define or directive not defined: \'`DataMemNum\'\n for(i = 0; i < `DataMemNum; i = i + 1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:33: Define or directive not defined: \'`ChipDisable\'\n if(ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:36: Define or directive not defined: \'`WriteEnable\'\n else if(we == `WriteEnable) begin \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:38: Define or directive not defined: \'`Byte\'\n `Byte : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:42: Define or directive not defined: \'`Half\'\n `Half : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:47: Define or directive not defined: \'`Word\'\n `Word : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:69: Define or directive not defined: \'`ChipDisable\'\n if(ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:70: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:72: Define or directive not defined: \'`WriteEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:72: Define or directive not defined: \'`ReadEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:75: Define or directive not defined: \'`ReadEnable\'\n else if(re == `ReadEnable) begin \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:77: Define or directive not defined: \'`Byte\'\n `Byte : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:80: Define or directive not defined: \'`Half\'\n `Half : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:83: Define or directive not defined: \'`Word\'\n `Word : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/data_ram.v:90: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 26 error(s)\n' | 6,307 | module | module data_ram(
input wire ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o
);
reg[7:0] data_mem[0:`DataMemNum-1];
integer i;
initial begin
for(i = 0; i < `DataMemNum; i = i + 1) begin
data_mem[i] = 8'h00;
end
end
always @ (*) begin
if(ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
case(wvalid_bit)
`Byte : begin
data_mem[waddr] <= data_i[7:0];
end
`Half : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
end
`Word : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
data_mem[waddr+2] <= data_i[23:16];
data_mem[waddr+3] <= data_i[31:24];
end
default : begin
end
endcase
end
end
always @ (*) begin
if(ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= data_i;
end
else if(re == `ReadEnable) begin
case(rvalid_bit)
`Byte : begin
data_o <= {{24{1'b0}}, data_mem[raddr]};
end
`Half : begin
data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
end
`Word : begin
data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
end
endcase
end
else begin
data_o <= `ZeroWord;
end
end
endmodule | module data_ram(
input wire ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o
); |
reg[7:0] data_mem[0:`DataMemNum-1];
integer i;
initial begin
for(i = 0; i < `DataMemNum; i = i + 1) begin
data_mem[i] = 8'h00;
end
end
always @ (*) begin
if(ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
case(wvalid_bit)
`Byte : begin
data_mem[waddr] <= data_i[7:0];
end
`Half : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
end
`Word : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
data_mem[waddr+2] <= data_i[23:16];
data_mem[waddr+3] <= data_i[31:24];
end
default : begin
end
endcase
end
end
always @ (*) begin
if(ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= data_i;
end
else if(re == `ReadEnable) begin
case(rvalid_bit)
`Byte : begin
data_o <= {{24{1'b0}}, data_mem[raddr]};
end
`Half : begin
data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
end
`Word : begin
data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
end
endcase
end
else begin
data_o <= `ZeroWord;
end
end
endmodule | 0 |
5,591 | data/full_repos/permissive/114459345/srcCache/ex.v | 114,459,345 | ex.v | v | 277 | 86 | [] | [] | [] | [(219, 492)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/ex.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:10: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:11: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] alufunct3_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:12: Define or directive not defined: \'`AluFunct7Bus\'\n input wire[`AluFunct7Bus] alufunct7_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] imm_i, \n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:16: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg[`AluOpBus] aluop_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:20: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:21: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] alufunct3_o, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`MemAddrBus] maddr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:23: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] maddr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:25: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o, \n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_f,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:30: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_f,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:31: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_f\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:36: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] shiftbits = reg2_i[4:0];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] shiftbits = reg2_i[4:0];\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:39: Define or directive not defined: \'`MemAddrBus\'\n reg[`MemAddrBus] maddr; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`MemAddrBus] maddr; \n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:40: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] logicout; \n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] logicout; \n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:44: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:45: Define or directive not defined: \'`MemDisable\'\n me <= `MemDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:46: Define or directive not defined: \'`NopMem\'\n maddr <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:47: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:50: Define or directive not defined: \'`MemDisable\'\n me <= `MemDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:51: Define or directive not defined: \'`NopMem\'\n maddr <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:52: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:55: Define or directive not defined: \'`LUI\'\n `LUI : begin\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:58: Define or directive not defined: \'`AUIPC\'\n `AUIPC : begin\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:61: Define or directive not defined: \'`JAL\'\n `JAL : begin\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:64: Define or directive not defined: \'`JALR\'\n `JALR : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:68: Define or directive not defined: \'`LOAD\'\n `LOAD : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:69: Define or directive not defined: \'`MemEnable\'\n me <= `MemEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:89: Define or directive not defined: \'`STORE\'\n `STORE : begin\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:90: Define or directive not defined: \'`MemEnable\'\n me <= `MemEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:105: Define or directive not defined: \'`EXE_IMM\'\n `EXE_IMM : begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:107: Define or directive not defined: \'`ADDI\'\n `ADDI : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:110: Define or directive not defined: \'`SLTI\'\n `SLTI : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:112: Define or directive not defined: \'`OneWord\'\n logicout <= `OneWord;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:115: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:118: Define or directive not defined: \'`SLTIU\'\n `SLTIU : begin\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:120: Define or directive not defined: \'`OneWord\'\n logicout <= `OneWord;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex.v:123: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,309 | module | module ex(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`AluOpBus] aluop_i,
input wire[`AluFunct3Bus] alufunct3_i,
input wire[`AluFunct7Bus] alufunct7_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] imm_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
output reg[`AluOpBus] aluop_o,
output reg[`AluFunct3Bus] alufunct3_o,
output reg me_o,
output reg[`MemAddrBus] maddr_o,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg[`RegBus] wdata_o,
output reg wreg_f,
output reg[`RegAddrBus] wd_f,
output reg[`RegBus] wdata_f
);
wire[`RegAddrBus] shiftbits = reg2_i[4:0];
reg me;
reg[`MemAddrBus] maddr;
reg[`RegBus] logicout;
always @ (*) begin
if(rst == `RstEnable) begin
me <= `MemDisable;
maddr <= `NopMem;
logicout <= `ZeroWord;
end
else begin
me <= `MemDisable;
maddr <= `NopMem;
logicout <= `ZeroWord;
case(aluop_i)
`LUI : begin
logicout <= reg1_i;
end
`AUIPC : begin
logicout <= reg1_i + pc_i;
end
`JAL : begin
logicout <= pc_i + 4;
end
`JALR : begin
logicout <= pc_i + 4;
end
`LOAD : begin
me <= `MemEnable;
maddr <= reg1_i + imm_i;
end
`STORE : begin
me <= `MemEnable;
maddr <= reg1_i + imm_i;
logicout <= reg2_i;
end
`EXE_IMM : begin
case(alufunct3_i)
`ADDI : begin
logicout <= reg1_i + reg2_i;
end
`SLTI : begin
if($signed(reg1_i) < $signed(reg2_i)) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`SLTIU : begin
if(reg1_i < reg2_i) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`XORI : begin
logicout <= reg1_i ^ reg2_i;
end
`ORI : begin
logicout <= reg1_i | reg2_i;
end
`ANDI : begin
logicout <= reg1_i & reg2_i;
end
`SLLI : begin
logicout <= reg1_i << shiftbits;
end
`SRLI_SRAI : begin
case(alufunct7_i)
`SRLI : begin
logicout <= reg1_i >> shiftbits;
end
`SRAI : begin
logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
end
endcase
end
endcase
end
`EXE : begin
case(alufunct3_i)
`ADD_SUB : begin
case(alufunct7_i)
`ADD : begin
logicout <= $signed(reg1_i) + $signed(reg2_i);
end
`SUB : begin
logicout <= $signed(reg1_i) - $signed(reg2_i);
end
endcase
end
`SLL : begin
logicout <= reg1_i << shiftbits;
end
`SLT : begin
if($signed(reg1_i) < $signed(reg2_i)) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`SLTU : begin
if(reg1_i < reg2_i) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`XOR : begin
logicout <= reg1_i ^ reg2_i;
end
`SRL_SRA : begin
case(alufunct7_i)
`SRL : begin
logicout <= reg1_i >> shiftbits;
end
`SRA : begin
logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
end
endcase
end
`OR : begin
logicout <= reg1_i | reg2_i;
end
`AND : begin
logicout <= reg1_i & reg2_i;
end
endcase
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
aluop_o <= `NOP;
alufunct3_o <= `NOP_FUNCT3;
me_o <= `MemDisable;
maddr_o <= `NopMem;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
wdata_o <= `ZeroWord;
end
else begin
aluop_o <= aluop_i;
alufunct3_o <= alufunct3_i;
me_o <= me;
maddr_o <= maddr;
wreg_o <= wreg_i;
wd_o <= wd_i;
wdata_o <= logicout;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_f <= `WriteDisable;
wd_f <= `NopRegAddr;
wdata_f <= `ZeroWord;
end
else begin
if(aluop_i == `LOAD) begin
wreg_f <= `WriteDisable;
end
else begin
wreg_f <= wreg_o;
end
wd_f <= wd_o;
wdata_f <= wdata_o;
end
end
endmodule | module ex(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`AluOpBus] aluop_i,
input wire[`AluFunct3Bus] alufunct3_i,
input wire[`AluFunct7Bus] alufunct7_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] imm_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
output reg[`AluOpBus] aluop_o,
output reg[`AluFunct3Bus] alufunct3_o,
output reg me_o,
output reg[`MemAddrBus] maddr_o,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg[`RegBus] wdata_o,
output reg wreg_f,
output reg[`RegAddrBus] wd_f,
output reg[`RegBus] wdata_f
); |
wire[`RegAddrBus] shiftbits = reg2_i[4:0];
reg me;
reg[`MemAddrBus] maddr;
reg[`RegBus] logicout;
always @ (*) begin
if(rst == `RstEnable) begin
me <= `MemDisable;
maddr <= `NopMem;
logicout <= `ZeroWord;
end
else begin
me <= `MemDisable;
maddr <= `NopMem;
logicout <= `ZeroWord;
case(aluop_i)
`LUI : begin
logicout <= reg1_i;
end
`AUIPC : begin
logicout <= reg1_i + pc_i;
end
`JAL : begin
logicout <= pc_i + 4;
end
`JALR : begin
logicout <= pc_i + 4;
end
`LOAD : begin
me <= `MemEnable;
maddr <= reg1_i + imm_i;
end
`STORE : begin
me <= `MemEnable;
maddr <= reg1_i + imm_i;
logicout <= reg2_i;
end
`EXE_IMM : begin
case(alufunct3_i)
`ADDI : begin
logicout <= reg1_i + reg2_i;
end
`SLTI : begin
if($signed(reg1_i) < $signed(reg2_i)) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`SLTIU : begin
if(reg1_i < reg2_i) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`XORI : begin
logicout <= reg1_i ^ reg2_i;
end
`ORI : begin
logicout <= reg1_i | reg2_i;
end
`ANDI : begin
logicout <= reg1_i & reg2_i;
end
`SLLI : begin
logicout <= reg1_i << shiftbits;
end
`SRLI_SRAI : begin
case(alufunct7_i)
`SRLI : begin
logicout <= reg1_i >> shiftbits;
end
`SRAI : begin
logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
end
endcase
end
endcase
end
`EXE : begin
case(alufunct3_i)
`ADD_SUB : begin
case(alufunct7_i)
`ADD : begin
logicout <= $signed(reg1_i) + $signed(reg2_i);
end
`SUB : begin
logicout <= $signed(reg1_i) - $signed(reg2_i);
end
endcase
end
`SLL : begin
logicout <= reg1_i << shiftbits;
end
`SLT : begin
if($signed(reg1_i) < $signed(reg2_i)) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`SLTU : begin
if(reg1_i < reg2_i) begin
logicout <= `OneWord;
end
else begin
logicout <= `ZeroWord;
end
end
`XOR : begin
logicout <= reg1_i ^ reg2_i;
end
`SRL_SRA : begin
case(alufunct7_i)
`SRL : begin
logicout <= reg1_i >> shiftbits;
end
`SRA : begin
logicout <= (reg1_i >> shiftbits) | ({32{1'b1}} << (`RegWidth - shiftbits));
end
endcase
end
`OR : begin
logicout <= reg1_i | reg2_i;
end
`AND : begin
logicout <= reg1_i & reg2_i;
end
endcase
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
aluop_o <= `NOP;
alufunct3_o <= `NOP_FUNCT3;
me_o <= `MemDisable;
maddr_o <= `NopMem;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
wdata_o <= `ZeroWord;
end
else begin
aluop_o <= aluop_i;
alufunct3_o <= alufunct3_i;
me_o <= me;
maddr_o <= maddr;
wreg_o <= wreg_i;
wd_o <= wd_i;
wdata_o <= logicout;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_f <= `WriteDisable;
wd_f <= `NopRegAddr;
wdata_f <= `ZeroWord;
end
else begin
if(aluop_i == `LOAD) begin
wreg_f <= `WriteDisable;
end
else begin
wreg_f <= wreg_o;
end
wd_f <= wd_o;
wdata_f <= wdata_o;
end
end
endmodule | 0 |
5,592 | data/full_repos/permissive/114459345/srcCache/ex_mem.v | 114,459,345 | ex_mem.v | v | 62 | 44 | [] | [] | [] | [(219, 277)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] ex_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus] ex_aluop,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:14: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] ex_alufunct3,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`MemAddrBus] ex_maddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:16: Define or directive not defined: \'`MemAddrBus\'\n input wire[`MemAddrBus] ex_maddr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] ex_wd,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:18: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:19: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:22: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] mem_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:23: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] mem_alufunct3,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`MemAddrBus] mem_maddr,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:25: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] mem_maddr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] mem_wd,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:27: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] mem_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:28: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_wdata\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:33: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:34: Define or directive not defined: \'`ChipDisable\'\n ce <= `ChipDisable; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:37: Define or directive not defined: \'`ChipEnable\'\n ce <= `ChipEnable; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:42: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:43: Define or directive not defined: \'`NOP\'\n mem_aluop <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:44: Define or directive not defined: \'`NOP_FUNCT3\'\n mem_alufunct3 <= `NOP_FUNCT3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:45: Define or directive not defined: \'`MemDisable\'\n mem_me <= `MemDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:46: Define or directive not defined: \'`NopMem\'\n mem_maddr <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:47: Define or directive not defined: \'`WriteDisable\'\n mem_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:48: Define or directive not defined: \'`NopRegAddr\'\n mem_wd <= `NopRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/ex_mem.v:49: Define or directive not defined: \'`ZeroWord\'\n mem_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 27 error(s)\n' | 6,310 | module | module ex_mem(
input wire clk,
input wire rst,
output reg ce,
input wire[`AluOpBus] ex_aluop,
input wire[`AluFunct3Bus] ex_alufunct3,
input wire ex_me,
input wire[`MemAddrBus] ex_maddr,
input wire ex_wreg,
input wire[`RegAddrBus] ex_wd,
input wire[`RegBus] ex_wdata,
output reg[`AluOpBus] mem_aluop,
output reg[`AluFunct3Bus] mem_alufunct3,
output reg mem_me,
output reg[`MemAddrBus] mem_maddr,
output reg mem_wreg,
output reg[`RegAddrBus] mem_wd,
output reg[`RegBus] mem_wdata
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ce <= `ChipDisable;
end
else begin
ce <= `ChipEnable;
end
end
always @ (posedge clk) begin
if(rst == `RstEnable) begin
mem_aluop <= `NOP;
mem_alufunct3 <= `NOP_FUNCT3;
mem_me <= `MemDisable;
mem_maddr <= `NopMem;
mem_wreg <= `WriteDisable;
mem_wd <= `NopRegAddr;
mem_wdata <= `ZeroWord;
end
else begin
mem_aluop <= ex_aluop;
mem_alufunct3 <= ex_alufunct3;
mem_me <= ex_me;
mem_maddr <= ex_maddr;
mem_wreg <= ex_wreg;
mem_wd <= ex_wd;
mem_wdata <= ex_wdata;
end
end
endmodule | module ex_mem(
input wire clk,
input wire rst,
output reg ce,
input wire[`AluOpBus] ex_aluop,
input wire[`AluFunct3Bus] ex_alufunct3,
input wire ex_me,
input wire[`MemAddrBus] ex_maddr,
input wire ex_wreg,
input wire[`RegAddrBus] ex_wd,
input wire[`RegBus] ex_wdata,
output reg[`AluOpBus] mem_aluop,
output reg[`AluFunct3Bus] mem_alufunct3,
output reg mem_me,
output reg[`MemAddrBus] mem_maddr,
output reg mem_wreg,
output reg[`RegAddrBus] mem_wd,
output reg[`RegBus] mem_wdata
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ce <= `ChipDisable;
end
else begin
ce <= `ChipEnable;
end
end
always @ (posedge clk) begin
if(rst == `RstEnable) begin
mem_aluop <= `NOP;
mem_alufunct3 <= `NOP_FUNCT3;
mem_me <= `MemDisable;
mem_maddr <= `NopMem;
mem_wreg <= `WriteDisable;
mem_wd <= `NopRegAddr;
mem_wdata <= `ZeroWord;
end
else begin
mem_aluop <= ex_aluop;
mem_alufunct3 <= ex_alufunct3;
mem_me <= ex_me;
mem_maddr <= ex_maddr;
mem_wreg <= ex_wreg;
mem_wd <= ex_wd;
mem_wdata <= ex_wdata;
end
end
endmodule | 0 |
5,593 | data/full_repos/permissive/114459345/srcCache/id.v | 114,459,345 | id.v | v | 338 | 95 | [] | [] | [] | [(219, 553)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/id.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:10: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] inst_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] reg1_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] reg2_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:20: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_read_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:21: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:22: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg2_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:25: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] pc_o,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:26: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:27: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] alufunct3_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:28: Define or directive not defined: \'`AluFunct7Bus\'\n output reg[`AluFunct7Bus] alufunct7_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg1_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:30: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg2_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:31: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] imm_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:33: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg jump_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`InstAddrBus] jpc_o\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:40: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] jpc_o\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:47: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:53: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:54: Define or directive not defined: \'`IType\'\n inst_type <= `IType; \n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:57: Define or directive not defined: \'`IType\'\n inst_type <= `IType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:59: Define or directive not defined: \'`LUI\'\n `LUI : inst_type <= `UType;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:59: Define or directive not defined: \'`UType\'\n `LUI : inst_type <= `UType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:60: Define or directive not defined: \'`AUIPC\'\n `AUIPC : inst_type <= `UType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:60: Define or directive not defined: \'`UType\'\n `AUIPC : inst_type <= `UType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:61: Define or directive not defined: \'`JAL\'\n `JAL : inst_type <= `JType;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:61: Define or directive not defined: \'`JType\'\n `JAL : inst_type <= `JType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:62: Define or directive not defined: \'`JALR\'\n `JALR : inst_type <= `IType;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:62: Define or directive not defined: \'`IType\'\n `JALR : inst_type <= `IType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:63: Define or directive not defined: \'`BRANCH\'\n `BRANCH : inst_type <= `BType;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:63: Define or directive not defined: \'`BType\'\n `BRANCH : inst_type <= `BType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:64: Define or directive not defined: \'`LOAD\'\n `LOAD : inst_type <= `IType;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:64: Define or directive not defined: \'`IType\'\n `LOAD : inst_type <= `IType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:65: Define or directive not defined: \'`STORE\'\n `STORE : inst_type <= `SType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:65: Define or directive not defined: \'`SType\'\n `STORE : inst_type <= `SType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:66: Define or directive not defined: \'`EXE_IMM\'\n `EXE_IMM : inst_type <= `IType;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:66: Define or directive not defined: \'`IType\'\n `EXE_IMM : inst_type <= `IType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:67: Define or directive not defined: \'`EXE\'\n `EXE : inst_type <= `RType;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:67: Define or directive not defined: \'`RType\'\n `EXE : inst_type <= `RType;\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:76: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:77: Define or directive not defined: \'`NopInst\'\n pc_o <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id.v:78: Define or directive not defined: \'`NOP\'\n aluop_o <= `NOP;\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,311 | module | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire reg1_suc,
input wire[`RegBus] reg1_data_i,
input wire reg2_suc,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`InstAddrBus] pc_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluFunct3Bus] alufunct3_o,
output reg[`AluFunct7Bus] alufunct7_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegBus] imm_o,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg stall_req,
output reg jump_o,
output reg[`InstAddrBus] jpc_o
);
wire[6:0] op = inst_i[6:0];
reg[2:0] inst_type;
reg[`RegBus] imm;
always @ (*) begin
if(rst == `RstEnable) begin
inst_type <= `IType;
end
else begin
inst_type <= `IType;
case(op)
`LUI : inst_type <= `UType;
`AUIPC : inst_type <= `UType;
`JAL : inst_type <= `JType;
`JALR : inst_type <= `IType;
`BRANCH : inst_type <= `BType;
`LOAD : inst_type <= `IType;
`STORE : inst_type <= `SType;
`EXE_IMM : inst_type <= `IType;
`EXE : inst_type <= `RType;
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
pc_o <= `NopInst;
aluop_o <= `NOP;
alufunct3_o <= `NOP_FUNCT3;
alufunct7_o <= `NOP_FUNCT7;
imm <= `ZeroWord;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
end
else begin
pc_o <= pc_i;
aluop_o <= op;
alufunct3_o <= `NOP_FUNCT3;
alufunct7_o <= `NOP_FUNCT7;
imm <= `ZeroWord;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
case(inst_type)
`RType : begin
wreg_o <= `WriteEnable;
alufunct3_o <= inst_i[14:12];
alufunct7_o <= inst_i[31:25];
wd_o <= inst_i[11:7];
end
`IType : begin
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wreg_o <= `WriteEnable;
alufunct3_o <= inst_i[14:12];
alufunct7_o <= inst_i[31:25];
wd_o <= inst_i[11:7];
end
`SType : begin
imm <= {{21{inst_i[31]}}, inst_i[30:25], inst_i[11:8], inst_i[7]};
wreg_o <= `WriteDisable;
alufunct3_o <= inst_i[14:12];
end
`BType : begin
imm <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
wreg_o <= `WriteDisable;
alufunct3_o <= inst_i[14:12];
end
`UType : begin
imm <= {inst_i[31:12], {12{1'b0}}};
wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
end
`JType : begin
imm <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0};
wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
end
default : begin
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= `NopRegAddr;
reg2_addr_o <= `NopRegAddr;
end
else begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= `NopRegAddr;
reg2_addr_o <= `NopRegAddr;
case(inst_type)
`RType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`IType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= inst_i[19:15];
end
`SType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`BType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`UType : begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
end
`JType : begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end
else if(reg1_read_o == `ReadEnable) begin
reg1_o <= reg1_data_i;
end
else if(reg1_read_o == `ReadDisable) begin
reg1_o <= imm;
end
else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end
else if(reg2_read_o == `ReadEnable) begin
reg2_o <= reg2_data_i;
end
else if(reg2_read_o == `ReadDisable) begin
reg2_o <= imm;
end
else begin
reg2_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
imm_o <= `ZeroWord;
end
else begin
imm_o <= imm;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
stall_req <= `Continue;
end
else begin
stall_req <= `Continue;
case(inst_type)
`RType : stall_req <= !(reg1_suc & reg2_suc);
`IType : stall_req <= !reg1_suc;
`SType : stall_req <= !(reg1_suc & reg2_suc);
`BType : stall_req <= !(reg1_suc & reg2_suc);
`UType : stall_req <= `Continue;
`JType : stall_req <= `Continue;
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
jump_o <= `Stay;
jpc_o <= `NopInst;
end
else begin
jump_o <= `Stay;
jpc_o <= `NopInst;
case (op)
`JAL : begin
jump_o <= `Jump;
jpc_o <= reg1_o + pc_i;
end
`JALR : begin
jump_o <= `Jump;
jpc_o <= {reg1_o[31:1] + reg2_o[31:1] + {{30{1'b0}}, reg1_o[0] & reg2_o[0]}, 1'b0};
end
`BRANCH : begin
case(alufunct3_o)
`BEQ : begin
if(reg1_o == reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BNE : begin
if(reg1_o != reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
end
`BLT : begin
if($signed(reg1_o) < $signed(reg2_o)) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BGE : begin
if($signed(reg1_o) >= $signed(reg2_o)) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BLTU : begin
if(reg1_o < reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BGEU : begin
if(reg1_o >= reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
endcase
end
endcase
end
end
endmodule | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire reg1_suc,
input wire[`RegBus] reg1_data_i,
input wire reg2_suc,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`InstAddrBus] pc_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluFunct3Bus] alufunct3_o,
output reg[`AluFunct7Bus] alufunct7_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegBus] imm_o,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg stall_req,
output reg jump_o,
output reg[`InstAddrBus] jpc_o
); |
wire[6:0] op = inst_i[6:0];
reg[2:0] inst_type;
reg[`RegBus] imm;
always @ (*) begin
if(rst == `RstEnable) begin
inst_type <= `IType;
end
else begin
inst_type <= `IType;
case(op)
`LUI : inst_type <= `UType;
`AUIPC : inst_type <= `UType;
`JAL : inst_type <= `JType;
`JALR : inst_type <= `IType;
`BRANCH : inst_type <= `BType;
`LOAD : inst_type <= `IType;
`STORE : inst_type <= `SType;
`EXE_IMM : inst_type <= `IType;
`EXE : inst_type <= `RType;
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
pc_o <= `NopInst;
aluop_o <= `NOP;
alufunct3_o <= `NOP_FUNCT3;
alufunct7_o <= `NOP_FUNCT7;
imm <= `ZeroWord;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
end
else begin
pc_o <= pc_i;
aluop_o <= op;
alufunct3_o <= `NOP_FUNCT3;
alufunct7_o <= `NOP_FUNCT7;
imm <= `ZeroWord;
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
case(inst_type)
`RType : begin
wreg_o <= `WriteEnable;
alufunct3_o <= inst_i[14:12];
alufunct7_o <= inst_i[31:25];
wd_o <= inst_i[11:7];
end
`IType : begin
imm <= {{21{inst_i[31]}}, inst_i[30:20]};
wreg_o <= `WriteEnable;
alufunct3_o <= inst_i[14:12];
alufunct7_o <= inst_i[31:25];
wd_o <= inst_i[11:7];
end
`SType : begin
imm <= {{21{inst_i[31]}}, inst_i[30:25], inst_i[11:8], inst_i[7]};
wreg_o <= `WriteDisable;
alufunct3_o <= inst_i[14:12];
end
`BType : begin
imm <= {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
wreg_o <= `WriteDisable;
alufunct3_o <= inst_i[14:12];
end
`UType : begin
imm <= {inst_i[31:12], {12{1'b0}}};
wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
end
`JType : begin
imm <= {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:25], inst_i[24:21], 1'b0};
wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
end
default : begin
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= `NopRegAddr;
reg2_addr_o <= `NopRegAddr;
end
else begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= `NopRegAddr;
reg2_addr_o <= `NopRegAddr;
case(inst_type)
`RType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`IType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadDisable;
reg1_addr_o <= inst_i[19:15];
end
`SType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`BType : begin
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
end
`UType : begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
end
`JType : begin
reg1_read_o <= `ReadDisable;
reg2_read_o <= `ReadDisable;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end
else if(reg1_read_o == `ReadEnable) begin
reg1_o <= reg1_data_i;
end
else if(reg1_read_o == `ReadDisable) begin
reg1_o <= imm;
end
else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end
else if(reg2_read_o == `ReadEnable) begin
reg2_o <= reg2_data_i;
end
else if(reg2_read_o == `ReadDisable) begin
reg2_o <= imm;
end
else begin
reg2_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
imm_o <= `ZeroWord;
end
else begin
imm_o <= imm;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
stall_req <= `Continue;
end
else begin
stall_req <= `Continue;
case(inst_type)
`RType : stall_req <= !(reg1_suc & reg2_suc);
`IType : stall_req <= !reg1_suc;
`SType : stall_req <= !(reg1_suc & reg2_suc);
`BType : stall_req <= !(reg1_suc & reg2_suc);
`UType : stall_req <= `Continue;
`JType : stall_req <= `Continue;
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
jump_o <= `Stay;
jpc_o <= `NopInst;
end
else begin
jump_o <= `Stay;
jpc_o <= `NopInst;
case (op)
`JAL : begin
jump_o <= `Jump;
jpc_o <= reg1_o + pc_i;
end
`JALR : begin
jump_o <= `Jump;
jpc_o <= {reg1_o[31:1] + reg2_o[31:1] + {{30{1'b0}}, reg1_o[0] & reg2_o[0]}, 1'b0};
end
`BRANCH : begin
case(alufunct3_o)
`BEQ : begin
if(reg1_o == reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BNE : begin
if(reg1_o != reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
end
`BLT : begin
if($signed(reg1_o) < $signed(reg2_o)) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BGE : begin
if($signed(reg1_o) >= $signed(reg2_o)) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BLTU : begin
if(reg1_o < reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
`BGEU : begin
if(reg1_o >= reg2_o) begin
jump_o <= `Jump;
jpc_o <= imm_o + pc_i;
end
else begin
jpc_o <= pc_i + 4;
end
end
endcase
end
endcase
end
end
endmodule | 0 |
5,594 | data/full_repos/permissive/114459345/srcCache/id_ex.v | 114,459,345 | id_ex.v | v | 78 | 42 | [] | [] | [] | [(219, 293)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:10: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] id_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] id_pc,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:11: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] id_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:12: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] id_alufunct3,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:13: Define or directive not defined: \'`AluFunct7Bus\'\n input wire[`AluFunct7Bus] id_alufunct7,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_reg1,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_reg2,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] id_imm,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] id_wd,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:18: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] id_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:21: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] ex_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:22: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] ex_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:23: Define or directive not defined: \'`AluFunct3Bus\'\n output reg[`AluFunct3Bus] ex_alufunct3,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:24: Define or directive not defined: \'`AluFunct7Bus\'\n output reg[`AluFunct7Bus] ex_alufunct7,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:25: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_reg1,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_reg2,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:27: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] ex_imm,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] ex_wd,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:29: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] ex_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:32: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth] stall\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:37: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:38: Define or directive not defined: \'`NopInst\'\n ex_pc <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:39: Define or directive not defined: \'`NOP\'\n ex_aluop <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:40: Define or directive not defined: \'`NOP_FUNCT3\'\n ex_alufunct3 <= `NOP_FUNCT3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:41: Define or directive not defined: \'`NOP_FUNCT7\'\n ex_alufunct7 <= `NOP_FUNCT7;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:42: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:43: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:44: Define or directive not defined: \'`ZeroWord\'\n ex_imm <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:45: Define or directive not defined: \'`NopRegAddr\'\n ex_wd <= `NopRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:46: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:48: Define or directive not defined: \'`EX_BIT\'\n else if(stall[`EX_BIT] == `Stop) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:48: Define or directive not defined: \'`Stop\'\n else if(stall[`EX_BIT] == `Stop) begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:50: Define or directive not defined: \'`MEM_BIT\'\n if(stall[`MEM_BIT] == `Continue) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:50: Define or directive not defined: \'`Continue\'\n if(stall[`MEM_BIT] == `Continue) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:51: Define or directive not defined: \'`NopInst\'\n ex_pc <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:52: Define or directive not defined: \'`NOP\'\n ex_aluop <= `NOP;\n ^~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:53: Define or directive not defined: \'`NOP_FUNCT3\'\n ex_alufunct3 <= `NOP_FUNCT3;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:54: Define or directive not defined: \'`NOP_FUNCT7\'\n ex_alufunct7 <= `NOP_FUNCT7;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:55: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:56: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:57: Define or directive not defined: \'`ZeroWord\'\n ex_imm <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:58: Define or directive not defined: \'`NopRegAddr\'\n ex_wd <= `NopRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/id_ex.v:59: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable; \n ^~~~~~~~~~~~~\n%Error: Exiting due to 44 error(s)\n' | 6,312 | module | module id_ex(
input wire clk,
input wire rst,
input wire[`InstAddrBus] id_pc,
input wire[`AluOpBus] id_aluop,
input wire[`AluFunct3Bus] id_alufunct3,
input wire[`AluFunct7Bus] id_alufunct7,
input wire[`RegBus] id_reg1,
input wire[`RegBus] id_reg2,
input wire[`RegBus] id_imm,
input wire id_wreg,
input wire[`RegAddrBus] id_wd,
output reg[`InstAddrBus] ex_pc,
output reg[`AluOpBus] ex_aluop,
output reg[`AluFunct3Bus] ex_alufunct3,
output reg[`AluFunct7Bus] ex_alufunct7,
output reg[`RegBus] ex_reg1,
output reg[`RegBus] ex_reg2,
output reg[`RegBus] ex_imm,
output reg ex_wreg,
output reg[`RegAddrBus] ex_wd,
input wire[`CtrlWidth] stall
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ex_pc <= `NopInst;
ex_aluop <= `NOP;
ex_alufunct3 <= `NOP_FUNCT3;
ex_alufunct7 <= `NOP_FUNCT7;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_imm <= `ZeroWord;
ex_wd <= `NopRegAddr;
ex_wreg <= `WriteDisable;
end
else if(stall[`EX_BIT] == `Stop) begin
if(stall[`MEM_BIT] == `Continue) begin
ex_pc <= `NopInst;
ex_aluop <= `NOP;
ex_alufunct3 <= `NOP_FUNCT3;
ex_alufunct7 <= `NOP_FUNCT7;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_imm <= `ZeroWord;
ex_wd <= `NopRegAddr;
ex_wreg <= `WriteDisable;
end
else begin
end
end
else begin
ex_pc <= id_pc;
ex_aluop <= id_aluop;
ex_alufunct3 <= id_alufunct3;
ex_alufunct7 <= id_alufunct7;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_imm <= id_imm;
ex_wreg <= id_wreg;
ex_wd <= id_wd;
end
end
endmodule | module id_ex(
input wire clk,
input wire rst,
input wire[`InstAddrBus] id_pc,
input wire[`AluOpBus] id_aluop,
input wire[`AluFunct3Bus] id_alufunct3,
input wire[`AluFunct7Bus] id_alufunct7,
input wire[`RegBus] id_reg1,
input wire[`RegBus] id_reg2,
input wire[`RegBus] id_imm,
input wire id_wreg,
input wire[`RegAddrBus] id_wd,
output reg[`InstAddrBus] ex_pc,
output reg[`AluOpBus] ex_aluop,
output reg[`AluFunct3Bus] ex_alufunct3,
output reg[`AluFunct7Bus] ex_alufunct7,
output reg[`RegBus] ex_reg1,
output reg[`RegBus] ex_reg2,
output reg[`RegBus] ex_imm,
output reg ex_wreg,
output reg[`RegAddrBus] ex_wd,
input wire[`CtrlWidth] stall
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ex_pc <= `NopInst;
ex_aluop <= `NOP;
ex_alufunct3 <= `NOP_FUNCT3;
ex_alufunct7 <= `NOP_FUNCT7;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_imm <= `ZeroWord;
ex_wd <= `NopRegAddr;
ex_wreg <= `WriteDisable;
end
else if(stall[`EX_BIT] == `Stop) begin
if(stall[`MEM_BIT] == `Continue) begin
ex_pc <= `NopInst;
ex_aluop <= `NOP;
ex_alufunct3 <= `NOP_FUNCT3;
ex_alufunct7 <= `NOP_FUNCT7;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_imm <= `ZeroWord;
ex_wd <= `NopRegAddr;
ex_wreg <= `WriteDisable;
end
else begin
end
end
else begin
ex_pc <= id_pc;
ex_aluop <= id_aluop;
ex_alufunct3 <= id_alufunct3;
ex_alufunct7 <= id_alufunct7;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_imm <= id_imm;
ex_wreg <= id_wreg;
ex_wd <= id_wd;
end
end
endmodule | 0 |
5,595 | data/full_repos/permissive/114459345/srcCache/if_id.v | 114,459,345 | if_id.v | v | 50 | 57 | [] | [] | [] | [(219, 265)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:10: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth] stall,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`CtrlWidth] stall,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`InstAddrBus] if_pc,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:16: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] if_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:17: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] if_inst,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:20: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] id_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:21: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] id_inst\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:27: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:28: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:29: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:31: Define or directive not defined: \'`Jump\'\n else if(jumpout == `Jump) begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:32: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:33: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:35: Define or directive not defined: \'`ID_BIT\'\n else if(stall[`ID_BIT] == `Stop) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:35: Define or directive not defined: \'`Stop\'\n else if(stall[`ID_BIT] == `Stop) begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:36: Define or directive not defined: \'`EX_BIT\'\n if(stall[`EX_BIT] == `Continue) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:36: Define or directive not defined: \'`Continue\'\n if(stall[`EX_BIT] == `Continue) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:37: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/if_id.v:38: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord; \n ^~~~~~~~~\n%Error: Exiting due to 20 error(s)\n' | 6,313 | module | module if_id(
input wire clk,
input wire rst,
input wire[`CtrlWidth] stall,
input wire jumpout,
input wire[`InstAddrBus] if_pc,
input wire[`InstBus] if_inst,
output reg[`InstAddrBus] id_pc,
output reg[`InstBus] id_inst
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else if(jumpout == `Jump) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else if(stall[`ID_BIT] == `Stop) begin
if(stall[`EX_BIT] == `Continue) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else begin
end
end
else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
endmodule | module if_id(
input wire clk,
input wire rst,
input wire[`CtrlWidth] stall,
input wire jumpout,
input wire[`InstAddrBus] if_pc,
input wire[`InstBus] if_inst,
output reg[`InstAddrBus] id_pc,
output reg[`InstBus] id_inst
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else if(jumpout == `Jump) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else if(stall[`ID_BIT] == `Stop) begin
if(stall[`EX_BIT] == `Continue) begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end
else begin
end
end
else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
endmodule | 0 |
5,596 | data/full_repos/permissive/114459345/srcCache/inst_rom.v | 114,459,345 | inst_rom.v | v | 33 | 122 | [] | [] | [] | [(219, 248)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:7: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:10: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:14: Define or directive not defined: \'`InstBus\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:14: Define or directive not defined: \'`InstMemNum\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:25: Define or directive not defined: \'`ChipDisable\'\n if(ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/inst_rom.v:26: Define or directive not defined: \'`NopInst\'\n inst <= `NopInst;\n ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 6,314 | module | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
);
reg[`InstBus] inst_mem[0:`InstMemNum-1];
initial begin
$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", inst_mem);
end
always @ (*) begin
if(ce == `ChipDisable) begin
inst <= `NopInst;
end
else begin
inst <= {inst_mem[addr >> 2][7:0], inst_mem[addr >> 2][15:8], inst_mem[addr >> 2][23:16], inst_mem[addr >> 2][31:24]};
end
end
endmodule | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
); |
reg[`InstBus] inst_mem[0:`InstMemNum-1];
initial begin
$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", inst_mem);
end
always @ (*) begin
if(ce == `ChipDisable) begin
inst <= `NopInst;
end
else begin
inst <= {inst_mem[addr >> 2][7:0], inst_mem[addr >> 2][15:8], inst_mem[addr >> 2][23:16], inst_mem[addr >> 2][31:24]};
end
end
endmodule | 0 |
5,597 | data/full_repos/permissive/114459345/srcCache/mem.v | 114,459,345 | mem.v | v | 179 | 78 | [] | [] | [] | [(219, 394)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/mem.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:9: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus] aluop_i,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:10: Define or directive not defined: \'`AluFunct3Bus\'\n input wire[`AluFunct3Bus] alufunct3_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`MemAddrBus] maddr_i, \n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:12: Define or directive not defined: \'`MemAddrBus\'\n input wire[`MemAddrBus] maddr_i, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] wd_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:14: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata_i, \n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:19: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`ValidBitBus] rvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:19: Define or directive not defined: \'`ValidBitBus\'\n output reg[`ValidBitBus] rvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:20: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] raddr_m,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:21: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] rdata_m, \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`ValidBitBus] wvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:23: Define or directive not defined: \'`ValidBitBus\'\n output reg[`ValidBitBus] wvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:24: Define or directive not defined: \'`MemAddrBus\'\n output reg[`MemAddrBus] waddr_m,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:25: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] wdata_m, \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:29: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:30: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_f,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:34: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_f,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:35: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_f\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:39: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] mout;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] mout;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:43: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:44: Define or directive not defined: \'`ReadDisable\'\n re_m <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:45: Define or directive not defined: \'`ZeroValidBit\'\n rvalid_bit <= `ZeroValidBit;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:46: Define or directive not defined: \'`NopMem\'\n raddr_m <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n we_m <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:48: Define or directive not defined: \'`ZeroValidBit\'\n wvalid_bit <= `ZeroValidBit;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:49: Define or directive not defined: \'`NopMem\'\n waddr_m <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:50: Define or directive not defined: \'`ZeroWord\'\n wdata_m <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:53: Define or directive not defined: \'`ReadDisable\'\n re_m <= `ReadDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:54: Define or directive not defined: \'`ZeroValidBit\'\n rvalid_bit <= `ZeroValidBit;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:55: Define or directive not defined: \'`NopMem\'\n raddr_m <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:56: Define or directive not defined: \'`WriteDisable\'\n we_m <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:57: Define or directive not defined: \'`ZeroValidBit\'\n wvalid_bit <= `ZeroValidBit;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:58: Define or directive not defined: \'`NopMem\'\n waddr_m <= `NopMem;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:59: Define or directive not defined: \'`ZeroWord\'\n wdata_m <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:61: Define or directive not defined: \'`MemEnable\'\n if(me_i == `MemEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:63: Define or directive not defined: \'`LOAD\'\n `LOAD : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:64: Define or directive not defined: \'`ReadEnable\'\n re_m <= `ReadEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:67: Define or directive not defined: \'`LB\'\n `LB : begin\n ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:68: Define or directive not defined: \'`Byte\'\n rvalid_bit <= `Byte;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:70: Define or directive not defined: \'`LH\'\n `LH : begin\n ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:71: Define or directive not defined: \'`Half\'\n rvalid_bit <= `Half; \n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:73: Define or directive not defined: \'`LW\'\n `LW : begin\n ^~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:74: Define or directive not defined: \'`Word\'\n rvalid_bit <= `Word;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem.v:76: Define or directive not defined: \'`LBU\'\n `LBU : begin\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,315 | module | module mem(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluFunct3Bus] alufunct3_i,
input wire me_i,
input wire[`MemAddrBus] maddr_i,
input wire wreg_i,
input wire[`RegAddrBus] wd_i,
input wire[`RegBus] wdata_i,
output reg re_m,
output reg[`ValidBitBus] rvalid_bit,
output reg[`MemAddrBus] raddr_m,
input wire[`DataBus] rdata_m,
output reg we_m,
output reg[`ValidBitBus] wvalid_bit,
output reg[`MemAddrBus] waddr_m,
output reg[`DataBus] wdata_m,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg[`RegBus] wdata_o,
output reg wreg_f,
output reg[`RegAddrBus] wd_f,
output reg[`RegBus] wdata_f
);
reg[`RegBus] mout;
always @ (*) begin
if(rst == `RstEnable) begin
re_m <= `ReadDisable;
rvalid_bit <= `ZeroValidBit;
raddr_m <= `NopMem;
we_m <= `WriteDisable;
wvalid_bit <= `ZeroValidBit;
waddr_m <= `NopMem;
wdata_m <= `ZeroWord;
end
else begin
re_m <= `ReadDisable;
rvalid_bit <= `ZeroValidBit;
raddr_m <= `NopMem;
we_m <= `WriteDisable;
wvalid_bit <= `ZeroValidBit;
waddr_m <= `NopMem;
wdata_m <= `ZeroWord;
if(me_i == `MemEnable) begin
case(aluop_i)
`LOAD : begin
re_m <= `ReadEnable;
raddr_m <= maddr_i;
case(alufunct3_i)
`LB : begin
rvalid_bit <= `Byte;
end
`LH : begin
rvalid_bit <= `Half;
end
`LW : begin
rvalid_bit <= `Word;
end
`LBU : begin
rvalid_bit <= `Byte;
end
`LHU : begin
rvalid_bit <= `Half;
end
endcase
end
`STORE : begin
case(alufunct3_i)
`SB : begin
we_m <= `WriteEnable;
wvalid_bit <= `Byte;
waddr_m <= maddr_i;
wdata_m <= {{24{1'b0}}, wdata_i[7:0]};
end
`SH : begin
we_m <= `WriteEnable;
wvalid_bit <= `Half;
waddr_m <= maddr_i;
wdata_m <= {{16{1'b0}}, wdata_i[15:0]};
end
`SW : begin
we_m <= `WriteEnable;
wvalid_bit <= `Word;
waddr_m <= maddr_i;
wdata_m <= wdata_i[31:0];
end
endcase
end
default : begin
end
endcase
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
mout <= `ZeroWord;
end
else begin
mout <= `ZeroWord;
if(aluop_i == `LOAD) begin
case(alufunct3_i)
`LB : begin
mout <= {{24{rdata_m[7]}},rdata_m[7:0]};
end
`LH : begin
mout <= {{16{rdata_m[15]}},rdata_m[15:0]};
end
`LW : begin
mout <= rdata_m;
end
`LBU : begin
mout <= {{24{1'b0}},rdata_m[7:0]};
end
`LHU : begin
mout <= {{16{1'b0}},rdata_m[15:0]};
end
default : begin
end
endcase
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
wdata_o <= `ZeroWord;
end
else begin
wreg_o <= wreg_i;
wd_o <= wd_i;
if(aluop_i == `LOAD) begin
wdata_o <= mout;
end
else begin
wdata_o <= wdata_i;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_f <= `WriteDisable;
wd_f <= `NopRegAddr;
wdata_f <= `ZeroWord;
end
else begin
wreg_f <= wreg_o;
wd_f <= wd_o;
wdata_f <= wdata_o;
end
end
endmodule | module mem(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluFunct3Bus] alufunct3_i,
input wire me_i,
input wire[`MemAddrBus] maddr_i,
input wire wreg_i,
input wire[`RegAddrBus] wd_i,
input wire[`RegBus] wdata_i,
output reg re_m,
output reg[`ValidBitBus] rvalid_bit,
output reg[`MemAddrBus] raddr_m,
input wire[`DataBus] rdata_m,
output reg we_m,
output reg[`ValidBitBus] wvalid_bit,
output reg[`MemAddrBus] waddr_m,
output reg[`DataBus] wdata_m,
output reg wreg_o,
output reg[`RegAddrBus] wd_o,
output reg[`RegBus] wdata_o,
output reg wreg_f,
output reg[`RegAddrBus] wd_f,
output reg[`RegBus] wdata_f
); |
reg[`RegBus] mout;
always @ (*) begin
if(rst == `RstEnable) begin
re_m <= `ReadDisable;
rvalid_bit <= `ZeroValidBit;
raddr_m <= `NopMem;
we_m <= `WriteDisable;
wvalid_bit <= `ZeroValidBit;
waddr_m <= `NopMem;
wdata_m <= `ZeroWord;
end
else begin
re_m <= `ReadDisable;
rvalid_bit <= `ZeroValidBit;
raddr_m <= `NopMem;
we_m <= `WriteDisable;
wvalid_bit <= `ZeroValidBit;
waddr_m <= `NopMem;
wdata_m <= `ZeroWord;
if(me_i == `MemEnable) begin
case(aluop_i)
`LOAD : begin
re_m <= `ReadEnable;
raddr_m <= maddr_i;
case(alufunct3_i)
`LB : begin
rvalid_bit <= `Byte;
end
`LH : begin
rvalid_bit <= `Half;
end
`LW : begin
rvalid_bit <= `Word;
end
`LBU : begin
rvalid_bit <= `Byte;
end
`LHU : begin
rvalid_bit <= `Half;
end
endcase
end
`STORE : begin
case(alufunct3_i)
`SB : begin
we_m <= `WriteEnable;
wvalid_bit <= `Byte;
waddr_m <= maddr_i;
wdata_m <= {{24{1'b0}}, wdata_i[7:0]};
end
`SH : begin
we_m <= `WriteEnable;
wvalid_bit <= `Half;
waddr_m <= maddr_i;
wdata_m <= {{16{1'b0}}, wdata_i[15:0]};
end
`SW : begin
we_m <= `WriteEnable;
wvalid_bit <= `Word;
waddr_m <= maddr_i;
wdata_m <= wdata_i[31:0];
end
endcase
end
default : begin
end
endcase
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
mout <= `ZeroWord;
end
else begin
mout <= `ZeroWord;
if(aluop_i == `LOAD) begin
case(alufunct3_i)
`LB : begin
mout <= {{24{rdata_m[7]}},rdata_m[7:0]};
end
`LH : begin
mout <= {{16{rdata_m[15]}},rdata_m[15:0]};
end
`LW : begin
mout <= rdata_m;
end
`LBU : begin
mout <= {{24{1'b0}},rdata_m[7:0]};
end
`LHU : begin
mout <= {{16{1'b0}},rdata_m[15:0]};
end
default : begin
end
endcase
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_o <= `WriteDisable;
wd_o <= `NopRegAddr;
wdata_o <= `ZeroWord;
end
else begin
wreg_o <= wreg_i;
wd_o <= wd_i;
if(aluop_i == `LOAD) begin
wdata_o <= mout;
end
else begin
wdata_o <= wdata_i;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
wreg_f <= `WriteDisable;
wd_f <= `NopRegAddr;
wdata_f <= `ZeroWord;
end
else begin
wreg_f <= wreg_o;
wd_f <= wd_o;
wdata_f <= wdata_o;
end
end
endmodule | 0 |
5,598 | data/full_repos/permissive/114459345/srcCache/mem_wb.v | 114,459,345 | mem_wb.v | v | 33 | 33 | [] | [] | [] | [(219, 248)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] mem_wd,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_wdata,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:14: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wb_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:16: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wb_wdata\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:16: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wb_wdata\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:21: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:22: Define or directive not defined: \'`NopRegAddr\'\n wb_wd <= `NopRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:23: Define or directive not defined: \'`WriteDisable\'\n wb_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/mem_wb.v:24: Define or directive not defined: \'`ZeroWord\'\n wb_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 12 error(s)\n' | 6,316 | module | module mem_wb(
input wire clk,
input wire rst,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NopRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
end
else begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
end
end
endmodule | module mem_wb(
input wire clk,
input wire rst,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NopRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
end
else begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
end
end
endmodule | 0 |
5,599 | data/full_repos/permissive/114459345/srcCache/pc_reg.v | 114,459,345 | pc_reg.v | v | 50 | 47 | [] | [] | [] | [(219, 265)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:10: Define or directive not defined: \'`CtrlWidth\'\n input wire[`CtrlWidth] stall,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`CtrlWidth] stall,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`InstAddrBus] pc_i,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:14: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:17: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus] pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:25: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:26: Define or directive not defined: \'`ChipDisable\'\n ce <= `ChipDisable; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:29: Define or directive not defined: \'`ChipEnable\'\n ce <= `ChipEnable; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:36: Define or directive not defined: \'`ChipDisable\'\n if(ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:37: Define or directive not defined: \'`ZeroWord\'\n pc <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:39: Define or directive not defined: \'`Jump\'\n else if(jumpout == `Jump) begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:42: Define or directive not defined: \'`PC_BIT\'\n else if(stall[`PC_BIT] == `Stop) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/pc_reg.v:42: Define or directive not defined: \'`Stop\'\n else if(stall[`PC_BIT] == `Stop) begin\n ^~~~~\n%Error: Exiting due to 14 error(s)\n' | 6,317 | module | module pc_reg(
input wire clk,
input wire rst,
input wire[`CtrlWidth] stall,
input wire jumpout,
input wire[`InstAddrBus] pc_i,
output reg[`InstAddrBus] pc,
output reg ce
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ce <= `ChipDisable;
end
else begin
ce <= `ChipEnable;
end
end
always @ (posedge clk) begin
if(ce == `ChipDisable) begin
pc <= `ZeroWord;
end
else if(jumpout == `Jump) begin
pc <= pc_i;
end
else if(stall[`PC_BIT] == `Stop) begin
end
else begin
pc <= pc + 4'h4;
end
end
endmodule | module pc_reg(
input wire clk,
input wire rst,
input wire[`CtrlWidth] stall,
input wire jumpout,
input wire[`InstAddrBus] pc_i,
output reg[`InstAddrBus] pc,
output reg ce
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
ce <= `ChipDisable;
end
else begin
ce <= `ChipEnable;
end
end
always @ (posedge clk) begin
if(ce == `ChipDisable) begin
pc <= `ZeroWord;
end
else if(jumpout == `Jump) begin
pc <= pc_i;
end
else if(stall[`PC_BIT] == `Stop) begin
end
else begin
pc <= pc + 4'h4;
end
end
endmodule | 0 |
5,600 | data/full_repos/permissive/114459345/srcCache/regfile.v | 114,459,345 | regfile.v | v | 132 | 91 | [] | [] | [] | [(219, 347)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:11: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] waddr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] waddr,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:12: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] ex_waddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:16: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_waddr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] mem_waddr,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:21: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_waddr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:22: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] raddr1,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:26: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] raddr1,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:28: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] rdata1,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:28: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] rdata1,\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegAddrBus] raddr2,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:32: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] raddr2,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] rdata2\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:34: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] rdata2\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] regs[0:`RegNum-1];\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] regs[0:`RegNum-1];\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:38: Define or directive not defined: \'`RegNum\'\n reg[`RegBus] regs[0:`RegNum-1];\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:41: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:49: Define or directive not defined: \'`RstDisable\'\n if(rst == `RstDisable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:50: Define or directive not defined: \'`WriteEnable\'\n if(we == `WriteEnable && (waddr != `RegNumLog2\'h0)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:50: Define or directive not defined: \'`RegNumLog2\'\n if(we == `WriteEnable && (waddr != `RegNumLog2\'h0)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:58: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:59: Define or directive not defined: \'`ReadFailed\'\n rsuc1 <= `ReadFailed;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:60: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:62: Define or directive not defined: \'`RegNumLog2\'\n else if(raddr1 == `RegNumLog2\'h0) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:63: Define or directive not defined: \'`ReadSucceed\'\n rsuc1 <= `ReadSucceed;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:64: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:66: Define or directive not defined: \'`ReadEnable\'\n else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:67: Define or directive not defined: \'`WriteEnable\'\n if(ex_we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:68: Define or directive not defined: \'`ReadSucceed\'\n rsuc1 <= `ReadSucceed;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:72: Define or directive not defined: \'`ReadFailed\'\n rsuc1 <= `ReadFailed;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:73: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord; \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:76: Define or directive not defined: \'`WriteEnable\'\n else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:76: Define or directive not defined: \'`ReadEnable\'\n else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:77: Define or directive not defined: \'`ReadSucceed\'\n rsuc1 <= `ReadSucceed;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:80: Define or directive not defined: \'`WriteEnable\'\n else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:80: Define or directive not defined: \'`ReadEnable\'\n else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:81: Define or directive not defined: \'`ReadSucceed\'\n rsuc1 <= `ReadSucceed;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:84: Define or directive not defined: \'`ReadEnable\'\n else if(re1 == `ReadEnable) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:85: Define or directive not defined: \'`ReadSucceed\'\n rsuc1 <= `ReadSucceed;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:89: Define or directive not defined: \'`ReadFailed\'\n rsuc1 <= `ReadFailed;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:90: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:96: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:97: Define or directive not defined: \'`ReadFailed\'\n rsuc2 <= `ReadFailed;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:98: Define or directive not defined: \'`ZeroWord\'\n rdata2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/regfile.v:100: Define or directive not defined: \'`RegNumLog2\'\n else if(raddr2 == `RegNumLog2\'h0) begin\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,318 | module | module regfile(
input wire clk,
input wire rst,
input wire we,
input wire[`RegAddrBus] waddr,
input wire[`RegBus] wdata,
input wire ex_we,
input wire[`RegAddrBus] ex_waddr,
input wire[`RegBus] ex_wdata,
input wire mem_we,
input wire[`RegAddrBus] mem_waddr,
input wire[`RegBus] mem_wdata,
input wire re1,
input wire[`RegAddrBus] raddr1,
output reg rsuc1,
output reg[`RegBus] rdata1,
input wire re2,
input wire[`RegAddrBus] raddr2,
output reg rsuc2,
output reg[`RegBus] rdata2
);
reg[`RegBus] regs[0:`RegNum-1];
integer i;
initial begin
for(i = 0; i < 32; i = i + 1) begin
regs[i] = 0;
end
end
always @ (posedge clk) begin
if(rst == `RstDisable) begin
if(we == `WriteEnable && (waddr != `RegNumLog2'h0)) begin
regs[waddr] <= wdata;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
else if(raddr1 == `RegNumLog2'h0) begin
rsuc1 <= `ReadSucceed;
rdata1 <= `ZeroWord;
end
else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin
if(ex_we == `WriteEnable) begin
rsuc1 <= `ReadSucceed;
rdata1 <= ex_wdata;
end
else begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
end
else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin
rsuc1 <= `ReadSucceed;
rdata1 <= mem_wdata;
end
else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin
rsuc1 <= `ReadSucceed;
rdata1 <= wdata;
end
else if(re1 == `ReadEnable) begin
rsuc1 <= `ReadSucceed;
rdata1 <= regs[raddr1];
end
else begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
else if(raddr2 == `RegNumLog2'h0) begin
rsuc2 <= `ReadSucceed;
rdata2 <= `ZeroWord;
end
else if((raddr2 == ex_waddr) && (ex_we == `WriteEnable) && (re2 == `ReadEnable)) begin
if(ex_we == `WriteEnable) begin
rsuc2 <= `ReadSucceed;
rdata2 <= ex_wdata;
end
else begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
end
else if((raddr2 == mem_waddr) && (mem_we == `WriteEnable) && (re2 == `ReadEnable)) begin
rsuc2 <= `ReadSucceed;
rdata2 <= mem_wdata;
end
else if((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin
rsuc2 <= `ReadSucceed;
rdata2 <= wdata;
end
else if(re2 == `ReadEnable) begin
rsuc2 <= `ReadSucceed;
rdata2 <= regs[raddr2];
end
else begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
end
endmodule | module regfile(
input wire clk,
input wire rst,
input wire we,
input wire[`RegAddrBus] waddr,
input wire[`RegBus] wdata,
input wire ex_we,
input wire[`RegAddrBus] ex_waddr,
input wire[`RegBus] ex_wdata,
input wire mem_we,
input wire[`RegAddrBus] mem_waddr,
input wire[`RegBus] mem_wdata,
input wire re1,
input wire[`RegAddrBus] raddr1,
output reg rsuc1,
output reg[`RegBus] rdata1,
input wire re2,
input wire[`RegAddrBus] raddr2,
output reg rsuc2,
output reg[`RegBus] rdata2
); |
reg[`RegBus] regs[0:`RegNum-1];
integer i;
initial begin
for(i = 0; i < 32; i = i + 1) begin
regs[i] = 0;
end
end
always @ (posedge clk) begin
if(rst == `RstDisable) begin
if(we == `WriteEnable && (waddr != `RegNumLog2'h0)) begin
regs[waddr] <= wdata;
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
else if(raddr1 == `RegNumLog2'h0) begin
rsuc1 <= `ReadSucceed;
rdata1 <= `ZeroWord;
end
else if((raddr1 == ex_waddr) && (re1 == `ReadEnable)) begin
if(ex_we == `WriteEnable) begin
rsuc1 <= `ReadSucceed;
rdata1 <= ex_wdata;
end
else begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
end
else if((raddr1 == mem_waddr) && (mem_we == `WriteEnable) && (re1 == `ReadEnable)) begin
rsuc1 <= `ReadSucceed;
rdata1 <= mem_wdata;
end
else if((raddr1 == waddr) && (we == `WriteEnable) && (re1 == `ReadEnable)) begin
rsuc1 <= `ReadSucceed;
rdata1 <= wdata;
end
else if(re1 == `ReadEnable) begin
rsuc1 <= `ReadSucceed;
rdata1 <= regs[raddr1];
end
else begin
rsuc1 <= `ReadFailed;
rdata1 <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
else if(raddr2 == `RegNumLog2'h0) begin
rsuc2 <= `ReadSucceed;
rdata2 <= `ZeroWord;
end
else if((raddr2 == ex_waddr) && (ex_we == `WriteEnable) && (re2 == `ReadEnable)) begin
if(ex_we == `WriteEnable) begin
rsuc2 <= `ReadSucceed;
rdata2 <= ex_wdata;
end
else begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
end
else if((raddr2 == mem_waddr) && (mem_we == `WriteEnable) && (re2 == `ReadEnable)) begin
rsuc2 <= `ReadSucceed;
rdata2 <= mem_wdata;
end
else if((raddr2 == waddr) && (we == `WriteEnable) && (re2 == `ReadEnable)) begin
rsuc2 <= `ReadSucceed;
rdata2 <= wdata;
end
else if(re2 == `ReadEnable) begin
rsuc2 <= `ReadSucceed;
rdata2 <= regs[raddr2];
end
else begin
rsuc2 <= `ReadFailed;
rdata2 <= `ZeroWord;
end
end
endmodule | 0 |
5,601 | data/full_repos/permissive/114459345/srcCache/riscv.v | 114,459,345 | riscv.v | v | 253 | 94 | [] | [] | [] | [(440, 469), (689, 735), (953, 999), (1217, 1551), (1769, 1843), (2061, 2334), (2552, 2610), (2828, 3003), (3221, 3250), (3468, 3596), (3597, 3836)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:3: Cannot find include file: ctrl.v\n`include "ctrl.v" \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:4: Cannot find include file: pc_reg.v\n`include "pc_reg.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:5: Cannot find include file: if_id.v\n`include "if_id.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:6: Cannot find include file: id.v\n`include "id.v" \n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:7: Cannot find include file: id_ex.v\n`include "id_ex.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:8: Cannot find include file: ex.v\n`include "ex.v" \n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:9: Cannot find include file: ex_mem.v\n`include "ex_mem.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:10: Cannot find include file: mem.v\n`include "mem.v" \n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:11: Cannot find include file: mem_wb.v\n`include "mem_wb.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:12: Cannot find include file: regfile.v\n`include "regfile.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:21: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] rom_data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstBus] rom_data_i,\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:22: Define or directive not defined: \'`InstAddrBus\'\n output wire[`InstAddrBus] rom_addr_o,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_ce_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_re_m,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`ValidBitBus] ram_rvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:32: Define or directive not defined: \'`ValidBitBus\'\n output wire[`ValidBitBus] ram_rvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:33: Define or directive not defined: \'`MemAddrBus\'\n output wire[`MemAddrBus] ram_raddr_m,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:34: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] ram_rdata_m, \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:36: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[`ValidBitBus] ram_wvalid_bit,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:36: Define or directive not defined: \'`ValidBitBus\'\n output wire[`ValidBitBus] ram_wvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:37: Define or directive not defined: \'`MemAddrBus\'\n output wire[`MemAddrBus] ram_waddr_m,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:38: Define or directive not defined: \'`DataBus\'\n output wire[`DataBus] ram_wdata_m \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:41: Define or directive not defined: \'`CtrlWidth\'\n wire[`CtrlWidth] stall;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`CtrlWidth] stall;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:44: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] pc; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] pc; \n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:47: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_i; \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_i; \n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:48: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] id_inst_i; \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] id_inst_i; \n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:52: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg1_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg1_data;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:54: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg2_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:54: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg2_data;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:59: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg1_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:59: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg1_addr;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:60: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg2_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg2_addr;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:66: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_o;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_o;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:67: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] id_aluop_o;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] id_aluop_o;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:68: Define or directive not defined: \'`AluFunct3Bus\'\n wire[`AluFunct3Bus] id_alufunct3_o;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluFunct3Bus] id_alufunct3_o;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:69: Define or directive not defined: \'`AluFunct7Bus\'\n wire[`AluFunct7Bus] id_alufunct7_o;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluFunct7Bus] id_alufunct7_o;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:70: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg1_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg1_o;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,319 | module | module riscv(
input wire clk,
input wire rst,
output wire rom_ce_o,
input wire[`InstBus] rom_data_i,
output wire[`InstAddrBus] rom_addr_o,
input wire req_if,
output wire ram_ce_o,
output wire ram_re_m,
output wire[`ValidBitBus] ram_rvalid_bit,
output wire[`MemAddrBus] ram_raddr_m,
input wire[`DataBus] ram_rdata_m,
output wire ram_we_m,
output wire[`ValidBitBus] ram_wvalid_bit,
output wire[`MemAddrBus] ram_waddr_m,
output wire[`DataBus] ram_wdata_m
);
wire[`CtrlWidth] stall;
wire[`InstAddrBus] pc;
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire reg1_suc;
wire[`RegBus] reg1_data;
wire reg2_suc;
wire[`RegBus] reg2_data;
wire reg1_read;
wire reg2_read;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire req_id;
wire[`InstAddrBus] id_pc_o;
wire[`AluOpBus] id_aluop_o;
wire[`AluFunct3Bus] id_alufunct3_o;
wire[`AluFunct7Bus] id_alufunct7_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire[`RegBus] id_imm_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire jump_o;
wire[`InstAddrBus] jpc_o;
wire[`InstAddrBus] ex_pc_i;
wire[`AluOpBus] ex_aluop_i;
wire[`AluFunct3Bus] ex_alufunct3_i;
wire[`AluFunct7Bus] ex_alufunct7_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire[`RegBus] ex_imm_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire[`AluOpBus] ex_aluop_o;
wire[`AluFunct3Bus] ex_alufunct3_o;
wire ex_me_o;
wire[`MemAddrBus] ex_maddr_o;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire ex_wreg_f;
wire[`RegAddrBus] ex_wd_f;
wire[`RegBus] ex_wdata_f;
wire[`AluOpBus] mem_aluop_i;
wire[`AluFunct3Bus] mem_alufunct3_i;
wire mem_me_i;
wire[`MemAddrBus] mem_maddr_i;
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire mem_wreg_f;
wire[`RegAddrBus] mem_wd_f;
wire[`RegBus] mem_wdata_f;
wire[`RegAddrBus] wb_wd_o;
wire wb_wreg_o;
wire[`RegBus] wb_wdata_o;
ctrl ctrl0(
.rst(rst),
.req_id(req_id), .req_if(req_if),
.stall(stall)
);
pc_reg pc_reg0(
.clk(clk), .rst(rst),
.stall(stall),
.jumpout(jump_o), .pc_i(jpc_o),
.pc(pc), .ce(rom_ce_o)
);
assign rom_addr_o = pc;
if_id if_id0(
.clk(clk), .rst(rst),
.stall(stall), .jumpout(jump_o),
.if_pc(pc), .if_inst(rom_data_i),
.id_pc(id_pc_i), .id_inst(id_inst_i)
);
id id0(
.rst(rst),
.pc_i(id_pc_i), .inst_i(id_inst_i),
.reg1_suc(reg1_suc), .reg2_suc(reg2_suc),
.reg1_data_i(reg1_data), .reg2_data_i(reg2_data),
.reg1_read_o(reg1_read), .reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr), .reg2_addr_o(reg2_addr),
.pc_o(id_pc_o), .aluop_o(id_aluop_o),
.alufunct3_o(id_alufunct3_o), .alufunct7_o(id_alufunct7_o),
.reg1_o(id_reg1_o), .reg2_o(id_reg2_o), .imm_o(id_imm_o),
.wd_o(id_wd_o), .wreg_o(id_wreg_o),
.stall_req(req_id),
.jump_o(jump_o), .jpc_o(jpc_o)
);
regfile regfile0(
.clk(clk), .rst(rst),
.we(wb_wreg_o), .waddr(wb_wd_o), .wdata(wb_wdata_o),
.ex_we(ex_wreg_f), .ex_waddr(ex_wd_f), .ex_wdata(ex_wdata_f),
.mem_we(mem_wreg_f), .mem_waddr(mem_wd_f), .mem_wdata(mem_wdata_f),
.re1(reg1_read), .raddr1(reg1_addr), .rsuc1(reg1_suc), .rdata1(reg1_data),
.re2(reg2_read), .raddr2(reg2_addr), .rsuc2(reg2_suc), .rdata2(reg2_data)
);
id_ex id_ex0(
.clk(clk), .rst(rst),
.id_pc(id_pc_o), .id_aluop(id_aluop_o),
.id_alufunct3(id_alufunct3_o), .id_alufunct7(id_alufunct7_o),
.id_reg1(id_reg1_o), .id_reg2(id_reg2_o), .id_imm(id_imm_o),
.id_wreg(id_wreg_o), .id_wd(id_wd_o),
.ex_pc(ex_pc_i), .ex_aluop(ex_aluop_i),
.ex_alufunct3(ex_alufunct3_i), .ex_alufunct7(ex_alufunct7_i),
.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_imm(ex_imm_i),
.ex_wreg(ex_wreg_i), .ex_wd(ex_wd_i),
.stall(stall)
);
ex ex0(
.rst(rst),
.pc_i(ex_pc_i), .aluop_i(ex_aluop_i),
.alufunct3_i(ex_alufunct3_i), .alufunct7_i(ex_alufunct7_i),
.reg1_i(ex_reg1_i), .reg2_i(ex_reg2_i), .imm_i(ex_imm_i),
.wreg_i(ex_wreg_i), .wd_i(ex_wd_i),
.aluop_o(ex_aluop_o), .alufunct3_o(ex_alufunct3_o),
.me_o(ex_me_o), .maddr_o(ex_maddr_o),
.wreg_o(ex_wreg_o), .wd_o(ex_wd_o), .wdata_o(ex_wdata_o),
.wreg_f(ex_wreg_f), .wd_f(ex_wd_f), .wdata_f(ex_wdata_f)
);
ex_mem ex_mem0(
.clk(clk), .rst(rst),
.ce(ram_ce_o),
.ex_aluop(ex_aluop_o), .ex_alufunct3(ex_alufunct3_o),
.ex_me(ex_me_o), .ex_maddr(ex_maddr_o),
.ex_wreg(ex_wreg_o), .ex_wd(ex_wd_o), .ex_wdata(ex_wdata_o),
.mem_aluop(mem_aluop_i), .mem_alufunct3(mem_alufunct3_i),
.mem_me(mem_me_i), .mem_maddr(mem_maddr_i),
.mem_wd(mem_wd_i), .mem_wreg(mem_wreg_i), .mem_wdata(mem_wdata_i)
);
mem mem0(
.rst(rst),
.aluop_i(mem_aluop_i), .alufunct3_i(mem_alufunct3_i),
.me_i(mem_me_i), .maddr_i(mem_maddr_i),
.wreg_i(mem_wreg_i), .wd_i(mem_wd_i), .wdata_i(mem_wdata_i),
.re_m(ram_re_m), .rvalid_bit(ram_rvalid_bit), .raddr_m(ram_raddr_m), .rdata_m(ram_rdata_m),
.we_m(ram_we_m), .wvalid_bit(ram_wvalid_bit), .waddr_m(ram_waddr_m), .wdata_m(ram_wdata_m),
.wreg_o(mem_wreg_o), .wd_o(mem_wd_o), .wdata_o(mem_wdata_o),
.wreg_f(mem_wreg_f), .wd_f(mem_wd_f), .wdata_f(mem_wdata_f)
);
mem_wb mem_wb0(
.clk(clk), .rst(rst),
.mem_wd(mem_wd_o), .mem_wreg(mem_wreg_o), .mem_wdata(mem_wdata_o),
.wb_wd(wb_wd_o), .wb_wreg(wb_wreg_o), .wb_wdata(wb_wdata_o)
);
endmodule | module riscv(
input wire clk,
input wire rst,
output wire rom_ce_o,
input wire[`InstBus] rom_data_i,
output wire[`InstAddrBus] rom_addr_o,
input wire req_if,
output wire ram_ce_o,
output wire ram_re_m,
output wire[`ValidBitBus] ram_rvalid_bit,
output wire[`MemAddrBus] ram_raddr_m,
input wire[`DataBus] ram_rdata_m,
output wire ram_we_m,
output wire[`ValidBitBus] ram_wvalid_bit,
output wire[`MemAddrBus] ram_waddr_m,
output wire[`DataBus] ram_wdata_m
); |
wire[`CtrlWidth] stall;
wire[`InstAddrBus] pc;
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire reg1_suc;
wire[`RegBus] reg1_data;
wire reg2_suc;
wire[`RegBus] reg2_data;
wire reg1_read;
wire reg2_read;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire req_id;
wire[`InstAddrBus] id_pc_o;
wire[`AluOpBus] id_aluop_o;
wire[`AluFunct3Bus] id_alufunct3_o;
wire[`AluFunct7Bus] id_alufunct7_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire[`RegBus] id_imm_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire jump_o;
wire[`InstAddrBus] jpc_o;
wire[`InstAddrBus] ex_pc_i;
wire[`AluOpBus] ex_aluop_i;
wire[`AluFunct3Bus] ex_alufunct3_i;
wire[`AluFunct7Bus] ex_alufunct7_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire[`RegBus] ex_imm_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire[`AluOpBus] ex_aluop_o;
wire[`AluFunct3Bus] ex_alufunct3_o;
wire ex_me_o;
wire[`MemAddrBus] ex_maddr_o;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire ex_wreg_f;
wire[`RegAddrBus] ex_wd_f;
wire[`RegBus] ex_wdata_f;
wire[`AluOpBus] mem_aluop_i;
wire[`AluFunct3Bus] mem_alufunct3_i;
wire mem_me_i;
wire[`MemAddrBus] mem_maddr_i;
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire mem_wreg_f;
wire[`RegAddrBus] mem_wd_f;
wire[`RegBus] mem_wdata_f;
wire[`RegAddrBus] wb_wd_o;
wire wb_wreg_o;
wire[`RegBus] wb_wdata_o;
ctrl ctrl0(
.rst(rst),
.req_id(req_id), .req_if(req_if),
.stall(stall)
);
pc_reg pc_reg0(
.clk(clk), .rst(rst),
.stall(stall),
.jumpout(jump_o), .pc_i(jpc_o),
.pc(pc), .ce(rom_ce_o)
);
assign rom_addr_o = pc;
if_id if_id0(
.clk(clk), .rst(rst),
.stall(stall), .jumpout(jump_o),
.if_pc(pc), .if_inst(rom_data_i),
.id_pc(id_pc_i), .id_inst(id_inst_i)
);
id id0(
.rst(rst),
.pc_i(id_pc_i), .inst_i(id_inst_i),
.reg1_suc(reg1_suc), .reg2_suc(reg2_suc),
.reg1_data_i(reg1_data), .reg2_data_i(reg2_data),
.reg1_read_o(reg1_read), .reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr), .reg2_addr_o(reg2_addr),
.pc_o(id_pc_o), .aluop_o(id_aluop_o),
.alufunct3_o(id_alufunct3_o), .alufunct7_o(id_alufunct7_o),
.reg1_o(id_reg1_o), .reg2_o(id_reg2_o), .imm_o(id_imm_o),
.wd_o(id_wd_o), .wreg_o(id_wreg_o),
.stall_req(req_id),
.jump_o(jump_o), .jpc_o(jpc_o)
);
regfile regfile0(
.clk(clk), .rst(rst),
.we(wb_wreg_o), .waddr(wb_wd_o), .wdata(wb_wdata_o),
.ex_we(ex_wreg_f), .ex_waddr(ex_wd_f), .ex_wdata(ex_wdata_f),
.mem_we(mem_wreg_f), .mem_waddr(mem_wd_f), .mem_wdata(mem_wdata_f),
.re1(reg1_read), .raddr1(reg1_addr), .rsuc1(reg1_suc), .rdata1(reg1_data),
.re2(reg2_read), .raddr2(reg2_addr), .rsuc2(reg2_suc), .rdata2(reg2_data)
);
id_ex id_ex0(
.clk(clk), .rst(rst),
.id_pc(id_pc_o), .id_aluop(id_aluop_o),
.id_alufunct3(id_alufunct3_o), .id_alufunct7(id_alufunct7_o),
.id_reg1(id_reg1_o), .id_reg2(id_reg2_o), .id_imm(id_imm_o),
.id_wreg(id_wreg_o), .id_wd(id_wd_o),
.ex_pc(ex_pc_i), .ex_aluop(ex_aluop_i),
.ex_alufunct3(ex_alufunct3_i), .ex_alufunct7(ex_alufunct7_i),
.ex_reg1(ex_reg1_i), .ex_reg2(ex_reg2_i), .ex_imm(ex_imm_i),
.ex_wreg(ex_wreg_i), .ex_wd(ex_wd_i),
.stall(stall)
);
ex ex0(
.rst(rst),
.pc_i(ex_pc_i), .aluop_i(ex_aluop_i),
.alufunct3_i(ex_alufunct3_i), .alufunct7_i(ex_alufunct7_i),
.reg1_i(ex_reg1_i), .reg2_i(ex_reg2_i), .imm_i(ex_imm_i),
.wreg_i(ex_wreg_i), .wd_i(ex_wd_i),
.aluop_o(ex_aluop_o), .alufunct3_o(ex_alufunct3_o),
.me_o(ex_me_o), .maddr_o(ex_maddr_o),
.wreg_o(ex_wreg_o), .wd_o(ex_wd_o), .wdata_o(ex_wdata_o),
.wreg_f(ex_wreg_f), .wd_f(ex_wd_f), .wdata_f(ex_wdata_f)
);
ex_mem ex_mem0(
.clk(clk), .rst(rst),
.ce(ram_ce_o),
.ex_aluop(ex_aluop_o), .ex_alufunct3(ex_alufunct3_o),
.ex_me(ex_me_o), .ex_maddr(ex_maddr_o),
.ex_wreg(ex_wreg_o), .ex_wd(ex_wd_o), .ex_wdata(ex_wdata_o),
.mem_aluop(mem_aluop_i), .mem_alufunct3(mem_alufunct3_i),
.mem_me(mem_me_i), .mem_maddr(mem_maddr_i),
.mem_wd(mem_wd_i), .mem_wreg(mem_wreg_i), .mem_wdata(mem_wdata_i)
);
mem mem0(
.rst(rst),
.aluop_i(mem_aluop_i), .alufunct3_i(mem_alufunct3_i),
.me_i(mem_me_i), .maddr_i(mem_maddr_i),
.wreg_i(mem_wreg_i), .wd_i(mem_wd_i), .wdata_i(mem_wdata_i),
.re_m(ram_re_m), .rvalid_bit(ram_rvalid_bit), .raddr_m(ram_raddr_m), .rdata_m(ram_rdata_m),
.we_m(ram_we_m), .wvalid_bit(ram_wvalid_bit), .waddr_m(ram_waddr_m), .wdata_m(ram_wdata_m),
.wreg_o(mem_wreg_o), .wd_o(mem_wd_o), .wdata_o(mem_wdata_o),
.wreg_f(mem_wreg_f), .wd_f(mem_wd_f), .wdata_f(mem_wdata_f)
);
mem_wb mem_wb0(
.clk(clk), .rst(rst),
.mem_wd(mem_wd_o), .mem_wreg(mem_wreg_o), .mem_wdata(mem_wdata_o),
.wb_wd(wb_wd_o), .wb_wreg(wb_wreg_o), .wb_wdata(wb_wdata_o)
);
endmodule | 0 |
5,602 | data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v | 114,459,345 | riscv_min_sopc_tb.v | v | 30 | 34 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 42059: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcCache,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:3: Cannot find include file: riscv_min_sopc.v\n`include "riscv_min_sopc.v" \n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:20: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:20: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:21: Define or directive not defined: \'`RstDisable\'\n #195 rst= `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 rst= `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #195 rst= `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114459345/srcCache/riscv_min_sopc_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10000 $finish;\n ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n' | 6,321 | module | module riscv_min_sopc_tb();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever begin
#10 CLOCK_50 = ~CLOCK_50;
end
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#10000 $finish;
end
riscv_min_sopc riscv_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | module riscv_min_sopc_tb(); |
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever begin
#10 CLOCK_50 = ~CLOCK_50;
end
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#10000 $finish;
end
riscv_min_sopc riscv_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | 0 |
5,603 | data/full_repos/permissive/114459345/srcCache/test_coding.v | 114,459,345 | test_coding.v | v | 53 | 79 | [] | [] | [] | null | line:16: before: "," | null | 1: b'%Error: data/full_repos/permissive/114459345/srcCache/test_coding.v:16: syntax error, unexpected \',\', expecting \'}\'\n b = {reg1_i[31:1] + reg2_i[31:1] + {30{1\'b0}, reg1_i[0] & reg2_i[0]}, 1\'b0};\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114459345/srcCache/test_coding.v:21: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 6,323 | module | module test_mod;
reg[31:0] t;
reg[31:0] m;
reg clk;
reg a;
reg b;
reg c;
initial begin
b = {reg1_i[31:1] + reg2_i[31:1] + {30{1'b0}, reg1_i[0] & reg2_i[0]}, 1'b0};
a = 1'b0;
clk = 1'b0;
c = {{0{"1"}},1'b0};
$display(c);
forever #1 clk = ~clk;
end
always @ (posedge clk) begin
a <= ~a;
end
always @ (posedge clk) begin
b <= a;
end
always @ (b) begin
end
endmodule | module test_mod; |
reg[31:0] t;
reg[31:0] m;
reg clk;
reg a;
reg b;
reg c;
initial begin
b = {reg1_i[31:1] + reg2_i[31:1] + {30{1'b0}, reg1_i[0] & reg2_i[0]}, 1'b0};
a = 1'b0;
clk = 1'b0;
c = {{0{"1"}},1'b0};
$display(c);
forever #1 clk = ~clk;
end
always @ (posedge clk) begin
a <= ~a;
end
always @ (posedge clk) begin
b <= a;
end
always @ (b) begin
end
endmodule | 0 |
5,604 | data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v | 114,459,345 | riscv_min_sopc.v | v | 68 | 88 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38121: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:3: Cannot find include file: riscv.v\n`include "riscv.v" \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:4: Cannot find include file: rom_ram.v\n`include "rom_ram.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:15: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] inst_addr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] inst_addr;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:16: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] inst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] inst;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:22: Define or directive not defined: \'`ValidBitBus\'\n wire[`ValidBitBus] rvalid_bit;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ValidBitBus] rvalid_bit;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:23: Define or directive not defined: \'`DataAddrBus\'\n wire[`DataAddrBus] raddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataAddrBus] raddr;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:24: Define or directive not defined: \'`DataBus\'\n wire[`DataBus] rdata;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataBus] rdata;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:26: Define or directive not defined: \'`ValidBitBus\'\n wire[`ValidBitBus] wvalid_bit;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:26: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`ValidBitBus] wvalid_bit;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:27: Define or directive not defined: \'`DataAddrBus\'\n wire[`DataAddrBus] waddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataAddrBus] waddr;\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:28: Define or directive not defined: \'`DataBus\'\n wire[`DataBus] wdata;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/riscv_min_sopc.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`DataBus] wdata;\n ^\n%Error: Exiting due to 19 error(s)\n' | 6,338 | module | module riscv_min_sopc(
input wire clk,
input wire rst
);
wire[`InstAddrBus] inst_addr;
wire[`InstBus] inst;
wire rom_ce;
wire req_if;
wire re;
wire[`ValidBitBus] rvalid_bit;
wire[`DataAddrBus] raddr;
wire[`DataBus] rdata;
wire we;
wire[`ValidBitBus] wvalid_bit;
wire[`DataAddrBus] waddr;
wire[`DataBus] wdata;
wire ram_ce;
riscv riscv0(
.clk(clk),.rst(rst),
.rom_addr_o(inst_addr), .rom_data_i(inst), .rom_ce_o(rom_ce), .req_if(req_if),
.ram_ce_o(ram_ce),
.ram_re_m(re), .ram_rvalid_bit(rvalid_bit), .ram_raddr_m(raddr), .ram_rdata_m(rdata),
.ram_we_m(we), .ram_wvalid_bit(wvalid_bit), .ram_waddr_m(waddr), .ram_wdata_m(wdata)
);
rom_ram rom_ram0(
.rom_ce(rom_ce),
.addr(inst_addr),
.inst(inst),
.stall_req(req_if),
.ram_ce(ram_ce),
.we(we), .wvalid_bit(wvalid_bit), .waddr(waddr), .data_i(wdata),
.re(re), .rvalid_bit(rvalid_bit), .raddr(raddr), .data_o(rdata)
);
endmodule | module riscv_min_sopc(
input wire clk,
input wire rst
); |
wire[`InstAddrBus] inst_addr;
wire[`InstBus] inst;
wire rom_ce;
wire req_if;
wire re;
wire[`ValidBitBus] rvalid_bit;
wire[`DataAddrBus] raddr;
wire[`DataBus] rdata;
wire we;
wire[`ValidBitBus] wvalid_bit;
wire[`DataAddrBus] waddr;
wire[`DataBus] wdata;
wire ram_ce;
riscv riscv0(
.clk(clk),.rst(rst),
.rom_addr_o(inst_addr), .rom_data_i(inst), .rom_ce_o(rom_ce), .req_if(req_if),
.ram_ce_o(ram_ce),
.ram_re_m(re), .ram_rvalid_bit(rvalid_bit), .ram_raddr_m(raddr), .ram_rdata_m(rdata),
.ram_we_m(we), .ram_wvalid_bit(wvalid_bit), .ram_waddr_m(waddr), .ram_wdata_m(wdata)
);
rom_ram rom_ram0(
.rom_ce(rom_ce),
.addr(inst_addr),
.inst(inst),
.stall_req(req_if),
.ram_ce(ram_ce),
.we(we), .wvalid_bit(wvalid_bit), .waddr(waddr), .data_i(wdata),
.re(re), .rvalid_bit(rvalid_bit), .raddr(raddr), .data_o(rdata)
);
endmodule | 0 |
5,605 | data/full_repos/permissive/114459345/srcOrigin/rom_ram.v | 114,459,345 | rom_ram.v | v | 113 | 90 | [] | [] | [] | [(200, 309)] | null | null | 1: b'%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:2: Cannot find include file: defs.v\n`include "defs.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.v\n data/full_repos/permissive/114459345/srcOrigin,data/full_repos/permissive/114459345/defs.v.sv\n defs.v\n defs.v.v\n defs.v.sv\n obj_dir/defs.v\n obj_dir/defs.v.v\n obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:7: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`InstBus] inst,\n ^~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:13: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire we,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] wvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:20: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] wvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:21: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] waddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:22: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:26: Define or directive not defined: \'`ValidBitBus\'\n input wire[`ValidBitBus] rvalid_bit,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:27: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] raddr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:28: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] data_o \n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:33: Define or directive not defined: \'`DataMemNum\'\n reg[7:0] data_mem[0:`DataMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:35: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:44: Define or directive not defined: \'`ChipDisable\'\n if(rom_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:45: Define or directive not defined: \'`NopInst\'\n inst <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:46: Define or directive not defined: \'`Continue\'\n stall_req <= `Continue;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:49: Define or directive not defined: \'`WriteEnable\'\n if(we == `WriteEnable) begin \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:50: Define or directive not defined: \'`Stop\'\n stall_req <= `Stop;\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:53: Define or directive not defined: \'`Continue\'\n stall_req <= `Continue;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:61: Define or directive not defined: \'`ChipDisable\'\n if(ram_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:64: Define or directive not defined: \'`WriteEnable\'\n else if(we == `WriteEnable) begin \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:66: Define or directive not defined: \'`Byte\'\n `Byte : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:69: Define or directive not defined: \'`Half\'\n `Half : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:73: Define or directive not defined: \'`Word\'\n `Word : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:89: Define or directive not defined: \'`ChipDisable\'\n if(ram_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:90: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:92: Define or directive not defined: \'`WriteEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:92: Define or directive not defined: \'`ReadEnable\'\n else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:95: Define or directive not defined: \'`ReadEnable\'\n else if(re == `ReadEnable) begin \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:97: Define or directive not defined: \'`Byte\'\n `Byte : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:100: Define or directive not defined: \'`Half\'\n `Half : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:103: Define or directive not defined: \'`Word\'\n `Word : begin\n ^~~~~\n%Error: data/full_repos/permissive/114459345/srcOrigin/rom_ram.v:109: Define or directive not defined: \'`ZeroWord\'\n data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 36 error(s)\n' | 6,340 | module | module rom_ram(
input wire rom_ce,
input wire[`InstAddrBus] addr,
output reg stall_req,
output reg[`InstBus] inst,
input wire ram_ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o
);
reg[7:0] data_mem[0:`DataMemNum-1];
initial begin
$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", data_mem);
end
always @ (*) begin
if(rom_ce == `ChipDisable) begin
inst <= `NopInst;
stall_req <= `Continue;
end
else begin
if(we == `WriteEnable) begin
stall_req <= `Stop;
end
else begin
stall_req <= `Continue;
inst <= {data_mem[addr + 3], data_mem[addr + 2], data_mem[addr + 1], data_mem[addr]};
end
end
end
always @ (*) begin
if(ram_ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
case(wvalid_bit)
`Byte : begin
data_mem[waddr] <= data_i[7:0];
end
`Half : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
end
`Word : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
data_mem[waddr+2] <= data_i[23:16];
data_mem[waddr+3] <= data_i[31:24];
end
default : begin
end
endcase
$display("mem_wdata -> %c", data_i[7:0]);
end
end
always @ (*) begin
if(ram_ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= data_i;
end
else if(re == `ReadEnable) begin
case(rvalid_bit)
`Byte : begin
data_o <= {{24{1'b0}}, data_mem[raddr]};
end
`Half : begin
data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
end
`Word : begin
data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
end
endcase
end
else begin
data_o <= `ZeroWord;
end
end
endmodule | module rom_ram(
input wire rom_ce,
input wire[`InstAddrBus] addr,
output reg stall_req,
output reg[`InstBus] inst,
input wire ram_ce,
input wire we,
input wire[`ValidBitBus] wvalid_bit,
input wire[`DataAddrBus] waddr,
input wire[`DataBus] data_i,
input wire re,
input wire[`ValidBitBus] rvalid_bit,
input wire[`DataAddrBus] raddr,
output reg[`DataBus] data_o
); |
reg[7:0] data_mem[0:`DataMemNum-1];
initial begin
$readmemh("D:\\Coding\\cpu-risc-v\\inst_test\\helloworld.s", data_mem);
end
always @ (*) begin
if(rom_ce == `ChipDisable) begin
inst <= `NopInst;
stall_req <= `Continue;
end
else begin
if(we == `WriteEnable) begin
stall_req <= `Stop;
end
else begin
stall_req <= `Continue;
inst <= {data_mem[addr + 3], data_mem[addr + 2], data_mem[addr + 1], data_mem[addr]};
end
end
end
always @ (*) begin
if(ram_ce == `ChipDisable) begin
end
else if(we == `WriteEnable) begin
case(wvalid_bit)
`Byte : begin
data_mem[waddr] <= data_i[7:0];
end
`Half : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
end
`Word : begin
data_mem[waddr] <= data_i[7:0];
data_mem[waddr+1] <= data_i[15:8];
data_mem[waddr+2] <= data_i[23:16];
data_mem[waddr+3] <= data_i[31:24];
end
default : begin
end
endcase
$display("mem_wdata -> %c", data_i[7:0]);
end
end
always @ (*) begin
if(ram_ce == `ChipDisable) begin
data_o <= `ZeroWord;
end
else if((raddr == waddr) && (we == `WriteEnable) && (re == `ReadEnable)) begin
data_o <= data_i;
end
else if(re == `ReadEnable) begin
case(rvalid_bit)
`Byte : begin
data_o <= {{24{1'b0}}, data_mem[raddr]};
end
`Half : begin
data_o <= {{16{1'b0}}, data_mem[raddr+1],data_mem[raddr]};
end
`Word : begin
data_o <= {data_mem[raddr+3],data_mem[raddr+2],data_mem[raddr+1],data_mem[raddr]};
end
endcase
end
else begin
data_o <= `ZeroWord;
end
end
endmodule | 0 |
5,606 | data/full_repos/permissive/11448235/fpga.v | 11,448,235 | fpga.v | v | 93 | 158 | [] | [] | [] | null | line:72: before: "," | null | 1: b"%Error: data/full_repos/permissive/11448235/fpga.v:34: Cannot find file containing module: 'dcm'\n dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk)); \n ^~~\n ... Looked in:\n data/full_repos/permissive/11448235,data/full_repos/permissive/11448235/dcm\n data/full_repos/permissive/11448235,data/full_repos/permissive/11448235/dcm.v\n data/full_repos/permissive/11448235,data/full_repos/permissive/11448235/dcm.sv\n dcm\n dcm.v\n dcm.sv\n obj_dir/dcm\n obj_dir/dcm.v\n obj_dir/dcm.sv\n%Error: data/full_repos/permissive/11448235/fpga.v:48: Cannot find file containing module: 'debounce'\n debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));\n ^~~~~~~~\n%Error: data/full_repos/permissive/11448235/fpga.v:55: Cannot find file containing module: 'sseg'\n sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));\n ^~~~\n%Error: data/full_repos/permissive/11448235/fpga.v:69: Cannot find file containing module: 'uart_multibyte_transmitter'\n uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbtx(.clk(clk), .data(uart_rx_data), .req(uart_tx_req), .uart_tx(RsTx));\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/11448235/fpga.v:76: Cannot find file containing module: 'uart_multibyte_receiver'\n uart_multibyte_receiver #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b1), .uart_rx(RsRx2));\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 6,342 | module | module fpga(
input wire input_clk,
input wire [7:0] sw,
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an,
output wire RsTx,
input wire RsRx
);
wire clk;
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));
reg [4:0] btn_sync, btn_sync2;
always @(posedge clk) begin
{btn_sync, btn_sync2} <= {btn, btn_sync};
end
wire [4:0] btn_debounced;
genvar idx;
generate
for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
end
endgenerate
reg [15:0] ctr;
reg [4:0] btn_prev;
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
wire uart_tx_req, uart_tx_ready;
wire [31:0] uart_rx_data;
wire uart_rx_valid;
assign uart_tx_req = uart_rx_valid;
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbtx(.clk(clk), .data(uart_rx_data), .req(uart_tx_req), .uart_tx(RsTx));
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
uart_multibyte_receiver #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b1), .uart_rx(RsRx2));
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
if (uart_rx_valid) begin
ctr <= uart_rx_data[15:0];
end
btn_prev <= btn_debounced;
end
endmodule | module fpga(
input wire input_clk,
input wire [7:0] sw,
input wire [4:0] btn,
output wire [7:0] led,
output wire [7:0] seg,
output wire [3:0] an,
output wire RsTx,
input wire RsRx
); |
wire clk;
dcm dcm(.CLK_IN(input_clk), .CLK_OUT(clk));
reg [4:0] btn_sync, btn_sync2;
always @(posedge clk) begin
{btn_sync, btn_sync2} <= {btn, btn_sync};
end
wire [4:0] btn_debounced;
genvar idx;
generate
for (idx=0; idx<5; idx=idx+1) begin: debounce_btn
debounce btn_db(.clk(clk), .in(btn_sync2[idx]), .out(btn_debounced[idx]));
end
endgenerate
reg [15:0] ctr;
reg [4:0] btn_prev;
sseg #(.N(16)) sseg(.clk(clk), .in(ctr), .c(seg), .an(an));
wire uart_tx_req, uart_tx_ready;
wire [31:0] uart_rx_data;
wire uart_rx_valid;
assign uart_tx_req = uart_rx_valid;
uart_multibyte_transmitter #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbtx(.clk(clk), .data(uart_rx_data), .req(uart_tx_req), .uart_tx(RsTx));
reg RsRx1=1, RsRx2=1;
always @(posedge clk) begin
{RsRx1, RsRx2} <= {RsRx, RsRx1};
end
uart_multibyte_receiver #(.CLK_CYCLES(87), .MSG_LOG_WIDTH(2)) uart_mbrx(.clk(clk), .data(uart_rx_data), .valid(uart_rx_valid), .ack(1'b1), .uart_rx(RsRx2));
always @(posedge clk) begin
if (btn_debounced[0] && !btn_prev[0]) ctr <= ctr + 1'b1;
if (btn_debounced[2] && !btn_prev[2]) ctr <= 0;
if (uart_rx_valid) begin
ctr <= uart_rx_data[15:0];
end
btn_prev <= btn_debounced;
end
endmodule | 3 |
5,618 | data/full_repos/permissive/11448235/test/sha_chunk_test.v | 11,448,235 | sha_chunk_test.v | v | 65 | 81 | [] | [] | [] | [(25, 63)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11448235/test/sha_chunk_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #(P/2) clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11448235/test/sha_chunk_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n #(80*P);\n ^\n%Error: data/full_repos/permissive/11448235/test/sha_chunk_test.v:55: Can\'t find definition of \'roundnum\' in dotted variable: \'uut.roundnum\'\n uut.roundnum = 6\'h3e;\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,348 | module | module sha_chunk_test;
reg [511:0] data;
reg [255:0] V_in;
reg clk = 0;
wire [255:0] hash;
sha256_chunk uut (
.clk(clk),
.data(data),
.V_in(V_in),
.hash(hash)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
data = 0;
data[7:0] = 8'd97;
data[15:8] = 8'd98;
data[23:16] = 8'd99;
data[31:24] = 8'h80;
data[511:504] = 8'd24;
V_in = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
uut.roundnum = 6'h3e;
#(80*P);
$stop();
end
endmodule | module sha_chunk_test; |
reg [511:0] data;
reg [255:0] V_in;
reg clk = 0;
wire [255:0] hash;
sha256_chunk uut (
.clk(clk),
.data(data),
.V_in(V_in),
.hash(hash)
);
parameter P=10;
always #(P/2) clk = ~clk;
initial begin
data = 0;
data[7:0] = 8'd97;
data[15:8] = 8'd98;
data[23:16] = 8'd99;
data[31:24] = 8'h80;
data[511:504] = 8'd24;
V_in = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
uut.roundnum = 6'h3e;
#(80*P);
$stop();
end
endmodule | 3 |
5,619 | data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v | 114,498,561 | core_top_tb.v | v | 545 | 75 | [] | [] | [] | null | line:139: before: "resetb_tb" | null | 1: b'%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:5: Cannot find include file: core/opcode.vh\n `include "core/opcode.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i,data/full_repos/permissive/114498561/core/opcode.vh\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i,data/full_repos/permissive/114498561/core/opcode.vh.v\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i,data/full_repos/permissive/114498561/core/opcode.vh.sv\n core/opcode.vh\n core/opcode.vh.v\n core/opcode.vh.sv\n obj_dir/core/opcode.vh\n obj_dir/core/opcode.vh.v\n obj_dir/core/opcode.vh.sv\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:32: Define or directive not defined: \'`LOAD\'\n `LOAD: FD_disasm_opcode = "LOAD ";\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:32: syntax error, unexpected \':\', expecting endcase\n `LOAD: FD_disasm_opcode = "LOAD ";\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:33: Define or directive not defined: \'`OP_IMM\'\n `OP_IMM: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:47: Define or directive not defined: \'`AUIPC\'\n `AUIPC: FD_disasm_opcode = "AUIPC ";\n ^~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:48: Define or directive not defined: \'`STORE\'\n `STORE: FD_disasm_opcode = "STORE ";\n ^~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:49: Define or directive not defined: \'`OP\'\n `OP: begin\n ^~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:64: Define or directive not defined: \'`LUI\'\n `LUI: FD_disasm_opcode = "LUI ";\n ^~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:65: Define or directive not defined: \'`BRANCH\'\n `BRANCH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:76: Define or directive not defined: \'`JALR\'\n `JALR: FD_disasm_opcode = "JALR ";\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:77: Define or directive not defined: \'`JAL\'\n `JAL: FD_disasm_opcode = "JAL ";\n ^~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:78: Define or directive not defined: \'`SYSTEM\'\n `SYSTEM: begin \n ^~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:118: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:125: syntax error, unexpected \'[\', expecting IDENTIFIER\n instruction_memory_tb[i][8*j+:8] = bytes[i*4+j];\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:128: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:139: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:152: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h", FD_disasm_opcode, UUT.FD_PC);\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:161: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:173: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D", \n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:183: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:195: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D", \n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:205: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:215: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h", \n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:225: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:237: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h", \n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:247: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:258: syntax error, unexpected $display\n $display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h", \n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:268: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:281: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:290: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:303: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:312: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:325: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:334: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:347: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:356: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:369: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:378: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:391: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:400: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:413: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:422: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:435: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:444: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:457: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:466: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:482: syntax error, unexpected $display\n $display("(TT) Test failed!");\n ^~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:513: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_log/core_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:514: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,core_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core_top_tb.v:519: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,352 | module | module core_tb();
`include "core/opcode.vh"
reg clk_tb, resetb_tb;
wire dm_we_tb;
wire [31:0] im_addr_tb, dm_addr_tb, dm_di_tb;
wire [31:0] im_do_tb, dm_do_tb;
wire [3:0] dm_be_tb;
wire dm_is_signed_tb;
wire [11:2] im_addr_out_tb;
wire [31:0] im_data_tb, io_data_read_tb, io_data_write_tb;
wire [7:0] io_addr_tb;
wire io_en_tb, io_we_tb;
reg [31:0] instruction_memory_tb [0:1023];
reg [31:0] io_memory_tb [0:255];
integer i;
reg [32767:0] im_rom_flattened;
always @ (*) begin
for (i=0; i<1024; i=i+1)
im_rom_flattened[i*4+:32] = instruction_memory_tb[i];
end
reg [255:0] FD_disasm_opcode;
always @ (*) begin : Disassembly
case (UUT.inst_dec.opcode[6:2])
`LOAD: FD_disasm_opcode = "LOAD ";
`OP_IMM: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = "ADDI ";
3'b001: FD_disasm_opcode = "SLLI ";
3'b010: FD_disasm_opcode = "SLTI ";
3'b011: FD_disasm_opcode = "SLTIU ";
3'b100: FD_disasm_opcode = "XORI ";
3'b101: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SRAI " : "SRLI ";
3'b110: FD_disasm_opcode = "ORI ";
3'b111: FD_disasm_opcode = "ANDI ";
default: FD_disasm_opcode = "OP-IMM ";
endcase
end
`AUIPC: FD_disasm_opcode = "AUIPC ";
`STORE: FD_disasm_opcode = "STORE ";
`OP: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SUB " : "ADD ";
3'b001: FD_disasm_opcode = "SLL ";
3'b010: FD_disasm_opcode = "SLT ";
3'b011: FD_disasm_opcode = "SLTU ";
3'b100: FD_disasm_opcode = "XOR ";
3'b101: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SRA " : "SRL ";
3'b110: FD_disasm_opcode = "OR ";
3'b111: FD_disasm_opcode = "AND ";
default: FD_disasm_opcode = "OP? ";
endcase
end
`LUI: FD_disasm_opcode = "LUI ";
`BRANCH: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = "BEQ ";
3'b001: FD_disasm_opcode = "BNE ";
3'b100: FD_disasm_opcode = "BLT ";
3'b101: FD_disasm_opcode = "BGE ";
3'b110: FD_disasm_opcode = "BLTU ";
3'b111: FD_disasm_opcode = "BGEU ";
default: FD_disasm_opcode = "BRANCH ";
endcase
end
`JALR: FD_disasm_opcode = "JALR ";
`JAL: FD_disasm_opcode = "JAL ";
`SYSTEM: begin
case (UUT.inst_dec.funct3)
3'b000: begin
if (UUT.inst_dec.funct7==7'b0011000 &&
UUT.inst_dec.a_rs2 == 5'b00010 &&
UUT.inst_dec.a_rs1 == 5'b00000)
FD_disasm_opcode = "MRET ";
else
FD_disasm_opcode = "SYSTEM ";
end
3'b001: FD_disasm_opcode = "CSRRW ";
3'b010: FD_disasm_opcode = "CSRRS ";
3'b011: FD_disasm_opcode = "CSRRC ";
3'b101: FD_disasm_opcode = "CSRRWI ";
3'b110: FD_disasm_opcode = "CSRRSI ";
3'b111: FD_disasm_opcode = "CSRRCI ";
default: FD_disasm_opcode = "SYSTEM ";
endcase
end
default: FD_disasm_opcode = "ILLEGAL ";
endcase
end
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
task hard_reset;
begin
resetb_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
end
endtask
task load_program;
input [2047:0] path;
integer fid, tmp;
reg [7:0] bytes [0:4095];
integer i,j;
begin
fid = $fopen(path, "rb");
tmp = $fread(bytes, fid);
$fclose(fid);
for (i=0; i<1024; i=i+1) begin
for (j=0; j<4; j=j+1) begin
instruction_memory_tb[i][8*j+:8] = bytes[i*4+j];
end
end
end
endtask
task render_pipeline;
begin
end
endtask
task run_test0;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 0: NOP and J Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. Before reset, PC is at 0xFFFFFFFC.");
$display("(TT) 3. Reset PC is 0x0, which then jumps to 0xC.");
$display("(TT) 4. Then, increments at steps of 0x4.");
$display("(TT) 5. Then, jumps to 0xC after 0x20.");
$display("(TT) --------------------------------------------------");
load_program("tb_out/00-nop.bin");
hard_reset();
for (i=0; i<12; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h", FD_disasm_opcode, UUT.FD_PC);
@(posedge clk_tb);
end
end
endtask
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: OP-IMM Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. OP-IMM's start at PC=10, depositing x1 in XB stage");
$display("(TT) 3. x1=1,2,3,4,5,6,1,2,1,0,1,-1,-1");
$display("(TT) 4. Loops to 0x0C at 0x40");
$display("(TT) --------------------------------------------------");
load_program("tb_out/01-opimm.bin");
hard_reset();
for (i=0; i<20; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D",
FD_disasm_opcode, UUT.FD_PC, $signed(UUT.RF.data[1]));
@(posedge clk_tb);
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: OP Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. OP's start at PC=14. x1 has 2 clock delay");
$display("(TT) 3. x1=4,3,1,0,1,0,1,2,4,2,-2,-1,1,0,1");
$display("(TT) 4. Loops to 0x0C at 50");
$display("(TT) --------------------------------------------------");
load_program("tb_out/02-op.bin");
hard_reset();
for (i=0; i<24; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D",
FD_disasm_opcode, UUT.FD_PC, $signed(UUT.RF.data[1]));
@(posedge clk_tb);
end
end
endtask
task run_test3;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 3: Branch Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. Each type of branch instruction executes twice");
$display("(TT) --------------------------------------------------");
load_program("tb_out/03-br.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h",
FD_disasm_opcode, UUT.FD_PC);
@(posedge clk_tb);
end
end
endtask
task run_test4;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 4: LUI/AUIPC Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. First, x1 will be loaded with 0xDEADBEEF");
$display("(TT) 3. Then, x1 will be loaded with PC=0x14");
$display("(TT) 4. Loops at 0x18");
$display("(TT) --------------------------------------------------");
load_program("tb_out/04-lui.bin");
hard_reset();
for (i=0; i<16; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h",
FD_disasm_opcode, UUT.FD_PC, UUT.RF.data[1]);
@(posedge clk_tb);
end
end
endtask
task run_test5;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 5: JAL/JALR Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. PC=00,0C,18,10,1C,14,0C,18,10,1C,...");
$display("(TT) 3. x1=XX,XX,XX,10,10,14,20,20,10,10,...");
$display("(TT) --------------------------------------------------");
load_program("tb_out/05-jalr.bin");
hard_reset();
for (i=0; i<16; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h",
FD_disasm_opcode, UUT.FD_PC, UUT.RF.data[1]);
@(posedge clk_tb);
end
end
endtask
task run_test6;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 6: CSRR Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/06-csrr.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test7;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 7: CSRWI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/07-csrwi.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test8;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 8: CSRW Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/08-csrw.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test9;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 9: CSRSI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/09-csrsi.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test10;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 10: CSRS Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/10-csrs.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test11;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 11: CSRCI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/11-csrci.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test12;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 12: CSRC Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/12-csrc.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test13;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 13: CSR Atomic Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/13-csr.bin");
hard_reset();
for (i=0; i<12; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test14;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 14: Memory");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/14-mem.bin");
hard_reset();
for (i=0; i<80; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test15;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 15: Exception");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/15-exception.bin");
hard_reset();
for (i=0; i<256; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
assign im_data_tb = instruction_memory_tb[im_addr_out_tb[11:2]];
assign io_data_read_tb = io_memory_tb[io_addr_tb[7:2]];
mmu MMU0(.clk(clk_tb), .resetb(resetb_tb), .dm_we(dm_we_tb),
.im_addr(im_addr_tb), .im_do(im_do_tb),
.dm_addr(dm_addr_tb), .dm_di(dm_di_tb),
.dm_do(dm_do_tb), .dm_be(dm_be_tb),
.is_signed(dm_is_signed_tb),
.im_addr_out(im_addr_out_tb), .im_data(im_data_tb),
.io_addr(io_addr_tb), .io_en(io_en_tb), .io_we(io_we_tb),
.io_data_read(io_data_read_tb), .io_data_write(io_data_write_tb)
);
core UUT
(
.clk(clk_tb), .resetb(resetb_tb),
.dm_we(dm_we_tb), .im_addr(im_addr_tb),
.im_do(im_do_tb), .dm_addr(dm_addr_tb),
.dm_di(dm_di_tb), .dm_do(dm_do_tb),
.dm_be(dm_be_tb), .dm_is_signed(dm_is_signed_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/core_tb.vcd");
$dumpvars(0,core_tb);
for (i = 0; i < 256; i = i + 1) begin
io_memory_tb[i] = 4096 + i;
end
@(posedge clk_tb);
run_test0();
run_test1();
run_test2();
run_test3();
run_test4();
run_test5();
run_test6();
run_test7();
run_test8();
run_test9();
run_test10();
run_test11();
run_test12();
run_test13();
run_test14();
run_test15();
$finish;
end
endmodule | module core_tb(); |
`include "core/opcode.vh"
reg clk_tb, resetb_tb;
wire dm_we_tb;
wire [31:0] im_addr_tb, dm_addr_tb, dm_di_tb;
wire [31:0] im_do_tb, dm_do_tb;
wire [3:0] dm_be_tb;
wire dm_is_signed_tb;
wire [11:2] im_addr_out_tb;
wire [31:0] im_data_tb, io_data_read_tb, io_data_write_tb;
wire [7:0] io_addr_tb;
wire io_en_tb, io_we_tb;
reg [31:0] instruction_memory_tb [0:1023];
reg [31:0] io_memory_tb [0:255];
integer i;
reg [32767:0] im_rom_flattened;
always @ (*) begin
for (i=0; i<1024; i=i+1)
im_rom_flattened[i*4+:32] = instruction_memory_tb[i];
end
reg [255:0] FD_disasm_opcode;
always @ (*) begin : Disassembly
case (UUT.inst_dec.opcode[6:2])
`LOAD: FD_disasm_opcode = "LOAD ";
`OP_IMM: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = "ADDI ";
3'b001: FD_disasm_opcode = "SLLI ";
3'b010: FD_disasm_opcode = "SLTI ";
3'b011: FD_disasm_opcode = "SLTIU ";
3'b100: FD_disasm_opcode = "XORI ";
3'b101: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SRAI " : "SRLI ";
3'b110: FD_disasm_opcode = "ORI ";
3'b111: FD_disasm_opcode = "ANDI ";
default: FD_disasm_opcode = "OP-IMM ";
endcase
end
`AUIPC: FD_disasm_opcode = "AUIPC ";
`STORE: FD_disasm_opcode = "STORE ";
`OP: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SUB " : "ADD ";
3'b001: FD_disasm_opcode = "SLL ";
3'b010: FD_disasm_opcode = "SLT ";
3'b011: FD_disasm_opcode = "SLTU ";
3'b100: FD_disasm_opcode = "XOR ";
3'b101: FD_disasm_opcode = UUT.inst_dec.funct7[5]
? "SRA " : "SRL ";
3'b110: FD_disasm_opcode = "OR ";
3'b111: FD_disasm_opcode = "AND ";
default: FD_disasm_opcode = "OP? ";
endcase
end
`LUI: FD_disasm_opcode = "LUI ";
`BRANCH: begin
case (UUT.inst_dec.funct3)
3'b000: FD_disasm_opcode = "BEQ ";
3'b001: FD_disasm_opcode = "BNE ";
3'b100: FD_disasm_opcode = "BLT ";
3'b101: FD_disasm_opcode = "BGE ";
3'b110: FD_disasm_opcode = "BLTU ";
3'b111: FD_disasm_opcode = "BGEU ";
default: FD_disasm_opcode = "BRANCH ";
endcase
end
`JALR: FD_disasm_opcode = "JALR ";
`JAL: FD_disasm_opcode = "JAL ";
`SYSTEM: begin
case (UUT.inst_dec.funct3)
3'b000: begin
if (UUT.inst_dec.funct7==7'b0011000 &&
UUT.inst_dec.a_rs2 == 5'b00010 &&
UUT.inst_dec.a_rs1 == 5'b00000)
FD_disasm_opcode = "MRET ";
else
FD_disasm_opcode = "SYSTEM ";
end
3'b001: FD_disasm_opcode = "CSRRW ";
3'b010: FD_disasm_opcode = "CSRRS ";
3'b011: FD_disasm_opcode = "CSRRC ";
3'b101: FD_disasm_opcode = "CSRRWI ";
3'b110: FD_disasm_opcode = "CSRRSI ";
3'b111: FD_disasm_opcode = "CSRRCI ";
default: FD_disasm_opcode = "SYSTEM ";
endcase
end
default: FD_disasm_opcode = "ILLEGAL ";
endcase
end
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
task hard_reset;
begin
resetb_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
end
endtask
task load_program;
input [2047:0] path;
integer fid, tmp;
reg [7:0] bytes [0:4095];
integer i,j;
begin
fid = $fopen(path, "rb");
tmp = $fread(bytes, fid);
$fclose(fid);
for (i=0; i<1024; i=i+1) begin
for (j=0; j<4; j=j+1) begin
instruction_memory_tb[i][8*j+:8] = bytes[i*4+j];
end
end
end
endtask
task render_pipeline;
begin
end
endtask
task run_test0;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 0: NOP and J Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. Before reset, PC is at 0xFFFFFFFC.");
$display("(TT) 3. Reset PC is 0x0, which then jumps to 0xC.");
$display("(TT) 4. Then, increments at steps of 0x4.");
$display("(TT) 5. Then, jumps to 0xC after 0x20.");
$display("(TT) --------------------------------------------------");
load_program("tb_out/00-nop.bin");
hard_reset();
for (i=0; i<12; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h", FD_disasm_opcode, UUT.FD_PC);
@(posedge clk_tb);
end
end
endtask
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: OP-IMM Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. OP-IMM's start at PC=10, depositing x1 in XB stage");
$display("(TT) 3. x1=1,2,3,4,5,6,1,2,1,0,1,-1,-1");
$display("(TT) 4. Loops to 0x0C at 0x40");
$display("(TT) --------------------------------------------------");
load_program("tb_out/01-opimm.bin");
hard_reset();
for (i=0; i<20; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D",
FD_disasm_opcode, UUT.FD_PC, $signed(UUT.RF.data[1]));
@(posedge clk_tb);
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: OP Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. OP's start at PC=14. x1 has 2 clock delay");
$display("(TT) 3. x1=4,3,1,0,1,0,1,2,4,2,-2,-1,1,0,1");
$display("(TT) 4. Loops to 0x0C at 50");
$display("(TT) --------------------------------------------------");
load_program("tb_out/02-op.bin");
hard_reset();
for (i=0; i<24; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=%0D",
FD_disasm_opcode, UUT.FD_PC, $signed(UUT.RF.data[1]));
@(posedge clk_tb);
end
end
endtask
task run_test3;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 3: Branch Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. Each type of branch instruction executes twice");
$display("(TT) --------------------------------------------------");
load_program("tb_out/03-br.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h",
FD_disasm_opcode, UUT.FD_PC);
@(posedge clk_tb);
end
end
endtask
task run_test4;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 4: LUI/AUIPC Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. First, x1 will be loaded with 0xDEADBEEF");
$display("(TT) 3. Then, x1 will be loaded with PC=0x14");
$display("(TT) 4. Loops at 0x18");
$display("(TT) --------------------------------------------------");
load_program("tb_out/04-lui.bin");
hard_reset();
for (i=0; i<16; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h",
FD_disasm_opcode, UUT.FD_PC, UUT.RF.data[1]);
@(posedge clk_tb);
end
end
endtask
task run_test5;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 5: JAL/JALR Test ");
$display("(TT) 1. Waveform must be inspected");
$display("(TT) 2. PC=00,0C,18,10,1C,14,0C,18,10,1C,...");
$display("(TT) 3. x1=XX,XX,XX,10,10,14,20,20,10,10,...");
$display("(TT) --------------------------------------------------");
load_program("tb_out/05-jalr.bin");
hard_reset();
for (i=0; i<16; i=i+1) begin
$display("(TT) Opcode=%0s, FD_PC=0x%h, x1=0x%h",
FD_disasm_opcode, UUT.FD_PC, UUT.RF.data[1]);
@(posedge clk_tb);
end
end
endtask
task run_test6;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 6: CSRR Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/06-csrr.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test7;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 7: CSRWI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/07-csrwi.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test8;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 8: CSRW Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/08-csrw.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test9;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 9: CSRSI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/09-csrsi.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test10;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 10: CSRS Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/10-csrs.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test11;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 11: CSRCI Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/11-csrci.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test12;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 12: CSRC Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/12-csrc.bin");
hard_reset();
for (i=0; i<48; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test13;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 13: CSR Atomic Test ");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/13-csr.bin");
hard_reset();
for (i=0; i<12; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test14;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 14: Memory");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/14-mem.bin");
hard_reset();
for (i=0; i<80; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
task run_test15;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 15: Exception");
$display("(TT) 1. On failure, a message is displayed");
$display("(TT) 2. Failure vector is PC=0x10");
$display("(TT) --------------------------------------------------");
load_program("tb_out/15-exception.bin");
hard_reset();
for (i=0; i<256; i=i+1) begin
if (UUT.FD_PC == 32'h10 || FD_disasm_opcode == "ILLEGAL ")
$display("(TT) Test failed!");
@(posedge clk_tb);
end
end
endtask
assign im_data_tb = instruction_memory_tb[im_addr_out_tb[11:2]];
assign io_data_read_tb = io_memory_tb[io_addr_tb[7:2]];
mmu MMU0(.clk(clk_tb), .resetb(resetb_tb), .dm_we(dm_we_tb),
.im_addr(im_addr_tb), .im_do(im_do_tb),
.dm_addr(dm_addr_tb), .dm_di(dm_di_tb),
.dm_do(dm_do_tb), .dm_be(dm_be_tb),
.is_signed(dm_is_signed_tb),
.im_addr_out(im_addr_out_tb), .im_data(im_data_tb),
.io_addr(io_addr_tb), .io_en(io_en_tb), .io_we(io_we_tb),
.io_data_read(io_data_read_tb), .io_data_write(io_data_write_tb)
);
core UUT
(
.clk(clk_tb), .resetb(resetb_tb),
.dm_we(dm_we_tb), .im_addr(im_addr_tb),
.im_do(im_do_tb), .dm_addr(dm_addr_tb),
.dm_di(dm_di_tb), .dm_do(dm_do_tb),
.dm_be(dm_be_tb), .dm_is_signed(dm_is_signed_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/core_tb.vcd");
$dumpvars(0,core_tb);
for (i = 0; i < 256; i = i + 1) begin
io_memory_tb[i] = 4096 + i;
end
@(posedge clk_tb);
run_test0();
run_test1();
run_test2();
run_test3();
run_test4();
run_test5();
run_test6();
run_test7();
run_test8();
run_test9();
run_test10();
run_test11();
run_test12();
run_test13();
run_test14();
run_test15();
$finish;
end
endmodule | 31 |
5,621 | data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v | 114,498,561 | mmu_tb.v | v | 278 | 96 | [] | [] | [] | null | line:39: before: "resetb_tb" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_tb = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #5 clk_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:39: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:47: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:50: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:53: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:56: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:63: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:68: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:73: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:78: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:100: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:108: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:111: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:118: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:123: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:144: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:152: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:159: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:181: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:186: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:210: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:218: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:228: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n #0;\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:253: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_log/mmu_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:254: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,mmu_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/mmu_tb.v:263: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: Exiting due to 25 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,354 | module | module mmu_tb();
reg clk_tb, resetb_tb, dm_we_tb;
reg [31:0] im_addr_tb, dm_addr_tb, dm_di_tb;
wire [31:0] im_do_tb, dm_do_tb;
reg [3:0] dm_be_tb;
reg is_signed_tb;
wire [11:2] im_addr_out_tb;
wire [31:0] im_data_tb, io_data_read_tb, io_data_write_tb;
wire [7:0] io_addr_tb;
wire io_en_tb, io_we_tb;
reg [31:0] instruction_memory [0:4095];
reg [31:0] io_memory [0:255];
integer i;
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Byte R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned bytes");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 4*i + 0;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
dm_be_tb = 4'b0010;
dm_di_tb = 4*i + 1;
@(posedge clk_tb);
dm_be_tb = 4'b0100;
dm_di_tb = 4*i + 2;
@(posedge clk_tb);
dm_be_tb = 4'b1000;
dm_di_tb = 4*i + 3;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0010;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1000;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Half Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned half words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 2*i + 0;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
dm_be_tb = 4'b1100;
dm_di_tb = 2*i + 1;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test3;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 3: Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test4;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 4: Read Instruction Memory ");
$display("(TT) 1. Reads words from 0x0000000, 0x0000004, ...");
$display("(TT) 2. Pipelined. Should read 4095, 4094, ...");
$display("(TT) 3. The first read is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
im_addr_tb = 32'h0 + i*4;
@(posedge clk_tb);
$display("(TT) im_addr = 0x%h, im_do(prev) = %d",
im_addr_tb, im_do_tb);
#0;
end
end
endtask
task run_test5;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 5: IO R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x80000000, ... consecutively in unsigned words");
$display("(TT) 2. The IO port should pipeline output the written values");
$display("(TT) 3. Then IO port is read");
$display("(TT) 4. IO port should read 4096, 4097, ...");
$display("(TT) 5. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) io_we = %b, io_addr = 0x%h, io_data_write = 0x%h",
io_we_tb, io_addr_tb, io_data_write_tb);
#0;
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
assign im_data_tb = instruction_memory[im_addr_out_tb[11:2]];
assign io_data_read_tb = io_memory[io_addr_tb[7:2]];
mmu UUT(.clk(clk_tb), .resetb(resetb_tb), .dm_we(dm_we_tb),
.im_addr(im_addr_tb), .im_do(im_do_tb),
.dm_addr(dm_addr_tb), .dm_di(dm_di_tb),
.dm_do(dm_do_tb), .dm_be(dm_be_tb),
.is_signed(is_signed_tb),
.im_addr_out(im_addr_out_tb), .im_data(im_data_tb),
.io_addr(io_addr_tb), .io_en(io_en_tb), .io_we(io_we_tb),
.io_data_read(io_data_read_tb), .io_data_write(io_data_write_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/mmu_tb.vcd");
$dumpvars(0,mmu_tb);
for (i = 0; i < 4096; i = i + 1) begin
instruction_memory[i] = 4095 - i;
end
for (i = 0; i < 256; i = i + 1) begin
io_memory[i] = 4096 + i;
end
@(posedge clk_tb);
run_test1();
run_test2();
run_test3();
run_test4();
run_test5();
$finish;
end
endmodule | module mmu_tb(); |
reg clk_tb, resetb_tb, dm_we_tb;
reg [31:0] im_addr_tb, dm_addr_tb, dm_di_tb;
wire [31:0] im_do_tb, dm_do_tb;
reg [3:0] dm_be_tb;
reg is_signed_tb;
wire [11:2] im_addr_out_tb;
wire [31:0] im_data_tb, io_data_read_tb, io_data_write_tb;
wire [7:0] io_addr_tb;
wire io_en_tb, io_we_tb;
reg [31:0] instruction_memory [0:4095];
reg [31:0] io_memory [0:255];
integer i;
always begin : CLK_GENERATOR
#5 clk_tb = 1'b0;
#5 clk_tb = 1'b1;
end
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Byte R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned bytes");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 4*i + 0;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
dm_be_tb = 4'b0010;
dm_di_tb = 4*i + 1;
@(posedge clk_tb);
dm_be_tb = 4'b0100;
dm_di_tb = 4*i + 2;
@(posedge clk_tb);
dm_be_tb = 4'b1000;
dm_di_tb = 4*i + 3;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0001;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0010;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b0100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1000;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Half Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned half words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = 2*i + 0;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
dm_be_tb = 4'b1100;
dm_di_tb = 2*i + 1;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b0011;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
dm_be_tb = 4'b1100;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test3;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 3: Word R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x10000000, ... consecutively in unsigned words");
$display("(TT) 2. Then reads from the same addresses. Values should be same");
$display("(TT) 3. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h10000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
task run_test4;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 4: Read Instruction Memory ");
$display("(TT) 1. Reads words from 0x0000000, 0x0000004, ...");
$display("(TT) 2. Pipelined. Should read 4095, 4094, ...");
$display("(TT) 3. The first read is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
im_addr_tb = 32'h0 + i*4;
@(posedge clk_tb);
$display("(TT) im_addr = 0x%h, im_do(prev) = %d",
im_addr_tb, im_do_tb);
#0;
end
end
endtask
task run_test5;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 5: IO R/W ");
$display("(TT) 1. Writes 0, 1, ... to 0x80000000, ... consecutively in unsigned words");
$display("(TT) 2. The IO port should pipeline output the written values");
$display("(TT) 3. Then IO port is read");
$display("(TT) 4. IO port should read 4096, 4097, ...");
$display("(TT) 5. The first dm_do(prev) is invalid");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
dm_we_tb = 1'b0;
is_signed_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
dm_we_tb = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_di_tb = i;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) io_we = %b, io_addr = 0x%h, io_data_write = 0x%h",
io_we_tb, io_addr_tb, io_data_write_tb);
#0;
end
dm_we_tb = 1'b0;
for (i = 0; i < 8; i = i + 1) begin
dm_addr_tb = 32'h80000000 + i*4;
dm_be_tb = 4'b1111;
@(posedge clk_tb);
$display("(TT) dm_addr = 0x%h, dm_be = %b, dm_do(prev) = %d",
dm_addr_tb, dm_be_tb, dm_do_tb);
#0;
end
end
endtask
assign im_data_tb = instruction_memory[im_addr_out_tb[11:2]];
assign io_data_read_tb = io_memory[io_addr_tb[7:2]];
mmu UUT(.clk(clk_tb), .resetb(resetb_tb), .dm_we(dm_we_tb),
.im_addr(im_addr_tb), .im_do(im_do_tb),
.dm_addr(dm_addr_tb), .dm_di(dm_di_tb),
.dm_do(dm_do_tb), .dm_be(dm_be_tb),
.is_signed(is_signed_tb),
.im_addr_out(im_addr_out_tb), .im_data(im_data_tb),
.io_addr(io_addr_tb), .io_en(io_en_tb), .io_we(io_we_tb),
.io_data_read(io_data_read_tb), .io_data_write(io_data_write_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/mmu_tb.vcd");
$dumpvars(0,mmu_tb);
for (i = 0; i < 4096; i = i + 1) begin
instruction_memory[i] = 4095 - i;
end
for (i = 0; i < 256; i = i + 1) begin
io_memory[i] = 4096 + i;
end
@(posedge clk_tb);
run_test1();
run_test2();
run_test3();
run_test4();
run_test5();
$finish;
end
endmodule | 31 |
5,622 | data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v | 114,498,561 | csr_ehu.v | v | 221 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:28: Cannot find include file: core/csrlist.vh\n`include "core/csrlist.vh" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core,data/full_repos/permissive/114498561/core/csrlist.vh\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core,data/full_repos/permissive/114498561/core/csrlist.vh.v\n data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core,data/full_repos/permissive/114498561/core/csrlist.vh.sv\n core/csrlist.vh\n core/csrlist.vh.v\n core/csrlist.vh.sv\n obj_dir/core/csrlist.vh\n obj_dir/core/csrlist.vh.v\n obj_dir/core/csrlist.vh.sv\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:106: Define or directive not defined: \'`CSR_MVENDORID\'\n `CSR_MVENDORID: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:106: syntax error, unexpected \':\', expecting endcase\n `CSR_MVENDORID: begin\n ^\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:109: Define or directive not defined: \'`CSR_MARCHID\'\n `CSR_MARCHID: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:109: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MARCHID: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:112: Define or directive not defined: \'`CSR_MIMPID\'\n `CSR_MIMPID: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:112: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MIMPID: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:115: Define or directive not defined: \'`CSR_MHARTID\'\n `CSR_MHARTID: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:115: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MHARTID: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:118: Define or directive not defined: \'`CSR_MISA\'\n `CSR_MISA: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:118: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MISA: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:122: Define or directive not defined: \'`CSR_MTVEC\'\n `CSR_MTVEC: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:122: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MTVEC: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:126: Define or directive not defined: \'`CSR_MSCRATCH\'\n `CSR_MSCRATCH: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:126: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MSCRATCH: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:132: Define or directive not defined: \'`CSR_MEPC\'\n `CSR_MEPC: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:132: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MEPC: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:138: Define or directive not defined: \'`CSR_MCAUSE\'\n `CSR_MCAUSE: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:138: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MCAUSE: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:144: Define or directive not defined: \'`CSR_MTVAL\'\n `CSR_MTVAL: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:144: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MTVAL: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:150: Define or directive not defined: \'`CSR_MCYCLE\'\n `CSR_MCYCLE: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:150: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MCYCLE: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:156: Define or directive not defined: \'`CSR_MINSTRET\'\n `CSR_MINSTRET: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:156: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MINSTRET: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:162: Define or directive not defined: \'`CSR_MCYCLEH\'\n `CSR_MCYCLEH: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:162: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MCYCLEH: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:168: Define or directive not defined: \'`CSR_MINSTRETH\'\n `CSR_MINSTRETH: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:168: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `CSR_MINSTRETH: begin\n ^~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:174: syntax error, unexpected default\n default: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:204: syntax error, unexpected <=, expecting IDENTIFIER\n mcause <= 32\'d0;\n ^~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:208: syntax error, unexpected <=, expecting IDENTIFIER\n mcause <= 32\'d2;\n ^~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:211: syntax error, unexpected <=, expecting IDENTIFIER\n mcause <= 32\'d4;\n ^~\n%Error: data/full_repos/permissive/114498561/01-embedded-softcore-rv32i/core/csr_ehu.v:214: syntax error, unexpected <=, expecting IDENTIFIER\n mcause <= 32\'d6;\n ^~\n%Error: Cannot continue\n' | 6,360 | module | module csr_ehu
(
clk, resetb, XB_bubble,
read, write, set, clear, imm, a_rd,
initiate_illinst, initiate_misaligned,
XB_FD_exception_unsupported_category,
XB_FD_exception_illegal_instruction,
XB_FD_exception_instruction_misaligned,
XB_FD_exception_load_misaligned,
XB_FD_exception_store_misaligned,
src_dst, d_rs1, uimm, FD_pc, XB_pc, data_out, csr_mepc
);
`include "core/csrlist.vh"
input wire clk, resetb, XB_bubble;
input wire read, write, set, clear, imm;
input wire [4:0] a_rd;
input wire [11:0] src_dst;
input wire [31:0] FD_pc, XB_pc, d_rs1;
input wire [4:0] uimm;
input wire XB_FD_exception_unsupported_category;
input wire XB_FD_exception_illegal_instruction;
input wire XB_FD_exception_instruction_misaligned;
input wire XB_FD_exception_load_misaligned;
input wire XB_FD_exception_store_misaligned;
output reg [31:0] data_out;
output reg initiate_illinst, initiate_misaligned;
output wire [31:0] csr_mepc;
reg XB_exception_illegal_instruction;
reg [31:0] mepc;
reg [31:0] mscratch, mcause, mtval;
reg [63:0] mcycle, minstret;
wire initiate_exception;
wire FD_exception, XB_exception;
assign FD_exception = XB_FD_exception_unsupported_category |
XB_FD_exception_illegal_instruction |
XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned;
assign XB_exception = XB_exception_illegal_instruction;
assign initiate_exception = XB_exception | FD_exception;
assign csr_mepc = mepc;
always @ (*) begin : EXCEPTION_HANDLING_UNIT
initiate_illinst
= ~XB_bubble & (XB_exception_illegal_instruction |
XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category);
initiate_misaligned
= ~XB_bubble & (XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned);
end
wire [31:0] operand;
assign operand = imm ? {27'b0, uimm} : d_rs1;
wire really_read, really_write, really_set, really_clear;
assign really_read = read && (a_rd != 5'b0);
assign really_write = write && !(imm && uimm == 5'b0);
assign really_set = set && (uimm != 5'b0);
assign really_clear = clear && (uimm != 5'b0);
always @ (posedge clk, negedge resetb) begin : CSR_PIPELINE
if (!resetb) begin
mcycle <= 64'b0;
minstret <= 64'b0;
mepc <= 32'bX;
data_out <= 32'bX;
end
else if (clk) begin
XB_exception_illegal_instruction = 1'b0;
mcycle <= mcycle + 64'b1;
if (!XB_bubble) begin
minstret <= minstret + 64'b1;
end
case (src_dst)
`CSR_MVENDORID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MARCHID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MIMPID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MHARTID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MISA: begin
if (really_read) data_out <= 32'b0100_0000_0000_0000_0000_0001_0000_0000;
end
`CSR_MTVEC: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MSCRATCH: begin
if (really_read) data_out <= mscratch;
if (really_write) mscratch <= operand;
if (really_set) mscratch <= mscratch | operand;
if (really_clear) mscratch <= mscratch & ~operand;
end
`CSR_MEPC: begin
if (really_read) data_out <= mepc;
if (really_write) mepc <= operand;
if (really_set) mepc <= mepc | operand;
if (really_clear) mepc <= mepc & ~operand;
end
`CSR_MCAUSE: begin
if (really_read) data_out <= mcause;
if (really_write) mcause <= operand;
if (really_set) mcause <= mcause | operand;
if (really_clear) mcause <= mcause & ~operand;
end
`CSR_MTVAL: begin
if (really_read) data_out <= mtval;
if (really_write) mtval <= operand;
if (really_set) mtval <= mtval | operand;
if (really_clear) mtval <= mtval & ~operand;
end
`CSR_MCYCLE: begin
if (really_read) data_out <= mcycle[0+:32];
if (really_write) mcycle[0+:32] <= operand;
if (really_set) mcycle[0+:32] <= mcycle[0+:32] | operand;
if (really_clear) mcycle[0+:32] <= mcycle[0+:32] & ~operand;
end
`CSR_MINSTRET: begin
if (really_read) data_out <= minstret[0+:32];
if (really_write) minstret[0+:32] <= operand;
if (really_set) minstret[0+:32] <= minstret[0+:32] | operand;
if (really_clear) minstret[0+:32] <= minstret[0+:32] & ~operand;
end
`CSR_MCYCLEH: begin
if (really_read) data_out <= mcycle[32+:32];
if (really_write) mcycle[32+:32] <= operand;
if (really_set) mcycle[32+:32] <= mcycle[32+:32] | operand;
if (really_clear) mcycle[32+:32] <= mcycle[32+:32] & ~operand;
end
`CSR_MINSTRETH: begin
if (really_read) data_out <= minstret[32+:32];
if (really_write) minstret[32+:32] <= operand;
if (really_set) minstret[32+:32] <= minstret[32+:32] | operand;
if (really_clear) minstret[32+:32] <= minstret[32+:32] & ~operand;
end
default: begin
if (src_dst[11:4] == 8'hB0 ||
src_dst[11:4] == 8'hB1 ||
src_dst[11:4] == 8'hB8 ||
src_dst[11:4] == 8'hB9 ||
src_dst[11:4] == 8'h32 ||
src_dst[11:4] == 8'h33
) begin : PERFORMANCE_MONITORS
data_out <= 32'b0;
end
else begin
if (~XB_bubble & (read|write|set|clear))
XB_exception_illegal_instruction = 1'b1;
end
end
endcase
if (XB_exception) begin
mepc <= FD_pc;
mcause <= 32'd2;
end
else if (FD_exception) begin
mepc <= XB_pc;
if (XB_FD_exception_instruction_misaligned) begin
mcause <= 32'd0;
end
else if (XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category) begin
mcause <= 32'd2;
end
else if (XB_FD_exception_load_misaligned) begin
mcause <= 32'd4;
end
else if (XB_FD_exception_store_misaligned) begin
mcause <= 32'd6;
end
end
end
end
endmodule | module csr_ehu
(
clk, resetb, XB_bubble,
read, write, set, clear, imm, a_rd,
initiate_illinst, initiate_misaligned,
XB_FD_exception_unsupported_category,
XB_FD_exception_illegal_instruction,
XB_FD_exception_instruction_misaligned,
XB_FD_exception_load_misaligned,
XB_FD_exception_store_misaligned,
src_dst, d_rs1, uimm, FD_pc, XB_pc, data_out, csr_mepc
); |
`include "core/csrlist.vh"
input wire clk, resetb, XB_bubble;
input wire read, write, set, clear, imm;
input wire [4:0] a_rd;
input wire [11:0] src_dst;
input wire [31:0] FD_pc, XB_pc, d_rs1;
input wire [4:0] uimm;
input wire XB_FD_exception_unsupported_category;
input wire XB_FD_exception_illegal_instruction;
input wire XB_FD_exception_instruction_misaligned;
input wire XB_FD_exception_load_misaligned;
input wire XB_FD_exception_store_misaligned;
output reg [31:0] data_out;
output reg initiate_illinst, initiate_misaligned;
output wire [31:0] csr_mepc;
reg XB_exception_illegal_instruction;
reg [31:0] mepc;
reg [31:0] mscratch, mcause, mtval;
reg [63:0] mcycle, minstret;
wire initiate_exception;
wire FD_exception, XB_exception;
assign FD_exception = XB_FD_exception_unsupported_category |
XB_FD_exception_illegal_instruction |
XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned;
assign XB_exception = XB_exception_illegal_instruction;
assign initiate_exception = XB_exception | FD_exception;
assign csr_mepc = mepc;
always @ (*) begin : EXCEPTION_HANDLING_UNIT
initiate_illinst
= ~XB_bubble & (XB_exception_illegal_instruction |
XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category);
initiate_misaligned
= ~XB_bubble & (XB_FD_exception_instruction_misaligned |
XB_FD_exception_load_misaligned |
XB_FD_exception_store_misaligned);
end
wire [31:0] operand;
assign operand = imm ? {27'b0, uimm} : d_rs1;
wire really_read, really_write, really_set, really_clear;
assign really_read = read && (a_rd != 5'b0);
assign really_write = write && !(imm && uimm == 5'b0);
assign really_set = set && (uimm != 5'b0);
assign really_clear = clear && (uimm != 5'b0);
always @ (posedge clk, negedge resetb) begin : CSR_PIPELINE
if (!resetb) begin
mcycle <= 64'b0;
minstret <= 64'b0;
mepc <= 32'bX;
data_out <= 32'bX;
end
else if (clk) begin
XB_exception_illegal_instruction = 1'b0;
mcycle <= mcycle + 64'b1;
if (!XB_bubble) begin
minstret <= minstret + 64'b1;
end
case (src_dst)
`CSR_MVENDORID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MARCHID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MIMPID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MHARTID: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MISA: begin
if (really_read) data_out <= 32'b0100_0000_0000_0000_0000_0001_0000_0000;
end
`CSR_MTVEC: begin
if (really_read) data_out <= 32'b0;
end
`CSR_MSCRATCH: begin
if (really_read) data_out <= mscratch;
if (really_write) mscratch <= operand;
if (really_set) mscratch <= mscratch | operand;
if (really_clear) mscratch <= mscratch & ~operand;
end
`CSR_MEPC: begin
if (really_read) data_out <= mepc;
if (really_write) mepc <= operand;
if (really_set) mepc <= mepc | operand;
if (really_clear) mepc <= mepc & ~operand;
end
`CSR_MCAUSE: begin
if (really_read) data_out <= mcause;
if (really_write) mcause <= operand;
if (really_set) mcause <= mcause | operand;
if (really_clear) mcause <= mcause & ~operand;
end
`CSR_MTVAL: begin
if (really_read) data_out <= mtval;
if (really_write) mtval <= operand;
if (really_set) mtval <= mtval | operand;
if (really_clear) mtval <= mtval & ~operand;
end
`CSR_MCYCLE: begin
if (really_read) data_out <= mcycle[0+:32];
if (really_write) mcycle[0+:32] <= operand;
if (really_set) mcycle[0+:32] <= mcycle[0+:32] | operand;
if (really_clear) mcycle[0+:32] <= mcycle[0+:32] & ~operand;
end
`CSR_MINSTRET: begin
if (really_read) data_out <= minstret[0+:32];
if (really_write) minstret[0+:32] <= operand;
if (really_set) minstret[0+:32] <= minstret[0+:32] | operand;
if (really_clear) minstret[0+:32] <= minstret[0+:32] & ~operand;
end
`CSR_MCYCLEH: begin
if (really_read) data_out <= mcycle[32+:32];
if (really_write) mcycle[32+:32] <= operand;
if (really_set) mcycle[32+:32] <= mcycle[32+:32] | operand;
if (really_clear) mcycle[32+:32] <= mcycle[32+:32] & ~operand;
end
`CSR_MINSTRETH: begin
if (really_read) data_out <= minstret[32+:32];
if (really_write) minstret[32+:32] <= operand;
if (really_set) minstret[32+:32] <= minstret[32+:32] | operand;
if (really_clear) minstret[32+:32] <= minstret[32+:32] & ~operand;
end
default: begin
if (src_dst[11:4] == 8'hB0 ||
src_dst[11:4] == 8'hB1 ||
src_dst[11:4] == 8'hB8 ||
src_dst[11:4] == 8'hB9 ||
src_dst[11:4] == 8'h32 ||
src_dst[11:4] == 8'h33
) begin : PERFORMANCE_MONITORS
data_out <= 32'b0;
end
else begin
if (~XB_bubble & (read|write|set|clear))
XB_exception_illegal_instruction = 1'b1;
end
end
endcase
if (XB_exception) begin
mepc <= FD_pc;
mcause <= 32'd2;
end
else if (FD_exception) begin
mepc <= XB_pc;
if (XB_FD_exception_instruction_misaligned) begin
mcause <= 32'd0;
end
else if (XB_FD_exception_illegal_instruction |
XB_FD_exception_unsupported_category) begin
mcause <= 32'd2;
end
else if (XB_FD_exception_load_misaligned) begin
mcause <= 32'd4;
end
else if (XB_FD_exception_store_misaligned) begin
mcause <= 32'd6;
end
end
end
end
endmodule | 31 |
5,624 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/board_top.v | 114,498,561 | board_top.v | v | 15 | 58 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/board_top.v:9: Cannot find file containing module: 'SB_GB'\n SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/SB_GB\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/SB_GB.v\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/SB_GB.sv\n SB_GB\n SB_GB.v\n SB_GB.sv\n obj_dir/SB_GB\n obj_dir/SB_GB.v\n obj_dir/SB_GB.sv\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/board_top.v:12: Cannot find file containing module: 'cpu_top'\n cpu_top U0(.clk(clk), .resetb(resetb), .gpio0(gpio0));\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 6,364 | module | module board_top
(
input wire clki,
input wire resetb,
output wire [7:0] gpio0
);
wire clk;
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
.GLOBAL_BUFFER_OUTPUT(clk));
cpu_top U0(.clk(clk), .resetb(resetb), .gpio0(gpio0));
endmodule | module board_top
(
input wire clki,
input wire resetb,
output wire [7:0] gpio0
); |
wire clk;
SB_GB clk_gb(.USER_SIGNAL_TO_GLOBAL_BUFFER(clki),
.GLOBAL_BUFFER_OUTPUT(clk));
cpu_top U0(.clk(clk), .resetb(resetb), .gpio0(gpio0));
endmodule | 31 |
5,626 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v | 114,498,561 | core_top.v | v | 55 | 61 | [] | [] | [] | [(4, 54)] | null | null | 1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v:31: Cannot find file containing module: 'core'\ncore CPU0\n^~~~\n ... Looked in:\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core.v\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core.sv\n core\n core.v\n core.sv\n obj_dir/core\n obj_dir/core.v\n obj_dir/core.sv\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/core_top.v:40: Cannot find file containing module: 'mmu'\nmmu MMU0\n^~~\n%Error: Exiting due to 2 error(s)\n" | 6,367 | module | module core_top
(
input wire clk,
input wire resetb,
output wire [7:0] io_addr,
output wire io_en,
output wire io_we,
input wire [31:0] io_data_read,
output wire [31:0] io_data_write,
input wire irq_mtimecmp
);
wire dm_we;
wire [31:0] im_addr;
wire [31:0] im_do;
wire [31:0] dm_addr;
wire [31:0] dm_di;
wire [31:0] dm_do;
wire [3:0] dm_be;
wire dm_is_signed;
core CPU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .dm_is_signed(dm_is_signed),
.irq_mtimecmp(irq_mtimecmp)
);
mmu MMU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we),
.im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .is_signed(dm_is_signed),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write)
);
endmodule | module core_top
(
input wire clk,
input wire resetb,
output wire [7:0] io_addr,
output wire io_en,
output wire io_we,
input wire [31:0] io_data_read,
output wire [31:0] io_data_write,
input wire irq_mtimecmp
); |
wire dm_we;
wire [31:0] im_addr;
wire [31:0] im_do;
wire [31:0] dm_addr;
wire [31:0] dm_di;
wire [31:0] dm_do;
wire [3:0] dm_be;
wire dm_is_signed;
core CPU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we), .im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .dm_is_signed(dm_is_signed),
.irq_mtimecmp(irq_mtimecmp)
);
mmu MMU0
(
.clk(clk), .resetb(resetb),
.dm_we(dm_we),
.im_addr(im_addr), .im_do(im_do),
.dm_addr(dm_addr), .dm_di(dm_di), .dm_do(dm_do),
.dm_be(dm_be), .is_signed(dm_is_signed),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write)
);
endmodule | 31 |
5,627 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/cpu_top.v | 114,498,561 | cpu_top.v | v | 36 | 66 | [] | [] | [] | [(4, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/cpu_top.v:17: Cannot find file containing module: 'core_top'\n core_top CT0 \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core_top\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core_top.v\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/core_top.sv\n core_top\n core_top.v\n core_top.sv\n obj_dir/core_top\n obj_dir/core_top.v\n obj_dir/core_top.sv\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/cpu_top.v:25: Cannot find file containing module: 'io_port'\n io_port IO0\n ^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 6,369 | module | module cpu_top
(
input wire clk,
input wire resetb,
output wire [7:0] gpio0
);
wire [7:0] io_addr;
wire io_en, io_we;
wire [31:0] io_data_read;
wire [31:0] io_data_write;
wire irq_mtimecmp;
core_top CT0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp)
);
io_port IO0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp),
.gpio0(gpio0)
);
endmodule | module cpu_top
(
input wire clk,
input wire resetb,
output wire [7:0] gpio0
); |
wire [7:0] io_addr;
wire io_en, io_we;
wire [31:0] io_data_read;
wire [31:0] io_data_write;
wire irq_mtimecmp;
core_top CT0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp)
);
io_port IO0
(
.clk(clk), .resetb(resetb),
.io_addr(io_addr), .io_en(io_en), .io_we(io_we),
.io_data_read(io_data_read), .io_data_write(io_data_write),
.irq_mtimecmp(irq_mtimecmp),
.gpio0(gpio0)
);
endmodule | 31 |
5,628 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/EBRAM_ROM.v | 114,498,561 | EBRAM_ROM.v | v | 25 | 59 | [] | [] | [] | [(4, 24)] | null | data/verilator_xmls/07a62f47-0e0b-4460-9152-f32b61f866bf.xml | null | 6,370 | module | module EBRAM_ROM(
clk,
addra, douta, addrb, doutb
);
parameter
DEPTH = 512,
DEPTH_LOG = 9,
WIDTH = 32;
input wire clk;
input wire [DEPTH_LOG-1:0] addra, addrb;
output reg [WIDTH-1:0] douta, doutb;
reg [WIDTH-1:0] ROM [DEPTH-1:0];
always @ (posedge clk) begin
douta <= ROM[addra];
doutb <= ROM[addrb];
end
endmodule | module EBRAM_ROM(
clk,
addra, douta, addrb, doutb
); |
parameter
DEPTH = 512,
DEPTH_LOG = 9,
WIDTH = 32;
input wire clk;
input wire [DEPTH_LOG-1:0] addra, addrb;
output reg [WIDTH-1:0] douta, doutb;
reg [WIDTH-1:0] ROM [DEPTH-1:0];
always @ (posedge clk) begin
douta <= ROM[addra];
doutb <= ROM[addrb];
end
endmodule | 31 |
5,629 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/io_port.v | 114,498,561 | io_port.v | v | 44 | 76 | [] | [] | [] | [(1, 43)] | null | null | 1: b"%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/io_port.v:36: Cannot find file containing module: 'timer'\n timer TIMER0\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer.v\n data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40,data/full_repos/permissive/114498561/timer.sv\n timer\n timer.v\n timer.sv\n obj_dir/timer\n obj_dir/timer.v\n obj_dir/timer.sv\n%Error: Exiting due to 1 error(s)\n" | 6,371 | module | module io_port
(
input wire clk,
input wire resetb,
input wire [7:0] io_addr,
input wire io_en,
input wire io_we,
input wire [31:0] io_data_write,
output wire [31:0] io_data_read,
output wire irq_mtimecmp,
output reg [7:0] gpio0
);
wire mtime_we;
wire [31:0] mtime_dout;
assign mtime_we = io_addr[7:4] == 4'b0001 ? io_we : 1'b0;
assign io_data_read = io_addr[7:4] == 4'b0001 ? mtime_dout : 32'bX;
always @ (posedge clk) begin : GPIO0
if (!resetb) begin
gpio0 <= 8'b0;
end
else if (clk) begin
if (io_addr[7:2] == 6'b0 && io_we) begin
gpio0 <= io_data_write[7:0];
end
end
end
timer TIMER0
(
.clk(clk), .resetb(resetb),
.io_addr_3_2(io_addr[3:2]), .io_we(mtime_we), .io_din(io_data_write),
.io_dout(mtime_dout), .irq_mtimecmp(irq_mtimecmp)
);
endmodule | module io_port
(
input wire clk,
input wire resetb,
input wire [7:0] io_addr,
input wire io_en,
input wire io_we,
input wire [31:0] io_data_write,
output wire [31:0] io_data_read,
output wire irq_mtimecmp,
output reg [7:0] gpio0
); |
wire mtime_we;
wire [31:0] mtime_dout;
assign mtime_we = io_addr[7:4] == 4'b0001 ? io_we : 1'b0;
assign io_data_read = io_addr[7:4] == 4'b0001 ? mtime_dout : 32'bX;
always @ (posedge clk) begin : GPIO0
if (!resetb) begin
gpio0 <= 8'b0;
end
else if (clk) begin
if (io_addr[7:2] == 6'b0 && io_we) begin
gpio0 <= io_data_write[7:0];
end
end
end
timer TIMER0
(
.clk(clk), .resetb(resetb),
.io_addr_3_2(io_addr[3:2]), .io_we(mtime_we), .io_din(io_data_write),
.io_dout(mtime_dout), .irq_mtimecmp(irq_mtimecmp)
);
endmodule | 31 |
5,632 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v | 114,498,561 | regfile_tb.v | v | 127 | 80 | [] | [] | [] | null | line:34: before: "resetb_tb" | null | 1: b'%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:34: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:54: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:76: syntax error, unexpected \'@\'\n @(posedge clk_tb) resetb_tb = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #0; \n ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:96: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:112: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb_log/regfile_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:113: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,regfile_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/regfile_tb.v:115: syntax error, unexpected \'@\'\n @(posedge clk_tb);\n ^\n%Error: Exiting due to 7 error(s), 2 warning(s)\n' | 6,375 | module | module regfile_tb(clk);
reg clk_tb, resetb_tb, we_rd_tb;
reg [4:0] a_rs1_tb, a_rs2_tb, a_rd_tb;
wire [31:0] d_rs1_tb, d_rs2_tb;
reg [31:0] d_rd_tb;
assign clk_tb = clk;
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Basic R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x31, x0, x1, ...");
$display("(TT) 3. RS2 reads x30, x31, x0, x1, ...");
$display("(TT) 4. RS1 should read X, 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
a_rd_tb = i;
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
a_rs1_tb = i - 1;
a_rs2_tb = i - 2;
#0;
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Forwarding R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x0, x1, ...");
$display("(TT) 3. RS2 reads x31, x0, x1, ...");
$display("(TT) 4. RS1 should read 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
a_rd_tb = i;
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
a_rs1_tb = i;
a_rs2_tb = i - 1;
#0;
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask
regfile UUT(
.clk(clk_tb), .resetb(resetb_tb),
.a_rs1(a_rs1_tb), .d_rs1(d_rs1_tb),
.a_rs2(a_rs2_tb), .d_rs2(d_rs2_tb),
.a_rd(a_rd_tb), .d_rd(d_rd_tb),
.we_rd(we_rd_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/regfile_tb.vcd");
$dumpvars(0,regfile_tb);
@(posedge clk_tb);
run_test1();
run_test2();
$finish;
end
endmodule | module regfile_tb(clk); |
reg clk_tb, resetb_tb, we_rd_tb;
reg [4:0] a_rs1_tb, a_rs2_tb, a_rd_tb;
wire [31:0] d_rs1_tb, d_rs2_tb;
reg [31:0] d_rd_tb;
assign clk_tb = clk;
task run_test1;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 1: Basic R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x31, x0, x1, ...");
$display("(TT) 3. RS2 reads x30, x31, x0, x1, ...");
$display("(TT) 4. RS1 should read X, 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
a_rd_tb = i;
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
a_rs1_tb = i - 1;
a_rs2_tb = i - 2;
#0;
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask
task run_test2;
integer i;
begin
$display("(TT) --------------------------------------------------");
$display("(TT) Test 2: Forwarding R/W ");
$display("(TT) 1. Writes 32, 31, ... to x0, x1, ... consecutively");
$display("(TT) 2. RS1 reads x0, x1, ...");
$display("(TT) 3. RS2 reads x31, x0, x1, ...");
$display("(TT) 4. RS1 should read 0, 31, 30, ...");
$display("(TT) 5. RS2 should read X, 0, 31, 30, ...");
$display("(TT) 6. No stray value should remain");
$display("(TT) --------------------------------------------------");
resetb_tb = 1'b0;
we_rd_tb = 1'b0;
@(posedge clk_tb) resetb_tb = 1'b1;
for (i = 0; i < 40; i = i + 1) begin
a_rd_tb = i;
d_rd_tb = 32 - i%32;
we_rd_tb = 1'b1;
a_rs1_tb = i;
a_rs2_tb = i - 1;
#0;
$display("(TT) a_rd = x%d, d_rd = %d, we_rd = %d",
a_rd_tb, d_rd_tb, we_rd_tb);
$display("(TT) a_rs1 = x%d, d_rs1 = %d",
a_rs1_tb, d_rs1_tb);
$display("(TT) a_rs2 = x%d, d_rs2 = %d",
a_rs2_tb, d_rs2_tb);
$display("");
@(posedge clk_tb);
end
end
endtask
regfile UUT(
.clk(clk_tb), .resetb(resetb_tb),
.a_rs1(a_rs1_tb), .d_rs1(d_rs1_tb),
.a_rs2(a_rs2_tb), .d_rs2(d_rs2_tb),
.a_rd(a_rd_tb), .d_rd(d_rd_tb),
.we_rd(we_rd_tb)
);
initial
begin : RUN_ALL_TESTS
$dumpfile("tb_log/regfile_tb.vcd");
$dumpvars(0,regfile_tb);
@(posedge clk_tb);
run_test1();
run_test2();
$finish;
end
endmodule | 31 |
5,636 | data/full_repos/permissive/114498561/02-rv32i-pipeline-ice40/timer.v | 114,498,561 | timer.v | v | 59 | 60 | [] | [] | [] | [(8, 58)] | null | data/verilator_xmls/805a7f00-1418-4020-8068-154a7cbdf702.xml | null | 6,380 | module | module timer(
input wire clk,
input wire resetb,
input wire [3:2] io_addr_3_2,
input wire io_we,
input wire [31:0] io_din,
output wire [31:0] io_dout,
output reg irq_mtimecmp
);
reg [63:0] mtime;
reg [63:0] mtimecmp;
always @ (posedge clk) begin : TIMER_PIPELINE
if (!resetb) begin
mtime <= 64'b0;
mtimecmp <= 64'b0;
irq_mtimecmp <= 1'b0;
end
else if (clk) begin
mtime <= mtime + 1;
if (io_we) begin
case (io_addr_3_2[3:2])
2'b00: mtime[0+:32] <= io_din;
2'b01: mtime[32+:32] <= io_din;
2'b10: begin
mtimecmp[0+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
2'b11: begin
mtimecmp[32+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
endcase
end
if (mtime == mtimecmp) begin
irq_mtimecmp <= 1'b1;
end
end
end
assign io_dout =
io_addr_3_2[3]
? ( io_addr_3_2[2] ? mtimecmp[32+:32] : mtimecmp[0+:32] )
: ( io_addr_3_2[2] ? mtime[32+:32] : mtime[0+:32] );
endmodule | module timer(
input wire clk,
input wire resetb,
input wire [3:2] io_addr_3_2,
input wire io_we,
input wire [31:0] io_din,
output wire [31:0] io_dout,
output reg irq_mtimecmp
); |
reg [63:0] mtime;
reg [63:0] mtimecmp;
always @ (posedge clk) begin : TIMER_PIPELINE
if (!resetb) begin
mtime <= 64'b0;
mtimecmp <= 64'b0;
irq_mtimecmp <= 1'b0;
end
else if (clk) begin
mtime <= mtime + 1;
if (io_we) begin
case (io_addr_3_2[3:2])
2'b00: mtime[0+:32] <= io_din;
2'b01: mtime[32+:32] <= io_din;
2'b10: begin
mtimecmp[0+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
2'b11: begin
mtimecmp[32+:32] <= io_din;
irq_mtimecmp <= 1'b0;
end
endcase
end
if (mtime == mtimecmp) begin
irq_mtimecmp <= 1'b1;
end
end
end
assign io_dout =
io_addr_3_2[3]
? ( io_addr_3_2[2] ? mtimecmp[32+:32] : mtimecmp[0+:32] )
: ( io_addr_3_2[2] ? mtime[32+:32] : mtime[0+:32] );
endmodule | 31 |
5,637 | data/full_repos/permissive/114519317/knowles32.v | 114,519,317 | knowles32.v | v | 408 | 81 | [] | [] | [] | null | line:87: before: "~|" | null | 1: b'%Error: data/full_repos/permissive/114519317/knowles32.v:21: Cannot find include file: ./components/input_PG_n.v\n`include "./components/input_PG_n.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/./components/input_PG_n.v\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/./components/input_PG_n.v.v\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/./components/input_PG_n.v.sv\n ./components/input_PG_n.v\n ./components/input_PG_n.v.v\n ./components/input_PG_n.v.sv\n obj_dir/./components/input_PG_n.v\n obj_dir/./components/input_PG_n.v.v\n obj_dir/./components/input_PG_n.v.sv\n%Error: data/full_repos/permissive/114519317/knowles32.v:22: Cannot find include file: ./components/PG_n.v\n`include "./components/PG_n.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114519317/knowles32.v:23: Cannot find include file: ./components/G_n.v\n`include "./components/G_n.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114519317/knowles32.v:24: Cannot find include file: ./components/n_PG.v\n`include "./components/n_PG.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114519317/knowles32.v:25: Cannot find include file: ./components/n_G.v\n`include "./components/n_G.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 6,387 | module | module knowles32
#(
parameter [31:0] KNOWLES_S2 = 2,
parameter [31:0] KNOWLES_S3 = 4,
parameter [31:0] KNOWLES_S4 = 8,
parameter [31:0] KNOWLES_S5 = 16
)
(
output Co,
output [32:1] S,
input [32:1] A,
input [32:1] B,
input Ci
);
genvar i;
wire [32:1] s0_P_n;
wire [32:0] s0_G_n;
generate
for (i = 32; i > 0; i=i-1) begin : s0_unknown
input_PG_n s0u (
.P_n(s0_P_n[i]),
.G_n(s0_G_n[i]),
.A(A[i]),
.B(B[i])
);
end
endgenerate
not (s0_G_n[0], Ci);
localparam S0_KNOWN = 0;
localparam S0_GROUP_SIZE = 1;
wire [31:1] s1_P;
wire [31:0] s1_G;
generate
for (i = 31; i > S0_KNOWN + S0_GROUP_SIZE; i=i-1) begin: s1_unknown
n_PG s1u (
.Pc(s1_P[i]),
.Gc(s1_G[i]),
.n_Pu(s0_P_n[i]),
.n_Gu(s0_G_n[i]),
.n_Pl(s0_P_n[(i-1)]),
.n_Gl(s0_G_n[(i-1)])
);
end
endgenerate
generate
for (i = S0_KNOWN + S0_GROUP_SIZE; i > S0_KNOWN; i=i-1) begin : s1_known
n_G s1k (
.Gc(s1_G[i]),
.n_Pu(s0_P_n[i]),
.n_Gu(s0_G_n[i]),
.n_Gl(s0_G_n[(i-1)])
);
end
endgenerate
not (s1_G[0], s0_G_n[0]);
localparam S1_KNOWN = 1;
localparam S1_GROUP_SIZE = 2;
wire [31:1] s2_P_n;
wire [31:0] s2_G_n;
generate
for (i = 31; i > S1_KNOWN + S1_GROUP_SIZE; i=i-1) begin : s2_unknown
PG_n s2u (
.Pc_n(s2_P_n[i]),
.Gc_n(s2_G_n[i]),
.Pu(s1_P[i]),
.Gu(s1_G[i]),
.Pl(s1_P[(i | KNOWLES_S2-1) - S1_GROUP_SIZE]),
.Gl(s1_G[(i | KNOWLES_S2-1) - S1_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S1_KNOWN + S1_GROUP_SIZE; i > S1_KNOWN; i=i-1) begin : s2_known
G_n s2k (
.Gc_n(s2_G_n[i]),
.Pu(s1_P[i]),
.Gu(s1_G[i]),
.Gl(s1_G[(i | KNOWLES_S2-1) - S1_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S1_KNOWN; i >= 0; i=i-1) begin : s2_prev_known
not s2pk (s2_G_n[i], s1_G[i]);
end
endgenerate
localparam S2_KNOWN = 3;
localparam S2_GROUP_SIZE = 4;
wire [31:1] s3_P;
wire [31:0] s3_G;
generate
for (i = 31; i > S2_KNOWN + S2_GROUP_SIZE; i=i-1) begin : s3_unknown
n_PG s3u (
.Pc(s3_P[i]),
.Gc(s3_G[i]),
.n_Pu(s2_P_n[i]),
.n_Gu(s2_G_n[i]),
.n_Pl(s2_P_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE]),
.n_Gl(s2_G_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S2_KNOWN + S2_GROUP_SIZE; i > S2_KNOWN; i=i-1) begin : s3_known
n_G s3k (
.Gc(s3_G[i]),
.n_Pu(s2_P_n[i]),
.n_Gu(s2_G_n[i]),
.n_Gl(s2_G_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S2_KNOWN; i >= 0; i=i-1) begin : s3_prev_known
not s3pk (s3_G[i], s2_G_n[i]);
end
endgenerate
localparam S3_KNOWN = 7;
localparam S3_GROUP_SIZE = 8;
wire [31:1] s4_P_n;
wire [31:0] s4_G_n;
generate
for (i = 31; i > S3_KNOWN + S3_GROUP_SIZE; i=i-1) begin : s4_unknown
PG_n s4u (
.Pc_n(s4_P_n[i]),
.Gc_n(s4_G_n[i]),
.Pu(s3_P[i]),
.Gu(s3_G[i]),
.Pl(s3_P[(i | KNOWLES_S4-1) - S3_GROUP_SIZE]),
.Gl(s3_G[(i | KNOWLES_S4-1) - S3_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S3_KNOWN + S3_GROUP_SIZE; i > S3_KNOWN; i=i-1) begin : s4_known
G_n s4k (
.Gc_n(s4_G_n[i]),
.Pu(s3_P[i]),
.Gu(s3_G[i]),
.Gl(s3_G[(i | KNOWLES_S4-1) - S3_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S3_KNOWN; i >= 0; i=i-1) begin : s4_prev_known
not s4pk (s4_G_n[i], s3_G[i]);
end
endgenerate
localparam S4_KNOWN = 15;
localparam S4_GROUP_SIZE = 16;
wire [31:1] s5_P;
wire [31:0] s5_G;
generate
for (i = 31; i > S4_KNOWN + S4_GROUP_SIZE; i=i-1) begin : s5_unknown
n_PG s5u (
.Pc(s5_P[i]),
.Gc(s5_G[i]),
.n_Pu(s4_P_n[i]),
.n_Gu(s4_G_n[i]),
.n_Pl(s4_P_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE]),
.n_Gl(s4_G_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S4_KNOWN + S4_GROUP_SIZE; i > S4_KNOWN; i=i-1) begin : s5_known
n_G s5k (
.Gc(s5_G[i]),
.n_Pu(s4_P_n[i]),
.n_Gu(s4_G_n[i]),
.n_Gl(s4_G_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S4_KNOWN; i >= 0; i=i-1) begin : s5_prev_known
not s5pk (s5_G[i], s4_G_n[i]);
end
endgenerate
generate
for (i = 32; i > 0; i=i-1) begin : output_sum
xnor sum (S[i], s0_P_n[i], s5_G[i-1]);
end
endgenerate
wire inverted_31_0_G;
not (inverted_31_0_G, s5_G[31]);
n_G carry_out (
.Gc(Co),
.n_Pu(s0_P_n[32]),
.n_Gu(s0_G_n[32]),
.n_Gl(inverted_31_0_G)
);
endmodule | module knowles32
#(
parameter [31:0] KNOWLES_S2 = 2,
parameter [31:0] KNOWLES_S3 = 4,
parameter [31:0] KNOWLES_S4 = 8,
parameter [31:0] KNOWLES_S5 = 16
)
(
output Co,
output [32:1] S,
input [32:1] A,
input [32:1] B,
input Ci
); |
genvar i;
wire [32:1] s0_P_n;
wire [32:0] s0_G_n;
generate
for (i = 32; i > 0; i=i-1) begin : s0_unknown
input_PG_n s0u (
.P_n(s0_P_n[i]),
.G_n(s0_G_n[i]),
.A(A[i]),
.B(B[i])
);
end
endgenerate
not (s0_G_n[0], Ci);
localparam S0_KNOWN = 0;
localparam S0_GROUP_SIZE = 1;
wire [31:1] s1_P;
wire [31:0] s1_G;
generate
for (i = 31; i > S0_KNOWN + S0_GROUP_SIZE; i=i-1) begin: s1_unknown
n_PG s1u (
.Pc(s1_P[i]),
.Gc(s1_G[i]),
.n_Pu(s0_P_n[i]),
.n_Gu(s0_G_n[i]),
.n_Pl(s0_P_n[(i-1)]),
.n_Gl(s0_G_n[(i-1)])
);
end
endgenerate
generate
for (i = S0_KNOWN + S0_GROUP_SIZE; i > S0_KNOWN; i=i-1) begin : s1_known
n_G s1k (
.Gc(s1_G[i]),
.n_Pu(s0_P_n[i]),
.n_Gu(s0_G_n[i]),
.n_Gl(s0_G_n[(i-1)])
);
end
endgenerate
not (s1_G[0], s0_G_n[0]);
localparam S1_KNOWN = 1;
localparam S1_GROUP_SIZE = 2;
wire [31:1] s2_P_n;
wire [31:0] s2_G_n;
generate
for (i = 31; i > S1_KNOWN + S1_GROUP_SIZE; i=i-1) begin : s2_unknown
PG_n s2u (
.Pc_n(s2_P_n[i]),
.Gc_n(s2_G_n[i]),
.Pu(s1_P[i]),
.Gu(s1_G[i]),
.Pl(s1_P[(i | KNOWLES_S2-1) - S1_GROUP_SIZE]),
.Gl(s1_G[(i | KNOWLES_S2-1) - S1_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S1_KNOWN + S1_GROUP_SIZE; i > S1_KNOWN; i=i-1) begin : s2_known
G_n s2k (
.Gc_n(s2_G_n[i]),
.Pu(s1_P[i]),
.Gu(s1_G[i]),
.Gl(s1_G[(i | KNOWLES_S2-1) - S1_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S1_KNOWN; i >= 0; i=i-1) begin : s2_prev_known
not s2pk (s2_G_n[i], s1_G[i]);
end
endgenerate
localparam S2_KNOWN = 3;
localparam S2_GROUP_SIZE = 4;
wire [31:1] s3_P;
wire [31:0] s3_G;
generate
for (i = 31; i > S2_KNOWN + S2_GROUP_SIZE; i=i-1) begin : s3_unknown
n_PG s3u (
.Pc(s3_P[i]),
.Gc(s3_G[i]),
.n_Pu(s2_P_n[i]),
.n_Gu(s2_G_n[i]),
.n_Pl(s2_P_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE]),
.n_Gl(s2_G_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S2_KNOWN + S2_GROUP_SIZE; i > S2_KNOWN; i=i-1) begin : s3_known
n_G s3k (
.Gc(s3_G[i]),
.n_Pu(s2_P_n[i]),
.n_Gu(s2_G_n[i]),
.n_Gl(s2_G_n[(i | KNOWLES_S3-1) - S2_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S2_KNOWN; i >= 0; i=i-1) begin : s3_prev_known
not s3pk (s3_G[i], s2_G_n[i]);
end
endgenerate
localparam S3_KNOWN = 7;
localparam S3_GROUP_SIZE = 8;
wire [31:1] s4_P_n;
wire [31:0] s4_G_n;
generate
for (i = 31; i > S3_KNOWN + S3_GROUP_SIZE; i=i-1) begin : s4_unknown
PG_n s4u (
.Pc_n(s4_P_n[i]),
.Gc_n(s4_G_n[i]),
.Pu(s3_P[i]),
.Gu(s3_G[i]),
.Pl(s3_P[(i | KNOWLES_S4-1) - S3_GROUP_SIZE]),
.Gl(s3_G[(i | KNOWLES_S4-1) - S3_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S3_KNOWN + S3_GROUP_SIZE; i > S3_KNOWN; i=i-1) begin : s4_known
G_n s4k (
.Gc_n(s4_G_n[i]),
.Pu(s3_P[i]),
.Gu(s3_G[i]),
.Gl(s3_G[(i | KNOWLES_S4-1) - S3_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S3_KNOWN; i >= 0; i=i-1) begin : s4_prev_known
not s4pk (s4_G_n[i], s3_G[i]);
end
endgenerate
localparam S4_KNOWN = 15;
localparam S4_GROUP_SIZE = 16;
wire [31:1] s5_P;
wire [31:0] s5_G;
generate
for (i = 31; i > S4_KNOWN + S4_GROUP_SIZE; i=i-1) begin : s5_unknown
n_PG s5u (
.Pc(s5_P[i]),
.Gc(s5_G[i]),
.n_Pu(s4_P_n[i]),
.n_Gu(s4_G_n[i]),
.n_Pl(s4_P_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE]),
.n_Gl(s4_G_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S4_KNOWN + S4_GROUP_SIZE; i > S4_KNOWN; i=i-1) begin : s5_known
n_G s5k (
.Gc(s5_G[i]),
.n_Pu(s4_P_n[i]),
.n_Gu(s4_G_n[i]),
.n_Gl(s4_G_n[(i | KNOWLES_S5-1) - S4_GROUP_SIZE])
);
end
endgenerate
generate
for (i = S4_KNOWN; i >= 0; i=i-1) begin : s5_prev_known
not s5pk (s5_G[i], s4_G_n[i]);
end
endgenerate
generate
for (i = 32; i > 0; i=i-1) begin : output_sum
xnor sum (S[i], s0_P_n[i], s5_G[i-1]);
end
endgenerate
wire inverted_31_0_G;
not (inverted_31_0_G, s5_G[31]);
n_G carry_out (
.Gc(Co),
.n_Pu(s0_P_n[32]),
.n_Gu(s0_G_n[32]),
.n_Gl(inverted_31_0_G)
);
endmodule | 0 |
5,638 | data/full_repos/permissive/114519317/knowles32_testbench.v | 114,519,317 | knowles32_testbench.v | v | 62 | 80 | [] | [] | [] | null | line:96: before: "~|" | null | 1: b'%Error: data/full_repos/permissive/114519317/knowles32_testbench.v:10: Cannot find include file: knowles32.v\n`include "knowles32.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/knowles32.v\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/knowles32.v.v\n data/full_repos/permissive/114519317,data/full_repos/permissive/114519317/knowles32.v.sv\n knowles32.v\n knowles32.v.v\n knowles32.v.sv\n obj_dir/knowles32.v\n obj_dir/knowles32.v.v\n obj_dir/knowles32.v.sv\n%Error: data/full_repos/permissive/114519317/knowles32_testbench.v:33: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("knowles32.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114519317/knowles32_testbench.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,knowles32_testbench); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/114519317/knowles32_testbench.v:36: Unsupported or unknown PLI call: $monitor\n $monitor("%b\\t%d\\t%d\\t%d\\t%d%d", success, S_exp, S, Co_exp, Co, $time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114519317/knowles32_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n always #arbitrary_delay begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114519317/knowles32_testbench.v:53: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n Ci = $random(SEED);\n ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/114519317/knowles32_testbench.v:53: ../V3Ast.cpp:358: Null item passed to setOp1p\n Ci = $random(SEED);\n ^\n' | 6,388 | module | module knowles32_testbench();
integer SEED = 255;
parameter TRIALS = 100000;
parameter arbitrary_delay = 10;
reg [31:0] A, B;
reg Ci;
wire [31:0] S;
wire Co;
wire [31:0] S_exp = A + B + Ci;
wire Co_exp = (S < A) | (S < B);
wire success;
initial begin
$dumpfile("knowles32.vcd");
$dumpvars(0,knowles32_testbench);
$display("success\tout\t\texpect\t\tCo\texpect\t\tTime");
$monitor("%b\t%d\t%d\t%d\t%d%d", success, S_exp, S, Co_exp, Co, $time);
end
knowles32 dut (.A(A), .B(B), .Ci(Ci), .S(S), .Co(Co));
assign success = (S_exp == S) && (Co == Co_exp);
always #arbitrary_delay begin
if (~success)
$stop;
end
integer i;
initial begin
for (i = 0; i <= TRIALS; i = i + 1) begin
Ci = $random(SEED);
A = $random(SEED);
B = $random(SEED);
#arbitrary_delay;
end
$finish;
end
endmodule | module knowles32_testbench(); |
integer SEED = 255;
parameter TRIALS = 100000;
parameter arbitrary_delay = 10;
reg [31:0] A, B;
reg Ci;
wire [31:0] S;
wire Co;
wire [31:0] S_exp = A + B + Ci;
wire Co_exp = (S < A) | (S < B);
wire success;
initial begin
$dumpfile("knowles32.vcd");
$dumpvars(0,knowles32_testbench);
$display("success\tout\t\texpect\t\tCo\texpect\t\tTime");
$monitor("%b\t%d\t%d\t%d\t%d%d", success, S_exp, S, Co_exp, Co, $time);
end
knowles32 dut (.A(A), .B(B), .Ci(Ci), .S(S), .Co(Co));
assign success = (S_exp == S) && (Co == Co_exp);
always #arbitrary_delay begin
if (~success)
$stop;
end
integer i;
initial begin
for (i = 0; i <= TRIALS; i = i + 1) begin
Ci = $random(SEED);
A = $random(SEED);
B = $random(SEED);
#arbitrary_delay;
end
$finish;
end
endmodule | 0 |
5,639 | data/full_repos/permissive/114519317/components/aoi.v | 114,519,317 | aoi.v | v | 13 | 29 | [] | [] | [] | null | line:9: before: "~|" | data/verilator_xmls/8cf4c6bc-1bb1-406e-8f53-646fea074238.xml | null | 6,389 | module | module aoi (
output O,
input A, B, C
);
assign O = C ~| (A & B);
endmodule | module aoi (
output O,
input A, B, C
); |
assign O = C ~| (A & B);
endmodule | 0 |
5,640 | data/full_repos/permissive/114519317/components/G_n.v | 114,519,317 | G_n.v | v | 42 | 71 | [] | [] | [] | null | line:28: before: "~|" | null | 1: b'%Error: data/full_repos/permissive/114519317/components/G_n.v:20: Cannot find include file: ./components/aoi.v\n`include "./components/aoi.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v.sv\n ./components/aoi.v\n ./components/aoi.v.v\n ./components/aoi.v.sv\n obj_dir/./components/aoi.v\n obj_dir/./components/aoi.v.v\n obj_dir/./components/aoi.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,390 | module | module G_n (
output Gc_n,
input Pu, Gu, Gl
);
aoi group_generate (
.O(Gc_n),
.A(Gl),
.B(Pu),
.C(Gu)
);
endmodule | module G_n (
output Gc_n,
input Pu, Gu, Gl
); |
aoi group_generate (
.O(Gc_n),
.A(Gl),
.B(Pu),
.C(Gu)
);
endmodule | 0 |
5,641 | data/full_repos/permissive/114519317/components/input_PG_n.v | 114,519,317 | input_PG_n.v | v | 38 | 79 | [] | [] | [] | [(24, 36)] | null | data/verilator_xmls/6dcf09df-92f9-4090-833e-6fbeb3766acc.xml | null | 6,391 | module | module input_PG_n (
output P_n, G_n,
input A, B
);
nand inverted_generate (G_n, A, B);
xnor inverted_propagate (P_n, A, B);
endmodule | module input_PG_n (
output P_n, G_n,
input A, B
); |
nand inverted_generate (G_n, A, B);
xnor inverted_propagate (P_n, A, B);
endmodule | 0 |
5,642 | data/full_repos/permissive/114519317/components/n_G.v | 114,519,317 | n_G.v | v | 43 | 71 | [] | [] | [] | null | line:28: before: "~&" | null | 1: b'%Error: data/full_repos/permissive/114519317/components/n_G.v:20: Cannot find include file: ./components/oai.v\n`include "./components/oai.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v.sv\n ./components/oai.v\n ./components/oai.v.v\n ./components/oai.v.sv\n obj_dir/./components/oai.v\n obj_dir/./components/oai.v.v\n obj_dir/./components/oai.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,392 | module | module n_G (
output Gc,
input n_Pu, n_Gu, n_Gl
);
oai group_generate (
.O(Gc),
.A(n_Gl),
.B(n_Pu),
.C(n_Gu)
);
endmodule | module n_G (
output Gc,
input n_Pu, n_Gu, n_Gl
); |
oai group_generate (
.O(Gc),
.A(n_Gl),
.B(n_Pu),
.C(n_Gu)
);
endmodule | 0 |
5,643 | data/full_repos/permissive/114519317/components/n_PG.v | 114,519,317 | n_PG.v | v | 50 | 72 | [] | [] | [] | null | line:30: before: "~&" | null | 1: b'%Error: data/full_repos/permissive/114519317/components/n_PG.v:22: Cannot find include file: ./components/oai.v\n`include "./components/oai.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/oai.v.sv\n ./components/oai.v\n ./components/oai.v.v\n ./components/oai.v.sv\n obj_dir/./components/oai.v\n obj_dir/./components/oai.v.v\n obj_dir/./components/oai.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,393 | module | module n_PG (
output Pc, Gc,
input n_Pu, n_Gu, n_Pl, n_Gl
);
nor group_propagate (Pc, n_Pu, n_Pl);
oai group_generate (
.O(Gc),
.A(n_Gl),
.B(n_Pu),
.C(n_Gu)
);
endmodule | module n_PG (
output Pc, Gc,
input n_Pu, n_Gu, n_Pl, n_Gl
); |
nor group_propagate (Pc, n_Pu, n_Pl);
oai group_generate (
.O(Gc),
.A(n_Gl),
.B(n_Pu),
.C(n_Gu)
);
endmodule | 0 |
5,644 | data/full_repos/permissive/114519317/components/oai.v | 114,519,317 | oai.v | v | 13 | 29 | [] | [] | [] | null | line:9: before: "~&" | data/verilator_xmls/3f3d46f7-0115-41e4-a664-e0edbbbbb8dd.xml | null | 6,394 | module | module oai (
output O,
input A, B, C
);
assign O = C ~& (A | B);
endmodule | module oai (
output O,
input A, B, C
); |
assign O = C ~& (A | B);
endmodule | 0 |
5,645 | data/full_repos/permissive/114519317/components/PG_n.v | 114,519,317 | PG_n.v | v | 47 | 72 | [] | [] | [] | null | line:30: before: "~|" | null | 1: b'%Error: data/full_repos/permissive/114519317/components/PG_n.v:22: Cannot find include file: ./components/aoi.v\n`include "./components/aoi.v" \n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v.v\n data/full_repos/permissive/114519317/components,data/full_repos/permissive/114519317/./components/aoi.v.sv\n ./components/aoi.v\n ./components/aoi.v.v\n ./components/aoi.v.sv\n obj_dir/./components/aoi.v\n obj_dir/./components/aoi.v.v\n obj_dir/./components/aoi.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,395 | module | module PG_n (
output Pc_n, Gc_n,
input Pu, Gu, Pl, Gl
);
nand group_propagate (Pc_n, Pu, Pl);
aoi group_generate (
.O(Gc_n),
.A(Gl),
.B(Pu),
.C(Gu)
);
endmodule | module PG_n (
output Pc_n, Gc_n,
input Pu, Gu, Pl, Gl
); |
nand group_propagate (Pc_n, Pu, Pl);
aoi group_generate (
.O(Gc_n),
.A(Gl),
.B(Pu),
.C(Gu)
);
endmodule | 0 |
5,646 | data/full_repos/permissive/114553631/src/alu.v | 114,553,631 | alu.v | v | 36 | 47 | [] | [] | [] | [(4, 33)] | null | data/verilator_xmls/0b77651f-a6f2-48e3-b0b7-4d359143bf17.xml | null | 6,396 | module | module alu(
output reg [31:0] e_valE,
input [31:0] e_aluA,
input [31:0] e_aluB,
input [5:0] e_alufunc
);
always @(e_aluA, e_aluB, e_alufunc) begin
case(e_alufunc)
6'b100000: begin
e_valE <= e_aluA + e_aluB;
end
6'b100010: begin
e_valE <= e_aluB - e_aluA;
end
6'b100100: begin
e_valE <= e_aluA & e_aluB;
end
6'b100101: begin
e_valE <= e_aluA | e_aluB;
end
6'b101010: begin
e_valE <= (e_aluA>e_aluB)?1:0;
end
endcase
end
endmodule | module alu(
output reg [31:0] e_valE,
input [31:0] e_aluA,
input [31:0] e_aluB,
input [5:0] e_alufunc
); |
always @(e_aluA, e_aluB, e_alufunc) begin
case(e_alufunc)
6'b100000: begin
e_valE <= e_aluA + e_aluB;
end
6'b100010: begin
e_valE <= e_aluB - e_aluA;
end
6'b100100: begin
e_valE <= e_aluA & e_aluB;
end
6'b100101: begin
e_valE <= e_aluA | e_aluB;
end
6'b101010: begin
e_valE <= (e_aluA>e_aluB)?1:0;
end
endcase
end
endmodule | 2 |
5,647 | data/full_repos/permissive/114553631/src/aluA.v | 114,553,631 | aluA.v | v | 26 | 38 | [] | [] | [] | [(22, 39)] | null | null | 1: b'%Error: data/full_repos/permissive/114553631/src/aluA.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/aluA.v:14: Define or directive not defined: \'`IROP\'\n if (E_op==`IROP) begin\n ^~~~~\n%Error: data/full_repos/permissive/114553631/src/aluA.v:14: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (E_op==`IROP) begin\n ^\n%Error: data/full_repos/permissive/114553631/src/aluA.v:16: Define or directive not defined: \'`IJ\'\n end else if (E_op!=`IJ) begin\n ^~~\n%Error: Cannot continue\n' | 6,397 | module | module aluA(
output reg [31:0] e_aluA,
input [5:0] E_op,
input [31:0] E_valC,
input [31:0] E_valA
);
always @(*) begin
if (E_op==`IROP) begin
e_aluA <= E_valA;
end else if (E_op!=`IJ) begin
e_aluA <= E_valC;
end else begin
e_aluA <= 0;
end
end
endmodule | module aluA(
output reg [31:0] e_aluA,
input [5:0] E_op,
input [31:0] E_valC,
input [31:0] E_valA
); |
always @(*) begin
if (E_op==`IROP) begin
e_aluA <= E_valA;
end else if (E_op!=`IJ) begin
e_aluA <= E_valC;
end else begin
e_aluA <= 0;
end
end
endmodule | 2 |
5,648 | data/full_repos/permissive/114553631/src/aluB.v | 114,553,631 | aluB.v | v | 19 | 30 | [] | [] | [] | [(22, 32)] | null | null | 1: b'%Error: data/full_repos/permissive/114553631/src/aluB.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/aluB.v:12: Define or directive not defined: \'`IJ\'\n if (E_op!=`IJ) begin\n ^~~\n%Error: data/full_repos/permissive/114553631/src/aluB.v:12: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (E_op!=`IJ) begin\n ^\n%Error: Cannot continue\n' | 6,398 | module | module aluB(
output reg [31:0] e_aluB,
input [5:0] E_op,
input [31:0] E_valB
);
always @(*) begin
if (E_op!=`IJ) begin
e_aluB <= E_valB;
end
end
endmodule | module aluB(
output reg [31:0] e_aluB,
input [5:0] E_op,
input [31:0] E_valB
); |
always @(*) begin
if (E_op!=`IJ) begin
e_aluB <= E_valB;
end
end
endmodule | 2 |
5,649 | data/full_repos/permissive/114553631/src/alufunc.v | 114,553,631 | alufunc.v | v | 15 | 31 | [] | [] | [] | [(4, 12)] | null | data/verilator_xmls/89544631-3d13-4be9-a421-dfe3f104db99.xml | null | 6,399 | module | module alufunc(
output [5:0] e_alufunc,
input [5:0] E_op,
input [5:0] E_func
);
assign e_alufunc = E_func;
endmodule | module alufunc(
output [5:0] e_alufunc,
input [5:0] E_op,
input [5:0] E_func
); |
assign e_alufunc = E_func;
endmodule | 2 |
5,650 | data/full_repos/permissive/114553631/src/data_mem.v | 114,553,631 | data_mem.v | v | 30 | 49 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/114553631/src/data_mem.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:21: Define or directive not defined: \'`ILW\'\n if (M_op==`ILW) begin\n ^~~~\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (M_op==`ILW) begin\n ^\n%Error: data/full_repos/permissive/114553631/src/data_mem.v:23: Define or directive not defined: \'`ISW\'\n end else if (M_op==`ISW) begin\n ^~~~\n%Error: Cannot continue\n' | 6,401 | module | module data_mem(
output reg [31:0] m_valM,
input [5:0] M_op,
input [31:0] M_valE,
input [31:0] M_valA
);
parameter DM_DATA="../data/data_memory.txt";
reg[31:0] data[0:63];
initial begin
$readmemh(DM_DATA, data, 0, 63);
end
always @(*) begin
if (M_op==`ILW) begin
m_valM <= data[M_valE[5:0]];
end else if (M_op==`ISW) begin
data[M_valE[5:0]] <= M_valA;
end
end
endmodule | module data_mem(
output reg [31:0] m_valM,
input [5:0] M_op,
input [31:0] M_valE,
input [31:0] M_valA
); |
parameter DM_DATA="../data/data_memory.txt";
reg[31:0] data[0:63];
initial begin
$readmemh(DM_DATA, data, 0, 63);
end
always @(*) begin
if (M_op==`ILW) begin
m_valM <= data[M_valE[5:0]];
end else if (M_op==`ISW) begin
data[M_valE[5:0]] <= M_valA;
end
end
endmodule | 2 |
5,651 | data/full_repos/permissive/114553631/src/dstE.v | 114,553,631 | dstE.v | v | 27 | 88 | [] | [] | [] | [(22, 40)] | null | null | 1: b'%Error: data/full_repos/permissive/114553631/src/dstE.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/dstE.v:14: Define or directive not defined: \'`IROP\'\n if (D_op==`IROP) begin\n ^~~~~\n%Error: data/full_repos/permissive/114553631/src/dstE.v:14: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (D_op==`IROP) begin\n ^\n%Error: data/full_repos/permissive/114553631/src/dstE.v:16: Define or directive not defined: \'`IADDI\'\n end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114553631/src/dstE.v:16: Define or directive not defined: \'`IANDI\'\n end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114553631/src/dstE.v:16: Define or directive not defined: \'`IORI\'\n end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin\n ^~~~~\n%Error: data/full_repos/permissive/114553631/src/dstE.v:16: Define or directive not defined: \'`ISLTI\'\n end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114553631/src/dstE.v:19: Define or directive not defined: \'`RNONE\'\n d_dstE = `RNONE;\n ^~~~~~\n%Error: Cannot continue\n' | 6,403 | module | module dstE(
output reg [4:0] d_dstE,
input [5:0] D_op,
input [4:0] D_rt,
input [4:0] D_rd
);
always @(*) begin
if (D_op==`IROP) begin
d_dstE = D_rd;
end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin
d_dstE = D_rt;
end else begin
d_dstE = `RNONE;
end
$display("D_op: %d, D_rt=%d, dstE: %d",D_op, D_rt, d_dstE);
end
endmodule | module dstE(
output reg [4:0] d_dstE,
input [5:0] D_op,
input [4:0] D_rt,
input [4:0] D_rd
); |
always @(*) begin
if (D_op==`IROP) begin
d_dstE = D_rd;
end else if (D_op==`IADDI || D_op==`IANDI || D_op==`IORI || D_op==`ISLTI) begin
d_dstE = D_rt;
end else begin
d_dstE = `RNONE;
end
$display("D_op: %d, D_rt=%d, dstE: %d",D_op, D_rt, d_dstE);
end
endmodule | 2 |
5,653 | data/full_repos/permissive/114553631/src/D_reg.v | 114,553,631 | D_reg.v | v | 35 | 32 | [] | [] | [] | [(4, 32)] | null | data/verilator_xmls/6bbba3a4-ec6e-4893-bc34-bd6acac9ef73.xml | null | 6,405 | module | module D_reg(
output reg [5:0] D_op,
output reg [5:0] D_func,
output reg [4:0] D_rs,
output reg [4:0] D_rt,
output reg [4:0] D_rd,
output reg [31:0] D_valC,
input clk,
input D_stall,
input [5:0] f_op,
input [5:0] f_func,
input [4:0] f_rs,
input [4:0] f_rt,
input [4:0] f_rd,
input [31:0] f_valC
);
always @(posedge clk) begin
if (!D_stall) begin
D_op <= f_op;
D_func <= f_func;
D_rs <= f_rs;
D_rt <= f_rt;
D_rd <= f_rd;
D_valC <= f_valC;
end
end
endmodule | module D_reg(
output reg [5:0] D_op,
output reg [5:0] D_func,
output reg [4:0] D_rs,
output reg [4:0] D_rt,
output reg [4:0] D_rd,
output reg [31:0] D_valC,
input clk,
input D_stall,
input [5:0] f_op,
input [5:0] f_func,
input [4:0] f_rs,
input [4:0] f_rt,
input [4:0] f_rd,
input [31:0] f_valC
); |
always @(posedge clk) begin
if (!D_stall) begin
D_op <= f_op;
D_func <= f_func;
D_rs <= f_rs;
D_rt <= f_rt;
D_rd <= f_rd;
D_valC <= f_valC;
end
end
endmodule | 2 |
5,659 | data/full_repos/permissive/114553631/src/srcB.v | 114,553,631 | srcB.v | v | 18 | 45 | [] | [] | [] | [(22, 31)] | null | null | 1: b'%Error: data/full_repos/permissive/114553631/src/srcB.v:4: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/src,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/src/srcB.v:12: Define or directive not defined: \'`IJ\'\n assign d_srcB = (D_op!=`IJ)?D_rs:`RNONE;\n ^~~\n%Error: data/full_repos/permissive/114553631/src/srcB.v:12: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign d_srcB = (D_op!=`IJ)?D_rs:`RNONE;\n ^\n%Error: data/full_repos/permissive/114553631/src/srcB.v:12: Define or directive not defined: \'`RNONE\'\n assign d_srcB = (D_op!=`IJ)?D_rs:`RNONE;\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,416 | module | module srcB(
output [4:0] d_srcB,
input [5:0] D_op,
input [4:0] D_rs
);
assign d_srcB = (D_op!=`IJ)?D_rs:`RNONE;
endmodule | module srcB(
output [4:0] d_srcB,
input [5:0] D_op,
input [4:0] D_rs
); |
assign d_srcB = (D_op!=`IJ)?D_rs:`RNONE;
endmodule | 2 |
5,661 | data/full_repos/permissive/114553631/test/test_alufunc.v | 114,553,631 | test_alufunc.v | v | 40 | 83 | [] | [] | [] | null | line:68 column:2: Illegal character '\x00' | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_alufunc.v:6: Cannot find include file: ../src/alufunc.v\n`include "../src/alufunc.v" \n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/alufunc.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/alufunc.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/alufunc.v.sv\n ../src/alufunc.v\n ../src/alufunc.v.v\n ../src/alufunc.v.sv\n obj_dir/../src/alufunc.v\n obj_dir/../src/alufunc.v.v\n obj_dir/../src/alufunc.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:17: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_alufunc.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_alufunc.v:34: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, "op=%b func=%b efunc=%b", E_op, E_func, e_alufunc);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n' | 6,421 | module | module test_alufunc;
reg [5:0] E_func = 0;
reg [5:0] E_op = 0;
wire [5:0] e_alufunc;
parameter stop_time = 60;
alufunc ALUFUNC(e_alufunc, E_op, E_func);
initial #stop_time $finish;
initial begin
#10;
E_func = 6'b100000;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
end
initial begin
$monitor("time = ", $time, "op=%b func=%b efunc=%b", E_op, E_func, e_alufunc);
end
endmodule | module test_alufunc; |
reg [5:0] E_func = 0;
reg [5:0] E_op = 0;
wire [5:0] e_alufunc;
parameter stop_time = 60;
alufunc ALUFUNC(e_alufunc, E_op, E_func);
initial #stop_time $finish;
initial begin
#10;
E_func = 6'b100000;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
E_func = 6'b100010;
#10;
end
initial begin
$monitor("time = ", $time, "op=%b func=%b efunc=%b", E_op, E_func, e_alufunc);
end
endmodule | 2 |
5,662 | data/full_repos/permissive/114553631/test/test_cpu.v | 114,553,631 | test_cpu.v | v | 25 | 32 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_cpu.v:6: Cannot find include file: ../src/cpu.v\n`include "../src/cpu.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/cpu.v.sv\n ../src/cpu.v\n ../src/cpu.v.v\n ../src/cpu.v.sv\n obj_dir/../src/cpu.v\n obj_dir/../src/cpu.v.v\n obj_dir/../src/cpu.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_cpu.v:13: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_cpu.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100 clk = ~clk;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 6,422 | module | module test_cpu;
reg clk;
parameter stop_time = 5000;
initial #stop_time $finish;
cpu CPU(clk);
initial begin
clk = 0;
repeat(50)
#100 clk = ~clk;
end
endmodule | module test_cpu; |
reg clk;
parameter stop_time = 5000;
initial #stop_time $finish;
cpu CPU(clk);
initial begin
clk = 0;
repeat(50)
#100 clk = ~clk;
end
endmodule | 2 |
5,663 | data/full_repos/permissive/114553631/test/test_data_mem.v | 114,553,631 | test_data_mem.v | v | 52 | 70 | [] | [] | [] | null | line:62: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:6: Cannot find include file: ../src/data_mem.v\n`include "../src/data_mem.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/data_mem.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/data_mem.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/data_mem.v.sv\n ../src/data_mem.v\n ../src/data_mem.v.v\n ../src/data_mem.v.sv\n obj_dir/../src/data_mem.v\n obj_dir/../src/data_mem.v.v\n obj_dir/../src/data_mem.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:18: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:22: Define or directive not defined: \'`ISW\'\n M_op = `ISW;\n ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `ISW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:26: Define or directive not defined: \'`ISW\'\n M_op = `ISW;\n ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `ISW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:30: Define or directive not defined: \'`ILW\'\n M_op = `ILW;\n ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `ILW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:33: Define or directive not defined: \'`ILW\'\n M_op = `ILW;\n ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `ILW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:36: Define or directive not defined: \'`IROP\'\n M_op = `IROP;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `IROP;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:40: Define or directive not defined: \'`IJ\'\n M_op = `IJ;\n ^~~\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n M_op = `IJ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_data_mem.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_data_mem.v:46: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " valM=%x", m_valM); \n ^~~~~~~~\n%Error: Exiting due to 14 error(s), 8 warning(s)\n' | 6,423 | module | module test_data_mem;
reg [5:0] M_op;
reg [31:0] M_valE;
reg [31:0] M_valA;
wire [31:0] m_valM;
parameter stop_time = 100;
data_mem DATA_MEM(m_valM, M_op, M_valE, M_valA);
initial #stop_time $finish;
initial begin
#10;
M_op = `ISW;
M_valE = 1;
M_valA = 1;
#10;
M_op = `ISW;
M_valE = 2;
M_valA = 2;
#10;
M_op = `ILW;
M_valE = 2;
#10;
M_op = `ILW;
M_valE = 1;
#10;
M_op = `IROP;
M_valE = 3;
M_valA = 3;
#10;
M_op = `IJ;
M_valE = 3;
#10;
end
initial begin
$monitor("time = ", $time, " valM=%x", m_valM);
end
endmodule | module test_data_mem; |
reg [5:0] M_op;
reg [31:0] M_valE;
reg [31:0] M_valA;
wire [31:0] m_valM;
parameter stop_time = 100;
data_mem DATA_MEM(m_valM, M_op, M_valE, M_valA);
initial #stop_time $finish;
initial begin
#10;
M_op = `ISW;
M_valE = 1;
M_valA = 1;
#10;
M_op = `ISW;
M_valE = 2;
M_valA = 2;
#10;
M_op = `ILW;
M_valE = 2;
#10;
M_op = `ILW;
M_valE = 1;
#10;
M_op = `IROP;
M_valE = 3;
M_valA = 3;
#10;
M_op = `IJ;
M_valE = 3;
#10;
end
initial begin
$monitor("time = ", $time, " valM=%x", m_valM);
end
endmodule | 2 |
5,665 | data/full_repos/permissive/114553631/test/test_D_reg.v | 114,553,631 | test_D_reg.v | v | 76 | 119 | [] | [] | [] | null | line:79: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:6: Cannot find include file: ../src/def.v\n`include "../src/def.v" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/def.v.sv\n ../src/def.v\n ../src/def.v.v\n ../src/def.v.sv\n obj_dir/../src/def.v\n obj_dir/../src/def.v.v\n obj_dir/../src/def.v.sv\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:8: Cannot find include file: ../src/D_reg.v\n`include "../src/D_reg.v" \n ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:30: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:34: Define or directive not defined: \'`IROP\'\n f_op = `IROP;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n f_op = `IROP;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:42: Define or directive not defined: \'`IROP\'\n f_op = `IROP;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n f_op = `IROP;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:48: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:50: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:52: Define or directive not defined: \'`IORI\'\n f_op = `IORI;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n f_op = `IORI;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:58: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:61: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_D_reg.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_D_reg.v:70: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);\n ^~~~~~~~\n%Error: Exiting due to 9 error(s), 8 warning(s)\n' | 6,426 | module | module test_D_reg;
reg clk = 0;
reg D_stall = 0;
reg [5:0] f_op = 0;
reg [5:0] f_func = 0;
reg [4:0] f_rs = 0;
reg [4:0] f_rt = 0;
reg [4:0] f_rd = 0;
reg [31:0] f_valC = 0;
wire [5:0] D_op;
wire [5:0] D_func;
wire [4:0] D_rs;
wire [4:0] D_rt;
wire [4:0] D_rd;
wire [31:0] D_valC;
parameter stop_time = 100;
D_reg DREG(D_op, D_func, D_rs, D_rt, D_rd, D_valC, clk, D_stall, f_op, f_func, f_rs, f_rd, f_rt, f_valC);
initial #stop_time $finish;
initial begin
#10;
f_op = `IROP;
f_func = 6'b100111;
f_rs = 5'b10011;
f_rt = 5'b11110;
f_rd = 5'b11101;
f_valC = 66;
#20;
D_stall = 1;
f_op = `IROP;
f_func = 6'b100100;
f_rs = 5'b10010;
f_rt = 5'b10110;
f_rd = 5'b10101;
f_valC = 77;
#20;
D_stall = 0;
#20;
D_stall = 0;
f_op = `IORI;
f_func = 6'b100000;
f_rs = 5'b10111;
f_rt = 5'b10000;
f_rd = 5'b10100;
f_valC = 88;
#20;
D_stall = 1;
f_valC = 99;
#20;
end
initial begin
repeat(10)
#10 clk = ~clk;
end
initial begin
$monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);
end
endmodule | module test_D_reg; |
reg clk = 0;
reg D_stall = 0;
reg [5:0] f_op = 0;
reg [5:0] f_func = 0;
reg [4:0] f_rs = 0;
reg [4:0] f_rt = 0;
reg [4:0] f_rd = 0;
reg [31:0] f_valC = 0;
wire [5:0] D_op;
wire [5:0] D_func;
wire [4:0] D_rs;
wire [4:0] D_rt;
wire [4:0] D_rd;
wire [31:0] D_valC;
parameter stop_time = 100;
D_reg DREG(D_op, D_func, D_rs, D_rt, D_rd, D_valC, clk, D_stall, f_op, f_func, f_rs, f_rd, f_rt, f_valC);
initial #stop_time $finish;
initial begin
#10;
f_op = `IROP;
f_func = 6'b100111;
f_rs = 5'b10011;
f_rt = 5'b11110;
f_rd = 5'b11101;
f_valC = 66;
#20;
D_stall = 1;
f_op = `IROP;
f_func = 6'b100100;
f_rs = 5'b10010;
f_rt = 5'b10110;
f_rd = 5'b10101;
f_valC = 77;
#20;
D_stall = 0;
#20;
D_stall = 0;
f_op = `IORI;
f_func = 6'b100000;
f_rs = 5'b10111;
f_rt = 5'b10000;
f_rd = 5'b10100;
f_valC = 88;
#20;
D_stall = 1;
f_valC = 99;
#20;
end
initial begin
repeat(10)
#10 clk = ~clk;
end
initial begin
$monitor("time = ", $time, " op=%b func=%b rs=%d rt=%d rd=%d valC=%d", D_op, D_func, D_rs, D_rt, D_rd, D_valC);
end
endmodule | 2 |
5,666 | data/full_repos/permissive/114553631/test/test_E_reg.v | 114,553,631 | test_E_reg.v | v | 103 | 206 | [] | [] | [] | null | line:103: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_E_reg.v:6: Cannot find include file: ../src/E_reg.v\n`include "../src/E_reg.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/E_reg.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/E_reg.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/E_reg.v.sv\n ../src/E_reg.v\n ../src/E_reg.v.v\n ../src/E_reg.v.sv\n obj_dir/../src/E_reg.v\n obj_dir/../src/E_reg.v.v\n obj_dir/../src/E_reg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:34: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:80: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_E_reg.v:94: Unsupported: Ignoring delay on this delayed statement.\n #10 clk=~clk;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_E_reg.v:98: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " E_op=%b, E_func=%b, E_valC=%d, E_valA=%d, E_valB=%d, E_dstE=%b, E_dstM=%b, E_srcA=%b, E_srcB=%b", E_op, E_func, E_valC, E_valA, E_valB, E_dstE, E_dstM, E_srcA, E_srcB);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n' | 6,427 | module | module test_E_reg;
reg clk;
reg E_bubble;
reg [5:0] D_op;
reg [5:0] D_func;
reg [31:0] D_valC;
reg [31:0] d_valA;
reg [31:0] d_valB;
reg [4:0] d_dstE;
reg [4:0] d_dstM;
reg [4:0] d_srcA;
reg [4:0] d_srcB;
wire [5:0] E_op;
wire [5:0] E_func;
wire [31:0] E_valC;
wire [31:0] E_valA;
wire [31:0] E_valB;
wire [4:0] E_dstE;
wire [4:0] E_dstM;
wire [4:0] E_srcA;
wire [4:0] E_srcB;
parameter stop_time = 80;
E_reg E_REG(E_op, E_func, E_valC, E_valA, E_valB, E_dstE, E_dstM, E_srcA, E_srcB, clk, E_bubble, D_op, D_func, D_valC, d_valA, d_valB, d_dstE, d_dstM, d_srcA, d_srcB);
initial #stop_time $finish;
initial begin
E_bubble = 0;
clk = 0;
#10;
D_op = 6'b000001;
D_func = 6'b000001;
D_valC = 1;
d_valA = 1;
d_valB = 1;
d_dstE = 1;
d_dstM = 1;
d_srcA = 1;
d_srcB = 1;
#10;
D_op = 6'b000010;
D_func = 6'b000010;
D_valC = 2;
d_valA = 2;
d_valB = 2;
d_dstE = 2;
d_dstM = 2;
d_srcA = 2;
d_srcB = 2;
#10;
D_op = 6'b000011;
D_func = 6'b000011;
D_valC = 3;
d_valA = 3;
d_valB = 3;
d_dstE = 3;
d_dstM = 3;
d_srcA = 3;
d_srcB = 3;
#10;
E_bubble = 0;
D_op = 6'b000100;
D_func = 6'b000100;
D_valC = 4;
d_valA = 4;
d_valB = 4;
d_dstE = 4;
d_dstM = 4;
d_srcA = 4;
d_srcB = 4;
#10;
D_op = 6'b000101;
D_func = 6'b000101;
D_valC = 5;
d_valA = 5;
d_valB = 5;
d_dstE = 5;
d_dstM = 5;
d_srcA = 5;
d_srcB = 5;
end
initial begin
repeat(8)
#10 clk=~clk;
end
initial begin
$monitor("time = ", $time, " E_op=%b, E_func=%b, E_valC=%d, E_valA=%d, E_valB=%d, E_dstE=%b, E_dstM=%b, E_srcA=%b, E_srcB=%b", E_op, E_func, E_valC, E_valA, E_valB, E_dstE, E_dstM, E_srcA, E_srcB);
end
endmodule | module test_E_reg; |
reg clk;
reg E_bubble;
reg [5:0] D_op;
reg [5:0] D_func;
reg [31:0] D_valC;
reg [31:0] d_valA;
reg [31:0] d_valB;
reg [4:0] d_dstE;
reg [4:0] d_dstM;
reg [4:0] d_srcA;
reg [4:0] d_srcB;
wire [5:0] E_op;
wire [5:0] E_func;
wire [31:0] E_valC;
wire [31:0] E_valA;
wire [31:0] E_valB;
wire [4:0] E_dstE;
wire [4:0] E_dstM;
wire [4:0] E_srcA;
wire [4:0] E_srcB;
parameter stop_time = 80;
E_reg E_REG(E_op, E_func, E_valC, E_valA, E_valB, E_dstE, E_dstM, E_srcA, E_srcB, clk, E_bubble, D_op, D_func, D_valC, d_valA, d_valB, d_dstE, d_dstM, d_srcA, d_srcB);
initial #stop_time $finish;
initial begin
E_bubble = 0;
clk = 0;
#10;
D_op = 6'b000001;
D_func = 6'b000001;
D_valC = 1;
d_valA = 1;
d_valB = 1;
d_dstE = 1;
d_dstM = 1;
d_srcA = 1;
d_srcB = 1;
#10;
D_op = 6'b000010;
D_func = 6'b000010;
D_valC = 2;
d_valA = 2;
d_valB = 2;
d_dstE = 2;
d_dstM = 2;
d_srcA = 2;
d_srcB = 2;
#10;
D_op = 6'b000011;
D_func = 6'b000011;
D_valC = 3;
d_valA = 3;
d_valB = 3;
d_dstE = 3;
d_dstM = 3;
d_srcA = 3;
d_srcB = 3;
#10;
E_bubble = 0;
D_op = 6'b000100;
D_func = 6'b000100;
D_valC = 4;
d_valA = 4;
d_valB = 4;
d_dstE = 4;
d_dstM = 4;
d_srcA = 4;
d_srcB = 4;
#10;
D_op = 6'b000101;
D_func = 6'b000101;
D_valC = 5;
d_valA = 5;
d_valB = 5;
d_dstE = 5;
d_dstM = 5;
d_srcA = 5;
d_srcB = 5;
end
initial begin
repeat(8)
#10 clk=~clk;
end
initial begin
$monitor("time = ", $time, " E_op=%b, E_func=%b, E_valC=%d, E_valA=%d, E_valB=%d, E_dstE=%b, E_dstM=%b, E_srcA=%b, E_srcB=%b", E_op, E_func, E_valC, E_valA, E_valB, E_dstE, E_dstM, E_srcA, E_srcB);
end
endmodule | 2 |
5,667 | data/full_repos/permissive/114553631/test/test_fwdA.v | 114,553,631 | test_fwdA.v | v | 74 | 120 | [] | [] | [] | null | line:80: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:6: Cannot find include file: ../src/fwdA.v\n`include "../src/fwdA.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/fwdA.v.sv\n ../src/fwdA.v\n ../src/fwdA.v.v\n ../src/fwdA.v.sv\n obj_dir/../src/fwdA.v\n obj_dir/../src/fwdA.v.v\n obj_dir/../src/fwdA.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:27: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:30: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./logs/test_fwdA.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:35: Define or directive not defined: \'`RNONE\'\n d_srcA = `RNONE;\n ^~~~~~\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n d_srcA = `RNONE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_fwdA.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_fwdA.v:69: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);\n ^~~~~~~~\n%Error: Exiting due to 6 error(s), 9 warning(s)\n' | 6,428 | module | module test_fwdA;
reg [4:0] d_srcA;
reg [4:0] E_dstE;
reg [4:0] M_dstM;
reg [4:0] M_dstE;
reg [4:0] W_dstM;
reg [4:0] W_dstE;
reg [31:0] d_rvalA;
reg [31:0] e_valE;
reg [31:0] m_valM;
reg [31:0] M_valE;
reg [31:0] W_valM;
reg [31:0] W_valE;
wire [31:0] d_valA;
parameter stop_time = 80;
fwdA FWDA(d_valA, d_srcA, E_dstE, M_dstM, M_dstE, W_dstM, W_dstE, d_rvalA, e_valE, m_valM, M_valE, W_valM, W_valE);
initial #stop_time $finish;
initial begin
$dumpfile("./logs/test_fwdA.vcd");
$dumpvars();
d_srcA = 0;
d_rvalA = 0;
#10;
d_srcA = `RNONE;
d_rvalA = 1;
#10;
d_srcA = 5'b10101;
E_dstE = 5'b10101;
e_valE = 2;
#10;
d_srcA = 5'b10110;
M_dstE = 5'b10110;
M_valE = 3;
#10;
d_srcA = 5'b10111;
M_dstM = 5'b10111;
m_valM = 4;
#10;
d_srcA = 5'b11000;
W_dstE = 5'b11000;
W_valE = 5;
#10;
d_srcA = 5'b11001;
W_dstM = 5'b11001;
W_valM = 6;
#10;
d_srcA = 5'b11010;
E_dstE = 5'b00001;
M_dstE = 5'b00010;
M_dstM = 5'b00011;
W_dstE = 5'b00100;
W_dstM = 5'b00101;
d_rvalA = 7;
#10;
end
initial begin
$monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);
end
endmodule | module test_fwdA; |
reg [4:0] d_srcA;
reg [4:0] E_dstE;
reg [4:0] M_dstM;
reg [4:0] M_dstE;
reg [4:0] W_dstM;
reg [4:0] W_dstE;
reg [31:0] d_rvalA;
reg [31:0] e_valE;
reg [31:0] m_valM;
reg [31:0] M_valE;
reg [31:0] W_valM;
reg [31:0] W_valE;
wire [31:0] d_valA;
parameter stop_time = 80;
fwdA FWDA(d_valA, d_srcA, E_dstE, M_dstM, M_dstE, W_dstM, W_dstE, d_rvalA, e_valE, m_valM, M_valE, W_valM, W_valE);
initial #stop_time $finish;
initial begin
$dumpfile("./logs/test_fwdA.vcd");
$dumpvars();
d_srcA = 0;
d_rvalA = 0;
#10;
d_srcA = `RNONE;
d_rvalA = 1;
#10;
d_srcA = 5'b10101;
E_dstE = 5'b10101;
e_valE = 2;
#10;
d_srcA = 5'b10110;
M_dstE = 5'b10110;
M_valE = 3;
#10;
d_srcA = 5'b10111;
M_dstM = 5'b10111;
m_valM = 4;
#10;
d_srcA = 5'b11000;
W_dstE = 5'b11000;
W_valE = 5;
#10;
d_srcA = 5'b11001;
W_dstM = 5'b11001;
W_valM = 6;
#10;
d_srcA = 5'b11010;
E_dstE = 5'b00001;
M_dstE = 5'b00010;
M_dstM = 5'b00011;
W_dstE = 5'b00100;
W_dstM = 5'b00101;
d_rvalA = 7;
#10;
end
initial begin
$monitor("time = ", $time, " valA=%d, srcA=%b", d_valA, d_srcA);
end
endmodule | 2 |
5,669 | data/full_repos/permissive/114553631/test/test_F_reg.v | 114,553,631 | test_F_reg.v | v | 52 | 97 | [] | [] | [] | null | line:42: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_F_reg.v:6: Cannot find include file: ../src/F_reg.v\n`include "../src/F_reg.v" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/F_reg.v.sv\n ../src/F_reg.v\n ../src/F_reg.v.v\n ../src/F_reg.v.sv\n obj_dir/../src/F_reg.v\n obj_dir/../src/F_reg.v.v\n obj_dir/../src/F_reg.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:18: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:21: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_F_reg.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_F_reg.v:46: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n' | 6,430 | module | module test_F_reg;
reg [31:0] f_valP = 0;
reg clk = 0;
reg F_stall = 0;
wire [31:0] F_valP;
parameter stop_time = 80;
F_reg FREG(F_valP, f_valP, clk, F_stall);
initial #stop_time $finish;
initial begin
#10;
f_valP = 4;
#10;
f_valP = 8;
#10;
F_stall = 1;
f_valP = 12;
#10;
f_valP = 16;
#10;
f_valP = 20;
#10;
F_stall = 0;
f_valP = 24;
#10;
f_valP = 28;
#10;
end
initial begin
repeat(8)
#10 clk = ~clk;
end
initial begin
$monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);
end
endmodule | module test_F_reg; |
reg [31:0] f_valP = 0;
reg clk = 0;
reg F_stall = 0;
wire [31:0] F_valP;
parameter stop_time = 80;
F_reg FREG(F_valP, f_valP, clk, F_stall);
initial #stop_time $finish;
initial begin
#10;
f_valP = 4;
#10;
f_valP = 8;
#10;
F_stall = 1;
f_valP = 12;
#10;
f_valP = 16;
#10;
f_valP = 20;
#10;
F_stall = 0;
f_valP = 24;
#10;
f_valP = 28;
#10;
end
initial begin
repeat(8)
#10 clk = ~clk;
end
initial begin
$monitor("time = ", $time, "F_ValP=%d, F_stall=%d, f_valP=%d", F_valP, F_stall, f_valP);
end
endmodule | 2 |
5,672 | data/full_repos/permissive/114553631/test/test_reg_file.v | 114,553,631 | test_reg_file.v | v | 65 | 106 | [] | [] | [] | null | line:125: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_reg_file.v:6: Cannot find include file: ../src/reg_file.v\n`include "../src/reg_file.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/reg_file.v.sv\n ../src/reg_file.v\n ../src/reg_file.v.v\n ../src/reg_file.v.sv\n obj_dir/../src/reg_file.v\n obj_dir/../src/reg_file.v.v\n obj_dir/../src/reg_file.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:23: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:29: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_reg_file.v:56: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk; \n ^\n%Error: data/full_repos/permissive/114553631/test/test_reg_file.v:60: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n' | 6,435 | module | module test_reg_file;
wire [31:0] d_rvalA;
wire [31:0] d_rvalB;
reg clk = 0;
reg [4:0] d_srcA;
reg [4:0] d_srcB;
reg [4:0] W_dstM;
reg [4:0] W_dstE;
reg [31:0] W_valM;
reg [31:0] W_valE;
parameter stop_time = 50;
reg_file REG_FILE(d_rvalA, d_rvalB, clk, d_srcA, d_srcB, W_dstM, W_dstE, W_valM, W_valE);
initial #stop_time $finish;
initial begin
clk = 0;
d_srcA = 0;
d_srcB = 0;
#5;
W_dstE = 1;
W_dstM = 2;
W_valE = 1;
W_valM = 2;
#5;
d_srcA = 1;
d_srcB = 2;
#5;
W_dstE = 1;
W_dstM = 2;
W_valE = 3;
W_valM = 4;
#5;
d_srcA = 0;
d_srcB = 0;
#5;
W_dstE = 0;
W_valE = 5;
#5;
d_srcA = 2;
d_srcB = 1;
#5;
end
initial begin
repeat(10)
#5 clk=~clk;
end
initial begin
$monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);
end
endmodule | module test_reg_file; |
wire [31:0] d_rvalA;
wire [31:0] d_rvalB;
reg clk = 0;
reg [4:0] d_srcA;
reg [4:0] d_srcB;
reg [4:0] W_dstM;
reg [4:0] W_dstE;
reg [31:0] W_valM;
reg [31:0] W_valE;
parameter stop_time = 50;
reg_file REG_FILE(d_rvalA, d_rvalB, clk, d_srcA, d_srcB, W_dstM, W_dstE, W_valM, W_valE);
initial #stop_time $finish;
initial begin
clk = 0;
d_srcA = 0;
d_srcB = 0;
#5;
W_dstE = 1;
W_dstM = 2;
W_valE = 1;
W_valM = 2;
#5;
d_srcA = 1;
d_srcB = 2;
#5;
W_dstE = 1;
W_dstM = 2;
W_valE = 3;
W_valM = 4;
#5;
d_srcA = 0;
d_srcB = 0;
#5;
W_dstE = 0;
W_valE = 5;
#5;
d_srcA = 2;
d_srcB = 1;
#5;
end
initial begin
repeat(10)
#5 clk=~clk;
end
initial begin
$monitor("time = ", $time, " srcA=%d srcB=%d valA=%d valB=%d", d_srcA, d_srcB, d_rvalA, d_rvalB);
end
endmodule | 2 |
5,673 | data/full_repos/permissive/114553631/test/test_srcB.v | 114,553,631 | test_srcB.v | v | 42 | 90 | [] | [] | [] | null | line:49: before: "$" | null | 1: b'%Error: data/full_repos/permissive/114553631/test/test_srcB.v:6: Cannot find include file: ../src/srcB.v\n`include "../src/srcB.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v.v\n data/full_repos/permissive/114553631/test,data/full_repos/permissive/114553631/../src/srcB.v.sv\n ../src/srcB.v\n ../src/srcB.v.v\n ../src/srcB.v.sv\n obj_dir/../src/srcB.v\n obj_dir/../src/srcB.v.v\n obj_dir/../src/srcB.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:17: Unsupported: Ignoring delay on this delayed statement.\n initial #stop_time $finish; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:21: Define or directive not defined: \'`IROP\'\n D_op = `IROP;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n D_op = `IROP;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:23: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:24: Define or directive not defined: \'`IJ\'\n D_op = `IJ;\n ^~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n D_op = `IJ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:27: Define or directive not defined: \'`ISW\'\n D_op = `ISW;\n ^~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n D_op = `ISW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:31: Define or directive not defined: \'`IROP\'\n D_op = `IROP;\n ^~~~~\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:31: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n D_op = `IROP;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114553631/test/test_srcB.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/114553631/test/test_srcB.v:37: Unsupported or unknown PLI call: $monitor\n $monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB); \n ^~~~~~~~\n%Error: Exiting due to 10 error(s), 7 warning(s)\n' | 6,437 | module | module test_srcB;
reg [5:0] D_op = 0;
reg [4:0] D_rs = 0;
wire [4:0] d_srcB;
parameter stop_time = 80;
srcB SRCB(d_srcB, D_op, D_rs);
initial #stop_time $finish;
initial begin
#10;
D_op = `IROP;
D_rs = 5'b10011;
#10;
D_op = `IJ;
D_rs = 5'b10000;
#10;
D_op = `ISW;
#10;
D_rs = 5'b10010;
#10;
D_op = `IROP;
D_rs = 5'b01011;
#10;
end
initial begin
$monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB);
end
endmodule | module test_srcB; |
reg [5:0] D_op = 0;
reg [4:0] D_rs = 0;
wire [4:0] d_srcB;
parameter stop_time = 80;
srcB SRCB(d_srcB, D_op, D_rs);
initial #stop_time $finish;
initial begin
#10;
D_op = `IROP;
D_rs = 5'b10011;
#10;
D_op = `IJ;
D_rs = 5'b10000;
#10;
D_op = `ISW;
#10;
D_rs = 5'b10010;
#10;
D_op = `IROP;
D_rs = 5'b01011;
#10;
end
initial begin
$monitor("time = ", $time, " op=%b rs=%d srcB=%d", D_op, D_rs, d_srcB);
end
endmodule | 2 |
5,674 | data/full_repos/permissive/11455462/90522175_3(tb) (1).v | 11,455,462 | 90522175_3(tb) (1).v | v | 27 | 35 | [] | [] | [] | null | line:7 column:16: Illegal character "'" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:8: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:10: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:12: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:14: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:16: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:18: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:20: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:22: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522175_3(tb).v:24: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,439 | module | module tb_BCD_Seven_segment();
reg [3:0] in;
wire [6:0] out;
BCD_Seven_segment Bss(in,out);
initial
begin
in = 4'b 0000;
#40;
in = 4'b 0001;
#40;
in = 4'b 0010;
#40;
in = 4'b 0011;
#40;
in = 4'b 0100;
#40;
in = 4'b 0101;
#40;
in = 4'b 0110;
#40;
in = 4'b 0111;
#40;
in = 4'b 1000;
#40;
in = 4'b 1001;
end
endmodule | module tb_BCD_Seven_segment(); |
reg [3:0] in;
wire [6:0] out;
BCD_Seven_segment Bss(in,out);
initial
begin
in = 4'b 0000;
#40;
in = 4'b 0001;
#40;
in = 4'b 0010;
#40;
in = 4'b 0011;
#40;
in = 4'b 0100;
#40;
in = 4'b 0101;
#40;
in = 4'b 0110;
#40;
in = 4'b 0111;
#40;
in = 4'b 1000;
#40;
in = 4'b 1001;
end
endmodule | 0 |
5,675 | data/full_repos/permissive/11455462/90522175_3.v | 11,455,462 | 90522175_3.v | v | 20 | 42 | [] | [] | [] | null | line:8 column:15: Illegal character "'" | data/verilator_xmls/518eddaf-c787-4b54-96ae-fd0871142817.xml | null | 6,441 | module | module BCD_Seven_segment(in,out);
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(in)
begin
case(in)
4'b 0000 : out = 7'b 1111110;
4'b 0001 : out = 7'b 0110000;
4'b 0010 : out = 7'b 1101110;
4'b 0011 : out = 7'b 1111001;
4'b 0100 : out = 7'b 0110011;
4'b 0101 : out = 7'b 1011011;
4'b 0110 : out = 7'b 1011111;
4'b 0111 : out = 7'b 1110000;
4'b 1000 : out = 7'b 1111111;
4'b 1001 : out = 7'b 1111011;
endcase
end
endmodule | module BCD_Seven_segment(in,out); |
input [3:0] in;
output [6:0] out;
reg [6:0] out;
always @(in)
begin
case(in)
4'b 0000 : out = 7'b 1111110;
4'b 0001 : out = 7'b 0110000;
4'b 0010 : out = 7'b 1101110;
4'b 0011 : out = 7'b 1111001;
4'b 0100 : out = 7'b 0110011;
4'b 0101 : out = 7'b 1011011;
4'b 0110 : out = 7'b 1011111;
4'b 0111 : out = 7'b 1110000;
4'b 1000 : out = 7'b 1111111;
4'b 1001 : out = 7'b 1111011;
endcase
end
endmodule | 0 |
5,676 | data/full_repos/permissive/11455462/90522229_1.v | 11,455,462 | 90522229_1.v | v | 18 | 40 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/2c51b98c-39dd-4664-ad1b-f3ae90b40834.xml | null | 6,442 | module | module Mux4_1(z,a0,a1,a2,a3,ctr0,ctr1);
input a0,a1,a2,a3,ctr0,ctr1;
output z;
wire w1,w2,w3,w4,w5,w6;
not n1(w5,ctr0);
not n2(w6,ctr1);
and a4(w4,ctr0,ctr1);
and a11(w1,w5,w6);
and a21(w2,ctr0,w6);
and a31(w3,w5,ctr1);
bufif1 if1(z,a0,w1);
bufif1 if2(z,a1,w2);
bufif1 if3(z,a2,w3);
bufif1 if4(z,a3,w4);
endmodule | module Mux4_1(z,a0,a1,a2,a3,ctr0,ctr1); |
input a0,a1,a2,a3,ctr0,ctr1;
output z;
wire w1,w2,w3,w4,w5,w6;
not n1(w5,ctr0);
not n2(w6,ctr1);
and a4(w4,ctr0,ctr1);
and a11(w1,w5,w6);
and a21(w2,ctr0,w6);
and a31(w3,w5,ctr1);
bufif1 if1(z,a0,w1);
bufif1 if2(z,a1,w2);
bufif1 if3(z,a2,w3);
bufif1 if4(z,a3,w4);
endmodule | 0 |
5,677 | data/full_repos/permissive/11455462/90522229_2 (1).v | 11,455,462 | 90522229_2 (1).v | v | 19 | 26 | [] | [] | [] | [(1, 19)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:8: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:10: Unsupported: Ignoring delay on this delayed statement.\n#10 \n^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_2.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 \n^\n%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,443 | module | module encode_tb();
reg in,out,en;
initial begin
en = 1;
in = 1;
#10
in = 2;
#10
in = 4;
#10
in = 8;
end
encode24 test(out,in,en);
endmodule | module encode_tb(); |
reg in,out,en;
initial begin
en = 1;
in = 1;
#10
in = 2;
#10
in = 4;
#10
in = 8;
end
encode24 test(out,in,en);
endmodule | 0 |
5,678 | data/full_repos/permissive/11455462/90522229_2_tb.v | 11,455,462 | 90522229_2_tb.v | v | 23 | 45 | [] | [] | [] | [(1, 21)] | null | data/verilator_xmls/3c29ae58-5664-4bb7-a6fe-510c9b16c69f.xml | null | 6,446 | module | module encode24 (b_output, b_input, enable);
output [1:0] b_output;
input enable ;
input [3:0] b_input ;
reg [1:0] b_output;
always @(*) begin
if (enable)
begin
b_output = 0;
if(b_input==8)
b_output=1;
else if(b_input==4)
b_output=2;
else if(b_input==2)
b_output=3;
end
end
endmodule | module encode24 (b_output, b_input, enable); |
output [1:0] b_output;
input enable ;
input [3:0] b_input ;
reg [1:0] b_output;
always @(*) begin
if (enable)
begin
b_output = 0;
if(b_input==8)
b_output=1;
else if(b_input==4)
b_output=2;
else if(b_input==2)
b_output=3;
end
end
endmodule | 0 |
5,679 | data/full_repos/permissive/11455462/90522229_4 (1).v | 11,455,462 | 90522229_4 (1).v | v | 21 | 53 | [] | [] | [] | null | line:4 column:33: Illegal character "'" | null | 1: b'%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,449 | module | module bcd_greey(a,b,c,d,in);
input [3:0] in ;
output a,b,c,d ;
assign {a,b,c,d} = (in == 4'b 0000) ? 4'b 0000 :
(in == 4'b 0001) ? 4'b 0001 :
(in == 4'b 0010) ? 4'b 0011 :
(in == 4'b 0011) ? 4'b 0010 :
(in == 4'b 0100) ? 4'b 0110 :
(in == 4'b 0101) ? 4'b 0111 :
(in == 4'b 0110) ? 4'b 0101 :
(in == 4'b 0111) ? 4'b 0100 :
(in == 4'b 1000) ? 4'b 1100 :
(in == 4'b 1001) ? 4'b 1101 :
(in == 4'b 1010) ? 4'b 1111 :
(in == 4'b 1011) ? 4'b 1110 :
(in == 4'b 1100) ? 4'b 1010 :
(in == 4'b 1101) ? 4'b 1011 :
(in == 4'b 1110) ? 4'b 1001 :
(in == 4'b 1111) ? 4'b 1000 : 4'b0000 ;
endmodule | module bcd_greey(a,b,c,d,in); |
input [3:0] in ;
output a,b,c,d ;
assign {a,b,c,d} = (in == 4'b 0000) ? 4'b 0000 :
(in == 4'b 0001) ? 4'b 0001 :
(in == 4'b 0010) ? 4'b 0011 :
(in == 4'b 0011) ? 4'b 0010 :
(in == 4'b 0100) ? 4'b 0110 :
(in == 4'b 0101) ? 4'b 0111 :
(in == 4'b 0110) ? 4'b 0101 :
(in == 4'b 0111) ? 4'b 0100 :
(in == 4'b 1000) ? 4'b 1100 :
(in == 4'b 1001) ? 4'b 1101 :
(in == 4'b 1010) ? 4'b 1111 :
(in == 4'b 1011) ? 4'b 1110 :
(in == 4'b 1100) ? 4'b 1010 :
(in == 4'b 1101) ? 4'b 1011 :
(in == 4'b 1110) ? 4'b 1001 :
(in == 4'b 1111) ? 4'b 1000 : 4'b0000 ;
endmodule | 0 |
5,680 | data/full_repos/permissive/11455462/90522229_4_tb.v | 11,455,462 | 90522229_4_tb.v | v | 17 | 31 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_4_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #30 \n ^\n%Error: data/full_repos/permissive/11455462/90522229_4_tb.v:4: Cannot find file containing module: \'bcd_greey\'\n bcd_greey test(a,b,c,d,in);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/bcd_greey.sv\n bcd_greey\n bcd_greey.v\n bcd_greey.sv\n obj_dir/bcd_greey\n obj_dir/bcd_greey.v\n obj_dir/bcd_greey.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,451 | module | module bcd_greey_tb;
reg [3:0] in;
wire a,b,c,d;
bcd_greey test(a,b,c,d,in);
initial
begin
in = 4'b0000;
#30
in = 4'b0001;
#30
in = 4'b0010;
#30
in = 4'b1111;
end
endmodule | module bcd_greey_tb; |
reg [3:0] in;
wire a,b,c,d;
bcd_greey test(a,b,c,d,in);
initial
begin
in = 4'b0000;
#30
in = 4'b0001;
#30
in = 4'b0010;
#30
in = 4'b1111;
end
endmodule | 0 |
5,681 | data/full_repos/permissive/11455462/90522229_5 (1).v | 11,455,462 | 90522229_5 (1).v | v | 35 | 59 | [] | [] | [] | [(1, 34)] | null | null | 1: b'%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,452 | module | module elv_sim( u1, u2, pos1, pos2, source, st);
input [1:0]pos1;
input[1:0]pos2;
input [1:0]source;
input st;
output u1,u2;
reg u1,u2;
always @(st)
begin
if( (pos1-source) > (pos2-source) )
begin
if( pos1 > source )
u1 = 0;
else
u1 = 1;
end
else
begin
if( pos2 > source)
u2 = 0;
else
u2 = 1;
end
end
endmodule | module elv_sim( u1, u2, pos1, pos2, source, st); |
input [1:0]pos1;
input[1:0]pos2;
input [1:0]source;
input st;
output u1,u2;
reg u1,u2;
always @(st)
begin
if( (pos1-source) > (pos2-source) )
begin
if( pos1 > source )
u1 = 0;
else
u1 = 1;
end
else
begin
if( pos2 > source)
u2 = 0;
else
u2 = 1;
end
end
endmodule | 0 |
5,682 | data/full_repos/permissive/11455462/90522229_5_tb.v | 11,455,462 | 90522229_5_tb.v | v | 32 | 41 | [] | [] | [] | [(1, 30)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_5_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/90522229_5_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/11455462/90522229_5_tb.v:9: Cannot find file containing module: \'elv_sim\'\nelv_sim test(u1,u2,pos1,pos2,source,st);\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/elv_sim.sv\n elv_sim\n elv_sim.v\n elv_sim.sv\n obj_dir/elv_sim\n obj_dir/elv_sim.v\n obj_dir/elv_sim.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,454 | module | module elv_test();
reg [1:0]source;
reg st;
reg [1:0]pos1;
reg [1:0]pos2;
wire u1,u2;
elv_sim test(u1,u2,pos1,pos2,source,st);
initial
begin
pos1 = 2'b11;
pos2 = 2'b00;
#40
st =1;
source = 2'b10;
#10
st = 1;
source = 2'b01;
end
endmodule | module elv_test(); |
reg [1:0]source;
reg st;
reg [1:0]pos1;
reg [1:0]pos2;
wire u1,u2;
elv_sim test(u1,u2,pos1,pos2,source,st);
initial
begin
pos1 = 2'b11;
pos2 = 2'b00;
#40
st =1;
source = 2'b10;
#10
st = 1;
source = 2'b01;
end
endmodule | 0 |
5,683 | data/full_repos/permissive/11455462/9052229_1_tb.v | 11,455,462 | 9052229_1_tb.v | v | 25 | 39 | [] | [] | [] | [(1, 24)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/11455462/9052229_1_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/11455462/9052229_1_tb.v:23: Cannot find file containing module: \'Mux4_1\'\nMux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1.v\n data/full_repos/permissive/11455462,data/full_repos/permissive/11455462/Mux4_1.sv\n Mux4_1\n Mux4_1.v\n Mux4_1.sv\n obj_dir/Mux4_1\n obj_dir/Mux4_1.v\n obj_dir/Mux4_1.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,455 | module | module tb();
reg a0,a1,a2,a3,ctr0,ctr1;
wire z;
initial begin
a0 = 0;
ctr0 = 1;
ctr1 = 1;
#100
a1 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a2 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a3 = 1;
ctr0 = 1;
ctr1 = 1;
end
Mux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);
endmodule | module tb(); |
reg a0,a1,a2,a3,ctr0,ctr1;
wire z;
initial begin
a0 = 0;
ctr0 = 1;
ctr1 = 1;
#100
a1 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a2 = 1;
ctr0 = 1;
ctr1 = 1;
#100
a3 = 1;
ctr0 = 1;
ctr1 = 1;
end
Mux4_1 ramin(z,a0,a1,a2,a3,ctr0,ctr1);
endmodule | 0 |
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