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5,340 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter5_1/id.v | 113,839,829 | id.v | v | 149 | 80 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xd2 in position 1806: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter5_1,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter5_1/id.v\n%Error: Exiting due to 3 error(s)\n' | 5,918 | module | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o
);
wire[5:0] op = inst_i[31:26];
wire[4:0] op2 = inst_i[10:6];
wire[5:0] op3 = inst_i[5:0];
wire[4:0] op4 = inst_i[20:16];
reg[`RegBus] imm;
reg instvalid;
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[15:11];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[25:21];
reg2_addr_o <= inst_i[20:16];
imm <= `ZeroWord;
case (op)
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
default: begin
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o
); |
wire[5:0] op = inst_i[31:26];
wire[4:0] op2 = inst_i[10:6];
wire[5:0] op3 = inst_i[5:0];
wire[4:0] op4 = inst_i[20:16];
reg[`RegBus] imm;
reg instvalid;
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[15:11];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[25:21];
reg2_addr_o <= inst_i[20:16];
imm <= `ZeroWord;
case (op)
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
default: begin
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | 48 |
5,341 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter5_2/ex.v | 113,839,829 | ex.v | v | 120 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xd0 in position 1808: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter5_2,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter5_2/ex.v\n%Error: Exiting due to 3 error(s)\n' | 5,930 | module | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o
);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o
); |
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | 48 |
5,344 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter7_1/ex.v | 113,839,829 | ex.v | v | 315 | 86 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xd0 in position 1808: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter7_1,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter7_1/ex.v\n%Error: Exiting due to 3 error(s)\n' | 5,959 | module | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
input wire[`RegBus] wb_hi_i,
input wire[`RegBus] wb_lo_i,
input wire wb_whilo_i,
input wire[`RegBus] mem_hi_i,
input wire[`RegBus] mem_lo_i,
input wire mem_whilo_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o,
output reg whilo_o
);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] moveres;
reg[`RegBus] arithmeticres;
reg[`DoubleRegBus] mulres;
reg[`RegBus] HI;
reg[`RegBus] LO;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
wire ov_sum;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] opdata1_mult;
wire[`RegBus] opdata2_mult;
wire[`DoubleRegBus] hilo_temp;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) || (aluop_i == `EXE_SUBU_OP) ||
(aluop_i == `EXE_SLT_OP) )
? (~reg2_i)+1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
assign ov_sum = ((!reg1_i[31] && !reg2_i_mux[31]) && result_sum[31]) ||
((reg1_i[31] && reg2_i_mux[31]) && (!result_sum[31]));
assign reg1_lt_reg2 = ((aluop_i == `EXE_SLT_OP)) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31])||
(reg1_i[31] && reg2_i[31] && result_sum[31]))
: (reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2 ;
end
`EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP, `EXE_SUBU_OP: begin
arithmeticres <= result_sum;
end
`EXE_CLZ_OP: begin
arithmeticres <= reg1_i[31] ? 0 : reg1_i[30] ? 1 : reg1_i[29] ? 2 :
reg1_i[28] ? 3 : reg1_i[27] ? 4 : reg1_i[26] ? 5 :
reg1_i[25] ? 6 : reg1_i[24] ? 7 : reg1_i[23] ? 8 :
reg1_i[22] ? 9 : reg1_i[21] ? 10 : reg1_i[20] ? 11 :
reg1_i[19] ? 12 : reg1_i[18] ? 13 : reg1_i[17] ? 14 :
reg1_i[16] ? 15 : reg1_i[15] ? 16 : reg1_i[14] ? 17 :
reg1_i[13] ? 18 : reg1_i[12] ? 19 : reg1_i[11] ? 20 :
reg1_i[10] ? 21 : reg1_i[9] ? 22 : reg1_i[8] ? 23 :
reg1_i[7] ? 24 : reg1_i[6] ? 25 : reg1_i[5] ? 26 :
reg1_i[4] ? 27 : reg1_i[3] ? 28 : reg1_i[2] ? 29 :
reg1_i[1] ? 30 : reg1_i[0] ? 31 : 32 ;
end
`EXE_CLO_OP: begin
arithmeticres <= (reg1_i_not[31] ? 0 : reg1_i_not[30] ? 1 : reg1_i_not[29] ? 2 :
reg1_i_not[28] ? 3 : reg1_i_not[27] ? 4 : reg1_i_not[26] ? 5 :
reg1_i_not[25] ? 6 : reg1_i_not[24] ? 7 : reg1_i_not[23] ? 8 :
reg1_i_not[22] ? 9 : reg1_i_not[21] ? 10 : reg1_i_not[20] ? 11 :
reg1_i_not[19] ? 12 : reg1_i_not[18] ? 13 : reg1_i_not[17] ? 14 :
reg1_i_not[16] ? 15 : reg1_i_not[15] ? 16 : reg1_i_not[14] ? 17 :
reg1_i_not[13] ? 18 : reg1_i_not[12] ? 19 : reg1_i_not[11] ? 20 :
reg1_i_not[10] ? 21 : reg1_i_not[9] ? 22 : reg1_i_not[8] ? 23 :
reg1_i_not[7] ? 24 : reg1_i_not[6] ? 25 : reg1_i_not[5] ? 26 :
reg1_i_not[4] ? 27 : reg1_i_not[3] ? 28 : reg1_i_not[2] ? 29 :
reg1_i_not[1] ? 30 : reg1_i_not[0] ? 31 : 32) ;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
assign opdata1_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP))
&& (reg1_i[31] == 1'b1)) ? (~reg1_i + 1) : reg1_i;
assign opdata2_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP))
&& (reg2_i[31] == 1'b1)) ? (~reg2_i + 1) : reg2_i;
assign hilo_temp = opdata1_mult * opdata2_mult;
always @ (*) begin
if(rst == `RstEnable) begin
mulres <= {`ZeroWord,`ZeroWord};
end else if ((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP))begin
if(reg1_i[31] ^ reg2_i[31] == 1'b1) begin
mulres <= ~hilo_temp + 1;
end else begin
mulres <= hilo_temp;
end
end else begin
mulres <= hilo_temp;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
{HI,LO} <= {`ZeroWord,`ZeroWord};
end else if(mem_whilo_i == `WriteEnable) begin
{HI,LO} <= {mem_hi_i,mem_lo_i};
end else if(wb_whilo_i == `WriteEnable) begin
{HI,LO} <= {wb_hi_i,wb_lo_i};
end else begin
{HI,LO} <= {hi_i,lo_i};
end
end
always @ (*) begin
if(rst == `RstEnable) begin
moveres <= `ZeroWord;
end else begin
moveres <= `ZeroWord;
case (aluop_i)
`EXE_MFHI_OP: begin
moveres <= HI;
end
`EXE_MFLO_OP: begin
moveres <= LO;
end
`EXE_MOVZ_OP: begin
moveres <= reg1_i;
end
`EXE_MOVN_OP: begin
moveres <= reg1_i;
end
default : begin
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
if(((aluop_i == `EXE_ADD_OP) || (aluop_i == `EXE_ADDI_OP) ||
(aluop_i == `EXE_SUB_OP)) && (ov_sum == 1'b1)) begin
wreg_o <= `WriteDisable;
end else begin
wreg_o <= wreg_i;
end
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_MOVE: begin
wdata_o <= moveres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_MUL: begin
wdata_o <= mulres[31:0];
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
always @ (*) begin
if(rst == `RstEnable) begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end else if((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MULTU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= mulres[63:32];
lo_o <= mulres[31:0];
end else if(aluop_i == `EXE_MTHI_OP) begin
whilo_o <= `WriteEnable;
hi_o <= reg1_i;
lo_o <= LO;
end else if(aluop_i == `EXE_MTLO_OP) begin
whilo_o <= `WriteEnable;
hi_o <= HI;
lo_o <= reg1_i;
end else begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end
end
endmodule | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
input wire[`RegBus] wb_hi_i,
input wire[`RegBus] wb_lo_i,
input wire wb_whilo_i,
input wire[`RegBus] mem_hi_i,
input wire[`RegBus] mem_lo_i,
input wire mem_whilo_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o,
output reg whilo_o
); |
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] moveres;
reg[`RegBus] arithmeticres;
reg[`DoubleRegBus] mulres;
reg[`RegBus] HI;
reg[`RegBus] LO;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
wire ov_sum;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] opdata1_mult;
wire[`RegBus] opdata2_mult;
wire[`DoubleRegBus] hilo_temp;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_NOR_OP: begin
logicout <= ~(reg1_i |reg2_i);
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg2_i << reg1_i[4:0] ;
end
`EXE_SRL_OP: begin
shiftres <= reg2_i >> reg1_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg2_i[31]}} << (6'd32-{1'b0, reg1_i[4:0]}))
| reg2_i >> reg1_i[4:0];
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) || (aluop_i == `EXE_SUBU_OP) ||
(aluop_i == `EXE_SLT_OP) )
? (~reg2_i)+1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
assign ov_sum = ((!reg1_i[31] && !reg2_i_mux[31]) && result_sum[31]) ||
((reg1_i[31] && reg2_i_mux[31]) && (!result_sum[31]));
assign reg1_lt_reg2 = ((aluop_i == `EXE_SLT_OP)) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31])||
(reg1_i[31] && reg2_i[31] && result_sum[31]))
: (reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2 ;
end
`EXE_ADD_OP, `EXE_ADDU_OP, `EXE_ADDI_OP, `EXE_ADDIU_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP, `EXE_SUBU_OP: begin
arithmeticres <= result_sum;
end
`EXE_CLZ_OP: begin
arithmeticres <= reg1_i[31] ? 0 : reg1_i[30] ? 1 : reg1_i[29] ? 2 :
reg1_i[28] ? 3 : reg1_i[27] ? 4 : reg1_i[26] ? 5 :
reg1_i[25] ? 6 : reg1_i[24] ? 7 : reg1_i[23] ? 8 :
reg1_i[22] ? 9 : reg1_i[21] ? 10 : reg1_i[20] ? 11 :
reg1_i[19] ? 12 : reg1_i[18] ? 13 : reg1_i[17] ? 14 :
reg1_i[16] ? 15 : reg1_i[15] ? 16 : reg1_i[14] ? 17 :
reg1_i[13] ? 18 : reg1_i[12] ? 19 : reg1_i[11] ? 20 :
reg1_i[10] ? 21 : reg1_i[9] ? 22 : reg1_i[8] ? 23 :
reg1_i[7] ? 24 : reg1_i[6] ? 25 : reg1_i[5] ? 26 :
reg1_i[4] ? 27 : reg1_i[3] ? 28 : reg1_i[2] ? 29 :
reg1_i[1] ? 30 : reg1_i[0] ? 31 : 32 ;
end
`EXE_CLO_OP: begin
arithmeticres <= (reg1_i_not[31] ? 0 : reg1_i_not[30] ? 1 : reg1_i_not[29] ? 2 :
reg1_i_not[28] ? 3 : reg1_i_not[27] ? 4 : reg1_i_not[26] ? 5 :
reg1_i_not[25] ? 6 : reg1_i_not[24] ? 7 : reg1_i_not[23] ? 8 :
reg1_i_not[22] ? 9 : reg1_i_not[21] ? 10 : reg1_i_not[20] ? 11 :
reg1_i_not[19] ? 12 : reg1_i_not[18] ? 13 : reg1_i_not[17] ? 14 :
reg1_i_not[16] ? 15 : reg1_i_not[15] ? 16 : reg1_i_not[14] ? 17 :
reg1_i_not[13] ? 18 : reg1_i_not[12] ? 19 : reg1_i_not[11] ? 20 :
reg1_i_not[10] ? 21 : reg1_i_not[9] ? 22 : reg1_i_not[8] ? 23 :
reg1_i_not[7] ? 24 : reg1_i_not[6] ? 25 : reg1_i_not[5] ? 26 :
reg1_i_not[4] ? 27 : reg1_i_not[3] ? 28 : reg1_i_not[2] ? 29 :
reg1_i_not[1] ? 30 : reg1_i_not[0] ? 31 : 32) ;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
assign opdata1_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP))
&& (reg1_i[31] == 1'b1)) ? (~reg1_i + 1) : reg1_i;
assign opdata2_mult = (((aluop_i == `EXE_MUL_OP) || (aluop_i == `EXE_MULT_OP))
&& (reg2_i[31] == 1'b1)) ? (~reg2_i + 1) : reg2_i;
assign hilo_temp = opdata1_mult * opdata2_mult;
always @ (*) begin
if(rst == `RstEnable) begin
mulres <= {`ZeroWord,`ZeroWord};
end else if ((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MUL_OP))begin
if(reg1_i[31] ^ reg2_i[31] == 1'b1) begin
mulres <= ~hilo_temp + 1;
end else begin
mulres <= hilo_temp;
end
end else begin
mulres <= hilo_temp;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
{HI,LO} <= {`ZeroWord,`ZeroWord};
end else if(mem_whilo_i == `WriteEnable) begin
{HI,LO} <= {mem_hi_i,mem_lo_i};
end else if(wb_whilo_i == `WriteEnable) begin
{HI,LO} <= {wb_hi_i,wb_lo_i};
end else begin
{HI,LO} <= {hi_i,lo_i};
end
end
always @ (*) begin
if(rst == `RstEnable) begin
moveres <= `ZeroWord;
end else begin
moveres <= `ZeroWord;
case (aluop_i)
`EXE_MFHI_OP: begin
moveres <= HI;
end
`EXE_MFLO_OP: begin
moveres <= LO;
end
`EXE_MOVZ_OP: begin
moveres <= reg1_i;
end
`EXE_MOVN_OP: begin
moveres <= reg1_i;
end
default : begin
end
endcase
end
end
always @ (*) begin
wd_o <= wd_i;
if(((aluop_i == `EXE_ADD_OP) || (aluop_i == `EXE_ADDI_OP) ||
(aluop_i == `EXE_SUB_OP)) && (ov_sum == 1'b1)) begin
wreg_o <= `WriteDisable;
end else begin
wreg_o <= wreg_i;
end
case ( alusel_i )
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_MOVE: begin
wdata_o <= moveres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_MUL: begin
wdata_o <= mulres[31:0];
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
always @ (*) begin
if(rst == `RstEnable) begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end else if((aluop_i == `EXE_MULT_OP) || (aluop_i == `EXE_MULTU_OP)) begin
whilo_o <= `WriteEnable;
hi_o <= mulres[63:32];
lo_o <= mulres[31:0];
end else if(aluop_i == `EXE_MTHI_OP) begin
whilo_o <= `WriteEnable;
hi_o <= reg1_i;
lo_o <= LO;
end else if(aluop_i == `EXE_MTLO_OP) begin
whilo_o <= `WriteEnable;
hi_o <= HI;
lo_o <= reg1_i;
end else begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end
end
endmodule | 48 |
5,346 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter7_2/id.v | 113,839,829 | id.v | v | 379 | 87 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xd2 in position 1806: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter7_2,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter7_2/id.v\n%Error: Exiting due to 3 error(s)\n' | 5,978 | module | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire stallreq
);
wire[5:0] op = inst_i[31:26];
wire[4:0] op2 = inst_i[10:6];
wire[5:0] op3 = inst_i[5:0];
wire[4:0] op4 = inst_i[20:16];
reg[`RegBus] imm;
reg instvalid;
assign stallreq = `NoStop;
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[15:11];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[25:21];
reg2_addr_o <= inst_i[20:16];
imm <= `ZeroWord;
case (op)
`EXE_SPECIAL_INST: begin
case (op2)
5'b00000: begin
case (op3)
`EXE_OR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_AND: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_XOR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_NOR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_NOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLLV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRLV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRAV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MFHI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MFHI_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MFLO: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MFLO_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MTHI: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MTHI_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b0; instvalid <= `InstValid;
end
`EXE_MTLO: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MTLO_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b0; instvalid <= `InstValid;
end
`EXE_MOVN: begin
aluop_o <= `EXE_MOVN_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
if(reg2_o != `ZeroWord) begin
wreg_o <= `WriteEnable;
end else begin
wreg_o <= `WriteDisable;
end
end
`EXE_MOVZ: begin
aluop_o <= `EXE_MOVZ_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
if(reg2_o == `ZeroWord) begin
wreg_o <= `WriteEnable;
end else begin
wreg_o <= `WriteDisable;
end
end
`EXE_SLT: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLTU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_ADD: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_ADDU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUB: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUBU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUBU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MULT: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MULT_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
end
`EXE_MULTU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MULTU_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
end
default: begin
end
endcase
end
default: begin
end
endcase
end
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ANDI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_XORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_LUI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {inst_i[15:0], 16'h0}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SLTI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SLTIU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ADDI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDI_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ADDIU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDIU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SPECIAL2_INST: begin
case ( op3 )
`EXE_CLZ: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_CLZ_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_CLO: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_CLO_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MUL: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MUL_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MADD: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MADD_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MADDU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MADDU_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MSUB: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MSUB_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MSUBU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MSUBU_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin
end
endcase
end
default: begin
end
endcase
if (inst_i[31:21] == 11'b00000000000) begin
if (op3 == `EXE_SLL) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if ( op3 == `EXE_SRL ) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if ( op3 == `EXE_SRA ) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | module id(
input wire rst,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire stallreq
); |
wire[5:0] op = inst_i[31:26];
wire[4:0] op2 = inst_i[10:6];
wire[5:0] op3 = inst_i[5:0];
wire[4:0] op4 = inst_i[20:16];
reg[`RegBus] imm;
reg instvalid;
assign stallreq = `NoStop;
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[15:11];
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[25:21];
reg2_addr_o <= inst_i[20:16];
imm <= `ZeroWord;
case (op)
`EXE_SPECIAL_INST: begin
case (op2)
5'b00000: begin
case (op3)
`EXE_OR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_AND: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_XOR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_NOR: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_NOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLLV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRLV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SRAV: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MFHI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MFHI_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MFLO: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MFLO_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b0; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MTHI: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MTHI_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b0; instvalid <= `InstValid;
end
`EXE_MTLO: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MTLO_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b0; instvalid <= `InstValid;
end
`EXE_MOVN: begin
aluop_o <= `EXE_MOVN_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
if(reg2_o != `ZeroWord) begin
wreg_o <= `WriteEnable;
end else begin
wreg_o <= `WriteDisable;
end
end
`EXE_MOVZ: begin
aluop_o <= `EXE_MOVZ_OP;
alusel_o <= `EXE_RES_MOVE; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
if(reg2_o == `ZeroWord) begin
wreg_o <= `WriteEnable;
end else begin
wreg_o <= `WriteDisable;
end
end
`EXE_SLT: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SLTU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_ADD: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_ADDU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUB: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_SUBU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SUBU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MULT: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MULT_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
end
`EXE_MULTU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MULTU_OP;
reg1_read_o <= 1'b1; reg2_read_o <= 1'b1; instvalid <= `InstValid;
end
default: begin
end
endcase
end
default: begin
end
endcase
end
`EXE_ORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ANDI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_XORI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {16'h0, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_LUI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {inst_i[15:0], 16'h0}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SLTI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SLTIU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ADDI: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDI_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_ADDIU: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_ADDIU_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
imm <= {{16{inst_i[15]}}, inst_i[15:0]}; wd_o <= inst_i[20:16];
instvalid <= `InstValid;
end
`EXE_SPECIAL2_INST: begin
case ( op3 )
`EXE_CLZ: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_CLZ_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_CLO: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_CLO_OP;
alusel_o <= `EXE_RES_ARITHMETIC; reg1_read_o <= 1'b1; reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
`EXE_MUL: begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_MUL_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MADD: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MADD_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MADDU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MADDU_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MSUB: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MSUB_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
`EXE_MSUBU: begin
wreg_o <= `WriteDisable; aluop_o <= `EXE_MSUBU_OP;
alusel_o <= `EXE_RES_MUL; reg1_read_o <= 1'b1; reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin
end
endcase
end
default: begin
end
endcase
if (inst_i[31:21] == 11'b00000000000) begin
if (op3 == `EXE_SLL) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if ( op3 == `EXE_SRL ) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end else if ( op3 == `EXE_SRA ) begin
wreg_o <= `WriteEnable; aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT; reg1_read_o <= 1'b0; reg2_read_o <= 1'b1;
imm[4:0] <= inst_i[10:6]; wd_o <= inst_i[15:11];
instvalid <= `InstValid;
end
end
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | 48 |
5,348 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chapter9_2/mem_wb.v | 113,839,829 | mem_wb.v | v | 100 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chapter9_2,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chapter9_2/mem_wb.v\n%Error: Exiting due to 3 error(s)\n' | 6,037 | module | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
end
end
endmodule | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegAddrBus] mem_wd,
input wire mem_wreg,
input wire[`RegBus] mem_wdata,
input wire[`RegBus] mem_hi,
input wire[`RegBus] mem_lo,
input wire mem_whilo,
input wire mem_LLbit_we,
input wire mem_LLbit_value,
output reg[`RegAddrBus] wb_wd,
output reg wb_wreg,
output reg[`RegBus] wb_wdata,
output reg[`RegBus] wb_hi,
output reg[`RegBus] wb_lo,
output reg wb_whilo,
output reg wb_LLbit_we,
output reg wb_LLbit_value
); |
always @ (posedge clk) begin
if(rst == `RstEnable) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
end else if(stall[4] == `Stop && stall[5] == `NoStop) begin
wb_wd <= `NOPRegAddr;
wb_wreg <= `WriteDisable;
wb_wdata <= `ZeroWord;
wb_hi <= `ZeroWord;
wb_lo <= `ZeroWord;
wb_whilo <= `WriteDisable;
wb_LLbit_we <= 1'b0;
wb_LLbit_value <= 1'b0;
end else if(stall[4] == `NoStop) begin
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
wb_wdata <= mem_wdata;
wb_hi <= mem_hi;
wb_lo <= mem_lo;
wb_whilo <= mem_whilo;
wb_LLbit_we <= mem_LLbit_we;
wb_LLbit_value <= mem_LLbit_value;
end
end
endmodule | 48 |
5,350 | data/full_repos/permissive/113839829/Code Library/OpenMIPS/Chpater7_3/openmips.v | 113,839,829 | openmips.v | v | 393 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xb4 in position 1826: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829\n ... Looked in:\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.v\n data/full_repos/permissive/113839829/Code/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.sv\n Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829\n Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.v\n Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.sv\n obj_dir/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829\n obj_dir/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.v\n obj_dir/Library/OpenMIPS/Chpater7_3,data/full_repos/permissive/113839829.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113839829/Code\n%Error: Cannot find file containing module: Library/OpenMIPS/Chpater7_3/openmips.v\n%Error: Exiting due to 3 error(s)\n' | 6,074 | module | module openmips(
input wire clk,
input wire rst,
input wire[`RegBus] rom_data_i,
output wire[`RegBus] rom_addr_o,
output wire rom_ce_o
);
wire[`InstAddrBus] pc;
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire[`RegBus] ex_hi_o;
wire[`RegBus] ex_lo_o;
wire ex_whilo_o;
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire[`RegBus] mem_hi_i;
wire[`RegBus] mem_lo_i;
wire mem_whilo_i;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire[`RegBus] mem_hi_o;
wire[`RegBus] mem_lo_o;
wire mem_whilo_o;
wire wb_wreg_i;
wire[`RegAddrBus] wb_wd_i;
wire[`RegBus] wb_wdata_i;
wire[`RegBus] wb_hi_i;
wire[`RegBus] wb_lo_i;
wire wb_whilo_i;
wire reg1_read;
wire reg2_read;
wire[`RegBus] reg1_data;
wire[`RegBus] reg2_data;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire[`RegBus] hi;
wire[`RegBus] lo;
wire[`DoubleRegBus] hilo_temp_o;
wire[1:0] cnt_o;
wire[`DoubleRegBus] hilo_temp_i;
wire[1:0] cnt_i;
wire[`DoubleRegBus] div_result;
wire div_ready;
wire[`RegBus] div_opdata1;
wire[`RegBus] div_opdata2;
wire div_start;
wire div_annul;
wire signed_div;
wire[5:0] stall;
wire stallreq_from_id;
wire stallreq_from_ex;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(stall),
.pc(pc),
.ce(rom_ce_o)
);
assign rom_addr_o = pc;
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(stall),
.if_pc(pc),
.if_inst(rom_data_i),
.id_pc(id_pc_i),
.id_inst(id_inst_i)
);
id id0(
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.reg1_data_i(reg1_data),
.reg2_data_i(reg2_data),
.ex_wreg_i(ex_wreg_o),
.ex_wdata_i(ex_wdata_o),
.ex_wd_i(ex_wd_o),
.mem_wreg_i(mem_wreg_o),
.mem_wdata_i(mem_wdata_o),
.mem_wd_i(mem_wd_o),
.reg1_read_o(reg1_read),
.reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr),
.reg2_addr_o(reg2_addr),
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.wd_o(id_wd_o),
.wreg_o(id_wreg_o),
.stallreq(stallreq_from_id)
);
regfile regfile1(
.clk (clk),
.rst (rst),
.we (wb_wreg_i),
.waddr (wb_wd_i),
.wdata (wb_wdata_i),
.re1 (reg1_read),
.raddr1 (reg1_addr),
.rdata1 (reg1_data),
.re2 (reg2_read),
.raddr2 (reg2_addr),
.rdata2 (reg2_data)
);
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(stall),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_wd(id_wd_o),
.id_wreg(id_wreg_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_wd(ex_wd_i),
.ex_wreg(ex_wreg_i)
);
ex ex0(
.rst(rst),
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.wd_i(ex_wd_i),
.wreg_i(ex_wreg_i),
.hi_i(hi),
.lo_i(lo),
.wb_hi_i(wb_hi_i),
.wb_lo_i(wb_lo_i),
.wb_whilo_i(wb_whilo_i),
.mem_hi_i(mem_hi_o),
.mem_lo_i(mem_lo_o),
.mem_whilo_i(mem_whilo_o),
.hilo_temp_i(hilo_temp_i),
.cnt_i(cnt_i),
.div_result_i(div_result),
.div_ready_i(div_ready),
.wd_o(ex_wd_o),
.wreg_o(ex_wreg_o),
.wdata_o(ex_wdata_o),
.hi_o(ex_hi_o),
.lo_o(ex_lo_o),
.whilo_o(ex_whilo_o),
.hilo_temp_o(hilo_temp_o),
.cnt_o(cnt_o),
.div_opdata1_o(div_opdata1),
.div_opdata2_o(div_opdata2),
.div_start_o(div_start),
.signed_div_o(signed_div),
.stallreq(stallreq_from_ex)
);
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(stall),
.ex_wd(ex_wd_o),
.ex_wreg(ex_wreg_o),
.ex_wdata(ex_wdata_o),
.ex_hi(ex_hi_o),
.ex_lo(ex_lo_o),
.ex_whilo(ex_whilo_o),
.hilo_i(hilo_temp_o),
.cnt_i(cnt_o),
.mem_wd(mem_wd_i),
.mem_wreg(mem_wreg_i),
.mem_wdata(mem_wdata_i),
.mem_hi(mem_hi_i),
.mem_lo(mem_lo_i),
.mem_whilo(mem_whilo_i),
.hilo_o(hilo_temp_i),
.cnt_o(cnt_i)
);
mem mem0(
.rst(rst),
.wd_i(mem_wd_i),
.wreg_i(mem_wreg_i),
.wdata_i(mem_wdata_i),
.hi_i(mem_hi_i),
.lo_i(mem_lo_i),
.whilo_i(mem_whilo_i),
.wd_o(mem_wd_o),
.wreg_o(mem_wreg_o),
.wdata_o(mem_wdata_o),
.hi_o(mem_hi_o),
.lo_o(mem_lo_o),
.whilo_o(mem_whilo_o)
);
mem_wb mem_wb0(
.clk(clk),
.rst(rst),
.stall(stall),
.mem_wd(mem_wd_o),
.mem_wreg(mem_wreg_o),
.mem_wdata(mem_wdata_o),
.mem_hi(mem_hi_o),
.mem_lo(mem_lo_o),
.mem_whilo(mem_whilo_o),
.wb_wd(wb_wd_i),
.wb_wreg(wb_wreg_i),
.wb_wdata(wb_wdata_i),
.wb_hi(wb_hi_i),
.wb_lo(wb_lo_i),
.wb_whilo(wb_whilo_i)
);
hilo_reg hilo_reg0(
.clk(clk),
.rst(rst),
.we(wb_whilo_i),
.hi_i(wb_hi_i),
.lo_i(wb_lo_i),
.hi_o(hi),
.lo_o(lo)
);
ctrl ctrl0(
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ex(stallreq_from_ex),
.stall(stall)
);
div div0(
.clk(clk),
.rst(rst),
.signed_div_i(signed_div),
.opdata1_i(div_opdata1),
.opdata2_i(div_opdata2),
.start_i(div_start),
.annul_i(1'b0),
.result_o(div_result),
.ready_o(div_ready)
);
endmodule | module openmips(
input wire clk,
input wire rst,
input wire[`RegBus] rom_data_i,
output wire[`RegBus] rom_addr_o,
output wire rom_ce_o
); |
wire[`InstAddrBus] pc;
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire[`RegBus] ex_hi_o;
wire[`RegBus] ex_lo_o;
wire ex_whilo_o;
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire[`RegBus] mem_hi_i;
wire[`RegBus] mem_lo_i;
wire mem_whilo_i;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire[`RegBus] mem_hi_o;
wire[`RegBus] mem_lo_o;
wire mem_whilo_o;
wire wb_wreg_i;
wire[`RegAddrBus] wb_wd_i;
wire[`RegBus] wb_wdata_i;
wire[`RegBus] wb_hi_i;
wire[`RegBus] wb_lo_i;
wire wb_whilo_i;
wire reg1_read;
wire reg2_read;
wire[`RegBus] reg1_data;
wire[`RegBus] reg2_data;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire[`RegBus] hi;
wire[`RegBus] lo;
wire[`DoubleRegBus] hilo_temp_o;
wire[1:0] cnt_o;
wire[`DoubleRegBus] hilo_temp_i;
wire[1:0] cnt_i;
wire[`DoubleRegBus] div_result;
wire div_ready;
wire[`RegBus] div_opdata1;
wire[`RegBus] div_opdata2;
wire div_start;
wire div_annul;
wire signed_div;
wire[5:0] stall;
wire stallreq_from_id;
wire stallreq_from_ex;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(stall),
.pc(pc),
.ce(rom_ce_o)
);
assign rom_addr_o = pc;
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(stall),
.if_pc(pc),
.if_inst(rom_data_i),
.id_pc(id_pc_i),
.id_inst(id_inst_i)
);
id id0(
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.reg1_data_i(reg1_data),
.reg2_data_i(reg2_data),
.ex_wreg_i(ex_wreg_o),
.ex_wdata_i(ex_wdata_o),
.ex_wd_i(ex_wd_o),
.mem_wreg_i(mem_wreg_o),
.mem_wdata_i(mem_wdata_o),
.mem_wd_i(mem_wd_o),
.reg1_read_o(reg1_read),
.reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr),
.reg2_addr_o(reg2_addr),
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.wd_o(id_wd_o),
.wreg_o(id_wreg_o),
.stallreq(stallreq_from_id)
);
regfile regfile1(
.clk (clk),
.rst (rst),
.we (wb_wreg_i),
.waddr (wb_wd_i),
.wdata (wb_wdata_i),
.re1 (reg1_read),
.raddr1 (reg1_addr),
.rdata1 (reg1_data),
.re2 (reg2_read),
.raddr2 (reg2_addr),
.rdata2 (reg2_data)
);
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(stall),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_wd(id_wd_o),
.id_wreg(id_wreg_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_wd(ex_wd_i),
.ex_wreg(ex_wreg_i)
);
ex ex0(
.rst(rst),
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.wd_i(ex_wd_i),
.wreg_i(ex_wreg_i),
.hi_i(hi),
.lo_i(lo),
.wb_hi_i(wb_hi_i),
.wb_lo_i(wb_lo_i),
.wb_whilo_i(wb_whilo_i),
.mem_hi_i(mem_hi_o),
.mem_lo_i(mem_lo_o),
.mem_whilo_i(mem_whilo_o),
.hilo_temp_i(hilo_temp_i),
.cnt_i(cnt_i),
.div_result_i(div_result),
.div_ready_i(div_ready),
.wd_o(ex_wd_o),
.wreg_o(ex_wreg_o),
.wdata_o(ex_wdata_o),
.hi_o(ex_hi_o),
.lo_o(ex_lo_o),
.whilo_o(ex_whilo_o),
.hilo_temp_o(hilo_temp_o),
.cnt_o(cnt_o),
.div_opdata1_o(div_opdata1),
.div_opdata2_o(div_opdata2),
.div_start_o(div_start),
.signed_div_o(signed_div),
.stallreq(stallreq_from_ex)
);
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(stall),
.ex_wd(ex_wd_o),
.ex_wreg(ex_wreg_o),
.ex_wdata(ex_wdata_o),
.ex_hi(ex_hi_o),
.ex_lo(ex_lo_o),
.ex_whilo(ex_whilo_o),
.hilo_i(hilo_temp_o),
.cnt_i(cnt_o),
.mem_wd(mem_wd_i),
.mem_wreg(mem_wreg_i),
.mem_wdata(mem_wdata_i),
.mem_hi(mem_hi_i),
.mem_lo(mem_lo_i),
.mem_whilo(mem_whilo_i),
.hilo_o(hilo_temp_i),
.cnt_o(cnt_i)
);
mem mem0(
.rst(rst),
.wd_i(mem_wd_i),
.wreg_i(mem_wreg_i),
.wdata_i(mem_wdata_i),
.hi_i(mem_hi_i),
.lo_i(mem_lo_i),
.whilo_i(mem_whilo_i),
.wd_o(mem_wd_o),
.wreg_o(mem_wreg_o),
.wdata_o(mem_wdata_o),
.hi_o(mem_hi_o),
.lo_o(mem_lo_o),
.whilo_o(mem_whilo_o)
);
mem_wb mem_wb0(
.clk(clk),
.rst(rst),
.stall(stall),
.mem_wd(mem_wd_o),
.mem_wreg(mem_wreg_o),
.mem_wdata(mem_wdata_o),
.mem_hi(mem_hi_o),
.mem_lo(mem_lo_o),
.mem_whilo(mem_whilo_o),
.wb_wd(wb_wd_i),
.wb_wreg(wb_wreg_i),
.wb_wdata(wb_wdata_i),
.wb_hi(wb_hi_i),
.wb_lo(wb_lo_i),
.wb_whilo(wb_whilo_i)
);
hilo_reg hilo_reg0(
.clk(clk),
.rst(rst),
.we(wb_whilo_i),
.hi_i(wb_hi_i),
.lo_i(wb_lo_i),
.hi_o(hi),
.lo_o(lo)
);
ctrl ctrl0(
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ex(stallreq_from_ex),
.stall(stall)
);
div div0(
.clk(clk),
.rst(rst),
.signed_div_i(signed_div),
.opdata1_i(div_opdata1),
.opdata2_i(div_opdata2),
.start_i(div_start),
.annul_i(1'b0),
.result_o(div_result),
.ready_o(div_ready)
);
endmodule | 48 |
5,352 | data/full_repos/permissive/113839829/Source/CPU/ctrl.v | 113,839,829 | ctrl.v | v | 36 | 104 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 112: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:20: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) stall <= 6\'b000000;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ctrl.v:20: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) stall <= 6\'b000000;\n ^\n%Error: Exiting due to 3 error(s)\n' | 6,081 | module | module ctrl
(
input wire rst,
input wire stallreq_from_id1,
input wire stallreq_from_id2,
input wire stallreq_from_if_cache,
input wire stallreq_from_mem_cache,
output reg [5:0] stall
);
always @ (*)
begin
if(rst == `RstEnable) stall <= 6'b000000;
else if (stallreq_from_mem_cache == 1'b1)
stall <= 6'b011111;
else if (stallreq_from_if_cache == 1'b1)
stall <= 6'b000111;
else if (stallreq_from_id2 == 1'b1)
stall <= 6'b000111;
else if (stallreq_from_id1 == 1'b1)
stall <= 6'b000010;
else stall <= 6'b000000;
end
endmodule | module ctrl
(
input wire rst,
input wire stallreq_from_id1,
input wire stallreq_from_id2,
input wire stallreq_from_if_cache,
input wire stallreq_from_mem_cache,
output reg [5:0] stall
); |
always @ (*)
begin
if(rst == `RstEnable) stall <= 6'b000000;
else if (stallreq_from_mem_cache == 1'b1)
stall <= 6'b011111;
else if (stallreq_from_if_cache == 1'b1)
stall <= 6'b000111;
else if (stallreq_from_id2 == 1'b1)
stall <= 6'b000111;
else if (stallreq_from_id1 == 1'b1)
stall <= 6'b000010;
else stall <= 6'b000000;
end
endmodule | 48 |
5,356 | data/full_repos/permissive/113839829/Source/CPU/ex_mem.v | 113,839,829 | ex_mem.v | v | 72 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:15: Define or directive not defined: \'`RegAddrBus\'\n input wire [`RegAddrBus] ex_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`RegAddrBus] ex_wd,\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`RegBus] ex_wdata, \n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:17: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] ex_wdata, \n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:19: Define or directive not defined: \'`AluOpBus\'\n input wire [`AluOpBus] ex_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:20: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] ex_mem_addr,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:21: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] ex_reg2,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:24: Define or directive not defined: \'`RegAddrBus\'\n output reg [`RegAddrBus] mem_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`RegBus] mem_wdata,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:26: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] mem_wdata,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:28: Define or directive not defined: \'`AluOpBus\'\n output reg [`AluOpBus] mem_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:29: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] mem_mem_addr,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:30: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] mem_reg2\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:36: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:38: Define or directive not defined: \'`NOPRegAddr\'\n mem_wd <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:39: Define or directive not defined: \'`WriteDisable\'\n mem_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:40: Define or directive not defined: \'`ZeroWord\'\n mem_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:41: Define or directive not defined: \'`EXE_NOP_OP\'\n mem_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:42: Define or directive not defined: \'`ZeroWord\'\n mem_mem_addr <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:43: Define or directive not defined: \'`ZeroWord\'\n mem_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:48: Define or directive not defined: \'`NOPRegAddr\'\n mem_wd <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:49: Define or directive not defined: \'`WriteDisable\'\n mem_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:50: Define or directive not defined: \'`ZeroWord\'\n mem_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:51: Define or directive not defined: \'`EXE_NOP_OP\'\n mem_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:52: Define or directive not defined: \'`ZeroWord\'\n mem_mem_addr <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/ex_mem.v:53: Define or directive not defined: \'`ZeroWord\'\n mem_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 27 error(s)\n' | 6,086 | module | module ex_mem
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire [`RegBus] ex_wdata,
input wire [`AluOpBus] ex_aluop,
input wire [`RegBus] ex_mem_addr,
input wire [`RegBus] ex_reg2,
output reg [`RegAddrBus] mem_wd,
output reg mem_wreg,
output reg [`RegBus] mem_wdata,
output reg [`AluOpBus] mem_aluop,
output reg [`RegBus] mem_mem_addr,
output reg [`RegBus] mem_reg2
);
always @ (posedge clk)
begin
if(rst == `RstEnable)
begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
end
if (stall[3] == 1'b1&&stall[4] == 1'b0)
begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
end
else if (stall[3] == 1'b0)
begin
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_wdata <= ex_wdata;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
end
end
endmodule | module ex_mem
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire [`RegBus] ex_wdata,
input wire [`AluOpBus] ex_aluop,
input wire [`RegBus] ex_mem_addr,
input wire [`RegBus] ex_reg2,
output reg [`RegAddrBus] mem_wd,
output reg mem_wreg,
output reg [`RegBus] mem_wdata,
output reg [`AluOpBus] mem_aluop,
output reg [`RegBus] mem_mem_addr,
output reg [`RegBus] mem_reg2
); |
always @ (posedge clk)
begin
if(rst == `RstEnable)
begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
end
if (stall[3] == 1'b1&&stall[4] == 1'b0)
begin
mem_wd <= `NOPRegAddr;
mem_wreg <= `WriteDisable;
mem_wdata <= `ZeroWord;
mem_aluop <= `EXE_NOP_OP;
mem_mem_addr <= `ZeroWord;
mem_reg2 <= `ZeroWord;
end
else if (stall[3] == 1'b0)
begin
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_wdata <= ex_wdata;
mem_aluop <= ex_aluop;
mem_mem_addr <= ex_mem_addr;
mem_reg2 <= ex_reg2;
end
end
endmodule | 48 |
5,357 | data/full_repos/permissive/113839829/Source/CPU/icache.v | 113,839,829 | icache.v | v | 191 | 144 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 112: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:57: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:57: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:59: syntax error, unexpected \';\'\n for (i = 0;i < NASSOC;i = i+1)\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:59: syntax error, unexpected \')\', expecting \';\'\n for (i = 0;i < NASSOC;i = i+1)\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:60: syntax error, unexpected \';\'\n for (j = 0;j < NBLOCK;j = j+1)\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:60: syntax error, unexpected \')\', expecting \';\'\n for (j = 0;j < NBLOCK;j = j+1)\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:67: syntax error, unexpected \'[\', expecting IDENTIFIER\n for (i = 0;i < NBLOCK;i = i+1) crep[i] = 0;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:92: syntax error, unexpected \'[\', expecting IDENTIFIER\n crep[addr_index] <= 1;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:95: syntax error, unexpected <=, expecting IDENTIFIER\n read_data <= {cdata[0][addr_index][0],cdata[0][addr_index][1],\n ^~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:98: syntax error, unexpected <=, expecting IDENTIFIER\n read_data <= {cdata[0][addr_index][4],cdata[0][addr_index][5],\n ^~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n crep[addr_index] <= 0;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:107: syntax error, unexpected <=, expecting IDENTIFIER\n read_data <= {cdata[1][addr_index][0],cdata[1][addr_index][1],\n ^~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:110: syntax error, unexpected <=, expecting IDENTIFIER\n read_data <= {cdata[1][addr_index][4],cdata[1][addr_index][5],\n ^~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:116: syntax error, unexpected <=, expecting IDENTIFIER\n stallreq <= 1\'b1;\n ^~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:127: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/icache.v:135: syntax error, unexpected \'[\', expecting IDENTIFIER\n cdata[i][j][k] <= 0;\n ^\n%Error: Cannot continue\n' | 6,087 | module | module icache
#(
parameter WORD_SELECT_BIT = 3,
parameter INDEX_BIT = 2,
parameter NASSOC = 2
)
(
input clk,
input rst,
input ce,
input [31:0] addr,
input read_flag,
output reg [31:0] read_data,
output reg cache_req_o,
output reg [31:0] cache_addr_o,
output reg cache_write_o,
output wire [31:0] cache_write_data_o,
output wire [3:0] cache_write_mask_o,
input cache_rep_i,
input [63:0] cache_rep_data_i,
output reg stallreq
);
parameter NBLOCK = 1<<INDEX_BIT;
parameter TAG_BIT = 32-INDEX_BIT-WORD_SELECT_BIT;
wire [TAG_BIT-1:0] addr_tag = addr[31:31-TAG_BIT+1];
wire [INDEX_BIT-1:0] addr_index = addr[WORD_SELECT_BIT+INDEX_BIT-1:WORD_SELECT_BIT];
reg [TAG_BIT-1:0] ctag[NASSOC-1:0][NBLOCK-1:0];
reg cvalid[NASSOC-1:0][NBLOCK-1:0];
reg [7:0] cdata[NASSOC-1:0][NBLOCK-1:0][1<<WORD_SELECT_BIT:0];
reg crep[NBLOCK-1:0];
integer i,j,k;
always @ (clk)
begin
if (rst == `RstEnable)
begin
for (i = 0;i < NASSOC;i = i+1)
for (j = 0;j < NBLOCK;j = j+1)
begin
ctag[i][j] <= 0;
cvalid[i][j] <= 0;
for (k = 0;k < (1<<WORD_SELECT_BIT);k = k+1)
cdata[i][j][k] <= 0;
end
for (i = 0;i < NBLOCK;i = i+1) crep[i] = 0;
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (ce !== 1'b1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (read_flag == 1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
if (ctag[0][addr_index] == addr_tag&&cvalid[0][addr_index] == 1'b1)
begin
crep[addr_index] <= 1;
stallreq <= 0;
if (addr[2] == 0)
read_data <= {cdata[0][addr_index][0],cdata[0][addr_index][1],
cdata[0][addr_index][2],cdata[0][addr_index][3]};
if (addr[2] == 1)
read_data <= {cdata[0][addr_index][4],cdata[0][addr_index][5],
cdata[0][addr_index][6],cdata[0][addr_index][7]};
end
if (ctag[1][addr_index] == addr_tag&&cvalid[1][addr_index] == 1'b1)
begin
crep[addr_index] <= 0;
stallreq <= 0;
if (addr[2] == 0)
read_data <= {cdata[1][addr_index][0],cdata[1][addr_index][1],
cdata[1][addr_index][2],cdata[1][addr_index][3]};
if (addr[2] == 1)
read_data <= {cdata[1][addr_index][4],cdata[1][addr_index][5],
cdata[1][addr_index][6],cdata[1][addr_index][7]};
end
if (!(ctag[0][addr_index] == addr_tag&&cvalid[0][addr_index] == 1'b1)&&!(ctag[1][addr_index] == addr_tag&&cvalid[1][addr_index] == 1'b1))
begin
stallreq <= 1'b1;
cache_addr_o <= addr;
cache_req_o <= 1'b1;
end
end
end
always @ (cache_req_o)
begin
if (rst == `RstEnable)
begin
for (i = 0;i < NASSOC;i = i+1)
for (j = 0;j < NBLOCK;j = j+1)
begin
ctag[i][j] <= 0;
cvalid[i][j] <= 0;
for (k = 0;k < (1<<WORD_SELECT_BIT);k = k+1)
cdata[i][j][k] <= 0;
end
for (i = 0;i < NBLOCK;i = i+1) crep[i] = 0;
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (ce !== 1'b1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (cache_rep_i == 1)
begin
if (crep[addr_index] == 1'b0)
begin
cvalid[0][addr_index] <= 1'b1;
ctag[0][addr_index] <= addr_tag;
cdata[0][addr_index][0] <= cache_rep_data_i[7:0];
cdata[0][addr_index][1] <= cache_rep_data_i[15:8];
cdata[0][addr_index][2] <= cache_rep_data_i[23:16];
cdata[0][addr_index][3] <= cache_rep_data_i[31:24];
cdata[0][addr_index][4] <= cache_rep_data_i[39:32];
cdata[0][addr_index][5] <= cache_rep_data_i[47:40];
cdata[0][addr_index][6] <= cache_rep_data_i[55:48];
cdata[0][addr_index][7] <= cache_rep_data_i[63:56];
end
if (crep[addr_index] == 1'b1)
begin
cvalid[1][addr_index] <= 1'b1;
ctag[1][addr_index] <= addr_tag;
cdata[1][addr_index][0] <= cache_rep_data_i[7:0];
cdata[1][addr_index][1] <= cache_rep_data_i[15:8];
cdata[1][addr_index][2] <= cache_rep_data_i[23:16];
cdata[1][addr_index][3] <= cache_rep_data_i[31:24];
cdata[1][addr_index][4] <= cache_rep_data_i[39:32];
cdata[1][addr_index][5] <= cache_rep_data_i[47:40];
cdata[1][addr_index][6] <= cache_rep_data_i[55:48];
cdata[1][addr_index][7] <= cache_rep_data_i[63:56];
end
end
end
endmodule | module icache
#(
parameter WORD_SELECT_BIT = 3,
parameter INDEX_BIT = 2,
parameter NASSOC = 2
)
(
input clk,
input rst,
input ce,
input [31:0] addr,
input read_flag,
output reg [31:0] read_data,
output reg cache_req_o,
output reg [31:0] cache_addr_o,
output reg cache_write_o,
output wire [31:0] cache_write_data_o,
output wire [3:0] cache_write_mask_o,
input cache_rep_i,
input [63:0] cache_rep_data_i,
output reg stallreq
); |
parameter NBLOCK = 1<<INDEX_BIT;
parameter TAG_BIT = 32-INDEX_BIT-WORD_SELECT_BIT;
wire [TAG_BIT-1:0] addr_tag = addr[31:31-TAG_BIT+1];
wire [INDEX_BIT-1:0] addr_index = addr[WORD_SELECT_BIT+INDEX_BIT-1:WORD_SELECT_BIT];
reg [TAG_BIT-1:0] ctag[NASSOC-1:0][NBLOCK-1:0];
reg cvalid[NASSOC-1:0][NBLOCK-1:0];
reg [7:0] cdata[NASSOC-1:0][NBLOCK-1:0][1<<WORD_SELECT_BIT:0];
reg crep[NBLOCK-1:0];
integer i,j,k;
always @ (clk)
begin
if (rst == `RstEnable)
begin
for (i = 0;i < NASSOC;i = i+1)
for (j = 0;j < NBLOCK;j = j+1)
begin
ctag[i][j] <= 0;
cvalid[i][j] <= 0;
for (k = 0;k < (1<<WORD_SELECT_BIT);k = k+1)
cdata[i][j][k] <= 0;
end
for (i = 0;i < NBLOCK;i = i+1) crep[i] = 0;
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (ce !== 1'b1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (read_flag == 1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
if (ctag[0][addr_index] == addr_tag&&cvalid[0][addr_index] == 1'b1)
begin
crep[addr_index] <= 1;
stallreq <= 0;
if (addr[2] == 0)
read_data <= {cdata[0][addr_index][0],cdata[0][addr_index][1],
cdata[0][addr_index][2],cdata[0][addr_index][3]};
if (addr[2] == 1)
read_data <= {cdata[0][addr_index][4],cdata[0][addr_index][5],
cdata[0][addr_index][6],cdata[0][addr_index][7]};
end
if (ctag[1][addr_index] == addr_tag&&cvalid[1][addr_index] == 1'b1)
begin
crep[addr_index] <= 0;
stallreq <= 0;
if (addr[2] == 0)
read_data <= {cdata[1][addr_index][0],cdata[1][addr_index][1],
cdata[1][addr_index][2],cdata[1][addr_index][3]};
if (addr[2] == 1)
read_data <= {cdata[1][addr_index][4],cdata[1][addr_index][5],
cdata[1][addr_index][6],cdata[1][addr_index][7]};
end
if (!(ctag[0][addr_index] == addr_tag&&cvalid[0][addr_index] == 1'b1)&&!(ctag[1][addr_index] == addr_tag&&cvalid[1][addr_index] == 1'b1))
begin
stallreq <= 1'b1;
cache_addr_o <= addr;
cache_req_o <= 1'b1;
end
end
end
always @ (cache_req_o)
begin
if (rst == `RstEnable)
begin
for (i = 0;i < NASSOC;i = i+1)
for (j = 0;j < NBLOCK;j = j+1)
begin
ctag[i][j] <= 0;
cvalid[i][j] <= 0;
for (k = 0;k < (1<<WORD_SELECT_BIT);k = k+1)
cdata[i][j][k] <= 0;
end
for (i = 0;i < NBLOCK;i = i+1) crep[i] = 0;
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (ce !== 1'b1)
begin
read_data <= 0;
cache_req_o <= 0;
cache_addr_o <= 0;
cache_write_o <= 0;
stallreq <= 0;
end
else if (cache_rep_i == 1)
begin
if (crep[addr_index] == 1'b0)
begin
cvalid[0][addr_index] <= 1'b1;
ctag[0][addr_index] <= addr_tag;
cdata[0][addr_index][0] <= cache_rep_data_i[7:0];
cdata[0][addr_index][1] <= cache_rep_data_i[15:8];
cdata[0][addr_index][2] <= cache_rep_data_i[23:16];
cdata[0][addr_index][3] <= cache_rep_data_i[31:24];
cdata[0][addr_index][4] <= cache_rep_data_i[39:32];
cdata[0][addr_index][5] <= cache_rep_data_i[47:40];
cdata[0][addr_index][6] <= cache_rep_data_i[55:48];
cdata[0][addr_index][7] <= cache_rep_data_i[63:56];
end
if (crep[addr_index] == 1'b1)
begin
cvalid[1][addr_index] <= 1'b1;
ctag[1][addr_index] <= addr_tag;
cdata[1][addr_index][0] <= cache_rep_data_i[7:0];
cdata[1][addr_index][1] <= cache_rep_data_i[15:8];
cdata[1][addr_index][2] <= cache_rep_data_i[23:16];
cdata[1][addr_index][3] <= cache_rep_data_i[31:24];
cdata[1][addr_index][4] <= cache_rep_data_i[39:32];
cdata[1][addr_index][5] <= cache_rep_data_i[47:40];
cdata[1][addr_index][6] <= cache_rep_data_i[55:48];
cdata[1][addr_index][7] <= cache_rep_data_i[63:56];
end
end
end
endmodule | 48 |
5,358 | data/full_repos/permissive/113839829/Source/CPU/id.v | 113,839,829 | id.v | v | 869 | 108 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Warning-BSSPACE: data/full_repos/permissive/113839829/Source/CPU/id.v:826: Backslash followed by whitespace, perhaps the whitespace is accidental?\n `define GET_OPRAND(reg_o,reg_read_o,reg_data_i,reg_addr_o) \\ \n ^\n ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message.\n%Warning-BSSPACE: data/full_repos/permissive/113839829/Source/CPU/id.v:850: Backslash followed by whitespace, perhaps the whitespace is accidental?\n `define HAVE_TO_STOP(reg_read_o,reg_addr_o,stallreq_for_reg) \\ \n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:10: Define or directive not defined: \'`InstAddrBus\'\n input wire [`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`InstAddrBus] pc_i,\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:11: Define or directive not defined: \'`InstBus\'\n input wire [`InstBus] inst_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire which_pdt_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [9:0] history_i, \n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire ex_wreg_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`RegBus] ex_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:20: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] ex_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:21: Define or directive not defined: \'`RegAddrBus\'\n input wire [`RegAddrBus] ex_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire mem_wreg_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`RegBus] mem_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:26: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] mem_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:27: Define or directive not defined: \'`RegAddrBus\'\n input wire [`RegAddrBus] mem_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:29: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] reg1_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:30: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] reg2_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_read_o, \n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:35: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`RegAddrBus] reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:35: Define or directive not defined: \'`RegAddrBus\'\n output reg [`RegAddrBus] reg1_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:36: Define or directive not defined: \'`RegAddrBus\'\n output reg [`RegAddrBus] reg2_addr_o, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:39: Define or directive not defined: \'`AluOpBus\'\n output reg [`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:40: Define or directive not defined: \'`AluSelBus\'\n output reg [`AluSelBus] alusel_o,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:41: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] reg1_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:42: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] reg2_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:43: Define or directive not defined: \'`RegAddrBus\'\n output reg [`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire [`RegBus] inst_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:45: Define or directive not defined: \'`RegBus\'\n output wire [`RegBus] inst_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`RegBus] branch_target_address_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:48: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] branch_target_address_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:49: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] link_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:53: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg id_branch_res_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:54: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg id_pdt_true_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:55: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire which_pdt_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:56: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire [`InstAddrBus] pc_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:56: Define or directive not defined: \'`InstAddrBus\'\n output wire [`InstAddrBus] pc_o,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:59: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg stallreq1, \n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:60: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg stallreq2 \n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:63: Define or directive not defined: \'`RegBus\'\n reg [`RegBus] imm;\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`RegBus] imm;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:66: syntax error, unexpected assign\n assign inst_o = inst_i;\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:75: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:77: Define or directive not defined: \'`EXE_NOP_OP\'\n aluop_o <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:78: Define or directive not defined: \'`EXE_RES_NOP\'\n alusel_o <= `EXE_RES_NOP;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:79: Define or directive not defined: \'`NOPRegAddr\'\n wd_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:80: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:83: Define or directive not defined: \'`NOPRegAddr\'\n reg1_addr_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:84: Define or directive not defined: \'`NOPRegAddr\'\n reg2_addr_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:85: Define or directive not defined: \'`ZeroWord\'\n imm <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:87: Define or directive not defined: \'`ZeroWord\'\n branch_target_address_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id.v:88: Define or directive not defined: \'`ZeroWord\'\n link_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,088 | module | module id
(
input wire rst,
input wire [`InstAddrBus] pc_i,
input wire [`InstBus] inst_i,
input wire pdt_res_i,
input wire which_pdt_i,
input wire [9:0] history_i,
input wire ex_wreg_i,
input wire [`RegBus] ex_wdata_i,
input wire [`RegAddrBus] ex_wd_i,
input wire ex_is_load_i,
input wire mem_wreg_i,
input wire [`RegBus] mem_wdata_i,
input wire [`RegAddrBus] mem_wd_i,
input wire [`RegBus] reg1_data_i,
input wire [`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg [`RegAddrBus] reg1_addr_o,
output reg [`RegAddrBus] reg2_addr_o,
output reg [`AluOpBus] aluop_o,
output reg [`AluSelBus] alusel_o,
output reg [`RegBus] reg1_o,
output reg [`RegBus] reg2_o,
output reg [`RegAddrBus] wd_o,
output reg wreg_o,
output wire [`RegBus] inst_o,
output reg branch_flag_o,
output reg [`RegBus] branch_target_address_o,
output reg [`RegBus] link_addr_o,
output reg id_is_branch_o,
output reg id_branch_res_o,
output reg id_pdt_true_o,
output wire which_pdt_o,
output wire [`InstAddrBus] pc_o,
output wire [9:0] history_o,
output reg stallreq1,
output reg stallreq2
);
reg [`RegBus] imm;
reg instvalid;
assign inst_o = inst_i;
assign which_pdt_o = which_pdt_i;
assign pc_o = pc_i;
assign history_o = history_i;
always @ (*)
begin
if (rst == `RstEnable)
begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= `ZeroWord;
branch_flag_o <= 1'b0;
branch_target_address_o <= `ZeroWord;
link_addr_o <= `ZeroWord;
stallreq1 <= 1'b0;
stallreq2 <= 1'b0;
id_is_branch_o <= 1'b0;
id_branch_res_o <= 1'b0;
id_pdt_true_o = 1'b0;
instvalid <= `InstInvalid;
end
else
begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[11:7];
wreg_o <= `WriteDisable;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
imm <= `ZeroWord;
branch_flag_o <= 1'b0;
branch_target_address_o <= `ZeroWord;
link_addr_o <= `ZeroWord;
stallreq1 <= 1'b0;
stallreq2 <= 1'b0;
id_is_branch_o <= 1'b0;
id_branch_res_o <= 1'b0;
instvalid <= `InstInvalid;
case (inst_i[6:0])
7'b0000011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LB_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b001:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LH_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b010:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LW_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b100:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LBU_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b101:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LHU_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0100011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SB_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b001:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SH_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b010:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SW_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0010011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b001:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
default: begin end
endcase
end
3'b010:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b011:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b100:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b101:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
default: begin end
endcase
end
3'b110:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0010111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
imm <= pc_i+{inst_i[31:12],12'h0};
instvalid <= `InstValid;
end
7'b0110011:
begin
case (inst_i[14:12])
3'b000:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b001:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b010:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b011:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b100:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b101:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b110:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b111:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
endcase
end
7'b0110111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
imm <= {inst_i[31:12],12'h0};
instvalid <= `InstValid;
end
7'b1100111:
begin
wreg_o <= `WriteEnable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
branch_flag_o <= 1'b1;
branch_target_address_o <= reg2_o+{{20{inst_i[31]}},inst_i[31:20]};
link_addr_o <= pc_i+4;
stallreq1 <= 1'b1;
instvalid <= `InstValid;
end
7'b1100011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o == reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b001:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o != reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b100:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if ((reg1_o[31] == reg2_o[31]&®1_o[30:0] < reg2_o[30:0])||(reg1_o[31] > reg2_o[31]))
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b101:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if ((reg1_o[31] == reg2_o[31]&®1_o[30:0] >= reg2_o[30:0])||(reg1_o[31] < reg2_o[31]))
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b110:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o < reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b111:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o >= reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
default: begin end
endcase
end
7'b1101111:
begin
wreg_o <= `WriteEnable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{11{inst_i[31]}},inst_i[31],inst_i[19:12],inst_i[20],inst_i[30:21],1'b0};
link_addr_o <= pc_i+4;
stallreq1 <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
end
`define GET_OPRAND(reg_o,reg_read_o,reg_data_i,reg_addr_o) \
always @ (*) \
begin \
if (rst == `RstEnable) reg_o <= `ZeroWord; \
else if (reg_read_o == 1'b1) \
begin \
if (reg_addr_o == 5'b0) reg_o <= `ZeroWord; \
else if ((ex_wreg_i == 1'b1)&&(ex_wd_i == reg_addr_o)) \
reg_o <= ex_wdata_i; \
else if ((mem_wreg_i == 1'b1)&&(mem_wd_i == reg_addr_o)) \
reg_o <= mem_wdata_i; \
else if (reg_read_o == 1'b1) \
reg_o <= reg_data_i; \
else reg_o <= `ZeroWord; \
end \
else \
reg_o <= imm; \
end
`GET_OPRAND(reg1_o,reg1_read_o,reg1_data_i,reg1_addr_o)
`GET_OPRAND(reg2_o,reg2_read_o,reg2_data_i,reg2_addr_o)
reg stallreq_for_reg1,stallreq_for_reg2;
`define HAVE_TO_STOP(reg_read_o,reg_addr_o,stallreq_for_reg) \
always @ (*) \
begin \
stallreq_for_reg <= 1'b0; \
if (rst == `RstEnable);\
else if ((reg_read_o == 1'b1&®_addr_o != `ZeroWord)&&ex_is_load_i == 1'b1&&(ex_wd_i == reg_addr_o)) \
stallreq_for_reg <= 1'b1; \
end
`HAVE_TO_STOP(reg1_read_o,reg1_addr_o,stallreq_for_reg1)
`HAVE_TO_STOP(reg2_read_o,reg2_addr_o,stallreq_for_reg2)
always @ (*) stallreq2 <= stallreq_for_reg1|stallreq_for_reg2;
always @ (stallreq2 == 1) id_is_branch_o <= 1'b0;
endmodule | module id
(
input wire rst,
input wire [`InstAddrBus] pc_i,
input wire [`InstBus] inst_i,
input wire pdt_res_i,
input wire which_pdt_i,
input wire [9:0] history_i,
input wire ex_wreg_i,
input wire [`RegBus] ex_wdata_i,
input wire [`RegAddrBus] ex_wd_i,
input wire ex_is_load_i,
input wire mem_wreg_i,
input wire [`RegBus] mem_wdata_i,
input wire [`RegAddrBus] mem_wd_i,
input wire [`RegBus] reg1_data_i,
input wire [`RegBus] reg2_data_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg [`RegAddrBus] reg1_addr_o,
output reg [`RegAddrBus] reg2_addr_o,
output reg [`AluOpBus] aluop_o,
output reg [`AluSelBus] alusel_o,
output reg [`RegBus] reg1_o,
output reg [`RegBus] reg2_o,
output reg [`RegAddrBus] wd_o,
output reg wreg_o,
output wire [`RegBus] inst_o,
output reg branch_flag_o,
output reg [`RegBus] branch_target_address_o,
output reg [`RegBus] link_addr_o,
output reg id_is_branch_o,
output reg id_branch_res_o,
output reg id_pdt_true_o,
output wire which_pdt_o,
output wire [`InstAddrBus] pc_o,
output wire [9:0] history_o,
output reg stallreq1,
output reg stallreq2
); |
reg [`RegBus] imm;
reg instvalid;
assign inst_o = inst_i;
assign which_pdt_o = which_pdt_i;
assign pc_o = pc_i;
assign history_o = history_i;
always @ (*)
begin
if (rst == `RstEnable)
begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= `ZeroWord;
branch_flag_o <= 1'b0;
branch_target_address_o <= `ZeroWord;
link_addr_o <= `ZeroWord;
stallreq1 <= 1'b0;
stallreq2 <= 1'b0;
id_is_branch_o <= 1'b0;
id_branch_res_o <= 1'b0;
id_pdt_true_o = 1'b0;
instvalid <= `InstInvalid;
end
else
begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= inst_i[11:7];
wreg_o <= `WriteDisable;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
imm <= `ZeroWord;
branch_flag_o <= 1'b0;
branch_target_address_o <= `ZeroWord;
link_addr_o <= `ZeroWord;
stallreq1 <= 1'b0;
stallreq2 <= 1'b0;
id_is_branch_o <= 1'b0;
id_branch_res_o <= 1'b0;
instvalid <= `InstInvalid;
case (inst_i[6:0])
7'b0000011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LB_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b001:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LH_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b010:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LW_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b100:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LBU_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
3'b101:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_LHU_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0100011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SB_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b001:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SH_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
3'b010:
begin
wreg_o <= `WriteDisable;
aluop_o <= `EXE_SW_OP;
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0010011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b001:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
default: begin end
endcase
end
3'b010:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b011:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b100:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b101:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {27'h0,inst_i[24:20]};
instvalid = `InstValid;
end
default: begin end
endcase
end
3'b110:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
3'b111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31]}},inst_i[31:20]};
instvalid <= `InstValid;
end
default: begin end
endcase
end
7'b0010111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
imm <= pc_i+{inst_i[31:12],12'h0};
instvalid <= `InstValid;
end
7'b0110011:
begin
case (inst_i[14:12])
3'b000:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b001:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b010:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b011:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b100:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b101:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
7'b0100000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b110:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
3'b111:
begin
case (inst_i[31:25])
7'b0000000:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
endcase
end
7'b0110111:
begin
wreg_o <= `WriteEnable;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
imm <= {inst_i[31:12],12'h0};
instvalid <= `InstValid;
end
7'b1100111:
begin
wreg_o <= `WriteEnable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b1;
branch_flag_o <= 1'b1;
branch_target_address_o <= reg2_o+{{20{inst_i[31]}},inst_i[31:20]};
link_addr_o <= pc_i+4;
stallreq1 <= 1'b1;
instvalid <= `InstValid;
end
7'b1100011:
begin
case (inst_i[14:12])
3'b000:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o == reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b001:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o != reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b100:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if ((reg1_o[31] == reg2_o[31]&®1_o[30:0] < reg2_o[30:0])||(reg1_o[31] > reg2_o[31]))
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b101:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if ((reg1_o[31] == reg2_o[31]&®1_o[30:0] >= reg2_o[30:0])||(reg1_o[31] < reg2_o[31]))
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b110:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o < reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
3'b111:
begin
wreg_o <= `WriteDisable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
id_is_branch_o <= 1'b1;
instvalid <= `InstValid;
if (reg1_o >= reg2_o)
begin
id_branch_res_o <= 1'b1;
if (pdt_res_i == 1'b1)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{19{inst_i[31]}},inst_i[31],inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
stallreq1 <= 1'b1;
end
end
else
begin
id_branch_res_o <= 1'b0;
if (pdt_res_i == 1'b0)
id_pdt_true_o <= 1'b1;
else
begin
id_pdt_true_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o <= pc_i+4;
stallreq1 <= 1'b1;
end
end
end
default: begin end
endcase
end
7'b1101111:
begin
wreg_o <= `WriteEnable;
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
branch_flag_o <= 1'b1;
branch_target_address_o
<= pc_i+{{11{inst_i[31]}},inst_i[31],inst_i[19:12],inst_i[20],inst_i[30:21],1'b0};
link_addr_o <= pc_i+4;
stallreq1 <= 1'b1;
instvalid <= `InstValid;
end
default: begin end
endcase
end
end
`define GET_OPRAND(reg_o,reg_read_o,reg_data_i,reg_addr_o) \
always @ (*) \
begin \
if (rst == `RstEnable) reg_o <= `ZeroWord; \
else if (reg_read_o == 1'b1) \
begin \
if (reg_addr_o == 5'b0) reg_o <= `ZeroWord; \
else if ((ex_wreg_i == 1'b1)&&(ex_wd_i == reg_addr_o)) \
reg_o <= ex_wdata_i; \
else if ((mem_wreg_i == 1'b1)&&(mem_wd_i == reg_addr_o)) \
reg_o <= mem_wdata_i; \
else if (reg_read_o == 1'b1) \
reg_o <= reg_data_i; \
else reg_o <= `ZeroWord; \
end \
else \
reg_o <= imm; \
end
`GET_OPRAND(reg1_o,reg1_read_o,reg1_data_i,reg1_addr_o)
`GET_OPRAND(reg2_o,reg2_read_o,reg2_data_i,reg2_addr_o)
reg stallreq_for_reg1,stallreq_for_reg2;
`define HAVE_TO_STOP(reg_read_o,reg_addr_o,stallreq_for_reg) \
always @ (*) \
begin \
stallreq_for_reg <= 1'b0; \
if (rst == `RstEnable);\
else if ((reg_read_o == 1'b1&®_addr_o != `ZeroWord)&&ex_is_load_i == 1'b1&&(ex_wd_i == reg_addr_o)) \
stallreq_for_reg <= 1'b1; \
end
`HAVE_TO_STOP(reg1_read_o,reg1_addr_o,stallreq_for_reg1)
`HAVE_TO_STOP(reg2_read_o,reg2_addr_o,stallreq_for_reg2)
always @ (*) stallreq2 <= stallreq_for_reg1|stallreq_for_reg2;
always @ (stallreq2 == 1) id_is_branch_o <= 1'b0;
endmodule | 48 |
5,359 | data/full_repos/permissive/113839829/Source/CPU/id_ex.v | 113,839,829 | id_ex.v | v | 80 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:15: Define or directive not defined: \'`AluOpBus\'\n input wire [`AluOpBus] id_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`AluOpBus] id_aluop,\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:16: Define or directive not defined: \'`AluSelBus\'\n input wire [`AluSelBus] id_alusel,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:17: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] id_reg1,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:18: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] id_reg2,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:19: Define or directive not defined: \'`RegAddrBus\'\n input wire [`RegAddrBus] id_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [`RegBus] id_link_address,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:21: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] id_link_address,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:22: Define or directive not defined: \'`RegBus\'\n input wire [`RegBus] id_inst, \n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:25: Define or directive not defined: \'`AluOpBus\'\n output reg [`AluOpBus] ex_aluop,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:26: Define or directive not defined: \'`AluSelBus\'\n output reg [`AluSelBus] ex_alusel,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:27: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] ex_reg1,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:28: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] ex_reg2,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:29: Define or directive not defined: \'`RegAddrBus\'\n output reg [`RegAddrBus] ex_wd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [`RegBus] ex_link_address,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:31: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] ex_link_address,\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:32: Define or directive not defined: \'`RegBus\'\n output reg [`RegBus] ex_inst\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:38: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:40: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:41: Define or directive not defined: \'`EXE_RES_NOP\'\n ex_alusel <= `EXE_RES_NOP;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:42: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:43: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:44: Define or directive not defined: \'`NOPRegAddr\'\n ex_wd <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:45: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:46: Define or directive not defined: \'`ZeroWord\'\n ex_link_address <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:47: Define or directive not defined: \'`ZeroWord\'\n ex_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:52: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:53: Define or directive not defined: \'`EXE_RES_NOP\'\n ex_alusel <= `EXE_RES_NOP;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:54: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:55: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:56: Define or directive not defined: \'`NOPRegAddr\'\n ex_wd <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:57: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:58: Define or directive not defined: \'`ZeroWord\'\n ex_link_address <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/id_ex.v:59: Define or directive not defined: \'`ZeroWord\'\n ex_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 35 error(s)\n' | 6,089 | module | module id_ex
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`AluOpBus] id_aluop,
input wire [`AluSelBus] id_alusel,
input wire [`RegBus] id_reg1,
input wire [`RegBus] id_reg2,
input wire [`RegAddrBus] id_wd,
input wire id_wreg,
input wire [`RegBus] id_link_address,
input wire [`RegBus] id_inst,
output reg [`AluOpBus] ex_aluop,
output reg [`AluSelBus] ex_alusel,
output reg [`RegBus] ex_reg1,
output reg [`RegBus] ex_reg2,
output reg [`RegAddrBus] ex_wd,
output reg ex_wreg,
output reg [`RegBus] ex_link_address,
output reg [`RegBus] ex_inst
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
end
else if (stall[2] == 1'b1&&stall[3] == 1'b0)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
end
else if (stall[2] == 1'b0)
begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_link_address <= id_link_address;
ex_inst <= id_inst;
end
end
endmodule | module id_ex
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`AluOpBus] id_aluop,
input wire [`AluSelBus] id_alusel,
input wire [`RegBus] id_reg1,
input wire [`RegBus] id_reg2,
input wire [`RegAddrBus] id_wd,
input wire id_wreg,
input wire [`RegBus] id_link_address,
input wire [`RegBus] id_inst,
output reg [`AluOpBus] ex_aluop,
output reg [`AluSelBus] ex_alusel,
output reg [`RegBus] ex_reg1,
output reg [`RegBus] ex_reg2,
output reg [`RegAddrBus] ex_wd,
output reg ex_wreg,
output reg [`RegBus] ex_link_address,
output reg [`RegBus] ex_inst
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
end
else if (stall[2] == 1'b1&&stall[3] == 1'b0)
begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_RES_NOP;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `NOPRegAddr;
ex_wreg <= `WriteDisable;
ex_link_address <= `ZeroWord;
ex_inst <= `ZeroWord;
end
else if (stall[2] == 1'b0)
begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_link_address <= id_link_address;
ex_inst <= id_inst;
end
end
endmodule | 48 |
5,360 | data/full_repos/permissive/113839829/Source/CPU/if_id.v | 113,839,829 | if_id.v | v | 63 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:14: Define or directive not defined: \'`InstAddrBus\'\n input wire [`InstAddrBus] if_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`InstAddrBus] if_pc,\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:15: Define or directive not defined: \'`InstBus\'\n input wire [`InstBus] if_inst,\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire which_pdt_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [9:0] history_i,\n ^~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [`InstAddrBus] id_pc,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:21: Define or directive not defined: \'`InstAddrBus\'\n output reg [`InstAddrBus] id_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:22: Define or directive not defined: \'`InstBus\'\n output reg [`InstBus] id_inst,\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg which_pdt_o,\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [9:0] history_o\n ^~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:27: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:32: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:34: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:35: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:42: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/if_id.v:43: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n' | 6,090 | module | module if_id
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`InstAddrBus] if_pc,
input wire [`InstBus] if_inst,
input wire pdt_res_i,
input wire which_pdt_i,
input wire [9:0] history_i,
output reg [`InstAddrBus] id_pc,
output reg [`InstBus] id_inst,
output reg pdt_res_o,
output reg which_pdt_o,
output reg [9:0] history_o
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
pdt_res_o <= 0;
which_pdt_o <= 0;
history_o <= 10'b0;
end
else if (stall[1] == 1'b1&&stall[2] == 1'b0)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
pdt_res_o <= 0;
which_pdt_o <= 0;
history_o <= 10'b0;
end
else if (stall[1] == 1'b0)
begin
id_pc <= if_pc;
id_inst <= if_inst;
pdt_res_o <= pdt_res_i;
which_pdt_o <= which_pdt_i;
history_o <= history_i;
end
end
endmodule | module if_id
(
input wire clk,
input wire rst,
input wire [5:0] stall,
input wire [`InstAddrBus] if_pc,
input wire [`InstBus] if_inst,
input wire pdt_res_i,
input wire which_pdt_i,
input wire [9:0] history_i,
output reg [`InstAddrBus] id_pc,
output reg [`InstBus] id_inst,
output reg pdt_res_o,
output reg which_pdt_o,
output reg [9:0] history_o
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
pdt_res_o <= 0;
which_pdt_o <= 0;
history_o <= 10'b0;
end
else if (stall[1] == 1'b1&&stall[2] == 1'b0)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
pdt_res_o <= 0;
which_pdt_o <= 0;
history_o <= 10'b0;
end
else if (stall[1] == 1'b0)
begin
id_pc <= if_pc;
id_inst <= if_inst;
pdt_res_o <= pdt_res_i;
which_pdt_o <= which_pdt_i;
history_o <= history_i;
end
end
endmodule | 48 |
5,361 | data/full_repos/permissive/113839829/Source/CPU/inst_rom.v | 113,839,829 | inst_rom.v | v | 40 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:9: Define or directive not defined: \'`InstAddrBus\'\n input wire [`InstAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire [`InstAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:11: Define or directive not defined: \'`InstBus\'\n output reg [`InstBus] inst,\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:14: Define or directive not defined: \'`InstAddrBus\'\n output wire [`InstAddrBus] pdt_pc,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:15: Define or directive not defined: \'`InstBus\'\n output reg [`InstBus] pdt_inst\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: Define or directive not defined: \'`InstBus\'\n reg[`InstBus] inst_mem[0:`InstMemNum];\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`InstBus] inst_mem[0:`InstMemNum];\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:20: Define or directive not defined: \'`InstMemNum\'\n reg[`InstBus] inst_mem[0:`InstMemNum];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:26: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) inst <= `ZeroWord;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/inst_rom.v:26: Define or directive not defined: \'`ZeroWord\'\n if (ce == `ChipDisable) inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 11 error(s)\n' | 6,091 | module | module inst_rom(
input wire ce,
input wire [`InstAddrBus] addr,
output reg [`InstBus] inst,
output wire [`InstAddrBus] pdt_pc,
output reg [`InstBus] pdt_inst
);
assign pdt_pc = addr;
reg[`InstBus] inst_mem[0:`InstMemNum];
initial $readmemh ("instr.data",inst_mem);
always @ (*)
begin
if (ce == `ChipDisable) inst <= `ZeroWord;
else
begin
inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
pdt_inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
end
end
endmodule | module inst_rom(
input wire ce,
input wire [`InstAddrBus] addr,
output reg [`InstBus] inst,
output wire [`InstAddrBus] pdt_pc,
output reg [`InstBus] pdt_inst
); |
assign pdt_pc = addr;
reg[`InstBus] inst_mem[0:`InstMemNum];
initial $readmemh ("instr.data",inst_mem);
always @ (*)
begin
if (ce == `ChipDisable) inst <= `ZeroWord;
else
begin
inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
pdt_inst <= {inst_mem[addr>>2][7:0],inst_mem[addr>>2][15:8],
inst_mem[addr>>2][23:16],inst_mem[addr>>2][31:24]};
end
end
endmodule | 48 |
5,362 | data/full_repos/permissive/113839829/Source/CPU/mem_sim.v | 113,839,829 | mem_sim.v | v | 88 | 88 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: Define or directive not defined: \'`InstBus\'\n reg [`InstBus] mem_data[0:`MemNumber];\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg [`InstBus] mem_data[0:`MemNumber];\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/mem_sim.v:28: Define or directive not defined: \'`MemNumber\'\n reg [`InstBus] mem_data[0:`MemNumber];\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 6,093 | module | module mem_sim
(
input wire clk,
input wire if_ms_req_i,
input wire [31:0] if_addr,
input wire mem_ms_req_i,
input wire [31:0] mem_addr,
input wire ms_write_i,
input wire [31:0] ms_write_data_i,
input wire [3:0] ms_write_mask_i,
output reg if_ms_rep_o,
output reg [63:0] if_ms_rep_data_o,
output reg mem_ms_rep_o,
output reg [63:0] mem_ms_rep_data_o
);
reg [`InstBus] mem_data[0:`MemNumber];
initial $readmemh("instr.data",mem_data);
always @ (*)
begin
if_ms_rep_o <= 0;
if_ms_rep_data_o <= 0;
if (if_ms_req_i == 1'b1)
begin
if_ms_rep_o <= 1;
if_ms_rep_data_o <= {mem_data[((if_addr>>3)<<1)+1],mem_data[(if_addr>>3)<<1]};
end
end
always @ (*)
begin
mem_ms_rep_o <= 0;
mem_ms_rep_data_o <= 0;
if (mem_ms_req_i == 1'b1)
begin
mem_ms_rep_o <= 1;
mem_ms_rep_data_o <= {mem_data[((mem_addr>>3)<<1)+1],mem_data[(mem_addr>>3)<<1]};
end
end
always @ (posedge clk)
begin
if (ms_write_i == 1'b1)
begin
if (ms_write_mask_i[3] == 1)
mem_data[mem_addr>>2][7:0] <= ms_write_data_i[31:24];
if (ms_write_mask_i[2] == 1)
mem_data[mem_addr>>2][15:8] <= ms_write_data_i[23:16];
if (ms_write_mask_i[1] == 1)
mem_data[mem_addr>>2][23:16] <= ms_write_data_i[15:8];
if (ms_write_mask_i[0] == 1)
begin
mem_data[mem_addr>>2][31:24] <= ms_write_data_i[7:0];
if (mem_addr == 32'h00000104)
$display("Print (%c)",ms_write_data_i[7:0]);
end
end
end
endmodule | module mem_sim
(
input wire clk,
input wire if_ms_req_i,
input wire [31:0] if_addr,
input wire mem_ms_req_i,
input wire [31:0] mem_addr,
input wire ms_write_i,
input wire [31:0] ms_write_data_i,
input wire [3:0] ms_write_mask_i,
output reg if_ms_rep_o,
output reg [63:0] if_ms_rep_data_o,
output reg mem_ms_rep_o,
output reg [63:0] mem_ms_rep_data_o
); |
reg [`InstBus] mem_data[0:`MemNumber];
initial $readmemh("instr.data",mem_data);
always @ (*)
begin
if_ms_rep_o <= 0;
if_ms_rep_data_o <= 0;
if (if_ms_req_i == 1'b1)
begin
if_ms_rep_o <= 1;
if_ms_rep_data_o <= {mem_data[((if_addr>>3)<<1)+1],mem_data[(if_addr>>3)<<1]};
end
end
always @ (*)
begin
mem_ms_rep_o <= 0;
mem_ms_rep_data_o <= 0;
if (mem_ms_req_i == 1'b1)
begin
mem_ms_rep_o <= 1;
mem_ms_rep_data_o <= {mem_data[((mem_addr>>3)<<1)+1],mem_data[(mem_addr>>3)<<1]};
end
end
always @ (posedge clk)
begin
if (ms_write_i == 1'b1)
begin
if (ms_write_mask_i[3] == 1)
mem_data[mem_addr>>2][7:0] <= ms_write_data_i[31:24];
if (ms_write_mask_i[2] == 1)
mem_data[mem_addr>>2][15:8] <= ms_write_data_i[23:16];
if (ms_write_mask_i[1] == 1)
mem_data[mem_addr>>2][23:16] <= ms_write_data_i[15:8];
if (ms_write_mask_i[0] == 1)
begin
mem_data[mem_addr>>2][31:24] <= ms_write_data_i[7:0];
if (mem_addr == 32'h00000104)
$display("Print (%c)",ms_write_data_i[7:0]);
end
end
end
endmodule | 48 |
5,364 | data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v | 113,839,829 | openmips_min_sopc.v | v | 142 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 92: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:5: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:6: Cannot find include file: openmips.v\n `include "openmips.v" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:9: Cannot find include file: mem_sim.v\n `include "mem_sim.v" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:10: Cannot find include file: dcache.v\n `include "dcache.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:11: Cannot find include file: icache.v\n `include "icache.v" \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:19: Define or directive not defined: \'`InstAddrBus\'\n wire [`InstAddrBus] inst_addr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`InstAddrBus] inst_addr;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:20: Define or directive not defined: \'`InstBus\'\n wire [`InstBus] inst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`InstBus] inst;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:27: Define or directive not defined: \'`RegBus\'\n wire [`RegBus] mem_addr_i;\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`RegBus] mem_addr_i;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:28: Define or directive not defined: \'`RegBus\'\n wire [`RegBus] mem_data_i;\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`RegBus] mem_data_i;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:29: Define or directive not defined: \'`RegBus\'\n wire [`RegBus] mem_data_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`RegBus] mem_data_o;\n ^\n%Error: Exiting due to 15 error(s)\n' | 6,096 | module | module openmips_min_sopc
(
input wire clk,
input wire rst
);
wire [`InstAddrBus] inst_addr;
wire [`InstBus] inst;
wire rom_ce;
wire mem_ce;
wire mem_we_i;
wire mem_re_i;
wire [`RegBus] mem_addr_i;
wire [`RegBus] mem_data_i;
wire [`RegBus] mem_data_o;
wire [3:0] mem_sel_i;
wire stallreq_from_if_cache;
wire stallreq_from_mem_cache;
openmips openmips0
(
.clk(clk),
.rst(rst),
.rom_data_i(inst),
.rom_addr_o(inst_addr),
.rom_ce_o(rom_ce),
.ram_data_i(mem_data_o),
.ram_addr_o(mem_addr_i),
.ram_data_o(mem_data_i),
.ram_we_o(mem_we_i),
.ram_re_o(mem_re_i),
.ram_sel_o(mem_sel_i),
.ram_ce_o(mem_ce_i),
.stallreq_from_if_cache(stallreq_from_if_cache),
.stallreq_from_mem_cache(stallreq_from_mem_cache)
);
wire if_cache_req_o;
wire [31:0] if_cache_addr_o;
wire if_cache_rep_i;
wire [63:0] if_cache_rep_data_i;
icache if_cache
(
.clk(clk),
.rst(rst),
.ce(rom_ce),
.addr(inst_addr),
.read_flag(1'b1),
.read_data(inst),
.cache_req_o(if_cache_req_o),
.cache_addr_o(if_cache_addr_o),
.cache_rep_i(if_cache_rep_i),
.cache_rep_data_i(if_cache_rep_data_i),
.stallreq(stallreq_from_if_cache)
);
wire mem_cache_req_o;
wire [31:0] mem_cache_addr_o;
wire mem_cache_write_o;
wire [31:0] mem_cache_data_o;
wire [3:0] mem_cache_mask_o;
wire mem_cache_rep_i;
wire [63:0] mem_cache_rep_data_i;
dcache mem_cache
(
.clk(clk),
.rst(rst),
.ce(mem_ce),
.addr(mem_addr_i),
.read_flag(mem_re_i),
.read_data(mem_data_o),
.write_data(mem_data_i),
.write_mask(mem_sel_i),
.write_flag(mem_we_i),
.cache_req_o(mem_cache_req_o),
.cache_addr_o(mem_cache_addr_o),
.cache_write_o(mem_cache_write_o),
.cache_write_data_o(mem_cache_data_o),
.cache_write_mask_o(mem_cache_mask_o),
.cache_rep_i(mem_cache_rep_i),
.cache_rep_data_i(mem_cache_rep_data_i),
.stallreq(stallreq_from_mem_cache)
);
mem_sim mem_sim0
(
.clk(clk),
.if_ms_req_i(if_cache_req_o),
.if_addr(if_cache_addr_o),
.mem_ms_req_i(mem_cache_req_o),
.mem_addr(mem_cache_addr_o),
.ms_write_i(mem_cache_write_o),
.ms_write_data_i(mem_cache_data_o),
.ms_write_mask_i(mem_cache_mask_o),
.if_ms_rep_o(if_cache_rep_i),
.if_ms_rep_data_o(if_cache_rep_data_i),
.mem_ms_rep_o(mem_cache_rep_i),
.mem_ms_rep_data_o(mem_cache_rep_data_i)
);
endmodule | module openmips_min_sopc
(
input wire clk,
input wire rst
); |
wire [`InstAddrBus] inst_addr;
wire [`InstBus] inst;
wire rom_ce;
wire mem_ce;
wire mem_we_i;
wire mem_re_i;
wire [`RegBus] mem_addr_i;
wire [`RegBus] mem_data_i;
wire [`RegBus] mem_data_o;
wire [3:0] mem_sel_i;
wire stallreq_from_if_cache;
wire stallreq_from_mem_cache;
openmips openmips0
(
.clk(clk),
.rst(rst),
.rom_data_i(inst),
.rom_addr_o(inst_addr),
.rom_ce_o(rom_ce),
.ram_data_i(mem_data_o),
.ram_addr_o(mem_addr_i),
.ram_data_o(mem_data_i),
.ram_we_o(mem_we_i),
.ram_re_o(mem_re_i),
.ram_sel_o(mem_sel_i),
.ram_ce_o(mem_ce_i),
.stallreq_from_if_cache(stallreq_from_if_cache),
.stallreq_from_mem_cache(stallreq_from_mem_cache)
);
wire if_cache_req_o;
wire [31:0] if_cache_addr_o;
wire if_cache_rep_i;
wire [63:0] if_cache_rep_data_i;
icache if_cache
(
.clk(clk),
.rst(rst),
.ce(rom_ce),
.addr(inst_addr),
.read_flag(1'b1),
.read_data(inst),
.cache_req_o(if_cache_req_o),
.cache_addr_o(if_cache_addr_o),
.cache_rep_i(if_cache_rep_i),
.cache_rep_data_i(if_cache_rep_data_i),
.stallreq(stallreq_from_if_cache)
);
wire mem_cache_req_o;
wire [31:0] mem_cache_addr_o;
wire mem_cache_write_o;
wire [31:0] mem_cache_data_o;
wire [3:0] mem_cache_mask_o;
wire mem_cache_rep_i;
wire [63:0] mem_cache_rep_data_i;
dcache mem_cache
(
.clk(clk),
.rst(rst),
.ce(mem_ce),
.addr(mem_addr_i),
.read_flag(mem_re_i),
.read_data(mem_data_o),
.write_data(mem_data_i),
.write_mask(mem_sel_i),
.write_flag(mem_we_i),
.cache_req_o(mem_cache_req_o),
.cache_addr_o(mem_cache_addr_o),
.cache_write_o(mem_cache_write_o),
.cache_write_data_o(mem_cache_data_o),
.cache_write_mask_o(mem_cache_mask_o),
.cache_rep_i(mem_cache_rep_i),
.cache_rep_data_i(mem_cache_rep_data_i),
.stallreq(stallreq_from_mem_cache)
);
mem_sim mem_sim0
(
.clk(clk),
.if_ms_req_i(if_cache_req_o),
.if_addr(if_cache_addr_o),
.mem_ms_req_i(mem_cache_req_o),
.mem_addr(mem_cache_addr_o),
.ms_write_i(mem_cache_write_o),
.ms_write_data_i(mem_cache_data_o),
.ms_write_mask_i(mem_cache_mask_o),
.if_ms_rep_o(if_cache_rep_i),
.if_ms_rep_data_o(if_cache_rep_data_i),
.mem_ms_rep_o(mem_cache_rep_i),
.mem_ms_rep_data_o(mem_cache_rep_data_i)
);
endmodule | 48 |
5,365 | data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v | 113,839,829 | openmips_min_sopc_tb.v | v | 40 | 84 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 113: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:7: Cannot find include file: defines.v\n `include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.v\n data/full_repos/permissive/113839829/Source/CPU,data/full_repos/permissive/113839829/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:8: Cannot find include file: openmips_min_sopc.v\n `include "openmips_min_sopc.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:25: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:26: Define or directive not defined: \'`RstDisable\'\n #19 rst = `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #19 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #19 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113839829/Source/CPU/openmips_min_sopc_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2040 $finish;\n ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n' | 6,097 | module | module openmips_min_sopc_tb();
reg CLOCK_50;
reg rst;
integer i;
initial
begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial
begin
rst = `RstEnable;
#19 rst = `RstDisable;
#2040 $finish;
end
openmips_min_sopc openmips_min_sopc0
(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | module openmips_min_sopc_tb(); |
reg CLOCK_50;
reg rst;
integer i;
initial
begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial
begin
rst = `RstEnable;
#19 rst = `RstDisable;
#2040 $finish;
end
openmips_min_sopc openmips_min_sopc0
(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | 48 |
5,370 | data/full_repos/permissive/113890540/icestorm version/j1.v | 113,890,540 | j1.v | v | 230 | 141 | [] | [] | [] | null | line:106: before: "." | null | 1: b'%Error: Cannot find file containing module: version,data/full_repos/permissive/113890540\n ... Looked in:\n data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540\n data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540.v\n data/full_repos/permissive/113890540/icestorm/version,data/full_repos/permissive/113890540.sv\n version,data/full_repos/permissive/113890540\n version,data/full_repos/permissive/113890540.v\n version,data/full_repos/permissive/113890540.sv\n obj_dir/version,data/full_repos/permissive/113890540\n obj_dir/version,data/full_repos/permissive/113890540.v\n obj_dir/version,data/full_repos/permissive/113890540.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/113890540/icestorm\n%Error: Cannot find file containing module: version/j1.v\n%Error: Exiting due to 3 error(s)\n' | 6,107 | module | module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [15:0] dout,
input wire [15:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn_from_memory,
input wire [7:0] int_rqst
);
reg [4:0] rsp, rspN;
reg [4:0] dsp, dspN;
reg [15:0] st0, st0N;
reg dstkW;
reg rstkW;
wire [15:0] rstkD;
reg [15:0] insn;
reg [13:0] pc, pcN;
reg interrupt_enable = 0;
wire interrupt_request = |( int_rqst );
wire interrupt = interrupt_request & interrupt_enable;
always @* begin
casex (int_rqst)
8'b1xxxxxxx : insn = interrupt ? 16'h5DFF : insn_from_memory;
8'b01xxxxxx : insn = interrupt ? 16'h5DFE : insn_from_memory;
8'b001xxxxx : insn = interrupt ? 16'h5DFD : insn_from_memory;
8'b0001xxxx : insn = interrupt ? 16'h5DFC : insn_from_memory;
8'b00001xxx : insn = interrupt ? 16'h5DFB : insn_from_memory;
8'b000001xx : insn = interrupt ? 16'h5DFA : insn_from_memory;
8'b0000001x : insn = interrupt ? 16'h5DF9 : insn_from_memory;
8'b00000001 : insn = interrupt ? 16'h5DF8 : insn_from_memory;
default : insn = insn_from_memory;
endcase
end
wire [13:0] pc_plus_1 = pc + {13'b0, ~interrupt};
wire fetch = pc[13] & ~interrupt;
reg notreboot = 0;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
wire [15:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(32)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(32)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
wire unsignedless = minus[16];
wire zeroflag = minus[15:0] == 0;
SB_MAC16 i_sbmac16 (
.A(st0),
.B(st1),
.C(16'h0000),
.D(16'h0000),
.O(umstar),
.CLK(0),
.CE(1),
.IRSTTOP(0),
.IRSTBOT(0),
.ORSTTOP(0),
.ORSTBOT(0),
.AHOLD(1),
.BHOLD(1),
.CHOLD(0),
.DHOLD(0),
.OHOLDTOP(0),
.OHOLDBOT(0),
.OLOADTOP(0),
.OLOADBOT(0),
.ADDSUBTOP(0),
.ADDSUBBOT(0),
.CO(),
.CI(0),
.ACCUMCI(),
.ACCUMCO(),
.SIGNEXTIN(0),
.SIGNEXTOUT() );
defparam i_sbmac16.B_SIGNED = 1'b0 ;
defparam i_sbmac16.A_SIGNED = 1'b0 ;
defparam i_sbmac16.BOTOUTPUT_SELECT = 2'b11 ;
defparam i_sbmac16.TOPOUTPUT_SELECT = 2'b11 ;
wire [31:0] umstar;
always @*
begin
casez ({fetch, insn[15:8]})
9'b0_011_00001: st0N = st1;
9'b0_011_00010: st0N = st0 + st1;
9'b0_011_00011: st0N = st0 & st1;
9'b0_011_00100: st0N = st0 | st1;
9'b0_011_00101: st0N = st0 ^ st1;
9'b0_011_00110: st0N = ~st0;
9'b0_011_00111: st0N = {16{zeroflag}};
9'b0_011_01000: st0N = {16{signedless}};
9'b0_011_01001: st0N = {st0[15], st0[15:1]};
9'b0_011_01010: st0N = {st0[14:0], 1'b0};
9'b0_011_01011: st0N = rst0;
9'b0_011_01100: st0N = minus[15:0];
9'b0_011_01101: st0N = io_din;
9'b0_011_01110: st0N = {11'b0, dsp};
9'b0_011_01111: st0N = {16{unsignedless}};
9'b1_???_?????: st0N = insn;
9'b0_1??_?????: st0N = { 1'b0, insn[14:0] };
9'b0_001_?????: st0N = st1;
9'b0_011_10000: st0N = st1 << st0;
9'b0_011_10001: st0N = st1 >> st0;
9'b0_011_10010: st0N = $signed(st1) >>> st0;
9'b0_011_10011: st0N = {11'b0, rsp};
9'b0_011_10100: st0N = umstar[15:0];
9'b0_011_10101: st0N = umstar[31:16];
9'b0_011_10110: st0N = st0 + 1;
9'b0_011_10111: st0N = st0 - 1;
default: st0N = st0;
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire func_dint = (insn[6:4] == 6);
wire func_eint = (insn[6:4] == 7);
wire is_alu = notreboot & !fetch & (insn[15:13] == 3'b011);
assign mem_wr = is_alu & func_write;
assign io_wr = is_alu & func_iow;
assign io_rd = is_alu & func_ior;
assign dout = st1;
wire eint = is_alu & func_eint;
wire dint = is_alu & func_dint;
wire interrupt_enableN = (interrupt_enable | eint) & ~(interrupt | dint);
assign rstkD = (insn[13] == 1'b0) ? {1'b0, pc_plus_1, interrupt_enable} : st0;
always @*
begin
casez ({fetch, insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({fetch, insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
rspN = rsp + {rspI[1], rspI[1], rspI[1], rspI};
casez ({notreboot, fetch, insn[15:13], insn[7], |st0})
7'b0_0_???_?_?: pcN = 0;
7'b1_0_000_?_?,
7'b1_0_010_?_?,
7'b1_0_001_?_0: pcN = {1'b0, insn[12:0]};
7'b1_1_???_?_?,
7'b1_0_011_1_?: pcN = rst0[14:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
notreboot <= 0;
{ pc, dsp, rsp, st0, interrupt_enable} <= 0;
end else begin
notreboot <= 1;
{ pc, dsp, rsp, st0, interrupt_enable} <= { pcN, dspN, rspN, st0N, interrupt_enableN };
end
end
endmodule | module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [15:0] dout,
input wire [15:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn_from_memory,
input wire [7:0] int_rqst
); |
reg [4:0] rsp, rspN;
reg [4:0] dsp, dspN;
reg [15:0] st0, st0N;
reg dstkW;
reg rstkW;
wire [15:0] rstkD;
reg [15:0] insn;
reg [13:0] pc, pcN;
reg interrupt_enable = 0;
wire interrupt_request = |( int_rqst );
wire interrupt = interrupt_request & interrupt_enable;
always @* begin
casex (int_rqst)
8'b1xxxxxxx : insn = interrupt ? 16'h5DFF : insn_from_memory;
8'b01xxxxxx : insn = interrupt ? 16'h5DFE : insn_from_memory;
8'b001xxxxx : insn = interrupt ? 16'h5DFD : insn_from_memory;
8'b0001xxxx : insn = interrupt ? 16'h5DFC : insn_from_memory;
8'b00001xxx : insn = interrupt ? 16'h5DFB : insn_from_memory;
8'b000001xx : insn = interrupt ? 16'h5DFA : insn_from_memory;
8'b0000001x : insn = interrupt ? 16'h5DF9 : insn_from_memory;
8'b00000001 : insn = interrupt ? 16'h5DF8 : insn_from_memory;
default : insn = insn_from_memory;
endcase
end
wire [13:0] pc_plus_1 = pc + {13'b0, ~interrupt};
wire fetch = pc[13] & ~interrupt;
reg notreboot = 0;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
wire [15:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(32)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(32)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
wire unsignedless = minus[16];
wire zeroflag = minus[15:0] == 0;
SB_MAC16 i_sbmac16 (
.A(st0),
.B(st1),
.C(16'h0000),
.D(16'h0000),
.O(umstar),
.CLK(0),
.CE(1),
.IRSTTOP(0),
.IRSTBOT(0),
.ORSTTOP(0),
.ORSTBOT(0),
.AHOLD(1),
.BHOLD(1),
.CHOLD(0),
.DHOLD(0),
.OHOLDTOP(0),
.OHOLDBOT(0),
.OLOADTOP(0),
.OLOADBOT(0),
.ADDSUBTOP(0),
.ADDSUBBOT(0),
.CO(),
.CI(0),
.ACCUMCI(),
.ACCUMCO(),
.SIGNEXTIN(0),
.SIGNEXTOUT() );
defparam i_sbmac16.B_SIGNED = 1'b0 ;
defparam i_sbmac16.A_SIGNED = 1'b0 ;
defparam i_sbmac16.BOTOUTPUT_SELECT = 2'b11 ;
defparam i_sbmac16.TOPOUTPUT_SELECT = 2'b11 ;
wire [31:0] umstar;
always @*
begin
casez ({fetch, insn[15:8]})
9'b0_011_00001: st0N = st1;
9'b0_011_00010: st0N = st0 + st1;
9'b0_011_00011: st0N = st0 & st1;
9'b0_011_00100: st0N = st0 | st1;
9'b0_011_00101: st0N = st0 ^ st1;
9'b0_011_00110: st0N = ~st0;
9'b0_011_00111: st0N = {16{zeroflag}};
9'b0_011_01000: st0N = {16{signedless}};
9'b0_011_01001: st0N = {st0[15], st0[15:1]};
9'b0_011_01010: st0N = {st0[14:0], 1'b0};
9'b0_011_01011: st0N = rst0;
9'b0_011_01100: st0N = minus[15:0];
9'b0_011_01101: st0N = io_din;
9'b0_011_01110: st0N = {11'b0, dsp};
9'b0_011_01111: st0N = {16{unsignedless}};
9'b1_???_?????: st0N = insn;
9'b0_1??_?????: st0N = { 1'b0, insn[14:0] };
9'b0_001_?????: st0N = st1;
9'b0_011_10000: st0N = st1 << st0;
9'b0_011_10001: st0N = st1 >> st0;
9'b0_011_10010: st0N = $signed(st1) >>> st0;
9'b0_011_10011: st0N = {11'b0, rsp};
9'b0_011_10100: st0N = umstar[15:0];
9'b0_011_10101: st0N = umstar[31:16];
9'b0_011_10110: st0N = st0 + 1;
9'b0_011_10111: st0N = st0 - 1;
default: st0N = st0;
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire func_dint = (insn[6:4] == 6);
wire func_eint = (insn[6:4] == 7);
wire is_alu = notreboot & !fetch & (insn[15:13] == 3'b011);
assign mem_wr = is_alu & func_write;
assign io_wr = is_alu & func_iow;
assign io_rd = is_alu & func_ior;
assign dout = st1;
wire eint = is_alu & func_eint;
wire dint = is_alu & func_dint;
wire interrupt_enableN = (interrupt_enable | eint) & ~(interrupt | dint);
assign rstkD = (insn[13] == 1'b0) ? {1'b0, pc_plus_1, interrupt_enable} : st0;
always @*
begin
casez ({fetch, insn[15:13]})
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01};
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11};
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({fetch, insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01};
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]};
default: {rstkW, rspI} = {1'b0, 2'b00};
endcase
rspN = rsp + {rspI[1], rspI[1], rspI[1], rspI};
casez ({notreboot, fetch, insn[15:13], insn[7], |st0})
7'b0_0_???_?_?: pcN = 0;
7'b1_0_000_?_?,
7'b1_0_010_?_?,
7'b1_0_001_?_0: pcN = {1'b0, insn[12:0]};
7'b1_1_???_?_?,
7'b1_0_011_1_?: pcN = rst0[14:1];
default: pcN = pc_plus_1;
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
notreboot <= 0;
{ pc, dsp, rsp, st0, interrupt_enable} <= 0;
end else begin
notreboot <= 1;
{ pc, dsp, rsp, st0, interrupt_enable} <= { pcN, dspN, rspN, st0N, interrupt_enableN };
end
end
endmodule | 15 |
5,384 | data/full_repos/permissive/113904439/src/rtl/blake2s_G.v | 113,904,439 | blake2s_G.v | v | 113 | 73 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(42, 108)] | null | data/verilator_xmls/c2eefe68-524b-4c67-a529-1a217fb561aa.xml | null | 6,127 | module | module blake2s_G(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
input wire [31 : 0] m0,
input wire [31 : 0] m1,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
);
reg [31 : 0] a1;
reg [31 : 0] a2;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] b4;
reg [31 : 0] c1;
reg [31 : 0] c2;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
reg [31 : 0] d4;
assign a_prim = a2;
assign b_prim = b4;
assign c_prim = c2;
assign d_prim = d4;
always @*
begin : G_function
a1 = a + b + m0;
d1 = d ^ a1;
d2 = {d1[15 : 0], d1[31 : 16]};
c1 = c + d2;
b1 = b ^ c1;
b2 = {b1[11 : 0], b1[31 : 12]};
a2 = a1 + b2 + m1;
d3 = d2 ^ a2;
d4 = {d3[7 : 0], d3[31 : 8]};
c2 = c1 + d4;
b3 = b2 ^ c2;
b4 = {b3[6 : 0], b3[31 : 7]};
end
endmodule | module blake2s_G(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
input wire [31 : 0] m0,
input wire [31 : 0] m1,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
); |
reg [31 : 0] a1;
reg [31 : 0] a2;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] b4;
reg [31 : 0] c1;
reg [31 : 0] c2;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
reg [31 : 0] d4;
assign a_prim = a2;
assign b_prim = b4;
assign c_prim = c2;
assign d_prim = d4;
always @*
begin : G_function
a1 = a + b + m0;
d1 = d ^ a1;
d2 = {d1[15 : 0], d1[31 : 16]};
c1 = c + d2;
b1 = b ^ c1;
b2 = {b1[11 : 0], b1[31 : 12]};
a2 = a1 + b2 + m1;
d3 = d2 ^ a2;
d4 = {d3[7 : 0], d3[31 : 8]};
c2 = c1 + d4;
b3 = b2 ^ c2;
b4 = {b3[6 : 0], b3[31 : 7]};
end
endmodule | 16 |
5,385 | data/full_repos/permissive/113904439/src/rtl/blake2s_m_select.v | 113,904,439 | blake2s_m_select.v | v | 392 | 93 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(49, 387)] | null | data/verilator_xmls/237826bf-a658-4ef7-af60-7917da324549.xml | null | 6,128 | module | module blake2s_m_select(
input wire clk,
input wire reset_n,
input wire load,
input wire [511 : 0] m,
input wire [3 : 0] round,
input wire mode,
output wire [31 : 0] G0_m0,
output wire [31 : 0] G0_m1,
output wire [31 : 0] G1_m0,
output wire [31 : 0] G1_m1,
output wire [31 : 0] G2_m0,
output wire [31 : 0] G2_m1,
output wire [31 : 0] G3_m0,
output wire [31 : 0] G3_m1
);
reg [31 : 0] m_mem [0 : 15];
reg [3 : 0] i_G0_m0;
reg [3 : 0] i_G0_m1;
reg [3 : 0] i_G1_m0;
reg [3 : 0] i_G1_m1;
reg [3 : 0] i_G2_m0;
reg [3 : 0] i_G2_m1;
reg [3 : 0] i_G3_m0;
reg [3 : 0] i_G3_m1;
assign G0_m0 = m_mem[i_G0_m0];
assign G0_m1 = m_mem[i_G0_m1];
assign G1_m0 = m_mem[i_G1_m0];
assign G1_m1 = m_mem[i_G1_m1];
assign G2_m0 = m_mem[i_G2_m0];
assign G2_m1 = m_mem[i_G2_m1];
assign G3_m0 = m_mem[i_G3_m0];
assign G3_m1 = m_mem[i_G3_m1];
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
m_mem[i] <= 32'h0;
end
else
begin
if (load)
begin
m_mem[00] <= {m[0487 : 0480], m[0495 : 0488], m[0503 : 0496], m[0511 : 0504]};
m_mem[01] <= {m[0455 : 0448], m[0463 : 0456], m[0471 : 0464], m[0479 : 0472]};
m_mem[02] <= {m[0423 : 0416], m[0431 : 0424], m[0439 : 0432], m[0447 : 0440]};
m_mem[03] <= {m[0391 : 0384], m[0399 : 0392], m[0407 : 0400], m[0415 : 0408]};
m_mem[04] <= {m[0359 : 0352], m[0367 : 0360], m[0375 : 0368], m[0383 : 0376]};
m_mem[05] <= {m[0327 : 0320], m[0335 : 0328], m[0343 : 0336], m[0351 : 0344]};
m_mem[06] <= {m[0295 : 0288], m[0303 : 0296], m[0311 : 0304], m[0319 : 0312]};
m_mem[07] <= {m[0263 : 0256], m[0271 : 0264], m[0279 : 0272], m[0287 : 0280]};
m_mem[08] <= {m[0231 : 0224], m[0239 : 0232], m[0247 : 0240], m[0255 : 0248]};
m_mem[09] <= {m[0199 : 0192], m[0207 : 0200], m[0215 : 0208], m[0223 : 0216]};
m_mem[10] <= {m[0167 : 0160], m[0175 : 0168], m[0183 : 0176], m[0191 : 0184]};
m_mem[11] <= {m[0135 : 0128], m[0143 : 0136], m[0151 : 0144], m[0159 : 0152]};
m_mem[12] <= {m[0103 : 0096], m[0111 : 0104], m[0119 : 0112], m[0127 : 0120]};
m_mem[13] <= {m[0071 : 0064], m[0079 : 0072], m[0087 : 0080], m[0095 : 0088]};
m_mem[14] <= {m[0039 : 0032], m[0047 : 0040], m[0055 : 0048], m[0063 : 0056]};
m_mem[15] <= {m[0007 : 0000], m[0015 : 0008], m[0023 : 0016], m[0031 : 0024]};
end
end
end
always @*
begin : get_indices
i_G0_m0 = 4'd0;
i_G0_m1 = 4'd0;
i_G1_m0 = 4'd0;
i_G1_m1 = 4'd0;
i_G2_m0 = 4'd0;
i_G2_m1 = 4'd0;
i_G3_m0 = 4'd0;
i_G3_m1 = 4'd0;
case ({round, mode})
0: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd02;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd05;
i_G3_m0 = 4'd06;
i_G3_m1 = 4'd07;
end
1: begin
i_G0_m0 = 4'd08;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd10;
i_G1_m1 = 4'd11;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd14;
i_G3_m1 = 4'd15;
end
2: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd10;
i_G1_m0 = 4'd04;
i_G1_m1 = 4'd08;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd15;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd06;
end
3: begin
i_G0_m0 = 4'd01;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd00;
i_G1_m1 = 4'd02;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd07;
i_G3_m0 = 4'd05;
i_G3_m1 = 4'd03;
end
4: begin
i_G0_m0 = 4'd11;
i_G0_m1 = 4'd08;
i_G1_m0 = 4'd12;
i_G1_m1 = 4'd00;
i_G2_m0 = 4'd05;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd13;
end
5: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd14;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd06;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd09;
i_G3_m1 = 4'd04;
end
6: begin
i_G0_m0 = 4'd07;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd01;
i_G2_m0 = 4'd13;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd11;
i_G3_m1 = 4'd14;
end
7: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd06;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd00;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd08;
end
8: begin
i_G0_m0 = 4'd09;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd02;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd15;
end
9: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd11;
i_G1_m1 = 4'd12;
i_G2_m0 = 4'd06;
i_G2_m1 = 4'd08;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd13;
end
10: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd00;
i_G2_m1 = 4'd11;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd03;
end
11: begin
i_G0_m0 = 4'd04;
i_G0_m1 = 4'd13;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd05;
i_G2_m0 = 4'd15;
i_G2_m1 = 4'd14;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd09;
end
12: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd05;
i_G1_m0 = 4'd01;
i_G1_m1 = 4'd15;
i_G2_m0 = 4'd14;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd04;
i_G3_m1 = 4'd10;
end
13: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd07;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd11;
end
14: begin
i_G0_m0 = 4'd13;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd09;
end
15: begin
i_G0_m0 = 4'd05;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd15;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd08;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd02;
i_G3_m1 = 4'd10;
end
16: begin
i_G0_m0 = 4'd06;
i_G0_m1 = 4'd15;
i_G1_m0 = 4'd14;
i_G1_m1 = 4'd09;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd03;
i_G3_m0 = 4'd00;
i_G3_m1 = 4'd08;
end
17: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd13;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd01;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd05;
end
18: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd08;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd05;
end
19: begin
i_G0_m0 = 4'd15;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd09;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd03;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd00;
end
default: begin end
endcase
end
endmodule | module blake2s_m_select(
input wire clk,
input wire reset_n,
input wire load,
input wire [511 : 0] m,
input wire [3 : 0] round,
input wire mode,
output wire [31 : 0] G0_m0,
output wire [31 : 0] G0_m1,
output wire [31 : 0] G1_m0,
output wire [31 : 0] G1_m1,
output wire [31 : 0] G2_m0,
output wire [31 : 0] G2_m1,
output wire [31 : 0] G3_m0,
output wire [31 : 0] G3_m1
); |
reg [31 : 0] m_mem [0 : 15];
reg [3 : 0] i_G0_m0;
reg [3 : 0] i_G0_m1;
reg [3 : 0] i_G1_m0;
reg [3 : 0] i_G1_m1;
reg [3 : 0] i_G2_m0;
reg [3 : 0] i_G2_m1;
reg [3 : 0] i_G3_m0;
reg [3 : 0] i_G3_m1;
assign G0_m0 = m_mem[i_G0_m0];
assign G0_m1 = m_mem[i_G0_m1];
assign G1_m0 = m_mem[i_G1_m0];
assign G1_m1 = m_mem[i_G1_m1];
assign G2_m0 = m_mem[i_G2_m0];
assign G2_m1 = m_mem[i_G2_m1];
assign G3_m0 = m_mem[i_G3_m0];
assign G3_m1 = m_mem[i_G3_m1];
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
m_mem[i] <= 32'h0;
end
else
begin
if (load)
begin
m_mem[00] <= {m[0487 : 0480], m[0495 : 0488], m[0503 : 0496], m[0511 : 0504]};
m_mem[01] <= {m[0455 : 0448], m[0463 : 0456], m[0471 : 0464], m[0479 : 0472]};
m_mem[02] <= {m[0423 : 0416], m[0431 : 0424], m[0439 : 0432], m[0447 : 0440]};
m_mem[03] <= {m[0391 : 0384], m[0399 : 0392], m[0407 : 0400], m[0415 : 0408]};
m_mem[04] <= {m[0359 : 0352], m[0367 : 0360], m[0375 : 0368], m[0383 : 0376]};
m_mem[05] <= {m[0327 : 0320], m[0335 : 0328], m[0343 : 0336], m[0351 : 0344]};
m_mem[06] <= {m[0295 : 0288], m[0303 : 0296], m[0311 : 0304], m[0319 : 0312]};
m_mem[07] <= {m[0263 : 0256], m[0271 : 0264], m[0279 : 0272], m[0287 : 0280]};
m_mem[08] <= {m[0231 : 0224], m[0239 : 0232], m[0247 : 0240], m[0255 : 0248]};
m_mem[09] <= {m[0199 : 0192], m[0207 : 0200], m[0215 : 0208], m[0223 : 0216]};
m_mem[10] <= {m[0167 : 0160], m[0175 : 0168], m[0183 : 0176], m[0191 : 0184]};
m_mem[11] <= {m[0135 : 0128], m[0143 : 0136], m[0151 : 0144], m[0159 : 0152]};
m_mem[12] <= {m[0103 : 0096], m[0111 : 0104], m[0119 : 0112], m[0127 : 0120]};
m_mem[13] <= {m[0071 : 0064], m[0079 : 0072], m[0087 : 0080], m[0095 : 0088]};
m_mem[14] <= {m[0039 : 0032], m[0047 : 0040], m[0055 : 0048], m[0063 : 0056]};
m_mem[15] <= {m[0007 : 0000], m[0015 : 0008], m[0023 : 0016], m[0031 : 0024]};
end
end
end
always @*
begin : get_indices
i_G0_m0 = 4'd0;
i_G0_m1 = 4'd0;
i_G1_m0 = 4'd0;
i_G1_m1 = 4'd0;
i_G2_m0 = 4'd0;
i_G2_m1 = 4'd0;
i_G3_m0 = 4'd0;
i_G3_m1 = 4'd0;
case ({round, mode})
0: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd02;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd05;
i_G3_m0 = 4'd06;
i_G3_m1 = 4'd07;
end
1: begin
i_G0_m0 = 4'd08;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd10;
i_G1_m1 = 4'd11;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd14;
i_G3_m1 = 4'd15;
end
2: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd10;
i_G1_m0 = 4'd04;
i_G1_m1 = 4'd08;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd15;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd06;
end
3: begin
i_G0_m0 = 4'd01;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd00;
i_G1_m1 = 4'd02;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd07;
i_G3_m0 = 4'd05;
i_G3_m1 = 4'd03;
end
4: begin
i_G0_m0 = 4'd11;
i_G0_m1 = 4'd08;
i_G1_m0 = 4'd12;
i_G1_m1 = 4'd00;
i_G2_m0 = 4'd05;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd13;
end
5: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd14;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd06;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd09;
i_G3_m1 = 4'd04;
end
6: begin
i_G0_m0 = 4'd07;
i_G0_m1 = 4'd09;
i_G1_m0 = 4'd03;
i_G1_m1 = 4'd01;
i_G2_m0 = 4'd13;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd11;
i_G3_m1 = 4'd14;
end
7: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd06;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd04;
i_G2_m1 = 4'd00;
i_G3_m0 = 4'd15;
i_G3_m1 = 4'd08;
end
8: begin
i_G0_m0 = 4'd09;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd05;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd02;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd15;
end
9: begin
i_G0_m0 = 4'd14;
i_G0_m1 = 4'd01;
i_G1_m0 = 4'd11;
i_G1_m1 = 4'd12;
i_G2_m0 = 4'd06;
i_G2_m1 = 4'd08;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd13;
end
10: begin
i_G0_m0 = 4'd02;
i_G0_m1 = 4'd12;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd10;
i_G2_m0 = 4'd00;
i_G2_m1 = 4'd11;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd03;
end
11: begin
i_G0_m0 = 4'd04;
i_G0_m1 = 4'd13;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd05;
i_G2_m0 = 4'd15;
i_G2_m1 = 4'd14;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd09;
end
12: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd05;
i_G1_m0 = 4'd01;
i_G1_m1 = 4'd15;
i_G2_m0 = 4'd14;
i_G2_m1 = 4'd13;
i_G3_m0 = 4'd04;
i_G3_m1 = 4'd10;
end
13: begin
i_G0_m0 = 4'd00;
i_G0_m1 = 4'd07;
i_G1_m0 = 4'd06;
i_G1_m1 = 4'd03;
i_G2_m0 = 4'd09;
i_G2_m1 = 4'd02;
i_G3_m0 = 4'd08;
i_G3_m1 = 4'd11;
end
14: begin
i_G0_m0 = 4'd13;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd07;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd12;
i_G2_m1 = 4'd01;
i_G3_m0 = 4'd03;
i_G3_m1 = 4'd09;
end
15: begin
i_G0_m0 = 4'd05;
i_G0_m1 = 4'd00;
i_G1_m0 = 4'd15;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd08;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd02;
i_G3_m1 = 4'd10;
end
16: begin
i_G0_m0 = 4'd06;
i_G0_m1 = 4'd15;
i_G1_m0 = 4'd14;
i_G1_m1 = 4'd09;
i_G2_m0 = 4'd11;
i_G2_m1 = 4'd03;
i_G3_m0 = 4'd00;
i_G3_m1 = 4'd08;
end
17: begin
i_G0_m0 = 4'd12;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd13;
i_G1_m1 = 4'd07;
i_G2_m0 = 4'd01;
i_G2_m1 = 4'd04;
i_G3_m0 = 4'd10;
i_G3_m1 = 4'd05;
end
18: begin
i_G0_m0 = 4'd10;
i_G0_m1 = 4'd02;
i_G1_m0 = 4'd08;
i_G1_m1 = 4'd04;
i_G2_m0 = 4'd07;
i_G2_m1 = 4'd06;
i_G3_m0 = 4'd01;
i_G3_m1 = 4'd05;
end
19: begin
i_G0_m0 = 4'd15;
i_G0_m1 = 4'd11;
i_G1_m0 = 4'd09;
i_G1_m1 = 4'd14;
i_G2_m0 = 4'd03;
i_G2_m1 = 4'd12;
i_G3_m0 = 4'd13;
i_G3_m1 = 4'd00;
end
default: begin end
endcase
end
endmodule | 16 |
5,387 | data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v | 113,904,439 | tb_blake2s_core.v | v | 530 | 167 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:98: Unsupported: Ignoring delay on this delayed statement.\n #CLK_HALF_PERIOD tb_clk = !tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:212: Unsupported: Ignoring delay on this delayed statement.\n #(num_cycles * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:226: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:285: Unsupported: Ignoring delay on this delayed statement.\n #(2 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:287: Unsupported: Ignoring delay on this delayed statement.\n #(2 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:305: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:312: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:317: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:322: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:350: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:353: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:363: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:367: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:381: Unsupported: Ignoring delay on this delayed statement.\n #(2 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:397: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:400: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:410: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:415: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:421: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:425: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:439: Unsupported: Ignoring delay on this delayed statement.\n #(2 * CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:458: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:465: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:471: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:476: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/113904439/src/tb/tb_blake2s_core.v:522: Unsupported or unknown PLI call: $finish_and_return\n $finish_and_return(error_ctr);\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 25 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,130 | module | module tb_blake2s_core();
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg display_cycle_ctr;
reg display_dut_state;
reg tb_clk;
reg tb_reset_n;
reg tb_init;
reg tb_update;
reg tb_finish;
reg [511 : 0] tb_block;
reg [6 : 0] tb_blocklen;
wire [255 : 0] tb_digest;
wire tb_ready;
blake2s_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.init(tb_init),
.update(tb_update),
.finish(tb_finish),
.block(tb_block),
.blocklen(tb_blocklen),
.digest(tb_digest),
.ready(tb_ready)
);
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_dut_state)
dump_dut_state();
end
task dump_dut_state;
begin
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("DUT internal state at cycle: %08d", cycle_ctr);
$display("-------------------------------------");
$display("init: 0x%01x, update: 0x%01x, finish: 0x%01x", dut.init, dut.update, dut.finish);
$display("block M: 0x%064x", dut.block[511 : 256]);
$display("block L: 0x%064x", dut.block[255 : 000]);
$display("blocklen: 0x%02x", dut.blocklen);
$display("digest: 0x%064x", dut.digest);
$display("ready: 0x%01x", dut.ready);
$display("");
$display("blake2s_ctrl_reg: 0x%02x, blake2s_ctrl_new: 0x%02x, blake2s_ctrl_we: 0x%01x",
dut.blake2s_ctrl_reg, dut.blake2s_ctrl_new, dut.blake2s_ctrl_we);
$display("");
$display("h0: 0x%08x, h1: 0x%08x, h2: 0x%08x, h3: 0x%08x",
dut.h_reg[0], dut.h_reg[1], dut.h_reg[2], dut.h_reg[3]);
$display("h4: 0x%08x, h5: 0x%08x, h6: 0x%08x, h7: 0x%08x",
dut.h_reg[4], dut.h_reg[5], dut.h_reg[6], dut.h_reg[7]);
$display("");
$display("v0: 0x%08x, v1: 0x%08x, v2: 0x%08x, v3: 0x%08x",
dut.v_reg[0], dut.v_reg[1], dut.v_reg[2], dut.v_reg[3]);
$display("v4: 0x%08x, v5: 0x%08x, v6: 0x%08x, v7: 0x%08x",
dut.v_reg[4], dut.v_reg[5], dut.v_reg[6], dut.v_reg[7]);
$display("v8: 0x%08x, v9: 0x%08x, v10: 0x%08x, v11: 0x%08x",
dut.v_reg[8], dut.v_reg[9], dut.v_reg[10], dut.v_reg[11]);
$display("v12: 0x%08x, v13: 0x%08x, v14: 0x%08x, v15: 0x%08x",
dut.v_reg[12], dut.v_reg[13], dut.v_reg[14], dut.v_reg[15]);
$display("init_v: 0x%1x, update_v: 0x%1x, v_we: 0x%1x", dut.init_v, dut.update_v, dut.v_we);
$display("");
$display("t0_reg: 0x%08x, t0_new: 0x%08x", dut.t0_reg, dut.t0_new);
$display("t1_reg: 0x%08x, t1_new: 0x%08x", dut.t1_reg, dut.t1_new);
$display("t_ctr_rst: 0x%1x, t_ctr_inc: 0x%1x", dut.t_ctr_rst, dut.t_ctr_inc);
$display("last_reg: 0x%1x, last_new: 0x%1x, last_we: 0x%1x",
dut.last_reg, dut.last_new, dut.last_we);
$display("");
$display("v0_new: 0x%08x, v1_new: 0x%08x, v2_new: 0x%08x, v3_new: 0x%08x",
dut.v_new[0], dut.v_new[1], dut.v_new[2], dut.v_new[3]);
$display("v4_new: 0x%08x, v5_new: 0x%08x, v6_new: 0x%08x, v7_new: 0x%08x",
dut.v_new[4], dut.v_new[5], dut.v_new[6], dut.v_new[7]);
$display("v8_new: 0x%08x, v9_new: 0x%08x, v10_new: 0x%08x, v11_new: 0x%08x",
dut.v_new[8], dut.v_new[9], dut.v_new[10], dut.v_new[11]);
$display("v12_new: 0x%08x, v13_new: 0x%08x, v14_new: 0x%08x, v15_new: 0x%08x",
dut.v_new[12], dut.v_new[13], dut.v_new[14], dut.v_new[15]);
$display("");
$display("G_mode: 0x%1x, ", dut.G_mode);
$display("G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
dut.G0_m0, dut.G0_m1, dut.G1_m0, dut.G1_m1);
$display("G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
dut.G2_m0, dut.G2_m1, dut.G3_m0, dut.G3_m1);
$display("round_ctr_reg: 0x%02x, round_ctr_new: 0x%02x", dut.round_ctr_reg, dut.round_ctr_reg);
$display("round_ctr_rst: 0x%1x, round_ctr_inc: 0x%1x, round_ctr_we: 0x%1x",
dut.round_ctr_rst, dut.round_ctr_inc, dut.round_ctr_we);
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("");
$display("");
end
endtask
task inc_tc_ctr;
tc_ctr = tc_ctr + 1;
endtask
task inc_error_ctr;
error_ctr = error_ctr + 1;
endtask
task pause_finish(input [31 : 0] num_cycles);
begin
$display("--- Pausing for %04d cycles and then finishing hard.", num_cycles);
#(num_cycles * CLK_PERIOD);
$finish;
end
endtask
task wait_ready;
begin : wready
while (!tb_ready)
#(CLK_PERIOD);
end
endtask
task display_test_result;
begin
$display("--- %02d test cases executed ---", tc_ctr);
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully ---", tc_ctr);
end
else
begin
$display("--- %02d test cases did not complete successfully ---", error_ctr);
end
end
endtask
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
display_cycle_ctr = 1;
display_dut_state = 0;
tb_clk = 1'h0;
tb_reset_n = 1'h1;
tb_init = 1'h0;
tb_update = 1'h0;
tb_finish = 1'h0;
tb_block = 512'h0;
tb_blocklen = 7'h0;
end
endtask
task reset_dut;
begin
$display("--- TB: Resetting dut.");
tb_reset_n = 1'h0;
#(2 * CLK_PERIOD);
tb_reset_n = 1'h1;
#(2 * CLK_PERIOD);
$display("--- TB: Reset done.");
end
endtask
task test_empty_message;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_empty_message: Started.");
$display("--- test_empty_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_empty_message: Init should be completed.");
#(CLK_PERIOD);
$display("--- test_empty_message: Asserting finish.");
tb_blocklen = 7'h00;
tb_block = 512'h0;
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_empty_message: Finish should be completed.");
#(CLK_PERIOD);
$display("--- test_empty_message: Checking generated digest.");
if (tb_digest == 256'h69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9) begin
$display("--- test_empty_message: Correct digest generated.");
$display("--- test_empty_message: Got: 0x%064x", tb_digest);
end else begin
$display("--- test_empty_message: Error. Incorrect digest generated.");
$display("--- test_empty_message: Expected: 0x69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9");
$display("--- test_empty_message: Got: 0x%064x", tb_digest);
error_ctr = error_ctr + 1;
end
$display("--- test_empty_message: Completed.\n");
end
endtask
task test_one_block_message;
begin: test_one_block_message
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_one_block_message: Started.");
#(CLK_PERIOD);
$display("--- test_one_block_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_one_block_message: Init completed.");
tb_block = 512'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f_20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f;
tb_blocklen = 7'h40;
$display("--- test_one_block_message: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_one_block_message: Finish completed.");
#(CLK_PERIOD);
if (dut.digest == 256'h56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e) begin
$display("--- test_one_block_message: Correct digest generated.");
$display("--- test_one_block_message: Got: 0x%064x", dut.digest);
end else begin
$display("--- test_one_block_message: ERROR incorrect digest generated.");
$display("--- test_one_block_message: Expected: 0x56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e");
$display("--- test_one_block_message: Got: 0x%064x", dut.digest);
error_ctr = error_ctr + 1;
end
$display("--- test_one_block_message: Completed.\n");
#(2 * CLK_PERIOD);
end
endtask
task test_one_block_one_byte_message;
begin: test_one_block_one_byte_message
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_one_block_one_byte_message: Started.");
#(CLK_PERIOD);
$display("--- test_one_block_one_byte_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Init completed.");
tb_block = 512'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f_20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f;
tb_blocklen = 7'h40;
$display("--- test_one_block_one_byte_message: Asserting update.");
tb_update = 1'h1;
#(CLK_PERIOD);
tb_update = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Update completed.");
#(CLK_PERIOD);
tb_block = {8'h40, {63{8'h00}}};
tb_blocklen = 7'h01;
$display("--- test_one_block_one_byte_message: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Finish completed.");
#(CLK_PERIOD);
if (dut.digest == 256'h1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472) begin
$display("--- test_one_block_one_byte_message: Correct digest generated.");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", dut.digest);
end else begin
$display("--- test_one_block_one_byte_message: ERROR incorrect digest generated.");
$display("--- test_one_block_one_byte_message: Expected: 0x1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", dut.digest);
error_ctr = error_ctr + 1;
end
$display("--- test_one_block_one_byte_message: Completed.\n");
#(2 * CLK_PERIOD);
end
endtask
task test_rfc_7693;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_rfc_7693: Started.");
$display("--- test_rfc_7693: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_rfc_7693: Init should be completed.");
#(CLK_PERIOD);
$display("--- test_rfc_7693: Setting message and message length.");
tb_blocklen = 7'h03;
tb_block = {32'h61626300, {15{32'h0}}};
$display("--- test_rfc_7693: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_rfc_7693: Finish should be completed.");
#(CLK_PERIOD);
$display("--- test_rfc_7693: Checking generated digest.");
if (tb_digest == 256'h508c5e8c327c14e2_e1a72ba34eeb452f_37458b209ed63a29_4d999b4c86675982) begin
$display("--- test_rfc_7693: Correct digest generated.");
$display("--- test_rfc_7693: Got: 0x%064x", tb_digest);
end else begin
$display("--- test_rfc_7693: Error. Incorrect digest generated.");
$display("--- test_rfc_7693: Expected: 0x508c5e8c327c14e2e1a72ba34eeb452f37458b209ed63a294d999b4c86675982");
$display("--- test_rfc_7693: Got: 0x%064x", tb_digest);
error_ctr = error_ctr + 1;
end
$display("--- test_rfc_7693: Completed.\n");
end
endtask
initial
begin : testrunner
$display("");
$display("-------------------------------------------");
$display("--- Testbench for BLAKE2s core started ---");
$display("-------------------------------------------");
$display("");
init_sim();
reset_dut();
test_empty_message();
test_one_block_message();
test_one_block_one_byte_message();
test_rfc_7693();
display_test_result();
$display("");
$display("-------------------------------------------");
$display("--- testbench for BLAKE2s core completed ---");
$display("--------------------------------------------");
$display("");
$finish_and_return(error_ctr);
end
endmodule | module tb_blake2s_core(); |
parameter DEBUG = 0;
parameter VERBOSE = 0;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg display_cycle_ctr;
reg display_dut_state;
reg tb_clk;
reg tb_reset_n;
reg tb_init;
reg tb_update;
reg tb_finish;
reg [511 : 0] tb_block;
reg [6 : 0] tb_blocklen;
wire [255 : 0] tb_digest;
wire tb_ready;
blake2s_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.init(tb_init),
.update(tb_update),
.finish(tb_finish),
.block(tb_block),
.blocklen(tb_blocklen),
.digest(tb_digest),
.ready(tb_ready)
);
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_dut_state)
dump_dut_state();
end
task dump_dut_state;
begin
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("DUT internal state at cycle: %08d", cycle_ctr);
$display("-------------------------------------");
$display("init: 0x%01x, update: 0x%01x, finish: 0x%01x", dut.init, dut.update, dut.finish);
$display("block M: 0x%064x", dut.block[511 : 256]);
$display("block L: 0x%064x", dut.block[255 : 000]);
$display("blocklen: 0x%02x", dut.blocklen);
$display("digest: 0x%064x", dut.digest);
$display("ready: 0x%01x", dut.ready);
$display("");
$display("blake2s_ctrl_reg: 0x%02x, blake2s_ctrl_new: 0x%02x, blake2s_ctrl_we: 0x%01x",
dut.blake2s_ctrl_reg, dut.blake2s_ctrl_new, dut.blake2s_ctrl_we);
$display("");
$display("h0: 0x%08x, h1: 0x%08x, h2: 0x%08x, h3: 0x%08x",
dut.h_reg[0], dut.h_reg[1], dut.h_reg[2], dut.h_reg[3]);
$display("h4: 0x%08x, h5: 0x%08x, h6: 0x%08x, h7: 0x%08x",
dut.h_reg[4], dut.h_reg[5], dut.h_reg[6], dut.h_reg[7]);
$display("");
$display("v0: 0x%08x, v1: 0x%08x, v2: 0x%08x, v3: 0x%08x",
dut.v_reg[0], dut.v_reg[1], dut.v_reg[2], dut.v_reg[3]);
$display("v4: 0x%08x, v5: 0x%08x, v6: 0x%08x, v7: 0x%08x",
dut.v_reg[4], dut.v_reg[5], dut.v_reg[6], dut.v_reg[7]);
$display("v8: 0x%08x, v9: 0x%08x, v10: 0x%08x, v11: 0x%08x",
dut.v_reg[8], dut.v_reg[9], dut.v_reg[10], dut.v_reg[11]);
$display("v12: 0x%08x, v13: 0x%08x, v14: 0x%08x, v15: 0x%08x",
dut.v_reg[12], dut.v_reg[13], dut.v_reg[14], dut.v_reg[15]);
$display("init_v: 0x%1x, update_v: 0x%1x, v_we: 0x%1x", dut.init_v, dut.update_v, dut.v_we);
$display("");
$display("t0_reg: 0x%08x, t0_new: 0x%08x", dut.t0_reg, dut.t0_new);
$display("t1_reg: 0x%08x, t1_new: 0x%08x", dut.t1_reg, dut.t1_new);
$display("t_ctr_rst: 0x%1x, t_ctr_inc: 0x%1x", dut.t_ctr_rst, dut.t_ctr_inc);
$display("last_reg: 0x%1x, last_new: 0x%1x, last_we: 0x%1x",
dut.last_reg, dut.last_new, dut.last_we);
$display("");
$display("v0_new: 0x%08x, v1_new: 0x%08x, v2_new: 0x%08x, v3_new: 0x%08x",
dut.v_new[0], dut.v_new[1], dut.v_new[2], dut.v_new[3]);
$display("v4_new: 0x%08x, v5_new: 0x%08x, v6_new: 0x%08x, v7_new: 0x%08x",
dut.v_new[4], dut.v_new[5], dut.v_new[6], dut.v_new[7]);
$display("v8_new: 0x%08x, v9_new: 0x%08x, v10_new: 0x%08x, v11_new: 0x%08x",
dut.v_new[8], dut.v_new[9], dut.v_new[10], dut.v_new[11]);
$display("v12_new: 0x%08x, v13_new: 0x%08x, v14_new: 0x%08x, v15_new: 0x%08x",
dut.v_new[12], dut.v_new[13], dut.v_new[14], dut.v_new[15]);
$display("");
$display("G_mode: 0x%1x, ", dut.G_mode);
$display("G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
dut.G0_m0, dut.G0_m1, dut.G1_m0, dut.G1_m1);
$display("G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
dut.G2_m0, dut.G2_m1, dut.G3_m0, dut.G3_m1);
$display("round_ctr_reg: 0x%02x, round_ctr_new: 0x%02x", dut.round_ctr_reg, dut.round_ctr_reg);
$display("round_ctr_rst: 0x%1x, round_ctr_inc: 0x%1x, round_ctr_we: 0x%1x",
dut.round_ctr_rst, dut.round_ctr_inc, dut.round_ctr_we);
$display("-------------------------------------------------------------------------------------");
$display("-------------------------------------------------------------------------------------");
$display("");
$display("");
end
endtask
task inc_tc_ctr;
tc_ctr = tc_ctr + 1;
endtask
task inc_error_ctr;
error_ctr = error_ctr + 1;
endtask
task pause_finish(input [31 : 0] num_cycles);
begin
$display("--- Pausing for %04d cycles and then finishing hard.", num_cycles);
#(num_cycles * CLK_PERIOD);
$finish;
end
endtask
task wait_ready;
begin : wready
while (!tb_ready)
#(CLK_PERIOD);
end
endtask
task display_test_result;
begin
$display("--- %02d test cases executed ---", tc_ctr);
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully ---", tc_ctr);
end
else
begin
$display("--- %02d test cases did not complete successfully ---", error_ctr);
end
end
endtask
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
display_cycle_ctr = 1;
display_dut_state = 0;
tb_clk = 1'h0;
tb_reset_n = 1'h1;
tb_init = 1'h0;
tb_update = 1'h0;
tb_finish = 1'h0;
tb_block = 512'h0;
tb_blocklen = 7'h0;
end
endtask
task reset_dut;
begin
$display("--- TB: Resetting dut.");
tb_reset_n = 1'h0;
#(2 * CLK_PERIOD);
tb_reset_n = 1'h1;
#(2 * CLK_PERIOD);
$display("--- TB: Reset done.");
end
endtask
task test_empty_message;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_empty_message: Started.");
$display("--- test_empty_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_empty_message: Init should be completed.");
#(CLK_PERIOD);
$display("--- test_empty_message: Asserting finish.");
tb_blocklen = 7'h00;
tb_block = 512'h0;
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_empty_message: Finish should be completed.");
#(CLK_PERIOD);
$display("--- test_empty_message: Checking generated digest.");
if (tb_digest == 256'h69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9) begin
$display("--- test_empty_message: Correct digest generated.");
$display("--- test_empty_message: Got: 0x%064x", tb_digest);
end else begin
$display("--- test_empty_message: Error. Incorrect digest generated.");
$display("--- test_empty_message: Expected: 0x69217a3079908094e11121d042354a7c1f55b6482ca1a51e1b250dfd1ed0eef9");
$display("--- test_empty_message: Got: 0x%064x", tb_digest);
error_ctr = error_ctr + 1;
end
$display("--- test_empty_message: Completed.\n");
end
endtask
task test_one_block_message;
begin: test_one_block_message
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_one_block_message: Started.");
#(CLK_PERIOD);
$display("--- test_one_block_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_one_block_message: Init completed.");
tb_block = 512'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f_20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f;
tb_blocklen = 7'h40;
$display("--- test_one_block_message: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_one_block_message: Finish completed.");
#(CLK_PERIOD);
if (dut.digest == 256'h56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e) begin
$display("--- test_one_block_message: Correct digest generated.");
$display("--- test_one_block_message: Got: 0x%064x", dut.digest);
end else begin
$display("--- test_one_block_message: ERROR incorrect digest generated.");
$display("--- test_one_block_message: Expected: 0x56f34e8b96557e90c1f24b52d0c89d51086acf1b00f634cf1dde9233b8eaaa3e");
$display("--- test_one_block_message: Got: 0x%064x", dut.digest);
error_ctr = error_ctr + 1;
end
$display("--- test_one_block_message: Completed.\n");
#(2 * CLK_PERIOD);
end
endtask
task test_one_block_one_byte_message;
begin: test_one_block_one_byte_message
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_one_block_one_byte_message: Started.");
#(CLK_PERIOD);
$display("--- test_one_block_one_byte_message: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Init completed.");
tb_block = 512'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f_20212223_24252627_28292a2b_2c2d2e2f_30313233_34353637_38393a3b_3c3d3e3f;
tb_blocklen = 7'h40;
$display("--- test_one_block_one_byte_message: Asserting update.");
tb_update = 1'h1;
#(CLK_PERIOD);
tb_update = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Update completed.");
#(CLK_PERIOD);
tb_block = {8'h40, {63{8'h00}}};
tb_blocklen = 7'h01;
$display("--- test_one_block_one_byte_message: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_one_block_one_byte_message: Finish completed.");
#(CLK_PERIOD);
if (dut.digest == 256'h1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472) begin
$display("--- test_one_block_one_byte_message: Correct digest generated.");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", dut.digest);
end else begin
$display("--- test_one_block_one_byte_message: ERROR incorrect digest generated.");
$display("--- test_one_block_one_byte_message: Expected: 0x1b53ee94aaf34e4b159d48de352c7f0661d0a40edff95a0b1639b4090e974472");
$display("--- test_one_block_one_byte_message: Got: 0x%064x", dut.digest);
error_ctr = error_ctr + 1;
end
$display("--- test_one_block_one_byte_message: Completed.\n");
#(2 * CLK_PERIOD);
end
endtask
task test_rfc_7693;
begin : test_rfc_7693
tc_ctr = tc_ctr + 1;
$display("");
$display("--- test_rfc_7693: Started.");
$display("--- test_rfc_7693: Asserting init.");
tb_init = 1'h1;
#(CLK_PERIOD);
tb_init = 1'h0;
wait_ready();
$display("--- test_rfc_7693: Init should be completed.");
#(CLK_PERIOD);
$display("--- test_rfc_7693: Setting message and message length.");
tb_blocklen = 7'h03;
tb_block = {32'h61626300, {15{32'h0}}};
$display("--- test_rfc_7693: Asserting finish.");
tb_finish = 1'h1;
#(CLK_PERIOD);
tb_finish = 1'h0;
wait_ready();
$display("--- test_rfc_7693: Finish should be completed.");
#(CLK_PERIOD);
$display("--- test_rfc_7693: Checking generated digest.");
if (tb_digest == 256'h508c5e8c327c14e2_e1a72ba34eeb452f_37458b209ed63a29_4d999b4c86675982) begin
$display("--- test_rfc_7693: Correct digest generated.");
$display("--- test_rfc_7693: Got: 0x%064x", tb_digest);
end else begin
$display("--- test_rfc_7693: Error. Incorrect digest generated.");
$display("--- test_rfc_7693: Expected: 0x508c5e8c327c14e2e1a72ba34eeb452f37458b209ed63a294d999b4c86675982");
$display("--- test_rfc_7693: Got: 0x%064x", tb_digest);
error_ctr = error_ctr + 1;
end
$display("--- test_rfc_7693: Completed.\n");
end
endtask
initial
begin : testrunner
$display("");
$display("-------------------------------------------");
$display("--- Testbench for BLAKE2s core started ---");
$display("-------------------------------------------");
$display("");
init_sim();
reset_dut();
test_empty_message();
test_one_block_message();
test_one_block_one_byte_message();
test_rfc_7693();
display_test_result();
$display("");
$display("-------------------------------------------");
$display("--- testbench for BLAKE2s core completed ---");
$display("--------------------------------------------");
$display("");
$finish_and_return(error_ctr);
end
endmodule | 16 |
5,388 | data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v | 113,904,439 | tb_blake2s_m_select.v | v | 331 | 89 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | line:204: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:103: Unsupported: Ignoring delay on this delayed statement.\n #CLK_HALF_PERIOD tb_clk = !tb_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:206: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:209: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:240: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:272: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:279: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:285: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:288: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:294: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_PERIOD);\n ^\n%Error: data/full_repos/permissive/113904439/src/tb/tb_blake2s_m_select.v:323: Unsupported or unknown PLI call: $finish_and_return\n $finish_and_return(error_ctr);\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,132 | module | module tb_blake2s_m_select();
parameter VERBOSE = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_load;
reg [511 : 0] tb_m;
reg [3 : 0] tb_round;
reg tb_mode;
wire [31 : 0] tb_G0_m0;
wire [31 : 0] tb_G0_m1;
wire [31 : 0] tb_G1_m0;
wire [31 : 0] tb_G1_m1;
wire [31 : 0] tb_G2_m0;
wire [31 : 0] tb_G2_m1;
wire [31 : 0] tb_G3_m0;
wire [31 : 0] tb_G3_m1;
reg display_cycle_ctr;
blake2s_m_select dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.load(tb_load),
.m(tb_m),
.round(tb_round),
.mode(tb_mode),
.G0_m0(tb_G0_m0),
.G0_m1(tb_G0_m1),
.G1_m0(tb_G1_m0),
.G1_m1(tb_G1_m1),
.G2_m0(tb_G2_m0),
.G2_m1(tb_G2_m1),
.G3_m0(tb_G3_m0),
.G3_m1(tb_G3_m1)
);
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end
task dump_dut_state;
begin
if (VERBOSE)
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("contents of m:");
$display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
dut.m_mem[0], dut.m_mem[1], dut.m_mem[2], dut.m_mem[3],
dut.m_mem[4], dut.m_mem[5], dut.m_mem[6], dut.m_mem[7]);
$display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
dut.m_mem[8], dut.m_mem[9], dut.m_mem[10], dut.m_mem[11],
dut.m_mem[12], dut.m_mem[13], dut.m_mem[14], dut.m_mem[15]);
$display("");
end
end
endtask
task display_test_result;
begin
$display("--- %02d test cases executed ---", tc_ctr);
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully ---", tc_ctr);
end
else
begin
$display("--- %02d test cases did not complete successfully. ---", error_ctr);
end
end
endtask
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
display_cycle_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_load = 0;
tb_m = 512'h0;
tb_round = 0;
tb_mode = 0;
end
endtask
task test_reset;
begin : tc_reset
tc_ctr = tc_ctr + 1;
$display("--- Testing that reset clears the m memory");
$display("--- Memory before reset:");
dump_dut_state();
tb_reset_n = 0;
#(CLK_PERIOD);
$display("--- Pulling reset");
tb_reset_n = 1;
#(CLK_PERIOD);
$display("--- Memory after reset:");
dump_dut_state();
$display("");
end
endtask
task test_case1;
begin : tc1
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC1: Test case 1 started. Loading the m with a known block");
$display("--- TC1: Before loading:");
dump_dut_state();
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC1: After loading:");
dump_dut_state();
$display("");
end
endtask
task test_case2;
begin : tc2
integer i;
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC2: Test case 2 started. Loading the m with a known block");
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC2: Looping over all rounds and modes.");
for (i = 0 ; i < 16 ; i = i + 1) begin
tb_round = i[3 : 0];
tb_mode = 0;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
tb_mode = 1;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
end
$display("--- TC2: Test case 2 completed");
tb_load = 1;
$display("");
end
endtask
initial
begin : testrunner
$display("--- Testbench for BLAKE2 m select module started ---");
$display("----------------------------------------------------");
$display("");
init_dut();
test_reset();
test_case1();
test_case2();
display_test_result();
$display("--- Testbench for BLAKE2 m select module completed ---");
$display("------------------------------------------------------");
$finish_and_return(error_ctr);
end
endmodule | module tb_blake2s_m_select(); |
parameter VERBOSE = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_load;
reg [511 : 0] tb_m;
reg [3 : 0] tb_round;
reg tb_mode;
wire [31 : 0] tb_G0_m0;
wire [31 : 0] tb_G0_m1;
wire [31 : 0] tb_G1_m0;
wire [31 : 0] tb_G1_m1;
wire [31 : 0] tb_G2_m0;
wire [31 : 0] tb_G2_m1;
wire [31 : 0] tb_G3_m0;
wire [31 : 0] tb_G3_m1;
reg display_cycle_ctr;
blake2s_m_select dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.load(tb_load),
.m(tb_m),
.round(tb_round),
.mode(tb_mode),
.G0_m0(tb_G0_m0),
.G0_m1(tb_G0_m1),
.G1_m0(tb_G1_m0),
.G1_m1(tb_G1_m1),
.G2_m0(tb_G2_m0),
.G2_m1(tb_G2_m1),
.G3_m0(tb_G3_m0),
.G3_m1(tb_G3_m1)
);
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end
task dump_dut_state;
begin
if (VERBOSE)
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("contents of m:");
$display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
dut.m_mem[0], dut.m_mem[1], dut.m_mem[2], dut.m_mem[3],
dut.m_mem[4], dut.m_mem[5], dut.m_mem[6], dut.m_mem[7]);
$display("0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x ",
dut.m_mem[8], dut.m_mem[9], dut.m_mem[10], dut.m_mem[11],
dut.m_mem[12], dut.m_mem[13], dut.m_mem[14], dut.m_mem[15]);
$display("");
end
end
endtask
task display_test_result;
begin
$display("--- %02d test cases executed ---", tc_ctr);
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully ---", tc_ctr);
end
else
begin
$display("--- %02d test cases did not complete successfully. ---", error_ctr);
end
end
endtask
task init_dut;
begin
cycle_ctr = 0;
error_ctr = 0;
display_cycle_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_load = 0;
tb_m = 512'h0;
tb_round = 0;
tb_mode = 0;
end
endtask
task test_reset;
begin : tc_reset
tc_ctr = tc_ctr + 1;
$display("--- Testing that reset clears the m memory");
$display("--- Memory before reset:");
dump_dut_state();
tb_reset_n = 0;
#(CLK_PERIOD);
$display("--- Pulling reset");
tb_reset_n = 1;
#(CLK_PERIOD);
$display("--- Memory after reset:");
dump_dut_state();
$display("");
end
endtask
task test_case1;
begin : tc1
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC1: Test case 1 started. Loading the m with a known block");
$display("--- TC1: Before loading:");
dump_dut_state();
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC1: After loading:");
dump_dut_state();
$display("");
end
endtask
task test_case2;
begin : tc2
integer i;
tc_ctr = tc_ctr + 1;
tb_round = 0;
tb_mode = 0;
tb_load = 0;
tb_m = {32'h00010203, 32'h04050607, 32'h08090a0b, 32'h0c0d0e0f,
32'h10111213, 32'h14151617, 32'h18191a1b, 32'h1c1d1e1f,
32'h20212223, 32'h24252627, 32'h28292a2b, 32'h2c2d2e2f,
32'h30313233, 32'h34353637, 32'h38393a3b, 32'h3c3d3e3f};
$display("--- TC2: Test case 2 started. Loading the m with a known block");
tb_load = 1;
#(CLK_PERIOD);
tb_load = 0;
$display("--- TC2: Looping over all rounds and modes.");
for (i = 0 ; i < 16 ; i = i + 1) begin
tb_round = i[3 : 0];
tb_mode = 0;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
tb_mode = 1;
#(CLK_PERIOD);
$display("--- TC2: round %2d, mode: %1x:", tb_round, tb_mode);
$display("--- G0_m0: 0x%08x, G0_m1: 0x%08x, G1_m0: 0x%08x, G1_m1: 0x%08x",
tb_G0_m0, tb_G0_m1, tb_G1_m0, tb_G1_m1);
$display("--- G2_m0: 0x%08x, G2_m1: 0x%08x, G3_m0: 0x%08x, G3_m1: 0x%08x",
tb_G2_m0, tb_G2_m1, tb_G3_m0, tb_G3_m1);
#(CLK_PERIOD);
end
$display("--- TC2: Test case 2 completed");
tb_load = 1;
$display("");
end
endtask
initial
begin : testrunner
$display("--- Testbench for BLAKE2 m select module started ---");
$display("----------------------------------------------------");
$display("");
init_dut();
test_reset();
test_case1();
test_case2();
display_test_result();
$display("--- Testbench for BLAKE2 m select module completed ---");
$display("------------------------------------------------------");
$finish_and_return(error_ctr);
end
endmodule | 16 |
5,389 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v | 113,962,532 | cache.v | v | 625 | 90 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] inst_addr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:11: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] data_addr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:12: Define or directive not defined: \'`RegDataBytes\'\n input wire[`RegDataBytes-1:0] write_data_mask,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:13: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] write_data_value,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:15: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] inst_value,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:16: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] read_data_value,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:83: Define or directive not defined: \'`MemRead\'\n if(data_optype == `MemRead) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(data_optype == `MemRead) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:89: syntax error, unexpected begin, expecting assert or assume or cover or restrict\n CS_DATA_VALUE: begin\n ^~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:90: Define or directive not defined: \'`MemWrite\'\n if(data_optype == `MemWrite) begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:110: Define or directive not defined: \'`No\'\n busy <= `No;\n ^~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:117: Define or directive not defined: \'`Yes\'\n busy <= `Yes;\n ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:119: Define or directive not defined: \'`No\'\n busy <= `No;\n ^~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:135: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:135: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n uart_send_flag <= `SendDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:136: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:136: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n uart_recv_flag <= `RecvDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:144: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n uart_send_flag <= `SendDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:145: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:145: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n uart_recv_flag <= `RecvDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:161: Define or directive not defined: \'`SendEnable\'\n uart_send_flag <= `SendEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:161: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n uart_send_flag <= `SendEnable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:190: Define or directive not defined: \'`MemRead\'\n if (data_optype == `MemRead) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:190: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (data_optype == `MemRead) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:192: Define or directive not defined: \'`RecvEnable\'\n uart_recv_flag <= `RecvEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:216: syntax error, unexpected else, expecting endcase\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:220: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:222: Define or directive not defined: \'`SendEnable\'\n uart_send_flag <= `SendEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:228: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= write_data_value[7:0];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:230: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= write_data_value[15:8];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:232: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= write_data_value[23:16];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:234: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= write_data_value[31:24];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:236: syntax error, unexpected <=, expecting IDENTIFIER\n next_disp <= 0;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:238: syntax error, unexpected <=, expecting IDENTIFIER\n next_status <= CS_INST_HEAD;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:240: syntax error, unexpected <=, expecting IDENTIFIER\n next_status <= CS_OUTPUT;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:244: syntax error, unexpected <=, expecting IDENTIFIER\n next_status <= cur_status;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:255: Define or directive not defined: \'`SendEnable\'\n uart_send_flag <= `SendEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:261: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= cur_head[7:0];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:263: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= cur_head[15:8];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:265: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= cur_head[23:16];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:267: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= cur_head[31:24];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:269: syntax error, unexpected <=, expecting IDENTIFIER\n uart_send_data <= cur_head[39:32];\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:271: syntax error, unexpected <=, expecting IDENTIFIER\n next_status <= CS_INST_VALUE;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:275: syntax error, unexpected <=, expecting IDENTIFIER\n next_status <= cur_status;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:285: Define or directive not defined: \'`RecvEnable\'\n uart_recv_flag <= `RecvEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:291: syntax error, unexpected \'[\', expecting IDENTIFIER\n inst_value[7:0] <= uart_recv_data;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:293: syntax error, unexpected \'[\', expecting IDENTIFIER\n inst_value[15:8] <= uart_recv_data;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cache.v:295: syntax error, unexpected \'[\', expecting IDENTIFIER\n inst_value[23:16] <= uart_recv_data;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,149 | module | module cache(
input wire clk,
input wire rst,
input wire inst_ce, data_ce,
input wire data_optype,
input wire[`MemAddrWidth-1:0] inst_addr,
input wire[`MemAddrWidth-1:0] data_addr,
input wire[`RegDataBytes-1:0] write_data_mask,
input wire[`RegDataWidth-1:0] write_data_value,
output reg[`RegDataWidth-1:0] inst_value,
output reg[`RegDataWidth-1:0] read_data_value,
output reg busy,
output wire Tx,
input wire Rx
);
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0(
.CLK(clk),
.RST(rst),
.send_flag(uart_send_flag),
.send_data(uart_send_data),
.recv_flag(uart_recv_flag),
.recv_data(uart_recv_data),
.sendable(uart_sendable),
.receivable(uart_receivable),
.Tx(Tx),
.Rx(Rx) );
reg[39:0] cur_head;
reg[31:0] cur_data;
localparam CS_READY = 4'd0;
localparam CS_DATA_HEAD = 4'd1;
localparam CS_DATA_VALUE = 4'd2;
localparam CS_INST_HEAD = 4'd3;
localparam CS_INST_VALUE = 4'd4;
localparam CS_OUTPUT = 4'd5;
reg[3:0] cur_status;
reg[2:0] cur_disp;
reg[2:0] next_disp;
reg[3:0] next_status;
localparam READ_BIT = 1'b0;
localparam WRITE_BIT = 1'b1;
always @ (*) begin
if (rst) begin
cur_head <= 0;
cur_data <= 0;
end else begin
cur_head <= 0;
cur_data <= 0;
case (cur_status)
CS_READY: begin
cur_head <= 0;
cur_data <= 0;
end
CS_DATA_HEAD: begin
if(data_optype == `MemRead) begin
cur_head <= {{4{READ_BIT}}, {4{1'b0}}, data_addr};
end else begin
cur_head <= {{4{WRITE_BIT}}, write_data_mask, data_addr};
end
end
CS_DATA_VALUE: begin
if(data_optype == `MemWrite) begin
cur_data <= write_data_value;
end
end
CS_INST_HEAD: begin
cur_head <= {{4{READ_BIT}}, {4{1'b0}}, inst_addr};
end
endcase
end
end
always @ (*) begin
if(rst) begin
busy <= `No;
end else begin
if( cur_status == CS_INST_HEAD
|| cur_status == CS_INST_VALUE
|| cur_status == CS_DATA_HEAD
|| cur_status == CS_DATA_VALUE
|| (cur_status == CS_READY && (inst_ce || data_ce))) begin
busy <= `Yes;
end else begin
busy <= `No;
end
end
end
integer index;
localparam HeadFullDisp = 3'b100;
localparam DataFullDisp = 3'b011;
always @ (*) begin
if (rst) begin
next_status <= CS_READY;
next_disp <= 0;
uart_send_flag <= `SendDisable;
uart_recv_flag <= `RecvDisable;
uart_send_data <= 0;
inst_value <= 0;
read_data_value <= 0;
end else begin
next_status <= cur_status;
next_disp <= 0;
uart_send_data <= 0;
uart_send_flag <= `SendDisable;
uart_recv_flag <= `RecvDisable;
case (cur_status)
CS_READY: begin
if (data_ce) begin
next_status <= CS_DATA_HEAD;
next_disp <= 0;
end else if (inst_ce) begin
next_status <= CS_INST_HEAD;
next_disp <= 0;
end else begin
next_status <= CS_READY;
next_disp <= 0;
end
end
CS_DATA_HEAD: begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= cur_head[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= cur_head[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= cur_head[23:16];
else if(cur_disp == 3'b011)
uart_send_data <= cur_head[31:24];
else
uart_send_data <= cur_head[39:32];
if(cur_disp == HeadFullDisp) begin
next_status <= CS_DATA_VALUE;
next_disp <= 0;
$display("[cache] send data head [%x]", cur_head);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_DATA_VALUE: begin
if (data_optype == `MemRead) begin
if (uart_receivable) begin
uart_recv_flag <= `RecvEnable;
if(cur_disp == 3'b000)
read_data_value[7:0] <= uart_recv_data;
else if(cur_disp == 3'b001)
read_data_value[15:8] <= uart_recv_data;
else if(cur_disp == 3'b010)
read_data_value[23:16] <= uart_recv_data;
else
read_data_value[31:24] <= uart_recv_data;
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
if(inst_ce)
next_status <= CS_INST_HEAD;
else
next_status <= CS_OUTPUT;
$display("[cache] recv data value [%x]", {uart_recv_data,read_data_value[23:0]});
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end else begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= write_data_value[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= write_data_value[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= write_data_value[23:16];
else
uart_send_data <= write_data_value[31:24];
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
if(inst_ce) begin
next_status <= CS_INST_HEAD;
end else begin
next_status <= CS_OUTPUT;
end
$display("[cache] send data value [%x]", write_data_value);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
end
CS_INST_HEAD: begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= cur_head[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= cur_head[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= cur_head[23:16];
else if(cur_disp == 3'b011)
uart_send_data <= cur_head[31:24];
else
uart_send_data <= cur_head[39:32];
if(cur_disp == HeadFullDisp) begin
next_status <= CS_INST_VALUE;
next_disp <= 0;
$display("[cache] send inst head [%x]", cur_head);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_INST_VALUE: begin
if (uart_receivable) begin
uart_recv_flag <= `RecvEnable;
if(cur_disp == 3'b000)
inst_value[7:0] <= uart_recv_data;
else if(cur_disp == 3'b001)
inst_value[15:8] <= uart_recv_data;
else if(cur_disp == 3'b010)
inst_value[23:16] <= uart_recv_data;
else
inst_value[31:24] <= uart_recv_data;
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
next_status <= CS_OUTPUT;
$display("[cache] recv inst value [%x]", {uart_recv_data,inst_value[23:0]});
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_OUTPUT: begin
$display("[cache] cur_status: CS_OUTPUT");
next_status <= CS_READY;
next_disp <= 0;
end
endcase
end
end
always @ (posedge clk) begin
if(rst) begin
cur_status <= CS_READY;
cur_disp <= 0;
end else begin
cur_status <= next_status;
cur_disp <= next_disp;
end
end
endmodule | module cache(
input wire clk,
input wire rst,
input wire inst_ce, data_ce,
input wire data_optype,
input wire[`MemAddrWidth-1:0] inst_addr,
input wire[`MemAddrWidth-1:0] data_addr,
input wire[`RegDataBytes-1:0] write_data_mask,
input wire[`RegDataWidth-1:0] write_data_value,
output reg[`RegDataWidth-1:0] inst_value,
output reg[`RegDataWidth-1:0] read_data_value,
output reg busy,
output wire Tx,
input wire Rx
); |
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0(
.CLK(clk),
.RST(rst),
.send_flag(uart_send_flag),
.send_data(uart_send_data),
.recv_flag(uart_recv_flag),
.recv_data(uart_recv_data),
.sendable(uart_sendable),
.receivable(uart_receivable),
.Tx(Tx),
.Rx(Rx) );
reg[39:0] cur_head;
reg[31:0] cur_data;
localparam CS_READY = 4'd0;
localparam CS_DATA_HEAD = 4'd1;
localparam CS_DATA_VALUE = 4'd2;
localparam CS_INST_HEAD = 4'd3;
localparam CS_INST_VALUE = 4'd4;
localparam CS_OUTPUT = 4'd5;
reg[3:0] cur_status;
reg[2:0] cur_disp;
reg[2:0] next_disp;
reg[3:0] next_status;
localparam READ_BIT = 1'b0;
localparam WRITE_BIT = 1'b1;
always @ (*) begin
if (rst) begin
cur_head <= 0;
cur_data <= 0;
end else begin
cur_head <= 0;
cur_data <= 0;
case (cur_status)
CS_READY: begin
cur_head <= 0;
cur_data <= 0;
end
CS_DATA_HEAD: begin
if(data_optype == `MemRead) begin
cur_head <= {{4{READ_BIT}}, {4{1'b0}}, data_addr};
end else begin
cur_head <= {{4{WRITE_BIT}}, write_data_mask, data_addr};
end
end
CS_DATA_VALUE: begin
if(data_optype == `MemWrite) begin
cur_data <= write_data_value;
end
end
CS_INST_HEAD: begin
cur_head <= {{4{READ_BIT}}, {4{1'b0}}, inst_addr};
end
endcase
end
end
always @ (*) begin
if(rst) begin
busy <= `No;
end else begin
if( cur_status == CS_INST_HEAD
|| cur_status == CS_INST_VALUE
|| cur_status == CS_DATA_HEAD
|| cur_status == CS_DATA_VALUE
|| (cur_status == CS_READY && (inst_ce || data_ce))) begin
busy <= `Yes;
end else begin
busy <= `No;
end
end
end
integer index;
localparam HeadFullDisp = 3'b100;
localparam DataFullDisp = 3'b011;
always @ (*) begin
if (rst) begin
next_status <= CS_READY;
next_disp <= 0;
uart_send_flag <= `SendDisable;
uart_recv_flag <= `RecvDisable;
uart_send_data <= 0;
inst_value <= 0;
read_data_value <= 0;
end else begin
next_status <= cur_status;
next_disp <= 0;
uart_send_data <= 0;
uart_send_flag <= `SendDisable;
uart_recv_flag <= `RecvDisable;
case (cur_status)
CS_READY: begin
if (data_ce) begin
next_status <= CS_DATA_HEAD;
next_disp <= 0;
end else if (inst_ce) begin
next_status <= CS_INST_HEAD;
next_disp <= 0;
end else begin
next_status <= CS_READY;
next_disp <= 0;
end
end
CS_DATA_HEAD: begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= cur_head[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= cur_head[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= cur_head[23:16];
else if(cur_disp == 3'b011)
uart_send_data <= cur_head[31:24];
else
uart_send_data <= cur_head[39:32];
if(cur_disp == HeadFullDisp) begin
next_status <= CS_DATA_VALUE;
next_disp <= 0;
$display("[cache] send data head [%x]", cur_head);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_DATA_VALUE: begin
if (data_optype == `MemRead) begin
if (uart_receivable) begin
uart_recv_flag <= `RecvEnable;
if(cur_disp == 3'b000)
read_data_value[7:0] <= uart_recv_data;
else if(cur_disp == 3'b001)
read_data_value[15:8] <= uart_recv_data;
else if(cur_disp == 3'b010)
read_data_value[23:16] <= uart_recv_data;
else
read_data_value[31:24] <= uart_recv_data;
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
if(inst_ce)
next_status <= CS_INST_HEAD;
else
next_status <= CS_OUTPUT;
$display("[cache] recv data value [%x]", {uart_recv_data,read_data_value[23:0]});
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end else begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= write_data_value[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= write_data_value[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= write_data_value[23:16];
else
uart_send_data <= write_data_value[31:24];
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
if(inst_ce) begin
next_status <= CS_INST_HEAD;
end else begin
next_status <= CS_OUTPUT;
end
$display("[cache] send data value [%x]", write_data_value);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
end
CS_INST_HEAD: begin
if (uart_sendable) begin
uart_send_flag <= `SendEnable;
if(cur_disp == 3'b000)
uart_send_data <= cur_head[7:0];
else if(cur_disp == 3'b001)
uart_send_data <= cur_head[15:8];
else if(cur_disp == 3'b010)
uart_send_data <= cur_head[23:16];
else if(cur_disp == 3'b011)
uart_send_data <= cur_head[31:24];
else
uart_send_data <= cur_head[39:32];
if(cur_disp == HeadFullDisp) begin
next_status <= CS_INST_VALUE;
next_disp <= 0;
$display("[cache] send inst head [%x]", cur_head);
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_INST_VALUE: begin
if (uart_receivable) begin
uart_recv_flag <= `RecvEnable;
if(cur_disp == 3'b000)
inst_value[7:0] <= uart_recv_data;
else if(cur_disp == 3'b001)
inst_value[15:8] <= uart_recv_data;
else if(cur_disp == 3'b010)
inst_value[23:16] <= uart_recv_data;
else
inst_value[31:24] <= uart_recv_data;
if(cur_disp == DataFullDisp) begin
next_disp <= 0;
next_status <= CS_OUTPUT;
$display("[cache] recv inst value [%x]", {uart_recv_data,inst_value[23:0]});
end else begin
next_status <= cur_status;
next_disp <= cur_disp + 1;
end
end else begin
next_status <= cur_status;
next_disp <= cur_disp;
end
end
CS_OUTPUT: begin
$display("[cache] cur_status: CS_OUTPUT");
next_status <= CS_READY;
next_disp <= 0;
end
endcase
end
end
always @ (posedge clk) begin
if(rst) begin
cur_status <= CS_READY;
cur_disp <= 0;
end else begin
cur_status <= next_status;
cur_disp <= next_disp;
end
end
endmodule | 0 |
5,390 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cpu.v | 113,962,532 | cpu.v | v | 70 | 85 | [] | [] | [] | null | line:270: before: "ragma" | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/cpu.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 6,150 | module | module cpu(
input wire EXclk,
input wire button,
output Tx,
input Rx
);
reg rst;
reg rst_delay;
wire clk;
clk_wiz_0 clk0(.clk_out1(clk), .reset(1'b0), .clk_in1(EXclk));
always @(posedge clk or posedge button) begin
if(button) begin
rst <= 1;
rst_delay <= 1;
end else begin
rst_delay <= 0;
rst <= rst_delay;
end
end
risc32i risc32i0(
.clk(clk),
.rst(rst),
.Tx(Tx),
.Rx(Rx)
);
endmodule | module cpu(
input wire EXclk,
input wire button,
output Tx,
input Rx
); |
reg rst;
reg rst_delay;
wire clk;
clk_wiz_0 clk0(.clk_out1(clk), .reset(1'b0), .clk_in1(EXclk));
always @(posedge clk or posedge button) begin
if(button) begin
rst <= 1;
rst_delay <= 1;
end else begin
rst_delay <= 0;
rst <= rst_delay;
end
end
risc32i risc32i0(
.clk(clk),
.rst(rst),
.Tx(Tx),
.Rx(Rx)
);
endmodule | 0 |
5,391 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ctrl.v | 113,962,532 | ctrl.v | v | 31 | 38 | [] | [] | [] | [(204, 230)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ctrl.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: Exiting due to 1 error(s)\n' | 6,151 | module | module ctrl(
input wire rst,
input wire id_req,
input wire mem_busy,
output reg[5:0] stall
);
always @ (*)
begin
if (rst) begin
stall <= 6'b000000;
end else begin
if (mem_busy) begin
stall <= 6'b111111;
end else if (id_req) begin
stall <= 6'b000011;
end else begin
stall <= 6'b000000;
end
end
end
endmodule | module ctrl(
input wire rst,
input wire id_req,
input wire mem_busy,
output reg[5:0] stall
); |
always @ (*)
begin
if (rst) begin
stall <= 6'b000000;
end else begin
if (mem_busy) begin
stall <= 6'b111111;
end else if (id_req) begin
stall <= 6'b000011;
end else begin
stall <= 6'b000000;
end
end
end
endmodule | 0 |
5,392 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v | 113,962,532 | ex.v | v | 144 | 75 | [] | [] | [] | [(204, 343)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:8: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] aluop_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:9: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] alusel_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:10: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] reg1_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:11: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] reg2_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:12: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] wd_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:14: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:15: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:22: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] wdata_o, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:23: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] wd_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:25: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] addr_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:30: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] logicout;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:31: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] arithout;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:32: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] shiftout;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:34: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] reg2_comp;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:35: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] sub_res;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:36: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] sum_res;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: Define or directive not defined: \'`EXE_SLT_OP\'\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:42: Define or directive not defined: \'`EXE_SGE_OP\'\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:52: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:53: Define or directive not defined: \'`ZeroWord\'\n addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:54: Define or directive not defined: \'`NoJump\'\n end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:54: Define or directive not defined: \'`MEM_NOP\'\n end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:57: Define or directive not defined: \'`ZeroWord\'\n addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:64: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:65: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:66: Define or directive not defined: \'`ZeroWord\'\n arithout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:67: Define or directive not defined: \'`ZeroWord\'\n shiftout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:69: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:70: Define or directive not defined: \'`ZeroWord\'\n arithout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:71: Define or directive not defined: \'`ZeroWord\'\n shiftout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:73: Define or directive not defined: \'`EXE_ADD_OP\'\n `EXE_ADD_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:73: syntax error, unexpected \':\', expecting endcase\n `EXE_ADD_OP: begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:76: Define or directive not defined: \'`EXE_SUB_OP\'\n `EXE_SUB_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:79: Define or directive not defined: \'`EXE_SLT_OP\'\n `EXE_SLT_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:82: Define or directive not defined: \'`EXE_SLTU_OP\'\n `EXE_SLTU_OP: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:85: Define or directive not defined: \'`EXE_XOR_OP\'\n `EXE_XOR_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:88: Define or directive not defined: \'`EXE_OR_OP\'\n `EXE_OR_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:91: Define or directive not defined: \'`EXE_AND_OP\'\n `EXE_AND_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:94: Define or directive not defined: \'`EXE_SLL_OP\'\n `EXE_SLL_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:97: Define or directive not defined: \'`EXE_SRL_OP\'\n `EXE_SRL_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:100: Define or directive not defined: \'`EXE_SRA_OP\'\n `EXE_SRA_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:104: Define or directive not defined: \'`EXE_SEQ_OP\'\n `EXE_SEQ_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:107: Define or directive not defined: \'`EXE_SNE_OP\'\n `EXE_SNE_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:110: Define or directive not defined: \'`EXE_SGE_OP\'\n `EXE_SGE_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:113: Define or directive not defined: \'`EXE_SGEU_OP\'\n `EXE_SGEU_OP: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:128: Define or directive not defined: \'`EXE_LOGIC_RES\'\n `EXE_LOGIC_RES: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/ex.v:128: syntax error, unexpected \':\', expecting endcase\n `EXE_LOGIC_RES: begin\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,153 | module | module ex(
input wire rst,
input wire[`AluOpWidth-1:0] aluop_i,
input wire[`AluSelWidth-1:0] alusel_i,
input wire[`RegDataWidth-1:0] reg1_i,
input wire[`RegDataWidth-1:0] reg2_i,
input wire[`RegAddrWidth-1:0] wd_i,
input wire wreg_i,
input wire[`RegDataWidth-1:0] addr_base,
input wire[`RegDataWidth-1:0] addr_off,
input wire[1:0] jump_type_i,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`RegDataWidth-1:0] wdata_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o,
output reg[`RegDataWidth-1:0] addr_o,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o
);
reg[`RegDataWidth-1:0] logicout;
reg[`RegDataWidth-1:0] arithout;
reg[`RegDataWidth-1:0] shiftout;
wire[`RegDataWidth-1:0] reg2_comp;
wire[`RegDataWidth-1:0] sub_res;
wire[`RegDataWidth-1:0] sum_res;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
assign sub_res = reg1_i + (~reg2_i) + 1;
assign reg1_eq_reg2 = (reg1_i == reg2_i);
assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?
( (reg1_i[31] && !reg2_i[31])
|| (reg1_i[31] && reg2_i[31] && sub_res[31])
|| (!reg1_i[31] && !reg2_i[31] && sub_res[31])
) : (reg1_i < reg2_i));
always @ (*)
begin
if (rst == `RstEnable) begin
addr_o <= `ZeroWord;
end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin
addr_o <= addr_base + addr_off;
end else begin
addr_o <= `ZeroWord;
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
logicout <= `ZeroWord;
arithout <= `ZeroWord;
shiftout <= `ZeroWord;
end else begin
logicout <= `ZeroWord;
arithout <= `ZeroWord;
shiftout <= `ZeroWord;
case (aluop_i)
`EXE_ADD_OP: begin
arithout <= reg1_i + reg2_i;
end
`EXE_SUB_OP: begin
arithout <= sub_res;
end
`EXE_SLT_OP: begin
arithout <= {31'b0, reg1_lt_reg2};
end
`EXE_SLTU_OP: begin
arithout <= {31'b0, reg1_lt_reg2};
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_SLL_OP: begin
shiftout <= reg1_i << reg2_i[4:0];
end
`EXE_SRL_OP: begin
shiftout <= reg1_i >> reg2_i[4:0];
end
`EXE_SRA_OP: begin
shiftout <= (reg1_i >> reg2_i[4:0])
| ({32{reg1_i[31]}} << (6'd32 - {1'b0, reg2_i[4:0]}));
end
`EXE_SEQ_OP: begin
arithout <= {31'b0, reg1_eq_reg2};
end
`EXE_SNE_OP: begin
arithout <= {31'b0, !reg1_eq_reg2};
end
`EXE_SGE_OP: begin
arithout <= {31'b0, !reg1_lt_reg2};
end
`EXE_SGEU_OP: begin
arithout <= {31'b0, !reg1_lt_reg2};
end
endcase
end
end
always @ (*)
begin
wd_o <= wd_i;
wreg_o <= wreg_i;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
case (alusel_i)
`EXE_LOGIC_RES: begin
wdata_o <= logicout;
end
`EXE_ARITH_RES: begin
wdata_o <= arithout;
end
`EXE_SHIFT_RES: begin
wdata_o <= shiftout;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | module ex(
input wire rst,
input wire[`AluOpWidth-1:0] aluop_i,
input wire[`AluSelWidth-1:0] alusel_i,
input wire[`RegDataWidth-1:0] reg1_i,
input wire[`RegDataWidth-1:0] reg2_i,
input wire[`RegAddrWidth-1:0] wd_i,
input wire wreg_i,
input wire[`RegDataWidth-1:0] addr_base,
input wire[`RegDataWidth-1:0] addr_off,
input wire[1:0] jump_type_i,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`RegDataWidth-1:0] wdata_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o,
output reg[`RegDataWidth-1:0] addr_o,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o
); |
reg[`RegDataWidth-1:0] logicout;
reg[`RegDataWidth-1:0] arithout;
reg[`RegDataWidth-1:0] shiftout;
wire[`RegDataWidth-1:0] reg2_comp;
wire[`RegDataWidth-1:0] sub_res;
wire[`RegDataWidth-1:0] sum_res;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
assign sub_res = reg1_i + (~reg2_i) + 1;
assign reg1_eq_reg2 = (reg1_i == reg2_i);
assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP || aluop_i == `EXE_SGE_OP ?
( (reg1_i[31] && !reg2_i[31])
|| (reg1_i[31] && reg2_i[31] && sub_res[31])
|| (!reg1_i[31] && !reg2_i[31] && sub_res[31])
) : (reg1_i < reg2_i));
always @ (*)
begin
if (rst == `RstEnable) begin
addr_o <= `ZeroWord;
end else if (jump_type_i != `NoJump || memop_o != `MEM_NOP) begin
addr_o <= addr_base + addr_off;
end else begin
addr_o <= `ZeroWord;
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
logicout <= `ZeroWord;
arithout <= `ZeroWord;
shiftout <= `ZeroWord;
end else begin
logicout <= `ZeroWord;
arithout <= `ZeroWord;
shiftout <= `ZeroWord;
case (aluop_i)
`EXE_ADD_OP: begin
arithout <= reg1_i + reg2_i;
end
`EXE_SUB_OP: begin
arithout <= sub_res;
end
`EXE_SLT_OP: begin
arithout <= {31'b0, reg1_lt_reg2};
end
`EXE_SLTU_OP: begin
arithout <= {31'b0, reg1_lt_reg2};
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_SLL_OP: begin
shiftout <= reg1_i << reg2_i[4:0];
end
`EXE_SRL_OP: begin
shiftout <= reg1_i >> reg2_i[4:0];
end
`EXE_SRA_OP: begin
shiftout <= (reg1_i >> reg2_i[4:0])
| ({32{reg1_i[31]}} << (6'd32 - {1'b0, reg2_i[4:0]}));
end
`EXE_SEQ_OP: begin
arithout <= {31'b0, reg1_eq_reg2};
end
`EXE_SNE_OP: begin
arithout <= {31'b0, !reg1_eq_reg2};
end
`EXE_SGE_OP: begin
arithout <= {31'b0, !reg1_lt_reg2};
end
`EXE_SGEU_OP: begin
arithout <= {31'b0, !reg1_lt_reg2};
end
endcase
end
end
always @ (*)
begin
wd_o <= wd_i;
wreg_o <= wreg_i;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
case (alusel_i)
`EXE_LOGIC_RES: begin
wdata_o <= logicout;
end
`EXE_ARITH_RES: begin
wdata_o <= arithout;
end
`EXE_SHIFT_RES: begin
wdata_o <= shiftout;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | 0 |
5,393 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v | 113,962,532 | id.v | v | 515 | 86 | [] | [] | [] | [(204, 714)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:8: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] pc_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:9: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] inst_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:12: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] reg1_data_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:13: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] reg2_data_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:16: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] mem_wdata_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:17: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] mem_wd_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:25: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] ex_wdata_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:26: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] ex_wd_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:32: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] reg1_addr_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:33: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] reg2_addr_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:36: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] aluop_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:37: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] alusel_o,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:38: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] reg1_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:39: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] reg2_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:40: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] wd_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:42: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:43: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:60: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] imm;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:74: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:75: Define or directive not defined: \'`EXE_NOP_OP\'\n aluop_o <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:76: Define or directive not defined: \'`EXE_NOP_RES\'\n alusel_o <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n alusel_o <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:77: Define or directive not defined: \'`ZeroRegAddr\'\n wd_o <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wd_o <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:78: Define or directive not defined: \'`WriteDisable\'\n pre_wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pre_wreg_o <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:79: Define or directive not defined: \'`InstValid\'\n inst_valid <= `InstValid;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n inst_valid <= `InstValid;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:80: Define or directive not defined: \'`DataZero\'\n reg1_type <= `DataZero;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg1_type <= `DataZero;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:81: Define or directive not defined: \'`DataZero\'\n reg2_type <= `DataZero;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg2_type <= `DataZero;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:82: Define or directive not defined: \'`DataZero\'\n addr_base_type <= `DataZero;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n addr_base_type <= `DataZero;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:83: Define or directive not defined: \'`ChipDisable\'\n reg1_read_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg1_read_o <= `ChipDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:84: Define or directive not defined: \'`ChipDisable\'\n reg2_read_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg2_read_o <= `ChipDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:85: Define or directive not defined: \'`ZeroRegAddr\'\n reg1_addr_o <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg1_addr_o <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:86: Define or directive not defined: \'`ZeroRegAddr\'\n reg2_addr_o <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n reg2_addr_o <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:88: Define or directive not defined: \'`ZeroWord\'\n addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:89: Define or directive not defined: \'`NoJump\'\n jump_type_inner <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_inner <= `NoJump;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:90: Define or directive not defined: \'`MEM_NOP\'\n pre_memop_o <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/id.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n pre_memop_o <= `MEM_NOP;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,155 | module | module id(
input wire rst,
input wire[`MemAddrWidth-1:0] pc_i,
input wire[`InstWidth-1:0] inst_i,
input wire[`RegDataWidth-1:0] reg1_data_i,
input wire[`RegDataWidth-1:0] reg2_data_i,
input wire[`RegDataWidth-1:0] mem_wdata_i,
input wire[`RegAddrWidth-1:0] mem_wd_i,
input wire mem_wreg_i,
input wire[1:0] jump_type_i,
input wire[1:0] ex_memop_i,
input wire[`RegDataWidth-1:0] ex_wdata_i,
input wire[`RegAddrWidth-1:0] ex_wd_i,
input wire ex_wreg_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrWidth-1:0] reg1_addr_o,
output reg[`RegAddrWidth-1:0] reg2_addr_o,
output reg[`AluOpWidth-1:0] aluop_o,
output reg[`AluSelWidth-1:0] alusel_o,
output reg[`RegDataWidth-1:0] reg1_o,
output reg[`RegDataWidth-1:0] reg2_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o,
output reg[`RegDataWidth-1:0] addr_base,
output reg[`RegDataWidth-1:0] addr_off,
output reg[1:0] jump_type_o,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o,
output reg stall_req
);
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
reg[1:0] reg1_type;
reg[1:0] reg2_type;
reg[1:0] addr_base_type;
reg[`RegDataWidth-1:0] imm;
reg inst_valid;
reg[1:0] jump_type_inner;
reg[3:0] sub_reqstall;
reg stall_cur_available;
reg pre_wreg_o;
reg[1:0] pre_memop_o;
always @ (*)
begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
wd_o <= `ZeroRegAddr;
pre_wreg_o <= `WriteDisable;
inst_valid <= `InstValid;
reg1_type <= `DataZero;
reg2_type <= `DataZero;
addr_base_type <= `DataZero;
reg1_read_o <= `ChipDisable;
reg2_read_o <= `ChipDisable;
reg1_addr_o <= `ZeroRegAddr;
reg2_addr_o <= `ZeroRegAddr;
imm <= 32'b0;
addr_off <= `ZeroWord;
jump_type_inner <= `NoJump;
pre_memop_o <= `MEM_NOP;
memfunct_o <= 3'b000;
sub_reqstall[0] <= `NoRequestStall;
stall_cur_available <= `No;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
wd_o <= `ZeroRegAddr;
pre_wreg_o <= `WriteDisable;
inst_valid <= `InstValid;
reg1_type <= `DataZero;
reg2_type <= `DataZero;
addr_base_type <= `DataZero;
reg1_read_o <= `ChipDisable;
reg2_read_o <= `ChipDisable;
reg1_addr_o <= `ZeroRegAddr;
reg2_addr_o <= `ZeroRegAddr;
imm <= `ZeroWord;
addr_off <= `ZeroWord;
jump_type_inner <= `NoJump;
pre_memop_o <= `MEM_NOP;
memfunct_o <= 3'b000;
sub_reqstall[0] <= `NoRequestStall;
stall_cur_available <= `No;
case (opcode)
`OP_OP_IMM: begin
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataReg;
reg2_type <= `DataImm;
reg1_read_o <= `ChipEnable;
reg1_addr_o <= inst_i[19:15];
reg2_read_o <= `ChipDisable;
reg2_addr_o <= `ZeroRegAddr;
imm <= {{20{inst_i[31]}}, inst_i[31:20]};
case (funct3)
`FUNCT3_ADDI: begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTI: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTIU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_XORI: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_ORI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_ANDI: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_SLLI: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_SHIFT_RES;
end
`FUNCT3_SRLI_SRAI: begin
if(funct7[5] == 1'b0) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_SHIFT_RES;
end else begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_SHIFT_RES;
end
end
default:
begin
inst_valid <= `InstInvalid;
end
endcase
end
`OP_OP: begin
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataReg;
reg2_type <= `DataReg;
reg1_read_o <= `ChipEnable;
reg1_addr_o <= inst_i[19:15];
reg2_read_o <= `ChipEnable;
reg2_addr_o <= inst_i[24:20];
case(funct3)
`FUNCT3_ADD_SUB: begin
if (funct7[5] == 1'b0) begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end else begin
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`FUNCT3_SLL: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_SHIFT_RES;
end
`FUNCT3_SLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_XOR: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_SRL_SRA: begin
if(funct7[5] == 1'b0) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_SHIFT_RES;
end else begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_SHIFT_RES;
end
end
`FUNCT3_OR: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_AND: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_LOGIC_RES;
end
default: begin
inst_valid <= `InstInvalid;
end
endcase
end
`OP_LUI: begin
imm <= {inst_i[31:12], 12'h000};
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataZero;
reg2_type <= `DataImm;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`OP_AUIPC: begin
imm <= {inst_i[31:12], 12'h000};
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataPC;
reg2_type <= `DataImm;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
`OP_BRANCH: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpBranch;
addr_base_type <= `DataPC;
addr_off <= {{20{inst_i[31]}},inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
reg1_type <= `DataReg;
reg2_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
pre_wreg_o <= `WriteDisable;
wd_o <= `ZeroRegAddr;
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
case (funct3)
`FUNCT3_BEQ: begin
aluop_o <= `EXE_SEQ_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BNE: begin
aluop_o <= `EXE_SNE_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BGE: begin
aluop_o <= `EXE_SGE_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BGEU: begin
aluop_o <= `EXE_SGEU_OP;
alusel_o <= `EXE_ARITH_RES;
end
default: begin
inst_valid <= `InstInvalid;
end
endcase
end
end
`OP_JAL: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpUncdt;
addr_base_type <= `DataPC;
addr_off <= {{12{inst_i[31]}},inst_i[19:12],inst_i[20],inst_i[30:21],1'b0};
reg1_type <= `DataPC;
reg2_type <= `DataImm;
imm <= 32'd4;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`OP_JALR: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpUncdt;
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:20]};
reg1_type <= `DataPC;
reg2_type <= `DataImm;
imm <= 32'd4;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`OP_LOAD: begin
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:20]};
reg1_type <= `DataZero;
reg2_type <= `DataZero;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
pre_memop_o <= `MEM_LOAD;
memfunct_o <= funct3;
end
`OP_STORE: begin
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:25],inst_i[11:7]};
reg1_type <= `DataZero;
reg2_type <= `DataReg;
reg2_read_o <= `ReadEnable;
reg2_addr_o <= inst_i[24:20];
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
pre_memop_o <= `MEM_STORE;
memfunct_o <= funct3;
end
default:
begin
inst_valid <= `InstInvalid;
end
endcase
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
reg1_o <= `ZeroWord;
sub_reqstall[1] <= `NoRequestStall;
end else begin
sub_reqstall[1] <= `NoRequestStall;
if (reg1_type == `DataReg) begin
if (reg1_addr_o == `ZeroRegAddr) begin
reg1_o <= `ZeroWord;
end else if ( ex_wreg_i == `WriteEnable
&& ex_wd_i == reg1_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[1] <= `RequestStall;
reg1_o <= `ZeroWord;
end else begin
reg1_o <= ex_wdata_i;
end
reg1_o <= ex_wdata_i;
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg1_addr_o) begin
reg1_o <= mem_wdata_i;
end else begin
reg1_o <= reg1_data_i;
end
end else if (reg1_type == `DataImm) begin
reg1_o <= imm;
end else if (reg1_type == `DataPC) begin
reg1_o <= pc_i;
end else begin
reg1_o <= `ZeroWord;
end
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
reg2_o <= `ZeroWord;
sub_reqstall[2] <= `NoRequestStall;
end else begin
sub_reqstall[2] <= `NoRequestStall;
if (reg2_type == `DataReg) begin
if (reg2_addr_o == `ZeroRegAddr) begin
reg2_o <= `ZeroWord;
end else if ( ex_wreg_i == `WriteEnable
&& ex_wd_i == reg2_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[2] <= `RequestStall;
reg2_o <= `ZeroWord;
end else begin
reg2_o <= ex_wdata_i;
end
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg2_addr_o) begin
reg2_o <= mem_wdata_i;
end else begin
reg2_o <= reg2_data_i;
end
end else if (reg2_type == `DataImm) begin
reg2_o <= imm;
end else if (reg2_type == `DataPC) begin
reg2_o <= pc_i;
end else begin
reg2_o <= `ZeroWord;
end
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
addr_base <= `ZeroWord;
sub_reqstall[3] <= `NoRequestStall;
end else begin
sub_reqstall[3] <= `NoRequestStall;
if (addr_base_type == `DataReg) begin
if (reg1_addr_o == `ZeroRegAddr) begin
addr_base <= `ZeroWord;
end else if (ex_wreg_i == `WriteEnable
&& ex_wd_i == reg1_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[3] <= `RequestStall;
addr_base <= `ZeroWord;
end else begin
addr_base <= ex_wdata_i;
end
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg1_addr_o) begin
addr_base <= mem_wdata_i;
end else begin
addr_base <= reg1_data_i;
end
end else if (addr_base_type == `DataImm) begin
addr_base <= imm;
end else if (addr_base_type == `DataPC) begin
addr_base <= pc_i;
end else begin
addr_base <= `ZeroWord;
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
stall_req <= `NoRequestStall;
wreg_o <= `WriteDisable;
memop_o <= `MEM_NOP;
jump_type_o <= `NoJump;
end else begin
if(sub_reqstall[1] || sub_reqstall[2] || sub_reqstall[3]) begin
stall_req <= `RequestStall;
wreg_o <= `WriteDisable;
memop_o <= `MEM_NOP;
jump_type_o <= `NoJump;
end else if(sub_reqstall[0]) begin
stall_req <= `RequestStall;
wreg_o <= pre_wreg_o;
memop_o <= pre_memop_o;
jump_type_o <= jump_type_inner;
end else begin
stall_req <= `NoRequestStall;
wreg_o <= pre_wreg_o;
memop_o <= pre_memop_o;
jump_type_o <= jump_type_inner;
end
end
end
endmodule | module id(
input wire rst,
input wire[`MemAddrWidth-1:0] pc_i,
input wire[`InstWidth-1:0] inst_i,
input wire[`RegDataWidth-1:0] reg1_data_i,
input wire[`RegDataWidth-1:0] reg2_data_i,
input wire[`RegDataWidth-1:0] mem_wdata_i,
input wire[`RegAddrWidth-1:0] mem_wd_i,
input wire mem_wreg_i,
input wire[1:0] jump_type_i,
input wire[1:0] ex_memop_i,
input wire[`RegDataWidth-1:0] ex_wdata_i,
input wire[`RegAddrWidth-1:0] ex_wd_i,
input wire ex_wreg_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrWidth-1:0] reg1_addr_o,
output reg[`RegAddrWidth-1:0] reg2_addr_o,
output reg[`AluOpWidth-1:0] aluop_o,
output reg[`AluSelWidth-1:0] alusel_o,
output reg[`RegDataWidth-1:0] reg1_o,
output reg[`RegDataWidth-1:0] reg2_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o,
output reg[`RegDataWidth-1:0] addr_base,
output reg[`RegDataWidth-1:0] addr_off,
output reg[1:0] jump_type_o,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o,
output reg stall_req
); |
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
reg[1:0] reg1_type;
reg[1:0] reg2_type;
reg[1:0] addr_base_type;
reg[`RegDataWidth-1:0] imm;
reg inst_valid;
reg[1:0] jump_type_inner;
reg[3:0] sub_reqstall;
reg stall_cur_available;
reg pre_wreg_o;
reg[1:0] pre_memop_o;
always @ (*)
begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
wd_o <= `ZeroRegAddr;
pre_wreg_o <= `WriteDisable;
inst_valid <= `InstValid;
reg1_type <= `DataZero;
reg2_type <= `DataZero;
addr_base_type <= `DataZero;
reg1_read_o <= `ChipDisable;
reg2_read_o <= `ChipDisable;
reg1_addr_o <= `ZeroRegAddr;
reg2_addr_o <= `ZeroRegAddr;
imm <= 32'b0;
addr_off <= `ZeroWord;
jump_type_inner <= `NoJump;
pre_memop_o <= `MEM_NOP;
memfunct_o <= 3'b000;
sub_reqstall[0] <= `NoRequestStall;
stall_cur_available <= `No;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
wd_o <= `ZeroRegAddr;
pre_wreg_o <= `WriteDisable;
inst_valid <= `InstValid;
reg1_type <= `DataZero;
reg2_type <= `DataZero;
addr_base_type <= `DataZero;
reg1_read_o <= `ChipDisable;
reg2_read_o <= `ChipDisable;
reg1_addr_o <= `ZeroRegAddr;
reg2_addr_o <= `ZeroRegAddr;
imm <= `ZeroWord;
addr_off <= `ZeroWord;
jump_type_inner <= `NoJump;
pre_memop_o <= `MEM_NOP;
memfunct_o <= 3'b000;
sub_reqstall[0] <= `NoRequestStall;
stall_cur_available <= `No;
case (opcode)
`OP_OP_IMM: begin
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataReg;
reg2_type <= `DataImm;
reg1_read_o <= `ChipEnable;
reg1_addr_o <= inst_i[19:15];
reg2_read_o <= `ChipDisable;
reg2_addr_o <= `ZeroRegAddr;
imm <= {{20{inst_i[31]}}, inst_i[31:20]};
case (funct3)
`FUNCT3_ADDI: begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTI: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTIU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_XORI: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_ORI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_ANDI: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_SLLI: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_SHIFT_RES;
end
`FUNCT3_SRLI_SRAI: begin
if(funct7[5] == 1'b0) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_SHIFT_RES;
end else begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_SHIFT_RES;
end
end
default:
begin
inst_valid <= `InstInvalid;
end
endcase
end
`OP_OP: begin
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataReg;
reg2_type <= `DataReg;
reg1_read_o <= `ChipEnable;
reg1_addr_o <= inst_i[19:15];
reg2_read_o <= `ChipEnable;
reg2_addr_o <= inst_i[24:20];
case(funct3)
`FUNCT3_ADD_SUB: begin
if (funct7[5] == 1'b0) begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end else begin
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`FUNCT3_SLL: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_SHIFT_RES;
end
`FUNCT3_SLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_SLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_XOR: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_SRL_SRA: begin
if(funct7[5] == 1'b0) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_SHIFT_RES;
end else begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_SHIFT_RES;
end
end
`FUNCT3_OR: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`FUNCT3_AND: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_LOGIC_RES;
end
default: begin
inst_valid <= `InstInvalid;
end
endcase
end
`OP_LUI: begin
imm <= {inst_i[31:12], 12'h000};
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataZero;
reg2_type <= `DataImm;
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
end
`OP_AUIPC: begin
imm <= {inst_i[31:12], 12'h000};
wd_o <= inst_i[11:7];
pre_wreg_o <= `WriteEnable;
reg1_type <= `DataPC;
reg2_type <= `DataImm;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
`OP_BRANCH: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpBranch;
addr_base_type <= `DataPC;
addr_off <= {{20{inst_i[31]}},inst_i[7],inst_i[30:25],inst_i[11:8],1'b0};
reg1_type <= `DataReg;
reg2_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg2_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
reg2_addr_o <= inst_i[24:20];
pre_wreg_o <= `WriteDisable;
wd_o <= `ZeroRegAddr;
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
case (funct3)
`FUNCT3_BEQ: begin
aluop_o <= `EXE_SEQ_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BNE: begin
aluop_o <= `EXE_SNE_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BGE: begin
aluop_o <= `EXE_SGE_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_ARITH_RES;
end
`FUNCT3_BGEU: begin
aluop_o <= `EXE_SGEU_OP;
alusel_o <= `EXE_ARITH_RES;
end
default: begin
inst_valid <= `InstInvalid;
end
endcase
end
end
`OP_JAL: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpUncdt;
addr_base_type <= `DataPC;
addr_off <= {{12{inst_i[31]}},inst_i[19:12],inst_i[20],inst_i[30:21],1'b0};
reg1_type <= `DataPC;
reg2_type <= `DataImm;
imm <= 32'd4;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`OP_JALR: begin
if (jump_type_i != `NoJump) begin
end else begin
jump_type_inner <= `JumpUncdt;
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:20]};
reg1_type <= `DataPC;
reg2_type <= `DataImm;
imm <= 32'd4;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
sub_reqstall[0] <= `RequestStall;
stall_cur_available <= `Yes;
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_ARITH_RES;
end
end
`OP_LOAD: begin
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:20]};
reg1_type <= `DataZero;
reg2_type <= `DataZero;
pre_wreg_o <= `WriteEnable;
wd_o <= inst_i[11:7];
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_NOP_RES;
pre_memop_o <= `MEM_LOAD;
memfunct_o <= funct3;
end
`OP_STORE: begin
addr_base_type <= `DataReg;
reg1_read_o <= `ReadEnable;
reg1_addr_o <= inst_i[19:15];
addr_off <= {{20{inst_i[31]}},inst_i[31:25],inst_i[11:7]};
reg1_type <= `DataZero;
reg2_type <= `DataReg;
reg2_read_o <= `ReadEnable;
reg2_addr_o <= inst_i[24:20];
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_LOGIC_RES;
pre_memop_o <= `MEM_STORE;
memfunct_o <= funct3;
end
default:
begin
inst_valid <= `InstInvalid;
end
endcase
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
reg1_o <= `ZeroWord;
sub_reqstall[1] <= `NoRequestStall;
end else begin
sub_reqstall[1] <= `NoRequestStall;
if (reg1_type == `DataReg) begin
if (reg1_addr_o == `ZeroRegAddr) begin
reg1_o <= `ZeroWord;
end else if ( ex_wreg_i == `WriteEnable
&& ex_wd_i == reg1_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[1] <= `RequestStall;
reg1_o <= `ZeroWord;
end else begin
reg1_o <= ex_wdata_i;
end
reg1_o <= ex_wdata_i;
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg1_addr_o) begin
reg1_o <= mem_wdata_i;
end else begin
reg1_o <= reg1_data_i;
end
end else if (reg1_type == `DataImm) begin
reg1_o <= imm;
end else if (reg1_type == `DataPC) begin
reg1_o <= pc_i;
end else begin
reg1_o <= `ZeroWord;
end
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
reg2_o <= `ZeroWord;
sub_reqstall[2] <= `NoRequestStall;
end else begin
sub_reqstall[2] <= `NoRequestStall;
if (reg2_type == `DataReg) begin
if (reg2_addr_o == `ZeroRegAddr) begin
reg2_o <= `ZeroWord;
end else if ( ex_wreg_i == `WriteEnable
&& ex_wd_i == reg2_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[2] <= `RequestStall;
reg2_o <= `ZeroWord;
end else begin
reg2_o <= ex_wdata_i;
end
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg2_addr_o) begin
reg2_o <= mem_wdata_i;
end else begin
reg2_o <= reg2_data_i;
end
end else if (reg2_type == `DataImm) begin
reg2_o <= imm;
end else if (reg2_type == `DataPC) begin
reg2_o <= pc_i;
end else begin
reg2_o <= `ZeroWord;
end
end
end
always @ (*)
begin
if (rst == `RstEnable) begin
addr_base <= `ZeroWord;
sub_reqstall[3] <= `NoRequestStall;
end else begin
sub_reqstall[3] <= `NoRequestStall;
if (addr_base_type == `DataReg) begin
if (reg1_addr_o == `ZeroRegAddr) begin
addr_base <= `ZeroWord;
end else if (ex_wreg_i == `WriteEnable
&& ex_wd_i == reg1_addr_o) begin
if(ex_memop_i == `MEM_LOAD) begin
sub_reqstall[3] <= `RequestStall;
addr_base <= `ZeroWord;
end else begin
addr_base <= ex_wdata_i;
end
end else if ( mem_wreg_i == `WriteEnable
&& mem_wd_i == reg1_addr_o) begin
addr_base <= mem_wdata_i;
end else begin
addr_base <= reg1_data_i;
end
end else if (addr_base_type == `DataImm) begin
addr_base <= imm;
end else if (addr_base_type == `DataPC) begin
addr_base <= pc_i;
end else begin
addr_base <= `ZeroWord;
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
stall_req <= `NoRequestStall;
wreg_o <= `WriteDisable;
memop_o <= `MEM_NOP;
jump_type_o <= `NoJump;
end else begin
if(sub_reqstall[1] || sub_reqstall[2] || sub_reqstall[3]) begin
stall_req <= `RequestStall;
wreg_o <= `WriteDisable;
memop_o <= `MEM_NOP;
jump_type_o <= `NoJump;
end else if(sub_reqstall[0]) begin
stall_req <= `RequestStall;
wreg_o <= pre_wreg_o;
memop_o <= pre_memop_o;
jump_type_o <= jump_type_inner;
end else begin
stall_req <= `NoRequestStall;
wreg_o <= pre_wreg_o;
memop_o <= pre_memop_o;
jump_type_o <= jump_type_inner;
end
end
end
endmodule | 0 |
5,394 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v | 113,962,532 | mem.v | v | 137 | 78 | [] | [] | [] | [(205, 335)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:9: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] wdata_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:10: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] wd_i,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:12: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] exmem_addr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:17: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] read_data_value,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:22: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] data_addr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:23: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] write_data_value,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:24: Define or directive not defined: \'`RegDataBytes\'\n output reg[`RegDataBytes-1:0] write_data_mask,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:25: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] wdata_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:26: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] wd_o,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:32: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:33: Define or directive not defined: \'`ChipDisable\'\n data_ce <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:35: Define or directive not defined: \'`ZeroWord\'\n data_addr <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n data_addr <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:36: Define or directive not defined: \'`ZeroWord\'\n write_data_value <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n write_data_value <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:38: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wdata_o <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:39: Define or directive not defined: \'`ZeroRegAddr\'\n wd_o <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wd_o <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:40: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wreg_o <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:42: Define or directive not defined: \'`ChipDisable\'\n data_ce <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:44: Define or directive not defined: \'`ZeroWord\'\n data_addr <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:45: Define or directive not defined: \'`ZeroWord\'\n write_data_value <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:51: Define or directive not defined: \'`MEM_LOAD\'\n `MEM_LOAD: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:51: syntax error, unexpected \':\', expecting endcase\n `MEM_LOAD: begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:52: Define or directive not defined: \'`ChipEnable\'\n data_ce <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:53: Define or directive not defined: \'`MemRead\'\n data_optype <= `MemRead;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:56: Define or directive not defined: \'`FUNCT3_LBU\'\n `FUNCT3_LBU: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:56: syntax error, unexpected \':\', expecting endcase\n `FUNCT3_LBU: begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:64: Define or directive not defined: \'`FUNCT3_LB\'\n `FUNCT3_LB: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:72: Define or directive not defined: \'`FUNCT3_LHU\'\n `FUNCT3_LHU: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:78: Define or directive not defined: \'`FUNCT3_LH\'\n `FUNCT3_LH: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:84: Define or directive not defined: \'`FUNCT3_LW\'\n `FUNCT3_LW: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:89: Define or directive not defined: \'`MEM_STORE\'\n `MEM_STORE: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:90: Define or directive not defined: \'`ChipEnable\'\n data_ce <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:91: Define or directive not defined: \'`MemWrite\'\n data_optype <= `MemWrite;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:94: Define or directive not defined: \'`FUNCT3_SB\'\n `FUNCT3_SB: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:94: syntax error, unexpected \':\', expecting endcase\n `FUNCT3_SB: begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:114: Define or directive not defined: \'`FUNCT3_SH\'\n `FUNCT3_SH: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/mem.v:126: Define or directive not defined: \'`FUNCT3_SW\'\n `FUNCT3_SW: begin\n ^~~~~~~~~~\n%Error: Cannot continue\n' | 6,156 | module | module mem(
input wire rst,
input wire[`RegDataWidth-1:0] wdata_i,
input wire[`RegAddrWidth-1:0] wd_i,
input wire wreg_i,
input wire[`RegDataWidth-1:0] exmem_addr,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
input wire[`RegDataWidth-1:0] read_data_value,
output reg data_ce,
output reg data_optype,
output reg[`MemAddrWidth-1:0] data_addr,
output reg[`RegDataWidth-1:0] write_data_value,
output reg[`RegDataBytes-1:0] write_data_mask,
output reg[`RegDataWidth-1:0] wdata_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o
);
always @ (*)
begin
if (rst == `RstEnable) begin
data_ce <= `ChipDisable;
data_optype <= 1'b0;
data_addr <= `ZeroWord;
write_data_value <= `ZeroWord;
write_data_mask <= 4'b0000;
wdata_o <= `ZeroWord;
wd_o <= `ZeroRegAddr;
wreg_o <= `WriteDisable;
end else begin
data_ce <= `ChipDisable;
data_optype <= 1'b0;
data_addr <= `ZeroWord;
write_data_value <= `ZeroWord;
write_data_mask <= 0;
wdata_o <= wdata_i;
wd_o <= wd_i;
wreg_o <= wreg_i;
case (memop_i)
`MEM_LOAD: begin
data_ce <= `ChipEnable;
data_optype <= `MemRead;
data_addr <= {exmem_addr[31:2],2'b00};
case (memfunct_i)
`FUNCT3_LBU: begin
case (exmem_addr[1:0])
2'b00: wdata_o <= {{24{1'b0}},read_data_value[7:0]};
2'b01: wdata_o <= {{24{1'b0}},read_data_value[15:8]};
2'b10: wdata_o <= {{24{1'b0}},read_data_value[23:16]};
2'b11: wdata_o <= {{24{1'b0}},read_data_value[31:24]};
endcase
end
`FUNCT3_LB: begin
case (exmem_addr[1:0])
2'b00: wdata_o <= {{24{read_data_value[7]}},read_data_value[7:0]};
2'b01: wdata_o <= {{24{read_data_value[15]}},read_data_value[15:8]};
2'b10: wdata_o <= {{24{read_data_value[23]}},read_data_value[23:16]};
2'b11: wdata_o <= {{24{read_data_value[31]}},read_data_value[31:24]};
endcase
end
`FUNCT3_LHU: begin
case (exmem_addr[1])
1'b0: wdata_o <= {{16{1'b0}},read_data_value[15:0]};
1'b1: wdata_o <= {{16{1'b0}},read_data_value[31:16]};
endcase
end
`FUNCT3_LH: begin
case (exmem_addr[0])
1'b0: wdata_o <= {{16{read_data_value[15]}},read_data_value[15:0]};
1'b1: wdata_o <= {{16{read_data_value[31]}},read_data_value[31:16]};
endcase
end
`FUNCT3_LW: begin
wdata_o <= read_data_value;
end
endcase
end
`MEM_STORE: begin
data_ce <= `ChipEnable;
data_optype <= `MemWrite;
data_addr <= {exmem_addr[31:2],2'b00};
case (memfunct_i)
`FUNCT3_SB: begin
case (exmem_addr[1:0])
2'b00: begin
write_data_mask <= 4'b0001;
write_data_value <= wdata_i;
end
2'b01: begin
write_data_mask <= 4'b0010;
write_data_value <= wdata_i << 8;
end
2'b10: begin
write_data_mask <= 4'b0100;
write_data_value <= wdata_i << 16;
end
2'b11: begin
write_data_mask <= 4'b1000;
write_data_value <= wdata_i << 24;
end
endcase
end
`FUNCT3_SH: begin
case (exmem_addr[1])
1'b0: begin
write_data_mask <= 4'b0011;
write_data_value <= wdata_i;
end
1'b1: begin
write_data_mask <= 4'b1100;
write_data_value <= wdata_i << 16;
end
endcase
end
`FUNCT3_SW: begin
write_data_mask <= 4'b1111;
write_data_value <= wdata_i;
end
endcase
end
endcase
end
end
endmodule | module mem(
input wire rst,
input wire[`RegDataWidth-1:0] wdata_i,
input wire[`RegAddrWidth-1:0] wd_i,
input wire wreg_i,
input wire[`RegDataWidth-1:0] exmem_addr,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
input wire[`RegDataWidth-1:0] read_data_value,
output reg data_ce,
output reg data_optype,
output reg[`MemAddrWidth-1:0] data_addr,
output reg[`RegDataWidth-1:0] write_data_value,
output reg[`RegDataBytes-1:0] write_data_mask,
output reg[`RegDataWidth-1:0] wdata_o,
output reg[`RegAddrWidth-1:0] wd_o,
output reg wreg_o
); |
always @ (*)
begin
if (rst == `RstEnable) begin
data_ce <= `ChipDisable;
data_optype <= 1'b0;
data_addr <= `ZeroWord;
write_data_value <= `ZeroWord;
write_data_mask <= 4'b0000;
wdata_o <= `ZeroWord;
wd_o <= `ZeroRegAddr;
wreg_o <= `WriteDisable;
end else begin
data_ce <= `ChipDisable;
data_optype <= 1'b0;
data_addr <= `ZeroWord;
write_data_value <= `ZeroWord;
write_data_mask <= 0;
wdata_o <= wdata_i;
wd_o <= wd_i;
wreg_o <= wreg_i;
case (memop_i)
`MEM_LOAD: begin
data_ce <= `ChipEnable;
data_optype <= `MemRead;
data_addr <= {exmem_addr[31:2],2'b00};
case (memfunct_i)
`FUNCT3_LBU: begin
case (exmem_addr[1:0])
2'b00: wdata_o <= {{24{1'b0}},read_data_value[7:0]};
2'b01: wdata_o <= {{24{1'b0}},read_data_value[15:8]};
2'b10: wdata_o <= {{24{1'b0}},read_data_value[23:16]};
2'b11: wdata_o <= {{24{1'b0}},read_data_value[31:24]};
endcase
end
`FUNCT3_LB: begin
case (exmem_addr[1:0])
2'b00: wdata_o <= {{24{read_data_value[7]}},read_data_value[7:0]};
2'b01: wdata_o <= {{24{read_data_value[15]}},read_data_value[15:8]};
2'b10: wdata_o <= {{24{read_data_value[23]}},read_data_value[23:16]};
2'b11: wdata_o <= {{24{read_data_value[31]}},read_data_value[31:24]};
endcase
end
`FUNCT3_LHU: begin
case (exmem_addr[1])
1'b0: wdata_o <= {{16{1'b0}},read_data_value[15:0]};
1'b1: wdata_o <= {{16{1'b0}},read_data_value[31:16]};
endcase
end
`FUNCT3_LH: begin
case (exmem_addr[0])
1'b0: wdata_o <= {{16{read_data_value[15]}},read_data_value[15:0]};
1'b1: wdata_o <= {{16{read_data_value[31]}},read_data_value[31:16]};
endcase
end
`FUNCT3_LW: begin
wdata_o <= read_data_value;
end
endcase
end
`MEM_STORE: begin
data_ce <= `ChipEnable;
data_optype <= `MemWrite;
data_addr <= {exmem_addr[31:2],2'b00};
case (memfunct_i)
`FUNCT3_SB: begin
case (exmem_addr[1:0])
2'b00: begin
write_data_mask <= 4'b0001;
write_data_value <= wdata_i;
end
2'b01: begin
write_data_mask <= 4'b0010;
write_data_value <= wdata_i << 8;
end
2'b10: begin
write_data_mask <= 4'b0100;
write_data_value <= wdata_i << 16;
end
2'b11: begin
write_data_mask <= 4'b1000;
write_data_value <= wdata_i << 24;
end
endcase
end
`FUNCT3_SH: begin
case (exmem_addr[1])
1'b0: begin
write_data_mask <= 4'b0011;
write_data_value <= wdata_i;
end
1'b1: begin
write_data_mask <= 4'b1100;
write_data_value <= wdata_i << 16;
end
endcase
end
`FUNCT3_SW: begin
write_data_mask <= 4'b1111;
write_data_value <= wdata_i;
end
endcase
end
endcase
end
end
endmodule | 0 |
5,395 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v | 113,962,532 | memory_sim.v | v | 131 | 77 | [] | [] | [] | [(204, 330)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, data[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, bytes[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v:38: Define or directive not defined: \'`MemFile\'\n $readmemh(`MemFile, data);\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/memory_sim.v:38: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n $readmemh(`MemFile, data);\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,157 | module | module memory_sim(
input wire clk,
input wire rst,
output Tx,
input Rx
);
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag,
uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);
localparam MEM_SIZE = 8192;
reg[7:0] data[MEM_SIZE-1:0];
reg[7:0] bytes[8:0];
integer i;
initial begin
for(i = 0; i < MEM_SIZE; i=i+1) begin
data[i] = 0;
end
for(i = 0; i < 512; i=i+1) begin
$dumpvars(0, data[i]);
end
for(i = 0; i < 9; i=i+1) begin
$dumpvars(0, bytes[i]);
end
$readmemh(`MemFile, data);
end
integer cur_count;
integer next_count;
integer cur_disp;
integer next_disp;
integer index;
wire[31:0] addr;
wire[3:0] mask;
assign addr = {bytes[3], bytes[2], bytes[1], bytes[0]};
assign mask = bytes[4][3:0];
localparam FullDisp = 3;
integer idx;
always @ (*) begin
if(rst) begin
for(index = 0; index < 9; index=index+1)
bytes[index] = 0;
next_count <= 0;
next_disp <= 0;
uart_send_flag <= 0;
uart_recv_flag <= 0;
end else begin
uart_send_flag <= 0;
uart_recv_flag <= 0;
if(cur_count == 5 && bytes[4][7:4] == 4'b0000) begin
if(uart_sendable) begin
uart_send_flag <= 1;
uart_send_data <= data[addr+cur_disp];
if(cur_disp == FullDisp) begin
next_disp <= 0;
next_count <= 0;
$display("[memory_sim] cpu read request [%x], send data %x",
addr, {data[addr+3],data[addr+2],data[addr+1],data[addr]});
end else begin
next_disp <= cur_disp + 1;
next_count <= cur_count;
end
end else begin
next_disp <= cur_disp;
next_count <= cur_count;
end
end else if(cur_count == 9) begin
if(mask[0]) data[addr+0] <= bytes[5 + 0];
if(mask[1]) data[addr+1] <= bytes[5 + 1];
if(mask[2]) data[addr+2] <= bytes[5 + 2];
if(mask[3]) data[addr+3] <= bytes[5 + 3];
next_count <= 0;
next_disp <= 0;
if(addr == 32'h104 && mask[0]) begin
$display("*** %c ***", bytes[5]);
end
if(addr == 32'h108 && mask[0]) begin
$display("access %x, successfully exit", 32'h108);
$finish;
end
end else begin
if(uart_receivable) begin
uart_recv_flag <= 1;
bytes[cur_count] <= uart_recv_data;
next_count <= cur_count + 1;
next_disp <= 0;
end else begin
next_count <= cur_count;
next_disp <= 0;
end
end
end
end
always @ (posedge clk or posedge rst) begin
if(rst) begin
cur_count <= 0;
cur_disp <= 0;
end else begin
cur_count <= next_count;
cur_disp <= next_disp;
end
end
endmodule | module memory_sim(
input wire clk,
input wire rst,
output Tx,
input Rx
); |
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag,
uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);
localparam MEM_SIZE = 8192;
reg[7:0] data[MEM_SIZE-1:0];
reg[7:0] bytes[8:0];
integer i;
initial begin
for(i = 0; i < MEM_SIZE; i=i+1) begin
data[i] = 0;
end
for(i = 0; i < 512; i=i+1) begin
$dumpvars(0, data[i]);
end
for(i = 0; i < 9; i=i+1) begin
$dumpvars(0, bytes[i]);
end
$readmemh(`MemFile, data);
end
integer cur_count;
integer next_count;
integer cur_disp;
integer next_disp;
integer index;
wire[31:0] addr;
wire[3:0] mask;
assign addr = {bytes[3], bytes[2], bytes[1], bytes[0]};
assign mask = bytes[4][3:0];
localparam FullDisp = 3;
integer idx;
always @ (*) begin
if(rst) begin
for(index = 0; index < 9; index=index+1)
bytes[index] = 0;
next_count <= 0;
next_disp <= 0;
uart_send_flag <= 0;
uart_recv_flag <= 0;
end else begin
uart_send_flag <= 0;
uart_recv_flag <= 0;
if(cur_count == 5 && bytes[4][7:4] == 4'b0000) begin
if(uart_sendable) begin
uart_send_flag <= 1;
uart_send_data <= data[addr+cur_disp];
if(cur_disp == FullDisp) begin
next_disp <= 0;
next_count <= 0;
$display("[memory_sim] cpu read request [%x], send data %x",
addr, {data[addr+3],data[addr+2],data[addr+1],data[addr]});
end else begin
next_disp <= cur_disp + 1;
next_count <= cur_count;
end
end else begin
next_disp <= cur_disp;
next_count <= cur_count;
end
end else if(cur_count == 9) begin
if(mask[0]) data[addr+0] <= bytes[5 + 0];
if(mask[1]) data[addr+1] <= bytes[5 + 1];
if(mask[2]) data[addr+2] <= bytes[5 + 2];
if(mask[3]) data[addr+3] <= bytes[5 + 3];
next_count <= 0;
next_disp <= 0;
if(addr == 32'h104 && mask[0]) begin
$display("*** %c ***", bytes[5]);
end
if(addr == 32'h108 && mask[0]) begin
$display("access %x, successfully exit", 32'h108);
$finish;
end
end else begin
if(uart_receivable) begin
uart_recv_flag <= 1;
bytes[cur_count] <= uart_recv_data;
next_count <= cur_count + 1;
next_disp <= 0;
end else begin
next_count <= cur_count;
next_disp <= 0;
end
end
end
end
always @ (posedge clk or posedge rst) begin
if(rst) begin
cur_count <= 0;
cur_disp <= 0;
end else begin
cur_count <= next_count;
cur_disp <= next_disp;
end
end
endmodule | 0 |
5,396 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v | 113,962,532 | midbuf.v | v | 178 | 61 | [] | [] | [] | [(204, 240), (242, 304), (306, 346), (348, 377)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] if_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:11: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] if_inst,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:18: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] id_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:19: Define or directive not defined: \'`InstWidth\'\n output reg[`InstWidth-1:0] id_inst\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:26: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_inst <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:29: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:30: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:31: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:32: Define or directive not defined: \'`NopInst\'\n id_inst <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:48: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] id_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:49: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] id_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:50: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:51: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:52: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] id_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:54: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:55: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:61: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] ex_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:62: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] ex_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:63: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:64: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:65: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:67: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:68: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:78: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: Define or directive not defined: \'`EXE_NOP_RES\'\n ex_alusel <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_alusel <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg1 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg2 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: Define or directive not defined: \'`ZeroRegAddr\'\n ex_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wreg <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: Define or directive not defined: \'`ZeroWord\'\n ex_addr_base <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_base <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: Define or directive not defined: \'`ZeroWord\'\n ex_addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: Define or directive not defined: \'`NoJump\'\n jump_type_o <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_o <= `NoJump;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: Define or directive not defined: \'`MEM_NOP\'\n memop_o <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n memop_o <= `MEM_NOP;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:89: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,158 | module | module if_id(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`MemAddrWidth-1:0] if_pc,
input wire[`InstWidth-1:0] if_inst,
input wire ex_jump,
input wire[1:0] idex_jump_type,
output reg[`MemAddrWidth-1:0] id_pc,
output reg[`InstWidth-1:0] id_inst
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if (!stall[1]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
id_pc <= `ZeroWord;
id_inst <= `NopInst;
end else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
end
endmodule | module if_id(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`MemAddrWidth-1:0] if_pc,
input wire[`InstWidth-1:0] if_inst,
input wire ex_jump,
input wire[1:0] idex_jump_type,
output reg[`MemAddrWidth-1:0] id_pc,
output reg[`InstWidth-1:0] id_inst
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if (!stall[1]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
id_pc <= `ZeroWord;
id_inst <= `NopInst;
end else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
end
endmodule | 0 |
5,397 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v | 113,962,532 | midbuf.v | v | 178 | 61 | [] | [] | [] | [(204, 240), (242, 304), (306, 346), (348, 377)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] if_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:11: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] if_inst,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:18: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] id_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:19: Define or directive not defined: \'`InstWidth\'\n output reg[`InstWidth-1:0] id_inst\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:26: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_inst <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:29: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:30: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:31: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:32: Define or directive not defined: \'`NopInst\'\n id_inst <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:48: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] id_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:49: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] id_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:50: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:51: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:52: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] id_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:54: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:55: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:61: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] ex_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:62: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] ex_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:63: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:64: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:65: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:67: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:68: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:78: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: Define or directive not defined: \'`EXE_NOP_RES\'\n ex_alusel <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_alusel <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg1 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg2 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: Define or directive not defined: \'`ZeroRegAddr\'\n ex_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wreg <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: Define or directive not defined: \'`ZeroWord\'\n ex_addr_base <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_base <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: Define or directive not defined: \'`ZeroWord\'\n ex_addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: Define or directive not defined: \'`NoJump\'\n jump_type_o <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_o <= `NoJump;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: Define or directive not defined: \'`MEM_NOP\'\n memop_o <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n memop_o <= `MEM_NOP;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:89: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,158 | module | module id_ex(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`AluOpWidth-1:0] id_aluop,
input wire[`AluSelWidth-1:0] id_alusel,
input wire[`RegDataWidth-1:0] id_reg1,
input wire[`RegDataWidth-1:0] id_reg2,
input wire[`RegAddrWidth-1:0] id_wd,
input wire id_wreg,
input wire[`RegDataWidth-1:0] id_addr_base,
input wire[`RegDataWidth-1:0] id_addr_off,
input wire[1:0] id_jump_type,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`AluOpWidth-1:0] ex_aluop,
output reg[`AluSelWidth-1:0] ex_alusel,
output reg[`RegDataWidth-1:0] ex_reg1,
output reg[`RegDataWidth-1:0] ex_reg2,
output reg[`RegAddrWidth-1:0] ex_wd,
output reg ex_wreg,
output reg[`RegDataWidth-1:0] ex_addr_base,
output reg[`RegDataWidth-1:0] ex_addr_off,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o,
output reg[1:0] jump_type_o
);
always @ (posedge clk)
begin
if(rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_NOP_RES;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `ZeroRegAddr;
ex_wreg <= `WriteDisable;
ex_addr_base <= `ZeroWord;
ex_addr_off <= `ZeroWord;
jump_type_o <= `NoJump;
memop_o <= `MEM_NOP;
memfunct_o <= 0;
end else if(!stall[2]) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_addr_base <= id_addr_base;
ex_addr_off <= id_addr_off;
jump_type_o <= id_jump_type;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
end
end
endmodule | module id_ex(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`AluOpWidth-1:0] id_aluop,
input wire[`AluSelWidth-1:0] id_alusel,
input wire[`RegDataWidth-1:0] id_reg1,
input wire[`RegDataWidth-1:0] id_reg2,
input wire[`RegAddrWidth-1:0] id_wd,
input wire id_wreg,
input wire[`RegDataWidth-1:0] id_addr_base,
input wire[`RegDataWidth-1:0] id_addr_off,
input wire[1:0] id_jump_type,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`AluOpWidth-1:0] ex_aluop,
output reg[`AluSelWidth-1:0] ex_alusel,
output reg[`RegDataWidth-1:0] ex_reg1,
output reg[`RegDataWidth-1:0] ex_reg2,
output reg[`RegAddrWidth-1:0] ex_wd,
output reg ex_wreg,
output reg[`RegDataWidth-1:0] ex_addr_base,
output reg[`RegDataWidth-1:0] ex_addr_off,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o,
output reg[1:0] jump_type_o
); |
always @ (posedge clk)
begin
if(rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_NOP_RES;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `ZeroRegAddr;
ex_wreg <= `WriteDisable;
ex_addr_base <= `ZeroWord;
ex_addr_off <= `ZeroWord;
jump_type_o <= `NoJump;
memop_o <= `MEM_NOP;
memfunct_o <= 0;
end else if(!stall[2]) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_addr_base <= id_addr_base;
ex_addr_off <= id_addr_off;
jump_type_o <= id_jump_type;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
end
end
endmodule | 0 |
5,398 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v | 113,962,532 | midbuf.v | v | 178 | 61 | [] | [] | [] | [(204, 240), (242, 304), (306, 346), (348, 377)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] if_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:11: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] if_inst,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:18: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] id_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:19: Define or directive not defined: \'`InstWidth\'\n output reg[`InstWidth-1:0] id_inst\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:26: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_inst <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:29: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:30: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:31: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:32: Define or directive not defined: \'`NopInst\'\n id_inst <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:48: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] id_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:49: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] id_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:50: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:51: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:52: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] id_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:54: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:55: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:61: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] ex_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:62: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] ex_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:63: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:64: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:65: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:67: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:68: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:78: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: Define or directive not defined: \'`EXE_NOP_RES\'\n ex_alusel <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_alusel <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg1 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg2 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: Define or directive not defined: \'`ZeroRegAddr\'\n ex_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wreg <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: Define or directive not defined: \'`ZeroWord\'\n ex_addr_base <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_base <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: Define or directive not defined: \'`ZeroWord\'\n ex_addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: Define or directive not defined: \'`NoJump\'\n jump_type_o <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_o <= `NoJump;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: Define or directive not defined: \'`MEM_NOP\'\n memop_o <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n memop_o <= `MEM_NOP;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:89: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,158 | module | module ex_mem(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] ex_wdata,
input wire[`RegAddrWidth-1:0] ex_wd,
input wire ex_wreg,
input wire[`MemAddrWidth-1:0] ex_addr,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`RegDataWidth-1:0] mem_wdata,
output reg[`RegAddrWidth-1:0] mem_wd,
output reg mem_wreg,
output reg[`MemAddrWidth-1:0] mem_addr,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o
);
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
mem_wdata <= `ZeroWord;
mem_wd <= `ZeroRegAddr;
mem_wreg <= `WriteDisable;
mem_addr <= `ZeroWord;
memop_o <= 0;
memfunct_o <= 0;
end else if (!stall[3]) begin
mem_wdata <= ex_wdata;
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_addr <= ex_addr;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
end
end
endmodule | module ex_mem(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] ex_wdata,
input wire[`RegAddrWidth-1:0] ex_wd,
input wire ex_wreg,
input wire[`MemAddrWidth-1:0] ex_addr,
input wire[1:0] memop_i,
input wire[2:0] memfunct_i,
output reg[`RegDataWidth-1:0] mem_wdata,
output reg[`RegAddrWidth-1:0] mem_wd,
output reg mem_wreg,
output reg[`MemAddrWidth-1:0] mem_addr,
output reg[1:0] memop_o,
output reg[2:0] memfunct_o
); |
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
mem_wdata <= `ZeroWord;
mem_wd <= `ZeroRegAddr;
mem_wreg <= `WriteDisable;
mem_addr <= `ZeroWord;
memop_o <= 0;
memfunct_o <= 0;
end else if (!stall[3]) begin
mem_wdata <= ex_wdata;
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
mem_addr <= ex_addr;
memop_o <= memop_i;
memfunct_o <= memfunct_i;
end
end
endmodule | 0 |
5,399 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v | 113,962,532 | midbuf.v | v | 178 | 61 | [] | [] | [] | [(204, 240), (242, 304), (306, 346), (348, 377)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] if_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:11: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] if_inst,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:18: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] id_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:19: Define or directive not defined: \'`InstWidth\'\n output reg[`InstWidth-1:0] id_inst\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:26: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_inst <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:29: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:30: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:31: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:32: Define or directive not defined: \'`NopInst\'\n id_inst <= `NopInst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:48: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] id_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:49: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] id_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:50: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:51: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:52: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] id_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:54: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:55: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:61: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] ex_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:62: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] ex_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:63: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:64: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:65: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:67: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:68: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:78: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: Define or directive not defined: \'`EXE_NOP_RES\'\n ex_alusel <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_alusel <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg1 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg2 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: Define or directive not defined: \'`ZeroRegAddr\'\n ex_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wreg <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: Define or directive not defined: \'`ZeroWord\'\n ex_addr_base <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_base <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: Define or directive not defined: \'`ZeroWord\'\n ex_addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:85: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: Define or directive not defined: \'`NoJump\'\n jump_type_o <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_o <= `NoJump;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: Define or directive not defined: \'`MEM_NOP\'\n memop_o <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n memop_o <= `MEM_NOP;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/midbuf.v:89: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,158 | module | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] mem_wdata,
input wire[`RegAddrWidth-1:0] mem_wd,
input wire mem_wreg,
output reg[`RegDataWidth-1:0] wb_wdata,
output reg[`RegAddrWidth-1:0] wb_wd,
output reg wb_wreg
);
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
wb_wdata <= `ZeroWord;
wb_wd <= `ZeroRegAddr;
wb_wreg <= `WriteDisable;
end else if(!stall[4]) begin
wb_wdata <= mem_wdata;
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
end
end
endmodule | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] mem_wdata,
input wire[`RegAddrWidth-1:0] mem_wd,
input wire mem_wreg,
output reg[`RegDataWidth-1:0] wb_wdata,
output reg[`RegAddrWidth-1:0] wb_wd,
output reg wb_wreg
); |
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
wb_wdata <= `ZeroWord;
wb_wd <= `ZeroRegAddr;
wb_wreg <= `WriteDisable;
end else if(!stall[4]) begin
wb_wdata <= mem_wdata;
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
end
end
endmodule | 0 |
5,400 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v | 113,962,532 | pc_reg.v | v | 38 | 57 | [] | [] | [] | [(204, 237)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:12: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] ex_addr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:15: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:21: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) \n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:23: Define or directive not defined: \'`ChipDisable\'\n ce <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:25: syntax error, unexpected else\n end else if (!stall[0]) begin\n ^~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:26: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:27: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:28: Define or directive not defined: \'`ChipEnable\'\n ce <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/pc_reg.v:31: Define or directive not defined: \'`ChipEnable\'\n ce <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 6,160 | module | module pc_reg(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire ex_jump,
input wire[1:0] idex_jump_type,
input wire[`MemAddrWidth-1:0] ex_addr,
output reg[`MemAddrWidth-1:0] pc,
output reg ce
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ce <= `ChipDisable;
pc <= 32'hFFFFFFFC;
end else if (!stall[0]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
ce <= `ChipEnable;
pc <= ex_addr;
end else begin
ce <= `ChipEnable;
pc <= pc + 4'h4;
end
end
end
endmodule | module pc_reg(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire ex_jump,
input wire[1:0] idex_jump_type,
input wire[`MemAddrWidth-1:0] ex_addr,
output reg[`MemAddrWidth-1:0] pc,
output reg ce
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
ce <= `ChipDisable;
pc <= 32'hFFFFFFFC;
end else if (!stall[0]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
ce <= `ChipEnable;
pc <= ex_addr;
end else begin
ce <= `ChipEnable;
pc <= pc + 4'h4;
end
end
end
endmodule | 0 |
5,401 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v | 113,962,532 | regfile.v | v | 79 | 67 | [] | [] | [] | [(205, 278)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:12: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] waddr,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:13: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] wdata,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:17: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] raddr1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:18: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] rdata1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:22: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] raddr2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:23: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] rdata2\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:26: Define or directive not defined: \'`RegDataWidth\'\n reg[`RegDataWidth-1:0] regs[0:`RegNum-1];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:26: Define or directive not defined: \'`RegNum\'\n reg[`RegDataWidth-1:0] regs[0:`RegNum-1];\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: Define or directive not defined: \'`RegNum\'\n for(i = 0; i < `RegNum; i=i+1) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for(i = 0; i < `RegNum; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:30: syntax error, unexpected \')\', expecting \';\'\n for(i = 0; i < `RegNum; i=i+1) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:31: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, regs[i]);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:38: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:41: Define or directive not defined: \'`WriteEnable\'\n if (we == `WriteEnable && waddr != `ZeroRegAddr) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:41: Define or directive not defined: \'`ZeroRegAddr\'\n if (we == `WriteEnable && waddr != `ZeroRegAddr) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:50: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:51: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:52: Define or directive not defined: \'`ReadDisable\'\n end else if (re1 == `ReadDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:53: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:54: Define or directive not defined: \'`ZeroRegAddr\'\n end else if (raddr1 == `ZeroRegAddr) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:55: Define or directive not defined: \'`ZeroWord\'\n rdata1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:56: Define or directive not defined: \'`WriteEnable\'\n end else if (raddr1 == waddr && we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:66: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:67: Define or directive not defined: \'`ZeroWord\'\n rdata2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:68: Define or directive not defined: \'`ReadDisable\'\n end else if (re2 == `ReadDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:69: Define or directive not defined: \'`ZeroWord\'\n rdata2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:70: Define or directive not defined: \'`ZeroRegAddr\'\n end else if (raddr2 == `ZeroRegAddr) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:71: Define or directive not defined: \'`ZeroWord\'\n rdata2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/regfile.v:72: Define or directive not defined: \'`WriteEnable\'\n end else if (raddr2 == waddr && we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: Cannot continue\n' | 6,161 | module | module regfile(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire we,
input wire[`RegAddrWidth-1:0] waddr,
input wire[`RegDataWidth-1:0] wdata,
input wire re1,
input wire[`RegAddrWidth-1:0] raddr1,
output reg[`RegDataWidth-1:0] rdata1,
input wire re2,
input wire[`RegAddrWidth-1:0] raddr2,
output reg[`RegDataWidth-1:0] rdata2
);
reg[`RegDataWidth-1:0] regs[0:`RegNum-1];
integer i;
initial begin
for(i = 0; i < `RegNum; i=i+1) begin
$dumpvars(0, regs[i]);
end
end
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
end else if(!stall[5]) begin
if (we == `WriteEnable && waddr != `ZeroRegAddr) begin
regs[waddr] <= wdata;
end
end
end
always @(*)
begin
if (rst == `RstEnable) begin
rdata1 <= `ZeroWord;
end else if (re1 == `ReadDisable) begin
rdata1 <= `ZeroWord;
end else if (raddr1 == `ZeroRegAddr) begin
rdata1 <= `ZeroWord;
end else if (raddr1 == waddr && we == `WriteEnable) begin
rdata1 <= wdata;
end else begin
rdata1 <= regs[raddr1];
end
end
always @(*)
begin
if (rst == `RstEnable) begin
rdata2 <= `ZeroWord;
end else if (re2 == `ReadDisable) begin
rdata2 <= `ZeroWord;
end else if (raddr2 == `ZeroRegAddr) begin
rdata2 <= `ZeroWord;
end else if (raddr2 == waddr && we == `WriteEnable) begin
rdata2 <= wdata;
end else begin
rdata2 <= regs[raddr2];
end
end
endmodule | module regfile(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire we,
input wire[`RegAddrWidth-1:0] waddr,
input wire[`RegDataWidth-1:0] wdata,
input wire re1,
input wire[`RegAddrWidth-1:0] raddr1,
output reg[`RegDataWidth-1:0] rdata1,
input wire re2,
input wire[`RegAddrWidth-1:0] raddr2,
output reg[`RegDataWidth-1:0] rdata2
); |
reg[`RegDataWidth-1:0] regs[0:`RegNum-1];
integer i;
initial begin
for(i = 0; i < `RegNum; i=i+1) begin
$dumpvars(0, regs[i]);
end
end
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
end else if(!stall[5]) begin
if (we == `WriteEnable && waddr != `ZeroRegAddr) begin
regs[waddr] <= wdata;
end
end
end
always @(*)
begin
if (rst == `RstEnable) begin
rdata1 <= `ZeroWord;
end else if (re1 == `ReadDisable) begin
rdata1 <= `ZeroWord;
end else if (raddr1 == `ZeroRegAddr) begin
rdata1 <= `ZeroWord;
end else if (raddr1 == waddr && we == `WriteEnable) begin
rdata1 <= wdata;
end else begin
rdata1 <= regs[raddr1];
end
end
always @(*)
begin
if (rst == `RstEnable) begin
rdata2 <= `ZeroWord;
end else if (re2 == `ReadDisable) begin
rdata2 <= `ZeroWord;
end else if (raddr2 == `ZeroRegAddr) begin
rdata2 <= `ZeroWord;
end else if (raddr2 == waddr && we == `WriteEnable) begin
rdata2 <= wdata;
end else begin
rdata2 <= regs[raddr2];
end
end
endmodule | 0 |
5,402 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v | 113,962,532 | risc32i.v | v | 303 | 48 | [] | [] | [] | [(205, 502)] | null | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:14: Define or directive not defined: \'`MemAddrWidth\'\n wire[`MemAddrWidth-1:0] pcreg_pc;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:18: Define or directive not defined: \'`MemAddrWidth\'\n wire[`MemAddrWidth-1:0] ifid_pc;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:19: Define or directive not defined: \'`InstWidth\'\n wire[`InstWidth-1:0] ifid_inst;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:24: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] id_reg1_addr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:25: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] id_reg2_addr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:26: Define or directive not defined: \'`AluOpWidth\'\n wire[`AluOpWidth-1:0] id_aluop;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:27: Define or directive not defined: \'`AluSelWidth\'\n wire[`AluSelWidth-1:0] id_alusel;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:28: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] id_reg1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:29: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] id_reg2;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:30: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] id_wd;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:32: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] id_addr_base;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:33: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] id_addr_off;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:40: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] reg_reg1_data;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:41: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] reg_reg2_data; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:44: Define or directive not defined: \'`AluOpWidth\'\n wire[`AluOpWidth-1:0] idex_aluop;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:45: Define or directive not defined: \'`AluSelWidth\'\n wire[`AluSelWidth-1:0] idex_alusel;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:46: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] idex_reg1; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:47: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] idex_reg2; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:48: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] idex_wd; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:50: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] idex_addr_base;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:51: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] idex_addr_off;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:57: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] ex_wdata; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:58: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] ex_wd; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:60: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] ex_addr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:65: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] exmem_wdata; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:66: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] exmem_wd; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:68: Define or directive not defined: \'`MemAddrWidth\'\n wire[`MemAddrWidth-1:0] exmem_addr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:75: Define or directive not defined: \'`MemAddrWidth\'\n wire[`MemAddrWidth-1:0] mem_data_addr;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:76: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] mem_write_data_value;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:77: Define or directive not defined: \'`RegDataBytes\'\n wire[`RegDataBytes-1:0] mem_write_data_mask;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:78: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] mem_wdata; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:79: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] mem_wd; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:83: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] memwb_wdata; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:84: Define or directive not defined: \'`RegAddrWidth\'\n wire[`RegAddrWidth-1:0] memwb_wd; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:91: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] cache_inst_value;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/risc32i.v:92: Define or directive not defined: \'`RegDataWidth\'\n wire[`RegDataWidth-1:0] cache_read_data_value;\n ^~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n' | 6,162 | module | module risc32i(
input wire clk,
input wire rst,
output Tx,
input Rx
);
wire[`MemAddrWidth-1:0] pcreg_pc;
wire pcreg_ce;
wire[`MemAddrWidth-1:0] ifid_pc;
wire[`InstWidth-1:0] ifid_inst;
wire id_reg1_read;
wire id_reg2_read;
wire[`RegAddrWidth-1:0] id_reg1_addr;
wire[`RegAddrWidth-1:0] id_reg2_addr;
wire[`AluOpWidth-1:0] id_aluop;
wire[`AluSelWidth-1:0] id_alusel;
wire[`RegDataWidth-1:0] id_reg1;
wire[`RegDataWidth-1:0] id_reg2;
wire[`RegAddrWidth-1:0] id_wd;
wire id_wreg;
wire[`RegDataWidth-1:0] id_addr_base;
wire[`RegDataWidth-1:0] id_addr_off;
wire[1:0] id_jump_type;
wire[1:0] id_memop;
wire[2:0] id_memfunct;
wire id_stallreq;
wire[`RegDataWidth-1:0] reg_reg1_data;
wire[`RegDataWidth-1:0] reg_reg2_data;
wire[`AluOpWidth-1:0] idex_aluop;
wire[`AluSelWidth-1:0] idex_alusel;
wire[`RegDataWidth-1:0] idex_reg1;
wire[`RegDataWidth-1:0] idex_reg2;
wire[`RegAddrWidth-1:0] idex_wd;
wire idex_wreg;
wire[`RegDataWidth-1:0] idex_addr_base;
wire[`RegDataWidth-1:0] idex_addr_off;
wire[1:0] idex_memop;
wire[2:0] idex_memfunct;
wire[1:0] idex_jump_type;
wire[`RegDataWidth-1:0] ex_wdata;
wire[`RegAddrWidth-1:0] ex_wd;
wire ex_wreg;
wire[`RegDataWidth-1:0] ex_addr;
wire[1:0] ex_memop;
wire[2:0] ex_memfunct;
wire[`RegDataWidth-1:0] exmem_wdata;
wire[`RegAddrWidth-1:0] exmem_wd;
wire exmem_wreg;
wire[`MemAddrWidth-1:0] exmem_addr;
wire[1:0] exmem_memop;
wire[2:0] exmem_memfunct;
wire mem_data_ce;
wire mem_data_optype;
wire[`MemAddrWidth-1:0] mem_data_addr;
wire[`RegDataWidth-1:0] mem_write_data_value;
wire[`RegDataBytes-1:0] mem_write_data_mask;
wire[`RegDataWidth-1:0] mem_wdata;
wire[`RegAddrWidth-1:0] mem_wd;
wire mem_wreg;
wire[`RegDataWidth-1:0] memwb_wdata;
wire[`RegAddrWidth-1:0] memwb_wd;
wire memwb_wreg;
wire[5:0] ctrl_stall;
wire[`RegDataWidth-1:0] cache_inst_value;
wire[`RegDataWidth-1:0] cache_read_data_value;
wire cache_busy;
wire cache_Tx;
wire cache_Rx;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.ex_jump(ex_wdata[0]),
.idex_jump_type(idex_jump_type),
.ex_addr(ex_addr),
.pc(pcreg_pc),
.ce(pcreg_ce)
);
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.if_pc(pcreg_pc),
.if_inst(cache_inst_value),
.ex_jump(ex_wdata[0]),
.idex_jump_type(idex_jump_type),
.id_pc(ifid_pc),
.id_inst(ifid_inst)
);
id id0(
.rst(rst),
.pc_i(ifid_pc),
.inst_i(ifid_inst),
.reg1_data_i(reg_reg1_data),
.reg2_data_i(reg_reg2_data),
.mem_wdata_i(mem_wdata),
.mem_wd_i(mem_wd),
.mem_wreg_i(mem_wreg),
.jump_type_i(idex_jump_type),
.ex_memop_i(ex_memop),
.ex_wdata_i(ex_wdata),
.ex_wd_i(ex_wd),
.ex_wreg_i(ex_wreg),
.reg1_read_o(id_reg1_read),
.reg2_read_o(id_reg2_read),
.reg1_addr_o(id_reg1_addr),
.reg2_addr_o(id_reg2_addr),
.aluop_o(id_aluop),
.alusel_o(id_alusel),
.reg1_o(id_reg1),
.reg2_o(id_reg2),
.wd_o(id_wd),
.wreg_o(id_wreg),
.addr_base(id_addr_base),
.addr_off(id_addr_off),
.jump_type_o(id_jump_type),
.memop_o(id_memop),
.memfunct_o(id_memfunct),
.stall_req(id_stallreq)
);
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.id_aluop(id_aluop),
.id_alusel(id_alusel),
.id_reg1(id_reg1),
.id_reg2(id_reg2),
.id_wd(id_wd),
.id_wreg(id_wreg),
.id_addr_base(id_addr_base),
.id_addr_off(id_addr_off),
.id_jump_type(id_jump_type),
.memop_i(id_memop),
.memfunct_i(id_memfunct),
.ex_aluop(idex_aluop),
.ex_alusel(idex_alusel),
.ex_reg1(idex_reg1),
.ex_reg2(idex_reg2),
.ex_wd(idex_wd),
.ex_wreg(idex_wreg),
.ex_addr_base(idex_addr_base),
.ex_addr_off(idex_addr_off),
.memop_o(idex_memop),
.memfunct_o(idex_memfunct),
.jump_type_o(idex_jump_type)
);
ex ex0(
.rst(rst),
.aluop_i(idex_aluop),
.alusel_i(idex_alusel),
.reg1_i(idex_reg1),
.reg2_i(idex_reg2),
.wd_i(idex_wd),
.wreg_i(idex_wreg),
.addr_base(idex_addr_base),
.addr_off(idex_addr_off),
.jump_type_i(idex_jump_type),
.memop_i(idex_memop),
.memfunct_i(idex_memfunct),
.wdata_o(ex_wdata),
.wd_o(ex_wd),
.wreg_o(ex_wreg),
.addr_o(ex_addr),
.memop_o(ex_memop),
.memfunct_o(ex_memfunct)
);
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.ex_wdata(ex_wdata),
.ex_wd(ex_wd),
.ex_wreg(ex_wreg),
.ex_addr(ex_addr),
.memop_i(ex_memop),
.memfunct_i(ex_memfunct),
.mem_wdata(exmem_wdata),
.mem_wd(exmem_wd),
.mem_wreg(exmem_wreg),
.mem_addr(exmem_addr),
.memop_o(exmem_memop),
.memfunct_o(exmem_memfunct)
);
mem mem0(
.rst(rst),
.wdata_i(exmem_wdata),
.wd_i(exmem_wd),
.wreg_i(exmem_wreg),
.exmem_addr(exmem_addr),
.memop_i(exmem_memop),
.memfunct_i(exmem_memfunct),
.read_data_value(cache_read_data_value),
.data_ce(mem_data_ce),
.data_optype(mem_data_optype),
.data_addr(mem_data_addr),
.write_data_value(mem_write_data_value),
.write_data_mask(mem_write_data_mask),
.wdata_o(mem_wdata),
.wd_o(mem_wd),
.wreg_o(mem_wreg)
);
mem_wb mem_wb(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.mem_wdata(mem_wdata),
.mem_wd(mem_wd),
.mem_wreg(mem_wreg),
.wb_wdata(memwb_wdata),
.wb_wd(memwb_wd),
.wb_wreg(memwb_wreg)
);
regfile regfile0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.we(memwb_wreg),
.waddr(memwb_wd),
.wdata(memwb_wdata),
.re1(id_reg1_read),
.raddr1(id_reg1_addr),
.rdata1(reg_reg1_data),
.re2(id_reg2_read),
.raddr2(id_reg2_addr),
.rdata2(reg_reg2_data)
);
ctrl ctrl0(
.rst(rst),
.mem_busy(cache_busy),
.id_req(id_stallreq),
.stall(ctrl_stall)
);
cache cache0(
.clk(clk),
.rst(rst),
.inst_ce(pcreg_ce),
.data_ce(mem_data_ce),
.data_optype(mem_data_optype),
.inst_addr(pcreg_pc),
.data_addr(mem_data_addr),
.write_data_mask(mem_write_data_mask),
.write_data_value(mem_write_data_value),
.inst_value(cache_inst_value),
.read_data_value(cache_read_data_value),
.busy(cache_busy),
.Tx(Tx),
.Rx(Rx)
);
endmodule | module risc32i(
input wire clk,
input wire rst,
output Tx,
input Rx
); |
wire[`MemAddrWidth-1:0] pcreg_pc;
wire pcreg_ce;
wire[`MemAddrWidth-1:0] ifid_pc;
wire[`InstWidth-1:0] ifid_inst;
wire id_reg1_read;
wire id_reg2_read;
wire[`RegAddrWidth-1:0] id_reg1_addr;
wire[`RegAddrWidth-1:0] id_reg2_addr;
wire[`AluOpWidth-1:0] id_aluop;
wire[`AluSelWidth-1:0] id_alusel;
wire[`RegDataWidth-1:0] id_reg1;
wire[`RegDataWidth-1:0] id_reg2;
wire[`RegAddrWidth-1:0] id_wd;
wire id_wreg;
wire[`RegDataWidth-1:0] id_addr_base;
wire[`RegDataWidth-1:0] id_addr_off;
wire[1:0] id_jump_type;
wire[1:0] id_memop;
wire[2:0] id_memfunct;
wire id_stallreq;
wire[`RegDataWidth-1:0] reg_reg1_data;
wire[`RegDataWidth-1:0] reg_reg2_data;
wire[`AluOpWidth-1:0] idex_aluop;
wire[`AluSelWidth-1:0] idex_alusel;
wire[`RegDataWidth-1:0] idex_reg1;
wire[`RegDataWidth-1:0] idex_reg2;
wire[`RegAddrWidth-1:0] idex_wd;
wire idex_wreg;
wire[`RegDataWidth-1:0] idex_addr_base;
wire[`RegDataWidth-1:0] idex_addr_off;
wire[1:0] idex_memop;
wire[2:0] idex_memfunct;
wire[1:0] idex_jump_type;
wire[`RegDataWidth-1:0] ex_wdata;
wire[`RegAddrWidth-1:0] ex_wd;
wire ex_wreg;
wire[`RegDataWidth-1:0] ex_addr;
wire[1:0] ex_memop;
wire[2:0] ex_memfunct;
wire[`RegDataWidth-1:0] exmem_wdata;
wire[`RegAddrWidth-1:0] exmem_wd;
wire exmem_wreg;
wire[`MemAddrWidth-1:0] exmem_addr;
wire[1:0] exmem_memop;
wire[2:0] exmem_memfunct;
wire mem_data_ce;
wire mem_data_optype;
wire[`MemAddrWidth-1:0] mem_data_addr;
wire[`RegDataWidth-1:0] mem_write_data_value;
wire[`RegDataBytes-1:0] mem_write_data_mask;
wire[`RegDataWidth-1:0] mem_wdata;
wire[`RegAddrWidth-1:0] mem_wd;
wire mem_wreg;
wire[`RegDataWidth-1:0] memwb_wdata;
wire[`RegAddrWidth-1:0] memwb_wd;
wire memwb_wreg;
wire[5:0] ctrl_stall;
wire[`RegDataWidth-1:0] cache_inst_value;
wire[`RegDataWidth-1:0] cache_read_data_value;
wire cache_busy;
wire cache_Tx;
wire cache_Rx;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.ex_jump(ex_wdata[0]),
.idex_jump_type(idex_jump_type),
.ex_addr(ex_addr),
.pc(pcreg_pc),
.ce(pcreg_ce)
);
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.if_pc(pcreg_pc),
.if_inst(cache_inst_value),
.ex_jump(ex_wdata[0]),
.idex_jump_type(idex_jump_type),
.id_pc(ifid_pc),
.id_inst(ifid_inst)
);
id id0(
.rst(rst),
.pc_i(ifid_pc),
.inst_i(ifid_inst),
.reg1_data_i(reg_reg1_data),
.reg2_data_i(reg_reg2_data),
.mem_wdata_i(mem_wdata),
.mem_wd_i(mem_wd),
.mem_wreg_i(mem_wreg),
.jump_type_i(idex_jump_type),
.ex_memop_i(ex_memop),
.ex_wdata_i(ex_wdata),
.ex_wd_i(ex_wd),
.ex_wreg_i(ex_wreg),
.reg1_read_o(id_reg1_read),
.reg2_read_o(id_reg2_read),
.reg1_addr_o(id_reg1_addr),
.reg2_addr_o(id_reg2_addr),
.aluop_o(id_aluop),
.alusel_o(id_alusel),
.reg1_o(id_reg1),
.reg2_o(id_reg2),
.wd_o(id_wd),
.wreg_o(id_wreg),
.addr_base(id_addr_base),
.addr_off(id_addr_off),
.jump_type_o(id_jump_type),
.memop_o(id_memop),
.memfunct_o(id_memfunct),
.stall_req(id_stallreq)
);
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.id_aluop(id_aluop),
.id_alusel(id_alusel),
.id_reg1(id_reg1),
.id_reg2(id_reg2),
.id_wd(id_wd),
.id_wreg(id_wreg),
.id_addr_base(id_addr_base),
.id_addr_off(id_addr_off),
.id_jump_type(id_jump_type),
.memop_i(id_memop),
.memfunct_i(id_memfunct),
.ex_aluop(idex_aluop),
.ex_alusel(idex_alusel),
.ex_reg1(idex_reg1),
.ex_reg2(idex_reg2),
.ex_wd(idex_wd),
.ex_wreg(idex_wreg),
.ex_addr_base(idex_addr_base),
.ex_addr_off(idex_addr_off),
.memop_o(idex_memop),
.memfunct_o(idex_memfunct),
.jump_type_o(idex_jump_type)
);
ex ex0(
.rst(rst),
.aluop_i(idex_aluop),
.alusel_i(idex_alusel),
.reg1_i(idex_reg1),
.reg2_i(idex_reg2),
.wd_i(idex_wd),
.wreg_i(idex_wreg),
.addr_base(idex_addr_base),
.addr_off(idex_addr_off),
.jump_type_i(idex_jump_type),
.memop_i(idex_memop),
.memfunct_i(idex_memfunct),
.wdata_o(ex_wdata),
.wd_o(ex_wd),
.wreg_o(ex_wreg),
.addr_o(ex_addr),
.memop_o(ex_memop),
.memfunct_o(ex_memfunct)
);
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.ex_wdata(ex_wdata),
.ex_wd(ex_wd),
.ex_wreg(ex_wreg),
.ex_addr(ex_addr),
.memop_i(ex_memop),
.memfunct_i(ex_memfunct),
.mem_wdata(exmem_wdata),
.mem_wd(exmem_wd),
.mem_wreg(exmem_wreg),
.mem_addr(exmem_addr),
.memop_o(exmem_memop),
.memfunct_o(exmem_memfunct)
);
mem mem0(
.rst(rst),
.wdata_i(exmem_wdata),
.wd_i(exmem_wd),
.wreg_i(exmem_wreg),
.exmem_addr(exmem_addr),
.memop_i(exmem_memop),
.memfunct_i(exmem_memfunct),
.read_data_value(cache_read_data_value),
.data_ce(mem_data_ce),
.data_optype(mem_data_optype),
.data_addr(mem_data_addr),
.write_data_value(mem_write_data_value),
.write_data_mask(mem_write_data_mask),
.wdata_o(mem_wdata),
.wd_o(mem_wd),
.wreg_o(mem_wreg)
);
mem_wb mem_wb(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.mem_wdata(mem_wdata),
.mem_wd(mem_wd),
.mem_wreg(mem_wreg),
.wb_wdata(memwb_wdata),
.wb_wd(memwb_wd),
.wb_wreg(memwb_wreg)
);
regfile regfile0(
.clk(clk),
.rst(rst),
.stall(ctrl_stall),
.we(memwb_wreg),
.waddr(memwb_wd),
.wdata(memwb_wdata),
.re1(id_reg1_read),
.raddr1(id_reg1_addr),
.rdata1(reg_reg1_data),
.re2(id_reg2_read),
.raddr2(id_reg2_addr),
.rdata2(reg_reg2_data)
);
ctrl ctrl0(
.rst(rst),
.mem_busy(cache_busy),
.id_req(id_stallreq),
.stall(ctrl_stall)
);
cache cache0(
.clk(clk),
.rst(rst),
.inst_ce(pcreg_ce),
.data_ce(mem_data_ce),
.data_optype(mem_data_optype),
.inst_addr(pcreg_pc),
.data_addr(mem_data_addr),
.write_data_mask(mem_write_data_mask),
.write_data_value(mem_write_data_value),
.inst_value(cache_inst_value),
.read_data_value(cache_read_data_value),
.busy(cache_busy),
.Tx(Tx),
.Rx(Rx)
);
endmodule | 0 |
5,403 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v | 113,962,532 | sim.v | v | 31 | 40 | [] | [] | [] | null | line:227: before: "$" | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:15: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:20: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clk = !clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:26: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sim.v:27: Unsupported: Ignoring delay on this delayed statement.\n#700000 $finish;\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n' | 6,163 | module | module sim();
reg clk;
reg rst;
wire Tx;
wire Rx;
cpu cpu0(clk,rst,Tx,Rx);
memory_sim memory_sim0(clk,rst,Rx,Tx);
initial begin
$dumpvars(0);
end
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
rst = 0;
rst = 1;
#100 rst = 0;
#700000 $finish;
end
endmodule | module sim(); |
reg clk;
reg rst;
wire Tx;
wire Rx;
cpu cpu0(clk,rst,Tx,Rx);
memory_sim memory_sim0(clk,rst,Rx,Tx);
initial begin
$dumpvars(0);
end
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
rst = 0;
rst = 1;
#100 rst = 0;
#700000 $finish;
end
endmodule | 0 |
5,404 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v | 113,962,532 | sopc_tb.v | v | 25 | 42 | [] | [] | [] | null | line:217: before: "$" | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:15: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:16: Define or directive not defined: \'`RstDisable\'\n #195 rst = `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/sopc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #500000 $finish;\n ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n' | 6,164 | module | module sopc_tb();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
$dumpvars;
rst = `RstEnable;
#195 rst = `RstDisable;
#500000 $finish;
end
sopc sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | module sopc_tb(); |
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
$dumpvars;
rst = `RstEnable;
#195 rst = `RstDisable;
#500000 $finish;
end
sopc sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | 0 |
5,405 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v | 113,962,532 | sopc.v | v | 117 | 80 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:45: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 <= ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:56: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, data[idx]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:59: Unsupported: Ignoring delay on this delayed statement.\n# 100 rst <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:60: Unsupported: Ignoring delay on this delayed statement.\n# 100000 $finish;\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,167 | module | module grap(
output Tx,
input Rx
);
uart_comm uart0(.Tx(Tx), .Rx(Rx));
endmodule | module grap(
output Tx,
input Rx
); |
uart_comm uart0(.Tx(Tx), .Rx(Rx));
endmodule | 0 |
5,406 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v | 113,962,532 | sopc.v | v | 117 | 80 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:45: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 <= ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:53: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:56: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, data[idx]);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:59: Unsupported: Ignoring delay on this delayed statement.\n# 100 rst <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/experiment/sopc.v:60: Unsupported: Ignoring delay on this delayed statement.\n# 100000 $finish;\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,167 | module | module sopc();
reg clk1, rst1;
reg send_flag1, recv_flag1;
reg[7:0] send_data1;
wire[7:0] recv_data1;
wire receivable1, sendable1;
reg clk2, rst2;
reg send_flag2, recv_flag2;
reg[7:0] send_data2;
wire[7:0] recv_data2;
wire receivable2, sendable2;
wire t1_r2, r1_t2;
uart_comm agent1(clk1, rst1, send_flag1, send_data1, recv_flag1, recv_data1,
sendable1, receivable1, t1_r2, r1_t2
);
grap grap0( r1_t2, t1_r2);
reg clk, rst;
reg CLOCK_50;
always @(*) begin
clk = CLOCK_50;
clk1 = clk;
clk2 = clk;
rst1 = rst;
rst2 = rst;
end
initial begin
CLOCK_50 <= 1'b0;
forever #10 CLOCK_50 <= ~CLOCK_50;
end
reg[7:0] idx;
reg[7:0] data[0:255];
reg[7:0] current;
initial begin
rst <= 1'b1;
$dumpvars(0);
for(idx = 0; idx < 128; idx=idx+1) begin
data[idx] <= idx;
$dumpvars(0, data[idx]);
end
current <= 9'b0;
# 100 rst <= 1'b0;
# 100000 $finish;
end
initial begin
end
always @ (*) begin
if(rst) begin
send_flag1 <= 1'b0;
send_data1 <= 8'b0;
recv_flag1 <= 1'b0;
end else begin
if(sendable1) begin
send_flag1 <= 1'b1;
send_data1 <= data[current[7:0]];
end else begin
send_flag1 <= 1'b0;
send_data1 <= 8'b0;
end
recv_flag1 <= 1'b0;
end
end
always @ (posedge clk1) begin
if (rst) begin
current <= 8'b0;
end else begin
if (sendable1) begin
if(current[8]) begin
current <= 8'b0;
end else begin
current <= current + 1;
end
end
end
end
reg[7:0] recevied_data;
always @ (*) begin
if(rst) begin
send_flag2 <= 1'b0;
send_data2 <= 8'b0;
recv_flag2 <= 1'b0;
end else begin
if(receivable2) begin
recv_flag2 <= 1'b1;
recevied_data <= recv_data2;
end else begin
recv_flag2 <= 1'b0;
recevied_data <= 8'b0;
end
send_flag2 <= 1'b0;
send_data2 <= 8'b0;
end
end
endmodule | module sopc(); |
reg clk1, rst1;
reg send_flag1, recv_flag1;
reg[7:0] send_data1;
wire[7:0] recv_data1;
wire receivable1, sendable1;
reg clk2, rst2;
reg send_flag2, recv_flag2;
reg[7:0] send_data2;
wire[7:0] recv_data2;
wire receivable2, sendable2;
wire t1_r2, r1_t2;
uart_comm agent1(clk1, rst1, send_flag1, send_data1, recv_flag1, recv_data1,
sendable1, receivable1, t1_r2, r1_t2
);
grap grap0( r1_t2, t1_r2);
reg clk, rst;
reg CLOCK_50;
always @(*) begin
clk = CLOCK_50;
clk1 = clk;
clk2 = clk;
rst1 = rst;
rst2 = rst;
end
initial begin
CLOCK_50 <= 1'b0;
forever #10 CLOCK_50 <= ~CLOCK_50;
end
reg[7:0] idx;
reg[7:0] data[0:255];
reg[7:0] current;
initial begin
rst <= 1'b1;
$dumpvars(0);
for(idx = 0; idx < 128; idx=idx+1) begin
data[idx] <= idx;
$dumpvars(0, data[idx]);
end
current <= 9'b0;
# 100 rst <= 1'b0;
# 100000 $finish;
end
initial begin
end
always @ (*) begin
if(rst) begin
send_flag1 <= 1'b0;
send_data1 <= 8'b0;
recv_flag1 <= 1'b0;
end else begin
if(sendable1) begin
send_flag1 <= 1'b1;
send_data1 <= data[current[7:0]];
end else begin
send_flag1 <= 1'b0;
send_data1 <= 8'b0;
end
recv_flag1 <= 1'b0;
end
end
always @ (posedge clk1) begin
if (rst) begin
current <= 8'b0;
end else begin
if (sendable1) begin
if(current[8]) begin
current <= 8'b0;
end else begin
current <= current + 1;
end
end
end
end
reg[7:0] recevied_data;
always @ (*) begin
if(rst) begin
send_flag2 <= 1'b0;
send_data2 <= 8'b0;
recv_flag2 <= 1'b0;
end else begin
if(receivable2) begin
recv_flag2 <= 1'b1;
recevied_data <= recv_data2;
end else begin
recv_flag2 <= 1'b0;
recevied_data <= 8'b0;
end
send_flag2 <= 1'b0;
send_data2 <= 8'b0;
end
end
endmodule | 0 |
5,407 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v | 113,962,532 | memory_ctrl.v | v | 152 | 89 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:10: Define or directive not defined: \'`BlockAddrWidth\'\n input wire[`BlockAddrWidth-1:0] addr, \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:11: Define or directive not defined: \'`BlockWidth\'\n input wire[`BlockWidth-1:0] write_data, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:12: Define or directive not defined: \'`BlockWidth\'\n output reg[`BlockWidth-1:0] read_data, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:19: Define or directive not defined: \'`BlockWidth\'\n reg[`BlockWidth-1:0] next_read_data;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:24: Define or directive not defined: \'`CacheDispWidth\'\n reg[`CacheDispWidth-1:0] data_disp;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:28: Define or directive not defined: \'`CacheDispWidth\'\n reg[`CacheDispWidth-1:0] next_data_disp;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:43: Define or directive not defined: \'`NotBusy\'\n if(rst || !ce || busy == `NotBusy) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst || !ce || busy == `NotBusy) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:44: Define or directive not defined: \'`ZeroWord\'\n opaddr <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:46: Define or directive not defined: \'`MemRead\'\n if(optype == `MemRead) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:47: Define or directive not defined: \'`ReadOpHead\'\n opaddr <= {`ReadOpHead, addr};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:49: Define or directive not defined: \'`WriteOpHead\'\n opaddr <= {`WriteOpHead, addr};\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:55: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:56: Define or directive not defined: \'`ZeroByte\'\n uart_send_data <= `ZeroByte;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:57: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:58: Define or directive not defined: \'`NotBusy\'\n next_busy <= `NotBusy;\n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:59: Define or directive not defined: \'`ZeroBlock\'\n next_read_data <= `ZeroBlock;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:61: Define or directive not defined: \'`ZeroHeadDisp\'\n next_head_disp <= `ZeroHeadDisp;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:62: Define or directive not defined: \'`ZeroDataDisp\'\n next_data_disp <= `ZeroDataDisp;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:63: Define or directive not defined: \'`NotBusy\'\n end else if(busy == `NotBusy) begin \n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:64: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:65: Define or directive not defined: \'`ZeroByte\'\n uart_send_data <= `ZeroByte;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:66: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:74: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:75: Define or directive not defined: \'`ZeroByte\'\n uart_send_data <= `ZeroByte;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:76: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:83: Define or directive not defined: \'`MemRead\'\n if(optype == `MemRead) begin \n ^~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(optype == `MemRead) begin \n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:84: Define or directive not defined: \'`TransAddr\'\n if(trans_status == `TransAddr) begin \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:86: Define or directive not defined: \'`SendEnable\'\n uart_send_flag <= `SendEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:88: syntax error, unexpected \'[\', expecting IDENTIFIER\n uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:90: syntax error, unexpected <=, expecting IDENTIFIER\n uart_recv_flag <= `RecvDisable;\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:90: Define or directive not defined: \'`RecvDisable\'\n uart_recv_flag <= `RecvDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:91: Define or directive not defined: \'`IsBusy\'\n next_busy <= `IsBusy;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:92: Define or directive not defined: \'`ZeroBlock\'\n next_read_data <= `ZeroBlock;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`FullHeadDisp\'\n next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`TransData\'\n next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:93: Define or directive not defined: \'`TransAddr\'\n next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:95: Define or directive not defined: \'`ZeroDataDisp\'\n next_data_disp <= `ZeroDataDisp;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:99: Define or directive not defined: \'`SendDisable\'\n uart_send_flag <= `SendDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:100: Define or directive not defined: \'`ZeroByte\'\n uart_send_data <= `ZeroByte;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:101: Define or directive not defined: \'`RecvEnable\'\n uart_recv_flag <= `RecvEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:102: Define or directive not defined: \'`FullDataDisp\'\n next_busy <= (data_disp != `FullDataDisp);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: syntax error, unexpected <=, expecting IDENTIFIER\n next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n ^~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`FullDataDisp\'\n next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`TransAddr\'\n next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:107: Define or directive not defined: \'`TransData\'\n next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/goodbye/memory_ctrl.v:108: Define or directive not defined: \'`ZeroHeadDisp\'\n next_head_disp <= `ZeroHeadDisp;\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,169 | module | module memory_ctrl(
input wire clk,
input wire rst,
input wire ce,
input wire optype,
input wire[`BlockAddrWidth-1:0] addr,
input wire[`BlockWidth-1:0] write_data,
output reg[`BlockWidth-1:0] read_data,
output reg busy,
output wire Tx,
input Rx
);
reg[`BlockWidth-1:0] next_read_data;
reg next_busy;
reg trans_status;
reg[1:0] head_disp;
reg[`CacheDispWidth-1:0] data_disp;
reg next_trans_status;
reg[1:0] next_head_disp;
reg[`CacheDispWidth-1:0] next_data_disp;
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag,
uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);
integer idx;
reg[31:0] opaddr;
always @ (*) begin
if(rst || !ce || busy == `NotBusy) begin
opaddr <= `ZeroWord;
end else begin
if(optype == `MemRead) begin
opaddr <= {`ReadOpHead, addr};
end else begin
opaddr <= {`WriteOpHead, addr};
end
end
end
always @ (*) begin
if(rst || !ce) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= `NotBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= 1'b0;
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= `ZeroDataDisp;
end else if(busy == `NotBusy) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= busy;
next_read_data <= read_data;
next_trans_status <= trans_status;
next_head_disp <= head_disp;
next_data_disp <= data_disp;
end else begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= busy;
next_read_data <= read_data;
next_trans_status <= trans_status;
next_head_disp <= head_disp;
next_data_disp <= data_disp;
if(optype == `MemRead) begin
if(trans_status == `TransAddr) begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= `IsBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
next_head_disp <= head_disp + 1;
next_data_disp <= `ZeroDataDisp;
end
end else begin
if(uart_receivable) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvEnable;
next_busy <= (data_disp != `FullDataDisp);
next_read_data <= read_data;
for(idx = 0; idx < 8; idx=idx+1) begin
next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];
end
next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= data_disp + 1;
end
end
end else begin
if(trans_status == `TransAddr) begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= `IsBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
next_head_disp <= head_disp + 1;
next_data_disp <= `ZeroDataDisp;
end
end else begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= write_data[{data_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= (data_disp != `FullDataDisp);
next_read_data <= `ZeroBlock;
next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= data_disp + 1;
end
end
end
end
end
always @ (posedge clk) begin
busy <= next_busy;
read_data <= next_read_data;
trans_status <= next_trans_status;
head_disp <= next_head_disp;
data_disp <= next_data_disp;
end
endmodule | module memory_ctrl(
input wire clk,
input wire rst,
input wire ce,
input wire optype,
input wire[`BlockAddrWidth-1:0] addr,
input wire[`BlockWidth-1:0] write_data,
output reg[`BlockWidth-1:0] read_data,
output reg busy,
output wire Tx,
input Rx
); |
reg[`BlockWidth-1:0] next_read_data;
reg next_busy;
reg trans_status;
reg[1:0] head_disp;
reg[`CacheDispWidth-1:0] data_disp;
reg next_trans_status;
reg[1:0] next_head_disp;
reg[`CacheDispWidth-1:0] next_data_disp;
reg uart_send_flag, uart_recv_flag;
reg[7:0] uart_send_data;
wire[7:0] uart_recv_data;
wire uart_receivable, uart_sendable;
uart_comm uart0( clk, rst, uart_send_flag, uart_send_data, uart_recv_flag,
uart_recv_data, uart_sendable, uart_receivable, Tx, Rx);
integer idx;
reg[31:0] opaddr;
always @ (*) begin
if(rst || !ce || busy == `NotBusy) begin
opaddr <= `ZeroWord;
end else begin
if(optype == `MemRead) begin
opaddr <= {`ReadOpHead, addr};
end else begin
opaddr <= {`WriteOpHead, addr};
end
end
end
always @ (*) begin
if(rst || !ce) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= `NotBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= 1'b0;
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= `ZeroDataDisp;
end else if(busy == `NotBusy) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= busy;
next_read_data <= read_data;
next_trans_status <= trans_status;
next_head_disp <= head_disp;
next_data_disp <= data_disp;
end else begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvDisable;
next_busy <= busy;
next_read_data <= read_data;
next_trans_status <= trans_status;
next_head_disp <= head_disp;
next_data_disp <= data_disp;
if(optype == `MemRead) begin
if(trans_status == `TransAddr) begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= `IsBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
next_head_disp <= head_disp + 1;
next_data_disp <= `ZeroDataDisp;
end
end else begin
if(uart_receivable) begin
uart_send_flag <= `SendDisable;
uart_send_data <= `ZeroByte;
uart_recv_flag <= `RecvEnable;
next_busy <= (data_disp != `FullDataDisp);
next_read_data <= read_data;
for(idx = 0; idx < 8; idx=idx+1) begin
next_read_data[{data_disp,idx[2:0]}] <= uart_recv_data[idx[2:0]];
end
next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= data_disp + 1;
end
end
end else begin
if(trans_status == `TransAddr) begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= opaddr[{head_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= `IsBusy;
next_read_data <= `ZeroBlock;
next_trans_status <= (head_disp == `FullHeadDisp ? `TransData : `TransAddr);
next_head_disp <= head_disp + 1;
next_data_disp <= `ZeroDataDisp;
end
end else begin
if(uart_sendable) begin
uart_send_flag <= `SendEnable;
for(idx = 0; idx < 8; idx = idx + 1) begin
uart_send_data[idx[2:0]] <= write_data[{data_disp,idx[2:0]}];
end
uart_recv_flag <= `RecvDisable;
next_busy <= (data_disp != `FullDataDisp);
next_read_data <= `ZeroBlock;
next_trans_status <= (data_disp == `FullDataDisp ? `TransAddr : `TransData);
next_head_disp <= `ZeroHeadDisp;
next_data_disp <= data_disp + 1;
end
end
end
end
end
always @ (posedge clk) begin
busy <= next_busy;
read_data <= next_read_data;
trans_status <= next_trans_status;
head_disp <= next_head_disp;
data_disp <= next_data_disp;
end
endmodule | 0 |
5,408 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v | 113,962,532 | ex_mem.v | v | 33 | 61 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:10: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] ex_wdata,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:11: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:15: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] mem_wdata, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:16: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] mem_wd, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:22: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:23: Define or directive not defined: \'`ZeroWord\'\n mem_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:24: Define or directive not defined: \'`ZeroRegAddr\'\n mem_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:24: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:25: Define or directive not defined: \'`WriteDisable\'\n mem_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/ex_mem.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_wreg <= `WriteDisable;\n ^\n%Error: Cannot continue\n' | 6,170 | module | module ex_mem(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] ex_wdata,
input wire[`RegAddrWidth-1:0] ex_wd,
input wire ex_wreg,
output reg[`RegDataWidth-1:0] mem_wdata,
output reg[`RegAddrWidth-1:0] mem_wd,
output reg mem_wreg
);
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
mem_wdata <= `ZeroWord;
mem_wd <= `ZeroRegAddr;
mem_wreg <= `WriteDisable;
end else if (!stall[3]) begin
mem_wdata <= ex_wdata;
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
end
end
endmodule | module ex_mem(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] ex_wdata,
input wire[`RegAddrWidth-1:0] ex_wd,
input wire ex_wreg,
output reg[`RegDataWidth-1:0] mem_wdata,
output reg[`RegAddrWidth-1:0] mem_wd,
output reg mem_wreg
); |
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
mem_wdata <= `ZeroWord;
mem_wd <= `ZeroRegAddr;
mem_wreg <= `WriteDisable;
end else if (!stall[3]) begin
mem_wdata <= ex_wdata;
mem_wd <= ex_wd;
mem_wreg <= ex_wreg;
end
end
endmodule | 0 |
5,409 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v | 113,962,532 | id_ex.v | v | 60 | 46 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:10: Define or directive not defined: \'`AluOpWidth\'\n input wire[`AluOpWidth-1:0] id_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:11: Define or directive not defined: \'`AluSelWidth\'\n input wire[`AluSelWidth-1:0] id_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:12: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:13: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:14: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] id_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:16: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:17: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] id_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:21: Define or directive not defined: \'`AluOpWidth\'\n output reg[`AluOpWidth-1:0] ex_aluop,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:22: Define or directive not defined: \'`AluSelWidth\'\n output reg[`AluSelWidth-1:0] ex_alusel,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:23: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg1,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:24: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_reg2,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:25: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] ex_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:27: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_base,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:28: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] ex_addr_off,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:36: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:37: Define or directive not defined: \'`EXE_NOP_OP\'\n ex_aluop <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:38: Define or directive not defined: \'`EXE_NOP_RES\'\n ex_alusel <= `EXE_NOP_RES;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_alusel <= `EXE_NOP_RES;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:39: Define or directive not defined: \'`ZeroWord\'\n ex_reg1 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg1 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:40: Define or directive not defined: \'`ZeroWord\'\n ex_reg2 <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_reg2 <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:41: Define or directive not defined: \'`ZeroRegAddr\'\n ex_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:41: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:42: Define or directive not defined: \'`WriteDisable\'\n ex_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_wreg <= `WriteDisable;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:43: Define or directive not defined: \'`ZeroWord\'\n ex_addr_base <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_base <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:44: Define or directive not defined: \'`ZeroWord\'\n ex_addr_off <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n ex_addr_off <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:45: Define or directive not defined: \'`NoJump\'\n jump_type_o <= `NoJump;\n ^~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/id_ex.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n jump_type_o <= `NoJump;\n ^\n%Error: Cannot continue\n' | 6,171 | module | module id_ex(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`AluOpWidth-1:0] id_aluop,
input wire[`AluSelWidth-1:0] id_alusel,
input wire[`RegDataWidth-1:0] id_reg1,
input wire[`RegDataWidth-1:0] id_reg2,
input wire[`RegAddrWidth-1:0] id_wd,
input wire id_wreg,
input wire[`RegDataWidth-1:0] id_addr_base,
input wire[`RegDataWidth-1:0] id_addr_off,
input wire[1:0] id_jump_type,
output reg[`AluOpWidth-1:0] ex_aluop,
output reg[`AluSelWidth-1:0] ex_alusel,
output reg[`RegDataWidth-1:0] ex_reg1,
output reg[`RegDataWidth-1:0] ex_reg2,
output reg[`RegAddrWidth-1:0] ex_wd,
output reg ex_wreg,
output reg[`RegDataWidth-1:0] ex_addr_base,
output reg[`RegDataWidth-1:0] ex_addr_off,
output reg[1:0] jump_type_o
);
always @ (posedge clk)
begin
if(rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_NOP_RES;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `ZeroRegAddr;
ex_wreg <= `WriteDisable;
ex_addr_base <= `ZeroWord;
ex_addr_off <= `ZeroWord;
jump_type_o <= `NoJump;
end else if(!stall[2]) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_addr_base <= id_addr_base;
ex_addr_off <= id_addr_off;
jump_type_o <= id_jump_type;
end
end
endmodule | module id_ex(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`AluOpWidth-1:0] id_aluop,
input wire[`AluSelWidth-1:0] id_alusel,
input wire[`RegDataWidth-1:0] id_reg1,
input wire[`RegDataWidth-1:0] id_reg2,
input wire[`RegAddrWidth-1:0] id_wd,
input wire id_wreg,
input wire[`RegDataWidth-1:0] id_addr_base,
input wire[`RegDataWidth-1:0] id_addr_off,
input wire[1:0] id_jump_type,
output reg[`AluOpWidth-1:0] ex_aluop,
output reg[`AluSelWidth-1:0] ex_alusel,
output reg[`RegDataWidth-1:0] ex_reg1,
output reg[`RegDataWidth-1:0] ex_reg2,
output reg[`RegAddrWidth-1:0] ex_wd,
output reg ex_wreg,
output reg[`RegDataWidth-1:0] ex_addr_base,
output reg[`RegDataWidth-1:0] ex_addr_off,
output reg[1:0] jump_type_o
); |
always @ (posedge clk)
begin
if(rst == `RstEnable) begin
ex_aluop <= `EXE_NOP_OP;
ex_alusel <= `EXE_NOP_RES;
ex_reg1 <= `ZeroWord;
ex_reg2 <= `ZeroWord;
ex_wd <= `ZeroRegAddr;
ex_wreg <= `WriteDisable;
ex_addr_base <= `ZeroWord;
ex_addr_off <= `ZeroWord;
jump_type_o <= `NoJump;
end else if(!stall[2]) begin
ex_aluop <= id_aluop;
ex_alusel <= id_alusel;
ex_reg1 <= id_reg1;
ex_reg2 <= id_reg2;
ex_wd <= id_wd;
ex_wreg <= id_wreg;
ex_addr_base <= id_addr_base;
ex_addr_off <= id_addr_off;
jump_type_o <= id_jump_type;
end
end
endmodule | 0 |
5,410 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v | 113,962,532 | if_id.v | v | 41 | 57 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:10: Define or directive not defined: \'`MemAddrWidth\'\n input wire[`MemAddrWidth-1:0] if_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:11: Define or directive not defined: \'`InstWidth\'\n input wire[`InstWidth-1:0] if_inst,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:18: Define or directive not defined: \'`MemAddrWidth\'\n output reg[`MemAddrWidth-1:0] id_pc,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:19: Define or directive not defined: \'`InstWidth\'\n output reg[`InstWidth-1:0] id_inst\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:24: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable)\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:26: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:27: Define or directive not defined: \'`ZeroWord\'\n id_inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:27: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_inst <= `ZeroWord;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:29: Define or directive not defined: \'`JumpUncdt\'\n if (idex_jump_type == `JumpUncdt \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:30: Define or directive not defined: \'`JumpBranch\'\n || (idex_jump_type == `JumpBranch && ex_jump)) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:31: Define or directive not defined: \'`ZeroWord\'\n id_pc <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/if_id.v:32: Define or directive not defined: \'`NopInst\'\n id_inst <= `NopInst;\n ^~~~~~~~\n%Error: Cannot continue\n' | 6,172 | module | module if_id(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`MemAddrWidth-1:0] if_pc,
input wire[`InstWidth-1:0] if_inst,
input wire ex_jump,
input wire[1:0] idex_jump_type,
output reg[`MemAddrWidth-1:0] id_pc,
output reg[`InstWidth-1:0] id_inst
);
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if (!stall[1]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
id_pc <= `ZeroWord;
id_inst <= `NopInst;
end else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
end
endmodule | module if_id(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`MemAddrWidth-1:0] if_pc,
input wire[`InstWidth-1:0] if_inst,
input wire ex_jump,
input wire[1:0] idex_jump_type,
output reg[`MemAddrWidth-1:0] id_pc,
output reg[`InstWidth-1:0] id_inst
); |
always @ (posedge clk)
begin
if (rst == `RstEnable)
begin
id_pc <= `ZeroWord;
id_inst <= `ZeroWord;
end else if (!stall[1]) begin
if (idex_jump_type == `JumpUncdt
|| (idex_jump_type == `JumpBranch && ex_jump)) begin
id_pc <= `ZeroWord;
id_inst <= `NopInst;
end else begin
id_pc <= if_pc;
id_inst <= if_inst;
end
end
end
endmodule | 0 |
5,411 | data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v | 113,962,532 | mem_wb.v | v | 35 | 49 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.v\n data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash,data/full_repos/permissive/113962532/defines.vh.sv\n defines.vh\n defines.vh.v\n defines.vh.sv\n obj_dir/defines.vh\n obj_dir/defines.vh.v\n obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:11: Define or directive not defined: \'`RegDataWidth\'\n input wire[`RegDataWidth-1:0] mem_wdata,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:12: Define or directive not defined: \'`RegAddrWidth\'\n input wire[`RegAddrWidth-1:0] mem_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:16: Define or directive not defined: \'`RegDataWidth\'\n output reg[`RegDataWidth-1:0] wb_wdata,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:17: Define or directive not defined: \'`RegAddrWidth\'\n output reg[`RegAddrWidth-1:0] wb_wd,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:23: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:23: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `RstEnable) begin\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:24: Define or directive not defined: \'`ZeroWord\'\n wb_wdata <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:25: Define or directive not defined: \'`ZeroRegAddr\'\n wb_wd <= `ZeroRegAddr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:25: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wb_wd <= `ZeroRegAddr;\n ^\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:26: Define or directive not defined: \'`WriteDisable\'\n wb_wreg <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/113962532/risc-v/risc-v.srcs/sources_1/new/trash/mem_wb.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wb_wreg <= `WriteDisable;\n ^\n%Error: Cannot continue\n' | 6,173 | module | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] mem_wdata,
input wire[`RegAddrWidth-1:0] mem_wd,
input wire mem_wreg,
output reg[`RegDataWidth-1:0] wb_wdata,
output reg[`RegAddrWidth-1:0] wb_wd,
output reg wb_wreg
);
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
wb_wdata <= `ZeroWord;
wb_wd <= `ZeroRegAddr;
wb_wreg <= `WriteDisable;
end else if(!stall[4]) begin
wb_wdata <= mem_wdata;
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
end
end
endmodule | module mem_wb(
input wire clk,
input wire rst,
input wire[5:0] stall,
input wire[`RegDataWidth-1:0] mem_wdata,
input wire[`RegAddrWidth-1:0] mem_wd,
input wire mem_wreg,
output reg[`RegDataWidth-1:0] wb_wdata,
output reg[`RegAddrWidth-1:0] wb_wd,
output reg wb_wreg
); |
always @ (posedge clk)
begin
if (rst == `RstEnable) begin
wb_wdata <= `ZeroWord;
wb_wd <= `ZeroRegAddr;
wb_wreg <= `WriteDisable;
end else if(!stall[4]) begin
wb_wdata <= mem_wdata;
wb_wd <= mem_wd;
wb_wreg <= mem_wreg;
end
end
endmodule | 0 |
5,413 | data/full_repos/permissive/114091260/material/CPU设计代码/第三步/top.v | 114,091,260 | top.v | v | 52 | 36 | [] | [] | [] | [(43, 90)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: Exiting due to 1 error(s)\n' | 6,180 | module | module top(
input clk,
input enable,
input start,
input rst,
input [3:0] select_y,
output [15:0] y
);
wire [15:0] i_datain;
wire [15:0] d_datain;
wire [7:0] i_addr;
wire [7:0] d_addr;
wire d_we;
wire [15:0] d_dataout;
pcpu u_pcpu (
.clock(clk),
.enable(enable),
.reset(rst),
.start(start),
.i_datain(i_datain),
.d_datain(d_datain),
.select_y(select_y),
.i_addr(i_addr),
.d_addr(d_addr),
.d_we(d_we),
.d_dataout(d_dataout),
.y(y)
);
i_memory i_mem (
.clk(clk),
.rst(rst),
.addr(i_addr),
.we(1'b0),
.datain(16'b0000_0000_0000_0000),
.dataout(i_datain)
);
d_memory d_mem (
.clk(clk),
.rst(rst),
.addr(d_addr),
.we(d_we),
.datain(d_dataout),
.dataout(d_datain)
);
endmodule | module top(
input clk,
input enable,
input start,
input rst,
input [3:0] select_y,
output [15:0] y
); |
wire [15:0] i_datain;
wire [15:0] d_datain;
wire [7:0] i_addr;
wire [7:0] d_addr;
wire d_we;
wire [15:0] d_dataout;
pcpu u_pcpu (
.clock(clk),
.enable(enable),
.reset(rst),
.start(start),
.i_datain(i_datain),
.d_datain(d_datain),
.select_y(select_y),
.i_addr(i_addr),
.d_addr(d_addr),
.d_we(d_we),
.d_dataout(d_dataout),
.y(y)
);
i_memory i_mem (
.clk(clk),
.rst(rst),
.addr(i_addr),
.we(1'b0),
.datain(16'b0000_0000_0000_0000),
.dataout(i_datain)
);
d_memory d_mem (
.clk(clk),
.rst(rst),
.addr(d_addr),
.we(d_we),
.datain(d_dataout),
.dataout(d_datain)
);
endmodule | 6 |
5,414 | data/full_repos/permissive/114091260/material/CPU设计代码/第三步/top_test.v | 114,091,260 | top_test.v | v | 57 | 88 | [] | [] | [] | null | line:37 column:13: Illegal character '"' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:39: Unsupported or unknown PLI call: $monitor\n $monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b", \n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10 rst <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 rst <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10 enable <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10 start <=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10 start <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xb8\x89\xe6\xad\xa5/top_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #5\n ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,181 | module | module top_test;
reg clk;
reg enable;
reg start;
reg rst;
reg [3:0] select_y;
wire [15:0] y;
top uut (
.clk(clk),
.enable(enable),
.start(start),
.rst(rst),
.select_y(select_y),
.y(y)
);
initial begin
clk = 0;
enable = 0;
start = 0;
rst = 1;
select_y = 0;
#100;
$display("pc : id_ir :reg_A :reg_B :reg_C\
: da : dd : w : reC1 : gr1 : gr2 : gr3 :zf :nf:cf");
$monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b",
uut.u_pcpu.pc, uut.u_pcpu.id_ir, uut.u_pcpu.reg_A, uut.u_pcpu.reg_B,
uut.u_pcpu.reg_C, uut.d_addr, uut.d_dataout, uut.d_we, uut.u_pcpu.reg_C1,
uut.u_pcpu.gr[1], uut.u_pcpu.gr[2], uut.u_pcpu.gr[3],
uut.u_pcpu.zf, uut.u_pcpu.nf, uut.u_pcpu.cf);
#10 rst <= 0;
#10 rst <= 1;
#10 enable <= 1;
#10 start <=1;
#10 start <= 0;
end
always #5
clk = ~clk;
endmodule | module top_test; |
reg clk;
reg enable;
reg start;
reg rst;
reg [3:0] select_y;
wire [15:0] y;
top uut (
.clk(clk),
.enable(enable),
.start(start),
.rst(rst),
.select_y(select_y),
.y(y)
);
initial begin
clk = 0;
enable = 0;
start = 0;
rst = 1;
select_y = 0;
#100;
$display("pc : id_ir :reg_A :reg_B :reg_C\
: da : dd : w : reC1 : gr1 : gr2 : gr3 :zf :nf:cf");
$monitor("%h : %b : %h : %h : %h : %h : %h : %b : %h : %h : %h : %h : %b : %b : %b",
uut.u_pcpu.pc, uut.u_pcpu.id_ir, uut.u_pcpu.reg_A, uut.u_pcpu.reg_B,
uut.u_pcpu.reg_C, uut.d_addr, uut.d_dataout, uut.d_we, uut.u_pcpu.reg_C1,
uut.u_pcpu.gr[1], uut.u_pcpu.gr[2], uut.u_pcpu.gr[3],
uut.u_pcpu.zf, uut.u_pcpu.nf, uut.u_pcpu.cf);
#10 rst <= 0;
#10 rst <= 1;
#10 enable <= 1;
#10 start <=1;
#10 start <= 0;
end
always #5
clk = ~clk;
endmodule | 6 |
5,415 | data/full_repos/permissive/114091260/material/CPU设计代码/第二步/VGA显示/d_memory.v | 114,091,260 | d_memory.v | v | 28 | 38 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/fe7ed3a9-4bef-4155-903f-574297a6de71.xml | null | 6,183 | module | module d_memory(
input clk,
input rst,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
);
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
RAM[0] <= 16'h00AB;
RAM[1] <= 16'h3C00;
RAM[2] <= 16'h0000;
end
else if (we)
RAM[addr] <= datain;
end
endmodule | module d_memory(
input clk,
input rst,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
); |
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
RAM[0] <= 16'h00AB;
RAM[1] <= 16'h3C00;
RAM[2] <= 16'h0000;
end
else if (we)
RAM[addr] <= datain;
end
endmodule | 6 |
5,416 | data/full_repos/permissive/114091260/material/CPU设计代码/第二步/VGA显示/i_memory.v | 114,091,260 | i_memory.v | v | 42 | 53 | [] | [] | [] | [(1, 80)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`LOAD\'\n RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`gr1\'\n RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:20: Define or directive not defined: \'`gr0\'\n RAM[0] <= {`LOAD, `gr1, 1\'b0, `gr0, 4\'b0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`LOAD\'\n RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`gr2\'\n RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:21: Define or directive not defined: \'`gr0\'\n RAM[1] <= {`LOAD, `gr2, 1\'b0, `gr0, 4\'b0001};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:22: Define or directive not defined: \'`NOP\'\n RAM[2] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:22: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[2] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:23: Define or directive not defined: \'`NOP\'\n RAM[3] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:23: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[3] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:24: Define or directive not defined: \'`NOP\'\n RAM[4] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:24: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[4] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`ADD\'\n RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr3\'\n RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr1\'\n RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:25: Define or directive not defined: \'`gr2\'\n RAM[5] <= {`ADD, `gr3, 1\'b0, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:26: Define or directive not defined: \'`NOP\'\n RAM[6] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:26: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[6] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:27: Define or directive not defined: \'`NOP\'\n RAM[7] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:27: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[7] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:28: Define or directive not defined: \'`NOP\'\n RAM[8] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:28: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[8] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`STORE\'\n RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`gr3\'\n RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:29: Define or directive not defined: \'`gr0\'\n RAM[9] <= {`STORE, `gr3, 1\'b0, `gr0, 4\'b0010};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: Define or directive not defined: \'`BNZ\'\n RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:30: Define or directive not defined: \'`gr1\'\n RAM[10] <= {`BNZ, `gr1, 8\'b0001_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:31: Define or directive not defined: \'`NOP\'\n RAM[11] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:31: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[11] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:32: Define or directive not defined: \'`NOP\'\n RAM[12] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:32: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[12] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:33: Define or directive not defined: \'`NOP\'\n RAM[13] <= {`NOP, 11\'b000_0000_0000};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:33: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[13] <= {`NOP, 11\'b000_0000_0000};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`CMP\'\n RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n ^\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`gr1\'\n RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:34: Define or directive not defined: \'`gr2\'\n RAM[187] <= {`CMP, 4\'b0000, `gr1, 1\'b0, `gr2};\n ^~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:35: Define or directive not defined: \'`HALT\'\n RAM[188] <= {`HALT, 11\'b000_0000_0000};\n ^~~~~\n%Error: data/full_repos/permissive/114091260/material/CPU\xe8\xae\xbe\xe8\xae\xa1\xe4\xbb\xa3\xe7\xa0\x81/\xe7\xac\xac\xe4\xba\x8c\xe6\xad\xa5/VGA\xe6\x98\xbe\xe7\xa4\xba/i_memory.v:35: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n RAM[188] <= {`HALT, 11\'b000_0000_0000};\n ^\n%Error: Exiting due to 45 error(s)\n' | 6,184 | module | module i_memory(
input clk,
input rst,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
);
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
RAM[0] <= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
RAM[1] <= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
RAM[2] <= {`NOP, 11'b000_0000_0000};
RAM[3] <= {`NOP, 11'b000_0000_0000};
RAM[4] <= {`NOP, 11'b000_0000_0000};
RAM[5] <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
RAM[6] <= {`NOP, 11'b000_0000_0000};
RAM[7] <= {`NOP, 11'b000_0000_0000};
RAM[8] <= {`NOP, 11'b000_0000_0000};
RAM[9] <= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
RAM[10] <= {`BNZ, `gr1, 8'b0001_0000};
RAM[11] <= {`NOP, 11'b000_0000_0000};
RAM[12] <= {`NOP, 11'b000_0000_0000};
RAM[13] <= {`NOP, 11'b000_0000_0000};
RAM[187] <= {`CMP, 4'b0000, `gr1, 1'b0, `gr2};
RAM[188] <= {`HALT, 11'b000_0000_0000};
end
else if (we)
RAM[addr] <= datain;
end
endmodule | module i_memory(
input clk,
input rst,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
); |
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
RAM[0] <= {`LOAD, `gr1, 1'b0, `gr0, 4'b0000};
RAM[1] <= {`LOAD, `gr2, 1'b0, `gr0, 4'b0001};
RAM[2] <= {`NOP, 11'b000_0000_0000};
RAM[3] <= {`NOP, 11'b000_0000_0000};
RAM[4] <= {`NOP, 11'b000_0000_0000};
RAM[5] <= {`ADD, `gr3, 1'b0, `gr1, 1'b0, `gr2};
RAM[6] <= {`NOP, 11'b000_0000_0000};
RAM[7] <= {`NOP, 11'b000_0000_0000};
RAM[8] <= {`NOP, 11'b000_0000_0000};
RAM[9] <= {`STORE, `gr3, 1'b0, `gr0, 4'b0010};
RAM[10] <= {`BNZ, `gr1, 8'b0001_0000};
RAM[11] <= {`NOP, 11'b000_0000_0000};
RAM[12] <= {`NOP, 11'b000_0000_0000};
RAM[13] <= {`NOP, 11'b000_0000_0000};
RAM[187] <= {`CMP, 4'b0000, `gr1, 1'b0, `gr2};
RAM[188] <= {`HALT, 11'b000_0000_0000};
end
else if (we)
RAM[addr] <= datain;
end
endmodule | 6 |
5,419 | data/full_repos/permissive/114091260/material/CPU设计代码/第二步/内存实现/initial初始化/memory.v | 114,091,260 | memory.v | v | 19 | 29 | [] | [] | [] | [(3, 18)] | null | data/verilator_xmls/8442b39e-f01a-4555-a925-fa6bc95bc31b.xml | null | 6,190 | module | module memory(
input clk,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
);
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk)
if (we)
RAM[addr] <= datain;
endmodule | module memory(
input clk,
input [7:0] addr,
input we,
input [15:0] datain,
output [15:0] dataout
); |
reg [15:0] RAM[255:0];
assign dataout = RAM[addr];
always @(posedge clk)
if (we)
RAM[addr] <= datain;
endmodule | 6 |
5,433 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v | 114,091,260 | cpu_ex.v | v | 256 | 85 | [] | [] | [] | [(78, 311)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:67: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `True) begin\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:70: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:82: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lk_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n lk_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:83: Define or directive not defined: \'`True\'\n end else if (stall != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:94: Define or directive not defined: \'`LUI\'\n `LUI: begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:94: syntax error, unexpected \':\', expecting endcase\n `LUI: begin\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:98: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:100: Define or directive not defined: \'`AUIPC\'\n `AUIPC: begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:104: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:106: Define or directive not defined: \'`JAL\'\n `JAL: begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:108: Define or directive not defined: \'`True\'\n wPcIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:110: Define or directive not defined: \'`True\'\n clear <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:112: Define or directive not defined: \'`JALR\'\n `JALR: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:114: Define or directive not defined: \'`True\'\n wPcIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:116: Define or directive not defined: \'`True\'\n clear <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:118: Define or directive not defined: \'`BRANCH\'\n `BRANCH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:120: Define or directive not defined: \'`BEQ\'\n `BEQ:\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:122: Define or directive not defined: \'`BNE\'\n `BNE:\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:124: Define or directive not defined: \'`BLT\'\n `BLT:\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:126: Define or directive not defined: \'`BGE\'\n `BGE:\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:128: Define or directive not defined: \'`BLTU\'\n `BLTU:\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:130: Define or directive not defined: \'`BGEU\'\n `BGEU:\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:135: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("select jump? %d %d", rd0, rd1);\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:137: syntax error, unexpected <=, expecting IDENTIFIER\n wPcIs_o <= `True;\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:137: Define or directive not defined: \'`True\'\n wPcIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:139: Define or directive not defined: \'`True\'\n clear <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:141: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("no jump!");\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:141: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n if(`DEBUG == 1\'b1) $display("no jump!");\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:142: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wPcIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:144: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:148: Define or directive not defined: \'`LOAD\'\n `LOAD: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:151: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:153: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:153: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n if(`DEBUG == 1\'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:155: Define or directive not defined: \'`STORE\'\n `STORE: begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:158: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:161: Define or directive not defined: \'`OP_IMM\'\n `OP_IMM: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:164: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n clear <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:166: Define or directive not defined: \'`ADDI\'\n `ADDI: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:166: syntax error, unexpected \':\', expecting endcase\n `ADDI: begin\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:169: Define or directive not defined: \'`SLTI\'\n `SLTI: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:172: Define or directive not defined: \'`SLTIU\'\n `SLTIU: begin \n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:175: Define or directive not defined: \'`XORI\'\n `XORI: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:178: Define or directive not defined: \'`ORI\'\n `ORI: begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:181: Define or directive not defined: \'`ANDI\'\n `ANDI: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_ex.v:184: Define or directive not defined: \'`SLLI\'\n `SLLI: begin\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,210 | module | module CPU_EX(
clk, rst, state, stall,
i_id, i_id_o,
wrIs, wr,
opCode, opType,
rd0, rd1, imm,
wrIs_o, wr_o, wrData_o,
wPcIs_o, wPcData_o,
opCode_o, opType_o,
rd0_o, rd1_o, imm_o,
clear,
lk_o
);
input wire clk, rst, state, stall;
input wire [31 : 0] i_id;
output reg [31 : 0] i_id_o;
input wire wrIs;
input wire [ 4 : 0] wr;
input wire [ 6 : 0] opCode;
input wire [ 2 : 0] opType;
input wire [31 : 0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4 : 0] wr_o;
output reg [31 : 0] wrData_o;
output reg wPcIs_o;
output reg [31 : 0] wPcData_o;
output reg [ 6 : 0] opCode_o;
output reg [ 2 : 0] opType_o;
output reg [31 : 0] rd0_o, rd1_o, imm_o;
output reg clear, lk_o;
reg tmp0, tmp1, tmpOut, jumpFlag;
always @( * ) begin
if (rst == `True) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= 7'b0;
opType_o <= 3'b0;
rd0_o <= 32'b0;
rd1_o <= 32'b0;
imm_o <= 32'b0;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= 1'b0;
lk_o <= `False;
end else if (stall != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
opType_o <= opType;
wrIs_o <= wrIs;
wr_o <= wr;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
case (opCode)
`LUI: begin
wrData_o <= imm;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
`AUIPC: begin
wrData_o <= i_id + imm;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
`JAL: begin
wrData_o <= i_id + 4;
wPcIs_o <= `True;
wPcData_o <= imm + i_id;
clear <= `True;
end
`JALR: begin
wrData_o <= i_id + 4;
wPcIs_o <= `True;
wPcData_o <= (rd0 + imm) & (-1 ^ 1);
clear <= `True;
end
`BRANCH: begin
case (opType)
`BEQ:
jumpFlag = (rd0 == rd1) ? 1'b1 : 1'b0;
`BNE:
jumpFlag = (rd0 != rd1) ? 1'b1 : 1'b0;
`BLT:
jumpFlag = ($signed(rd0) < $signed(rd1)) ? 1'b1 : 1'b0;
`BGE:
jumpFlag = ($signed(rd0) >= $signed(rd1)) ? 1'b1 : 1'b0;
`BLTU:
jumpFlag = ($unsigned(rd0) < $unsigned(rd1)) ? 1'b1 : 1'b0;
`BGEU:
jumpFlag = ($unsigned(rd0) >= $unsigned(rd1)) ? 1'b1 : 1'b0;
default:
jumpFlag = 1'b0;
endcase
if(`DEBUG == 1'b1) $display("select jump? %d %d", rd0, rd1);
if (jumpFlag == 1'b1) begin
wPcIs_o <= `True;
wPcData_o <= i_id + imm;
clear <= `True;
end else begin
if(`DEBUG == 1'b1) $display("no jump!");
wPcIs_o <= `False;
wPcData_o <= i_id + 4;
clear <= `False;
end
end
`LOAD: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
wrData_o <= rd0 + imm;
if(`DEBUG == 1'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);
end
`STORE: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
wrData_o <= rd0 + imm;
end
`OP_IMM: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
case (opType)
`ADDI: begin
wrData_o <= rd0 + rd1;
end
`SLTI: begin
wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
end
`SLTIU: begin
wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
end
`XORI: begin
wrData_o <= rd0 ^ rd1;
end
`ORI: begin
wrData_o <= rd0 | rd1;
end
`ANDI: begin
wrData_o <= rd0 & rd1;
end
`SLLI: begin
wrData_o <= rd0 << rd1[4:0];
end
`SRLI: begin
if (imm[10] == 0)
wrData_o <= rd0 >> rd1[4:0];
else
wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
end
default: ;
endcase
end
`OP: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
case (opType)
`ADD: begin
if (imm[5] == 0)
wrData_o <= rd0 + rd1;
else
wrData_o <= rd0 - rd1;
end
`SLT: begin
wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
end
`SLTU: begin
wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
end
`XOR: begin
wrData_o <= rd0 ^ rd1;
end
`SLL: begin
wrData_o <= rd0 << rd1[4:0];
end
`SRL: begin
if (imm[5] == 0)
wrData_o <= rd0 >> rd1[4:0];
else
wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
end
`OR: begin
wrData_o <= rd0 | rd1;
end
`AND: begin
wrData_o <= rd0 & rd1;
end
default: ;
endcase
end
`MISC_MEM: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
default: ;
endcase
if (opCode != `LOAD)
lk_o = `False;
else
lk_o = `True;
end
end
endmodule | module CPU_EX(
clk, rst, state, stall,
i_id, i_id_o,
wrIs, wr,
opCode, opType,
rd0, rd1, imm,
wrIs_o, wr_o, wrData_o,
wPcIs_o, wPcData_o,
opCode_o, opType_o,
rd0_o, rd1_o, imm_o,
clear,
lk_o
); |
input wire clk, rst, state, stall;
input wire [31 : 0] i_id;
output reg [31 : 0] i_id_o;
input wire wrIs;
input wire [ 4 : 0] wr;
input wire [ 6 : 0] opCode;
input wire [ 2 : 0] opType;
input wire [31 : 0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4 : 0] wr_o;
output reg [31 : 0] wrData_o;
output reg wPcIs_o;
output reg [31 : 0] wPcData_o;
output reg [ 6 : 0] opCode_o;
output reg [ 2 : 0] opType_o;
output reg [31 : 0] rd0_o, rd1_o, imm_o;
output reg clear, lk_o;
reg tmp0, tmp1, tmpOut, jumpFlag;
always @( * ) begin
if (rst == `True) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= 7'b0;
opType_o <= 3'b0;
rd0_o <= 32'b0;
rd1_o <= 32'b0;
imm_o <= 32'b0;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= 1'b0;
lk_o <= `False;
end else if (stall != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
opType_o <= opType;
wrIs_o <= wrIs;
wr_o <= wr;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
case (opCode)
`LUI: begin
wrData_o <= imm;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
`AUIPC: begin
wrData_o <= i_id + imm;
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
`JAL: begin
wrData_o <= i_id + 4;
wPcIs_o <= `True;
wPcData_o <= imm + i_id;
clear <= `True;
end
`JALR: begin
wrData_o <= i_id + 4;
wPcIs_o <= `True;
wPcData_o <= (rd0 + imm) & (-1 ^ 1);
clear <= `True;
end
`BRANCH: begin
case (opType)
`BEQ:
jumpFlag = (rd0 == rd1) ? 1'b1 : 1'b0;
`BNE:
jumpFlag = (rd0 != rd1) ? 1'b1 : 1'b0;
`BLT:
jumpFlag = ($signed(rd0) < $signed(rd1)) ? 1'b1 : 1'b0;
`BGE:
jumpFlag = ($signed(rd0) >= $signed(rd1)) ? 1'b1 : 1'b0;
`BLTU:
jumpFlag = ($unsigned(rd0) < $unsigned(rd1)) ? 1'b1 : 1'b0;
`BGEU:
jumpFlag = ($unsigned(rd0) >= $unsigned(rd1)) ? 1'b1 : 1'b0;
default:
jumpFlag = 1'b0;
endcase
if(`DEBUG == 1'b1) $display("select jump? %d %d", rd0, rd1);
if (jumpFlag == 1'b1) begin
wPcIs_o <= `True;
wPcData_o <= i_id + imm;
clear <= `True;
end else begin
if(`DEBUG == 1'b1) $display("no jump!");
wPcIs_o <= `False;
wPcData_o <= i_id + 4;
clear <= `False;
end
end
`LOAD: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
wrData_o <= rd0 + imm;
if(`DEBUG == 1'b1) $display("[MEM]LOAD Addr:%d %d", rd0, imm);
end
`STORE: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
wrData_o <= rd0 + imm;
end
`OP_IMM: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
case (opType)
`ADDI: begin
wrData_o <= rd0 + rd1;
end
`SLTI: begin
wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
end
`SLTIU: begin
wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
end
`XORI: begin
wrData_o <= rd0 ^ rd1;
end
`ORI: begin
wrData_o <= rd0 | rd1;
end
`ANDI: begin
wrData_o <= rd0 & rd1;
end
`SLLI: begin
wrData_o <= rd0 << rd1[4:0];
end
`SRLI: begin
if (imm[10] == 0)
wrData_o <= rd0 >> rd1[4:0];
else
wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
end
default: ;
endcase
end
`OP: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
case (opType)
`ADD: begin
if (imm[5] == 0)
wrData_o <= rd0 + rd1;
else
wrData_o <= rd0 - rd1;
end
`SLT: begin
wrData_o <= $signed(rd0) < $signed(rd1) ? 32'b1 : 32'b0;
end
`SLTU: begin
wrData_o <= $unsigned(rd0) < $unsigned(rd1) ? 32'b1 : 32'b0;
end
`XOR: begin
wrData_o <= rd0 ^ rd1;
end
`SLL: begin
wrData_o <= rd0 << rd1[4:0];
end
`SRL: begin
if (imm[5] == 0)
wrData_o <= rd0 >> rd1[4:0];
else
wrData_o <= (rd0 >> rd1[4:0]) | ({32{rd0[31]}} << (6'd32 - {1'b0, rd1[4:0]}));
end
`OR: begin
wrData_o <= rd0 | rd1;
end
`AND: begin
wrData_o <= rd0 & rd1;
end
default: ;
endcase
end
`MISC_MEM: begin
wPcIs_o <= 1'b0;
wPcData_o <= 32'b0;
clear <= `False;
end
default: ;
endcase
if (opCode != `LOAD)
lk_o = `False;
else
lk_o = `True;
end
end
endmodule | 6 |
5,436 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v | 114,091,260 | cpu_mem.v | v | 151 | 87 | [] | [] | [] | null | line:99: before: ")" | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:43: syntax error, unexpected \')\', expecting \'[\'\n );\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:47: syntax error, unexpected input\n input wire [ 31:0] i_id;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:48: syntax error, unexpected output\n output reg [ 31:0] i_id_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:50: syntax error, unexpected input\n input wire wrIs;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:51: syntax error, unexpected input\n input wire [ 4:0] wr;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:52: syntax error, unexpected input\n input wire [31:0] wrData;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:53: syntax error, unexpected input\n input wire [ 6:0] opCode;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:54: syntax error, unexpected output\n output reg [ 6:0] opCode_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:55: syntax error, unexpected input\n input wire [ 2:0] opType;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:56: syntax error, unexpected output\n output reg [ 2:0] opType_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:57: syntax error, unexpected input\n input wire [31:0] rd0, rd1, imm;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:59: syntax error, unexpected output\n output reg memIs;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:60: syntax error, unexpected output\n output reg [ 3:0] memType;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:61: syntax error, unexpected output\n output reg [31:0] memData_o, memAdd;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:63: syntax error, unexpected input\n input wire [31:0] memData_i;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:65: syntax error, unexpected output\n output reg wrIs_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:66: syntax error, unexpected output\n output reg [ 4:0] wr_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:67: syntax error, unexpected output\n output reg [31:0] wrData_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:69: syntax error, unexpected input\n input wire cacheMiss, cacheReady;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:70: syntax error, unexpected output\n output reg stall_o;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:75: syntax error, unexpected always\n always @( * ) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:79: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:81: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:88: Define or directive not defined: \'`True\'\n end else if (stall != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:93: Define or directive not defined: \'`LOAD\'\n `LOAD: begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:95: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("[MEM]load");\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:96: Define or directive not defined: \'`True\'\n memIs <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:101: Define or directive not defined: \'`STORE\'\n `STORE: begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:102: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("[MEM]store");\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:103: Define or directive not defined: \'`True\'\n memIs <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:110: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n memIs <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:120: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:124: Define or directive not defined: \'`True\'\n wating = `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:130: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wating = `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:134: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:135: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:138: Define or directive not defined: \'`True\'\n end else if (stall != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:139: Define or directive not defined: \'`LOAD\'\n if (opCode == `LOAD && wating != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:139: Define or directive not defined: \'`True\'\n if (opCode == `LOAD && wating != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_mem.v:140: Define or directive not defined: \'`True\'\n wrIs_o <= `True;\n ^~~~~\n%Error: Exiting due to 41 error(s)\n' | 6,213 | module | module CPU_MEM(
clk, rst, state, stall,
i_id, i_id_o,
wrIs, wr, wrData,
opCode, opType,
rd0, rd1, imm,
opCode_o, opType_o,
memIs, memType,
memData_o, memAdd,
memData_i,
wrIs_o, wr_o, wrData_o,
stall_o,
cacheMiss, cacheReady,
);
input wire clk, rst, state, stall;
input wire [ 31:0] i_id;
output reg [ 31:0] i_id_o;
input wire wrIs;
input wire [ 4:0] wr;
input wire [31:0] wrData;
input wire [ 6:0] opCode;
output reg [ 6:0] opCode_o;
input wire [ 2:0] opType;
output reg [ 2:0] opType_o;
input wire [31:0] rd0, rd1, imm;
output reg memIs;
output reg [ 3:0] memType;
output reg [31:0] memData_o, memAdd;
input wire [31:0] memData_i;
output reg wrIs_o;
output reg [ 4:0] wr_o;
output reg [31:0] wrData_o;
input wire cacheMiss, cacheReady;
output reg stall_o;
reg wating;
always @( * ) begin
if (rst == `True) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= 7'b0;
opType_o <= 3'b0;
wating <= 1'b0;
stall_o <= 1'b0;
end else if (stall != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
opType_o <= opType;
case (opCode)
`LOAD: begin
if(`DEBUG == 1'b1) $display("[MEM]load");
memIs <= `True;
memType <= {1'b0, opType};
memAdd <= wrData;
memData_o <= 32'b0;
end
`STORE: begin
if(`DEBUG == 1'b1) $display("[MEM]store");
memIs <= `True;
memType <= {1'b1, opType};
memAdd <= wrData;
memData_o <= rd1;
end
default: begin
memIs <= `False;
memType <= 4'b0;
memAdd <= 32'b0;
memData_o <= 32'b0;
end
endcase
end
end
always @ ( posedge cacheMiss ) begin
wrIs_o <= `False;
wr_o <= 1'b0;
wrData_o <= 32'b0;
stall_o <= 1'b1;
wating = `True;
end
always @ ( posedge cacheReady ) begin
stall_o <= 1'b0;
wating = `False;
end
always @ ( * ) begin
if (rst == `True) begin
wrIs_o <= `False;
wr_o <= 1'b0;
wrData_o <= 32'b0;
end else if (stall != `True) begin
if (opCode == `LOAD && wating != `True) begin
wrIs_o <= `True;
wr_o <= wr;
wrData_o <= memData_i;
end else begin
wrIs_o <= wrIs;
wr_o <= wr;
wrData_o <= wrData;
end
end
end
endmodule | module CPU_MEM(
clk, rst, state, stall,
i_id, i_id_o,
wrIs, wr, wrData,
opCode, opType,
rd0, rd1, imm,
opCode_o, opType_o,
memIs, memType,
memData_o, memAdd,
memData_i,
wrIs_o, wr_o, wrData_o,
stall_o,
cacheMiss, cacheReady,
); |
input wire clk, rst, state, stall;
input wire [ 31:0] i_id;
output reg [ 31:0] i_id_o;
input wire wrIs;
input wire [ 4:0] wr;
input wire [31:0] wrData;
input wire [ 6:0] opCode;
output reg [ 6:0] opCode_o;
input wire [ 2:0] opType;
output reg [ 2:0] opType_o;
input wire [31:0] rd0, rd1, imm;
output reg memIs;
output reg [ 3:0] memType;
output reg [31:0] memData_o, memAdd;
input wire [31:0] memData_i;
output reg wrIs_o;
output reg [ 4:0] wr_o;
output reg [31:0] wrData_o;
input wire cacheMiss, cacheReady;
output reg stall_o;
reg wating;
always @( * ) begin
if (rst == `True) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= 7'b0;
opType_o <= 3'b0;
wating <= 1'b0;
stall_o <= 1'b0;
end else if (stall != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
opType_o <= opType;
case (opCode)
`LOAD: begin
if(`DEBUG == 1'b1) $display("[MEM]load");
memIs <= `True;
memType <= {1'b0, opType};
memAdd <= wrData;
memData_o <= 32'b0;
end
`STORE: begin
if(`DEBUG == 1'b1) $display("[MEM]store");
memIs <= `True;
memType <= {1'b1, opType};
memAdd <= wrData;
memData_o <= rd1;
end
default: begin
memIs <= `False;
memType <= 4'b0;
memAdd <= 32'b0;
memData_o <= 32'b0;
end
endcase
end
end
always @ ( posedge cacheMiss ) begin
wrIs_o <= `False;
wr_o <= 1'b0;
wrData_o <= 32'b0;
stall_o <= 1'b1;
wating = `True;
end
always @ ( posedge cacheReady ) begin
stall_o <= 1'b0;
wating = `False;
end
always @ ( * ) begin
if (rst == `True) begin
wrIs_o <= `False;
wr_o <= 1'b0;
wrData_o <= 32'b0;
end else if (stall != `True) begin
if (opCode == `LOAD && wating != `True) begin
wrIs_o <= `True;
wr_o <= wr;
wrData_o <= memData_i;
end else begin
wrIs_o <= wrIs;
wr_o <= wr;
wrData_o <= wrData;
end
end
end
endmodule | 6 |
5,437 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v | 114,091,260 | cpu_transmitter.v | v | 165 | 83 | [] | [] | [] | [(78, 101), (103, 156), (158, 220)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= {25\'b0,`OP_IMM};\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n opCode_o <= {25\'b0,`OP_IMM};\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:38: Define or directive not defined: \'`True\'\n end else if(stall[1] != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:88: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:90: Define or directive not defined: \'`True\'\n wrIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:147: syntax error, unexpected else\n end else if(!stall[3]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`STORE\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`DEBUG\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: Cannot continue\n' | 6,214 | module | module CPU_IDTrans(
clk, rst, stall,
i_id, opCode,
i_id_o, opCode_o
);
input wire clk, rst;
input wire [3 : 0] stall;
input wire [31 : 0] i_id, opCode;
output reg [31 : 0] i_id_o, opCode_o;
always @(posedge clk) begin
if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin
i_id_o <= 32'b0;
opCode_o <= {25'b0,`OP_IMM};
end else if(stall[1] != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
end
end
endmodule | module CPU_IDTrans(
clk, rst, stall,
i_id, opCode,
i_id_o, opCode_o
); |
input wire clk, rst;
input wire [3 : 0] stall;
input wire [31 : 0] i_id, opCode;
output reg [31 : 0] i_id_o, opCode_o;
always @(posedge clk) begin
if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin
i_id_o <= 32'b0;
opCode_o <= {25'b0,`OP_IMM};
end else if(stall[1] != `True) begin
i_id_o <= i_id;
opCode_o <= opCode;
end
end
endmodule | 6 |
5,438 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v | 114,091,260 | cpu_transmitter.v | v | 165 | 83 | [] | [] | [] | [(78, 101), (103, 156), (158, 220)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= {25\'b0,`OP_IMM};\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n opCode_o <= {25\'b0,`OP_IMM};\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:38: Define or directive not defined: \'`True\'\n end else if(stall[1] != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:88: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:90: Define or directive not defined: \'`True\'\n wrIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:147: syntax error, unexpected else\n end else if(!stall[3]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`STORE\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`DEBUG\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: Cannot continue\n' | 6,214 | module | module CPU_EXTrans (
clk, rst, stall,
i_id, i_id_o,
wrIs, wr,
opCode, opType,
rd0, rd1, imm,
wrIs_o, wr_o,
opCode_o, opType_o,
rd0_o, rd1_o, imm_o
);
input wire clk, rst;
input wire [3 : 0] stall;
input wire [31 : 0] i_id;
output reg [31 : 0] i_id_o;
input wire wrIs;
input wire [ 4 : 0] wr;
input wire [ 6 : 0] opCode;
input wire [ 2 : 0] opType;
input wire [31 : 0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4 : 0] wr_o;
output reg [ 6 : 0] opCode_o;
output reg [ 2 : 0] opType_o;
output reg [31 : 0] rd0_o, rd1_o, imm_o;
always @ ( posedge clk ) begin
if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
opCode_o <= `OP_IMM;
opType_o <= `ADDI;
rd0_o <= 32'b0;
rd1_o <= 32'b0;
imm_o <= 32'b0;
end else if(!stall[2]) begin
i_id_o <= i_id;
wrIs_o <= `True;
wr_o <= wr;
opCode_o <= opCode;
opType_o <= opType;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
end
end
endmodule | module CPU_EXTrans (
clk, rst, stall,
i_id, i_id_o,
wrIs, wr,
opCode, opType,
rd0, rd1, imm,
wrIs_o, wr_o,
opCode_o, opType_o,
rd0_o, rd1_o, imm_o
); |
input wire clk, rst;
input wire [3 : 0] stall;
input wire [31 : 0] i_id;
output reg [31 : 0] i_id_o;
input wire wrIs;
input wire [ 4 : 0] wr;
input wire [ 6 : 0] opCode;
input wire [ 2 : 0] opType;
input wire [31 : 0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4 : 0] wr_o;
output reg [ 6 : 0] opCode_o;
output reg [ 2 : 0] opType_o;
output reg [31 : 0] rd0_o, rd1_o, imm_o;
always @ ( posedge clk ) begin
if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
opCode_o <= `OP_IMM;
opType_o <= `ADDI;
rd0_o <= 32'b0;
rd1_o <= 32'b0;
imm_o <= 32'b0;
end else if(!stall[2]) begin
i_id_o <= i_id;
wrIs_o <= `True;
wr_o <= wr;
opCode_o <= opCode;
opType_o <= opType;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
end
end
endmodule | 6 |
5,439 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v | 114,091,260 | cpu_transmitter.v | v | 165 | 83 | [] | [] | [] | [(78, 101), (103, 156), (158, 220)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:35: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[1]!=`True&&stall[0]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= {25\'b0,`OP_IMM};\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:37: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n opCode_o <= {25\'b0,`OP_IMM};\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:38: Define or directive not defined: \'`True\'\n end else if(stall[1] != `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:79: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[2]!=`True&&stall[1]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:88: syntax error, unexpected else\n end else if(!stall[2]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:90: Define or directive not defined: \'`True\'\n wrIs_o <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:137: Define or directive not defined: \'`True\'\n if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n wrIs_o <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wrIs_o <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: Define or directive not defined: \'`OP_IMM\'\n opCode_o <= `OP_IMM;\n ^~~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:142: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opCode_o <= `OP_IMM;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: Define or directive not defined: \'`ADDI\'\n opType_o <= `ADDI;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:143: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n opType_o <= `ADDI;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:147: syntax error, unexpected else\n end else if(!stall[3]) begin\n ^~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`STORE\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/cpu_transmitter.v:157: Define or directive not defined: \'`DEBUG\'\n if(opCode == `STORE && opType == 3\'b000 && wrData == \'h104 && `DEBUG == 1\'b0)\n ^~~~~~\n%Error: Cannot continue\n' | 6,214 | module | module CPU_MEMTrans (
clk, rst, stall,
i_id, i_id_o,
opCode, opType,
wrIs, wr, wrData,
rd0, rd1, imm,
opCode_o, opType_o,
wrIs_o, wr_o, wrData_o,
rd0_o, rd1_o, imm_o
);
input wire clk, rst;
input wire [3 : 0] stall;
input wire [ 31:0] i_id;
output reg [ 31:0] i_id_o;
input wire wrIs;
input wire [ 4:0] wr;
input wire [31:0] wrData;
input wire [ 6:0] opCode;
output reg [ 6:0] opCode_o;
input wire [ 2:0] opType;
output reg [ 2:0] opType_o;
input wire [31:0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4:0] wr_o;
output reg [31:0] wrData_o;
output reg [31:0] rd0_o, rd1_o, imm_o;
always @ ( posedge clk ) begin
if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= `OP_IMM;
opType_o <= `ADDI;
rd0_o <= 32'd0;
rd1_o <= 32'd0;
imm_o <= 32'd0;
end else if(!stall[3]) begin
i_id_o <= i_id;
wrIs_o <= wrIs;
wr_o <= wr;
wrData_o <= wrData;
opCode_o <= opCode;
opType_o <= opType;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
if(opCode == `STORE && opType == 3'b000 && wrData == 'h104 && `DEBUG == 1'b0)
$write("%c",rd1);
end
end
endmodule | module CPU_MEMTrans (
clk, rst, stall,
i_id, i_id_o,
opCode, opType,
wrIs, wr, wrData,
rd0, rd1, imm,
opCode_o, opType_o,
wrIs_o, wr_o, wrData_o,
rd0_o, rd1_o, imm_o
); |
input wire clk, rst;
input wire [3 : 0] stall;
input wire [ 31:0] i_id;
output reg [ 31:0] i_id_o;
input wire wrIs;
input wire [ 4:0] wr;
input wire [31:0] wrData;
input wire [ 6:0] opCode;
output reg [ 6:0] opCode_o;
input wire [ 2:0] opType;
output reg [ 2:0] opType_o;
input wire [31:0] rd0, rd1, imm;
output reg wrIs_o;
output reg [ 4:0] wr_o;
output reg [31:0] wrData_o;
output reg [31:0] rd0_o, rd1_o, imm_o;
always @ ( posedge clk ) begin
if (rst == `True || (stall[3]!=`True&&stall[2]==`True)) begin
i_id_o <= 5'b0;
wrIs_o <= `False;
wr_o <= 4'b0;
wrData_o <= 32'b0;
opCode_o <= `OP_IMM;
opType_o <= `ADDI;
rd0_o <= 32'd0;
rd1_o <= 32'd0;
imm_o <= 32'd0;
end else if(!stall[3]) begin
i_id_o <= i_id;
wrIs_o <= wrIs;
wr_o <= wr;
wrData_o <= wrData;
opCode_o <= opCode;
opType_o <= opType;
rd0_o <= rd0;
rd1_o <= rd1;
imm_o <= imm;
if(opCode == `STORE && opType == 3'b000 && wrData == 'h104 && `DEBUG == 1'b0)
$write("%c",rd1);
end
end
endmodule | 6 |
5,442 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v | 114,091,260 | regfile.v | v | 147 | 83 | [] | [] | [] | [(80, 202)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:54: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:54: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `True) begin\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:56: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd0 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n lkd0 <= `False;\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:59: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd0 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:63: Define or directive not defined: \'`True\'\n lkd0 <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:64: Define or directive not defined: \'`True\'\n end else if (wr0Is == `True && rr0 == wr0) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:65: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd0 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:67: Define or directive not defined: \'`True\'\n end else if (wr1Is == `True && rr0 == wr1) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:68: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd0 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:71: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd0 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:79: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:81: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd1 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:84: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd1 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:87: Define or directive not defined: \'`True\'\n lkd1 <= `True;\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:88: Define or directive not defined: \'`True\'\n end else if (wr0Is == `True && rr1 == wr0) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:89: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd1 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:91: Define or directive not defined: \'`True\'\n end else if (wr1Is == `True && rr1 == wr1) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:92: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd1 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:95: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n lkd1 <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:102: Define or directive not defined: \'`True\'\n if ( rst == `True ) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:135: Define or directive not defined: \'`True\'\n end else if ( we == `True ) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/regfile.v:142: Define or directive not defined: \'`True\'\n if (wr1Is == `True && wr1 != 5\'d0)\n ^~~~~\n%Error: Cannot continue\n' | 6,218 | module | module RegFile (
clk, rst, we,
rr0, rr1, rd0, rd1,
lk0,
lkd0, lkd1,
wr0Is,
wr0, wd0,
wr1Is,
wr1, wd1
);
input wire clk, rst, we;
input wire [4 : 0] rr0, rr1;
output reg [31 : 0] rd0, rd1;
input wire lk0;
output reg lkd0, lkd1;
input wire wr0Is, wr1Is;
input wire [4 : 0] wr0, wr1;
input wire [31 : 0] wd0, wd1;
reg [31 : 0] regs [31:0];
always @(*) begin
if (rst == `True) begin
rd0 <= 32'd0;
lkd0 <= `False;
end else begin
if (rr0 == 5'd0) begin
lkd0 <= `False;
rd0 <= 32'd0;
end else if ({lk0, wr0} == {1'b1, rr0}) begin
lkd0 <= `True;
end else if (wr0Is == `True && rr0 == wr0) begin
lkd0 <= `False;
rd0 <= wd0;
end else if (wr1Is == `True && rr0 == wr1) begin
lkd0 <= `False;
rd0 <= wd1;
end else begin
lkd0 <= `False;
rd0 <= regs[rr0];
end
end
end
always @(*) begin
if (rst == `True) begin
rd1 <= 32'd0;
lkd1 <= `False;
end else begin
if (rr1 == 5'd0) begin
lkd1 <= `False;
rd1 <= 32'd0;
end else if ({lk0, wr0} == {1'b1, rr1}) begin
lkd1 <= `True;
end else if (wr0Is == `True && rr1 == wr0) begin
lkd1 <= `False;
rd1 <= wd0;
end else if (wr1Is == `True && rr1 == wr1) begin
lkd1 <= `False;
rd1 <= wd1;
end else begin
lkd1 <= `False;
rd1 <= regs[rr1];
end
end
end
always @(posedge clk) begin
if ( rst == `True ) begin
regs[0] <= 32'b0;
regs[1] <= 32'b0;
regs[2] <= 32'b0;
regs[3] <= 32'b0;
regs[4] <= 32'b0;
regs[5] <= 32'b0;
regs[6] <= 32'b0;
regs[7] <= 32'b0;
regs[8] <= 32'b0;
regs[9] <= 32'b0;
regs[10] <= 32'b0;
regs[11] <= 32'b0;
regs[12] <= 32'b0;
regs[13] <= 32'b0;
regs[14] <= 32'b0;
regs[15] <= 32'b0;
regs[16] <= 32'b0;
regs[17] <= 32'b0;
regs[18] <= 32'b0;
regs[19] <= 32'b0;
regs[20] <= 32'b0;
regs[21] <= 32'b0;
regs[22] <= 32'b0;
regs[23] <= 32'b0;
regs[24] <= 32'b0;
regs[25] <= 32'b0;
regs[26] <= 32'b0;
regs[27] <= 32'b0;
regs[28] <= 32'b0;
regs[29] <= 32'b0;
regs[30] <= 32'b0;
regs[31] <= 32'b0;
end else if ( we == `True ) begin
if (wr1Is == `True && wr1 != 5'd0)
regs[wr1] <= wd1;
end
end
endmodule | module RegFile (
clk, rst, we,
rr0, rr1, rd0, rd1,
lk0,
lkd0, lkd1,
wr0Is,
wr0, wd0,
wr1Is,
wr1, wd1
); |
input wire clk, rst, we;
input wire [4 : 0] rr0, rr1;
output reg [31 : 0] rd0, rd1;
input wire lk0;
output reg lkd0, lkd1;
input wire wr0Is, wr1Is;
input wire [4 : 0] wr0, wr1;
input wire [31 : 0] wd0, wd1;
reg [31 : 0] regs [31:0];
always @(*) begin
if (rst == `True) begin
rd0 <= 32'd0;
lkd0 <= `False;
end else begin
if (rr0 == 5'd0) begin
lkd0 <= `False;
rd0 <= 32'd0;
end else if ({lk0, wr0} == {1'b1, rr0}) begin
lkd0 <= `True;
end else if (wr0Is == `True && rr0 == wr0) begin
lkd0 <= `False;
rd0 <= wd0;
end else if (wr1Is == `True && rr0 == wr1) begin
lkd0 <= `False;
rd0 <= wd1;
end else begin
lkd0 <= `False;
rd0 <= regs[rr0];
end
end
end
always @(*) begin
if (rst == `True) begin
rd1 <= 32'd0;
lkd1 <= `False;
end else begin
if (rr1 == 5'd0) begin
lkd1 <= `False;
rd1 <= 32'd0;
end else if ({lk0, wr0} == {1'b1, rr1}) begin
lkd1 <= `True;
end else if (wr0Is == `True && rr1 == wr0) begin
lkd1 <= `False;
rd1 <= wd0;
end else if (wr1Is == `True && rr1 == wr1) begin
lkd1 <= `False;
rd1 <= wd1;
end else begin
lkd1 <= `False;
rd1 <= regs[rr1];
end
end
end
always @(posedge clk) begin
if ( rst == `True ) begin
regs[0] <= 32'b0;
regs[1] <= 32'b0;
regs[2] <= 32'b0;
regs[3] <= 32'b0;
regs[4] <= 32'b0;
regs[5] <= 32'b0;
regs[6] <= 32'b0;
regs[7] <= 32'b0;
regs[8] <= 32'b0;
regs[9] <= 32'b0;
regs[10] <= 32'b0;
regs[11] <= 32'b0;
regs[12] <= 32'b0;
regs[13] <= 32'b0;
regs[14] <= 32'b0;
regs[15] <= 32'b0;
regs[16] <= 32'b0;
regs[17] <= 32'b0;
regs[18] <= 32'b0;
regs[19] <= 32'b0;
regs[20] <= 32'b0;
regs[21] <= 32'b0;
regs[22] <= 32'b0;
regs[23] <= 32'b0;
regs[24] <= 32'b0;
regs[25] <= 32'b0;
regs[26] <= 32'b0;
regs[27] <= 32'b0;
regs[28] <= 32'b0;
regs[29] <= 32'b0;
regs[30] <= 32'b0;
regs[31] <= 32'b0;
end else if ( we == `True ) begin
if (wr1Is == `True && wr1 != 5'd0)
regs[wr1] <= wd1;
end
end
endmodule | 6 |
5,443 | data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v | 114,091,260 | reg_pc.v | v | 58 | 83 | [] | [] | [] | [(80, 113)] | null | null | 1: b'%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:2: Cannot find include file: def.v\n`include "def.v" \n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.v\n data/full_repos/permissive/114091260/src/CPU.srcs/sources,data/full_repos/permissive/114091260/def.v.sv\n def.v\n def.v.v\n def.v.sv\n obj_dir/def.v\n obj_dir/def.v.v\n obj_dir/def.v.sv\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:36: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n if (ce == `False) begin\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (ce == `False) begin\n ^\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:39: Define or directive not defined: \'`DEBUG\'\n if(`DEBUG == 1\'b1) $display("pc(%d)+4", pc);\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:50: Define or directive not defined: \'`True\'\n if (rst == `True) begin\n ^~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:51: Define or directive not defined: \'`False\'\n : ... Suggested alternative: \'`else\'\n ce <= `False;\n ^~~~~~\n%Error: data/full_repos/permissive/114091260/src/CPU.srcs/sources/reg_pc.v:53: Define or directive not defined: \'`True\'\n ce <= `True;\n ^~~~~\n%Error: Cannot continue\n' | 6,219 | module | module Reg_PC (
clk, rst, stall,
wIs, pcIn,
pc, ce
);
input wire clk, rst, stall, wIs;
input wire [31:0] pcIn;
output reg [31:0] pc;
output reg ce;
reg [31:0] regs[31:0];
always @ ( posedge clk ) begin
if (ce == `False) begin
pc <= 32'd0;
end else if (!stall) begin
if(`DEBUG == 1'b1) $display("pc(%d)+4", pc);
pc <= pc + 32'd4;
end
end
always @ ( * ) begin
if ({ce, wIs} == 2'b11) begin
pc <= pcIn;
end
end
always @ ( posedge clk ) begin
if (rst == `True) begin
ce <= `False;
end else begin
ce <= `True;
end
end
endmodule | module Reg_PC (
clk, rst, stall,
wIs, pcIn,
pc, ce
); |
input wire clk, rst, stall, wIs;
input wire [31:0] pcIn;
output reg [31:0] pc;
output reg ce;
reg [31:0] regs[31:0];
always @ ( posedge clk ) begin
if (ce == `False) begin
pc <= 32'd0;
end else if (!stall) begin
if(`DEBUG == 1'b1) $display("pc(%d)+4", pc);
pc <= pc + 32'd4;
end
end
always @ ( * ) begin
if ({ce, wIs} == 2'b11) begin
pc <= pcIn;
end
end
always @ ( posedge clk ) begin
if (rst == `True) begin
ce <= `False;
end else begin
ce <= `True;
end
end
endmodule | 6 |
5,445 | data/full_repos/permissive/114324064/src/cache_memory.v | 114,324,064 | cache_memory.v | v | 110 | 148 | [] | [] | [] | [(202, 308)] | null | null | 1: b'%Error: data/full_repos/permissive/114324064/src/cache_memory.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:22: Define or directive not defined: \'`DataAddrBus\'\n input wire[`DataAddrBus] ram_addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`DataAddrBus] ram_addr,\n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`DataBus] ram_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:24: Define or directive not defined: \'`DataBus\'\n input wire[`DataBus] ram_data_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:25: Define or directive not defined: \'`DataBus\'\n output reg[`DataBus] ram_data_o\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: Define or directive not defined: \'`InstBus\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:28: Define or directive not defined: \'`InstMemNum\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: Define or directive not defined: \'`ByteWidth\'\n reg[`ByteWidth] data_mem0[0:`DataMemNum-1]; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`ByteWidth] data_mem0[0:`DataMemNum-1]; \n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:29: Define or directive not defined: \'`DataMemNum\'\n reg[`ByteWidth] data_mem0[0:`DataMemNum-1]; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: Define or directive not defined: \'`ByteWidth\'\n reg[`ByteWidth] data_mem1[0:`DataMemNum-1];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`ByteWidth] data_mem1[0:`DataMemNum-1];\n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:30: Define or directive not defined: \'`DataMemNum\'\n reg[`ByteWidth] data_mem1[0:`DataMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: Define or directive not defined: \'`ByteWidth\'\n reg[`ByteWidth] data_mem2[0:`DataMemNum-1];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`ByteWidth] data_mem2[0:`DataMemNum-1];\n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:31: Define or directive not defined: \'`DataMemNum\'\n reg[`ByteWidth] data_mem2[0:`DataMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: Define or directive not defined: \'`ByteWidth\'\n reg[`ByteWidth] data_mem3[0:`DataMemNum-1]; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`ByteWidth] data_mem3[0:`DataMemNum-1]; \n ^\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:32: Define or directive not defined: \'`DataMemNum\'\n reg[`ByteWidth] data_mem3[0:`DataMemNum-1]; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:37: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:39: Define or directive not defined: \'`InstMemNum\'\n for (i = 0; i < `InstMemNum; i = i + 1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:66: Define or directive not defined: \'`ChipDisable\'\n if (ram_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:68: Define or directive not defined: \'`WriteEnable\'\n end else if(ram_we == `WriteEnable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:70: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:76: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:82: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:88: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:97: Define or directive not defined: \'`ChipDisable\'\n if (ram_ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:98: Define or directive not defined: \'`ZeroWord\'\n ram_data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:99: Define or directive not defined: \'`WriteDisable\'\n end else if(ram_we == `WriteDisable) begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:100: Define or directive not defined: \'`DataMemNumLog2\'\n ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:101: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem2[ram_addr[`DataMemNumLog2+1:2]],\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:102: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem1[ram_addr[`DataMemNumLog2+1:2]],\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:103: Define or directive not defined: \'`DataMemNumLog2\'\n data_mem0[ram_addr[`DataMemNumLog2+1:2]]};\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cache_memory.v:105: Define or directive not defined: \'`ZeroWord\'\n ram_data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: Exiting due to 37 error(s)\n' | 6,222 | module | module cache_memory
#(
parameter ADDR_WIDTH = 32,
parameter SELECT_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter BENCH_WIDTH = DATA_WIDTH * (1 << (SELECT_WIDTH-2))
)
(
input wire clk,
input wire ic_read_i,
input wire[ADDR_WIDTH-1:0] ic_addr_i,
output reg[BENCH_WIDTH-1:0] ic_data_o,
output reg ic_done_o,
input wire ram_ce,
input wire ram_we,
input wire[`DataAddrBus] ram_addr,
input wire[3:0] ram_sel,
input wire[`DataBus] ram_data_i,
output reg[`DataBus] ram_data_o
);
reg[`InstBus] inst_mem[0:`InstMemNum-1];
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
reg[3:0] cnt;
integer i;
initial begin
$readmemh ("D:\\Users\\DELL\\Desktop\\inst_rom.data", inst_mem);
for (i = 0; i < `InstMemNum; i = i + 1) begin
data_mem3[i] <= inst_mem[i][7:0];
data_mem2[i] <= inst_mem[i][15:8];
data_mem1[i] <= inst_mem[i][23:16];
data_mem0[i] <= inst_mem[i][31:24];
end
cnt <= 0;
end
always @ (posedge clk) begin
cnt <= cnt + 1;
end
always @ (*) begin
ic_data_o[31:0] <= {data_mem3[(ic_addr_i>>2)+0], data_mem2[(ic_addr_i>>2)+0], data_mem1[(ic_addr_i>>2)+0], data_mem0[(ic_addr_i>>2)+0]};
ic_data_o[63:32] <= {data_mem3[(ic_addr_i>>2)+1], data_mem2[(ic_addr_i>>2)+1], data_mem1[(ic_addr_i>>2)+1], data_mem0[(ic_addr_i>>2)+1]};
ic_data_o[95:64] <= {data_mem3[(ic_addr_i>>2)+2], data_mem2[(ic_addr_i>>2)+2], data_mem1[(ic_addr_i>>2)+2], data_mem0[(ic_addr_i>>2)+2]};
ic_data_o[127:96] <= {data_mem3[(ic_addr_i>>2)+3], data_mem2[(ic_addr_i>>2)+3], data_mem1[(ic_addr_i>>2)+3], data_mem0[(ic_addr_i>>2)+3]};
if (cnt == 0) begin
ic_done_o <= 1'b1;
cnt <= cnt + 1;
end else begin
ic_done_o <= 1'b0;
end
end
always @ (posedge clk) begin
if (ram_ce == `ChipDisable) begin
end else if(ram_we == `WriteEnable) begin
if (ram_sel[3] == 1'b1) begin
data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[31:24]);
end
end
if (ram_sel[2] == 1'b1) begin
data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[23:16]);
end
end
if (ram_sel[1] == 1'b1) begin
data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[15:8]);
end
end
if (ram_sel[0] == 1'b1) begin
data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[7:0]);
end
end
end
end
always @ (*) begin
if (ram_ce == `ChipDisable) begin
ram_data_o <= `ZeroWord;
end else if(ram_we == `WriteDisable) begin
ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],
data_mem2[ram_addr[`DataMemNumLog2+1:2]],
data_mem1[ram_addr[`DataMemNumLog2+1:2]],
data_mem0[ram_addr[`DataMemNumLog2+1:2]]};
end else begin
ram_data_o <= `ZeroWord;
end
end
endmodule | module cache_memory
#(
parameter ADDR_WIDTH = 32,
parameter SELECT_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter BENCH_WIDTH = DATA_WIDTH * (1 << (SELECT_WIDTH-2))
)
(
input wire clk,
input wire ic_read_i,
input wire[ADDR_WIDTH-1:0] ic_addr_i,
output reg[BENCH_WIDTH-1:0] ic_data_o,
output reg ic_done_o,
input wire ram_ce,
input wire ram_we,
input wire[`DataAddrBus] ram_addr,
input wire[3:0] ram_sel,
input wire[`DataBus] ram_data_i,
output reg[`DataBus] ram_data_o
); |
reg[`InstBus] inst_mem[0:`InstMemNum-1];
reg[`ByteWidth] data_mem0[0:`DataMemNum-1];
reg[`ByteWidth] data_mem1[0:`DataMemNum-1];
reg[`ByteWidth] data_mem2[0:`DataMemNum-1];
reg[`ByteWidth] data_mem3[0:`DataMemNum-1];
reg[3:0] cnt;
integer i;
initial begin
$readmemh ("D:\\Users\\DELL\\Desktop\\inst_rom.data", inst_mem);
for (i = 0; i < `InstMemNum; i = i + 1) begin
data_mem3[i] <= inst_mem[i][7:0];
data_mem2[i] <= inst_mem[i][15:8];
data_mem1[i] <= inst_mem[i][23:16];
data_mem0[i] <= inst_mem[i][31:24];
end
cnt <= 0;
end
always @ (posedge clk) begin
cnt <= cnt + 1;
end
always @ (*) begin
ic_data_o[31:0] <= {data_mem3[(ic_addr_i>>2)+0], data_mem2[(ic_addr_i>>2)+0], data_mem1[(ic_addr_i>>2)+0], data_mem0[(ic_addr_i>>2)+0]};
ic_data_o[63:32] <= {data_mem3[(ic_addr_i>>2)+1], data_mem2[(ic_addr_i>>2)+1], data_mem1[(ic_addr_i>>2)+1], data_mem0[(ic_addr_i>>2)+1]};
ic_data_o[95:64] <= {data_mem3[(ic_addr_i>>2)+2], data_mem2[(ic_addr_i>>2)+2], data_mem1[(ic_addr_i>>2)+2], data_mem0[(ic_addr_i>>2)+2]};
ic_data_o[127:96] <= {data_mem3[(ic_addr_i>>2)+3], data_mem2[(ic_addr_i>>2)+3], data_mem1[(ic_addr_i>>2)+3], data_mem0[(ic_addr_i>>2)+3]};
if (cnt == 0) begin
ic_done_o <= 1'b1;
cnt <= cnt + 1;
end else begin
ic_done_o <= 1'b0;
end
end
always @ (posedge clk) begin
if (ram_ce == `ChipDisable) begin
end else if(ram_we == `WriteEnable) begin
if (ram_sel[3] == 1'b1) begin
data_mem3[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[31:24];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[31:24]);
end
end
if (ram_sel[2] == 1'b1) begin
data_mem2[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[23:16];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[23:16]);
end
end
if (ram_sel[1] == 1'b1) begin
data_mem1[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[15:8];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[15:8]);
end
end
if (ram_sel[0] == 1'b1) begin
data_mem0[ram_addr[`DataMemNumLog2+1:2]] <= ram_data_i[7:0];
if (ram_addr == 32'h00000104) begin
$write("%c", ram_data_i[7:0]);
end
end
end
end
always @ (*) begin
if (ram_ce == `ChipDisable) begin
ram_data_o <= `ZeroWord;
end else if(ram_we == `WriteDisable) begin
ram_data_o <= {data_mem3[ram_addr[`DataMemNumLog2+1:2]],
data_mem2[ram_addr[`DataMemNumLog2+1:2]],
data_mem1[ram_addr[`DataMemNumLog2+1:2]],
data_mem0[ram_addr[`DataMemNumLog2+1:2]]};
end else begin
ram_data_o <= `ZeroWord;
end
end
endmodule | 10 |
5,446 | data/full_repos/permissive/114324064/src/cpu-riscv.v | 114,324,064 | cpu-riscv.v | v | 297 | 56 | [] | [] | [] | [(202, 495)] | null | null | 1: b'%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:11: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] rom_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n output wire[`RegBus] rom_addr_o,\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] ram_data_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ram_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:16: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] ram_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:17: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] ram_data_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[3:0] ram_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire ram_ce_o\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:25: Define or directive not defined: \'`RegBus\'\n wire [`RegBus] id_branch_target_addr_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`RegBus] id_branch_target_addr_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:32: syntax error, unexpected IDENTIFIER\n ctrl ctrl0(\n ^~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:40: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] pc;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] pc;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:52: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] inst;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] inst;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:69: Define or directive not defined: \'`InstAddrBus\'\n wire[`InstAddrBus] id_pc_i;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] id_pc_i;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:70: Define or directive not defined: \'`InstBus\'\n wire[`InstBus] id_inst_i;\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`InstBus] id_inst_i;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:83: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] id_aluop_o;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] id_aluop_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:84: Define or directive not defined: \'`AluSelBus\'\n wire[`AluSelBus] id_alusel_o;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluSelBus] id_alusel_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:85: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg1_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg1_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:86: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_reg2_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_reg2_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:88: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] id_wd_o;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] id_wd_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:89: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_link_addr_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:89: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_link_addr_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:90: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] id_offset_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:90: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] id_offset_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:96: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg1_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg1_data;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:97: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg2_data;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:97: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg2_data;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:98: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg1_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:98: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg1_addr;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:99: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] reg2_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:99: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] reg2_addr;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:102: Define or directive not defined: \'`RegAddrBus\'\n wire[`RegAddrBus] ex_wd_o;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:102: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegAddrBus] ex_wd_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:103: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_wdata_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:103: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_wdata_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:104: Define or directive not defined: \'`AluOpBus\'\n wire[`AluOpBus] ex_aluop_o;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:104: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`AluOpBus] ex_aluop_o;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:105: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] ex_mem_addr_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv.v:105: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] ex_mem_addr_o;\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,223 | module | module cpu_riscv(
input wire clk,
input wire rst,
input wire[127:0] rom_data_i,
input wire rom_done_i,
output wire[`RegBus] rom_addr_o,
output wire rom_read_o,
input wire[`RegBus] ram_data_i,
output wire[`RegBus] ram_addr_o,
output wire[`RegBus] ram_data_o,
output wire ram_we_o,
output wire[3:0] ram_sel_o,
output wire ram_ce_o
);
wire id_branch_flag_o;
wire [`RegBus] id_branch_target_addr_o;
wire[5:0] stall;
wire stallreq_from_ic;
wire stallreq_from_id;
ctrl ctrl0(
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ic(stallreq_from_ic),
.stall(stall)
);
wire[`InstAddrBus] pc;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(stall),
.branch_flag_i(id_branch_flag_o),
.branch_target_addr_i(id_branch_target_addr_o),
.pc(pc)
);
wire[`InstBus] inst;
i_cache i_cache0(
.clk(clk),
.rst(rst),
.core_addr_i(pc),
.core_data_o(inst),
.core_stallreq_o(stallreq_from_ic),
.mem_data_i(rom_data_i),
.mem_done_i(rom_done_i),
.mem_read_o(rom_read_o),
.mem_addr_o(rom_addr_o)
);
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(stall),
.if_pc(pc),
.if_inst(inst),
.id_pc(id_pc_i),
.id_inst(id_inst_i)
);
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire[`RegBus] id_link_addr_o;
wire[`RegBus] id_offset_o;
wire id_next_inst_invalid_o;
wire id_inst_invalid_i;
wire reg1_read;
wire reg2_read;
wire[`RegBus] reg1_data;
wire[`RegBus] reg2_data;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire[`AluOpBus] ex_aluop_o;
wire[`RegBus] ex_mem_addr_o;
wire[`RegBus] ex_reg2_o;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire wb_wreg_i;
wire[`RegAddrBus] wb_wd_i;
wire[`RegBus] wb_wdata_i;
id id0(
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.ex_wreg_i(ex_wreg_o),
.ex_wdata_i(ex_wdata_o),
.ex_wd_i(ex_wd_o),
.mem_wreg_i(mem_wreg_o),
.mem_wdata_i(mem_wdata_o),
.mem_wd_i(mem_wd_o),
.ex_aluop_i(ex_aluop_o),
.reg1_data_i(reg1_data),
.reg2_data_i(reg2_data),
.inst_invalid_i(id_inst_invalid_i),
.reg1_read_o(reg1_read),
.reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr),
.reg2_addr_o(reg2_addr),
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.wd_o(id_wd_o),
.wreg_o(id_wreg_o),
.offset_o(id_offset_o),
.next_inst_invalid_o(id_next_inst_invalid_o),
.branch_flag_o(id_branch_flag_o),
.branch_target_addr_o(id_branch_target_addr_o),
.link_addr_o(id_link_addr_o),
.stallreq(stallreq_from_id)
);
regfile regfile0(
.clk(clk),
.rst(rst),
.we(wb_wreg_i),
.waddr(wb_wd_i),
.wdata(wb_wdata_i),
.re1(reg1_read),
.raddr1(reg1_addr),
.rdata1(reg1_data),
.re2(reg2_read),
.raddr2(reg2_addr),
.rdata2(reg2_data)
);
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire[`RegBus] ex_link_addr_i;
wire[`RegBus] ex_offset_i;
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(stall),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_wd(id_wd_o),
.id_wreg(id_wreg_o),
.id_link_addr(id_link_addr_o),
.id_offset(id_offset_o),
.id_next_inst_invalid(id_next_inst_invalid_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_wd(ex_wd_i),
.ex_wreg(ex_wreg_i),
.ex_link_addr(ex_link_addr_i),
.ex_offset(ex_offset_i),
.id_inst_invalid(id_inst_invalid_i)
);
ex ex0(
.rst(rst),
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.wd_i(ex_wd_i),
.wreg_i(ex_wreg_i),
.link_addr_i(ex_link_addr_i),
.offset_i(ex_offset_i),
.wd_o(ex_wd_o),
.wreg_o(ex_wreg_o),
.wdata_o(ex_wdata_o),
.aluop_o(ex_aluop_o),
.mem_addr_o(ex_mem_addr_o),
.reg2_o(ex_reg2_o)
);
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire[`AluOpBus] mem_aluop_i;
wire[`RegBus] mem_mem_addr_i;
wire[`RegBus] mem_reg2_i;
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(stall),
.ex_wd(ex_wd_o),
.ex_wreg(ex_wreg_o),
.ex_wdata(ex_wdata_o),
.ex_aluop(ex_aluop_o),
.ex_mem_addr(ex_mem_addr_o),
.ex_reg2(ex_reg2_o),
.mem_wd(mem_wd_i),
.mem_wreg(mem_wreg_i),
.mem_wdata(mem_wdata_i),
.mem_aluop(mem_aluop_i),
.mem_mem_addr(mem_mem_addr_i),
.mem_reg2(mem_reg2_i)
);
mem mem0(
.rst(rst),
.wd_i(mem_wd_i),
.wreg_i(mem_wreg_i),
.wdata_i(mem_wdata_i),
.aluop_i(mem_aluop_i),
.mem_addr_i(mem_mem_addr_i),
.reg2_i(mem_reg2_i),
.mem_data_i(ram_data_i),
.wd_o(mem_wd_o),
.wreg_o(mem_wreg_o),
.wdata_o(mem_wdata_o),
.mem_addr_o(ram_addr_o),
.mem_we_o(ram_we_o),
.mem_sel_o(ram_sel_o),
.mem_data_o(ram_data_o),
.mem_ce_o(ram_ce_o)
);
mem_wb mem_wb0(
.clk(clk),
.rst(rst),
.stall(stall),
.mem_wd(mem_wd_o),
.mem_wreg(mem_wreg_o),
.mem_wdata(mem_wdata_o),
.wb_wd(wb_wd_i),
.wb_wreg(wb_wreg_i),
.wb_wdata(wb_wdata_i)
);
endmodule | module cpu_riscv(
input wire clk,
input wire rst,
input wire[127:0] rom_data_i,
input wire rom_done_i,
output wire[`RegBus] rom_addr_o,
output wire rom_read_o,
input wire[`RegBus] ram_data_i,
output wire[`RegBus] ram_addr_o,
output wire[`RegBus] ram_data_o,
output wire ram_we_o,
output wire[3:0] ram_sel_o,
output wire ram_ce_o
); |
wire id_branch_flag_o;
wire [`RegBus] id_branch_target_addr_o;
wire[5:0] stall;
wire stallreq_from_ic;
wire stallreq_from_id;
ctrl ctrl0(
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ic(stallreq_from_ic),
.stall(stall)
);
wire[`InstAddrBus] pc;
pc_reg pc_reg0(
.clk(clk),
.rst(rst),
.stall(stall),
.branch_flag_i(id_branch_flag_o),
.branch_target_addr_i(id_branch_target_addr_o),
.pc(pc)
);
wire[`InstBus] inst;
i_cache i_cache0(
.clk(clk),
.rst(rst),
.core_addr_i(pc),
.core_data_o(inst),
.core_stallreq_o(stallreq_from_ic),
.mem_data_i(rom_data_i),
.mem_done_i(rom_done_i),
.mem_read_o(rom_read_o),
.mem_addr_o(rom_addr_o)
);
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
if_id if_id0(
.clk(clk),
.rst(rst),
.stall(stall),
.if_pc(pc),
.if_inst(inst),
.id_pc(id_pc_i),
.id_inst(id_inst_i)
);
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire id_wreg_o;
wire[`RegAddrBus] id_wd_o;
wire[`RegBus] id_link_addr_o;
wire[`RegBus] id_offset_o;
wire id_next_inst_invalid_o;
wire id_inst_invalid_i;
wire reg1_read;
wire reg2_read;
wire[`RegBus] reg1_data;
wire[`RegBus] reg2_data;
wire[`RegAddrBus] reg1_addr;
wire[`RegAddrBus] reg2_addr;
wire ex_wreg_o;
wire[`RegAddrBus] ex_wd_o;
wire[`RegBus] ex_wdata_o;
wire[`AluOpBus] ex_aluop_o;
wire[`RegBus] ex_mem_addr_o;
wire[`RegBus] ex_reg2_o;
wire mem_wreg_o;
wire[`RegAddrBus] mem_wd_o;
wire[`RegBus] mem_wdata_o;
wire wb_wreg_i;
wire[`RegAddrBus] wb_wd_i;
wire[`RegBus] wb_wdata_i;
id id0(
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.ex_wreg_i(ex_wreg_o),
.ex_wdata_i(ex_wdata_o),
.ex_wd_i(ex_wd_o),
.mem_wreg_i(mem_wreg_o),
.mem_wdata_i(mem_wdata_o),
.mem_wd_i(mem_wd_o),
.ex_aluop_i(ex_aluop_o),
.reg1_data_i(reg1_data),
.reg2_data_i(reg2_data),
.inst_invalid_i(id_inst_invalid_i),
.reg1_read_o(reg1_read),
.reg2_read_o(reg2_read),
.reg1_addr_o(reg1_addr),
.reg2_addr_o(reg2_addr),
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.wd_o(id_wd_o),
.wreg_o(id_wreg_o),
.offset_o(id_offset_o),
.next_inst_invalid_o(id_next_inst_invalid_o),
.branch_flag_o(id_branch_flag_o),
.branch_target_addr_o(id_branch_target_addr_o),
.link_addr_o(id_link_addr_o),
.stallreq(stallreq_from_id)
);
regfile regfile0(
.clk(clk),
.rst(rst),
.we(wb_wreg_i),
.waddr(wb_wd_i),
.wdata(wb_wdata_i),
.re1(reg1_read),
.raddr1(reg1_addr),
.rdata1(reg1_data),
.re2(reg2_read),
.raddr2(reg2_addr),
.rdata2(reg2_data)
);
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire ex_wreg_i;
wire[`RegAddrBus] ex_wd_i;
wire[`RegBus] ex_link_addr_i;
wire[`RegBus] ex_offset_i;
id_ex id_ex0(
.clk(clk),
.rst(rst),
.stall(stall),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_wd(id_wd_o),
.id_wreg(id_wreg_o),
.id_link_addr(id_link_addr_o),
.id_offset(id_offset_o),
.id_next_inst_invalid(id_next_inst_invalid_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_wd(ex_wd_i),
.ex_wreg(ex_wreg_i),
.ex_link_addr(ex_link_addr_i),
.ex_offset(ex_offset_i),
.id_inst_invalid(id_inst_invalid_i)
);
ex ex0(
.rst(rst),
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.wd_i(ex_wd_i),
.wreg_i(ex_wreg_i),
.link_addr_i(ex_link_addr_i),
.offset_i(ex_offset_i),
.wd_o(ex_wd_o),
.wreg_o(ex_wreg_o),
.wdata_o(ex_wdata_o),
.aluop_o(ex_aluop_o),
.mem_addr_o(ex_mem_addr_o),
.reg2_o(ex_reg2_o)
);
wire mem_wreg_i;
wire[`RegAddrBus] mem_wd_i;
wire[`RegBus] mem_wdata_i;
wire[`AluOpBus] mem_aluop_i;
wire[`RegBus] mem_mem_addr_i;
wire[`RegBus] mem_reg2_i;
ex_mem ex_mem0(
.clk(clk),
.rst(rst),
.stall(stall),
.ex_wd(ex_wd_o),
.ex_wreg(ex_wreg_o),
.ex_wdata(ex_wdata_o),
.ex_aluop(ex_aluop_o),
.ex_mem_addr(ex_mem_addr_o),
.ex_reg2(ex_reg2_o),
.mem_wd(mem_wd_i),
.mem_wreg(mem_wreg_i),
.mem_wdata(mem_wdata_i),
.mem_aluop(mem_aluop_i),
.mem_mem_addr(mem_mem_addr_i),
.mem_reg2(mem_reg2_i)
);
mem mem0(
.rst(rst),
.wd_i(mem_wd_i),
.wreg_i(mem_wreg_i),
.wdata_i(mem_wdata_i),
.aluop_i(mem_aluop_i),
.mem_addr_i(mem_mem_addr_i),
.reg2_i(mem_reg2_i),
.mem_data_i(ram_data_i),
.wd_o(mem_wd_o),
.wreg_o(mem_wreg_o),
.wdata_o(mem_wdata_o),
.mem_addr_o(ram_addr_o),
.mem_we_o(ram_we_o),
.mem_sel_o(ram_sel_o),
.mem_data_o(ram_data_o),
.mem_ce_o(ram_ce_o)
);
mem_wb mem_wb0(
.clk(clk),
.rst(rst),
.stall(stall),
.mem_wd(mem_wd_o),
.mem_wreg(mem_wreg_o),
.mem_wdata(mem_wdata_o),
.wb_wd(wb_wd_i),
.wb_wreg(wb_wreg_i),
.wb_wdata(wb_wdata_i)
);
endmodule | 10 |
5,447 | data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v | 114,324,064 | cpu-riscv_min_sopc.v | v | 55 | 33 | [] | [] | [] | null | line:8: before: "]" | null | 1: b"%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:8: Define or directive not defined: '`InstAddrBus'\n wire[`InstAddrBus] rom_addr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:8: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n wire[`InstAddrBus] rom_addr;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:15: Define or directive not defined: '`RegBus'\n wire[`RegBus] ram_addr;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:15: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n wire[`RegBus] ram_addr;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:16: Define or directive not defined: '`RegBus'\n wire[`RegBus] ram_data_i;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:16: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n wire[`RegBus] ram_data_i;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:17: Define or directive not defined: '`RegBus'\n wire[`RegBus] ram_data_o;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc.v:17: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n wire[`RegBus] ram_data_o;\n ^\n%Error: Exiting due to 8 error(s)\n" | 6,224 | module | module cpu_riscv_min_sopc (
input wire clk,
input wire rst
);
wire[`InstAddrBus] rom_addr;
wire[127:0] rom_data;
wire rom_done;
wire rom_read;
wire ram_we;
wire[`RegBus] ram_addr;
wire[`RegBus] ram_data_i;
wire[`RegBus] ram_data_o;
wire[3:0] ram_sel;
wire ram_ce;
cpu_riscv cpu_riscv0(
.clk(clk),
.rst(rst),
.rom_data_i(rom_data),
.rom_done_i(rom_done),
.rom_addr_o(rom_addr),
.rom_read_o(rom_read),
.ram_we_o(ram_we),
.ram_addr_o(ram_addr),
.ram_sel_o(ram_sel),
.ram_data_o(ram_data_i),
.ram_data_i(ram_data_o),
.ram_ce_o(ram_ce)
);
cache_memory cache_memory0(
.clk(clk),
.ic_read_i(rom_read),
.ic_addr_i(rom_addr),
.ic_data_o(rom_data),
.ic_done_o(rom_done),
.ram_we(ram_we),
.ram_addr(ram_addr),
.ram_sel(ram_sel),
.ram_data_i(ram_data_i),
.ram_data_o(ram_data_o),
.ram_ce(ram_ce)
);
endmodule | module cpu_riscv_min_sopc (
input wire clk,
input wire rst
); |
wire[`InstAddrBus] rom_addr;
wire[127:0] rom_data;
wire rom_done;
wire rom_read;
wire ram_we;
wire[`RegBus] ram_addr;
wire[`RegBus] ram_data_i;
wire[`RegBus] ram_data_o;
wire[3:0] ram_sel;
wire ram_ce;
cpu_riscv cpu_riscv0(
.clk(clk),
.rst(rst),
.rom_data_i(rom_data),
.rom_done_i(rom_done),
.rom_addr_o(rom_addr),
.rom_read_o(rom_read),
.ram_we_o(ram_we),
.ram_addr_o(ram_addr),
.ram_sel_o(ram_sel),
.ram_data_o(ram_data_i),
.ram_data_i(ram_data_o),
.ram_ce_o(ram_ce)
);
cache_memory cache_memory0(
.clk(clk),
.ic_read_i(rom_read),
.ic_addr_i(rom_addr),
.ic_data_o(rom_data),
.ic_done_o(rom_done),
.ram_we(ram_we),
.ram_addr(ram_addr),
.ram_sel(ram_sel),
.ram_data_i(ram_data_i),
.ram_data_o(ram_data_o),
.ram_ce(ram_ce)
);
endmodule | 10 |
5,448 | data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v | 114,324,064 | cpu-riscv_min_sopc_tb.v | v | 26 | 44 | [] | [] | [] | null | line:15: before: ";" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n forever #5 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:15: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:15: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: Define or directive not defined: \'`RstDisable\'\n #195 rst = `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #195 rst = `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/114324064/src/cpu-riscv_min_sopc_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #100000 $stop;\n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 6,225 | module | module cpu_riscv_min_sopc_tb ();
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #5 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#100000 $stop;
end
cpu_riscv_min_sopc cpu_riscv_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | module cpu_riscv_min_sopc_tb (); |
reg CLOCK_50;
reg rst;
initial begin
CLOCK_50 = 1'b0;
forever #5 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#100000 $stop;
end
cpu_riscv_min_sopc cpu_riscv_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
endmodule | 10 |
5,449 | data/full_repos/permissive/114324064/src/ex.v | 114,324,064 | ex.v | v | 147 | 85 | [] | [] | [] | [(202, 345)] | null | null | 1: b'%Error: data/full_repos/permissive/114324064/src/ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/ex.v:8: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus] aluop_i,\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:9: Define or directive not defined: \'`AluSelBus\'\n input wire[`AluSelBus] alusel_i,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:10: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:12: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] link_addr_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] link_addr_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] offset_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:19: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:21: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wdata_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:21: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:23: Define or directive not defined: \'`AluOpBus\'\n output wire[`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:24: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] mem_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:25: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus] reg2_o\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:28: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] logicout;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] logicout;\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:29: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] shiftres;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] shiftres;\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:30: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] arithmeticres;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] arithmeticres;\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:34: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg2_i_mux;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg2_i_mux;\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:35: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] reg1_i_not;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] reg1_i_not;\n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:36: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] result_sum; \n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] result_sum; \n ^\n%Error: data/full_repos/permissive/114324064/src/ex.v:39: Define or directive not defined: \'`NoStop\'\n assign stallreq = `NoStop;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:40: Define or directive not defined: \'`EXE_SUB_OP\'\n assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:41: Define or directive not defined: \'`EXE_SLT_OP\'\n (aluop_i == `EXE_SLT_OP)) ?\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:44: Define or directive not defined: \'`EXE_SLT_OP\'\n assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:57: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:58: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:61: Define or directive not defined: \'`EXE_OR_OP\'\n `EXE_OR_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:64: Define or directive not defined: \'`EXE_AND_OP\'\n `EXE_AND_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:67: Define or directive not defined: \'`EXE_XOR_OP\'\n `EXE_XOR_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:70: Define or directive not defined: \'`EXE_LUI_OP\'\n `EXE_LUI_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:74: Define or directive not defined: \'`ZeroWord\'\n logicout <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:81: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:82: Define or directive not defined: \'`ZeroWord\'\n shiftres <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:85: Define or directive not defined: \'`EXE_SLL_OP\'\n `EXE_SLL_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:88: Define or directive not defined: \'`EXE_SRL_OP\'\n `EXE_SRL_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:91: Define or directive not defined: \'`EXE_SRA_OP\'\n `EXE_SRA_OP: begin \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:96: Define or directive not defined: \'`ZeroWord\'\n shiftres <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:103: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:104: Define or directive not defined: \'`ZeroWord\'\n arithmeticres <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:107: Define or directive not defined: \'`EXE_SLT_OP\'\n `EXE_SLT_OP, `EXE_SLTU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:107: Define or directive not defined: \'`EXE_SLTU_OP\'\n `EXE_SLT_OP, `EXE_SLTU_OP: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/ex.v:110: Define or directive not defined: \'`EXE_ADD_OP\'\n `EXE_ADD_OP, `EXE_ADDI_OP: begin\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,230 | module | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] link_addr_i,
input wire[`RegBus] offset_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output wire[`AluOpBus] aluop_o,
output wire[`RegBus] mem_addr_o,
output wire[`RegBus] reg2_o
);
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] arithmeticres;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
assign stallreq = `NoStop;
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||
(aluop_i == `EXE_SLT_OP)) ?
(~reg2_i) + 1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31]) ||
(reg1_i[31] && reg1_i[31] && result_sum[31])) :
(reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
assign aluop_o = aluop_i;
assign mem_addr_o = reg1_i + offset_i;
assign reg2_o = reg2_i;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
`EXE_LUI_OP: begin
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg1_i << reg2_i[4:0];
end
`EXE_SRL_OP: begin
shiftres <= reg1_i >> reg2_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg1_i[31]}} << (6'd32 - {1'b0,reg2_i[4:0]})) |
(reg1_i >> reg2_i[4:0]);
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2;
end
`EXE_ADD_OP, `EXE_ADDI_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP: begin
arithmeticres <= result_sum;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
always @ ( * ) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case (alusel_i)
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_JUMP_BRANCH: begin
wdata_o <= link_addr_i;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | module ex(
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] link_addr_i,
input wire[`RegBus] offset_i,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o,
output wire[`AluOpBus] aluop_o,
output wire[`RegBus] mem_addr_o,
output wire[`RegBus] reg2_o
); |
reg[`RegBus] logicout;
reg[`RegBus] shiftres;
reg[`RegBus] arithmeticres;
wire reg1_eq_reg2;
wire reg1_lt_reg2;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
assign stallreq = `NoStop;
assign reg2_i_mux = ((aluop_i == `EXE_SUB_OP) ||
(aluop_i == `EXE_SLT_OP)) ?
(~reg2_i) + 1 : reg2_i;
assign result_sum = reg1_i + reg2_i_mux;
assign reg1_lt_reg2 = (aluop_i == `EXE_SLT_OP) ?
((reg1_i[31] && !reg2_i[31]) ||
(!reg1_i[31] && !reg2_i[31] && result_sum[31]) ||
(reg1_i[31] && reg1_i[31] && result_sum[31])) :
(reg1_i < reg2_i);
assign reg1_i_not = ~reg1_i;
assign aluop_o = aluop_i;
assign mem_addr_o = reg1_i + offset_i;
assign reg2_o = reg2_i;
always @ (*) begin
if(rst == `RstEnable) begin
logicout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OR_OP: begin
logicout <= reg1_i | reg2_i;
end
`EXE_AND_OP: begin
logicout <= reg1_i & reg2_i;
end
`EXE_XOR_OP: begin
logicout <= reg1_i ^ reg2_i;
end
`EXE_LUI_OP: begin
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
shiftres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL_OP: begin
shiftres <= reg1_i << reg2_i[4:0];
end
`EXE_SRL_OP: begin
shiftres <= reg1_i >> reg2_i[4:0];
end
`EXE_SRA_OP: begin
shiftres <= ({32{reg1_i[31]}} << (6'd32 - {1'b0,reg2_i[4:0]})) |
(reg1_i >> reg2_i[4:0]);
end
default: begin
shiftres <= `ZeroWord;
end
endcase
end
end
always @ (*) begin
if(rst == `RstEnable) begin
arithmeticres <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLT_OP, `EXE_SLTU_OP: begin
arithmeticres <= reg1_lt_reg2;
end
`EXE_ADD_OP, `EXE_ADDI_OP: begin
arithmeticres <= result_sum;
end
`EXE_SUB_OP: begin
arithmeticres <= result_sum;
end
default: begin
arithmeticres <= `ZeroWord;
end
endcase
end
end
always @ ( * ) begin
wd_o <= wd_i;
wreg_o <= wreg_i;
case (alusel_i)
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftres;
end
`EXE_RES_ARITHMETIC: begin
wdata_o <= arithmeticres;
end
`EXE_RES_JUMP_BRANCH: begin
wdata_o <= link_addr_i;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endmodule | 10 |
5,450 | data/full_repos/permissive/114324064/src/fifo.v | 114,324,064 | fifo.v | v | 58 | 49 | [] | [] | [] | null | Syntax Error | data/verilator_xmls/7f5026b5-fd2b-4649-b9f4-013535516568.xml | null | 6,232 | module | module fifo
#(
parameter size_bit = 3,
parameter width = 8
)
(
input wire clk,
input wire rst,
input wire read_flag,
output reg[width-1:0] read_data,
input wire write_flag,
input reg[width-1:0] write_data,
output reg empty,
output reg full
);
localparam size = 1 << size_bit;
reg[width-1:0] buffer[size-1:0];
reg[size_bit-1:0] read_ptr;
reg[size_bit-1:0] write_ptr;
reg[size_bit:0] buffer_size;
assign empty = buffer_size == 0;
assign full = buffer_size == size;
wire read, write;
assign read = read_flag && !empty;
assign write = write_flag && !full;
assign read_data = buffer[read_ptr];
integer i;
always @(negedge clk or posedge rst) begin
if (rst) begin
read_ptr <= 0;
write_ptr <= 0;
buffer_size <= 0;
for (i = 0; i < size; i = i + 1)
buffer[i] <= 0;
end else begin
if (read && write) begin
buffer[write_ptr] <= write_data;
read_ptr <= read_ptr + 1;
write_ptr <= write_ptr + 1;
end else if (read) begin
read_ptr <= read_ptr + 1;
buffer_size <= buffer_size - 1;
end else if (write) begin
buffer[write_ptr] <= write_data;
write_ptr <= write_ptr + 1;
buffer_size <= buffer_size + 1;
end
end
end
endmodule | module fifo
#(
parameter size_bit = 3,
parameter width = 8
)
(
input wire clk,
input wire rst,
input wire read_flag,
output reg[width-1:0] read_data,
input wire write_flag,
input reg[width-1:0] write_data,
output reg empty,
output reg full
); |
localparam size = 1 << size_bit;
reg[width-1:0] buffer[size-1:0];
reg[size_bit-1:0] read_ptr;
reg[size_bit-1:0] write_ptr;
reg[size_bit:0] buffer_size;
assign empty = buffer_size == 0;
assign full = buffer_size == size;
wire read, write;
assign read = read_flag && !empty;
assign write = write_flag && !full;
assign read_data = buffer[read_ptr];
integer i;
always @(negedge clk or posedge rst) begin
if (rst) begin
read_ptr <= 0;
write_ptr <= 0;
buffer_size <= 0;
for (i = 0; i < size; i = i + 1)
buffer[i] <= 0;
end else begin
if (read && write) begin
buffer[write_ptr] <= write_data;
read_ptr <= read_ptr + 1;
write_ptr <= write_ptr + 1;
end else if (read) begin
read_ptr <= read_ptr + 1;
buffer_size <= buffer_size - 1;
end else if (write) begin
buffer[write_ptr] <= write_data;
write_ptr <= write_ptr + 1;
buffer_size <= buffer_size + 1;
end
end
end
endmodule | 10 |
5,451 | data/full_repos/permissive/114324064/src/id.v | 114,324,064 | id.v | v | 437 | 98 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114324064/src/id.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/id.v:11: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] pc_i,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] pc_i,\n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:12: Define or directive not defined: \'`InstBus\'\n input wire[`InstBus] inst_i,\n ^~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg1_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] ex_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:20: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] ex_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:21: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] ex_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] mem_wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:25: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:26: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] mem_wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:29: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] ex_aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg reg2_read_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:34: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg1_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:35: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] reg2_addr_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:38: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus] aluop_o,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:39: Define or directive not defined: \'`AluSelBus\'\n output reg[`AluSelBus] alusel_o,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:40: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg1_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:41: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] reg2_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:42: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output wire stallreq,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg branch_flag_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] branch_target_addr_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:48: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] branch_target_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:49: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] link_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:52: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] offset_o\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:52: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] offset_o\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:63: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm; \n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:63: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm; \n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:64: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] imm_unsigned;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:64: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] imm_unsigned;\n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:65: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] offset_imm; \n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] offset_imm; \n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:66: Define or directive not defined: \'`RegBus\'\n reg[`RegBus] offset_imm_unsigned;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus] offset_imm_unsigned;\n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:70: Define or directive not defined: \'`RegBus\'\n wire[`RegBus] pc_plus_4;\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire[`RegBus] pc_plus_4;\n ^\n%Error: data/full_repos/permissive/114324064/src/id.v:74: syntax error, unexpected assign\n assign pc_plus_4 = pc_i + 4;\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:76: Define or directive not defined: \'`EXE_LB_OP\'\n assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:77: Define or directive not defined: \'`EXE_LBU_OP\'\n (ex_aluop_i == `EXE_LBU_OP) ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:78: Define or directive not defined: \'`EXE_LH_OP\'\n (ex_aluop_i == `EXE_LH_OP) ||\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:79: Define or directive not defined: \'`EXE_LHU_OP\'\n (ex_aluop_i == `EXE_LHU_OP) ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:80: Define or directive not defined: \'`EXE_LW_OP\'\n (ex_aluop_i == `EXE_LW_OP));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:84: Define or directive not defined: \'`RstEnable\'\n if (rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:85: Define or directive not defined: \'`EXE_NOP_OP\'\n aluop_o <= `EXE_NOP_OP;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:86: Define or directive not defined: \'`EXE_RES_NOP\'\n alusel_o <= `EXE_RES_NOP;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:87: Define or directive not defined: \'`NOPRegAddr\'\n wd_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/id.v:88: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,233 | module | module id(
input wire rst,
input wire inst_invalid_i,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`AluOpBus] ex_aluop_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire stallreq,
output reg branch_flag_o,
output reg[`RegBus] branch_target_addr_o,
output reg[`RegBus] link_addr_o,
output reg next_inst_invalid_o,
output reg[`RegBus] offset_o
);
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
wire[4:0] rd_addr = inst_i[11:7];
wire[4:0] rs1_addr = inst_i[19:15];
wire[4:0] rs2_addr = inst_i[24:20];
reg[`RegBus] imm;
reg[`RegBus] imm_unsigned;
reg[`RegBus] offset_imm;
reg[`RegBus] offset_imm_unsigned;
reg instvalid;
reg stallreq_for_reg1_loadrelate;
reg stallreq_for_reg2_loadrelate;
wire[`RegBus] pc_plus_4;
wire pre_inst_is_load;
assign pc_plus_4 = pc_i + 4;
assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
(ex_aluop_i == `EXE_LBU_OP) ||
(ex_aluop_i == `EXE_LH_OP) ||
(ex_aluop_i == `EXE_LHU_OP) ||
(ex_aluop_i == `EXE_LW_OP));
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
end else if (inst_invalid_i == `InstInvalid) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= rd_addr;
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= rs1_addr;
reg2_addr_o <= rs2_addr;
imm <= `ZeroWord;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
case (opcode)
`OPCODE_AUIPC: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg1_addr_o <= 5'b00000;
imm <= {inst_i[31:12], 12'h0} + pc_i;
end
`OPCODE_LUI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg1_addr_o <= 5'b00000;
imm <= {inst_i[31:12], 12'h0};
end
`OPCODE_JAL: begin
aluop_o <= `EXE_JAL_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH;
wreg_o <= `WriteEnable;
link_addr_o <= pc_plus_4;
branch_flag_o <= `Branch;
branch_target_addr_o <= pc_i + {{12{inst_i[31:31]}},
inst_i[19:12], inst_i[20:20], inst_i[30:21], 1'b0};
next_inst_invalid_o <= `InstInvalid;
end
`OPCODE_JALR: begin
aluop_o <= `EXE_JALR_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
link_addr_o <= pc_plus_4;
branch_flag_o <= `Branch;
branch_target_addr_o <= (reg1_o + {{21{inst_i[31:31]}},
inst_i[30:20]}) & {31'b1, 1'b0};
next_inst_invalid_o <= `InstInvalid;
end
`OPCODE_BRANCH: begin
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
offset_imm <= {{20{inst_i[31:31]}},
inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
offset_imm_unsigned <= {19'b0, inst_i[31:31],
inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
case (funct3)
`FUNCT3_BEQ: begin
aluop_o <= `EXE_BEQ_OP;
if (reg1_o == reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BNE: begin
aluop_o <= `EXE_BNE_OP;
if (reg1_o != reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BLT: begin
aluop_o <= `EXE_BLT_OP;
if ((reg1_o[31] == 1'b1 && reg2_o[31] == 1'b0) ||
(reg1_o[31] == reg2_o[31] && reg1_o[30:0] < reg2_o[30:0])) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BGE: begin
aluop_o <= `EXE_BGE_OP;
if ((reg1_o[31] == 1'b0 && reg2_o[31] == 1'b1) ||
(reg1_o[31] == reg2_o[31] && reg1_o[30:0] >= reg2_o[30:0])) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BLTU: begin
aluop_o <= `EXE_BLTU_OP;
imm <= imm_unsigned;
if (reg1_o < reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BGEU: begin
aluop_o <= `EXE_BGEU_OP;
imm <= imm_unsigned;
if (reg1_o >= reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
default: begin
end
endcase
end
`OPCODE_LOAD: begin
alusel_o <= `EXE_RES_LOAD_STORE;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
offset_o <= {{20{inst_i[31:31]}}, inst_i[31:20]};
case (funct3)
`FUNCT3_LB: begin
aluop_o <= `EXE_LB_OP;
end
`FUNCT3_LH: begin
aluop_o <= `EXE_LH_OP;
end
`FUNCT3_LW: begin
aluop_o <= `EXE_LW_OP;
end
`FUNCT3_LBU: begin
aluop_o <= `EXE_LBU_OP;
end
`FUNCT3_LHU: begin
aluop_o <= `EXE_LHU_OP;
end
default: begin
end
endcase
end
`OPCODE_STORE: begin
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
offset_o <= {{21{inst_i[31:31]}}, inst_i[30:25], inst_i[11:7]};
case (funct3)
`FUNCT3_SB: begin
aluop_o <= `EXE_SB_OP;
end
`FUNCT3_SH: begin
aluop_o <= `EXE_SH_OP;
end
`FUNCT3_SW: begin
aluop_o <= `EXE_SW_OP;
end
default: begin
end
endcase
end
`OPCODE_OP_IMM: begin
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31:31]}}, inst_i[31:20]};
wd_o <= rd_addr;
instvalid <= `InstValid;
case (funct3)
`FUNCT3_XORI: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_ORI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_ANDI: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_SLLI: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end
`FUNCT3_SRLI: begin
if (funct7 == `FUNCT7_SRL) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end else if (funct7 == `FUNCT7_SRA) begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end
end
`FUNCT3_SLTI: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_SLTIU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_ADDI: begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
default: begin
end
endcase
end
`OPCODE_OP: begin
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
wd_o <= rd_addr;
instvalid <= `InstValid;
case (funct3)
`FUNCT3_XOR: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_OR: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_AND: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_SLL: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
end
`FUNCT3_SRL: begin
if (funct7 == `FUNCT7_SRL) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
end else if (funct7 == `FUNCT7_SRA) begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
end
end
`FUNCT3_SLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_SLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_ADD: begin
if (funct7 == `FUNCT7_ADD) begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end else if(funct7 == `FUNCT7_SUB) begin
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
end
default: begin
end
endcase
end
default: begin
end
endcase
end
end
always @ (*) begin
stallreq_for_reg1_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
&& reg1_read_o == 1'b1) begin
stallreq_for_reg1_loadrelate <= `Stop;
end else if ((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if ((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
stallreq_for_reg2_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
&& reg2_read_o == 1'b1) begin
stallreq_for_reg2_loadrelate <= `Stop;
end else if ((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if ((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | module id(
input wire rst,
input wire inst_invalid_i,
input wire[`InstAddrBus] pc_i,
input wire[`InstBus] inst_i,
input wire[`RegBus] reg1_data_i,
input wire[`RegBus] reg2_data_i,
input wire ex_wreg_i,
input wire[`RegBus] ex_wdata_i,
input wire[`RegAddrBus] ex_wd_i,
input wire mem_wreg_i,
input wire[`RegBus] mem_wdata_i,
input wire[`RegAddrBus] mem_wd_i,
input wire[`AluOpBus] ex_aluop_i,
output reg reg1_read_o,
output reg reg2_read_o,
output reg[`RegAddrBus] reg1_addr_o,
output reg[`RegAddrBus] reg2_addr_o,
output reg[`AluOpBus] aluop_o,
output reg[`AluSelBus] alusel_o,
output reg[`RegBus] reg1_o,
output reg[`RegBus] reg2_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output wire stallreq,
output reg branch_flag_o,
output reg[`RegBus] branch_target_addr_o,
output reg[`RegBus] link_addr_o,
output reg next_inst_invalid_o,
output reg[`RegBus] offset_o
); |
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
wire[4:0] rd_addr = inst_i[11:7];
wire[4:0] rs1_addr = inst_i[19:15];
wire[4:0] rs2_addr = inst_i[24:20];
reg[`RegBus] imm;
reg[`RegBus] imm_unsigned;
reg[`RegBus] offset_imm;
reg[`RegBus] offset_imm_unsigned;
reg instvalid;
reg stallreq_for_reg1_loadrelate;
reg stallreq_for_reg2_loadrelate;
wire[`RegBus] pc_plus_4;
wire pre_inst_is_load;
assign pc_plus_4 = pc_i + 4;
assign stallreq = stallreq_for_reg1_loadrelate | stallreq_for_reg2_loadrelate;
assign pre_inst_is_load = ((ex_aluop_i == `EXE_LB_OP) ||
(ex_aluop_i == `EXE_LBU_OP) ||
(ex_aluop_i == `EXE_LH_OP) ||
(ex_aluop_i == `EXE_LHU_OP) ||
(ex_aluop_i == `EXE_LW_OP));
always @ (*) begin
if (rst == `RstEnable) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstValid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
end else if (inst_invalid_i == `InstInvalid) begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= `NOPRegAddr;
reg2_addr_o <= `NOPRegAddr;
imm <= 32'h0;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
end else begin
aluop_o <= `EXE_NOP_OP;
alusel_o <= `EXE_RES_NOP;
wd_o <= rd_addr;
wreg_o <= `WriteDisable;
instvalid <= `InstInvalid;
reg1_read_o <= 1'b0;
reg2_read_o <= 1'b0;
reg1_addr_o <= rs1_addr;
reg2_addr_o <= rs2_addr;
imm <= `ZeroWord;
link_addr_o <= `ZeroWord;
branch_target_addr_o <= `ZeroWord;
branch_flag_o <= `NotBranch;
offset_o <= `ZeroWord;
next_inst_invalid_o <= `InstValid;
case (opcode)
`OPCODE_AUIPC: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg1_addr_o <= 5'b00000;
imm <= {inst_i[31:12], 12'h0} + pc_i;
end
`OPCODE_LUI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg1_addr_o <= 5'b00000;
imm <= {inst_i[31:12], 12'h0};
end
`OPCODE_JAL: begin
aluop_o <= `EXE_JAL_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH;
wreg_o <= `WriteEnable;
link_addr_o <= pc_plus_4;
branch_flag_o <= `Branch;
branch_target_addr_o <= pc_i + {{12{inst_i[31:31]}},
inst_i[19:12], inst_i[20:20], inst_i[30:21], 1'b0};
next_inst_invalid_o <= `InstInvalid;
end
`OPCODE_JALR: begin
aluop_o <= `EXE_JALR_OP;
alusel_o <= `EXE_RES_JUMP_BRANCH;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
link_addr_o <= pc_plus_4;
branch_flag_o <= `Branch;
branch_target_addr_o <= (reg1_o + {{21{inst_i[31:31]}},
inst_i[30:20]}) & {31'b1, 1'b0};
next_inst_invalid_o <= `InstInvalid;
end
`OPCODE_BRANCH: begin
alusel_o <= `EXE_RES_JUMP_BRANCH;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
offset_imm <= {{20{inst_i[31:31]}},
inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
offset_imm_unsigned <= {19'b0, inst_i[31:31],
inst_i[7:7], inst_i[30:25], inst_i[11:8], 1'b0};
case (funct3)
`FUNCT3_BEQ: begin
aluop_o <= `EXE_BEQ_OP;
if (reg1_o == reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BNE: begin
aluop_o <= `EXE_BNE_OP;
if (reg1_o != reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BLT: begin
aluop_o <= `EXE_BLT_OP;
if ((reg1_o[31] == 1'b1 && reg2_o[31] == 1'b0) ||
(reg1_o[31] == reg2_o[31] && reg1_o[30:0] < reg2_o[30:0])) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BGE: begin
aluop_o <= `EXE_BGE_OP;
if ((reg1_o[31] == 1'b0 && reg2_o[31] == 1'b1) ||
(reg1_o[31] == reg2_o[31] && reg1_o[30:0] >= reg2_o[30:0])) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BLTU: begin
aluop_o <= `EXE_BLTU_OP;
imm <= imm_unsigned;
if (reg1_o < reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
`FUNCT3_BGEU: begin
aluop_o <= `EXE_BGEU_OP;
imm <= imm_unsigned;
if (reg1_o >= reg2_o) begin
branch_target_addr_o <= pc_i + offset_imm;
branch_flag_o <= `Branch;
next_inst_invalid_o <= `InstInvalid;
end
end
default: begin
end
endcase
end
`OPCODE_LOAD: begin
alusel_o <= `EXE_RES_LOAD_STORE;
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
offset_o <= {{20{inst_i[31:31]}}, inst_i[31:20]};
case (funct3)
`FUNCT3_LB: begin
aluop_o <= `EXE_LB_OP;
end
`FUNCT3_LH: begin
aluop_o <= `EXE_LH_OP;
end
`FUNCT3_LW: begin
aluop_o <= `EXE_LW_OP;
end
`FUNCT3_LBU: begin
aluop_o <= `EXE_LBU_OP;
end
`FUNCT3_LHU: begin
aluop_o <= `EXE_LHU_OP;
end
default: begin
end
endcase
end
`OPCODE_STORE: begin
alusel_o <= `EXE_RES_LOAD_STORE;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
offset_o <= {{21{inst_i[31:31]}}, inst_i[30:25], inst_i[11:7]};
case (funct3)
`FUNCT3_SB: begin
aluop_o <= `EXE_SB_OP;
end
`FUNCT3_SH: begin
aluop_o <= `EXE_SH_OP;
end
`FUNCT3_SW: begin
aluop_o <= `EXE_SW_OP;
end
default: begin
end
endcase
end
`OPCODE_OP_IMM: begin
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b0;
imm <= {{20{inst_i[31:31]}}, inst_i[31:20]};
wd_o <= rd_addr;
instvalid <= `InstValid;
case (funct3)
`FUNCT3_XORI: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_ORI: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_ANDI: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_SLLI: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end
`FUNCT3_SRLI: begin
if (funct7 == `FUNCT7_SRL) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end else if (funct7 == `FUNCT7_SRA) begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
imm[4:0] <= inst_i[24:20];
end
end
`FUNCT3_SLTI: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_SLTIU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_ADDI: begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
default: begin
end
endcase
end
`OPCODE_OP: begin
wreg_o <= `WriteEnable;
reg1_read_o <= 1'b1;
reg2_read_o <= 1'b1;
wd_o <= rd_addr;
instvalid <= `InstValid;
case (funct3)
`FUNCT3_XOR: begin
aluop_o <= `EXE_XOR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_OR: begin
aluop_o <= `EXE_OR_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_AND: begin
aluop_o <= `EXE_AND_OP;
alusel_o <= `EXE_RES_LOGIC;
end
`FUNCT3_SLL: begin
aluop_o <= `EXE_SLL_OP;
alusel_o <= `EXE_RES_SHIFT;
end
`FUNCT3_SRL: begin
if (funct7 == `FUNCT7_SRL) begin
aluop_o <= `EXE_SRL_OP;
alusel_o <= `EXE_RES_SHIFT;
end else if (funct7 == `FUNCT7_SRA) begin
aluop_o <= `EXE_SRA_OP;
alusel_o <= `EXE_RES_SHIFT;
end
end
`FUNCT3_SLT: begin
aluop_o <= `EXE_SLT_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_SLTU: begin
aluop_o <= `EXE_SLTU_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
`FUNCT3_ADD: begin
if (funct7 == `FUNCT7_ADD) begin
aluop_o <= `EXE_ADD_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end else if(funct7 == `FUNCT7_SUB) begin
aluop_o <= `EXE_SUB_OP;
alusel_o <= `EXE_RES_ARITHMETIC;
end
end
default: begin
end
endcase
end
default: begin
end
endcase
end
end
always @ (*) begin
stallreq_for_reg1_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg1_o <= `ZeroWord;
end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg1_addr_o
&& reg1_read_o == 1'b1) begin
stallreq_for_reg1_loadrelate <= `Stop;
end else if ((reg1_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg1_addr_o)) begin
reg1_o <= ex_wdata_i;
end else if ((reg1_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg1_addr_o)) begin
reg1_o <= mem_wdata_i;
end else if(reg1_read_o == 1'b1) begin
reg1_o <= reg1_data_i;
end else if(reg1_read_o == 1'b0) begin
reg1_o <= imm;
end else begin
reg1_o <= `ZeroWord;
end
end
always @ (*) begin
stallreq_for_reg2_loadrelate <= `NoStop;
if(rst == `RstEnable) begin
reg2_o <= `ZeroWord;
end else if (pre_inst_is_load == 1'b1 && ex_wd_i == reg2_addr_o
&& reg2_read_o == 1'b1) begin
stallreq_for_reg2_loadrelate <= `Stop;
end else if ((reg2_read_o == 1'b1) && (ex_wreg_i == 1'b1)
&& (ex_wd_i == reg2_addr_o)) begin
reg2_o <= ex_wdata_i;
end else if ((reg2_read_o == 1'b1) && (mem_wreg_i == 1'b1)
&& (mem_wd_i == reg2_addr_o)) begin
reg2_o <= mem_wdata_i;
end else if(reg2_read_o == 1'b1) begin
reg2_o <= reg2_data_i;
end else if(reg2_read_o == 1'b0) begin
reg2_o <= imm;
end else begin
reg2_o <= `ZeroWord;
end
end
endmodule | 10 |
5,454 | data/full_repos/permissive/114324064/src/mem.v | 114,324,064 | mem.v | v | 191 | 90 | [] | [] | [] | [(202, 389)] | null | null | 1: b'%Error: data/full_repos/permissive/114324064/src/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/114324064/src/mem.v:8: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus] wd_i,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus] wd_i,\n ^\n%Error: data/full_repos/permissive/114324064/src/mem.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus] wdata_i,\n ^~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:10: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] wdata_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:12: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus] aluop_i,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_addr_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:14: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] reg2_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] mem_data_i,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:20: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_addr_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[3:0] mem_sel_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] mem_data_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:23: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] mem_data_o,\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegAddrBus] wd_o,\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:27: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus] wd_o,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg[`RegBus] wdata_o\n ^~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus] wdata_o\n ^~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:33: Define or directive not defined: \'`RstEnable\'\n if(rst == `RstEnable) begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:34: Define or directive not defined: \'`NOPRegAddr\'\n wd_o <= `NOPRegAddr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:35: Define or directive not defined: \'`WriteDisable\'\n wreg_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:36: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:37: Define or directive not defined: \'`ZeroWord\'\n mem_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:38: Define or directive not defined: \'`WriteDisable\'\n mem_we_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:40: Define or directive not defined: \'`ZeroWord\'\n mem_data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:41: Define or directive not defined: \'`ChipDisable\'\n mem_ce_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:46: Define or directive not defined: \'`ZeroWord\'\n mem_addr_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:47: Define or directive not defined: \'`WriteDisable\'\n mem_we_o <= `WriteDisable;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:49: Define or directive not defined: \'`ZeroWord\'\n mem_data_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:50: Define or directive not defined: \'`ChipDisable\'\n mem_ce_o <= `ChipDisable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LB_OP\'\n `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LH_OP\'\n `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LW_OP\'\n `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LBU_OP\'\n `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:52: Define or directive not defined: \'`EXE_LHU_OP\'\n `EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:54: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:56: Define or directive not defined: \'`EXE_LB_OP\'\n `EXE_LB_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:75: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:79: Define or directive not defined: \'`EXE_LH_OP\'\n `EXE_LH_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:90: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:94: Define or directive not defined: \'`EXE_LW_OP\'\n `EXE_LW_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:98: Define or directive not defined: \'`EXE_LBU_OP\'\n `EXE_LBU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:117: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:121: Define or directive not defined: \'`EXE_LHU_OP\'\n `EXE_LHU_OP: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:132: Define or directive not defined: \'`ZeroWord\'\n wdata_o <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SB_OP\'\n `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SH_OP\'\n `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:138: Define or directive not defined: \'`EXE_SW_OP\'\n `EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:140: Define or directive not defined: \'`WriteEnable\'\n mem_we_o <= `WriteEnable;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:141: Define or directive not defined: \'`ChipEnable\'\n mem_ce_o <= `ChipEnable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/114324064/src/mem.v:143: Define or directive not defined: \'`EXE_SB_OP\'\n `EXE_SB_OP: begin\n ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 6,238 | module | module mem(
input wire rst,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] wdata_i,
input wire[`AluOpBus] aluop_i,
input wire[`RegBus] mem_addr_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] mem_data_i,
output reg[`RegBus] mem_addr_o,
output reg mem_we_o,
output reg[3:0] mem_sel_o,
output reg[`RegBus] mem_data_o,
output reg mem_ce_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o
);
always @ (*) begin
if(rst == `RstEnable) begin
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
wdata_o <= `ZeroWord;
mem_addr_o <= `ZeroWord;
mem_we_o <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
end else begin
wd_o <= wd_i;
wreg_o <= wreg_i;
wdata_o <= wdata_i;
mem_addr_o <= `ZeroWord;
mem_we_o <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
case (aluop_i)
`EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin
mem_addr_o <= mem_addr_i;
mem_ce_o <= `ChipEnable;
case (aluop_i)
`EXE_LB_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
end
2'b01: begin
mem_sel_o <= 4'b0010;
wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
end
2'b10: begin
mem_sel_o <= 4'b0100;
wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
end
2'b11: begin
mem_sel_o <= 4'b1000;
wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LH_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
end
2'b10: begin
mem_sel_o <= 4'b1100;
wdata_o <= {{16{mem_data_i[31]}}, mem_data_i[31:16]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LW_OP: begin
mem_sel_o <= 4'b1111;
wdata_o <= mem_data_i;
end
`EXE_LBU_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
wdata_o <= {24'b0, mem_data_i[7:0]};
end
2'b01: begin
mem_sel_o <= 4'b0010;
wdata_o <= {24'b0, mem_data_i[15:8]};
end
2'b10: begin
mem_sel_o <= 4'b0100;
wdata_o <= {24'b0, mem_data_i[23:16]};
end
2'b11: begin
mem_sel_o <= 4'b1000;
wdata_o <= {24'b0, mem_data_i[31:24]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LHU_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
wdata_o <= {16'b0, mem_data_i[15:0]};
end
2'b10: begin
mem_sel_o <= 4'b1100;
wdata_o <= {16'b0, mem_data_i[31:16]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endcase
end
`EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we_o <= `WriteEnable;
mem_ce_o <= `ChipEnable;
case (aluop_i)
`EXE_SB_OP: begin
mem_data_o <= {4{reg2_i[7:0]}};
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
end
2'b01: begin
mem_sel_o <= 4'b0010;
end
2'b10: begin
mem_sel_o <= 4'b0100;
end
2'b11: begin
mem_sel_o <= 4'b1000;
end
default: begin
mem_sel_o <= 4'b0000;
end
endcase
end
`EXE_SH_OP: begin
mem_data_o <= {2{reg2_i[15:0]}};
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
end
2'b10: begin
mem_sel_o <= 4'b1100;
end
default: begin
mem_sel_o <= 4'b0000;
end
endcase
end
`EXE_SW_OP: begin
mem_sel_o <= 4'b1111;
mem_data_o <= reg2_i;
end
endcase
end
default: begin
end
endcase
end
end
endmodule | module mem(
input wire rst,
input wire[`RegAddrBus] wd_i,
input wire wreg_i,
input wire[`RegBus] wdata_i,
input wire[`AluOpBus] aluop_i,
input wire[`RegBus] mem_addr_i,
input wire[`RegBus] reg2_i,
input wire[`RegBus] mem_data_i,
output reg[`RegBus] mem_addr_o,
output reg mem_we_o,
output reg[3:0] mem_sel_o,
output reg[`RegBus] mem_data_o,
output reg mem_ce_o,
output reg[`RegAddrBus] wd_o,
output reg wreg_o,
output reg[`RegBus] wdata_o
); |
always @ (*) begin
if(rst == `RstEnable) begin
wd_o <= `NOPRegAddr;
wreg_o <= `WriteDisable;
wdata_o <= `ZeroWord;
mem_addr_o <= `ZeroWord;
mem_we_o <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
end else begin
wd_o <= wd_i;
wreg_o <= wreg_i;
wdata_o <= wdata_i;
mem_addr_o <= `ZeroWord;
mem_we_o <= `WriteDisable;
mem_sel_o <= 4'b0000;
mem_data_o <= `ZeroWord;
mem_ce_o <= `ChipDisable;
case (aluop_i)
`EXE_LB_OP, `EXE_LH_OP, `EXE_LW_OP, `EXE_LBU_OP, `EXE_LHU_OP: begin
mem_addr_o <= mem_addr_i;
mem_ce_o <= `ChipEnable;
case (aluop_i)
`EXE_LB_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
wdata_o <= {{24{mem_data_i[7]}}, mem_data_i[7:0]};
end
2'b01: begin
mem_sel_o <= 4'b0010;
wdata_o <= {{24{mem_data_i[15]}}, mem_data_i[15:8]};
end
2'b10: begin
mem_sel_o <= 4'b0100;
wdata_o <= {{24{mem_data_i[23]}}, mem_data_i[23:16]};
end
2'b11: begin
mem_sel_o <= 4'b1000;
wdata_o <= {{24{mem_data_i[31]}}, mem_data_i[31:24]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LH_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
wdata_o <= {{16{mem_data_i[15]}}, mem_data_i[15:0]};
end
2'b10: begin
mem_sel_o <= 4'b1100;
wdata_o <= {{16{mem_data_i[31]}}, mem_data_i[31:16]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LW_OP: begin
mem_sel_o <= 4'b1111;
wdata_o <= mem_data_i;
end
`EXE_LBU_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
wdata_o <= {24'b0, mem_data_i[7:0]};
end
2'b01: begin
mem_sel_o <= 4'b0010;
wdata_o <= {24'b0, mem_data_i[15:8]};
end
2'b10: begin
mem_sel_o <= 4'b0100;
wdata_o <= {24'b0, mem_data_i[23:16]};
end
2'b11: begin
mem_sel_o <= 4'b1000;
wdata_o <= {24'b0, mem_data_i[31:24]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
`EXE_LHU_OP: begin
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
wdata_o <= {16'b0, mem_data_i[15:0]};
end
2'b10: begin
mem_sel_o <= 4'b1100;
wdata_o <= {16'b0, mem_data_i[31:16]};
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
endcase
end
`EXE_SB_OP, `EXE_SH_OP, `EXE_SW_OP: begin
mem_addr_o <= mem_addr_i;
mem_we_o <= `WriteEnable;
mem_ce_o <= `ChipEnable;
case (aluop_i)
`EXE_SB_OP: begin
mem_data_o <= {4{reg2_i[7:0]}};
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0001;
end
2'b01: begin
mem_sel_o <= 4'b0010;
end
2'b10: begin
mem_sel_o <= 4'b0100;
end
2'b11: begin
mem_sel_o <= 4'b1000;
end
default: begin
mem_sel_o <= 4'b0000;
end
endcase
end
`EXE_SH_OP: begin
mem_data_o <= {2{reg2_i[15:0]}};
case (mem_addr_i[1:0])
2'b00: begin
mem_sel_o <= 4'b0011;
end
2'b10: begin
mem_sel_o <= 4'b1100;
end
default: begin
mem_sel_o <= 4'b0000;
end
endcase
end
`EXE_SW_OP: begin
mem_sel_o <= 4'b1111;
mem_data_o <= reg2_i;
end
endcase
end
default: begin
end
endcase
end
end
endmodule | 10 |
5,456 | data/full_repos/permissive/114324064/src/uart_comm.v | 114,324,064 | uart_comm.v | v | 184 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/114324064/src/uart_comm.v:27: Cannot find file containing module: 'fifo'\n fifo#(.width(width)) recv_buffer(clk,\n ^~~~\n ... Looked in:\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/fifo\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/fifo.v\n data/full_repos/permissive/114324064/src,data/full_repos/permissive/114324064/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: data/full_repos/permissive/114324064/src/uart_comm.v:39: Cannot find file containing module: 'fifo'\n fifo#(.width(width)) send_buffere(clk,\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 6,245 | module | module uart
#(
parameter width = 8,
parameter baud_rate = 9600,
parameter clk_rate = 100000000
)
(
input wire clk,
input wire rst,
input wire send_flag,
input wire[width-1:0] send_data,
input wire recv_flag,
output reg[width-1:0] recv_data,
output reg send_able,
output reg recv_able,
output reg Tx,
input wire Rx
);
reg recv_write_flag;
reg[width-1:0] recv_write_data;
wire recv_empty, recv_full;
fifo#(.width(width)) recv_buffer(clk,
rst,
recv_flag,
recv_data,
recv_write_flag,
recv_write_data,
recv_empty,
recv_full);
reg send_read_flag;
wire[width-1:0] send_read_data;
reg[width-1:0] send_read_data_buf;
wire send_empty, send_full;
fifo#(.width(width)) send_buffere(clk,
rst,
send_read_flag,
send_read_data,
send_flag,
send_data,
send_empty,
send_full);
assign recv_able = !recv_empty;
assign send_able = !send_full;
localparam sample_interval = clk_rate / baud_rate;
localparam status_idle = 0;
localparam status_begin = 1;
localparam status_data = 2;
localparam status_valid = 4;
localparam status_end = 8;
reg[3:0] recv_status;
reg[2:0] recv_bit;
reg recv_parity;
integer recv_cnt;
reg recv_clk;
wire sample = recv_cnt == sample_interval / 2;
always @(posedge clk or posedge rst) begin
if (rst) begin
recv_write_flag <= 0;
recv_write_data <= 0;
recv_status <= status_idle;
recv_bit <= 0;
recv_parity <= 0;
recv_cnt <= 0;
recv_clk <= 0;
end else begin
recv_write_flag <= 0;
if (recv_clk) begin
if (recv_cnt == sample_interval - 1)
recv_cnt <= 0;
else
recv_cnt <= recv_cnt + 1;
end
if (recv_status == status_idle) begin
if (!Rx) begin
recv_status <= status_begin;
recv_cnt <= 0;
recv_clk <= 1;
end
end else if (sample) begin
case (recv_status)
status_begin: begin
if (!Rx) begin
recv_status <= status_data;
recv_bit <= 0;
recv_parity <= 0;
end else begin
recv_status <= status_idle;
recv_clk <= 0;
end
end
status_data: begin
recv_parity <= recv_parity ^ Rx;
recv_write_data[recv_bit] <= Rx;
recv_bit <= recv_bit + 1;
if (recv_bit == 7)
recv_status <= status_valid;
end
status_valid: begin
if (recv_parity == Rx && !recv_full)
recv_write_flag <= 1;
recv_status <= status_end;
end
status_end: begin
recv_status <= status_idle;
recv_clk <= 0;
end
endcase
end
end
end
integer cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
if (cnt == sample_interval - 1)
cnt <= 0;
end
end
reg[3:0] send_status;
reg[2:0] send_bit;
reg send_parity;
reg tosend;
always @(posedge clk or posedge rst) begin
if (rst) begin
send_read_flag <= 0;
send_read_data_buf <= 0;
send_status <= status_idle;
send_bit <= 0;
send_parity <= 0;
tosend <= 0;
Tx <= 1;
end else begin
send_read_flag <= 0;
if (cnt == 0) begin
case (send_status)
status_idle: begin
if (!send_empty) begin
send_read_data_buf <= send_read_data;
send_read_flag <= 1;
Tx <= 0;
send_status <= status_data;
send_bit <= 0;
send_parity <= 0;
end
end
status_data: begin
Tx <= send_read_data_buf[send_bit];
send_parity <= send_parity ^ send_read_data_buf[send_bit];
send_bit <= send_bit + 1;
if (send_bit == 7)
send_status <= status_valid;
end
status_valid: begin
Tx <= send_parity;
send_status <= status_end;
end
status_end: begin
Tx <= 1;
send_status <= status_idle;
tosend = 0;
end
endcase
end
end
end
endmodule | module uart
#(
parameter width = 8,
parameter baud_rate = 9600,
parameter clk_rate = 100000000
)
(
input wire clk,
input wire rst,
input wire send_flag,
input wire[width-1:0] send_data,
input wire recv_flag,
output reg[width-1:0] recv_data,
output reg send_able,
output reg recv_able,
output reg Tx,
input wire Rx
); |
reg recv_write_flag;
reg[width-1:0] recv_write_data;
wire recv_empty, recv_full;
fifo#(.width(width)) recv_buffer(clk,
rst,
recv_flag,
recv_data,
recv_write_flag,
recv_write_data,
recv_empty,
recv_full);
reg send_read_flag;
wire[width-1:0] send_read_data;
reg[width-1:0] send_read_data_buf;
wire send_empty, send_full;
fifo#(.width(width)) send_buffere(clk,
rst,
send_read_flag,
send_read_data,
send_flag,
send_data,
send_empty,
send_full);
assign recv_able = !recv_empty;
assign send_able = !send_full;
localparam sample_interval = clk_rate / baud_rate;
localparam status_idle = 0;
localparam status_begin = 1;
localparam status_data = 2;
localparam status_valid = 4;
localparam status_end = 8;
reg[3:0] recv_status;
reg[2:0] recv_bit;
reg recv_parity;
integer recv_cnt;
reg recv_clk;
wire sample = recv_cnt == sample_interval / 2;
always @(posedge clk or posedge rst) begin
if (rst) begin
recv_write_flag <= 0;
recv_write_data <= 0;
recv_status <= status_idle;
recv_bit <= 0;
recv_parity <= 0;
recv_cnt <= 0;
recv_clk <= 0;
end else begin
recv_write_flag <= 0;
if (recv_clk) begin
if (recv_cnt == sample_interval - 1)
recv_cnt <= 0;
else
recv_cnt <= recv_cnt + 1;
end
if (recv_status == status_idle) begin
if (!Rx) begin
recv_status <= status_begin;
recv_cnt <= 0;
recv_clk <= 1;
end
end else if (sample) begin
case (recv_status)
status_begin: begin
if (!Rx) begin
recv_status <= status_data;
recv_bit <= 0;
recv_parity <= 0;
end else begin
recv_status <= status_idle;
recv_clk <= 0;
end
end
status_data: begin
recv_parity <= recv_parity ^ Rx;
recv_write_data[recv_bit] <= Rx;
recv_bit <= recv_bit + 1;
if (recv_bit == 7)
recv_status <= status_valid;
end
status_valid: begin
if (recv_parity == Rx && !recv_full)
recv_write_flag <= 1;
recv_status <= status_end;
end
status_end: begin
recv_status <= status_idle;
recv_clk <= 0;
end
endcase
end
end
end
integer cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
if (cnt == sample_interval - 1)
cnt <= 0;
end
end
reg[3:0] send_status;
reg[2:0] send_bit;
reg send_parity;
reg tosend;
always @(posedge clk or posedge rst) begin
if (rst) begin
send_read_flag <= 0;
send_read_data_buf <= 0;
send_status <= status_idle;
send_bit <= 0;
send_parity <= 0;
tosend <= 0;
Tx <= 1;
end else begin
send_read_flag <= 0;
if (cnt == 0) begin
case (send_status)
status_idle: begin
if (!send_empty) begin
send_read_data_buf <= send_read_data;
send_read_flag <= 1;
Tx <= 0;
send_status <= status_data;
send_bit <= 0;
send_parity <= 0;
end
end
status_data: begin
Tx <= send_read_data_buf[send_bit];
send_parity <= send_parity ^ send_read_data_buf[send_bit];
send_bit <= send_bit + 1;
if (send_bit == 7)
send_status <= status_valid;
end
status_valid: begin
Tx <= send_parity;
send_status <= status_end;
end
status_end: begin
Tx <= 1;
send_status <= status_idle;
tosend = 0;
end
endcase
end
end
end
endmodule | 10 |
5,458 | data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v | 114,379,717 | bjt_test.v | v | 87 | 129 | [] | [] | [] | [(4, 86)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:37: Signal definition not found, creating implicitly: \'tx_spi_sclk_wire\'\n : ... Suggested alternative: \'tx_spi_sclk\'\nassign tx_spi_sclk = tx_spi_sclk_wire; \n ^~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:85: Signal definition not found, creating implicitly: \'uart_tx_wire\'\n : ... Suggested alternative: \'uart_counter_wire\'\nalways@(*) uart_tx = uart_tx_wire;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:19: Cannot find file containing module: \'clockpll\'\nclockpll pll(.globalclock(globalclock), \n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll\n data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll.v\n data/full_repos/permissive/114379717/bjt_encapsulated,data/full_repos/permissive/114379717/clockpll.sv\n clockpll\n clockpll.v\n clockpll.sv\n obj_dir/clockpll\n obj_dir/clockpll.v\n obj_dir/clockpll.sv\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:27: Cannot find file containing module: \'DAC_control\'\nDAC_control DAC_control_inst(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:43: Cannot find file containing module: \'ADC_control\'\nADC_control ADC_control_inst(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:64: Cannot find file containing module: \'FIFO_control\'\nFIFO_control FIFO_control_inst(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/114379717/bjt_encapsulated/bjt_test.v:76: Cannot find file containing module: \'uart_control\'\nuart_control uart_control_inst(\n^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n' | 6,248 | module | module bjt(input globalclock,
input rst,
output tx_spi_sclk,
output tx_spi_sync,
output tx_spi_din,
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input wire ADC_SDO,
output reg uart_tx
);
wire [31:0] verti_counter;
wire [3:0] serial_counter;
clockpll pll(.globalclock(globalclock),
.rst(rst),
.dac_clk(tx_spi_sclk_wire),
.adc_clk(adc_clk),
.adc_clk_delay(adc_clk_delay),
.uart_clk(UART_CLK)
);
DAC_control DAC_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.tx_spi_sync(tx_spi_sync),
.tx_spi_din(tx_spi_din),
.adc_start(adc_start),
.verti_counter(verti_counter),
.serial_counter(serial_counter),
.loop(loop)
);
assign tx_spi_sclk = tx_spi_sclk_wire;
wire [23:0] fifo_data;
wire [11:0] measure_count;
ADC_control ADC_control_inst(
.adc_clk(adc_clk),
.adc_clk_delay(adc_clk_delay),
.adc_start(adc_start),
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO),
.rst(rst),
.loop(loop),
.serial_counter(serial_counter),
.verti_counter(verti_counter),
.fifo_data(fifo_data),
.measure_count(measure_count),
.measure_done(measure_done));
wire [1:0] uart_counter_wire;
wire [23:0] q_sig_wire;
wire idle;
FIFO_control FIFO_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.idle(idle),
.uart_counter(uart_counter_wire),
.serial_counter(serial_counter),
.measure_count(measure_count),
.fifo_data(fifo_data),
.measure_done(measure_done),
.q_sig_wire(q_sig_wire));
uart_control uart_control_inst(
.globalclock(globalclock),
.verti_counter(verti_counter),
.UART_CLK(UART_CLK),
.rst(rst),
.q_sig(q_sig_wire),
.uart_tx_wire(uart_tx_wire),
.idle(idle),
.uart_counter(uart_counter_wire));
always@(*) uart_tx = uart_tx_wire;
endmodule | module bjt(input globalclock,
input rst,
output tx_spi_sclk,
output tx_spi_sync,
output tx_spi_din,
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input wire ADC_SDO,
output reg uart_tx
); |
wire [31:0] verti_counter;
wire [3:0] serial_counter;
clockpll pll(.globalclock(globalclock),
.rst(rst),
.dac_clk(tx_spi_sclk_wire),
.adc_clk(adc_clk),
.adc_clk_delay(adc_clk_delay),
.uart_clk(UART_CLK)
);
DAC_control DAC_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.tx_spi_sync(tx_spi_sync),
.tx_spi_din(tx_spi_din),
.adc_start(adc_start),
.verti_counter(verti_counter),
.serial_counter(serial_counter),
.loop(loop)
);
assign tx_spi_sclk = tx_spi_sclk_wire;
wire [23:0] fifo_data;
wire [11:0] measure_count;
ADC_control ADC_control_inst(
.adc_clk(adc_clk),
.adc_clk_delay(adc_clk_delay),
.adc_start(adc_start),
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO),
.rst(rst),
.loop(loop),
.serial_counter(serial_counter),
.verti_counter(verti_counter),
.fifo_data(fifo_data),
.measure_count(measure_count),
.measure_done(measure_done));
wire [1:0] uart_counter_wire;
wire [23:0] q_sig_wire;
wire idle;
FIFO_control FIFO_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.idle(idle),
.uart_counter(uart_counter_wire),
.serial_counter(serial_counter),
.measure_count(measure_count),
.fifo_data(fifo_data),
.measure_done(measure_done),
.q_sig_wire(q_sig_wire));
uart_control uart_control_inst(
.globalclock(globalclock),
.verti_counter(verti_counter),
.UART_CLK(UART_CLK),
.rst(rst),
.q_sig(q_sig_wire),
.uart_tx_wire(uart_tx_wire),
.idle(idle),
.uart_counter(uart_counter_wire));
always@(*) uart_tx = uart_tx_wire;
endmodule | 1 |
5,460 | data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v | 114,379,717 | DAC_control.v | v | 198 | 152 | [] | [] | [] | [(1, 198)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:57: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_1[9\'d25-counter];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:60: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_1[9\'d25-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:68: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_2[9\'d50-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:71: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_2[9\'d50-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:79: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_3[9\'d75-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:82: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_3[9\'d75-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:90: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_4[9\'d100-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:93: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= inidata_4[9\'d100-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:102: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= sawtooth[9\'d125-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:105: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= sawtooth[9\'d125-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:113: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= stepwave[9\'d150-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:116: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= stepwave[9\'d150-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:124: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= pin3_C_yminu[9\'d175-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:127: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= pin3_C_yminu[9\'d175-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:135: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= pin4_D_yplus[9\'d200-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:138: Bit extraction of var[23:0] requires 5 bit index, not 9 bits.\n : ... In instance DAC_control\n tx_spi_din <= pin4_D_yplus[9\'d200-counter];\n ^\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:146: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'16\'h7cf\' generates 16 bits.\n : ... In instance DAC_control\n if(verti_counter == 16\'d1999 & serial_counter == 4) loop <= 1\'d1; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:147: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'16\'h0\' generates 16 bits.\n : ... In instance DAC_control\n if(verti_counter == 16\'d0) loop <= 1\'d0; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:155: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance DAC_control\n verti_counter <= 12\'d0; \n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:170: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'h0\' generates 12 bits.\n : ... In instance DAC_control\n verti_counter <= 12\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:169: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'12\'h7cf\' generates 12 bits.\n : ... In instance DAC_control\n if(verti_counter == 12\'d1999 & serial_counter == 4\'d4)begin \n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:173: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n : ... In instance DAC_control\n serial_counter <= 1\'d1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/114379717/bjt_encapsulated/DAC_control.v:180: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'12\'h1\' generates 12 bits.\n : ... In instance DAC_control\n verti_counter <= verti_counter + 12\'d1;\n ^\n%Error: Exiting due to 23 warning(s)\n' | 6,250 | module | module DAC_control(
input wire tx_spi_sclk_wire,
input wire rst,
output reg tx_spi_sync,
output reg tx_spi_din,
output reg adc_start,
output reg [31:0] verti_counter,
output reg [3:0] serial_counter,
output reg loop
);
parameter inidata_1 = 24'b001010010000000000000001, inidata_2 = 24'b001110010000000000000001,
inidata_3 = 24'b001000000000000000001111, inidata_4 = 24'b001100000000000000000000;
reg [8:0] counter;
reg init = 1'b1;
reg [7:0] hori_counter;
reg [23:0] sawtooth = 24'b00000000_0000000000000000;
reg [23:0] stepwave = 24'b00000001_0000000000000000;
reg [23:0] pin3_C_yminu = 24'b00000010_0000110110111001;
reg [23:0] pin4_D_yplus = 24'b00010011_1100111000111100;
parameter sawstep = 24'b0000_0000_0000_0000_0001_0000_0110;
parameter stepstep = 24'b0000_0000_0000_0010_0100_1001_0010;
always @(negedge tx_spi_sclk_wire) begin
if(~rst) begin
counter <= 0;
end
else begin
counter <= counter + 1'b1;
if(counter == 9'd201) counter <= 9'd102;
end
end
always @(posedge tx_spi_sclk_wire) begin
case(counter)
0:tx_spi_sync <= 1'b0;
1: begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 1'b0;
loop <= 1'b1;
end
2:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_1[9'd25-counter];
end
3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25:
tx_spi_din <= inidata_1[9'd25-counter];
26:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
27:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_2[9'd50-counter];
end
28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50:
tx_spi_din <= inidata_2[9'd50-counter];
51:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
52:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_3[9'd75-counter];
end
53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75:
tx_spi_din <= inidata_3[9'd75-counter];
76:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
77:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_4[9'd100-counter];
end
78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100:
tx_spi_din <= inidata_4[9'd100-counter];
101:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
init <= 1'b0;
end
102:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= sawtooth[9'd125-counter];
end
103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125:
tx_spi_din <= sawtooth[9'd125-counter];
126:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
127:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= stepwave[9'd150-counter];
end
128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150:
tx_spi_din <= stepwave[9'd150-counter];
151:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
152:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= pin3_C_yminu[9'd175-counter];
end
153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175:
tx_spi_din <= pin3_C_yminu[9'd175-counter];
176:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
177:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= pin4_D_yplus[9'd200-counter];
end
178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200:
tx_spi_din <= pin4_D_yplus[9'd200-counter];
201:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
default:;
endcase
if(verti_counter == 16'd1999 & serial_counter == 4) loop <= 1'd1;
if(verti_counter == 16'd0) loop <= 1'd0;
end
always @(posedge tx_spi_sync) begin
if (counter == 1) begin
hori_counter <= 8'b0;
verti_counter <= 12'd0;
serial_counter <= 4'd0;
adc_start <= 0;
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= 24'b00000001_0000000000000000;
pin3_C_yminu <= 24'b00000010_0000000000000000;
pin4_D_yplus <= 24'b00010011_0000000000000000;
end
else if(init == 0)begin
if(serial_counter == 4)
adc_start <= 1;
if(loop == 1'd1) begin
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= 24'b00000001_0000000000000000;
if(verti_counter == 12'd1999 & serial_counter == 4'd4)begin
verti_counter <= 12'd0;
hori_counter <= 8'b0;
end
serial_counter <= 1'd1;
end
else begin
serial_counter <= serial_counter + 1'b1;
if(serial_counter == 4'd4) begin
serial_counter <= 4'd1;
verti_counter <= verti_counter + 12'd1;
hori_counter <= hori_counter + 1'b1;
if(hori_counter == 8'd249) begin
hori_counter <= 8'b0;
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= stepwave + stepstep;
end
else begin
if(hori_counter < 8'd125) sawtooth <= sawtooth + sawstep;
if(hori_counter < 8'd249 && hori_counter >= 8'd125) sawtooth <= sawtooth - sawstep;
end
end
end
end
end
endmodule | module DAC_control(
input wire tx_spi_sclk_wire,
input wire rst,
output reg tx_spi_sync,
output reg tx_spi_din,
output reg adc_start,
output reg [31:0] verti_counter,
output reg [3:0] serial_counter,
output reg loop
); |
parameter inidata_1 = 24'b001010010000000000000001, inidata_2 = 24'b001110010000000000000001,
inidata_3 = 24'b001000000000000000001111, inidata_4 = 24'b001100000000000000000000;
reg [8:0] counter;
reg init = 1'b1;
reg [7:0] hori_counter;
reg [23:0] sawtooth = 24'b00000000_0000000000000000;
reg [23:0] stepwave = 24'b00000001_0000000000000000;
reg [23:0] pin3_C_yminu = 24'b00000010_0000110110111001;
reg [23:0] pin4_D_yplus = 24'b00010011_1100111000111100;
parameter sawstep = 24'b0000_0000_0000_0000_0001_0000_0110;
parameter stepstep = 24'b0000_0000_0000_0010_0100_1001_0010;
always @(negedge tx_spi_sclk_wire) begin
if(~rst) begin
counter <= 0;
end
else begin
counter <= counter + 1'b1;
if(counter == 9'd201) counter <= 9'd102;
end
end
always @(posedge tx_spi_sclk_wire) begin
case(counter)
0:tx_spi_sync <= 1'b0;
1: begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 1'b0;
loop <= 1'b1;
end
2:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_1[9'd25-counter];
end
3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25:
tx_spi_din <= inidata_1[9'd25-counter];
26:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
27:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_2[9'd50-counter];
end
28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50:
tx_spi_din <= inidata_2[9'd50-counter];
51:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
52:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_3[9'd75-counter];
end
53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75:
tx_spi_din <= inidata_3[9'd75-counter];
76:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
77:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= inidata_4[9'd100-counter];
end
78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100:
tx_spi_din <= inidata_4[9'd100-counter];
101:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
init <= 1'b0;
end
102:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= sawtooth[9'd125-counter];
end
103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125:
tx_spi_din <= sawtooth[9'd125-counter];
126:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
127:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= stepwave[9'd150-counter];
end
128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150:
tx_spi_din <= stepwave[9'd150-counter];
151:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
152:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= pin3_C_yminu[9'd175-counter];
end
153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175:
tx_spi_din <= pin3_C_yminu[9'd175-counter];
176:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
177:begin
tx_spi_sync <= 1'b0;
tx_spi_din <= pin4_D_yplus[9'd200-counter];
end
178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200:
tx_spi_din <= pin4_D_yplus[9'd200-counter];
201:begin
tx_spi_sync <= 1'b1;
tx_spi_din <= 0;
end
default:;
endcase
if(verti_counter == 16'd1999 & serial_counter == 4) loop <= 1'd1;
if(verti_counter == 16'd0) loop <= 1'd0;
end
always @(posedge tx_spi_sync) begin
if (counter == 1) begin
hori_counter <= 8'b0;
verti_counter <= 12'd0;
serial_counter <= 4'd0;
adc_start <= 0;
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= 24'b00000001_0000000000000000;
pin3_C_yminu <= 24'b00000010_0000000000000000;
pin4_D_yplus <= 24'b00010011_0000000000000000;
end
else if(init == 0)begin
if(serial_counter == 4)
adc_start <= 1;
if(loop == 1'd1) begin
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= 24'b00000001_0000000000000000;
if(verti_counter == 12'd1999 & serial_counter == 4'd4)begin
verti_counter <= 12'd0;
hori_counter <= 8'b0;
end
serial_counter <= 1'd1;
end
else begin
serial_counter <= serial_counter + 1'b1;
if(serial_counter == 4'd4) begin
serial_counter <= 4'd1;
verti_counter <= verti_counter + 12'd1;
hori_counter <= hori_counter + 1'b1;
if(hori_counter == 8'd249) begin
hori_counter <= 8'b0;
sawtooth <= 24'b00000000_0000000000000000;
stepwave <= stepwave + stepstep;
end
else begin
if(hori_counter < 8'd125) sawtooth <= sawtooth + sawstep;
if(hori_counter < 8'd249 && hori_counter >= 8'd125) sawtooth <= sawtooth - sawstep;
end
end
end
end
end
endmodule | 1 |
5,465 | data/full_repos/permissive/114380772/Snake/Apple_generate_module.v | 114,380,772 | Apple_generate_module.v | v | 54 | 132 | [] | [] | [] | [(1, 53)] | null | null | 1: b'%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:40: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_1[7:4] <= (Random_num_1[7:4] > 4\'d15)?(Random_num_1[7:4] - 4\'d15):((Random_num_1[7:4] == 4\'d0)?4\'d1:Random_num_1[7:4]);\n ^\n ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:41: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_1[3:0] <= (Random_num_1[3:0] > 4\'d15)?(Random_num_1[3:0] - 4\'d15):((Random_num_1[3:0] == 4\'d0)?4\'d1:Random_num_1[3:0]);\n ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:42: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_2[7:4] <= (Random_num_2[7:4] > 4\'d15)?(Random_num_2[7:4] - 4\'d15):((Random_num_2[7:4] == 4\'d0)?4\'d1:Random_num_2[7:4]);\n ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:43: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_2[3:0] <= (Random_num_2[3:0] > 4\'d15)?(Random_num_2[3:0] - 4\'d15):((Random_num_2[3:0] == 4\'d0)?4\'d1:Random_num_2[3:0]);\n ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:44: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_3[7:4] <= (Random_num_3[7:4] > 4\'d15)?(Random_num_3[7:4] - 4\'d15):((Random_num_3[7:4] == 4\'d0)?4\'d1:Random_num_3[7:4]);\n ^\n%Warning-CMPCONST: data/full_repos/permissive/114380772/Snake/Apple_generate_module.v:45: Comparison is constant due to limited range\n : ... In instance Apple_generate_module\n Apple_3[3:0] <= (Random_num_3[3:0] > 4\'d15)?(Random_num_3[3:0] - 4\'d15):((Random_num_3[3:0] == 4\'d0)?4\'d1:Random_num_3[3:0]);\n ^\n%Error: Exiting due to 6 warning(s)\n' | 6,261 | module | module Apple_generate_module
(
input Clk_24mhz,
input Rst_n,
input [7:0] Head,
output reg [7:0] Apple_1,
output reg [7:0] Apple_2,
output reg [7:0] Apple_3,
output reg Body_add_sig
);
reg [31:0] Count1;
reg [7:0] Random_num_1;
reg [7:0] Random_num_2;
reg [7:0] Random_num_3;
always@(posedge Clk_24mhz)
begin
Random_num_1 <= Random_num_1 + 8'd126;
Random_num_2 <= Random_num_2 + 8'd65;
Random_num_3 <= Random_num_3 + 8'd89;
end
always@(posedge Clk_24mhz or negedge Rst_n)
begin
if(!Rst_n)
begin
Count1 <= 32'd0;
Apple_1 <= {4'd5,4'd8};
Apple_2 <= {4'd6,4'd10};
Apple_3 <= {4'd10,4'd8};
Body_add_sig <= 1'd0;
end
else
begin
Count1 <= 32'd0;
if(Apple_1 == Head | Apple_2 == Head | Apple_3 == Head)
begin
Body_add_sig <= 1'd1;
Apple_1[7:4] <= (Random_num_1[7:4] > 4'd15)?(Random_num_1[7:4] - 4'd15):((Random_num_1[7:4] == 4'd0)?4'd1:Random_num_1[7:4]);
Apple_1[3:0] <= (Random_num_1[3:0] > 4'd15)?(Random_num_1[3:0] - 4'd15):((Random_num_1[3:0] == 4'd0)?4'd1:Random_num_1[3:0]);
Apple_2[7:4] <= (Random_num_2[7:4] > 4'd15)?(Random_num_2[7:4] - 4'd15):((Random_num_2[7:4] == 4'd0)?4'd1:Random_num_2[7:4]);
Apple_2[3:0] <= (Random_num_2[3:0] > 4'd15)?(Random_num_2[3:0] - 4'd15):((Random_num_2[3:0] == 4'd0)?4'd1:Random_num_2[3:0]);
Apple_3[7:4] <= (Random_num_3[7:4] > 4'd15)?(Random_num_3[7:4] - 4'd15):((Random_num_3[7:4] == 4'd0)?4'd1:Random_num_3[7:4]);
Apple_3[3:0] <= (Random_num_3[3:0] > 4'd15)?(Random_num_3[3:0] - 4'd15):((Random_num_3[3:0] == 4'd0)?4'd1:Random_num_3[3:0]);
end
else
Body_add_sig <= 1'd0;
end
end
endmodule | module Apple_generate_module
(
input Clk_24mhz,
input Rst_n,
input [7:0] Head,
output reg [7:0] Apple_1,
output reg [7:0] Apple_2,
output reg [7:0] Apple_3,
output reg Body_add_sig
); |
reg [31:0] Count1;
reg [7:0] Random_num_1;
reg [7:0] Random_num_2;
reg [7:0] Random_num_3;
always@(posedge Clk_24mhz)
begin
Random_num_1 <= Random_num_1 + 8'd126;
Random_num_2 <= Random_num_2 + 8'd65;
Random_num_3 <= Random_num_3 + 8'd89;
end
always@(posedge Clk_24mhz or negedge Rst_n)
begin
if(!Rst_n)
begin
Count1 <= 32'd0;
Apple_1 <= {4'd5,4'd8};
Apple_2 <= {4'd6,4'd10};
Apple_3 <= {4'd10,4'd8};
Body_add_sig <= 1'd0;
end
else
begin
Count1 <= 32'd0;
if(Apple_1 == Head | Apple_2 == Head | Apple_3 == Head)
begin
Body_add_sig <= 1'd1;
Apple_1[7:4] <= (Random_num_1[7:4] > 4'd15)?(Random_num_1[7:4] - 4'd15):((Random_num_1[7:4] == 4'd0)?4'd1:Random_num_1[7:4]);
Apple_1[3:0] <= (Random_num_1[3:0] > 4'd15)?(Random_num_1[3:0] - 4'd15):((Random_num_1[3:0] == 4'd0)?4'd1:Random_num_1[3:0]);
Apple_2[7:4] <= (Random_num_2[7:4] > 4'd15)?(Random_num_2[7:4] - 4'd15):((Random_num_2[7:4] == 4'd0)?4'd1:Random_num_2[7:4]);
Apple_2[3:0] <= (Random_num_2[3:0] > 4'd15)?(Random_num_2[3:0] - 4'd15):((Random_num_2[3:0] == 4'd0)?4'd1:Random_num_2[3:0]);
Apple_3[7:4] <= (Random_num_3[7:4] > 4'd15)?(Random_num_3[7:4] - 4'd15):((Random_num_3[7:4] == 4'd0)?4'd1:Random_num_3[7:4]);
Apple_3[3:0] <= (Random_num_3[3:0] > 4'd15)?(Random_num_3[3:0] - 4'd15):((Random_num_3[3:0] == 4'd0)?4'd1:Random_num_3[3:0]);
end
else
Body_add_sig <= 1'd0;
end
end
endmodule | 1 |
5,466 | data/full_repos/permissive/114380772/Snake/Array_decoder.v | 114,380,772 | Array_decoder.v | v | 301 | 58 | [] | [] | [] | [(1, 299)] | null | data/verilator_xmls/aeaa2c0f-ea90-4828-be5f-5b6159a6adea.xml | null | 6,262 | module | module Array_decoder
(
input Clk,
input rst,
input [7:0] BodyA,
input [7:0] BodyB,
input [7:0] BodyC,
input [7:0] BodyD,
input [7:0] BodyE,
input [7:0] BodyF,
input [7:0] BodyG,
input [7:0] BodyH,
input [7:0] BodyI,
input [7:0] BodyJ,
input [7:0] BodyK,
input [7:0] BodyL,
input [7:0] BodyM,
input [7:0] BodyN,
input [7:0] BodyO,
input [7:0] BodyP,
input [7:0] Snake_length,
input [7:0] Apple_1,
input [7:0] Apple_2,
input [7:0] Apple_3,
input [2:0] Game_status,
output reg [15:0] row,
output reg [15:0] col
);
parameter END = 3'b100;
parameter START = 3'b001;
reg [7:0] counter;
reg [7:0] select;
always@(posedge Clk)begin
if(~rst)begin
counter <= 0;
end
else if(Game_status == END | Game_status == START) begin
counter <= counter + 1;
case(counter)
8'd1:begin
col <= ~16'b0010_0000_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd2:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd3:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd4:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd5:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd6:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0100_0000_0000;
end
8'd7:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0100_0000_0000;
end
8'd8:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0100_0000_0000;
end
8'd9:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd10:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd11:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd12:begin
col <= ~16'b0000_0010_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd13:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd14:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0010_0000_0000;
end
8'd15:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd16:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd17:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd18:begin
col <= ~16'b0000_0001_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd19:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd20:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd21:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0001_0000_0000;
end
8'd22:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0001_0000_0000;
end
8'd23:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0001_0000_0000;
end
8'd24:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd25:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd26:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd27:begin
col <= ~16'b0000_0000_1000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd28:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd29:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0000_1000_0000;
end
8'd30:begin
col <= ~16'b0010_0000_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd31:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd32:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd33:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd34:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd35:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0000_0100_0000;
end
8'd36:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0000_0100_0000;
end
8'd37:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0000_0100_0000;
counter <= 0;
end
endcase
end
else begin
counter <= counter + 1;
case(counter)
8'd1:select <= Apple_1;
8'd2:select <= Apple_2;
8'd3:select <= Apple_3;
8'd4:select <= BodyA;
8'd5:select <= BodyB;
8'd6:select <= BodyC;
8'd7:begin
if(Snake_length >= 4) select <= BodyD;
else counter <= 0;
end
8'd8:begin
if(Snake_length >= 5) select <= BodyE;
else counter <= 0;
end
8'd9:begin
if(Snake_length >= 6) select <= BodyF;
else counter <= 0;
end
8'd10:begin
if(Snake_length >= 7) select <= BodyG;
else counter <= 0;
end
8'd11:begin
if(Snake_length >= 8) select <= BodyH;
else counter <= 0;
end
8'd12:begin
if(Snake_length >= 9) select <= BodyI;
else counter <= 0;
end
8'd13:begin
if(Snake_length >= 10) select <= BodyJ;
else counter <= 0;
end
8'd14:begin
if(Snake_length >= 11) select <= BodyK;
else counter <= 0;
end
8'd15:begin
if(Snake_length >= 12) select <= BodyL;
else counter <= 0;
end
8'd16:begin
if(Snake_length >= 13) select <= BodyM;
else counter <= 0;
end
8'd17:begin
if(Snake_length >= 14) select <= BodyN;
else counter <= 0;
end
8'd18:begin
if(Snake_length >= 15) select <= BodyO;
else counter <= 0;
end
8'd19:begin
if(Snake_length >= 16) select <= BodyP;
else counter <= 0;
counter <= 0;
end
endcase
case(select[7:4])
4'd0: col <= ~(16'b1000_0000_0000_0000);
4'd1: col <= ~16'b0100_0000_0000_0000;
4'd2: col <= ~16'b0010_0000_0000_0000;
4'd3: col <= ~16'b0001_0000_0000_0000;
4'd4: col <= ~16'b0000_1000_0000_0000;
4'd5: col <= ~16'b0000_0100_0000_0000;
4'd6: col <= ~16'b0000_0010_0000_0000;
4'd7: col <= ~16'b0000_0001_0000_0000;
4'd8: col <= ~16'b0000_0000_1000_0000;
4'd9: col <= ~16'b0000_0000_0100_0000;
4'd10: col <= ~16'b0000_0000_0010_0000;
4'd11: col <= ~16'b0000_0000_0001_0000;
4'd12: col <= ~16'b0000_0000_0000_1000;
4'd13: col <= ~16'b0000_0000_0000_0100;
4'd14: col <= ~16'b0000_0000_0000_0010;
4'd15: col <= ~16'b0000_0000_0000_0001;
endcase
case(select[3:0])
4'd0: row <= ~16'b1000_0000_0000_0000;
4'd1: row <= ~16'b0100_0000_0000_0000;
4'd2: row <= ~16'b0010_0000_0000_0000;
4'd3: row <= ~16'b0001_0000_0000_0000;
4'd4: row <= ~16'b0000_1000_0000_0000;
4'd5: row <= ~16'b0000_0100_0000_0000;
4'd6: row <= ~16'b0000_0010_0000_0000;
4'd7: row <= ~16'b0000_0001_0000_0000;
4'd8: row <= ~16'b0000_0000_1000_0000;
4'd9: row <= ~16'b0000_0000_0100_0000;
4'd10: row <= ~16'b0000_0000_0010_0000;
4'd11: row <= ~16'b0000_0000_0001_0000;
4'd12: row <= ~16'b0000_0000_0000_1000;
4'd13: row <= ~16'b0000_0000_0000_0100;
4'd14: row <= ~16'b0000_0000_0000_0010;
4'd15: row <= ~16'b0000_0000_0000_0001;
endcase
end
end
endmodule | module Array_decoder
(
input Clk,
input rst,
input [7:0] BodyA,
input [7:0] BodyB,
input [7:0] BodyC,
input [7:0] BodyD,
input [7:0] BodyE,
input [7:0] BodyF,
input [7:0] BodyG,
input [7:0] BodyH,
input [7:0] BodyI,
input [7:0] BodyJ,
input [7:0] BodyK,
input [7:0] BodyL,
input [7:0] BodyM,
input [7:0] BodyN,
input [7:0] BodyO,
input [7:0] BodyP,
input [7:0] Snake_length,
input [7:0] Apple_1,
input [7:0] Apple_2,
input [7:0] Apple_3,
input [2:0] Game_status,
output reg [15:0] row,
output reg [15:0] col
); |
parameter END = 3'b100;
parameter START = 3'b001;
reg [7:0] counter;
reg [7:0] select;
always@(posedge Clk)begin
if(~rst)begin
counter <= 0;
end
else if(Game_status == END | Game_status == START) begin
counter <= counter + 1;
case(counter)
8'd1:begin
col <= ~16'b0010_0000_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd2:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd3:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd4:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd5:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0100_0000_0000;
end
8'd6:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0100_0000_0000;
end
8'd7:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0100_0000_0000;
end
8'd8:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0100_0000_0000;
end
8'd9:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd10:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd11:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd12:begin
col <= ~16'b0000_0010_0000_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd13:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0010_0000_0000;
end
8'd14:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0010_0000_0000;
end
8'd15:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd16:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd17:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd18:begin
col <= ~16'b0000_0001_0000_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd19:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd20:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0001_0000_0000;
end
8'd21:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0001_0000_0000;
end
8'd22:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0001_0000_0000;
end
8'd23:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0001_0000_0000;
end
8'd24:begin
col <= ~16'b0100_0000_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd25:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd26:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd27:begin
col <= ~16'b0000_0000_1000_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd28:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0000_1000_0000;
end
8'd29:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0000_1000_0000;
end
8'd30:begin
col <= ~16'b0010_0000_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd31:begin
col <= ~16'b0001_0000_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd32:begin
col <= ~16'b0000_0100_0000_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd33:begin
col <= ~16'b0000_0000_0100_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd34:begin
col <= ~16'b0000_0000_0001_0000;
row <= ~16'b0000_0000_0100_0000;
end
8'd35:begin
col <= ~16'b0000_0000_0000_1000;
row <= ~16'b0000_0000_0100_0000;
end
8'd36:begin
col <= ~16'b0000_0000_0000_0100;
row <= ~16'b0000_0000_0100_0000;
end
8'd37:begin
col <= ~16'b0000_0000_0000_0010;
row <= ~16'b0000_0000_0100_0000;
counter <= 0;
end
endcase
end
else begin
counter <= counter + 1;
case(counter)
8'd1:select <= Apple_1;
8'd2:select <= Apple_2;
8'd3:select <= Apple_3;
8'd4:select <= BodyA;
8'd5:select <= BodyB;
8'd6:select <= BodyC;
8'd7:begin
if(Snake_length >= 4) select <= BodyD;
else counter <= 0;
end
8'd8:begin
if(Snake_length >= 5) select <= BodyE;
else counter <= 0;
end
8'd9:begin
if(Snake_length >= 6) select <= BodyF;
else counter <= 0;
end
8'd10:begin
if(Snake_length >= 7) select <= BodyG;
else counter <= 0;
end
8'd11:begin
if(Snake_length >= 8) select <= BodyH;
else counter <= 0;
end
8'd12:begin
if(Snake_length >= 9) select <= BodyI;
else counter <= 0;
end
8'd13:begin
if(Snake_length >= 10) select <= BodyJ;
else counter <= 0;
end
8'd14:begin
if(Snake_length >= 11) select <= BodyK;
else counter <= 0;
end
8'd15:begin
if(Snake_length >= 12) select <= BodyL;
else counter <= 0;
end
8'd16:begin
if(Snake_length >= 13) select <= BodyM;
else counter <= 0;
end
8'd17:begin
if(Snake_length >= 14) select <= BodyN;
else counter <= 0;
end
8'd18:begin
if(Snake_length >= 15) select <= BodyO;
else counter <= 0;
end
8'd19:begin
if(Snake_length >= 16) select <= BodyP;
else counter <= 0;
counter <= 0;
end
endcase
case(select[7:4])
4'd0: col <= ~(16'b1000_0000_0000_0000);
4'd1: col <= ~16'b0100_0000_0000_0000;
4'd2: col <= ~16'b0010_0000_0000_0000;
4'd3: col <= ~16'b0001_0000_0000_0000;
4'd4: col <= ~16'b0000_1000_0000_0000;
4'd5: col <= ~16'b0000_0100_0000_0000;
4'd6: col <= ~16'b0000_0010_0000_0000;
4'd7: col <= ~16'b0000_0001_0000_0000;
4'd8: col <= ~16'b0000_0000_1000_0000;
4'd9: col <= ~16'b0000_0000_0100_0000;
4'd10: col <= ~16'b0000_0000_0010_0000;
4'd11: col <= ~16'b0000_0000_0001_0000;
4'd12: col <= ~16'b0000_0000_0000_1000;
4'd13: col <= ~16'b0000_0000_0000_0100;
4'd14: col <= ~16'b0000_0000_0000_0010;
4'd15: col <= ~16'b0000_0000_0000_0001;
endcase
case(select[3:0])
4'd0: row <= ~16'b1000_0000_0000_0000;
4'd1: row <= ~16'b0100_0000_0000_0000;
4'd2: row <= ~16'b0010_0000_0000_0000;
4'd3: row <= ~16'b0001_0000_0000_0000;
4'd4: row <= ~16'b0000_1000_0000_0000;
4'd5: row <= ~16'b0000_0100_0000_0000;
4'd6: row <= ~16'b0000_0010_0000_0000;
4'd7: row <= ~16'b0000_0001_0000_0000;
4'd8: row <= ~16'b0000_0000_1000_0000;
4'd9: row <= ~16'b0000_0000_0100_0000;
4'd10: row <= ~16'b0000_0000_0010_0000;
4'd11: row <= ~16'b0000_0000_0001_0000;
4'd12: row <= ~16'b0000_0000_0000_1000;
4'd13: row <= ~16'b0000_0000_0000_0100;
4'd14: row <= ~16'b0000_0000_0000_0010;
4'd15: row <= ~16'b0000_0000_0000_0001;
endcase
end
end
endmodule | 1 |
5,467 | data/full_repos/permissive/114380772/Snake/Game_ctrl_module.v | 114,380,772 | Game_ctrl_module.v | v | 66 | 68 | [] | [] | [] | [(1, 64)] | null | data/verilator_xmls/d40a2d17-57e4-40fe-9674-f540f24b8a93.xml | null | 6,263 | module | module Game_ctrl_module
(
input Clk_24mhz,
input Rst_n,
input Key_left,
input Key_right,
input Key_up,
input Key_down,
output reg [2:0] Game_status,
input Hit_wall_sig,
input Hit_body_sig,
output reg Flash_sig
);
parameter START = 3'b001;
parameter PLAY = 3'b010;
parameter END = 3'b100;
always @ (posedge Clk_24mhz or negedge Rst_n)
begin
if(!Rst_n)
begin
Game_status <= START;;
Flash_sig <= 1'd1;
end
else
begin
Game_status <= START;
case(Game_status)
START:
begin
if(Key_left | Key_right | Key_up | Key_down)
begin
Game_status <= PLAY;
end
else
Game_status <= START;
end
PLAY:
begin
if(Hit_wall_sig | Hit_body_sig)
begin
Game_status <= END;
end
else
Game_status <= PLAY;
end
END:
begin
if(Key_left | Key_right | Key_up | Key_down)
begin
Game_status <= START;
Flash_sig <= 1'd1;
end
else
begin
Game_status <= END;
Flash_sig <= 1'd1;
end
end
endcase
end
end
endmodule | module Game_ctrl_module
(
input Clk_24mhz,
input Rst_n,
input Key_left,
input Key_right,
input Key_up,
input Key_down,
output reg [2:0] Game_status,
input Hit_wall_sig,
input Hit_body_sig,
output reg Flash_sig
); |
parameter START = 3'b001;
parameter PLAY = 3'b010;
parameter END = 3'b100;
always @ (posedge Clk_24mhz or negedge Rst_n)
begin
if(!Rst_n)
begin
Game_status <= START;;
Flash_sig <= 1'd1;
end
else
begin
Game_status <= START;
case(Game_status)
START:
begin
if(Key_left | Key_right | Key_up | Key_down)
begin
Game_status <= PLAY;
end
else
Game_status <= START;
end
PLAY:
begin
if(Hit_wall_sig | Hit_body_sig)
begin
Game_status <= END;
end
else
Game_status <= PLAY;
end
END:
begin
if(Key_left | Key_right | Key_up | Key_down)
begin
Game_status <= START;
Flash_sig <= 1'd1;
end
else
begin
Game_status <= END;
Flash_sig <= 1'd1;
end
end
endcase
end
end
endmodule | 1 |
5,468 | data/full_repos/permissive/114380772/Snake/Greedy_snake.v | 114,380,772 | Greedy_snake.v | v | 170 | 78 | [] | [] | [] | [(1, 169)] | null | null | 1: b"%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:18: Cannot find file containing module: 'altpll0'\n altpll0 altpll0_inst (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/114380772/Snake,data/full_repos/permissive/114380772/altpll0\n data/full_repos/permissive/114380772/Snake,data/full_repos/permissive/114380772/altpll0.v\n data/full_repos/permissive/114380772/Snake,data/full_repos/permissive/114380772/altpll0.sv\n altpll0\n altpll0.v\n altpll0.sv\n obj_dir/altpll0\n obj_dir/altpll0.v\n obj_dir/altpll0.sv\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:34: Cannot find file containing module: 'Game_ctrl_module'\n Game_ctrl_module U2( \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:55: Cannot find file containing module: 'Apple_generate_module'\n Apple_generate_module U3( \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:85: Cannot find file containing module: 'Snake_ctrl_module'\n Snake_ctrl_module U4( \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:118: Cannot find file containing module: 'Key_check_module'\n Key_check_module U6( \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:132: Cannot find file containing module: 'Smg_display_module'\n Smg_display_module U7( \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/114380772/Snake/Greedy_snake.v:141: Cannot find file containing module: 'Array_decoder'\n Array_decoder U8(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n" | 6,264 | module | module Greedy_snake
(
input Clk,
input Rst_n,
input Left,
input Right,
input Up,
input Down,
output [7:0] Smg_duan,
output [3:0] Smg_we,
output [15:0] Array_row,
output [15:0] Array_col
);
wire Clk_24mhz;
wire Clk_10khz;
altpll0 altpll0_inst (
.inclk0(Clk),
.c0(Clk_24mhz),
.c1(Clk_10khz)
);
wire Key_left;
wire Key_right;
wire Key_up;
wire Key_down;
wire [2:0] Game_status;
wire Hit_wall_sig;
wire Hit_body_sig;
wire Flash_sig;
wire Restart_sig;
Game_ctrl_module U2(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down),
.Game_status(Game_status),
.Hit_wall_sig(Hit_wall_sig),
.Hit_body_sig(Hit_body_sig),
.Flash_sig(Flash_sig)
);
wire [7:0] Apple_1;
wire [7:0] Apple_2;
wire [7:0] Apple_3;
wire [7:0] Head;
wire Body_add_sig;
Apple_generate_module U3(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Apple_1(Apple_1),
.Apple_2(Apple_2),
.Apple_3(Apple_3),
.Head(Head),
.Body_add_sig(Body_add_sig)
);
wire [6:0] Body_num;
wire [7:0] BodyA;
wire [7:0] BodyB;
wire [7:0] BodyC;
wire [7:0] BodyD;
wire [7:0] BodyE;
wire [7:0] BodyF;
wire [7:0] BodyG;
wire [7:0] BodyH;
wire [7:0] BodyI;
wire [7:0] BodyJ;
wire [7:0] BodyK;
wire [7:0] BodyL;
wire [7:0] BodyM;
wire [7:0] BodyN;
wire [7:0] BodyO;
wire [7:0] BodyP;
wire [7:0] Snake_length;
Snake_ctrl_module U4(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down),
.Head(Head),
.Body_add_sig(Body_add_sig),
.Game_status(Game_status),
.Hit_body_sig(Hit_body_sig),
.Hit_wall_sig(Hit_wall_sig),
.Flash_sig(Flash_sig),
.BodyA(BodyA),
.BodyB(BodyB),
.BodyC(BodyC),
.BodyD(BodyD),
.BodyE(BodyE),
.BodyF(BodyF),
.BodyG(BodyG),
.BodyH(BodyH),
.BodyI(BodyI),
.BodyJ(BodyJ),
.BodyK(BodyK),
.BodyL(BodyL),
.BodyM(BodyM),
.BodyN(BodyN),
.BodyO(BodyO),
.BodyP(BodyP),
.Snake_length(Snake_length)
);
Key_check_module U6(
.Clk_10khz(Clk_10khz),
.Rst_n(Rst_n),
.Left(~Left),
.Right(~Right),
.Up(~Up),
.Down(~Down),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down)
);
Smg_display_module U7(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Body_add_sig(Body_add_sig),
.Game_status(Game_status),
.Smg_duan(Smg_duan),
.Smg_we(Smg_we)
);
Array_decoder U8(
.Clk(Clk_10khz),
.rst(Rst_n),
.BodyA(BodyA),
.BodyB(BodyB),
.BodyC(BodyC),
.BodyD(BodyD),
.BodyE(BodyE),
.BodyF(BodyF),
.BodyG(BodyG),
.BodyH(BodyH),
.BodyI(BodyI),
.BodyJ(BodyJ),
.BodyK(BodyK),
.BodyL(BodyL),
.BodyM(BodyM),
.BodyN(BodyN),
.BodyO(BodyO),
.BodyP(BodyP),
.Snake_length(Snake_length),
.Apple_1(Apple_1),
.Apple_2(Apple_2),
.Apple_3(Apple_3),
.Game_status(Game_status),
.row(Array_row),
.col(Array_col)
);
endmodule | module Greedy_snake
(
input Clk,
input Rst_n,
input Left,
input Right,
input Up,
input Down,
output [7:0] Smg_duan,
output [3:0] Smg_we,
output [15:0] Array_row,
output [15:0] Array_col
); |
wire Clk_24mhz;
wire Clk_10khz;
altpll0 altpll0_inst (
.inclk0(Clk),
.c0(Clk_24mhz),
.c1(Clk_10khz)
);
wire Key_left;
wire Key_right;
wire Key_up;
wire Key_down;
wire [2:0] Game_status;
wire Hit_wall_sig;
wire Hit_body_sig;
wire Flash_sig;
wire Restart_sig;
Game_ctrl_module U2(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down),
.Game_status(Game_status),
.Hit_wall_sig(Hit_wall_sig),
.Hit_body_sig(Hit_body_sig),
.Flash_sig(Flash_sig)
);
wire [7:0] Apple_1;
wire [7:0] Apple_2;
wire [7:0] Apple_3;
wire [7:0] Head;
wire Body_add_sig;
Apple_generate_module U3(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Apple_1(Apple_1),
.Apple_2(Apple_2),
.Apple_3(Apple_3),
.Head(Head),
.Body_add_sig(Body_add_sig)
);
wire [6:0] Body_num;
wire [7:0] BodyA;
wire [7:0] BodyB;
wire [7:0] BodyC;
wire [7:0] BodyD;
wire [7:0] BodyE;
wire [7:0] BodyF;
wire [7:0] BodyG;
wire [7:0] BodyH;
wire [7:0] BodyI;
wire [7:0] BodyJ;
wire [7:0] BodyK;
wire [7:0] BodyL;
wire [7:0] BodyM;
wire [7:0] BodyN;
wire [7:0] BodyO;
wire [7:0] BodyP;
wire [7:0] Snake_length;
Snake_ctrl_module U4(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down),
.Head(Head),
.Body_add_sig(Body_add_sig),
.Game_status(Game_status),
.Hit_body_sig(Hit_body_sig),
.Hit_wall_sig(Hit_wall_sig),
.Flash_sig(Flash_sig),
.BodyA(BodyA),
.BodyB(BodyB),
.BodyC(BodyC),
.BodyD(BodyD),
.BodyE(BodyE),
.BodyF(BodyF),
.BodyG(BodyG),
.BodyH(BodyH),
.BodyI(BodyI),
.BodyJ(BodyJ),
.BodyK(BodyK),
.BodyL(BodyL),
.BodyM(BodyM),
.BodyN(BodyN),
.BodyO(BodyO),
.BodyP(BodyP),
.Snake_length(Snake_length)
);
Key_check_module U6(
.Clk_10khz(Clk_10khz),
.Rst_n(Rst_n),
.Left(~Left),
.Right(~Right),
.Up(~Up),
.Down(~Down),
.Key_left(Key_left),
.Key_right(Key_right),
.Key_up(Key_up),
.Key_down(Key_down)
);
Smg_display_module U7(
.Clk_24mhz(Clk_24mhz),
.Rst_n(Rst_n),
.Body_add_sig(Body_add_sig),
.Game_status(Game_status),
.Smg_duan(Smg_duan),
.Smg_we(Smg_we)
);
Array_decoder U8(
.Clk(Clk_10khz),
.rst(Rst_n),
.BodyA(BodyA),
.BodyB(BodyB),
.BodyC(BodyC),
.BodyD(BodyD),
.BodyE(BodyE),
.BodyF(BodyF),
.BodyG(BodyG),
.BodyH(BodyH),
.BodyI(BodyI),
.BodyJ(BodyJ),
.BodyK(BodyK),
.BodyL(BodyL),
.BodyM(BodyM),
.BodyN(BodyN),
.BodyO(BodyO),
.BodyP(BodyP),
.Snake_length(Snake_length),
.Apple_1(Apple_1),
.Apple_2(Apple_2),
.Apple_3(Apple_3),
.Game_status(Game_status),
.row(Array_row),
.col(Array_col)
);
endmodule | 1 |
5,469 | data/full_repos/permissive/114380772/Snake/Key_check_module.v | 114,380,772 | Key_check_module.v | v | 70 | 78 | [] | [] | [] | [(1, 69)] | null | data/verilator_xmls/23b2931b-d9d9-4611-abf3-dd6d47819f44.xml | null | 6,265 | module | module Key_check_module
(
input Clk_10khz,
input Rst_n,
input Left,
input Right,
input Up,
input Down,
output reg Key_left,
output reg Key_right,
output reg Key_up,
output reg Key_down
);
reg [31:0] Count1;
reg Key_left2;
reg Key_right2;
reg Key_up2;
reg Key_down2;
always @ (posedge Clk_10khz or negedge Rst_n)
begin
if(!Rst_n)
begin
Count1 <= 32'd0;
Key_left <= 1'd0;
Key_right <= 1'd0;
Key_up <= 1'd0;
Key_down <= 1'd0;
Key_left2 <= 1'd0;
Key_right2 <= 1'd0;
Key_up2 <= 1'd0;
Key_down2 <= 1'd0;
end
else
begin
if(Count1 == 32'd1000)
begin
Count1 <= 0;
Key_left2 <= Left;
Key_right2 <= Right;
Key_up2 <= Up;
Key_down2 <= Down;
if((Key_left2 == 1'd1) && (Left == 1'd0))
Key_left <= 1'd1;
if((Key_right2 == 1'd1) && (Right == 1'd0))
Key_right <= 1'd1;
if((Key_up2 == 1'd1) && (Up == 1'd0))
Key_up <= 1'd1;
if((Key_down2 == 1'd1) && (Down == 1'd0))
Key_down <= 1'd1;
end
else
begin
Count1 <= Count1 + 1;
Key_left <= 1'd0;
Key_right <= 1'd0;
Key_up <= 1'd0;
Key_down <= 1'd0;
end
end
end
endmodule | module Key_check_module
(
input Clk_10khz,
input Rst_n,
input Left,
input Right,
input Up,
input Down,
output reg Key_left,
output reg Key_right,
output reg Key_up,
output reg Key_down
); |
reg [31:0] Count1;
reg Key_left2;
reg Key_right2;
reg Key_up2;
reg Key_down2;
always @ (posedge Clk_10khz or negedge Rst_n)
begin
if(!Rst_n)
begin
Count1 <= 32'd0;
Key_left <= 1'd0;
Key_right <= 1'd0;
Key_up <= 1'd0;
Key_down <= 1'd0;
Key_left2 <= 1'd0;
Key_right2 <= 1'd0;
Key_up2 <= 1'd0;
Key_down2 <= 1'd0;
end
else
begin
if(Count1 == 32'd1000)
begin
Count1 <= 0;
Key_left2 <= Left;
Key_right2 <= Right;
Key_up2 <= Up;
Key_down2 <= Down;
if((Key_left2 == 1'd1) && (Left == 1'd0))
Key_left <= 1'd1;
if((Key_right2 == 1'd1) && (Right == 1'd0))
Key_right <= 1'd1;
if((Key_up2 == 1'd1) && (Up == 1'd0))
Key_up <= 1'd1;
if((Key_down2 == 1'd1) && (Down == 1'd0))
Key_down <= 1'd1;
end
else
begin
Count1 <= Count1 + 1;
Key_left <= 1'd0;
Key_right <= 1'd0;
Key_up <= 1'd0;
Key_down <= 1'd0;
end
end
end
endmodule | 1 |
5,472 | data/full_repos/permissive/114421971/bram_rom/top.v | 114,421,971 | top.v | v | 345 | 94 | [] | [] | [] | [(8, 34), (36, 39), (46, 158), (160, 343)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/bram_rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/bram_rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,269 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,473 | data/full_repos/permissive/114421971/bram_rom/top.v | 114,421,971 | top.v | v | 345 | 94 | [] | [] | [] | [(8, 34), (36, 39), (46, 158), (160, 343)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/bram_rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/bram_rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,269 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
ram_RAMB18E1 #(.LOC("XXX"))
ram_RAMB18E1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
ram_RAMB18E1 #(.LOC("XXX"))
ram_RAMB18E1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
endmodule | 2 |
5,474 | data/full_repos/permissive/114421971/bram_rom/top.v | 114,421,971 | top.v | v | 345 | 94 | [] | [] | [] | [(8, 34), (36, 39), (46, 158), (160, 343)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/bram_rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/bram_rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,269 | module | module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
RAMB18E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule | module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
RAMB18E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule | 2 |
5,475 | data/full_repos/permissive/114421971/bram_rom/top.v | 114,421,971 | top.v | v | 345 | 94 | [] | [] | [] | [(8, 34), (36, 39), (46, 158), (160, 343)] | null | null | 1: b"%Error: data/full_repos/permissive/114421971/bram_rom/top.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/bram_rom/top.v:27: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,269 | module | module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
RAMB36E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule | module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout); |
parameter LOC = "";
RAMB36E1 #(
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.SIM_DEVICE("VIRTEX6")
) ram (
.CLKARDCLK(din[0]),
.CLKBWRCLK(din[1]),
.ENARDEN(din[2]),
.ENBWREN(din[3]),
.REGCEAREGCE(din[4]),
.REGCEB(din[5]),
.RSTRAMARSTRAM(din[6]),
.RSTRAMB(din[7]),
.RSTREGARSTREG(din[0]),
.RSTREGB(din[1]),
.ADDRARDADDR(din[2]),
.ADDRBWRADDR(din[3]),
.DIADI(din[4]),
.DIBDI(din[5]),
.DIPADIP(din[6]),
.DIPBDIP(din[7]),
.WEA(din[0]),
.WEBWE(din[1]),
.DOADO(dout[0]),
.DOBDO(dout[1]),
.DOPADOP(dout[2]),
.DOPBDOP(dout[3]));
endmodule | 2 |
5,477 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,478 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module roi(input clk, input [255:0] din, output [255:0] dout);
clb_a clb_a (.clk(clk), .din(din[ 0 +: 16]), .dout(dout[ 0 +: 16]));
clb_b clb_b (.clk(clk), .din(din[ 16 +: 16]), .dout(dout[ 16 +: 16]));
clb_c clb_c (.clk(clk), .din(din[ 32 +: 16]), .dout(dout[ 32 +: 16]));
clb_d clb_d (.clk(clk), .din(din[ 48 +: 16]), .dout(dout[ 48 +: 16]));
clb_e clb_e (.clk(clk), .din(din[ 64 +: 16]), .dout(dout[ 64 +: 16]));
clb_f clb_f (.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
clb_g clb_g (.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
clb_h clb_h (.clk(clk), .din(din[112 +: 16]), .dout(dout[112 +: 16]));
clb_i clb_i (.clk(clk), .din(din[128 +: 16]), .dout(dout[128 +: 16]));
clb_j clb_j (.clk(clk), .din(din[144 +: 16]), .dout(dout[144 +: 16]));
clb_k clb_k (.clk(clk), .din(din[160 +: 16]), .dout(dout[160 +: 16]));
clb_l clb_l (.clk(clk), .din(din[176 +: 16]), .dout(dout[176 +: 16]));
clb_m clb_m (.clk(clk), .din(din[192 +: 16]), .dout(dout[192 +: 16]));
clb_n clb_n (.clk(clk), .din(din[208 +: 16]), .dout(dout[208 +: 16]));
clb_o clb_o (.clk(clk), .din(din[224 +: 16]), .dout(dout[224 +: 16]));
clb_p clb_p (.clk(clk), .din(din[240 +: 16]), .dout(dout[240 +: 16]));
endmodule | module roi(input clk, input [255:0] din, output [255:0] dout); |
clb_a clb_a (.clk(clk), .din(din[ 0 +: 16]), .dout(dout[ 0 +: 16]));
clb_b clb_b (.clk(clk), .din(din[ 16 +: 16]), .dout(dout[ 16 +: 16]));
clb_c clb_c (.clk(clk), .din(din[ 32 +: 16]), .dout(dout[ 32 +: 16]));
clb_d clb_d (.clk(clk), .din(din[ 48 +: 16]), .dout(dout[ 48 +: 16]));
clb_e clb_e (.clk(clk), .din(din[ 64 +: 16]), .dout(dout[ 64 +: 16]));
clb_f clb_f (.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
clb_g clb_g (.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
clb_h clb_h (.clk(clk), .din(din[112 +: 16]), .dout(dout[112 +: 16]));
clb_i clb_i (.clk(clk), .din(din[128 +: 16]), .dout(dout[128 +: 16]));
clb_j clb_j (.clk(clk), .din(din[144 +: 16]), .dout(dout[144 +: 16]));
clb_k clb_k (.clk(clk), .din(din[160 +: 16]), .dout(dout[160 +: 16]));
clb_l clb_l (.clk(clk), .din(din[176 +: 16]), .dout(dout[176 +: 16]));
clb_m clb_m (.clk(clk), .din(din[192 +: 16]), .dout(dout[192 +: 16]));
clb_n clb_n (.clk(clk), .din(din[208 +: 16]), .dout(dout[208 +: 16]));
clb_o clb_o (.clk(clk), .din(din[224 +: 16]), .dout(dout[224 +: 16]));
clb_p clb_p (.clk(clk), .din(din[240 +: 16]), .dout(dout[240 +: 16]));
endmodule | 2 |
5,479 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_a (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | module clb_a (input clk, input [15:0] din, output [15:0] dout); |
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | 2 |
5,480 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_b (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X16Y101", BEL="AFF", DONT_TOUCH *)
FDSE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.S(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | module clb_b (input clk, input [15:0] din, output [15:0] dout); |
(* LOC="SLICE_X16Y101", BEL="AFF", DONT_TOUCH *)
FDSE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.S(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | 2 |
5,481 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_c (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X16Y102", BEL="AFF", DONT_TOUCH *)
FDCE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.CLR(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | module clb_c (input clk, input [15:0] din, output [15:0] dout); |
(* LOC="SLICE_X16Y102", BEL="AFF", DONT_TOUCH *)
FDCE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.CLR(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | 2 |
5,482 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_d (input clk, input [15:0] din, output [15:0] dout);
(* LOC="SLICE_X16Y103", BEL="AFF", DONT_TOUCH *)
FDPE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.PRE(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | module clb_d (input clk, input [15:0] din, output [15:0] dout); |
(* LOC="SLICE_X16Y103", BEL="AFF", DONT_TOUCH *)
FDPE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.PRE(din[1]),
.D(din[2])
);
assign dout[15:1] = 0;
endmodule | 2 |
5,483 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_e (input clk, input [15:0] din, output [15:0] dout);
wire tmp;
(* LOC="SLICE_X16Y104", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X16Y104", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule | module clb_e (input clk, input [15:0] din, output [15:0] dout); |
wire tmp;
(* LOC="SLICE_X16Y104", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X16Y104", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule | 2 |
5,484 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_f (input clk, input [15:0] din, output [15:0] dout);
wire tmp;
(* LOC="SLICE_X16Y105", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X16Y105", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule | module clb_f (input clk, input [15:0] din, output [15:0] dout); |
wire tmp;
(* LOC="SLICE_X16Y105", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(tmp)
);
(* LOC="SLICE_X16Y105", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(tmp)
);
assign dout[15:1] = 0;
endmodule | 2 |
5,485 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_g (input clk, input [15:0] din, output [15:0] dout);
wire a, b, c;
(* LOC="SLICE_X16Y106", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X16Y106", BEL="F7BMUX", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X16Y106", BEL="F8MUX", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X16Y106", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule | module clb_g (input clk, input [15:0] din, output [15:0] dout); |
wire a, b, c;
(* LOC="SLICE_X16Y106", BEL="D6LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X16Y106", BEL="F7BMUX", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X16Y106", BEL="F8MUX", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X16Y106", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule | 2 |
5,486 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_h (input clk, input [15:0] din, output [15:0] dout);
wire a, b, c;
(* LOC="SLICE_X16Y107", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X16Y107", BEL="F7BMUX", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X16Y107", BEL="F8MUX", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X16Y107", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule | module clb_h (input clk, input [15:0] din, output [15:0] dout); |
wire a, b, c;
(* LOC="SLICE_X16Y107", BEL="D5LUT", LOCK_PINS="I0:A1", DONT_TOUCH *)
LUT1 #(
.INIT(2'b01)
) lut (
.I0(din[2]),
.O(a)
);
(* LOC="SLICE_X16Y107", BEL="F7BMUX", DONT_TOUCH *)
MUXF7 mux1 (
.I0(a),
.I1(din[3]),
.S(din[4]),
.O(b)
);
(* LOC="SLICE_X16Y107", BEL="F8MUX", DONT_TOUCH *)
MUXF8 mux2 (
.I0(b),
.I1(din[5]),
.S(din[6]),
.O(c)
);
(* LOC="SLICE_X16Y107", BEL="BFF", DONT_TOUCH *)
FDRE ff (
.C(clk),
.Q(dout[0]),
.CE(din[0]),
.R(din[1]),
.D(c)
);
assign dout[15:1] = 0;
endmodule | 2 |
5,487 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_i (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_i (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,488 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_j (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_j (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,489 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_k (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_k (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,490 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_l (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_l (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,491 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_m (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_m (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,492 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_n (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_n (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,493 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_o (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_o (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,494 | data/full_repos/permissive/114421971/clbconfigs/top.v | 114,421,971 | top.v | v | 260 | 73 | [] | [] | [] | null | line:53: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:2: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbconfigs/top.v:21: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,271 | module | module clb_p (input clk, input [15:0] din, output [15:0] dout);
assign dout = 0;
endmodule | module clb_p (input clk, input [15:0] din, output [15:0] dout); |
assign dout = 0;
endmodule | 2 |
5,495 | data/full_repos/permissive/114421971/clbpips/top.v | 114,421,971 | top.v | v | 93 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n setseed.vh\n setseed.vh.v\n setseed.vh.sv\n obj_dir/setseed.vh\n obj_dir/setseed.vh.v\n obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n hash32 = v ^ `SEED;\n ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n hash32 = v ^ `SEED;\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,272 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 10;
localparam integer DOUT_N = 10;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 10;
localparam integer DOUT_N = 10;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
5,496 | data/full_repos/permissive/114421971/clbpips/top.v | 114,421,971 | top.v | v | 93 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n setseed.vh\n setseed.vh.v\n setseed.vh.sv\n obj_dir/setseed.vh\n obj_dir/setseed.vh.v\n obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n hash32 = v ^ `SEED;\n ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n hash32 = v ^ `SEED;\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,272 | module | module roi(input clk, input [9:0] din, output [9:0] dout);
localparam integer N = 200;
function [31:0] xorshift32(input [31:0] v);
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [31:0] hash32(input [31:0] v);
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction
function [63:0] hash64(input [31:0] v);
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction
wire [N*10+9:0] nets;
assign nets[9:0] = din;
assign dout = nets[N*10+9:N*10];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 10; j = j+1) begin:js
localparam integer k = i*10 + j + 10;
wire lut_out;
LUT6 #(
.INIT(hash64({i, j, 8'hff}))
) lut (
.I0(nets[hash32({i, j, 8'h00}) % k]),
.I1(nets[hash32({i, j, 8'h01}) % k]),
.I2(nets[k-10]),
.I3(nets[k-9]),
.I4(nets[k-8]),
.I5(nets[k-7]),
.O(lut_out)
);
reg lut_out_reg;
always @(posedge clk)
lut_out_reg <= lut_out;
assign nets[k] = ((i+j) % 17) < 10 ? lut_out_reg : lut_out;
end
end
endgenerate
endmodule | module roi(input clk, input [9:0] din, output [9:0] dout); |
localparam integer N = 200;
function [31:0] xorshift32(input [31:0] v);
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [31:0] hash32(input [31:0] v);
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction
function [63:0] hash64(input [31:0] v);
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction
wire [N*10+9:0] nets;
assign nets[9:0] = din;
assign dout = nets[N*10+9:N*10];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 10; j = j+1) begin:js
localparam integer k = i*10 + j + 10;
wire lut_out;
LUT6 #(
.INIT(hash64({i, j, 8'hff}))
) lut (
.I0(nets[hash32({i, j, 8'h00}) % k]),
.I1(nets[hash32({i, j, 8'h01}) % k]),
.I2(nets[k-10]),
.I3(nets[k-9]),
.I4(nets[k-8]),
.I5(nets[k-7]),
.O(lut_out)
);
reg lut_out_reg;
always @(posedge clk)
lut_out_reg <= lut_out;
assign nets[k] = ((i+j) % 17) < 10 ? lut_out_reg : lut_out;
end
end
endgenerate
endmodule | 2 |
5,497 | data/full_repos/permissive/114421971/clbpips/top.v | 114,421,971 | top.v | v | 93 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n setseed.vh\n setseed.vh.v\n setseed.vh.sv\n obj_dir/setseed.vh\n obj_dir/setseed.vh.v\n obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n hash32 = v ^ `SEED;\n ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n hash32 = v ^ `SEED;\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,272 | function | function [31:0] xorshift32(input [31:0] v);
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction | function [31:0] xorshift32(input [31:0] v); |
begin
xorshift32 = v;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction | 2 |
5,498 | data/full_repos/permissive/114421971/clbpips/top.v | 114,421,971 | top.v | v | 93 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n setseed.vh\n setseed.vh.v\n setseed.vh.sv\n obj_dir/setseed.vh\n obj_dir/setseed.vh.v\n obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n hash32 = v ^ `SEED;\n ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n hash32 = v ^ `SEED;\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,272 | function | function [31:0] hash32(input [31:0] v);
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction | function [31:0] hash32(input [31:0] v); |
begin
hash32 = v ^ `SEED;
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
hash32 = xorshift32(hash32);
end
endfunction | 2 |
5,499 | data/full_repos/permissive/114421971/clbpips/top.v | 114,421,971 | top.v | v | 93 | 64 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/114421971/clbpips/top.v:1: Cannot find include file: setseed.vh\n`include "setseed.vh" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.v\n data/full_repos/permissive/114421971/clbpips,data/full_repos/permissive/114421971/setseed.vh.sv\n setseed.vh\n setseed.vh.v\n setseed.vh.sv\n obj_dir/setseed.vh\n obj_dir/setseed.vh.v\n obj_dir/setseed.vh.sv\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:3: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: Define or directive not defined: \'`SEED\'\n hash32 = v ^ `SEED;\n ^~~~~\n%Error: data/full_repos/permissive/114421971/clbpips/top.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n hash32 = v ^ `SEED;\n ^\n%Error: Exiting due to 5 error(s)\n' | 6,272 | function | function [63:0] hash64(input [31:0] v);
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction | function [63:0] hash64(input [31:0] v); |
begin
hash64[63:32] = hash32(v);
hash64[31: 0] = hash32(~v);
end
endfunction | 2 |
5,500 | data/full_repos/permissive/114421971/clb_bused/top.v | 114,421,971 | top.v | v | 87 | 83 | [] | [] | [] | null | line:41: before: "," | null | 1: b"%Error: data/full_repos/permissive/114421971/clb_bused/top.v:3: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule top(input clk, stb, di, output do);\n ^~\n%Error: data/full_repos/permissive/114421971/clb_bused/top.v:22: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n assign do = dout_shr[DOUT_N-1];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 6,273 | module | module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | module top(input clk, stb, di, output do); |
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule | 2 |
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