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3,413 | data/full_repos/permissive/104504209/PGM8755/src/programmer.v | 104,504,209 | programmer.v | v | 133 | 101 | [] | [] | [] | [(12, 117), (119, 132)] | null | data/verilator_xmls/0420d440-0505-41e4-ae05-8e6c726308a7.xml | null | 1,125 | module | module programmer(input clk, rst, mode, en, tx_busy, input [7:0] data_in, output reg tx_block, rdy,
ale, data_latch, ce, rd, output reg[10:0] addr_dat);
localparam PROGRAM = 2'b01, VERIFY = 2'b10, IDLE = 2'b00;
reg[1:0] state;
reg[10:0] address;
wire delay_rdy;
wire ale_rdy;
wire rd_wr_rdy;
wire prg_end;
reg start, addr_state, tx_state, prg_fall;
delay_cycles #(.WAIT_CYCLES(1000100)) prg_dly(.clk(clk), .rst(rst), .rdy(delay_rdy), .en(start));
delay_cycles #(.WAIT_CYCLES(3)) ale_dly(.clk(clk), .rst(rst), .rdy(ale_rdy), .en(ale));
delay_cycles #(.WAIT_CYCLES(100)) prg_fall_dly(.clk(clk), .rst(rst), .rdy(prg_end), .en(rd));
always@(posedge clk)begin
if(rst) begin
rdy <= 1'b0;
data_latch <= 1'b1;
addr_dat <= 11'b0;
state <= IDLE;
addr_state <= 1'b0;
addr_state <= 1'b1;
address <= 11'hFF0;
rd <= 1'b1;
tx_state <= 0;
prg_fall <= 0;
end
else begin
if(state == IDLE && ~en) begin
start <= 0;
rdy <= 0;
addr_dat <= 11'b0;
data_latch <= 0;
end
else if(state == IDLE && en) state <= (mode) ? PROGRAM:VERIFY;
else if(state == PROGRAM && en) begin
if(addr_state) begin
ce <= 1'b0;
addr_dat <= address;
ale <= 1;
if(ale_rdy) begin
addr_state <= 1'b0;
data_latch <= 1'b1;
ale <= 0;
end
end
else begin
start <= 1'b1;
rd <= 1'b1;
if(~delay_rdy) begin
ce <= 1'b1;
addr_dat[7:0] <= data_in;
data_latch <= 1'b0;
prg_fall <= 1'b1;
end
else begin
if(prg_end) begin
addr_state <= 1'b1;
address <= address - 1'b1;
start <= 1'b0;
prg_fall <= 1'b0;
end
end
end
end
else if(state == VERIFY && en) begin
ce <= 1'b0;
if(~tx_state && ~tx_busy) begin
rdy <= 1'b0;
ale <= 1'b1;
addr_dat <= address;
tx_state <= 1'b1;
rd <= 1'b1;
tx_block <= 1'b1;
end
else begin
tx_block <= 1'b0;
rd <= 1'b0;
rdy <= 1'b1;
end
end
else state <= IDLE;
end
end
endmodule | module programmer(input clk, rst, mode, en, tx_busy, input [7:0] data_in, output reg tx_block, rdy,
ale, data_latch, ce, rd, output reg[10:0] addr_dat); |
localparam PROGRAM = 2'b01, VERIFY = 2'b10, IDLE = 2'b00;
reg[1:0] state;
reg[10:0] address;
wire delay_rdy;
wire ale_rdy;
wire rd_wr_rdy;
wire prg_end;
reg start, addr_state, tx_state, prg_fall;
delay_cycles #(.WAIT_CYCLES(1000100)) prg_dly(.clk(clk), .rst(rst), .rdy(delay_rdy), .en(start));
delay_cycles #(.WAIT_CYCLES(3)) ale_dly(.clk(clk), .rst(rst), .rdy(ale_rdy), .en(ale));
delay_cycles #(.WAIT_CYCLES(100)) prg_fall_dly(.clk(clk), .rst(rst), .rdy(prg_end), .en(rd));
always@(posedge clk)begin
if(rst) begin
rdy <= 1'b0;
data_latch <= 1'b1;
addr_dat <= 11'b0;
state <= IDLE;
addr_state <= 1'b0;
addr_state <= 1'b1;
address <= 11'hFF0;
rd <= 1'b1;
tx_state <= 0;
prg_fall <= 0;
end
else begin
if(state == IDLE && ~en) begin
start <= 0;
rdy <= 0;
addr_dat <= 11'b0;
data_latch <= 0;
end
else if(state == IDLE && en) state <= (mode) ? PROGRAM:VERIFY;
else if(state == PROGRAM && en) begin
if(addr_state) begin
ce <= 1'b0;
addr_dat <= address;
ale <= 1;
if(ale_rdy) begin
addr_state <= 1'b0;
data_latch <= 1'b1;
ale <= 0;
end
end
else begin
start <= 1'b1;
rd <= 1'b1;
if(~delay_rdy) begin
ce <= 1'b1;
addr_dat[7:0] <= data_in;
data_latch <= 1'b0;
prg_fall <= 1'b1;
end
else begin
if(prg_end) begin
addr_state <= 1'b1;
address <= address - 1'b1;
start <= 1'b0;
prg_fall <= 1'b0;
end
end
end
end
else if(state == VERIFY && en) begin
ce <= 1'b0;
if(~tx_state && ~tx_busy) begin
rdy <= 1'b0;
ale <= 1'b1;
addr_dat <= address;
tx_state <= 1'b1;
rd <= 1'b1;
tx_block <= 1'b1;
end
else begin
tx_block <= 1'b0;
rd <= 1'b0;
rdy <= 1'b1;
end
end
else state <= IDLE;
end
end
endmodule | 0 |
3,414 | data/full_repos/permissive/104504209/PGM8755/src/programmer.v | 104,504,209 | programmer.v | v | 133 | 101 | [] | [] | [] | [(12, 117), (119, 132)] | null | data/verilator_xmls/0420d440-0505-41e4-ae05-8e6c726308a7.xml | null | 1,125 | module | module delay_cycles(input clk, rst, en, output rdy);
parameter WAIT_CYCLES = 1000000;
parameter CTR_SIZE = $clog2(WAIT_CYCLES);
reg[CTR_SIZE-1:0] counter;
always@(posedge clk) begin
if(rst || ~en) counter <= 0;
else counter <= counter + 1'b1;
end
assign rdy = counter == WAIT_CYCLES;
endmodule | module delay_cycles(input clk, rst, en, output rdy); |
parameter WAIT_CYCLES = 1000000;
parameter CTR_SIZE = $clog2(WAIT_CYCLES);
reg[CTR_SIZE-1:0] counter;
always@(posedge clk) begin
if(rst || ~en) counter <= 0;
else counter <= counter + 1'b1;
end
assign rdy = counter == WAIT_CYCLES;
endmodule | 0 |
3,415 | data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v | 104,504,209 | programmer_top.v | v | 64 | 109 | [] | [] | [] | [(35, 63)] | null | null | 1: b"%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:49: Cannot find file containing module: 'programmer'\n programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data), \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer\n data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer.v\n data/full_repos/permissive/104504209/PGM8755/src,data/full_repos/permissive/104504209/programmer.sv\n programmer\n programmer.v\n programmer.sv\n obj_dir/programmer\n obj_dir/programmer.v\n obj_dir/programmer.sv\n%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:53: Cannot find file containing module: 'buffer'\n buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));\n ^~~~~~\n%Error: data/full_repos/permissive/104504209/PGM8755/src/programmer_top.v:55: Cannot find file containing module: 'uart'\n uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data), \n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 1,126 | module | module programmer_top(input clk, rst_n, rx, mode, en, output tx, pce, rd, vdd_25, vdd_5,
ale, output[1:0]led, inout[10:0] address);
wire rst = ~rst_n;
wire[7:0] rx_data, buff_out;
wire new_rx_data, new_tx_data, busy, block;
programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data),
.tx_busy(busy), .addr_dat(address), .ce(pce), .rd(rd), .tx_block(block), .mode(mode),
.en(en), .ale(ale));
buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));
uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data),
.clk(clk), .tx_data(address[7:0]), .tx(tx), .new_rx_data(new_rx_data), .rx_data(rx_data),
.block(block), .busy(busy));
assign led[0] = new_rx_data;
assign led[1] = new_tx_data;
assign vdd_5 = ~vdd_25;
endmodule | module programmer_top(input clk, rst_n, rx, mode, en, output tx, pce, rd, vdd_25, vdd_5,
ale, output[1:0]led, inout[10:0] address); |
wire rst = ~rst_n;
wire[7:0] rx_data, buff_out;
wire new_rx_data, new_tx_data, busy, block;
programmer pgm(.clk(clk), .rst(rst), .data_latch(vdd_25), .data_in(buff_out), .rdy(new_tx_data),
.tx_busy(busy), .addr_dat(address), .ce(pce), .rd(rd), .tx_block(block), .mode(mode),
.en(en), .ale(ale));
buffer buff(.rst(rst), .clk(clk), .dir(en), .data_in(rx_data), .address(address), .data_out(buff_out));
uart #(.CLK_RATE(50000000), .SERIAL_BAUD_RATE(115200)) host(.rst(rst), .rx(rx), .new_tx_data(new_tx_data),
.clk(clk), .tx_data(address[7:0]), .tx(tx), .new_rx_data(new_rx_data), .rx_data(rx_data),
.block(block), .busy(busy));
assign led[0] = new_rx_data;
assign led[1] = new_tx_data;
assign vdd_5 = ~vdd_25;
endmodule | 0 |
3,417 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module pc(
input clk, rst, PCWre,
input [1:0] PCSrc,
input [31:0] immediate, readData1, addr,
output reg[31:0] pcout
);
initial begin
pcout = 0;
end
always@(negedge clk or negedge rst) begin
if (rst == 0) begin
pcout = 0;
end else if (PCWre) begin
if (PCSrc == 2'b00) begin
pcout = pcout + 4;
end else if (PCSrc == 2'b01) begin
pcout = pcout + 4 + immediate * 4;
end else if (PCSrc == 2'b10) begin
pcout = readData1;
end else if (PCSrc == 2'b11) begin
pcout = addr;
end
end
end
endmodule | module pc(
input clk, rst, PCWre,
input [1:0] PCSrc,
input [31:0] immediate, readData1, addr,
output reg[31:0] pcout
); |
initial begin
pcout = 0;
end
always@(negedge clk or negedge rst) begin
if (rst == 0) begin
pcout = 0;
end else if (PCWre) begin
if (PCSrc == 2'b00) begin
pcout = pcout + 4;
end else if (PCSrc == 2'b01) begin
pcout = pcout + 4 + immediate * 4;
end else if (PCSrc == 2'b10) begin
pcout = readData1;
end else if (PCSrc == 2'b11) begin
pcout = addr;
end
end
end
endmodule | 1 |
3,418 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module alu(
input [31:0] AData, BData, immediate,
input [4:0] sa,
input [2:0] ALUOp,
input ALUSrcA,ALUSrcB,
output reg zero,
output reg [31:0] ALUResult
);
initial
begin
ALUResult=0;
zero=1;
end
wire [31:0] A,B;
assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;
assign B=ALUSrcB ? immediate : BData;
always@(ALUOp or AData or BData or A or B)
begin
case(ALUOp)
3'b000 : ALUResult = A+B;
3'b001 : ALUResult = A-B;
3'b010 : ALUResult = (A<B)? 1:0;
3'b011 :
begin
if(A<B&&((A[31]==0&&B[31]==0)||(A[31]==1&&B[31]==1))) ALUResult =1;
else if(A[31]==0&&B[31]==1) ALUResult=0;
else if (A[31]==1 &&B[31]==0) ALUResult=1;
else ALUResult=0;
end
3'b100 : ALUResult = B << A;
3'b101 : ALUResult = A | B;
3'b110 : ALUResult = A & B;
3'b111 : ALUResult = (-A & B) | (A & -B);
default : ALUResult = 0;
endcase
zero = ALUResult ? 0 : 1;
end
endmodule | module alu(
input [31:0] AData, BData, immediate,
input [4:0] sa,
input [2:0] ALUOp,
input ALUSrcA,ALUSrcB,
output reg zero,
output reg [31:0] ALUResult
); |
initial
begin
ALUResult=0;
zero=1;
end
wire [31:0] A,B;
assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;
assign B=ALUSrcB ? immediate : BData;
always@(ALUOp or AData or BData or A or B)
begin
case(ALUOp)
3'b000 : ALUResult = A+B;
3'b001 : ALUResult = A-B;
3'b010 : ALUResult = (A<B)? 1:0;
3'b011 :
begin
if(A<B&&((A[31]==0&&B[31]==0)||(A[31]==1&&B[31]==1))) ALUResult =1;
else if(A[31]==0&&B[31]==1) ALUResult=0;
else if (A[31]==1 &&B[31]==0) ALUResult=1;
else ALUResult=0;
end
3'b100 : ALUResult = B << A;
3'b101 : ALUResult = A | B;
3'b110 : ALUResult = A & B;
3'b111 : ALUResult = (-A & B) | (A & -B);
default : ALUResult = 0;
endcase
zero = ALUResult ? 0 : 1;
end
endmodule | 1 |
3,419 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module extend(
input ExtSel,
input [15:0] halfImm,
output reg [31:0] Imm
);
initial
begin
Imm=0;
end
always@(ExtSel or halfImm)
begin
if(ExtSel)
Imm={{16{halfImm[15]}},halfImm[15:0]};
else
Imm={{16{0}},halfImm[15:0]};
end
endmodule | module extend(
input ExtSel,
input [15:0] halfImm,
output reg [31:0] Imm
); |
initial
begin
Imm=0;
end
always@(ExtSel or halfImm)
begin
if(ExtSel)
Imm={{16{halfImm[15]}},halfImm[15:0]};
else
Imm={{16{0}},halfImm[15:0]};
end
endmodule | 1 |
3,420 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module IR(
input IRWre,clk,
input [31:0] instruction,
output reg [31:0] IR_out
);
initial
begin
IR_out=0;
end
always@(negedge clk)
#2
begin
if(IRWre)
begin
IR_out <= instruction;
end
end
endmodule | module IR(
input IRWre,clk,
input [31:0] instruction,
output reg [31:0] IR_out
); |
initial
begin
IR_out=0;
end
always@(negedge clk)
#2
begin
if(IRWre)
begin
IR_out <= instruction;
end
end
endmodule | 1 |
3,421 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module DataLate(
input [31:0] i_data,
input clk,
output reg [31:0] o_data
);
always@(negedge clk)
begin
o_data=i_data;
end
endmodule | module DataLate(
input [31:0] i_data,
input clk,
output reg [31:0] o_data
); |
always@(negedge clk)
begin
o_data=i_data;
end
endmodule | 1 |
3,422 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module DataMemory(
input [31:0] DAddr,DataIn,
input RD,WR,
output reg [31:0] DataOut
);
reg [7:0] memory[0:127];
integer i;
initial
begin
DataOut=0;
for(i=0;i<128;i=i+1) memory[i] <= 0;
end
always@(RD or WR or DAddr or DataIn)
begin
if(RD)
begin
DataOut[31:24]=memory[DAddr];
DataOut[23:16]=memory[DAddr + 1];
DataOut[15:8]=memory[DAddr + 2];
DataOut[7:0]=memory[DAddr + 3];
end
else
if(WR)
begin
memory[DAddr]=DataIn[31:24];
memory[DAddr + 1]=DataIn[23:16];
memory[DAddr + 2]=DataIn[15:8];
memory[DAddr + 3]=DataIn[7:0];
end
end
endmodule | module DataMemory(
input [31:0] DAddr,DataIn,
input RD,WR,
output reg [31:0] DataOut
); |
reg [7:0] memory[0:127];
integer i;
initial
begin
DataOut=0;
for(i=0;i<128;i=i+1) memory[i] <= 0;
end
always@(RD or WR or DAddr or DataIn)
begin
if(RD)
begin
DataOut[31:24]=memory[DAddr];
DataOut[23:16]=memory[DAddr + 1];
DataOut[15:8]=memory[DAddr + 2];
DataOut[7:0]=memory[DAddr + 3];
end
else
if(WR)
begin
memory[DAddr]=DataIn[31:24];
memory[DAddr + 1]=DataIn[23:16];
memory[DAddr + 2]=DataIn[15:8];
memory[DAddr + 3]=DataIn[7:0];
end
end
endmodule | 1 |
3,423 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module InstructionMemory(
input [31:0]IAddr,
input InsMemRW,
output reg [31:0] instruction
);
reg [7:0] mem [0:127];
initial
begin
$readmemb("C:/Users/wonggwan/Desktop/ins.txt",mem);
end
always@(IAddr or InsMemRW)
begin
if(InsMemRW)
begin
instruction[31:24]=mem[IAddr];
instruction[23:16]=mem[IAddr+1];
instruction[15:8]=mem[IAddr+2];
instruction[7:0]=mem[IAddr+3];
end
end
endmodule | module InstructionMemory(
input [31:0]IAddr,
input InsMemRW,
output reg [31:0] instruction
); |
reg [7:0] mem [0:127];
initial
begin
$readmemb("C:/Users/wonggwan/Desktop/ins.txt",mem);
end
always@(IAddr or InsMemRW)
begin
if(InsMemRW)
begin
instruction[31:24]=mem[IAddr];
instruction[23:16]=mem[IAddr+1];
instruction[15:8]=mem[IAddr+2];
instruction[7:0]=mem[IAddr+3];
end
end
endmodule | 1 |
3,424 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module RegisterFile(
input [4:0] rs,rt,rd,
input [31:0] WriteData,
input [1:0] RegDst,
input clk,RegWre,
output reg [31:0] ReadData1,ReadData2
);
reg [31:0] register[0:31];
reg [4:0] WriteReg;
integer i;
initial
begin
for(i=0;i<32;i=i+1) register[i]=0;
end
always@(negedge clk)
begin
case(RegDst)
2'b00:WriteReg = 5'b11111;
2'b01:WriteReg = rt;
2'b10:WriteReg = rd;
endcase
assign ReadData1=register[rs];
assign ReadData2=register[rt];
end
always@(posedge clk)
begin
if(WriteReg != 0 && RegWre) register[WriteReg] = WriteData;
end
endmodule | module RegisterFile(
input [4:0] rs,rt,rd,
input [31:0] WriteData,
input [1:0] RegDst,
input clk,RegWre,
output reg [31:0] ReadData1,ReadData2
); |
reg [31:0] register[0:31];
reg [4:0] WriteReg;
integer i;
initial
begin
for(i=0;i<32;i=i+1) register[i]=0;
end
always@(negedge clk)
begin
case(RegDst)
2'b00:WriteReg = 5'b11111;
2'b01:WriteReg = rt;
2'b10:WriteReg = rd;
endcase
assign ReadData1=register[rs];
assign ReadData2=register[rt];
end
always@(posedge clk)
begin
if(WriteReg != 0 && RegWre) register[WriteReg] = WriteData;
end
endmodule | 1 |
3,425 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module pcaddr(
input [25:0] in,
input [31:0] PC0,
output reg [31:0] out
);
wire [31:0] PC4;
assign PC4=PC0+4;
always@(*)
begin
out[31:28]=PC4[31:28];
out[27:2]=in[25:0];
out[1:0]=0;
end
endmodule | module pcaddr(
input [25:0] in,
input [31:0] PC0,
output reg [31:0] out
); |
wire [31:0] PC4;
assign PC4=PC0+4;
always@(*)
begin
out[31:28]=PC4[31:28];
out[27:2]=in[25:0];
out[1:0]=0;
end
endmodule | 1 |
3,426 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module ControlUnit(
input clk,zero,rst,
input [5:0] op,
output reg WrRegData, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,
output reg[2:0] ALUOp,
output reg[1:0] RegDst, PCSrc
);
parameter[2:0] If=3'b000, id=3'b001,
exe1=3'b110,
exe2=3'b101,
exe3=3'b010,
wb1=3'b111,
wb2=3'b100,
mem=3'b011;
parameter[5:0] addu=6'b000000, subu=6'b000001, addiu=6'b000010,
Or=6'b010000, And=6'b010001, ori=6'b010010, sll=6'b011000,
sltu=6'b100110, slt=6'b100111, sw=6'b110000, lw=6'b110001,
beq=6'b110100, j=6'b111000, jr=6'b111001, jal=6'b111010, halt=6'b111111;
reg [2:0] state,nextstate;
initial
begin
PCWre=1;
ALUSrcA=0;
ALUSrcB=0;
ALUM2Reg=0;
RegWre=0;
WrRegData=0;
InsMemRW=0;
RD=0;
WR=0;
IRWre=1;
ExtSel=1;
PCSrc=2'b00;
RegDst=2'b01;
ALUOp=3'b000;
state=If;
nextstate=state;
end
always@(posedge clk)
begin
if(rst==0)
state<=If;
else
state<=nextstate;
end
always@(state or op)
begin
case(state)
If:nextstate=id;
id:begin
case(op)
beq:nextstate=exe2;
sw:nextstate=exe3;
lw:nextstate=exe3;
j:nextstate=If;
jal:nextstate=wb1;
jr:nextstate=If;
halt:nextstate=If;
addu:nextstate=exe1;
subu:nextstate=exe1;
addiu:nextstate=exe1;
Or:nextstate=exe1;
And:nextstate=exe1;
ori:nextstate=exe1;
sll:nextstate=exe1;
sltu:nextstate=exe1;
slt:nextstate=exe1;
endcase
end
exe1:nextstate=wb1;
exe2:nextstate=If;
exe3:nextstate=mem;
mem:if(op==lw) nextstate=wb2;
else if(op==sw) nextstate=If;
wb1:nextstate=If;
wb2:nextstate=If;
endcase
end
always@(state)
begin
if(state==If && op != halt) PCWre=1;
else PCWre=0;
if(op==sll) ALUSrcA=1;
else ALUSrcA=0;
if(op==addiu||op==ori||op==lw||op==sw) ALUSrcB=1;
else ALUSrcB=0;
if(op==lw) ALUM2Reg=1;
else ALUM2Reg=0;
if(state==wb1||state==wb2||op==jal) RegWre=1;
else RegWre=0;
if(op==jal) WrRegData=0;
else WrRegData=1;
InsMemRW=1;
if(state==mem && op==sw)
begin
WR=1;
RD=0;
end
else
begin
WR=0;
RD=1;
end
if(op !=halt) IRWre=1;
else IRWre=0;
if(op==ori) ExtSel=0;
else ExtSel=1;
case(op)
j:PCSrc=2'b11;
jal:PCSrc=2'b11;
jr:PCSrc=2'b10;
beq:if(zero) PCSrc=2'b01;
else PCSrc=2'b00;
default:PCSrc=2'b00;
endcase
if(op==jal) RegDst=2'b00;
else if(op==addiu||op==ori||op==lw) RegDst=2'b01;
else if(op==addu||op==subu||op==Or||op==And||op==sltu||op==sll||op==slt) RegDst=2'b10;
case(op)
subu:ALUOp=3'b001;
Or:ALUOp=3'b101;
And:ALUOp=3'b110;
ori:ALUOp=3'b101;
sll:ALUOp=3'b100;
sltu:ALUOp=3'b010;
beq:ALUOp=3'b001;
slt:ALUOp = 3'b011;
default: ALUOp=3'b000;
endcase
if(state==If)
begin
RegWre=0;
WR=0;
end
end
endmodule | module ControlUnit(
input clk,zero,rst,
input [5:0] op,
output reg WrRegData, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,
output reg[2:0] ALUOp,
output reg[1:0] RegDst, PCSrc
); |
parameter[2:0] If=3'b000, id=3'b001,
exe1=3'b110,
exe2=3'b101,
exe3=3'b010,
wb1=3'b111,
wb2=3'b100,
mem=3'b011;
parameter[5:0] addu=6'b000000, subu=6'b000001, addiu=6'b000010,
Or=6'b010000, And=6'b010001, ori=6'b010010, sll=6'b011000,
sltu=6'b100110, slt=6'b100111, sw=6'b110000, lw=6'b110001,
beq=6'b110100, j=6'b111000, jr=6'b111001, jal=6'b111010, halt=6'b111111;
reg [2:0] state,nextstate;
initial
begin
PCWre=1;
ALUSrcA=0;
ALUSrcB=0;
ALUM2Reg=0;
RegWre=0;
WrRegData=0;
InsMemRW=0;
RD=0;
WR=0;
IRWre=1;
ExtSel=1;
PCSrc=2'b00;
RegDst=2'b01;
ALUOp=3'b000;
state=If;
nextstate=state;
end
always@(posedge clk)
begin
if(rst==0)
state<=If;
else
state<=nextstate;
end
always@(state or op)
begin
case(state)
If:nextstate=id;
id:begin
case(op)
beq:nextstate=exe2;
sw:nextstate=exe3;
lw:nextstate=exe3;
j:nextstate=If;
jal:nextstate=wb1;
jr:nextstate=If;
halt:nextstate=If;
addu:nextstate=exe1;
subu:nextstate=exe1;
addiu:nextstate=exe1;
Or:nextstate=exe1;
And:nextstate=exe1;
ori:nextstate=exe1;
sll:nextstate=exe1;
sltu:nextstate=exe1;
slt:nextstate=exe1;
endcase
end
exe1:nextstate=wb1;
exe2:nextstate=If;
exe3:nextstate=mem;
mem:if(op==lw) nextstate=wb2;
else if(op==sw) nextstate=If;
wb1:nextstate=If;
wb2:nextstate=If;
endcase
end
always@(state)
begin
if(state==If && op != halt) PCWre=1;
else PCWre=0;
if(op==sll) ALUSrcA=1;
else ALUSrcA=0;
if(op==addiu||op==ori||op==lw||op==sw) ALUSrcB=1;
else ALUSrcB=0;
if(op==lw) ALUM2Reg=1;
else ALUM2Reg=0;
if(state==wb1||state==wb2||op==jal) RegWre=1;
else RegWre=0;
if(op==jal) WrRegData=0;
else WrRegData=1;
InsMemRW=1;
if(state==mem && op==sw)
begin
WR=1;
RD=0;
end
else
begin
WR=0;
RD=1;
end
if(op !=halt) IRWre=1;
else IRWre=0;
if(op==ori) ExtSel=0;
else ExtSel=1;
case(op)
j:PCSrc=2'b11;
jal:PCSrc=2'b11;
jr:PCSrc=2'b10;
beq:if(zero) PCSrc=2'b01;
else PCSrc=2'b00;
default:PCSrc=2'b00;
endcase
if(op==jal) RegDst=2'b00;
else if(op==addiu||op==ori||op==lw) RegDst=2'b01;
else if(op==addu||op==subu||op==Or||op==And||op==sltu||op==sll||op==slt) RegDst=2'b10;
case(op)
subu:ALUOp=3'b001;
Or:ALUOp=3'b101;
And:ALUOp=3'b110;
ori:ALUOp=3'b101;
sll:ALUOp=3'b100;
sltu:ALUOp=3'b010;
beq:ALUOp=3'b001;
slt:ALUOp = 3'b011;
default: ALUOp=3'b000;
endcase
if(state==If)
begin
RegWre=0;
WR=0;
end
end
endmodule | 1 |
3,427 | data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v | 104,620,603 | multicpu.v | v | 423 | 169 | [] | [] | [] | null | line:100: before: "begin" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:99: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:83: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.extend\n Imm={{16{0}},halfImm[15:0]};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:42: Unsized numbers/parameters not allowed in replications.\n : ... In instance multicpu.alu\n assign A=ALUSrcA ? {{27{0}},sa[4:0]} : AData;\n ^\n%Warning-WIDTH: data/full_repos/permissive/104620603/multicpu.srcs/sources_1/new/multicpu.v:64: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ALUResult\' generates 32 bits.\n : ... In instance multicpu.alu\n zero = ALUResult ? 0 : 1;\n ^\n%Error: Exiting due to 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,132 | module | module multicpu(
input clk,rst
);
wire PCWre,InsMemRW,IRWre,WrRegDSrc,ExtSel,RegWre,ALUSrcA,ALUSrcB,RD,WR,ALUM2Reg,zero;
wire [1:0] RegDst,PCSrc;
wire [2:0] ALUOp,state;
wire [4:0] rs,rt,rd,sa;
wire [5:0] op;
wire [15:0] halfImmediate;
wire [25:0] addr26;
wire [31:0] IAddr,IR_in,instruction,immediate,RegData1,RegData2,AData,BData,DataIn,DAddr,DataOut,result,ALUM2DR_in,ALUM2DR_out,PC4,WriteData,alu_a,alu_b,addr32;
assign PC4=IAddr+4;
assign op=instruction[31:26];
assign rs=instruction[25:21];
assign rt=instruction[20:16];
assign rd=instruction[15:11];
assign sa=instruction[15:11];
assign addr26=instruction[25:0];
assign halfImmediate=instruction[15:0];
assign WriteData=WrRegDSrc ? ALUM2DR_out:PC4;
assign ALUM2DR_in=ALUM2Reg? DataOut:result;
assign DataIn=BData;
pc pc(clk,rst,PCWre,PCSrc,immediate,RegData1,addr32,IAddr);
alu alu(AData,BData,immediate,sa,ALUOp,ALUSrcA,ALUSrcB,zero,result);
extend extend(ExtSel,halfImmediate,immediate);
IR ir(IRWre,clk,IR_in,instruction);
DataLate ADR(RegData1,clk,AData);
DataLate BDR(RegData2,clk,BData);
DataLate ALUM2DR(ALUM2DR_in,clk,ALUM2DR_out);
DataLate ALUout(result,clk,DAddr);
DataMemory DataMemory(DAddr,DataIn,RD,WR,DataOut);
InstructionMemory InsMemory(IAddr,InsMemRW,IR_in);
RegisterFile register(rs,rt,rd,WriteData,RegDst,clk,RegWre,RegData1,RegData2);
pcaddr pcaddr(addr26,IAddr,addr32);
ControlUnit ControlUnit(clk,zero,rst,op,WrRegDSrc, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,ALUOp,RegDst, PCSrc);
endmodule | module multicpu(
input clk,rst
); |
wire PCWre,InsMemRW,IRWre,WrRegDSrc,ExtSel,RegWre,ALUSrcA,ALUSrcB,RD,WR,ALUM2Reg,zero;
wire [1:0] RegDst,PCSrc;
wire [2:0] ALUOp,state;
wire [4:0] rs,rt,rd,sa;
wire [5:0] op;
wire [15:0] halfImmediate;
wire [25:0] addr26;
wire [31:0] IAddr,IR_in,instruction,immediate,RegData1,RegData2,AData,BData,DataIn,DAddr,DataOut,result,ALUM2DR_in,ALUM2DR_out,PC4,WriteData,alu_a,alu_b,addr32;
assign PC4=IAddr+4;
assign op=instruction[31:26];
assign rs=instruction[25:21];
assign rt=instruction[20:16];
assign rd=instruction[15:11];
assign sa=instruction[15:11];
assign addr26=instruction[25:0];
assign halfImmediate=instruction[15:0];
assign WriteData=WrRegDSrc ? ALUM2DR_out:PC4;
assign ALUM2DR_in=ALUM2Reg? DataOut:result;
assign DataIn=BData;
pc pc(clk,rst,PCWre,PCSrc,immediate,RegData1,addr32,IAddr);
alu alu(AData,BData,immediate,sa,ALUOp,ALUSrcA,ALUSrcB,zero,result);
extend extend(ExtSel,halfImmediate,immediate);
IR ir(IRWre,clk,IR_in,instruction);
DataLate ADR(RegData1,clk,AData);
DataLate BDR(RegData2,clk,BData);
DataLate ALUM2DR(ALUM2DR_in,clk,ALUM2DR_out);
DataLate ALUout(result,clk,DAddr);
DataMemory DataMemory(DAddr,DataIn,RD,WR,DataOut);
InstructionMemory InsMemory(IAddr,InsMemRW,IR_in);
RegisterFile register(rs,rt,rd,WriteData,RegDst,clk,RegWre,RegData1,RegData2);
pcaddr pcaddr(addr26,IAddr,addr32);
ControlUnit ControlUnit(clk,zero,rst,op,WrRegDSrc, ExtSel, RegWre, ALUSrcB, ALUSrcA, InsMemRW, IRWre, RD, WR, ALUM2Reg, PCWre,ALUOp,RegDst, PCSrc);
endmodule | 1 |
3,428 | data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv | 104,660,645 | template_Moore_machines.sv | sv | 62 | 122 | [] | [] | [] | null | line:4: before: "<" | null | 1: b"%Error: data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv:4: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n param1 = <value> ,\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv:7: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input logic clk, rst, ...\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv:8: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input logic [7:0] inp1, inp2, ...\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv:9: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n output logic [15:0] outp1, outp2, ...);\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_Moore_machines.sv:14: syntax error, unexpected '.', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n typedef enum logic [10:0] {A, B, C, ...} state;\n ^\n%Error: Exiting due to 5 error(s)\n" | 1,135 | module | module module_name
#(parameter
param1 = <value> ,
param2 = <value> )
(
input logic clk, rst, ...
input logic [7:0] inp1, inp2, ...
output logic [15:0] outp1, outp2, ...);
typedef enum logic [10:0] {A, B, C, ...} state;
state pr_state, nx_state;
always_ff @(posedge clk)
if (rst) pr_state < = A;
else pr_state < = nx_state;
always_comb
case (pr_state)
A: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (condition) nx_state = B;
else if (condition) nx_state = ...;
else nx_state = A;
end
B: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (condition) nx_state = C;
else if (condition) nx_state = ...;
else nx_state = B;
end
C: begin
...
end
...
endcase
always_ff @(posedge clk)
if (rst) begin
new_outp1 <= ...;
new_outp2 <= ...; ...
end
else begin
new_outp1 <= outp1;
new_outp2 <= outp2; ...
end
endmodule | module module_name
#(parameter
param1 = <value> ,
param2 = <value> )
(
input logic clk, rst, ...
input logic [7:0] inp1, inp2, ...
output logic [15:0] outp1, outp2, ...); |
typedef enum logic [10:0] {A, B, C, ...} state;
state pr_state, nx_state;
always_ff @(posedge clk)
if (rst) pr_state < = A;
else pr_state < = nx_state;
always_comb
case (pr_state)
A: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (condition) nx_state = B;
else if (condition) nx_state = ...;
else nx_state = A;
end
B: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (condition) nx_state = C;
else if (condition) nx_state = ...;
else nx_state = B;
end
C: begin
...
end
...
endcase
always_ff @(posedge clk)
if (rst) begin
new_outp1 <= ...;
new_outp2 <= ...; ...
end
else begin
new_outp1 <= outp1;
new_outp2 <= outp2; ...
end
endmodule | 0 |
3,429 | data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv | 104,660,645 | template_timed_Moore_machines.sv | sv | 76 | 124 | [] | [] | [] | null | line:6: before: "<" | null | 1: b"%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:6: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n param1 = <value> ,\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:9: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input logic clk, rst, ...\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:10: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n input logic [7:0] inp1, inp2, ...\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:11: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n output logic [15:0] outp1, outp2, ...);\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:16: syntax error, unexpected '.', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n typedef enum logic [10:0] {A, B, C, ...} state;\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:20: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] T1 = <value> ;\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:21: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] T2 = <value> ;\n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:22: syntax error, unexpected '<', expecting TYPE-IDENTIFIER\n const logic [7:0] tmax = <value> ; \n ^\n%Error: data/full_repos/permissive/104660645/FSM_templates/template_timed_Moore_machines.sv:28: syntax error, unexpected always_ff\n always_ff @(posedge clk, posedge rst)\n ^~~~~~~~~\n%Error: Exiting due to 9 error(s)\n" | 1,136 | module | module module_name
#(parameter
param1 = <value> ,
param2 = <value> )
(
input logic clk, rst, ...
input logic [7:0] inp1, inp2, ...
output logic [15:0] outp1, outp2, ...);
typedef enum logic [10:0] {A, B, C, ...} state;
state pr_state, nx_state;
const logic [7:0] T1 = <value> ;
const logic [7:0] T2 = <value> ;
const logic [7:0] tmax = <value> ;
logic [7:0] t;
always_ff @(posedge clk, posedge rst)
if (rst) t < = 0;
else if (pr_state != nx_state) t <= 0;
else if (t != tmax) t <= t + 1;
always_ff @(posedge clk, posedge rst)
if (rst) pr_state <= A;
else pr_state <= nx_state;
always_comb
case (pr_state)
A: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (... and t > =T1-1) nx_state = B;
else if (... and t >= T2-1) nx_state = ...;
else nx_state = A;
end
B: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (... and t >= T3-1) nx_state = C;
else if (...) nx_state = ...;
else nx_state = B;
end
C: begin
...
end
...
endcase
always_ff @(posedge clk)
if (rst) begin
new_outp1 <= ...;
new_outp2 <= ...; ...
end
else begin
new_outp1 <= outp1;
new_outp2 <= outp2; ...
end
endmodule | module module_name
#(parameter
param1 = <value> ,
param2 = <value> )
(
input logic clk, rst, ...
input logic [7:0] inp1, inp2, ...
output logic [15:0] outp1, outp2, ...); |
typedef enum logic [10:0] {A, B, C, ...} state;
state pr_state, nx_state;
const logic [7:0] T1 = <value> ;
const logic [7:0] T2 = <value> ;
const logic [7:0] tmax = <value> ;
logic [7:0] t;
always_ff @(posedge clk, posedge rst)
if (rst) t < = 0;
else if (pr_state != nx_state) t <= 0;
else if (t != tmax) t <= t + 1;
always_ff @(posedge clk, posedge rst)
if (rst) pr_state <= A;
else pr_state <= nx_state;
always_comb
case (pr_state)
A: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (... and t > =T1-1) nx_state = B;
else if (... and t >= T2-1) nx_state = ...;
else nx_state = A;
end
B: begin
outp1 = <value> ;
outp2 = <value> ;
...
if (... and t >= T3-1) nx_state = C;
else if (...) nx_state = ...;
else nx_state = B;
end
C: begin
...
end
...
endcase
always_ff @(posedge clk)
if (rst) begin
new_outp1 <= ...;
new_outp2 <= ...; ...
end
else begin
new_outp1 <= outp1;
new_outp2 <= outp2; ...
end
endmodule | 0 |
3,430 | data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv | 104,660,645 | debouncer_testbench.sv | sv | 38 | 83 | [] | [] | [] | null | line:18: before: "*" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:22: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk=~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:28: Unsupported: Ignoring delay on this delayed statement.\n #60 rst = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:29: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:30: Unsupported: Ignoring delay on this delayed statement.\n #50 PB = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:31: Unsupported: Ignoring delay on this delayed statement.\n #100 PB = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:32: Unsupported: Ignoring delay on this delayed statement.\n #50 PB = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #3 PB = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #20 PB = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:35: Unsupported: Ignoring delay on this delayed statement.\n #80 PB = 1\'b0;\n ^\n%Error: data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new/debouncer_testbench.sv:17: Cannot find file containing module: \'PB_Debouncer_counter\'\n PB_Debouncer_counter DUT(\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter\n data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter.v\n data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sim_1/new,data/full_repos/permissive/104660645/PB_Debouncer_counter.sv\n PB_Debouncer_counter\n PB_Debouncer_counter.v\n PB_Debouncer_counter.sv\n obj_dir/PB_Debouncer_counter\n obj_dir/PB_Debouncer_counter.v\n obj_dir/PB_Debouncer_counter.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,137 | module | module debouncer_testbench();
logic clk, rst, PB, PB_pressed_status, PB_pressed_pulse, PB_released_pulse;
PB_Debouncer_counter DUT(
.*
);
always #1 clk=~clk;
initial begin
clk = 1'b0;
rst = 1'b0;
#60 rst = 1'b1;
#30 rst = 1'b0;
#50 PB = 1'b1;
#100 PB = 1'b0;
#50 PB = 1'b1;
#3 PB = 1'b0;
#20 PB = 1'b1;
#80 PB = 1'b0;
end
endmodule | module debouncer_testbench(); |
logic clk, rst, PB, PB_pressed_status, PB_pressed_pulse, PB_released_pulse;
PB_Debouncer_counter DUT(
.*
);
always #1 clk=~clk;
initial begin
clk = 1'b0;
rst = 1'b0;
#60 rst = 1'b1;
#30 rst = 1'b0;
#50 PB = 1'b1;
#100 PB = 1'b0;
#50 PB = 1'b1;
#3 PB = 1'b0;
#20 PB = 1'b1;
#80 PB = 1'b0;
end
endmodule | 0 |
3,431 | data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sources_1/new/debouncer_counter.sv | 104,660,645 | debouncer_counter.sv | sv | 57 | 119 | [] | [] | [] | [(1, 57)] | null | data/verilator_xmls/d127163a-442d-45a5-a38d-82368e817fc3.xml | null | 1,138 | module | module PB_Debouncer_counter#(
parameter DELAY=15
)
(
input logic clk,
input logic rst,
input logic PB,
output logic PB_pressed_status,
output logic PB_pressed_pulse,
output logic PB_released_pulse
);
logic PB_sync_aux, PB_sync;
always_ff @(posedge clk) begin
if (rst) begin
PB_sync_aux <= 1'b0;
PB_sync <= 1'b0;
end
else begin
PB_sync_aux <= PB;
PB_sync <= PB_sync_aux;
end
end
localparam DELAY_WIDTH = $clog2(DELAY);
logic [DELAY_WIDTH-1:0] PB_cnt;
logic PB_IDLE;
logic PB_COUNT_MAX;
assign PB_IDLE = (PB_pressed_status==PB_sync);
assign PB_COUNT_MAX = &PB_cnt;
always_ff @(posedge clk) begin
if (rst) begin
PB_pressed_status <= 1'b0;
end
else
if(PB_IDLE)
PB_cnt <= 0;
else begin
PB_cnt <= PB_cnt + 'd1;
if(PB_COUNT_MAX) PB_pressed_status <= ~PB_pressed_status;
end
end
assign PB_pressed_pulse = ~PB_IDLE & PB_COUNT_MAX & ~PB_pressed_status;
assign PB_released_pulse = ~PB_IDLE & PB_COUNT_MAX & PB_pressed_status;
endmodule | module PB_Debouncer_counter#(
parameter DELAY=15
)
(
input logic clk,
input logic rst,
input logic PB,
output logic PB_pressed_status,
output logic PB_pressed_pulse,
output logic PB_released_pulse
); |
logic PB_sync_aux, PB_sync;
always_ff @(posedge clk) begin
if (rst) begin
PB_sync_aux <= 1'b0;
PB_sync <= 1'b0;
end
else begin
PB_sync_aux <= PB;
PB_sync <= PB_sync_aux;
end
end
localparam DELAY_WIDTH = $clog2(DELAY);
logic [DELAY_WIDTH-1:0] PB_cnt;
logic PB_IDLE;
logic PB_COUNT_MAX;
assign PB_IDLE = (PB_pressed_status==PB_sync);
assign PB_COUNT_MAX = &PB_cnt;
always_ff @(posedge clk) begin
if (rst) begin
PB_pressed_status <= 1'b0;
end
else
if(PB_IDLE)
PB_cnt <= 0;
else begin
PB_cnt <= PB_cnt + 'd1;
if(PB_COUNT_MAX) PB_pressed_status <= ~PB_pressed_status;
end
end
assign PB_pressed_pulse = ~PB_IDLE & PB_COUNT_MAX & ~PB_pressed_status;
assign PB_released_pulse = ~PB_IDLE & PB_COUNT_MAX & PB_pressed_status;
endmodule | 0 |
3,432 | data/full_repos/permissive/104660645/PB_debouncer_examples/project_1.srcs/sources_1/new/debouncer_FSM.sv | 104,660,645 | debouncer_FSM.sv | sv | 98 | 108 | [] | [] | [] | null | line:33: before: "logic" | data/verilator_xmls/e93fa21a-ae66-4040-bd78-6b027e4b1893.xml | null | 1,139 | module | module PB_Debouncer_FSM #(
parameter DELAY=15
)
(
input logic clk,
input logic rst,
input logic PB,
output logic PB_pressed_status,
output logic PB_pressed_pulse,
output logic PB_released_pulse
);
logic PB_sync_aux, PB_sync;
always_ff @(posedge clk) begin
if (rst) begin
PB_sync_aux <= 1'b0;
PB_sync <= 1'b0;
end
else begin
PB_sync_aux <= PB;
PB_sync <= PB_sync_aux;
end
end
localparam DELAY_WIDTH = $clog2(DELAY);
logic [DELAY_WIDTH-1:0] delay_timer;
enum logic[5:0] {PB_IDLE, PB_COUNT, PB_PRESSED, PB_STABLE, PB_RELEASED} state, next_state;
always_ff @(posedge clk) begin
if (rst) delay_timer <= 0;
else if (state != next_state) delay_timer <= 0;
else delay_timer <= delay_timer + 1;
end
always_comb begin
next_state = PB_IDLE;
PB_pressed_status = 1'b0;
PB_pressed_pulse = 1'b0;
PB_released_pulse = 1'b0;
case (state)
PB_IDLE: begin
if(PB_sync) begin
next_state= PB_COUNT;
end
end
PB_COUNT: begin
if ((PB_sync && (delay_timer >= DELAY-1))) begin
next_state = PB_PRESSED;
end
else if (PB_sync)
next_state = PB_COUNT;
end
PB_PRESSED: begin
PB_pressed_pulse = 1'b1;
if (PB_sync)
next_state = PB_STABLE;
end
PB_STABLE: begin
PB_pressed_status=1'b1;
next_state = PB_STABLE;
if (~PB_sync)
next_state = PB_RELEASED;
end
PB_RELEASED: begin
PB_released_pulse = 1'b1;
next_state = PB_IDLE;
end
endcase
end
always_ff@(posedge clk) begin
if(rst)
state <= PB_IDLE;
else
state <= next_state;
end
endmodule | module PB_Debouncer_FSM #(
parameter DELAY=15
)
(
input logic clk,
input logic rst,
input logic PB,
output logic PB_pressed_status,
output logic PB_pressed_pulse,
output logic PB_released_pulse
); |
logic PB_sync_aux, PB_sync;
always_ff @(posedge clk) begin
if (rst) begin
PB_sync_aux <= 1'b0;
PB_sync <= 1'b0;
end
else begin
PB_sync_aux <= PB;
PB_sync <= PB_sync_aux;
end
end
localparam DELAY_WIDTH = $clog2(DELAY);
logic [DELAY_WIDTH-1:0] delay_timer;
enum logic[5:0] {PB_IDLE, PB_COUNT, PB_PRESSED, PB_STABLE, PB_RELEASED} state, next_state;
always_ff @(posedge clk) begin
if (rst) delay_timer <= 0;
else if (state != next_state) delay_timer <= 0;
else delay_timer <= delay_timer + 1;
end
always_comb begin
next_state = PB_IDLE;
PB_pressed_status = 1'b0;
PB_pressed_pulse = 1'b0;
PB_released_pulse = 1'b0;
case (state)
PB_IDLE: begin
if(PB_sync) begin
next_state= PB_COUNT;
end
end
PB_COUNT: begin
if ((PB_sync && (delay_timer >= DELAY-1))) begin
next_state = PB_PRESSED;
end
else if (PB_sync)
next_state = PB_COUNT;
end
PB_PRESSED: begin
PB_pressed_pulse = 1'b1;
if (PB_sync)
next_state = PB_STABLE;
end
PB_STABLE: begin
PB_pressed_status=1'b1;
next_state = PB_STABLE;
if (~PB_sync)
next_state = PB_RELEASED;
end
PB_RELEASED: begin
PB_released_pulse = 1'b1;
next_state = PB_IDLE;
end
endcase
end
always_ff@(posedge clk) begin
if(rst)
state <= PB_IDLE;
else
state <= next_state;
end
endmodule | 0 |
3,433 | data/full_repos/permissive/104660645/sequence_detector/src/hdl/bcd_to_ss.v | 104,660,645 | bcd_to_ss.v | v | 38 | 55 | [] | [] | [] | [(10, 37)] | null | data/verilator_xmls/8484f066-5bca-4149-af10-2faedda61683.xml | null | 1,140 | module | module bcd_to_ss
(
input [3:0] bcd_in,
output reg [6:0] out
);
always @(*) begin
case (bcd_in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'hA: out = 7'b0001000;
4'hB: out = 7'b0000011;
4'hC: out = 7'b1000110;
4'hD: out = 7'b0100001;
4'hE: out = 7'b0000110;
default:
out = 7'b0001110;
endcase
end
endmodule | module bcd_to_ss
(
input [3:0] bcd_in,
output reg [6:0] out
); |
always @(*) begin
case (bcd_in)
4'h0: out = 7'b1000000;
4'h1: out = 7'b1111001;
4'h2: out = 7'b0100100;
4'h3: out = 7'b0110000;
4'h4: out = 7'b0011001;
4'h5: out = 7'b0010010;
4'h6: out = 7'b0000010;
4'h7: out = 7'b1111000;
4'h8: out = 7'b0000000;
4'h9: out = 7'b0010000;
4'hA: out = 7'b0001000;
4'hB: out = 7'b0000011;
4'hC: out = 7'b1000110;
4'hD: out = 7'b0100001;
4'hE: out = 7'b0000110;
default:
out = 7'b0001110;
endcase
end
endmodule | 0 |
3,434 | data/full_repos/permissive/104660645/sequence_detector/src/hdl/detector_secuencia.v | 104,660,645 | detector_secuencia.v | v | 80 | 53 | [] | [] | [] | null | line:24: before: "=" | data/verilator_xmls/249df101-4279-4728-8665-877d323822e4.xml | null | 1,142 | module | module detector_secuencia
(
input clk,
input reset,
input in,
input tick,
output [2:0] current_state,
output reg out
);
localparam S0 = 'b000;
localparam S1 = 'b001;
localparam S2 = 'b010;
localparam S3 = 'b011;
localparam S4 = 'b100;
reg [2:0] state, state_next = S0;
assign current_state = state;
always @(*) begin
case (state)
S0:
if (in == 1'b1)
state_next = S1;
else
state_next = S0;
S1:
if (in == 1'b0)
state_next = S2;
else
state_next = S1;
S2:
if (in == 1'b1)
state_next = S3;
else
state_next = S0;
S3:
if (in == 1'b1)
state_next = S4;
else
state_next = S2;
S4:
if (in == 1'b0)
state_next = S2;
else
state_next = S1;
default:
state_next = S0;
endcase
end
always @(*) begin
if (state == S4)
out = 1'b1;
else
out = 1'b0;
end
always @(posedge clk) begin
if (reset)
state <= S0;
else if (tick)
state <= state_next;
else
state <= state;
end
endmodule | module detector_secuencia
(
input clk,
input reset,
input in,
input tick,
output [2:0] current_state,
output reg out
); |
localparam S0 = 'b000;
localparam S1 = 'b001;
localparam S2 = 'b010;
localparam S3 = 'b011;
localparam S4 = 'b100;
reg [2:0] state, state_next = S0;
assign current_state = state;
always @(*) begin
case (state)
S0:
if (in == 1'b1)
state_next = S1;
else
state_next = S0;
S1:
if (in == 1'b0)
state_next = S2;
else
state_next = S1;
S2:
if (in == 1'b1)
state_next = S3;
else
state_next = S0;
S3:
if (in == 1'b1)
state_next = S4;
else
state_next = S2;
S4:
if (in == 1'b0)
state_next = S2;
else
state_next = S1;
default:
state_next = S0;
endcase
end
always @(*) begin
if (state == S4)
out = 1'b1;
else
out = 1'b0;
end
always @(posedge clk) begin
if (reset)
state <= S0;
else if (tick)
state <= state_next;
else
state <= state;
end
endmodule | 0 |
3,435 | data/full_repos/permissive/104660645/sequence_detector/src/hdl/pb_debouncer.v | 104,660,645 | pb_debouncer.v | v | 95 | 58 | [] | [] | [] | null | line:23: before: "=" | data/verilator_xmls/f7bdbf9e-553a-44f0-8ce2-588759361bad.xml | null | 1,143 | module | module pb_debouncer
#(
parameter COUNTER_WIDTH = 16
)(
input clk,
input rst,
input pb,
output reg pb_state,
output reg pb_negedge,
output reg pb_posedge
);
localparam PB_IDLE = 3'b000;
localparam PB_COUNT = 3'b001;
localparam PB_PE = 3'b010;
localparam PB_STABLE = 3'b011;
localparam PB_NE = 3'b100;
localparam COUNTER_MSB = COUNTER_WIDTH - 1;
reg [2:0] button_state, button_state_next = PB_IDLE;
reg [COUNTER_MSB:0] pb_cnt, pb_cnt_next;
reg [1:0] pb_sync_sr;
wire pb_sync = pb_sync_sr[0];
wire pb_cnt_max = &pb_cnt;
always @(posedge clk)
pb_sync_sr <= {pb, pb_sync_sr[1]};
always @(*) begin
button_state_next = button_state;
case (button_state)
PB_IDLE:
if (pb_sync == 1'b1)
button_state_next = PB_COUNT;
PB_COUNT:
if (pb_sync == 1'b0)
button_state_next = PB_IDLE;
else if (pb_cnt_max == 1'b1)
button_state_next = PB_PE;
PB_PE:
button_state_next = PB_STABLE;
PB_STABLE:
if (pb_sync == 1'b0)
button_state_next = PB_NE;
PB_NE:
button_state_next = PB_IDLE;
default:
button_state_next = PB_IDLE;
endcase
end
always @(*) begin
pb_state = 1'b0;
pb_negedge = 1'b0;
pb_posedge = 1'b0;
pb_cnt_next = 'd0;
case (button_state)
PB_STABLE:
pb_state = 1'b1;
PB_COUNT:
pb_cnt_next = pb_cnt + 'd1;
PB_PE: begin
pb_state = 1'b1;
pb_posedge = 1'b1;
end
PB_NE:
pb_negedge = 1'b1;
endcase
end
always @(posedge clk)
if (rst)
button_state <= PB_IDLE;
else
button_state <= button_state_next;
always @(posedge clk)
if (rst)
pb_cnt <= 'd0;
else
pb_cnt <= pb_cnt_next;
endmodule | module pb_debouncer
#(
parameter COUNTER_WIDTH = 16
)(
input clk,
input rst,
input pb,
output reg pb_state,
output reg pb_negedge,
output reg pb_posedge
); |
localparam PB_IDLE = 3'b000;
localparam PB_COUNT = 3'b001;
localparam PB_PE = 3'b010;
localparam PB_STABLE = 3'b011;
localparam PB_NE = 3'b100;
localparam COUNTER_MSB = COUNTER_WIDTH - 1;
reg [2:0] button_state, button_state_next = PB_IDLE;
reg [COUNTER_MSB:0] pb_cnt, pb_cnt_next;
reg [1:0] pb_sync_sr;
wire pb_sync = pb_sync_sr[0];
wire pb_cnt_max = &pb_cnt;
always @(posedge clk)
pb_sync_sr <= {pb, pb_sync_sr[1]};
always @(*) begin
button_state_next = button_state;
case (button_state)
PB_IDLE:
if (pb_sync == 1'b1)
button_state_next = PB_COUNT;
PB_COUNT:
if (pb_sync == 1'b0)
button_state_next = PB_IDLE;
else if (pb_cnt_max == 1'b1)
button_state_next = PB_PE;
PB_PE:
button_state_next = PB_STABLE;
PB_STABLE:
if (pb_sync == 1'b0)
button_state_next = PB_NE;
PB_NE:
button_state_next = PB_IDLE;
default:
button_state_next = PB_IDLE;
endcase
end
always @(*) begin
pb_state = 1'b0;
pb_negedge = 1'b0;
pb_posedge = 1'b0;
pb_cnt_next = 'd0;
case (button_state)
PB_STABLE:
pb_state = 1'b1;
PB_COUNT:
pb_cnt_next = pb_cnt + 'd1;
PB_PE: begin
pb_state = 1'b1;
pb_posedge = 1'b1;
end
PB_NE:
pb_negedge = 1'b1;
endcase
end
always @(posedge clk)
if (rst)
button_state <= PB_IDLE;
else
button_state <= button_state_next;
always @(posedge clk)
if (rst)
pb_cnt <= 'd0;
else
pb_cnt <= pb_cnt_next;
endmodule | 0 |
3,436 | data/full_repos/permissive/104660645/sequence_detector/src/hdl/ss_mux.v | 104,660,645 | ss_mux.v | v | 112 | 94 | [] | [] | [] | [(10, 111)] | null | null | 1: b"%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/ss_mux.v:46: Cannot find file containing module: 'bcd_to_ss'\n bcd_to_ss to_ss (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss.v\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/bcd_to_ss.sv\n bcd_to_ss\n bcd_to_ss.v\n bcd_to_ss.sv\n obj_dir/bcd_to_ss\n obj_dir/bcd_to_ss.v\n obj_dir/bcd_to_ss.sv\n%Error: Exiting due to 1 error(s)\n" | 1,144 | module | module ss_mux
(
input clk,
input [31:0] bcd,
input [7:0] dots,
output [7:0] ss_value,
output [7:0] ss_select
);
localparam DIG_0 = 8'b00000001;
localparam DIG_1 = 8'b00000010;
localparam DIG_2 = 8'b00000100;
localparam DIG_3 = 8'b00001000;
localparam DIG_4 = 8'b00010000;
localparam DIG_5 = 8'b00100000;
localparam DIG_6 = 8'b01000000;
localparam DIG_7 = 8'b10000000;
reg [7:0] ss_select_q;
reg [7:0] ss_select_d;
wire dot_enable;
assign dot_enable = |(ss_select_q & dots);
reg [3:0] bcd_nibble;
wire [6:0] ss_digits;
bcd_to_ss to_ss (
.bcd_in(bcd_nibble),
.out(ss_digits)
);
assign ss_value = {~dot_enable, ss_digits};
assign ss_select = ~ss_select_q;
always @(*) begin
case (ss_select_q)
DIG_0: begin
bcd_nibble = bcd[3:0];
ss_select_d = DIG_1;
end
DIG_1: begin
bcd_nibble = bcd[7:4];
ss_select_d = DIG_2;
end
DIG_2: begin
bcd_nibble = bcd[11:8];
ss_select_d = DIG_3;
end
DIG_3: begin
bcd_nibble = bcd[15:12];
ss_select_d = DIG_4;
end
DIG_4: begin
bcd_nibble = bcd[19:16];
ss_select_d = DIG_5;
end
DIG_5: begin
bcd_nibble = bcd[23:20];
ss_select_d = DIG_6;
end
DIG_6: begin
bcd_nibble = bcd[27:24];
ss_select_d = DIG_7;
end
DIG_7: begin
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
default: begin
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
endcase
end
always @(posedge clk)
ss_select_q <= ss_select_d;
endmodule | module ss_mux
(
input clk,
input [31:0] bcd,
input [7:0] dots,
output [7:0] ss_value,
output [7:0] ss_select
); |
localparam DIG_0 = 8'b00000001;
localparam DIG_1 = 8'b00000010;
localparam DIG_2 = 8'b00000100;
localparam DIG_3 = 8'b00001000;
localparam DIG_4 = 8'b00010000;
localparam DIG_5 = 8'b00100000;
localparam DIG_6 = 8'b01000000;
localparam DIG_7 = 8'b10000000;
reg [7:0] ss_select_q;
reg [7:0] ss_select_d;
wire dot_enable;
assign dot_enable = |(ss_select_q & dots);
reg [3:0] bcd_nibble;
wire [6:0] ss_digits;
bcd_to_ss to_ss (
.bcd_in(bcd_nibble),
.out(ss_digits)
);
assign ss_value = {~dot_enable, ss_digits};
assign ss_select = ~ss_select_q;
always @(*) begin
case (ss_select_q)
DIG_0: begin
bcd_nibble = bcd[3:0];
ss_select_d = DIG_1;
end
DIG_1: begin
bcd_nibble = bcd[7:4];
ss_select_d = DIG_2;
end
DIG_2: begin
bcd_nibble = bcd[11:8];
ss_select_d = DIG_3;
end
DIG_3: begin
bcd_nibble = bcd[15:12];
ss_select_d = DIG_4;
end
DIG_4: begin
bcd_nibble = bcd[19:16];
ss_select_d = DIG_5;
end
DIG_5: begin
bcd_nibble = bcd[23:20];
ss_select_d = DIG_6;
end
DIG_6: begin
bcd_nibble = bcd[27:24];
ss_select_d = DIG_7;
end
DIG_7: begin
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
default: begin
bcd_nibble = bcd[31:28];
ss_select_d = DIG_0;
end
endcase
end
always @(posedge clk)
ss_select_q <= ss_select_d;
endmodule | 0 |
3,437 | data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v | 104,660,645 | top_level.v | v | 163 | 80 | [] | [] | [] | null | line:66: before: "=" | null | 1: b"%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:104: Cannot find file containing module: 'detector_secuencia'\n detector_secuencia det_inst (\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/detector_secuencia\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/detector_secuencia.v\n data/full_repos/permissive/104660645/sequence_detector/src/hdl,data/full_repos/permissive/104660645/detector_secuencia.sv\n detector_secuencia\n detector_secuencia.v\n detector_secuencia.sv\n obj_dir/detector_secuencia\n obj_dir/detector_secuencia.v\n obj_dir/detector_secuencia.sv\n%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:114: Cannot find file containing module: 'unsigned_to_bcd'\n unsigned_to_bcd u32_to_bcd_inst (\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:123: Cannot find file containing module: 'clk_divider'\n clk_divider #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:132: Cannot find file containing module: 'ss_mux'\n ss_mux ss_mux_inst (\n ^~~~~~\n%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:141: Cannot find file containing module: 'pb_debouncer'\n pb_debouncer #(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/104660645/sequence_detector/src/hdl/top_level.v:152: Cannot find file containing module: 'pb_debouncer'\n pb_debouncer #(\n ^~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 1,145 | module | module top_level
(
input clk_100M,
input reset_n,
input [1:0] button,
output [7:0] ss_select,
output [7:0] ss_value,
output detected,
output [2:0] leds
);
reg [1:0] reset_sr;
wire reset = reset_sr[1];
always @(posedge clk_100M)
reset_sr <= {reset_sr[0], ~reset_n};
wire clk_ss;
wire [31:0] bcd;
wire det_out;
wire [1:0] button_posedge;
reg det_tick;
reg det_in;
always @(*) begin
case (button_posedge)
'b01: begin
det_in = 1'b0;
det_tick = 1'b1;
end
'b10: begin
det_in = 1'b1;
det_tick = 1'b1;
end
default: begin
det_in = 1'b0;
det_tick = 1'b0;
end
endcase
end
localparam C_WAIT = 'b001;
localparam C_ADD1 = 'b010;
localparam C_HOLD = 'b100;
reg [2:0] counter_state, counter_state_next;
reg [31:0] counter, counter_next = 'd0;
always @(*) begin
counter_next = counter;
counter_state_next = counter_state;
case (counter_state)
C_WAIT:
if (det_out == 1'b1)
counter_state_next = C_ADD1;
C_ADD1: begin
counter_next = counter + 'd1;
counter_state_next = C_HOLD;
end
C_HOLD:
if (det_out == 1'b0)
counter_state_next = C_WAIT;
default:
counter_state_next = C_WAIT;
endcase
end
always @(posedge clk_100M) begin
if (reset) begin
counter <= 'd0;
counter_state <= C_WAIT;
end else begin
counter <= counter_next;
counter_state <= counter_state_next;
end
end
assign detected = det_out;
detector_secuencia det_inst (
.clk(clk_100M),
.reset(reset),
.in(det_in),
.tick(det_tick),
.current_state(leds),
.out(det_out)
);
unsigned_to_bcd u32_to_bcd_inst (
.clk(clk_100M),
.trigger(1'b1),
.in(counter),
.idle(),
.bcd(bcd)
);
clk_divider #(
.O_CLK_FREQ(480)
) clk_div_ss_display (
.clk_in(clk_100M),
.reset(1'b0),
.clk_out(clk_ss)
);
ss_mux ss_mux_inst (
.clk(clk_ss),
.bcd(bcd),
.dots(8'h00),
.ss_value(ss_value),
.ss_select(ss_select)
);
pb_debouncer #(
.COUNTER_WIDTH(20)
) pb_deb0 (
.clk(clk_100M),
.rst(reset),
.pb(button[0]),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_posedge[0])
);
pb_debouncer #(
.COUNTER_WIDTH(20)
) pb_deb1 (
.clk(clk_100M),
.rst(reset),
.pb(button[1]),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_posedge[1])
);
endmodule | module top_level
(
input clk_100M,
input reset_n,
input [1:0] button,
output [7:0] ss_select,
output [7:0] ss_value,
output detected,
output [2:0] leds
); |
reg [1:0] reset_sr;
wire reset = reset_sr[1];
always @(posedge clk_100M)
reset_sr <= {reset_sr[0], ~reset_n};
wire clk_ss;
wire [31:0] bcd;
wire det_out;
wire [1:0] button_posedge;
reg det_tick;
reg det_in;
always @(*) begin
case (button_posedge)
'b01: begin
det_in = 1'b0;
det_tick = 1'b1;
end
'b10: begin
det_in = 1'b1;
det_tick = 1'b1;
end
default: begin
det_in = 1'b0;
det_tick = 1'b0;
end
endcase
end
localparam C_WAIT = 'b001;
localparam C_ADD1 = 'b010;
localparam C_HOLD = 'b100;
reg [2:0] counter_state, counter_state_next;
reg [31:0] counter, counter_next = 'd0;
always @(*) begin
counter_next = counter;
counter_state_next = counter_state;
case (counter_state)
C_WAIT:
if (det_out == 1'b1)
counter_state_next = C_ADD1;
C_ADD1: begin
counter_next = counter + 'd1;
counter_state_next = C_HOLD;
end
C_HOLD:
if (det_out == 1'b0)
counter_state_next = C_WAIT;
default:
counter_state_next = C_WAIT;
endcase
end
always @(posedge clk_100M) begin
if (reset) begin
counter <= 'd0;
counter_state <= C_WAIT;
end else begin
counter <= counter_next;
counter_state <= counter_state_next;
end
end
assign detected = det_out;
detector_secuencia det_inst (
.clk(clk_100M),
.reset(reset),
.in(det_in),
.tick(det_tick),
.current_state(leds),
.out(det_out)
);
unsigned_to_bcd u32_to_bcd_inst (
.clk(clk_100M),
.trigger(1'b1),
.in(counter),
.idle(),
.bcd(bcd)
);
clk_divider #(
.O_CLK_FREQ(480)
) clk_div_ss_display (
.clk_in(clk_100M),
.reset(1'b0),
.clk_out(clk_ss)
);
ss_mux ss_mux_inst (
.clk(clk_ss),
.bcd(bcd),
.dots(8'h00),
.ss_value(ss_value),
.ss_select(ss_select)
);
pb_debouncer #(
.COUNTER_WIDTH(20)
) pb_deb0 (
.clk(clk_100M),
.rst(reset),
.pb(button[0]),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_posedge[0])
);
pb_debouncer #(
.COUNTER_WIDTH(20)
) pb_deb1 (
.clk(clk_100M),
.rst(reset),
.pb(button[1]),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_posedge[1])
);
endmodule | 0 |
3,438 | data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v | 104,660,645 | semaforo_testbench.v | v | 49 | 83 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n always #25 clock=~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #40 TB = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n #60 reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n #38 TA = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n #206 TB = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n #302 TA = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n #40 TB = 1\'b1;\n ^\n%Error: data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new/semaforo_testbench.v:17: Cannot find file containing module: \'semaforo_FSM\'\n semaforo_FSM DUT(\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM\n data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM.v\n data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sim_1/new,data/full_repos/permissive/104660645/semaforo_FSM.sv\n semaforo_FSM\n semaforo_FSM.v\n semaforo_FSM.sv\n obj_dir/semaforo_FSM\n obj_dir/semaforo_FSM.v\n obj_dir/semaforo_FSM.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,147 | module | module testbench();
reg clock;
reg reset;
reg TA, TB;
wire [1:0] LA, LB;
semaforo_FSM DUT(
.clock (clock),
.reset (reset),
.TA (TA),
.TB (TB),
.LA (LA),
.LB (LB)
);
always #25 clock=~clock;
initial begin
clock = 1'b0;
reset = 1'b0;
TA = 1'b1;
TB = 1'b0;
#40 TB = 1'b1;
#60 reset = 1'b1;
#10 reset = 1'b0;
#38 TA = 1'b0;
#206 TB = 1'b0;
#302 TA = 1'b1;
#40 TB = 1'b1;
end
endmodule | module testbench(); |
reg clock;
reg reset;
reg TA, TB;
wire [1:0] LA, LB;
semaforo_FSM DUT(
.clock (clock),
.reset (reset),
.TA (TA),
.TB (TB),
.LA (LA),
.LB (LB)
);
always #25 clock=~clock;
initial begin
clock = 1'b0;
reset = 1'b0;
TA = 1'b1;
TB = 1'b0;
#40 TB = 1'b1;
#60 reset = 1'b1;
#10 reset = 1'b0;
#38 TA = 1'b0;
#206 TB = 1'b0;
#302 TA = 1'b1;
#40 TB = 1'b1;
end
endmodule | 0 |
3,439 | data/full_repos/permissive/104660645/TrafficLight_FSM_example/semaforo_FSM.srcs/sources_1/new/semaforo_FSM.sv | 104,660,645 | semaforo_FSM.sv | sv | 60 | 88 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/faccfd9c-6e34-44a8-b3f6-e433ae4ee5b0.xml | null | 1,148 | module | module semaforo_FSM(
input logic clock,
input logic reset, TA, TB,
output logic [1:0] LA, LB
);
enum logic[3:0] {STATE_0, STATE_1, STATE_2, STATE_3} state, next_state;
localparam GREEN = 2'b00;
localparam YELLOW = 2'b01;
localparam RED = 2'b10;
always_comb begin
next_state = state;
LA = RED;
LB = RED;
case (state)
STATE_0: begin
LA = GREEN;
if(TA == 1'b0) begin
next_state = STATE_1;
end
end
STATE_1: begin
LA = YELLOW;
next_state = STATE_2;
end
STATE_2: begin
LB = GREEN;
if(TB == 1'b0) begin
next_state = STATE_3;
end
end
STATE_3: begin
LB = YELLOW;
next_state = STATE_0;
end
endcase
end
always_ff@(posedge clock)
if(reset)
state <= STATE_0;
else
state <= next_state;
endmodule | module semaforo_FSM(
input logic clock,
input logic reset, TA, TB,
output logic [1:0] LA, LB
); |
enum logic[3:0] {STATE_0, STATE_1, STATE_2, STATE_3} state, next_state;
localparam GREEN = 2'b00;
localparam YELLOW = 2'b01;
localparam RED = 2'b10;
always_comb begin
next_state = state;
LA = RED;
LB = RED;
case (state)
STATE_0: begin
LA = GREEN;
if(TA == 1'b0) begin
next_state = STATE_1;
end
end
STATE_1: begin
LA = YELLOW;
next_state = STATE_2;
end
STATE_2: begin
LB = GREEN;
if(TB == 1'b0) begin
next_state = STATE_3;
end
end
STATE_3: begin
LB = YELLOW;
next_state = STATE_0;
end
endcase
end
always_ff@(posedge clock)
if(reset)
state <= STATE_0;
else
state <= next_state;
endmodule | 0 |
3,440 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/clk_divider.v | 104,660,645 | clk_divider.v | v | 56 | 86 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xe1 in position 188: invalid continuation byte | data/verilator_xmls/042a3f43-38ee-47f8-8326-f4c98c39ea81.xml | null | 1,150 | module | module clk_divider
#(
parameter O_CLK_FREQ = 1
)(
input clk_in,
input reset,
output reg clk_out
);
localparam COUNTER_MAX = 'd100_000_000/(2 * O_CLK_FREQ) - 1;
reg [26:0] counter = 'd0;
always @(posedge clk_in) begin
if (reset == 1'b1) begin
counter <= 'd0;
clk_out <= 0;
end else if (counter == COUNTER_MAX) begin
counter <= 'd0;
clk_out <= ~clk_out;
end else begin
counter <= counter + 'd1;
clk_out <= clk_out;
end
end
endmodule | module clk_divider
#(
parameter O_CLK_FREQ = 1
)(
input clk_in,
input reset,
output reg clk_out
); |
localparam COUNTER_MAX = 'd100_000_000/(2 * O_CLK_FREQ) - 1;
reg [26:0] counter = 'd0;
always @(posedge clk_in) begin
if (reset == 1'b1) begin
counter <= 'd0;
clk_out <= 0;
end else if (counter == COUNTER_MAX) begin
counter <= 'd0;
clk_out <= ~clk_out;
end else begin
counter <= counter + 'd1;
clk_out <= clk_out;
end
end
endmodule | 0 |
3,441 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/master_endpoint_top.v | 104,660,645 | master_endpoint_top.v | v | 128 | 85 | [] | [] | [] | null | line:133: before: "$" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/master_endpoint_top.v:38: Signal definition not found, creating implicitly: \'tx_busy\'\n assign uart_tx_busy = tx_busy;\n ^~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/master_endpoint_top.v:93: Signal definition not found, creating implicitly: \'rx_ready\'\n if (rx_ready)\n ^~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/master_endpoint_top.v:36: Assigning to input/const variable: \'uart_rx\'\n assign uart_rx = uart_rx;\n ^~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,152 | module | module master_endpoint_top
(
input clk_100M,
input reset_n,
input uart_rx,
output uart_tx,
output uart_tx_busy,
output uart_tx_usb,
input button_c,
input [15:0] switches,
output [1:0] leds,
output [7:0] ss_value,
output [7:0] ss_select
);
wire [7:0] tx_data;
wire [7:0] rx_data;
reg [15:0] result16;
wire [31:0] bcd;
reg [1:0] reset_sr;
wire reset = reset_sr[1];
always @(posedge clk_100M)
reset_sr <= {reset_sr[0], ~reset_n};
assign uart_tx_usb = uart_tx;
assign uart_rx = uart_rx;
assign uart_tx = uart_tx;
assign uart_tx_busy = tx_busy;
pb_debouncer #(
.COUNTER_WIDTH(16)
) pb_deb0 (
.clk(clk_100M),
.rst(reset),
.pb(button_c),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_c_posedge)
);
UART_tx_control_wrapper
#( .INTER_BYTE_DELAY (100000),
.WAIT_FOR_REGISTER_DELAY (100)
) UART_control_inst (
.clock(clk_100M),
.reset(reset),
.PB(button_c_posedge),
.SW(switches),
.tx_data(tx_data),
.tx_start(tx_start),
.stateID (leds[1:0])
);
uart_basic #(
.CLK_FREQUENCY(100000000),
.BAUD_RATE(115200)
) uart_basic_inst (
.clk(clk_100M),
.reset(reset),
.rx(uart_rx),
.rx_data(rx_data),
.rx_ready(rx_ready),
.tx(uart_tx),
.tx_start(tx_start),
.tx_data(tx_data),
.tx_busy(tx_busy)
);
always @(posedge clk_100M) begin
if(reset)
result16 <= 16'd0;
else
if (rx_ready)
result16 <= {rx_data, result16[15:8]};
end
unsigned_to_bcd u32_to_bcd_inst (
.clk(clk_100M),
.trigger(1'b1),
.in({16'd0, result16}),
.idle(),
.bcd(bcd)
);
wire clk_ss;
clk_divider #(.O_CLK_FREQ(480)
) clk_div_ss_display (
.clk_in(clk_100M),
.reset(1'b0),
.clk_out(clk_ss)
);
display_mux display_mux_inst (
.clk(clk_ss),
.clk_enable(1'b1),
.bcd(bcd),
.dots(1'b0),
.is_negative(1'b0),
.turn_off(1'b0),
.ss_value(ss_value),
.ss_select(ss_select)
);
endmodule | module master_endpoint_top
(
input clk_100M,
input reset_n,
input uart_rx,
output uart_tx,
output uart_tx_busy,
output uart_tx_usb,
input button_c,
input [15:0] switches,
output [1:0] leds,
output [7:0] ss_value,
output [7:0] ss_select
); |
wire [7:0] tx_data;
wire [7:0] rx_data;
reg [15:0] result16;
wire [31:0] bcd;
reg [1:0] reset_sr;
wire reset = reset_sr[1];
always @(posedge clk_100M)
reset_sr <= {reset_sr[0], ~reset_n};
assign uart_tx_usb = uart_tx;
assign uart_rx = uart_rx;
assign uart_tx = uart_tx;
assign uart_tx_busy = tx_busy;
pb_debouncer #(
.COUNTER_WIDTH(16)
) pb_deb0 (
.clk(clk_100M),
.rst(reset),
.pb(button_c),
.pb_state(),
.pb_negedge(),
.pb_posedge(button_c_posedge)
);
UART_tx_control_wrapper
#( .INTER_BYTE_DELAY (100000),
.WAIT_FOR_REGISTER_DELAY (100)
) UART_control_inst (
.clock(clk_100M),
.reset(reset),
.PB(button_c_posedge),
.SW(switches),
.tx_data(tx_data),
.tx_start(tx_start),
.stateID (leds[1:0])
);
uart_basic #(
.CLK_FREQUENCY(100000000),
.BAUD_RATE(115200)
) uart_basic_inst (
.clk(clk_100M),
.reset(reset),
.rx(uart_rx),
.rx_data(rx_data),
.rx_ready(rx_ready),
.tx(uart_tx),
.tx_start(tx_start),
.tx_data(tx_data),
.tx_busy(tx_busy)
);
always @(posedge clk_100M) begin
if(reset)
result16 <= 16'd0;
else
if (rx_ready)
result16 <= {rx_data, result16[15:8]};
end
unsigned_to_bcd u32_to_bcd_inst (
.clk(clk_100M),
.trigger(1'b1),
.in({16'd0, result16}),
.idle(),
.bcd(bcd)
);
wire clk_ss;
clk_divider #(.O_CLK_FREQ(480)
) clk_div_ss_display (
.clk_in(clk_100M),
.reset(1'b0),
.clk_out(clk_ss)
);
display_mux display_mux_inst (
.clk(clk_ss),
.clk_enable(1'b1),
.bcd(bcd),
.dots(1'b0),
.is_negative(1'b0),
.turn_off(1'b0),
.ss_value(ss_value),
.ss_select(ss_select)
);
endmodule | 0 |
3,442 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/TX_control.v | 104,660,645 | TX_control.v | v | 98 | 125 | [] | [] | [] | null | line:291: before: "$" | data/verilator_xmls/bd0f3054-2a04-454a-be7b-54c30a8a1201.xml | null | 1,154 | module | module TX_control
#( parameter INTER_BYTE_DELAY = 1000000,
parameter WAIT_FOR_REGISTER_DELAY = 100
)(
input clock,
input reset,
input PB,
input send16,
input [15:0] dataIn16,
output reg [7:0] tx_data,
output reg tx_start,
output reg busy
);
reg [2:0] next_state, state;
reg [15:0] tx_data16;
reg [31:0] hold_state_timer;
localparam IDLE = 3'd0;
localparam REGISTER_DATAIN16 = 3'd1;
localparam SEND_BYTE_0 = 3'd2;
localparam DELAY_BYTE_0 = 3'd3;
localparam SEND_BYTE_1 = 3'd4;
localparam DELAY_BYTE_1 = 3'd5;
always@(*) begin
next_state = state;
busy = 1'b1;
tx_start = 1'b0;
tx_data = tx_data16[7:0];
case (state)
IDLE: begin
busy = 1'b0;
if(PB) begin
next_state=REGISTER_DATAIN16;
end
end
REGISTER_DATAIN16: begin
if(hold_state_timer >= WAIT_FOR_REGISTER_DELAY)
next_state=SEND_BYTE_0;
end
SEND_BYTE_0: begin
next_state = DELAY_BYTE_0;
tx_start = 1'b1;
end
DELAY_BYTE_0: begin
if(hold_state_timer >= INTER_BYTE_DELAY) begin
if (send16)
next_state = SEND_BYTE_1;
else
next_state = IDLE;
end
end
SEND_BYTE_1: begin
tx_data = tx_data16[15:8];
next_state = DELAY_BYTE_1;
tx_start = 1'b1;
end
DELAY_BYTE_1: begin
if(hold_state_timer >= INTER_BYTE_DELAY)
next_state = IDLE;
end
endcase
end
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
always@ (posedge clock) begin
if(state == REGISTER_DATAIN16)
tx_data16 <= dataIn16;
end
always@(posedge clock) begin
if(state == DELAY_BYTE_0 || state == DELAY_BYTE_1 || state == REGISTER_DATAIN16) begin
hold_state_timer <= hold_state_timer + 1;
end else begin
hold_state_timer <= 0;
end
end
endmodule | module TX_control
#( parameter INTER_BYTE_DELAY = 1000000,
parameter WAIT_FOR_REGISTER_DELAY = 100
)(
input clock,
input reset,
input PB,
input send16,
input [15:0] dataIn16,
output reg [7:0] tx_data,
output reg tx_start,
output reg busy
); |
reg [2:0] next_state, state;
reg [15:0] tx_data16;
reg [31:0] hold_state_timer;
localparam IDLE = 3'd0;
localparam REGISTER_DATAIN16 = 3'd1;
localparam SEND_BYTE_0 = 3'd2;
localparam DELAY_BYTE_0 = 3'd3;
localparam SEND_BYTE_1 = 3'd4;
localparam DELAY_BYTE_1 = 3'd5;
always@(*) begin
next_state = state;
busy = 1'b1;
tx_start = 1'b0;
tx_data = tx_data16[7:0];
case (state)
IDLE: begin
busy = 1'b0;
if(PB) begin
next_state=REGISTER_DATAIN16;
end
end
REGISTER_DATAIN16: begin
if(hold_state_timer >= WAIT_FOR_REGISTER_DELAY)
next_state=SEND_BYTE_0;
end
SEND_BYTE_0: begin
next_state = DELAY_BYTE_0;
tx_start = 1'b1;
end
DELAY_BYTE_0: begin
if(hold_state_timer >= INTER_BYTE_DELAY) begin
if (send16)
next_state = SEND_BYTE_1;
else
next_state = IDLE;
end
end
SEND_BYTE_1: begin
tx_data = tx_data16[15:8];
next_state = DELAY_BYTE_1;
tx_start = 1'b1;
end
DELAY_BYTE_1: begin
if(hold_state_timer >= INTER_BYTE_DELAY)
next_state = IDLE;
end
endcase
end
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
always@ (posedge clock) begin
if(state == REGISTER_DATAIN16)
tx_data16 <= dataIn16;
end
always@(posedge clock) begin
if(state == DELAY_BYTE_0 || state == DELAY_BYTE_1 || state == REGISTER_DATAIN16) begin
hold_state_timer <= hold_state_timer + 1;
end else begin
hold_state_timer <= 0;
end
end
endmodule | 0 |
3,443 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/TX_sequence.v | 104,660,645 | TX_sequence.v | v | 63 | 95 | [] | [] | [] | [(1, 63)] | null | data/verilator_xmls/b9ef31fa-51b7-431a-9661-796aed205ce4.xml | null | 1,155 | module | module TX_sequence
(
input clock,
input reset,
input PB,
output reg send16,
input busy,
output [1:0] stateID
);
reg[1:0] next_state, state;
localparam IDLE = 2'd0;
localparam TX_OPERAND01 = 2'd1;
localparam TX_OPERAND02 = 2'd2;
localparam TX_ALU_CTRL = 2'd3;
assign stateID = state;
always@(*) begin
next_state = state;
send16 = 1'b1;
case (state)
IDLE: begin
if(PB & ~busy) begin
next_state=TX_OPERAND01;
end
end
TX_OPERAND01: begin
if(PB & ~busy) begin
next_state=TX_OPERAND02;
end
end
TX_OPERAND02: begin
if(PB & ~busy) begin
next_state=TX_ALU_CTRL;
end
end
TX_ALU_CTRL: begin
send16 = 1'b0;
if(~busy) begin
next_state=IDLE;
end
end
endcase
end
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
endmodule | module TX_sequence
(
input clock,
input reset,
input PB,
output reg send16,
input busy,
output [1:0] stateID
); |
reg[1:0] next_state, state;
localparam IDLE = 2'd0;
localparam TX_OPERAND01 = 2'd1;
localparam TX_OPERAND02 = 2'd2;
localparam TX_ALU_CTRL = 2'd3;
assign stateID = state;
always@(*) begin
next_state = state;
send16 = 1'b1;
case (state)
IDLE: begin
if(PB & ~busy) begin
next_state=TX_OPERAND01;
end
end
TX_OPERAND01: begin
if(PB & ~busy) begin
next_state=TX_OPERAND02;
end
end
TX_OPERAND02: begin
if(PB & ~busy) begin
next_state=TX_ALU_CTRL;
end
end
TX_ALU_CTRL: begin
send16 = 1'b0;
if(~busy) begin
next_state=IDLE;
end
end
endcase
end
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
endmodule | 0 |
3,444 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v | 104,660,645 | UART_tx_control_wrapper.v | v | 39 | 55 | [] | [] | [] | [(1, 39)] | null | null | 1: b"%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v:14: Cannot find file containing module: 'TX_control'\nTX_control \n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control.v\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new,data/full_repos/permissive/104660645/TX_control.sv\n TX_control\n TX_control.v\n TX_control.sv\n obj_dir/TX_control\n obj_dir/TX_control.v\n obj_dir/TX_control.sv\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/UART_tx_control_wrapper.v:29: Cannot find file containing module: 'TX_sequence'\nTX_sequence TX_sequence_inst0 \n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,156 | module | module UART_tx_control_wrapper
#( parameter INTER_BYTE_DELAY = 1000000,
parameter WAIT_FOR_REGISTER_DELAY = 100
)(
input clock,
input reset,
input PB,
input [15:0] SW,
output [7:0] tx_data,
output tx_start,
output [1:0] stateID
);
TX_control
#( .INTER_BYTE_DELAY (INTER_BYTE_DELAY),
.WAIT_FOR_REGISTER_DELAY (WAIT_FOR_REGISTER_DELAY)
)TX_control_inst0
(
.clock (clock),
.reset (reset),
.PB (PB),
.send16 (send16),
.dataIn16 (SW),
.tx_data (tx_data),
.tx_start (tx_start),
.busy (busy)
);
TX_sequence TX_sequence_inst0
(
.clock (clock),
.reset (reset),
.PB (PB),
.send16 (send16),
.busy (busy),
.stateID(stateID)
);
endmodule | module UART_tx_control_wrapper
#( parameter INTER_BYTE_DELAY = 1000000,
parameter WAIT_FOR_REGISTER_DELAY = 100
)(
input clock,
input reset,
input PB,
input [15:0] SW,
output [7:0] tx_data,
output tx_start,
output [1:0] stateID
); |
TX_control
#( .INTER_BYTE_DELAY (INTER_BYTE_DELAY),
.WAIT_FOR_REGISTER_DELAY (WAIT_FOR_REGISTER_DELAY)
)TX_control_inst0
(
.clock (clock),
.reset (reset),
.PB (PB),
.send16 (send16),
.dataIn16 (SW),
.tx_data (tx_data),
.tx_start (tx_start),
.busy (busy)
);
TX_sequence TX_sequence_inst0
(
.clock (clock),
.reset (reset),
.PB (PB),
.send16 (send16),
.busy (busy),
.stateID(stateID)
);
endmodule | 0 |
3,445 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/unsigned_to_bcd.v | 104,660,645 | unsigned_to_bcd.v | v | 134 | 86 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf3 in position 91: invalid continuation byte | data/verilator_xmls/d79e98fb-1342-488f-8f29-6d9e626b47dd.xml | null | 1,157 | module | module unsigned_to_bcd
(
input clk,
input trigger,
input [31:0] in,
output reg idle,
output reg [31:0] bcd
);
localparam S_IDLE = 'b001;
localparam S_SHIFT = 'b010;
localparam S_ADD3 = 'b100;
reg [2:0] state, state_next;
reg [31:0] shift, shift_next;
reg [31:0] bcd_next;
localparam COUNTER_MAX = 32;
reg [5:0] counter, counter_next;
always @(*) begin
state_next = state;
shift_next = shift;
bcd_next = bcd;
counter_next = counter;
idle = 1'b0;
case (state)
S_IDLE: begin
counter_next = 'd1;
shift_next = 'd0;
idle = 1'b1;
if (trigger) begin
state_next = S_SHIFT;
end
end
S_ADD3: begin
if (shift[31:28] >= 5)
shift_next[31:28] = shift[31:28] + 4'd3;
if (shift[27:24] >= 5)
shift_next[27:24] = shift[27:24] + 4'd3;
if (shift[23:20] >= 5)
shift_next[23:20] = shift[23:20] + 4'd3;
if (shift[19:16] >= 5)
shift_next[19:16] = shift[19:16] + 4'd3;
if (shift[15:12] >= 5)
shift_next[15:12] = shift[15:12] + 4'd3;
if (shift[11:8] >= 5)
shift_next[11:8] = shift[11:8] + 4'd3;
if (shift[7:4] >= 5)
shift_next[7:4] = shift[7:4] + 4'd3;
if (shift[3:0] >= 5)
shift_next[3:0] = shift[3:0] + 4'd3;
state_next = S_SHIFT;
end
S_SHIFT: begin
shift_next = {shift[30:0], in[COUNTER_MAX - counter_next]};
if (counter == COUNTER_MAX) begin
bcd_next = shift_next;
state_next = S_IDLE;
end else
state_next = S_ADD3;
counter_next = counter + 'd1;
end
default: begin
state_next = S_IDLE;
end
endcase
end
always @(posedge clk) begin
state <= state_next;
shift <= shift_next;
bcd <= bcd_next;
counter <= counter_next;
end
endmodule | module unsigned_to_bcd
(
input clk,
input trigger,
input [31:0] in,
output reg idle,
output reg [31:0] bcd
); |
localparam S_IDLE = 'b001;
localparam S_SHIFT = 'b010;
localparam S_ADD3 = 'b100;
reg [2:0] state, state_next;
reg [31:0] shift, shift_next;
reg [31:0] bcd_next;
localparam COUNTER_MAX = 32;
reg [5:0] counter, counter_next;
always @(*) begin
state_next = state;
shift_next = shift;
bcd_next = bcd;
counter_next = counter;
idle = 1'b0;
case (state)
S_IDLE: begin
counter_next = 'd1;
shift_next = 'd0;
idle = 1'b1;
if (trigger) begin
state_next = S_SHIFT;
end
end
S_ADD3: begin
if (shift[31:28] >= 5)
shift_next[31:28] = shift[31:28] + 4'd3;
if (shift[27:24] >= 5)
shift_next[27:24] = shift[27:24] + 4'd3;
if (shift[23:20] >= 5)
shift_next[23:20] = shift[23:20] + 4'd3;
if (shift[19:16] >= 5)
shift_next[19:16] = shift[19:16] + 4'd3;
if (shift[15:12] >= 5)
shift_next[15:12] = shift[15:12] + 4'd3;
if (shift[11:8] >= 5)
shift_next[11:8] = shift[11:8] + 4'd3;
if (shift[7:4] >= 5)
shift_next[7:4] = shift[7:4] + 4'd3;
if (shift[3:0] >= 5)
shift_next[3:0] = shift[3:0] + 4'd3;
state_next = S_SHIFT;
end
S_SHIFT: begin
shift_next = {shift[30:0], in[COUNTER_MAX - counter_next]};
if (counter == COUNTER_MAX) begin
bcd_next = shift_next;
state_next = S_IDLE;
end else
state_next = S_ADD3;
counter_next = counter + 'd1;
end
default: begin
state_next = S_IDLE;
end
endcase
end
always @(posedge clk) begin
state <= state_next;
shift <= shift_next;
bcd <= bcd_next;
counter <= counter_next;
end
endmodule | 0 |
3,446 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/data_sync.v | 104,660,645 | data_sync.v | v | 56 | 73 | [] | [] | [] | null | line:26: before: "," | data/verilator_xmls/b4af11c2-3bd3-4f8f-a1b0-9fc79a2a7c30.xml | null | 1,158 | module | module data_sync
(
input clk,
input in,
output reg stable_out
);
reg [1:0] in_sync_sr;
wire in_sync = in_sync_sr[0];
always @(posedge clk)
in_sync_sr <= {in, in_sync_sr[1]};
reg [1:0] sync_counter = 'b11, sync_counter_next;
reg stable_out_next;
always @(*) begin
if (in_sync == 1'b1 && sync_counter != 2'b11)
sync_counter_next = sync_counter + 'd1;
else if (in_sync == 1'b0 && sync_counter != 2'b00)
sync_counter_next = sync_counter - 'd1;
else
sync_counter_next = sync_counter;
end
always @(*) begin
case (sync_counter)
2'b00:
stable_out_next = 1'b0;
2'b11:
stable_out_next = 1'b1;
default:
stable_out_next = stable_out;
endcase
end
always @(posedge clk) begin
stable_out <= stable_out_next;
sync_counter <= sync_counter_next;
end
endmodule | module data_sync
(
input clk,
input in,
output reg stable_out
); |
reg [1:0] in_sync_sr;
wire in_sync = in_sync_sr[0];
always @(posedge clk)
in_sync_sr <= {in, in_sync_sr[1]};
reg [1:0] sync_counter = 'b11, sync_counter_next;
reg stable_out_next;
always @(*) begin
if (in_sync == 1'b1 && sync_counter != 2'b11)
sync_counter_next = sync_counter + 'd1;
else if (in_sync == 1'b0 && sync_counter != 2'b00)
sync_counter_next = sync_counter - 'd1;
else
sync_counter_next = sync_counter;
end
always @(*) begin
case (sync_counter)
2'b00:
stable_out_next = 1'b0;
2'b11:
stable_out_next = 1'b1;
default:
stable_out_next = stable_out;
endcase
end
always @(posedge clk) begin
stable_out <= stable_out_next;
sync_counter <= sync_counter_next;
end
endmodule | 0 |
3,447 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v | 104,660,645 | uart_basic.v | v | 78 | 53 | [] | [] | [] | [(10, 77)] | null | null | 1: b"%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:32: Cannot find file containing module: 'uart_baud_tick_gen'\n uart_baud_tick_gen #(\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen.v\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/uart_baud_tick_gen.sv\n uart_baud_tick_gen\n uart_baud_tick_gen.v\n uart_baud_tick_gen.sv\n obj_dir/uart_baud_tick_gen\n obj_dir/uart_baud_tick_gen.v\n obj_dir/uart_baud_tick_gen.sv\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:42: Cannot find file containing module: 'uart_rx'\n uart_rx uart_rx_blk (\n ^~~~~~~\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:57: Cannot find file containing module: 'uart_baud_tick_gen'\n uart_baud_tick_gen #(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_basic.v:67: Cannot find file containing module: 'uart_tx'\n uart_tx uart_tx_blk (\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,159 | module | module uart_basic
#(
parameter CLK_FREQUENCY = 100000000,
parameter BAUD_RATE = 115200
)(
input clk,
input reset,
input rx,
output [7:0] rx_data,
output reg rx_ready,
output tx,
input tx_start,
input [7:0] tx_data,
output tx_busy
);
wire baud8_tick;
wire baud_tick;
reg rx_ready_sync;
wire rx_ready_pre;
uart_baud_tick_gen #(
.CLK_FREQUENCY(CLK_FREQUENCY),
.BAUD_RATE(BAUD_RATE),
.OVERSAMPLING(8)
) baud8_tick_blk (
.clk(clk),
.enable(1'b1),
.tick(baud8_tick)
);
uart_rx uart_rx_blk (
.clk(clk),
.reset(reset),
.baud8_tick(baud8_tick),
.rx(rx),
.rx_data(rx_data),
.rx_ready(rx_ready_pre)
);
always @(posedge clk) begin
rx_ready_sync <= rx_ready_pre;
rx_ready <= ~rx_ready_sync & rx_ready_pre;
end
uart_baud_tick_gen #(
.CLK_FREQUENCY(CLK_FREQUENCY),
.BAUD_RATE(BAUD_RATE),
.OVERSAMPLING(1)
) baud_tick_blk (
.clk(clk),
.enable(tx_busy),
.tick(baud_tick)
);
uart_tx uart_tx_blk (
.clk(clk),
.reset(reset),
.baud_tick(baud_tick),
.tx(tx),
.tx_start(tx_start),
.tx_data(tx_data),
.tx_busy(tx_busy)
);
endmodule | module uart_basic
#(
parameter CLK_FREQUENCY = 100000000,
parameter BAUD_RATE = 115200
)(
input clk,
input reset,
input rx,
output [7:0] rx_data,
output reg rx_ready,
output tx,
input tx_start,
input [7:0] tx_data,
output tx_busy
); |
wire baud8_tick;
wire baud_tick;
reg rx_ready_sync;
wire rx_ready_pre;
uart_baud_tick_gen #(
.CLK_FREQUENCY(CLK_FREQUENCY),
.BAUD_RATE(BAUD_RATE),
.OVERSAMPLING(8)
) baud8_tick_blk (
.clk(clk),
.enable(1'b1),
.tick(baud8_tick)
);
uart_rx uart_rx_blk (
.clk(clk),
.reset(reset),
.baud8_tick(baud8_tick),
.rx(rx),
.rx_data(rx_data),
.rx_ready(rx_ready_pre)
);
always @(posedge clk) begin
rx_ready_sync <= rx_ready_pre;
rx_ready <= ~rx_ready_sync & rx_ready_pre;
end
uart_baud_tick_gen #(
.CLK_FREQUENCY(CLK_FREQUENCY),
.BAUD_RATE(BAUD_RATE),
.OVERSAMPLING(1)
) baud_tick_blk (
.clk(clk),
.enable(tx_busy),
.tick(baud_tick)
);
uart_tx uart_tx_blk (
.clk(clk),
.reset(reset),
.baud_tick(baud_tick),
.tx(tx),
.tx_start(tx_start),
.tx_data(tx_data),
.tx_busy(tx_busy)
);
endmodule | 0 |
3,448 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_baud_tick_gen.v | 104,660,645 | uart_baud_tick_gen.v | v | 49 | 81 | [] | [] | [] | null | line:23: before: "integer" | data/verilator_xmls/d109f985-b25a-496d-8bd8-2cb9e2c275a2.xml | null | 1,160 | module | module uart_baud_tick_gen
#(
parameter CLK_FREQUENCY = 25000000,
parameter BAUD_RATE = 115200,
parameter OVERSAMPLING = 1
)(
input clk,
input enable,
output tick
);
function integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction
localparam ACC_WIDTH = clog2(CLK_FREQUENCY / BAUD_RATE) + 8;
localparam SHIFT_LIMITER = clog2(BAUD_RATE * OVERSAMPLING >> (31 - ACC_WIDTH));
localparam INCREMENT =
((BAUD_RATE * OVERSAMPLING << (ACC_WIDTH - SHIFT_LIMITER)) +
(CLK_FREQUENCY >> (SHIFT_LIMITER + 1))) / (CLK_FREQUENCY >> SHIFT_LIMITER);
(* keep = "true" *)
reg [ACC_WIDTH:0] acc = 0;
always @(posedge clk)
if (enable)
acc <= acc[ACC_WIDTH-1:0] + INCREMENT[ACC_WIDTH:0];
else
acc <= INCREMENT[ACC_WIDTH:0];
assign tick = acc[ACC_WIDTH];
endmodule | module uart_baud_tick_gen
#(
parameter CLK_FREQUENCY = 25000000,
parameter BAUD_RATE = 115200,
parameter OVERSAMPLING = 1
)(
input clk,
input enable,
output tick
); |
function integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction
localparam ACC_WIDTH = clog2(CLK_FREQUENCY / BAUD_RATE) + 8;
localparam SHIFT_LIMITER = clog2(BAUD_RATE * OVERSAMPLING >> (31 - ACC_WIDTH));
localparam INCREMENT =
((BAUD_RATE * OVERSAMPLING << (ACC_WIDTH - SHIFT_LIMITER)) +
(CLK_FREQUENCY >> (SHIFT_LIMITER + 1))) / (CLK_FREQUENCY >> SHIFT_LIMITER);
(* keep = "true" *)
reg [ACC_WIDTH:0] acc = 0;
always @(posedge clk)
if (enable)
acc <= acc[ACC_WIDTH-1:0] + INCREMENT[ACC_WIDTH:0];
else
acc <= INCREMENT[ACC_WIDTH:0];
assign tick = acc[ACC_WIDTH];
endmodule | 0 |
3,449 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_baud_tick_gen.v | 104,660,645 | uart_baud_tick_gen.v | v | 49 | 81 | [] | [] | [] | null | line:23: before: "integer" | data/verilator_xmls/d109f985-b25a-496d-8bd8-2cb9e2c275a2.xml | null | 1,160 | function | function integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction | function integer clog2; |
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
endfunction | 0 |
3,450 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_rx.v | 104,660,645 | uart_rx.v | v | 109 | 56 | [] | [] | [] | null | line:35: before: "," | null | 1: b"%Error: data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_rx.v:28: Cannot find file containing module: 'data_sync'\n data_sync rx_sync_inst (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/data_sync\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/data_sync.v\n data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart,data/full_repos/permissive/104660645/data_sync.sv\n data_sync\n data_sync.v\n data_sync.sv\n obj_dir/data_sync\n obj_dir/data_sync.v\n obj_dir/data_sync.sv\n%Error: Exiting due to 1 error(s)\n" | 1,161 | module | module uart_rx
(
input clk,
input reset,
input baud8_tick,
input rx,
output reg [7:0] rx_data,
output reg rx_ready
);
localparam RX_IDLE = 'b000;
localparam RX_START = 'b001;
localparam RX_RECV = 'b010;
localparam RX_STOP = 'b011;
localparam RX_READY = 'b100;
wire rx_bit;
data_sync rx_sync_inst (
.clk(clk),
.in(rx),
.stable_out(rx_bit)
);
reg [2:0] spacing_counter = 'd0, spacing_counter_next;
wire next_bit;
assign next_bit = (spacing_counter == 'd4);
reg [2:0] state = RX_IDLE, state_next;
reg [2:0] bit_counter = 'd0, bit_counter_next;
reg [7:0] rx_data_next;
always @(*) begin
state_next = state;
case (state)
RX_IDLE:
if (rx_bit == 1'b0)
state_next = RX_START;
RX_START: begin
if (next_bit) begin
if (rx_bit == 1'b0)
state_next = RX_RECV;
else
state_next = RX_IDLE;
end
end
RX_RECV:
if (next_bit && bit_counter == 'd7)
state_next = RX_STOP;
RX_STOP:
if (next_bit)
state_next = RX_READY;
RX_READY:
state_next = RX_IDLE;
default:
state_next = RX_IDLE;
endcase
end
always @(*) begin
bit_counter_next = bit_counter;
spacing_counter_next = spacing_counter + 'd1;
rx_ready = 1'b0;
rx_data_next = rx_data;
case (state)
RX_IDLE: begin
bit_counter_next = 'd0;
spacing_counter_next = 'd0;
end
RX_RECV: begin
if (next_bit) begin
bit_counter_next = bit_counter + 'd1;
rx_data_next = {rx_bit, rx_data[7:1]};
end
end
RX_READY:
rx_ready = 1'b1;
endcase
end
always @(posedge clk) begin
if (reset) begin
spacing_counter <= 'd0;
bit_counter <= 'd0;
state <= RX_IDLE;
rx_data <= 'd0;
end else if (baud8_tick) begin
spacing_counter <= spacing_counter_next;
bit_counter <= bit_counter_next;
state <= state_next;
rx_data <= rx_data_next;
end
end
endmodule | module uart_rx
(
input clk,
input reset,
input baud8_tick,
input rx,
output reg [7:0] rx_data,
output reg rx_ready
); |
localparam RX_IDLE = 'b000;
localparam RX_START = 'b001;
localparam RX_RECV = 'b010;
localparam RX_STOP = 'b011;
localparam RX_READY = 'b100;
wire rx_bit;
data_sync rx_sync_inst (
.clk(clk),
.in(rx),
.stable_out(rx_bit)
);
reg [2:0] spacing_counter = 'd0, spacing_counter_next;
wire next_bit;
assign next_bit = (spacing_counter == 'd4);
reg [2:0] state = RX_IDLE, state_next;
reg [2:0] bit_counter = 'd0, bit_counter_next;
reg [7:0] rx_data_next;
always @(*) begin
state_next = state;
case (state)
RX_IDLE:
if (rx_bit == 1'b0)
state_next = RX_START;
RX_START: begin
if (next_bit) begin
if (rx_bit == 1'b0)
state_next = RX_RECV;
else
state_next = RX_IDLE;
end
end
RX_RECV:
if (next_bit && bit_counter == 'd7)
state_next = RX_STOP;
RX_STOP:
if (next_bit)
state_next = RX_READY;
RX_READY:
state_next = RX_IDLE;
default:
state_next = RX_IDLE;
endcase
end
always @(*) begin
bit_counter_next = bit_counter;
spacing_counter_next = spacing_counter + 'd1;
rx_ready = 1'b0;
rx_data_next = rx_data;
case (state)
RX_IDLE: begin
bit_counter_next = 'd0;
spacing_counter_next = 'd0;
end
RX_RECV: begin
if (next_bit) begin
bit_counter_next = bit_counter + 'd1;
rx_data_next = {rx_bit, rx_data[7:1]};
end
end
RX_READY:
rx_ready = 1'b1;
endcase
end
always @(posedge clk) begin
if (reset) begin
spacing_counter <= 'd0;
bit_counter <= 'd0;
state <= RX_IDLE;
rx_data <= 'd0;
end else if (baud8_tick) begin
spacing_counter <= spacing_counter_next;
bit_counter <= bit_counter_next;
state <= state_next;
rx_data <= rx_data_next;
end
end
endmodule | 0 |
3,451 | data/full_repos/permissive/104660645/UART_Tx_example/Lab5_UART_master_endpoint.srcs/sources_1/new/uart/uart_tx.v | 104,660,645 | uart_tx.v | v | 76 | 55 | [] | [] | [] | null | line:26: before: "," | data/verilator_xmls/d9285e45-e1c9-45e4-bb29-390b1e926f89.xml | null | 1,162 | module | module uart_tx
(
input clk,
input reset,
input baud_tick,
input tx_start,
input [7:0] tx_data,
output reg tx,
output reg tx_busy
);
localparam TX_IDLE = 2'b00;
localparam TX_START = 2'b01;
localparam TX_SEND = 2'b10;
localparam TX_STOP = 2'b11;
reg [1:0] state = TX_IDLE, state_next;
reg [2:0] counter = 3'd0, counter_next;
reg [7:0] tx_data_reg;
always @(posedge clk) begin
if (reset)
tx_data_reg <= 'd0;
else if (state == TX_IDLE && tx_start)
tx_data_reg <= tx_data;
end
always @(*) begin
tx = 1'b1;
tx_busy = 1'b1;
state_next = state;
counter_next = counter;
case (state)
TX_IDLE: begin
tx_busy = 1'b0;
state_next = (tx_start) ? TX_START : TX_IDLE;
end
TX_START: begin
tx = 1'b0;
state_next = (baud_tick) ? TX_SEND : TX_START;
counter_next = 'd0;
end
TX_SEND: begin
tx = tx_data_reg[counter];
if (baud_tick) begin
state_next = (counter == 'd7) ? TX_STOP : TX_SEND;
counter_next = counter + 'd1;
end
end
TX_STOP:
state_next = (baud_tick) ? TX_IDLE : TX_STOP;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= TX_IDLE;
counter <= 'd0;
end else begin
state <= state_next;
counter <= counter_next;
end
end
endmodule | module uart_tx
(
input clk,
input reset,
input baud_tick,
input tx_start,
input [7:0] tx_data,
output reg tx,
output reg tx_busy
); |
localparam TX_IDLE = 2'b00;
localparam TX_START = 2'b01;
localparam TX_SEND = 2'b10;
localparam TX_STOP = 2'b11;
reg [1:0] state = TX_IDLE, state_next;
reg [2:0] counter = 3'd0, counter_next;
reg [7:0] tx_data_reg;
always @(posedge clk) begin
if (reset)
tx_data_reg <= 'd0;
else if (state == TX_IDLE && tx_start)
tx_data_reg <= tx_data;
end
always @(*) begin
tx = 1'b1;
tx_busy = 1'b1;
state_next = state;
counter_next = counter;
case (state)
TX_IDLE: begin
tx_busy = 1'b0;
state_next = (tx_start) ? TX_START : TX_IDLE;
end
TX_START: begin
tx = 1'b0;
state_next = (baud_tick) ? TX_SEND : TX_START;
counter_next = 'd0;
end
TX_SEND: begin
tx = tx_data_reg[counter];
if (baud_tick) begin
state_next = (counter == 'd7) ? TX_STOP : TX_SEND;
counter_next = counter + 'd1;
end
end
TX_STOP:
state_next = (baud_tick) ? TX_IDLE : TX_STOP;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= TX_IDLE;
counter <= 'd0;
end else begin
state <= state_next;
counter <= counter_next;
end
end
endmodule | 0 |
3,452 | data/full_repos/permissive/104667535/verilog/cpu.v | 104,667,535 | cpu.v | v | 1,252 | 140 | [] | [] | [] | [(21, 1251)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104667535/verilog/cpu.v:382: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'PC_inc\' generates 1 bits.\n : ... In instance cpu\n PC <= PC_temp + PC_inc;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104667535/verilog/cpu.v:600: Cannot find file containing module: \'ALU\'\nALU ALU( .clk(clk),\n^~~\n ... Looked in:\n data/full_repos/permissive/104667535/verilog,data/full_repos/permissive/104667535/ALU\n data/full_repos/permissive/104667535/verilog,data/full_repos/permissive/104667535/ALU.v\n data/full_repos/permissive/104667535/verilog,data/full_repos/permissive/104667535/ALU.sv\n ALU\n ALU.v\n ALU.sv\n obj_dir/ALU\n obj_dir/ALU.v\n obj_dir/ALU.sv\n%Warning-WIDTH: data/full_repos/permissive/104667535/verilog/cpu.v:629: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'bx\' generates 1 bits.\n : ... In instance cpu\n ABS1: alu_op = 1\'bx;\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n' | 1,164 | module | module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY );
input clk;
input reset;
output reg [15:0] AB;
input [7:0] DI;
output [7:0] DO;
output WE;
input IRQ;
input NMI;
input RDY;
reg [15:0] PC;
reg [7:0] ABL;
reg [7:0] ABH;
wire [7:0] ADD;
reg [7:0] DIHOLD;
reg DIHOLD_valid;
wire [7:0] DIMUX;
reg [7:0] IRHOLD;
reg IRHOLD_valid;
reg [7:0] AXYS[3:0];
reg C = 0;
reg Z = 0;
reg I = 0;
reg D = 0;
reg V = 0;
reg N = 0;
wire AZ;
wire AV;
wire AN;
wire HC;
reg [7:0] AI;
reg [7:0] BI;
wire [7:0] DI;
wire [7:0] IR;
reg [7:0] DO;
reg WE;
reg CI;
wire CO;
wire [7:0] PCH = PC[15:8];
wire [7:0] PCL = PC[7:0];
reg NMI_edge = 0;
reg [1:0] regsel;
wire [7:0] regfile = AXYS[regsel];
parameter
SEL_A = 2'd0,
SEL_S = 2'd1,
SEL_X = 2'd2,
SEL_Y = 2'd3;
`ifdef SIM
wire [7:0] A = AXYS[SEL_A];
wire [7:0] X = AXYS[SEL_X];
wire [7:0] Y = AXYS[SEL_Y];
wire [7:0] S = AXYS[SEL_S];
`endif
initial begin
AB = 0;
PC = 0;
ABL = 0;
ABH = 0;
DIHOLD = 0;
DIHOLD_valid = 0;
IRHOLD = 0;
IRHOLD_valid = 0;
AXYS[0] = 0;
AXYS[1] = 0;
AXYS[2] = 0;
AXYS[3] = 0;
C = 0;
Z = 0;
I = 0;
D = 0;
V = 0;
N = 0;
AI = 0;
BI = 0;
DO = 0;
WE = 0;
CI = 0;
NMI_edge = 0;
regsel = 0;
end
wire [7:0] P = { N, V, 2'b11, D, I, Z, C };
reg [5:0] state;
reg PC_inc;
reg [15:0] PC_temp;
reg [1:0] src_reg;
reg [1:0] dst_reg;
reg index_y;
reg load_reg;
reg inc;
reg write_back;
reg load_only;
reg store;
reg adc_sbc;
reg compare;
reg shift;
reg rotate;
reg backwards;
reg cond_true;
reg [2:0] cond_code;
reg shift_right;
reg alu_shift_right;
reg [3:0] op;
reg [3:0] alu_op;
reg adc_bcd;
reg adj_bcd;
reg bit_ins;
reg plp;
reg php;
reg clc;
reg sec;
reg cld;
reg sed;
reg cli;
reg sei;
reg clv;
reg brk;
reg res;
parameter
OP_OR = 4'b1100,
OP_AND = 4'b1101,
OP_EOR = 4'b1110,
OP_ADD = 4'b0011,
OP_SUB = 4'b0111,
OP_ROL = 4'b1011,
OP_A = 4'b1111;
parameter
ABS0 = 6'd0,
ABS1 = 6'd1,
ABSX0 = 6'd2,
ABSX1 = 6'd3,
ABSX2 = 6'd4,
BRA0 = 6'd5,
BRA1 = 6'd6,
BRA2 = 6'd7,
BRK0 = 6'd8,
BRK1 = 6'd9,
BRK2 = 6'd10,
BRK3 = 6'd11,
DECODE = 6'd12,
FETCH = 6'd13,
INDX0 = 6'd14,
INDX1 = 6'd15,
INDX2 = 6'd16,
INDX3 = 6'd17,
INDY0 = 6'd18,
INDY1 = 6'd19,
INDY2 = 6'd20,
INDY3 = 6'd21,
JMP0 = 6'd22,
JMP1 = 6'd23,
JMPI0 = 6'd24,
JMPI1 = 6'd25,
JSR0 = 6'd26,
JSR1 = 6'd27,
JSR2 = 6'd28,
JSR3 = 6'd29,
PULL0 = 6'd30,
PULL1 = 6'd31,
PULL2 = 6'd32,
PUSH0 = 6'd33,
PUSH1 = 6'd34,
READ = 6'd35,
REG = 6'd36,
RTI0 = 6'd37,
RTI1 = 6'd38,
RTI2 = 6'd39,
RTI3 = 6'd40,
RTI4 = 6'd41,
RTS0 = 6'd42,
RTS1 = 6'd43,
RTS2 = 6'd44,
RTS3 = 6'd45,
WRITE = 6'd46,
ZP0 = 6'd47,
ZPX0 = 6'd48,
ZPX1 = 6'd49;
`ifdef SIM
reg [8*6-1:0] statename;
always @*
case( state )
DECODE: statename = "DECODE";
REG: statename = "REG";
ZP0: statename = "ZP0";
ZPX0: statename = "ZPX0";
ZPX1: statename = "ZPX1";
ABS0: statename = "ABS0";
ABS1: statename = "ABS1";
ABSX0: statename = "ABSX0";
ABSX1: statename = "ABSX1";
ABSX2: statename = "ABSX2";
INDX0: statename = "INDX0";
INDX1: statename = "INDX1";
INDX2: statename = "INDX2";
INDX3: statename = "INDX3";
INDY0: statename = "INDY0";
INDY1: statename = "INDY1";
INDY2: statename = "INDY2";
INDY3: statename = "INDY3";
READ: statename = "READ";
WRITE: statename = "WRITE";
FETCH: statename = "FETCH";
PUSH0: statename = "PUSH0";
PUSH1: statename = "PUSH1";
PULL0: statename = "PULL0";
PULL1: statename = "PULL1";
PULL2: statename = "PULL2";
JSR0: statename = "JSR0";
JSR1: statename = "JSR1";
JSR2: statename = "JSR2";
JSR3: statename = "JSR3";
RTI0: statename = "RTI0";
RTI1: statename = "RTI1";
RTI2: statename = "RTI2";
RTI3: statename = "RTI3";
RTI4: statename = "RTI4";
RTS0: statename = "RTS0";
RTS1: statename = "RTS1";
RTS2: statename = "RTS2";
RTS3: statename = "RTS3";
BRK0: statename = "BRK0";
BRK1: statename = "BRK1";
BRK2: statename = "BRK2";
BRK3: statename = "BRK3";
BRA0: statename = "BRA0";
BRA1: statename = "BRA1";
BRA2: statename = "BRA2";
JMP0: statename = "JMP0";
JMP1: statename = "JMP1";
JMPI0: statename = "JMPI0";
JMPI1: statename = "JMPI1";
endcase
`endif
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_temp = { ABH, ABL };
else
PC_temp = PC;
JMP1,
JMPI1,
JSR3,
RTS3,
RTI4: PC_temp = { DIMUX, ADD };
BRA1: PC_temp = { ABH, ADD };
BRA2: PC_temp = { ADD, PCL };
BRK2: PC_temp = res ? 16'hfffc :
NMI_edge ? 16'hfffa : 16'hfffe;
default: PC_temp = PC;
endcase
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_inc = 0;
else
PC_inc = 1;
ABS0,
ABSX0,
FETCH,
BRA0,
BRA2,
BRK3,
JMPI1,
JMP1,
RTI4,
RTS3: PC_inc = 1;
BRA1: PC_inc = CO ^~ backwards;
default: PC_inc = 0;
endcase
always @(posedge clk)
if( RDY )
PC <= PC_temp + PC_inc;
parameter
ZEROPAGE = 8'h00,
STACKPAGE = 8'h01;
always @*
case( state )
ABSX1,
INDX3,
INDY2,
JMP1,
JMPI1,
RTI4,
ABS1: AB = { DIMUX, ADD };
BRA2,
INDY3,
ABSX2: AB = { ADD, ABL };
BRA1: AB = { ABH, ADD };
JSR0,
PUSH1,
RTS0,
RTI0,
BRK0: AB = { STACKPAGE, regfile };
BRK1,
JSR1,
PULL1,
RTS1,
RTS2,
RTI1,
RTI2,
RTI3,
BRK2: AB = { STACKPAGE, ADD };
INDY1,
INDX1,
ZPX1,
INDX2: AB = { ZEROPAGE, ADD };
ZP0,
INDY0: AB = { ZEROPAGE, DIMUX };
REG,
READ,
WRITE: AB = { ABH, ABL };
default: AB = PC;
endcase
always @(posedge clk)
if( state != PUSH0 && state != PUSH1 && RDY &&
state != PULL0 && state != PULL1 && state != PULL2 )
begin
ABL <= AB[7:0];
ABH <= AB[15:8];
end
always @*
case( state )
WRITE: DO = ADD;
JSR0,
BRK0: DO = PCH;
JSR1,
BRK1: DO = PCL;
PUSH1: DO = php ? P : ADD;
BRK2: DO = (IRQ | NMI_edge) ? (P & 8'b1110_1111) : P;
default: DO = regfile;
endcase
always @*
case( state )
BRK0,
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = 1;
INDX3,
INDY3,
ABSX2,
ABS1,
ZPX1,
ZP0: WE = store;
default: WE = 0;
endcase
reg write_register;
always @*
case( state )
DECODE: write_register = load_reg & ~plp;
PULL1,
RTS2,
RTI3,
BRK3,
JSR0,
JSR2 : write_register = 1;
default: write_register = 0;
endcase
always @(posedge clk)
adj_bcd <= adc_sbc & D;
reg [3:0] ADJL;
reg [3:0] ADJH;
always @* begin
casex( {adj_bcd, adc_bcd, HC} )
3'b0xx: ADJL = 4'd0;
3'b100: ADJL = 4'd10;
3'b101: ADJL = 4'd0;
3'b110: ADJL = 4'd0;
3'b111: ADJL = 4'd6;
endcase
end
always @* begin
casex( {adj_bcd, adc_bcd, CO} )
3'b0xx: ADJH = 4'd0;
3'b100: ADJH = 4'd10;
3'b101: ADJH = 4'd0;
3'b110: ADJH = 4'd0;
3'b111: ADJH = 4'd6;
endcase
end
always @(posedge clk)
if( write_register & RDY )
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
always @*
case( state )
INDY1,
INDX0,
ZPX0,
ABSX0 : regsel = index_y ? SEL_Y : SEL_X;
DECODE : regsel = dst_reg;
BRK0,
BRK3,
JSR0,
JSR2,
PULL0,
PULL1,
PUSH1,
RTI0,
RTI3,
RTS0,
RTS2 : regsel = SEL_S;
default: regsel = src_reg;
endcase
ALU ALU( .clk(clk),
.op(alu_op),
.right(alu_shift_right),
.AI(AI),
.BI(BI),
.CI(CI),
.BCD(adc_bcd & (state == FETCH)),
.CO(CO),
.OUT(ADD),
.V(AV),
.Z(AZ),
.N(AN),
.HC(HC),
.RDY(RDY) );
always @*
case( state )
READ: alu_op = op;
BRA1: alu_op = backwards ? OP_SUB : OP_ADD;
FETCH,
REG : alu_op = op;
DECODE,
ABS1: alu_op = 1'bx;
PUSH1,
BRK0,
BRK1,
BRK2,
JSR0,
JSR1: alu_op = OP_SUB;
default: alu_op = OP_ADD;
endcase
always @*
if( state == FETCH || state == REG || state == READ )
alu_shift_right = shift_right;
else
alu_shift_right = 0;
always @(posedge clk)
if( RDY )
backwards <= DIMUX[7];
always @*
case( state )
JSR1,
RTS1,
RTI1,
RTI2,
BRK1,
BRK2,
INDX1: AI = ADD;
REG,
ZPX0,
INDX0,
ABSX0,
RTI0,
RTS0,
JSR0,
JSR2,
BRK0,
PULL0,
INDY1,
PUSH0,
PUSH1: AI = regfile;
BRA0,
READ: AI = DIMUX;
BRA1: AI = ABH;
FETCH: AI = load_only ? 0 : regfile;
DECODE,
ABS1: AI = 8'hxx;
default: AI = 0;
endcase
always @*
case( state )
BRA1,
RTS1,
RTI0,
RTI1,
RTI2,
INDX1,
READ,
REG,
JSR0,
JSR1,
JSR2,
BRK0,
BRK1,
BRK2,
PUSH0,
PUSH1,
PULL0,
RTS0: BI = 8'h00;
BRA0: BI = PCL;
DECODE,
ABS1: BI = 8'hxx;
default: BI = DIMUX;
endcase
always @*
case( state )
INDY2,
BRA1,
ABSX1: CI = CO;
DECODE,
ABS1: CI = 1'bx;
READ,
REG: CI = rotate ? C :
shift ? 0 : inc;
FETCH: CI = rotate ? C :
compare ? 1 :
(shift | load_only) ? 0 : C;
PULL0,
RTI0,
RTI1,
RTI2,
RTS0,
RTS1,
INDY0,
INDX1: CI = 1;
default: CI = 0;
endcase
always @(posedge clk )
if( shift && state == WRITE )
C <= CO;
else if( state == RTI2 )
C <= DIMUX[0];
else if( ~write_back && state == DECODE ) begin
if( adc_sbc | shift | compare )
C <= CO;
else if( plp )
C <= ADD[0];
else begin
if( sec ) C <= 1;
if( clc ) C <= 0;
end
end
always @(posedge clk)
if( state == WRITE )
Z <= AZ;
else if( state == RTI2 )
Z <= DIMUX[1];
else if( state == DECODE ) begin
if( plp )
Z <= ADD[1];
else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins )
Z <= AZ;
end
always @(posedge clk)
if( state == WRITE )
N <= AN;
else if( state == RTI2 )
N <= DIMUX[7];
else if( state == DECODE ) begin
if( plp )
N <= ADD[7];
else if( (load_reg & (regsel != SEL_S)) | compare )
N <= AN;
end else if( state == FETCH && bit_ins )
N <= DIMUX[7];
always @(posedge clk)
if( state == BRK3 )
I <= 1;
else if( state == RTI2 )
I <= DIMUX[2];
else if( state == REG ) begin
if( sei ) I <= 1;
if( cli ) I <= 0;
end else if( state == DECODE )
if( plp ) I <= ADD[2];
always @(posedge clk )
if( state == RTI2 )
D <= DIMUX[3];
else if( state == DECODE ) begin
if( sed ) D <= 1;
if( cld ) D <= 0;
if( plp ) D <= ADD[3];
end
always @(posedge clk )
if( state == RTI2 )
V <= DIMUX[6];
else if( state == DECODE ) begin
if( adc_sbc ) V <= AV;
if( clv ) V <= 0;
if( plp ) V <= ADD[6];
end else if( state == FETCH && bit_ins )
V <= DIMUX[6];
always @(posedge clk )
if( reset )
IRHOLD_valid <= 0;
else if( RDY ) begin
if( state == PULL0 || state == PUSH0 ) begin
IRHOLD <= DIMUX;
IRHOLD_valid <= 1;
end else if( state == DECODE )
IRHOLD_valid <= 0;
end
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
IRHOLD_valid ? IRHOLD : DIMUX;
always @(posedge clk )
if( RDY )
DIHOLD <= DI;
assign DIMUX = ~RDY ? DIHOLD : DI;
always @(posedge clk or posedge reset)
if( reset )
state <= BRK0;
else if( RDY ) case( state )
DECODE :
casex ( IR )
8'b0000_0000: state <= BRK0;
8'b0010_0000: state <= JSR0;
8'b0010_1100: state <= ABS0;
8'b0100_0000: state <= RTI0;
8'b0100_1100: state <= JMP0;
8'b0110_0000: state <= RTS0;
8'b0110_1100: state <= JMPI0;
8'b0x00_1000: state <= PUSH0;
8'b0x10_1000: state <= PULL0;
8'b0xx1_1000: state <= REG;
8'b1xx0_00x0: state <= FETCH;
8'b1xx0_1100: state <= ABS0;
8'b1xxx_1000: state <= REG;
8'bxxx0_0001: state <= INDX0;
8'bxxx0_01xx: state <= ZP0;
8'bxxx0_1001: state <= FETCH;
8'bxxx0_1101: state <= ABS0;
8'bxxx0_1110: state <= ABS0;
8'bxxx1_0000: state <= BRA0;
8'bxxx1_0001: state <= INDY0;
8'bxxx1_01xx: state <= ZPX0;
8'bxxx1_1001: state <= ABSX0;
8'bxxx1_11xx: state <= ABSX0;
8'bxxxx_1010: state <= REG;
endcase
ZP0 : state <= write_back ? READ : FETCH;
ZPX0 : state <= ZPX1;
ZPX1 : state <= write_back ? READ : FETCH;
ABS0 : state <= ABS1;
ABS1 : state <= write_back ? READ : FETCH;
ABSX0 : state <= ABSX1;
ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH;
ABSX2 : state <= write_back ? READ : FETCH;
INDX0 : state <= INDX1;
INDX1 : state <= INDX2;
INDX2 : state <= INDX3;
INDX3 : state <= FETCH;
INDY0 : state <= INDY1;
INDY1 : state <= INDY2;
INDY2 : state <= (CO | store) ? INDY3 : FETCH;
INDY3 : state <= FETCH;
READ : state <= WRITE;
WRITE : state <= FETCH;
FETCH : state <= DECODE;
REG : state <= DECODE;
PUSH0 : state <= PUSH1;
PUSH1 : state <= DECODE;
PULL0 : state <= PULL1;
PULL1 : state <= PULL2;
PULL2 : state <= DECODE;
JSR0 : state <= JSR1;
JSR1 : state <= JSR2;
JSR2 : state <= JSR3;
JSR3 : state <= FETCH;
RTI0 : state <= RTI1;
RTI1 : state <= RTI2;
RTI2 : state <= RTI3;
RTI3 : state <= RTI4;
RTI4 : state <= DECODE;
RTS0 : state <= RTS1;
RTS1 : state <= RTS2;
RTS2 : state <= RTS3;
RTS3 : state <= FETCH;
BRA0 : state <= cond_true ? BRA1 : DECODE;
BRA1 : state <= (CO ^ backwards) ? BRA2 : DECODE;
BRA2 : state <= DECODE;
JMP0 : state <= JMP1;
JMP1 : state <= DECODE;
JMPI0 : state <= JMPI1;
JMPI1 : state <= JMP0;
BRK0 : state <= BRK1;
BRK1 : state <= BRK2;
BRK2 : state <= BRK3;
BRK3 : state <= JMP0;
endcase
always @(posedge clk)
if( reset )
res <= 1;
else if( state == DECODE )
res <= 0;
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b0xx01010,
8'b0xxxxx01,
8'b100x10x0,
8'b1010xxx0,
8'b10111010,
8'b1011x1x0,
8'b11001010,
8'b1x1xxx01,
8'bxxx01000:
load_reg <= 1;
default: load_reg <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1110_1000,
8'b1100_1010,
8'b101x_xx10:
dst_reg <= SEL_X;
8'b0x00_1000,
8'b1001_1010:
dst_reg <= SEL_S;
8'b1x00_1000,
8'b101x_x100,
8'b1010_x000:
dst_reg <= SEL_Y;
default: dst_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1011_1010:
src_reg <= SEL_S;
8'b100x_x110,
8'b100x_1x10,
8'b1110_xx00,
8'b1100_1010:
src_reg <= SEL_X;
8'b100x_x100,
8'b1001_1000,
8'b1100_xx00,
8'b1x00_1000:
src_reg <= SEL_Y;
default: src_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'bxxx1_0001,
8'b10x1_x110,
8'bxxxx_1001:
index_y <= 1;
default: index_y <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b100x_x1x0,
8'b100x_xx01:
store <= 1;
default: store <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110,
8'b11xx_x110:
write_back <= 1;
default: write_back <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b101x_xxxx:
load_only <= 1;
default: load_only <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b111x_x110,
8'b11x0_1000:
inc <= 1;
default: inc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'bx11x_xx01:
adc_sbc <= 1;
default: adc_sbc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'b011x_xx01:
adc_bcd <= D;
default: adc_bcd <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110,
8'b0xxx_1010:
shift <= 1;
default: shift <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b11x0_0x00,
8'b11x0_1100,
8'b110x_xx01:
compare <= 1;
default: compare <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b01xx_xx10:
shift_right <= 1;
default: shift_right <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0x1x_1010,
8'b0x1x_x110:
rotate <= 1;
default: rotate <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b00xx_xx10:
op <= OP_ROL;
8'b0010_x100:
op <= OP_AND;
8'b01xx_xx10:
op <= OP_A;
8'b1000_1000,
8'b1100_1010,
8'b110x_x110,
8'b11xx_xx01,
8'b11x0_0x00,
8'b11x0_1100: op <= OP_SUB;
8'b010x_xx01,
8'b00xx_xx01:
op <= { 2'b11, IR[6:5] };
default: op <= OP_ADD;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0010_x100:
bit_ins <= 1;
default: bit_ins <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY ) begin
php <= (IR == 8'h08);
clc <= (IR == 8'h18);
plp <= (IR == 8'h28);
sec <= (IR == 8'h38);
cli <= (IR == 8'h58);
sei <= (IR == 8'h78);
clv <= (IR == 8'hb8);
cld <= (IR == 8'hd8);
sed <= (IR == 8'hf8);
brk <= (IR == 8'h00);
end
always @(posedge clk)
if( RDY )
cond_code <= IR[7:5];
always @*
case( cond_code )
3'b000: cond_true = ~N;
3'b001: cond_true = N;
3'b010: cond_true = ~V;
3'b011: cond_true = V;
3'b100: cond_true = ~C;
3'b101: cond_true = C;
3'b110: cond_true = ~Z;
3'b111: cond_true = Z;
endcase
reg NMI_1 = 0;
always @(posedge clk)
NMI_1 <= NMI;
always @(posedge clk )
if( NMI_edge && state == BRK3 )
NMI_edge <= 0;
else if( NMI & ~NMI_1 )
NMI_edge <= 1;
endmodule | module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY ); |
input clk;
input reset;
output reg [15:0] AB;
input [7:0] DI;
output [7:0] DO;
output WE;
input IRQ;
input NMI;
input RDY;
reg [15:0] PC;
reg [7:0] ABL;
reg [7:0] ABH;
wire [7:0] ADD;
reg [7:0] DIHOLD;
reg DIHOLD_valid;
wire [7:0] DIMUX;
reg [7:0] IRHOLD;
reg IRHOLD_valid;
reg [7:0] AXYS[3:0];
reg C = 0;
reg Z = 0;
reg I = 0;
reg D = 0;
reg V = 0;
reg N = 0;
wire AZ;
wire AV;
wire AN;
wire HC;
reg [7:0] AI;
reg [7:0] BI;
wire [7:0] DI;
wire [7:0] IR;
reg [7:0] DO;
reg WE;
reg CI;
wire CO;
wire [7:0] PCH = PC[15:8];
wire [7:0] PCL = PC[7:0];
reg NMI_edge = 0;
reg [1:0] regsel;
wire [7:0] regfile = AXYS[regsel];
parameter
SEL_A = 2'd0,
SEL_S = 2'd1,
SEL_X = 2'd2,
SEL_Y = 2'd3;
`ifdef SIM
wire [7:0] A = AXYS[SEL_A];
wire [7:0] X = AXYS[SEL_X];
wire [7:0] Y = AXYS[SEL_Y];
wire [7:0] S = AXYS[SEL_S];
`endif
initial begin
AB = 0;
PC = 0;
ABL = 0;
ABH = 0;
DIHOLD = 0;
DIHOLD_valid = 0;
IRHOLD = 0;
IRHOLD_valid = 0;
AXYS[0] = 0;
AXYS[1] = 0;
AXYS[2] = 0;
AXYS[3] = 0;
C = 0;
Z = 0;
I = 0;
D = 0;
V = 0;
N = 0;
AI = 0;
BI = 0;
DO = 0;
WE = 0;
CI = 0;
NMI_edge = 0;
regsel = 0;
end
wire [7:0] P = { N, V, 2'b11, D, I, Z, C };
reg [5:0] state;
reg PC_inc;
reg [15:0] PC_temp;
reg [1:0] src_reg;
reg [1:0] dst_reg;
reg index_y;
reg load_reg;
reg inc;
reg write_back;
reg load_only;
reg store;
reg adc_sbc;
reg compare;
reg shift;
reg rotate;
reg backwards;
reg cond_true;
reg [2:0] cond_code;
reg shift_right;
reg alu_shift_right;
reg [3:0] op;
reg [3:0] alu_op;
reg adc_bcd;
reg adj_bcd;
reg bit_ins;
reg plp;
reg php;
reg clc;
reg sec;
reg cld;
reg sed;
reg cli;
reg sei;
reg clv;
reg brk;
reg res;
parameter
OP_OR = 4'b1100,
OP_AND = 4'b1101,
OP_EOR = 4'b1110,
OP_ADD = 4'b0011,
OP_SUB = 4'b0111,
OP_ROL = 4'b1011,
OP_A = 4'b1111;
parameter
ABS0 = 6'd0,
ABS1 = 6'd1,
ABSX0 = 6'd2,
ABSX1 = 6'd3,
ABSX2 = 6'd4,
BRA0 = 6'd5,
BRA1 = 6'd6,
BRA2 = 6'd7,
BRK0 = 6'd8,
BRK1 = 6'd9,
BRK2 = 6'd10,
BRK3 = 6'd11,
DECODE = 6'd12,
FETCH = 6'd13,
INDX0 = 6'd14,
INDX1 = 6'd15,
INDX2 = 6'd16,
INDX3 = 6'd17,
INDY0 = 6'd18,
INDY1 = 6'd19,
INDY2 = 6'd20,
INDY3 = 6'd21,
JMP0 = 6'd22,
JMP1 = 6'd23,
JMPI0 = 6'd24,
JMPI1 = 6'd25,
JSR0 = 6'd26,
JSR1 = 6'd27,
JSR2 = 6'd28,
JSR3 = 6'd29,
PULL0 = 6'd30,
PULL1 = 6'd31,
PULL2 = 6'd32,
PUSH0 = 6'd33,
PUSH1 = 6'd34,
READ = 6'd35,
REG = 6'd36,
RTI0 = 6'd37,
RTI1 = 6'd38,
RTI2 = 6'd39,
RTI3 = 6'd40,
RTI4 = 6'd41,
RTS0 = 6'd42,
RTS1 = 6'd43,
RTS2 = 6'd44,
RTS3 = 6'd45,
WRITE = 6'd46,
ZP0 = 6'd47,
ZPX0 = 6'd48,
ZPX1 = 6'd49;
`ifdef SIM
reg [8*6-1:0] statename;
always @*
case( state )
DECODE: statename = "DECODE";
REG: statename = "REG";
ZP0: statename = "ZP0";
ZPX0: statename = "ZPX0";
ZPX1: statename = "ZPX1";
ABS0: statename = "ABS0";
ABS1: statename = "ABS1";
ABSX0: statename = "ABSX0";
ABSX1: statename = "ABSX1";
ABSX2: statename = "ABSX2";
INDX0: statename = "INDX0";
INDX1: statename = "INDX1";
INDX2: statename = "INDX2";
INDX3: statename = "INDX3";
INDY0: statename = "INDY0";
INDY1: statename = "INDY1";
INDY2: statename = "INDY2";
INDY3: statename = "INDY3";
READ: statename = "READ";
WRITE: statename = "WRITE";
FETCH: statename = "FETCH";
PUSH0: statename = "PUSH0";
PUSH1: statename = "PUSH1";
PULL0: statename = "PULL0";
PULL1: statename = "PULL1";
PULL2: statename = "PULL2";
JSR0: statename = "JSR0";
JSR1: statename = "JSR1";
JSR2: statename = "JSR2";
JSR3: statename = "JSR3";
RTI0: statename = "RTI0";
RTI1: statename = "RTI1";
RTI2: statename = "RTI2";
RTI3: statename = "RTI3";
RTI4: statename = "RTI4";
RTS0: statename = "RTS0";
RTS1: statename = "RTS1";
RTS2: statename = "RTS2";
RTS3: statename = "RTS3";
BRK0: statename = "BRK0";
BRK1: statename = "BRK1";
BRK2: statename = "BRK2";
BRK3: statename = "BRK3";
BRA0: statename = "BRA0";
BRA1: statename = "BRA1";
BRA2: statename = "BRA2";
JMP0: statename = "JMP0";
JMP1: statename = "JMP1";
JMPI0: statename = "JMPI0";
JMPI1: statename = "JMPI1";
endcase
`endif
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_temp = { ABH, ABL };
else
PC_temp = PC;
JMP1,
JMPI1,
JSR3,
RTS3,
RTI4: PC_temp = { DIMUX, ADD };
BRA1: PC_temp = { ABH, ADD };
BRA2: PC_temp = { ADD, PCL };
BRK2: PC_temp = res ? 16'hfffc :
NMI_edge ? 16'hfffa : 16'hfffe;
default: PC_temp = PC;
endcase
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_inc = 0;
else
PC_inc = 1;
ABS0,
ABSX0,
FETCH,
BRA0,
BRA2,
BRK3,
JMPI1,
JMP1,
RTI4,
RTS3: PC_inc = 1;
BRA1: PC_inc = CO ^~ backwards;
default: PC_inc = 0;
endcase
always @(posedge clk)
if( RDY )
PC <= PC_temp + PC_inc;
parameter
ZEROPAGE = 8'h00,
STACKPAGE = 8'h01;
always @*
case( state )
ABSX1,
INDX3,
INDY2,
JMP1,
JMPI1,
RTI4,
ABS1: AB = { DIMUX, ADD };
BRA2,
INDY3,
ABSX2: AB = { ADD, ABL };
BRA1: AB = { ABH, ADD };
JSR0,
PUSH1,
RTS0,
RTI0,
BRK0: AB = { STACKPAGE, regfile };
BRK1,
JSR1,
PULL1,
RTS1,
RTS2,
RTI1,
RTI2,
RTI3,
BRK2: AB = { STACKPAGE, ADD };
INDY1,
INDX1,
ZPX1,
INDX2: AB = { ZEROPAGE, ADD };
ZP0,
INDY0: AB = { ZEROPAGE, DIMUX };
REG,
READ,
WRITE: AB = { ABH, ABL };
default: AB = PC;
endcase
always @(posedge clk)
if( state != PUSH0 && state != PUSH1 && RDY &&
state != PULL0 && state != PULL1 && state != PULL2 )
begin
ABL <= AB[7:0];
ABH <= AB[15:8];
end
always @*
case( state )
WRITE: DO = ADD;
JSR0,
BRK0: DO = PCH;
JSR1,
BRK1: DO = PCL;
PUSH1: DO = php ? P : ADD;
BRK2: DO = (IRQ | NMI_edge) ? (P & 8'b1110_1111) : P;
default: DO = regfile;
endcase
always @*
case( state )
BRK0,
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = 1;
INDX3,
INDY3,
ABSX2,
ABS1,
ZPX1,
ZP0: WE = store;
default: WE = 0;
endcase
reg write_register;
always @*
case( state )
DECODE: write_register = load_reg & ~plp;
PULL1,
RTS2,
RTI3,
BRK3,
JSR0,
JSR2 : write_register = 1;
default: write_register = 0;
endcase
always @(posedge clk)
adj_bcd <= adc_sbc & D;
reg [3:0] ADJL;
reg [3:0] ADJH;
always @* begin
casex( {adj_bcd, adc_bcd, HC} )
3'b0xx: ADJL = 4'd0;
3'b100: ADJL = 4'd10;
3'b101: ADJL = 4'd0;
3'b110: ADJL = 4'd0;
3'b111: ADJL = 4'd6;
endcase
end
always @* begin
casex( {adj_bcd, adc_bcd, CO} )
3'b0xx: ADJH = 4'd0;
3'b100: ADJH = 4'd10;
3'b101: ADJH = 4'd0;
3'b110: ADJH = 4'd0;
3'b111: ADJH = 4'd6;
endcase
end
always @(posedge clk)
if( write_register & RDY )
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
always @*
case( state )
INDY1,
INDX0,
ZPX0,
ABSX0 : regsel = index_y ? SEL_Y : SEL_X;
DECODE : regsel = dst_reg;
BRK0,
BRK3,
JSR0,
JSR2,
PULL0,
PULL1,
PUSH1,
RTI0,
RTI3,
RTS0,
RTS2 : regsel = SEL_S;
default: regsel = src_reg;
endcase
ALU ALU( .clk(clk),
.op(alu_op),
.right(alu_shift_right),
.AI(AI),
.BI(BI),
.CI(CI),
.BCD(adc_bcd & (state == FETCH)),
.CO(CO),
.OUT(ADD),
.V(AV),
.Z(AZ),
.N(AN),
.HC(HC),
.RDY(RDY) );
always @*
case( state )
READ: alu_op = op;
BRA1: alu_op = backwards ? OP_SUB : OP_ADD;
FETCH,
REG : alu_op = op;
DECODE,
ABS1: alu_op = 1'bx;
PUSH1,
BRK0,
BRK1,
BRK2,
JSR0,
JSR1: alu_op = OP_SUB;
default: alu_op = OP_ADD;
endcase
always @*
if( state == FETCH || state == REG || state == READ )
alu_shift_right = shift_right;
else
alu_shift_right = 0;
always @(posedge clk)
if( RDY )
backwards <= DIMUX[7];
always @*
case( state )
JSR1,
RTS1,
RTI1,
RTI2,
BRK1,
BRK2,
INDX1: AI = ADD;
REG,
ZPX0,
INDX0,
ABSX0,
RTI0,
RTS0,
JSR0,
JSR2,
BRK0,
PULL0,
INDY1,
PUSH0,
PUSH1: AI = regfile;
BRA0,
READ: AI = DIMUX;
BRA1: AI = ABH;
FETCH: AI = load_only ? 0 : regfile;
DECODE,
ABS1: AI = 8'hxx;
default: AI = 0;
endcase
always @*
case( state )
BRA1,
RTS1,
RTI0,
RTI1,
RTI2,
INDX1,
READ,
REG,
JSR0,
JSR1,
JSR2,
BRK0,
BRK1,
BRK2,
PUSH0,
PUSH1,
PULL0,
RTS0: BI = 8'h00;
BRA0: BI = PCL;
DECODE,
ABS1: BI = 8'hxx;
default: BI = DIMUX;
endcase
always @*
case( state )
INDY2,
BRA1,
ABSX1: CI = CO;
DECODE,
ABS1: CI = 1'bx;
READ,
REG: CI = rotate ? C :
shift ? 0 : inc;
FETCH: CI = rotate ? C :
compare ? 1 :
(shift | load_only) ? 0 : C;
PULL0,
RTI0,
RTI1,
RTI2,
RTS0,
RTS1,
INDY0,
INDX1: CI = 1;
default: CI = 0;
endcase
always @(posedge clk )
if( shift && state == WRITE )
C <= CO;
else if( state == RTI2 )
C <= DIMUX[0];
else if( ~write_back && state == DECODE ) begin
if( adc_sbc | shift | compare )
C <= CO;
else if( plp )
C <= ADD[0];
else begin
if( sec ) C <= 1;
if( clc ) C <= 0;
end
end
always @(posedge clk)
if( state == WRITE )
Z <= AZ;
else if( state == RTI2 )
Z <= DIMUX[1];
else if( state == DECODE ) begin
if( plp )
Z <= ADD[1];
else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins )
Z <= AZ;
end
always @(posedge clk)
if( state == WRITE )
N <= AN;
else if( state == RTI2 )
N <= DIMUX[7];
else if( state == DECODE ) begin
if( plp )
N <= ADD[7];
else if( (load_reg & (regsel != SEL_S)) | compare )
N <= AN;
end else if( state == FETCH && bit_ins )
N <= DIMUX[7];
always @(posedge clk)
if( state == BRK3 )
I <= 1;
else if( state == RTI2 )
I <= DIMUX[2];
else if( state == REG ) begin
if( sei ) I <= 1;
if( cli ) I <= 0;
end else if( state == DECODE )
if( plp ) I <= ADD[2];
always @(posedge clk )
if( state == RTI2 )
D <= DIMUX[3];
else if( state == DECODE ) begin
if( sed ) D <= 1;
if( cld ) D <= 0;
if( plp ) D <= ADD[3];
end
always @(posedge clk )
if( state == RTI2 )
V <= DIMUX[6];
else if( state == DECODE ) begin
if( adc_sbc ) V <= AV;
if( clv ) V <= 0;
if( plp ) V <= ADD[6];
end else if( state == FETCH && bit_ins )
V <= DIMUX[6];
always @(posedge clk )
if( reset )
IRHOLD_valid <= 0;
else if( RDY ) begin
if( state == PULL0 || state == PUSH0 ) begin
IRHOLD <= DIMUX;
IRHOLD_valid <= 1;
end else if( state == DECODE )
IRHOLD_valid <= 0;
end
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
IRHOLD_valid ? IRHOLD : DIMUX;
always @(posedge clk )
if( RDY )
DIHOLD <= DI;
assign DIMUX = ~RDY ? DIHOLD : DI;
always @(posedge clk or posedge reset)
if( reset )
state <= BRK0;
else if( RDY ) case( state )
DECODE :
casex ( IR )
8'b0000_0000: state <= BRK0;
8'b0010_0000: state <= JSR0;
8'b0010_1100: state <= ABS0;
8'b0100_0000: state <= RTI0;
8'b0100_1100: state <= JMP0;
8'b0110_0000: state <= RTS0;
8'b0110_1100: state <= JMPI0;
8'b0x00_1000: state <= PUSH0;
8'b0x10_1000: state <= PULL0;
8'b0xx1_1000: state <= REG;
8'b1xx0_00x0: state <= FETCH;
8'b1xx0_1100: state <= ABS0;
8'b1xxx_1000: state <= REG;
8'bxxx0_0001: state <= INDX0;
8'bxxx0_01xx: state <= ZP0;
8'bxxx0_1001: state <= FETCH;
8'bxxx0_1101: state <= ABS0;
8'bxxx0_1110: state <= ABS0;
8'bxxx1_0000: state <= BRA0;
8'bxxx1_0001: state <= INDY0;
8'bxxx1_01xx: state <= ZPX0;
8'bxxx1_1001: state <= ABSX0;
8'bxxx1_11xx: state <= ABSX0;
8'bxxxx_1010: state <= REG;
endcase
ZP0 : state <= write_back ? READ : FETCH;
ZPX0 : state <= ZPX1;
ZPX1 : state <= write_back ? READ : FETCH;
ABS0 : state <= ABS1;
ABS1 : state <= write_back ? READ : FETCH;
ABSX0 : state <= ABSX1;
ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH;
ABSX2 : state <= write_back ? READ : FETCH;
INDX0 : state <= INDX1;
INDX1 : state <= INDX2;
INDX2 : state <= INDX3;
INDX3 : state <= FETCH;
INDY0 : state <= INDY1;
INDY1 : state <= INDY2;
INDY2 : state <= (CO | store) ? INDY3 : FETCH;
INDY3 : state <= FETCH;
READ : state <= WRITE;
WRITE : state <= FETCH;
FETCH : state <= DECODE;
REG : state <= DECODE;
PUSH0 : state <= PUSH1;
PUSH1 : state <= DECODE;
PULL0 : state <= PULL1;
PULL1 : state <= PULL2;
PULL2 : state <= DECODE;
JSR0 : state <= JSR1;
JSR1 : state <= JSR2;
JSR2 : state <= JSR3;
JSR3 : state <= FETCH;
RTI0 : state <= RTI1;
RTI1 : state <= RTI2;
RTI2 : state <= RTI3;
RTI3 : state <= RTI4;
RTI4 : state <= DECODE;
RTS0 : state <= RTS1;
RTS1 : state <= RTS2;
RTS2 : state <= RTS3;
RTS3 : state <= FETCH;
BRA0 : state <= cond_true ? BRA1 : DECODE;
BRA1 : state <= (CO ^ backwards) ? BRA2 : DECODE;
BRA2 : state <= DECODE;
JMP0 : state <= JMP1;
JMP1 : state <= DECODE;
JMPI0 : state <= JMPI1;
JMPI1 : state <= JMP0;
BRK0 : state <= BRK1;
BRK1 : state <= BRK2;
BRK2 : state <= BRK3;
BRK3 : state <= JMP0;
endcase
always @(posedge clk)
if( reset )
res <= 1;
else if( state == DECODE )
res <= 0;
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b0xx01010,
8'b0xxxxx01,
8'b100x10x0,
8'b1010xxx0,
8'b10111010,
8'b1011x1x0,
8'b11001010,
8'b1x1xxx01,
8'bxxx01000:
load_reg <= 1;
default: load_reg <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1110_1000,
8'b1100_1010,
8'b101x_xx10:
dst_reg <= SEL_X;
8'b0x00_1000,
8'b1001_1010:
dst_reg <= SEL_S;
8'b1x00_1000,
8'b101x_x100,
8'b1010_x000:
dst_reg <= SEL_Y;
default: dst_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1011_1010:
src_reg <= SEL_S;
8'b100x_x110,
8'b100x_1x10,
8'b1110_xx00,
8'b1100_1010:
src_reg <= SEL_X;
8'b100x_x100,
8'b1001_1000,
8'b1100_xx00,
8'b1x00_1000:
src_reg <= SEL_Y;
default: src_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'bxxx1_0001,
8'b10x1_x110,
8'bxxxx_1001:
index_y <= 1;
default: index_y <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b100x_x1x0,
8'b100x_xx01:
store <= 1;
default: store <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110,
8'b11xx_x110:
write_back <= 1;
default: write_back <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b101x_xxxx:
load_only <= 1;
default: load_only <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b111x_x110,
8'b11x0_1000:
inc <= 1;
default: inc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'bx11x_xx01:
adc_sbc <= 1;
default: adc_sbc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'b011x_xx01:
adc_bcd <= D;
default: adc_bcd <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110,
8'b0xxx_1010:
shift <= 1;
default: shift <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b11x0_0x00,
8'b11x0_1100,
8'b110x_xx01:
compare <= 1;
default: compare <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b01xx_xx10:
shift_right <= 1;
default: shift_right <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0x1x_1010,
8'b0x1x_x110:
rotate <= 1;
default: rotate <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b00xx_xx10:
op <= OP_ROL;
8'b0010_x100:
op <= OP_AND;
8'b01xx_xx10:
op <= OP_A;
8'b1000_1000,
8'b1100_1010,
8'b110x_x110,
8'b11xx_xx01,
8'b11x0_0x00,
8'b11x0_1100: op <= OP_SUB;
8'b010x_xx01,
8'b00xx_xx01:
op <= { 2'b11, IR[6:5] };
default: op <= OP_ADD;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0010_x100:
bit_ins <= 1;
default: bit_ins <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY ) begin
php <= (IR == 8'h08);
clc <= (IR == 8'h18);
plp <= (IR == 8'h28);
sec <= (IR == 8'h38);
cli <= (IR == 8'h58);
sei <= (IR == 8'h78);
clv <= (IR == 8'hb8);
cld <= (IR == 8'hd8);
sed <= (IR == 8'hf8);
brk <= (IR == 8'h00);
end
always @(posedge clk)
if( RDY )
cond_code <= IR[7:5];
always @*
case( cond_code )
3'b000: cond_true = ~N;
3'b001: cond_true = N;
3'b010: cond_true = ~V;
3'b011: cond_true = V;
3'b100: cond_true = ~C;
3'b101: cond_true = C;
3'b110: cond_true = ~Z;
3'b111: cond_true = Z;
endcase
reg NMI_1 = 0;
always @(posedge clk)
NMI_1 <= NMI;
always @(posedge clk )
if( NMI_edge && state == BRK3 )
NMI_edge <= 0;
else if( NMI & ~NMI_1 )
NMI_edge <= 1;
endmodule | 17 |
3,453 | data/full_repos/permissive/104667535/verilog/mcu.v | 104,667,535 | mcu.v | v | 304 | 89 | [] | [] | [] | [(3, 267), (269, 303)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:284: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:288: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:295: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/104667535/verilog/mcu.v:301: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,165 | module | module mcu (
input clock,
input reset,
inout [7:0] porta,
inout [7:0] portb
);
wire [15:0] address_bus;
wire [7:0] read_bus;
wire [7:0] write_bus;
wire write_enable;
wire irq = 1'b0;
wire nmi = 1'b0;
wire ready;
cpu cpu_inst (
.clk(clock),
.reset(reset),
.AB(address_bus),
.DI(read_bus),
.DO(write_bus),
.WE(write_enable),
.IRQ(irq),
.NMI(nmi),
.RDY(ready)
);
wire cpu_stb_o;
wire cpu_we_o;
wire [15:0] cpu_adr_o;
wire [7:0] cpu_dat_o;
wire cpu_ack_i;
wire [7:0] cpu_dat_i;
wb_6502_bridge wb_6502_bridge_inst (
.clk_i(clock),
.rst_i(reset),
.stb_o(cpu_stb_o),
.we_o(cpu_we_o),
.adr_o(cpu_adr_o),
.dat_o(cpu_dat_o),
.ack_i(cpu_ack_i),
.dat_i(cpu_dat_i),
.address_bus(address_bus),
.read_bus(read_bus),
.write_bus(write_bus),
.write_enable(write_enable),
.ready(ready)
);
wire ram_stb_i;
wire ram_we_i;
wire [15:0] ram_adr_i;
wire [7:0] ram_dat_i;
wire ram_ack_o;
wire [7:0] ram_dat_o;
wb_ram #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(9),
.WB_ALWAYS_READ(1),
.RAM_DEPTH(512)
) main_ram (
.clk_i(clock),
.rst_i(reset),
.stb_i(ram_stb_i),
.we_i(ram_we_i),
.adr_i(ram_adr_i),
.dat_i(ram_dat_i),
.ack_o(ram_ack_o),
.dat_o(ram_dat_o)
);
integer i;
initial begin
for (i = 0; i < 512; i = i + 1) begin
main_ram.ram[i] = 0;
end
end
wire rom_stb_i;
wire rom_we_i;
wire [15:0] rom_adr_i;
wire [7:0] rom_dat_i;
wire rom_ack_o;
wire [7:0] rom_dat_o;
wb_ram #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(9),
.WB_ALWAYS_READ(1),
.RAM_DEPTH(512)
) main_rom (
.clk_i(clock),
.rst_i(reset),
.stb_i(rom_stb_i),
.we_i(rom_we_i),
.adr_i(rom_adr_i),
.dat_i(rom_dat_i),
.ack_o(rom_ack_o),
.dat_o(rom_dat_o)
);
integer j;
initial begin
for (j = 0; j < 512; j = j + 1) begin
main_rom.ram[j] = 0;
end
main_rom.ram[0] = 8'ha9;
main_rom.ram[1] = 8'hff;
main_rom.ram[2] = 8'h8d;
main_rom.ram[3] = 8'h00;
main_rom.ram[4] = 8'hf0;
main_rom.ram[5] = 8'ha9;
main_rom.ram[6] = 8'h01;
main_rom.ram[7] = 8'hee;
main_rom.ram[8] = 8'h02;
main_rom.ram[9] = 8'hf0;
main_rom.ram[10] = 8'h4c;
main_rom.ram[11] = 8'h07;
main_rom.ram[12] = 8'hfe;
main_rom.ram[9'h1fe] = 8'h00;
main_rom.ram[9'h1ff] = 8'hfe;
end
wire via_stb_i;
wire via_we_i;
wire [15:0] via_adr_i;
wire [7:0] via_dat_i;
wire via_ack_o;
wire [7:0] via_dat_o;
wb_6522_via #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(4)
) wb_6522_via_inst (
.clk_i(clock),
.rst_i(reset),
.stb_i(via_stb_i),
.we_i(via_we_i),
.adr_i(via_adr_i),
.dat_i(via_dat_i),
.ack_o(via_ack_o),
.dat_o(via_dat_o),
.port_a(port_a),
.port_b(port_b)
);
wire portb_stb_i;
wire portb_we_i;
wire [15:0] portb_adr_i;
wire [7:0] portb_dat_i;
wire portb_ack_o;
wire [7:0] portb_dat_o;
wb_gpio #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(2)
) portb_inst (
.clk_i(clock),
.rst_i(reset),
.stb_i(portb_stb_i),
.we_i(portb_we_i),
.adr_i(portb_adr_i),
.dat_i(portb_dat_i),
.ack_o(portb_ack_o),
.dat_o(portb_dat_o),
.gpio(portb)
);
wb_bus #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(16),
.WB_NUM_SLAVES(4)
) bus (
.clk_i(clock),
.rst_i(reset),
.mstr_stb_i(cpu_stb_o),
.mstr_we_i(cpu_we_o),
.mstr_adr_i(cpu_adr_o),
.mstr_dat_i(cpu_dat_o),
.mstr_ack_o(cpu_ack_i),
.mstr_dat_o(cpu_dat_i),
.bus_slv_addr_decode_value({16'h0000, 16'hFE00, 16'hF000, 16'hF004}),
.bus_slv_addr_decode_mask ({16'hFE00, 16'hFE00, 16'hFFFC, 16'hFFFC}),
.slv_stb_o ({ram_stb_i, rom_stb_i, porta_stb_i, portb_stb_i}),
.slv_we_o ({ram_we_i, rom_we_i, porta_we_i, portb_we_i}),
.slv_adr_o ({ram_adr_i, rom_adr_i, porta_adr_i, portb_adr_i}),
.slv_dat_o ({ram_dat_i, rom_dat_i, porta_dat_i, portb_dat_i}),
.slv_ack_i ({ram_ack_o, rom_ack_o, porta_ack_o, portb_ack_o}),
.slv_dat_i ({ram_dat_o, rom_dat_o, porta_dat_o, portb_dat_o})
);
endmodule | module mcu (
input clock,
input reset,
inout [7:0] porta,
inout [7:0] portb
); |
wire [15:0] address_bus;
wire [7:0] read_bus;
wire [7:0] write_bus;
wire write_enable;
wire irq = 1'b0;
wire nmi = 1'b0;
wire ready;
cpu cpu_inst (
.clk(clock),
.reset(reset),
.AB(address_bus),
.DI(read_bus),
.DO(write_bus),
.WE(write_enable),
.IRQ(irq),
.NMI(nmi),
.RDY(ready)
);
wire cpu_stb_o;
wire cpu_we_o;
wire [15:0] cpu_adr_o;
wire [7:0] cpu_dat_o;
wire cpu_ack_i;
wire [7:0] cpu_dat_i;
wb_6502_bridge wb_6502_bridge_inst (
.clk_i(clock),
.rst_i(reset),
.stb_o(cpu_stb_o),
.we_o(cpu_we_o),
.adr_o(cpu_adr_o),
.dat_o(cpu_dat_o),
.ack_i(cpu_ack_i),
.dat_i(cpu_dat_i),
.address_bus(address_bus),
.read_bus(read_bus),
.write_bus(write_bus),
.write_enable(write_enable),
.ready(ready)
);
wire ram_stb_i;
wire ram_we_i;
wire [15:0] ram_adr_i;
wire [7:0] ram_dat_i;
wire ram_ack_o;
wire [7:0] ram_dat_o;
wb_ram #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(9),
.WB_ALWAYS_READ(1),
.RAM_DEPTH(512)
) main_ram (
.clk_i(clock),
.rst_i(reset),
.stb_i(ram_stb_i),
.we_i(ram_we_i),
.adr_i(ram_adr_i),
.dat_i(ram_dat_i),
.ack_o(ram_ack_o),
.dat_o(ram_dat_o)
);
integer i;
initial begin
for (i = 0; i < 512; i = i + 1) begin
main_ram.ram[i] = 0;
end
end
wire rom_stb_i;
wire rom_we_i;
wire [15:0] rom_adr_i;
wire [7:0] rom_dat_i;
wire rom_ack_o;
wire [7:0] rom_dat_o;
wb_ram #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(9),
.WB_ALWAYS_READ(1),
.RAM_DEPTH(512)
) main_rom (
.clk_i(clock),
.rst_i(reset),
.stb_i(rom_stb_i),
.we_i(rom_we_i),
.adr_i(rom_adr_i),
.dat_i(rom_dat_i),
.ack_o(rom_ack_o),
.dat_o(rom_dat_o)
);
integer j;
initial begin
for (j = 0; j < 512; j = j + 1) begin
main_rom.ram[j] = 0;
end
main_rom.ram[0] = 8'ha9;
main_rom.ram[1] = 8'hff;
main_rom.ram[2] = 8'h8d;
main_rom.ram[3] = 8'h00;
main_rom.ram[4] = 8'hf0;
main_rom.ram[5] = 8'ha9;
main_rom.ram[6] = 8'h01;
main_rom.ram[7] = 8'hee;
main_rom.ram[8] = 8'h02;
main_rom.ram[9] = 8'hf0;
main_rom.ram[10] = 8'h4c;
main_rom.ram[11] = 8'h07;
main_rom.ram[12] = 8'hfe;
main_rom.ram[9'h1fe] = 8'h00;
main_rom.ram[9'h1ff] = 8'hfe;
end
wire via_stb_i;
wire via_we_i;
wire [15:0] via_adr_i;
wire [7:0] via_dat_i;
wire via_ack_o;
wire [7:0] via_dat_o;
wb_6522_via #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(4)
) wb_6522_via_inst (
.clk_i(clock),
.rst_i(reset),
.stb_i(via_stb_i),
.we_i(via_we_i),
.adr_i(via_adr_i),
.dat_i(via_dat_i),
.ack_o(via_ack_o),
.dat_o(via_dat_o),
.port_a(port_a),
.port_b(port_b)
);
wire portb_stb_i;
wire portb_we_i;
wire [15:0] portb_adr_i;
wire [7:0] portb_dat_i;
wire portb_ack_o;
wire [7:0] portb_dat_o;
wb_gpio #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(2)
) portb_inst (
.clk_i(clock),
.rst_i(reset),
.stb_i(portb_stb_i),
.we_i(portb_we_i),
.adr_i(portb_adr_i),
.dat_i(portb_dat_i),
.ack_o(portb_ack_o),
.dat_o(portb_dat_o),
.gpio(portb)
);
wb_bus #(
.WB_DATA_WIDTH(8),
.WB_ADDR_WIDTH(16),
.WB_NUM_SLAVES(4)
) bus (
.clk_i(clock),
.rst_i(reset),
.mstr_stb_i(cpu_stb_o),
.mstr_we_i(cpu_we_o),
.mstr_adr_i(cpu_adr_o),
.mstr_dat_i(cpu_dat_o),
.mstr_ack_o(cpu_ack_i),
.mstr_dat_o(cpu_dat_i),
.bus_slv_addr_decode_value({16'h0000, 16'hFE00, 16'hF000, 16'hF004}),
.bus_slv_addr_decode_mask ({16'hFE00, 16'hFE00, 16'hFFFC, 16'hFFFC}),
.slv_stb_o ({ram_stb_i, rom_stb_i, porta_stb_i, portb_stb_i}),
.slv_we_o ({ram_we_i, rom_we_i, porta_we_i, portb_we_i}),
.slv_adr_o ({ram_adr_i, rom_adr_i, porta_adr_i, portb_adr_i}),
.slv_dat_o ({ram_dat_i, rom_dat_i, porta_dat_i, portb_dat_i}),
.slv_ack_i ({ram_ack_o, rom_ack_o, porta_ack_o, portb_ack_o}),
.slv_dat_i ({ram_dat_o, rom_dat_o, porta_dat_o, portb_dat_o})
);
endmodule | 17 |
3,454 | data/full_repos/permissive/104667535/verilog/mcu.v | 104,667,535 | mcu.v | v | 304 | 89 | [] | [] | [] | [(3, 267), (269, 303)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:284: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:288: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104667535/verilog/mcu.v:295: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/104667535/verilog/mcu.v:301: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,165 | module | module mcu_test;
reg clock;
reg reset;
wire [7:0] porta;
wire [7:0] portb;
mcu dut(
.clock(clock),
.reset(reset),
.porta(porta),
.portb(portb)
);
initial begin
clock <= 0;
#100;
while (1) begin
clock <= !clock;
#100;
end
end
initial begin
reset <= 1;
#1000;
reset <= 0;
end
initial begin
$dumpvars;
end
endmodule | module mcu_test; |
reg clock;
reg reset;
wire [7:0] porta;
wire [7:0] portb;
mcu dut(
.clock(clock),
.reset(reset),
.porta(porta),
.portb(portb)
);
initial begin
clock <= 0;
#100;
while (1) begin
clock <= !clock;
#100;
end
end
initial begin
reset <= 1;
#1000;
reset <= 0;
end
initial begin
$dumpvars;
end
endmodule | 17 |
3,459 | data/full_repos/permissive/104667535/verilog/wb_gpio.v | 104,667,535 | wb_gpio.v | v | 81 | 90 | [] | [] | [] | null | None: at end of input | data/verilator_xmls/9636e544-5437-4d2e-818e-ec5a2d13f4c2.xml | null | 1,169 | module | module wb_gpio #(
parameter WB_DATA_WIDTH = 8,
parameter WB_ADDR_WIDTH = 2
) (
input clk_i,
input rst_i,
input stb_i,
input we_i,
input [WB_ADDR_WIDTH-1:0] adr_i,
input [WB_DATA_WIDTH-1:0] dat_i,
output reg ack_o,
output reg [WB_DATA_WIDTH-1:0] dat_o,
inout [WB_DATA_WIDTH-1:0] gpio
);
initial ack_o = 0;
initial dat_o = 0;
reg [WB_DATA_WIDTH-1:0] data_direction_register = 0;
reg [WB_DATA_WIDTH-1:0] input_data_register = 0;
reg [WB_DATA_WIDTH-1:0] output_data_register = 0;
wire valid_cmd = !rst_i && stb_i;
wire valid_write_cmd = valid_cmd && we_i;
wire valid_read_cmd = valid_cmd && !we_i;
always @(posedge clk_i) begin
input_data_register <= gpio;
if (valid_read_cmd) begin
case (adr_i)
0: begin
dat_o <= data_direction_register;
end
1: begin
dat_o <= input_data_register;
end
2: begin
dat_o <= output_data_register;
end
endcase
end
if (valid_write_cmd) begin
case (adr_i)
0: begin
data_direction_register <= dat_i;
end
2: begin
output_data_register <= dat_i;
end
endcase
end
ack_o <= valid_cmd;
end
genvar i;
generate
for (i = 0; i < WB_DATA_WIDTH; i = i + 1) begin
assign gpio[i] = data_direction_register[i] ? output_data_register[i] : 1'bz;
end
endgenerate
endmodule | module wb_gpio #(
parameter WB_DATA_WIDTH = 8,
parameter WB_ADDR_WIDTH = 2
) (
input clk_i,
input rst_i,
input stb_i,
input we_i,
input [WB_ADDR_WIDTH-1:0] adr_i,
input [WB_DATA_WIDTH-1:0] dat_i,
output reg ack_o,
output reg [WB_DATA_WIDTH-1:0] dat_o,
inout [WB_DATA_WIDTH-1:0] gpio
); |
initial ack_o = 0;
initial dat_o = 0;
reg [WB_DATA_WIDTH-1:0] data_direction_register = 0;
reg [WB_DATA_WIDTH-1:0] input_data_register = 0;
reg [WB_DATA_WIDTH-1:0] output_data_register = 0;
wire valid_cmd = !rst_i && stb_i;
wire valid_write_cmd = valid_cmd && we_i;
wire valid_read_cmd = valid_cmd && !we_i;
always @(posedge clk_i) begin
input_data_register <= gpio;
if (valid_read_cmd) begin
case (adr_i)
0: begin
dat_o <= data_direction_register;
end
1: begin
dat_o <= input_data_register;
end
2: begin
dat_o <= output_data_register;
end
endcase
end
if (valid_write_cmd) begin
case (adr_i)
0: begin
data_direction_register <= dat_i;
end
2: begin
output_data_register <= dat_i;
end
endcase
end
ack_o <= valid_cmd;
end
genvar i;
generate
for (i = 0; i < WB_DATA_WIDTH; i = i + 1) begin
assign gpio[i] = data_direction_register[i] ? output_data_register[i] : 1'bz;
end
endgenerate
endmodule | 17 |
3,460 | data/full_repos/permissive/104667535/verilog/wb_ram.v | 104,667,535 | wb_ram.v | v | 40 | 52 | [] | [] | [] | [(4, 39)] | null | data/verilator_xmls/f2aed7b5-6e51-4200-a346-a25cd48f177c.xml | null | 1,170 | module | module wb_ram #(
parameter WB_DATA_WIDTH = 8,
parameter WB_ADDR_WIDTH = 9,
parameter WB_ALWAYS_READ = 1,
parameter RAM_DEPTH = 512
) (
input clk_i,
input rst_i,
input stb_i,
input we_i,
input [WB_ADDR_WIDTH-1:0] adr_i,
input [WB_DATA_WIDTH-1:0] dat_i,
output reg ack_o,
output reg [WB_DATA_WIDTH-1:0] dat_o
);
reg [WB_DATA_WIDTH-1:0] ram [RAM_DEPTH-1:0];
wire valid_cmd = !rst_i && stb_i;
wire valid_write_cmd = valid_cmd && we_i;
wire valid_read_cmd = valid_cmd && !we_i;
always @(posedge clk_i) begin
if (valid_read_cmd || WB_ALWAYS_READ) begin
dat_o <= ram[adr_i];
end
if (valid_write_cmd) begin
ram[adr_i] <= dat_i;
end
ack_o <= valid_cmd;
end
endmodule | module wb_ram #(
parameter WB_DATA_WIDTH = 8,
parameter WB_ADDR_WIDTH = 9,
parameter WB_ALWAYS_READ = 1,
parameter RAM_DEPTH = 512
) (
input clk_i,
input rst_i,
input stb_i,
input we_i,
input [WB_ADDR_WIDTH-1:0] adr_i,
input [WB_DATA_WIDTH-1:0] dat_i,
output reg ack_o,
output reg [WB_DATA_WIDTH-1:0] dat_o
); |
reg [WB_DATA_WIDTH-1:0] ram [RAM_DEPTH-1:0];
wire valid_cmd = !rst_i && stb_i;
wire valid_write_cmd = valid_cmd && we_i;
wire valid_read_cmd = valid_cmd && !we_i;
always @(posedge clk_i) begin
if (valid_read_cmd || WB_ALWAYS_READ) begin
dat_o <= ram[adr_i];
end
if (valid_write_cmd) begin
ram[adr_i] <= dat_i;
end
ack_o <= valid_cmd;
end
endmodule | 17 |
3,461 | data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v | 104,784,866 | CBox.v | v | 152 | 138 | [] | [] | [] | [(50, 151)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v:117: Cannot find file containing module: 'FromChannelBusToCLBJunction'\n FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction\n data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction.v\n data/full_repos/permissive/104784866/CBox/Verilog/src,data/full_repos/permissive/104784866/FromChannelBusToCLBJunction.sv\n FromChannelBusToCLBJunction\n FromChannelBusToCLBJunction.v\n FromChannelBusToCLBJunction.sv\n obj_dir/FromChannelBusToCLBJunction\n obj_dir/FromChannelBusToCLBJunction.v\n obj_dir/FromChannelBusToCLBJunction.sv\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox.v:130: Cannot find file containing module: 'FromCLBToChannelBusJunction'\n FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,173 | module | module CBox#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter CLB_IN_WIDTH = 2,
parameter CLB_OUT_WIDTH = 2,
parameter CLB_WIDTH_WIDTH = 2,
parameter UID_WIDTH = 16,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
clb_in,
clb_out
);
parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))+CLB_WIDTH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
output [CLB_IN_WIDTH-1:0] clb_in;
input [CLB_OUT_WIDTH-1:0] clb_out;
wire [CH_UP_WIDTH-1:0] w_ch_up [0:CLB_OUT_WIDTH];
wire [CH_DN_WIDTH-1:0] w_ch_dn [0:CLB_OUT_WIDTH];
genvar i;
generate
for(i = 0; i < CLB_IN_WIDTH; i = i+1) begin : FromChannelBusToCLBJunctionGen
wire filteredClk = c_clk && (i == `C_BUS_JN_ADDR) && (UID == c_uid);
FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
.c_dimension(c_dimension),
.ch({ch_dn_n, w_ch_up[0]}),
.clb_in(clb_in[i])
);
end
for(i = 0; i < CLB_OUT_WIDTH; i = i+1) begin : FromCLBToChannelBusJunctionGen
wire filteredClk = c_clk && ((i + CLB_IN_WIDTH) == `C_BUS_JN_ADDR) && (UID == c_uid);
FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
.c_dimension(c_dimension),
.ch_up_n(w_ch_up[i]),
.ch_up_s(w_ch_up[i+1]),
.ch_dn_n(w_ch_dn[i]),
.ch_dn_s(w_ch_dn[i+1]),
.clb_out(clb_out[i])
);
end
endgenerate
assign ch_up_n = w_ch_up[0];
assign w_ch_up[CLB_OUT_WIDTH] = ch_up_s;
assign w_ch_dn[0] = ch_dn_n;
assign ch_dn_s = w_ch_dn[CLB_OUT_WIDTH];
endmodule | module CBox#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter CLB_IN_WIDTH = 2,
parameter CLB_OUT_WIDTH = 2,
parameter CLB_WIDTH_WIDTH = 2,
parameter UID_WIDTH = 16,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
clb_in,
clb_out
); |
parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))+CLB_WIDTH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
output [CLB_IN_WIDTH-1:0] clb_in;
input [CLB_OUT_WIDTH-1:0] clb_out;
wire [CH_UP_WIDTH-1:0] w_ch_up [0:CLB_OUT_WIDTH];
wire [CH_DN_WIDTH-1:0] w_ch_dn [0:CLB_OUT_WIDTH];
genvar i;
generate
for(i = 0; i < CLB_IN_WIDTH; i = i+1) begin : FromChannelBusToCLBJunctionGen
wire filteredClk = c_clk && (i == `C_BUS_JN_ADDR) && (UID == c_uid);
FromChannelBusToCLBJunction#(DIMENSION, CH_UP_WIDTH + CH_DN_WIDTH, DIMENSION_WIDTH) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
.c_dimension(c_dimension),
.ch({ch_dn_n, w_ch_up[0]}),
.clb_in(clb_in[i])
);
end
for(i = 0; i < CLB_OUT_WIDTH; i = i+1) begin : FromCLBToChannelBusJunctionGen
wire filteredClk = c_clk && ((i + CLB_IN_WIDTH) == `C_BUS_JN_ADDR) && (UID == c_uid);
FromCLBToChannelBusJunction#(DIMENSION, CH_UP_WIDTH, CH_DN_WIDTH, DIMENSION_WIDTH) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus({`C_BUS_CLB_DN_JUNCTION, `C_BUS_CLB_UP_JUNCTION}),
.c_dimension(c_dimension),
.ch_up_n(w_ch_up[i]),
.ch_up_s(w_ch_up[i+1]),
.ch_dn_n(w_ch_dn[i]),
.ch_dn_s(w_ch_dn[i+1]),
.clb_out(clb_out[i])
);
end
endgenerate
assign ch_up_n = w_ch_up[0];
assign w_ch_up[CLB_OUT_WIDTH] = ch_up_s;
assign w_ch_dn[0] = ch_dn_n;
assign ch_dn_s = w_ch_dn[CLB_OUT_WIDTH];
endmodule | 0 |
3,462 | data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v | 104,784,866 | CBox_tb.v | v | 262 | 126 | [] | [] | [] | null | line:94: before: "@" | null | 1: b'%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:85: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("CBox_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:86: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:94: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:98: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:104: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:110: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:116: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:122: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:126: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:130: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:135: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:140: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:145: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:152: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:156: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:160: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:164: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:169: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:169: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:174: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:179: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:186: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:190: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:194: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:198: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:198: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:203: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:208: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:213: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:220: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:220: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:224: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:228: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:232: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:237: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:242: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:247: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:247: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:252: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:252: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/CBox_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n #50 r_clk <= ~r_clk;\n ^\n%Error: Exiting due to 35 error(s), 34 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,174 | module | module CBox_tb;
reg r_clk;
reg r_mode;
reg [17:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg [1:0] r_clb_out;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
wire [1:0] w_clb_in;
CBox#(0, 4, 2, 2, 2, 2, 2, 16, 2) inst(
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.clb_in(w_clb_in),
.clb_out(r_clb_out)
);
initial begin
$dumpfile("CBox_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_clb_out <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {2'h0, 16'h0330};
#50 @(posedge r_clk);
r_c_bus <= {2'h1, 16'h0200};
#50 @(posedge r_clk);
r_c_bus <= {2'h2, 8'b00100000, 8'b00001000};
#50 @(posedge r_clk);
r_c_bus <= {2'h3, 8'b00000011, 8'b00000111};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h3;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | module CBox_tb; |
reg r_clk;
reg r_mode;
reg [17:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg [1:0] r_clb_out;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
wire [1:0] w_clb_in;
CBox#(0, 4, 2, 2, 2, 2, 2, 16, 2) inst(
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.clb_in(w_clb_in),
.clb_out(r_clb_out)
);
initial begin
$dumpfile("CBox_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, w_clb_in, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_clb_out <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {2'h0, 16'h0330};
#50 @(posedge r_clk);
r_c_bus <= {2'h1, 16'h0200};
#50 @(posedge r_clk);
r_c_bus <= {2'h2, 8'b00100000, 8'b00001000};
#50 @(posedge r_clk);
r_c_bus <= {2'h3, 8'b00000011, 8'b00000111};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h3;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_clb_out <= 'h0;
#50 @(posedge r_clk);
r_clb_out <= 'h1;
#50 @(posedge r_clk);
r_clb_out <= 'h2;
#50 @(posedge r_clk);
r_clb_out <= 'h3;
#50 @(posedge r_clk);
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | 0 |
3,463 | data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction.v | 104,784,866 | FromChannelBusToCLBJunction.v | v | 121 | 117 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/01710d08-7445-4e8f-911e-2f2deeec6d8f.xml | null | 1,175 | module | module FromChannelBusToCLBJunction#(
parameter DIMENSION = 4,
parameter CH_WIDTH = 4,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_dimension,
ch,
clb_in
);
parameter CONFIG_WORD_WIDTH = DIMENSION*CH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [CH_WIDTH-1:0] ch;
output clb_in;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_CLB_JUNCTION = `C_BUS_CLB_JUNCTION;
end
end
assign clb_in = ch[(`CONFIGREG_CLB_JUNCTION >> (c_dimension * CH_WIDTH)) & (CH_WIDTH - 1)];
endmodule | module FromChannelBusToCLBJunction#(
parameter DIMENSION = 4,
parameter CH_WIDTH = 4,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_dimension,
ch,
clb_in
); |
parameter CONFIG_WORD_WIDTH = DIMENSION*CH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [CH_WIDTH-1:0] ch;
output clb_in;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_CLB_JUNCTION = `C_BUS_CLB_JUNCTION;
end
end
assign clb_in = ch[(`CONFIGREG_CLB_JUNCTION >> (c_dimension * CH_WIDTH)) & (CH_WIDTH - 1)];
endmodule | 0 |
3,464 | data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v | 104,784,866 | FromChannelBusToCLBJunction_tb.v | v | 179 | 119 | [] | [] | [] | null | line:73: before: "@" | null | 1: b'%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:64: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("FromChannelBusToCLBJunction_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:65: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, w_clb_in, inst);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:73: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:78: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:81: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:86: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:90: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:95: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:99: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:104: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:108: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:112: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:117: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:121: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:126: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:130: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:134: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:139: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:143: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:148: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:152: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:156: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:161: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:165: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:170: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromChannelBusToCLBJunction_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #50 r_clk <= ~r_clk;\n ^\n%Error: Exiting due to 25 error(s), 24 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,176 | module | module FromChannelBusToCLBJunction_tb;
reg r_clk;
reg r_mode;
reg [16:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
wire w_clb_in;
FromChannelBusToCLBJunction#(4, 4, 2) inst(
.mode(r_mode),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch({r_ch_dn_n, r_ch_up_s}),
.clb_in(w_clb_in)
);
initial begin
$dumpfile("FromChannelBusToCLBJunction_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, w_clb_in, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h0;
r_ch_dn_n <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 16'h3210};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 16'h3210};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 16'h3210};
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b01;
r_ch_dn_n <= 'b00;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h1;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b10;
r_ch_dn_n <= 'b00;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h2;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b01;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b01;
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | module FromChannelBusToCLBJunction_tb; |
reg r_clk;
reg r_mode;
reg [16:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
wire w_clb_in;
FromChannelBusToCLBJunction#(4, 4, 2) inst(
.mode(r_mode),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch({r_ch_dn_n, r_ch_up_s}),
.clb_in(w_clb_in)
);
initial begin
$dumpfile("FromChannelBusToCLBJunction_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, w_clb_in, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h0;
r_ch_dn_n <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 16'h3210};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 16'h3210};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 16'h3210};
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b01;
r_ch_dn_n <= 'b00;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h1;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b10;
r_ch_dn_n <= 'b00;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h2;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b01;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b00;
#50 @(posedge r_clk);
r_ch_up_s <= 'b00;
r_ch_dn_n <= 'b01;
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | 0 |
3,465 | data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v | 104,784,866 | FromCLBToChannelBusJunction.v | v | 133 | 152 | [] | [] | [] | [(69, 132)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v:125: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 8 bits.\n : ... In instance FromCLBToChannelBusJunction\n assign ch_up_n[i] = ((configReg[(DIMENSION*CH_UP_WIDTH)-1:0] >> ((c_dimension * CH_UP_WIDTH) + i)) & \'b1)? clb_out : ch_up_s[i];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction.v:128: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 32 or 8 bits.\n : ... In instance FromCLBToChannelBusJunction\n assign ch_dn_s[i] = ((configReg[(DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH))-1:(DIMENSION*CH_UP_WIDTH)] >> ((c_dimension * CH_DN_WIDTH) + i)) & \'b1)? clb_out : ch_dn_n[i];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,177 | module | module FromCLBToChannelBusJunction#(
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
clb_out
);
parameter CONFIG_WORD_WIDTH = DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH);
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
input clb_out;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_CLB_UP_JUNCTION = `C_BUS_CLB_UP_JUNCTION;
`CONFIGREG_CLB_DN_JUNCTION = `C_BUS_CLB_DN_JUNCTION;
end
end
genvar i;
generate
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : ch_up_nGen
assign ch_up_n[i] = ((`CONFIGREG_CLB_UP_JUNCTION >> ((c_dimension * CH_UP_WIDTH) + i)) & 'b1)? clb_out : ch_up_s[i];
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : ch_dn_sGen
assign ch_dn_s[i] = ((`CONFIGREG_CLB_DN_JUNCTION >> ((c_dimension * CH_DN_WIDTH) + i)) & 'b1)? clb_out : ch_dn_n[i];
end
endgenerate
endmodule | module FromCLBToChannelBusJunction#(
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter DIMENSION_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
clb_out
); |
parameter CONFIG_WORD_WIDTH = DIMENSION*(CH_UP_WIDTH+CH_DN_WIDTH);
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
input clb_out;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_CLB_UP_JUNCTION = `C_BUS_CLB_UP_JUNCTION;
`CONFIGREG_CLB_DN_JUNCTION = `C_BUS_CLB_DN_JUNCTION;
end
end
genvar i;
generate
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : ch_up_nGen
assign ch_up_n[i] = ((`CONFIGREG_CLB_UP_JUNCTION >> ((c_dimension * CH_UP_WIDTH) + i)) & 'b1)? clb_out : ch_up_s[i];
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : ch_dn_sGen
assign ch_dn_s[i] = ((`CONFIGREG_CLB_DN_JUNCTION >> ((c_dimension * CH_DN_WIDTH) + i)) & 'b1)? clb_out : ch_dn_n[i];
end
endgenerate
endmodule | 0 |
3,466 | data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v | 104,784,866 | FromCLBToChannelBusJunction_tb.v | v | 184 | 116 | [] | [] | [] | null | line:78: before: "@" | null | 1: b'%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("FromCLBToChannelBusJunction_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:78: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:83: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:86: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:91: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:95: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:100: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:104: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:109: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:113: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:117: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:122: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:126: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:131: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:135: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:139: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:144: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:148: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:153: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:157: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:161: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:166: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:170: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:175: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CBox/Verilog/src/FromCLBToChannelBusJunction_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #50 r_clk <= ~r_clk;\n ^\n%Error: Exiting due to 25 error(s), 24 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,178 | module | module FromCLBToChannelBusJunction_tb;
reg r_clk;
reg r_mode;
reg [16:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg r_clb_out;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
FromCLBToChannelBusJunction#(4, 2, 2, 2) inst(
.mode(r_mode),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.clb_out(r_clb_out)
);
initial begin
$dumpfile("FromCLBToChannelBusJunction_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_clb_out <= 'b0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 8'b10000011, 8'b10000111};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h1;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h2;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | module FromCLBToChannelBusJunction_tb; |
reg r_clk;
reg r_mode;
reg [16:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg r_clb_out;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
FromCLBToChannelBusJunction#(4, 2, 2, 2) inst(
.mode(r_mode),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.clb_out(r_clb_out)
);
initial begin
$dumpfile("FromCLBToChannelBusJunction_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_clb_out, w_ch_up_n, w_ch_dn_s, inst);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_clb_out <= 'b0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 8'b10000011, 8'b10000111};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 8'b10000011, 8'b10000111};
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h1;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h2;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#100 @(posedge r_clk);
r_mode <= 'b1;
#50@(posedge r_clk);
r_c_dimension <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b0;
#50 @(posedge r_clk);
r_clb_out <= 'b1;
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | 0 |
3,467 | data/full_repos/permissive/104784866/CLB/Verilog/src/AsyncRAM.v | 104,784,866 | AsyncRAM.v | v | 55 | 100 | [] | [] | [] | [(26, 54)] | null | data/verilator_xmls/e52a8eed-7e58-4182-b656-6ff0e8222691.xml | null | 1,179 | module | module AsyncRAM#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 4
) (
clk,
addr,
rw,
data_in,
data_out
);
input clk;
input [ADDR_WIDTH-1:0] addr;
input rw;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
(* ramstyle = "MLAB, no_rw_check" *)
reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];
assign data_out = mem[addr];
always @(posedge clk) begin
if(rw)
mem[addr] = data_in;
end
endmodule | module AsyncRAM#(
parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 4
) (
clk,
addr,
rw,
data_in,
data_out
); |
input clk;
input [ADDR_WIDTH-1:0] addr;
input rw;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
(* ramstyle = "MLAB, no_rw_check" *)
reg [DATA_WIDTH-1:0] mem [0:(1 << ADDR_WIDTH)-1];
assign data_out = mem[addr];
always @(posedge clk) begin
if(rw)
mem[addr] = data_in;
end
endmodule | 0 |
3,468 | data/full_repos/permissive/104784866/CLB/Verilog/src/CLB.v | 104,784,866 | CLB.v | v | 132 | 101 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB.v:98: Cannot find file containing module: 'AsyncRAM'\n AsyncRAM#(LUT_WIDTH, DIMENSION) lut (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM\n data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM.v\n data/full_repos/permissive/104784866/CLB/Verilog/src,data/full_repos/permissive/104784866/AsyncRAM.sv\n AsyncRAM\n AsyncRAM.v\n AsyncRAM.sv\n obj_dir/AsyncRAM\n obj_dir/AsyncRAM.v\n obj_dir/AsyncRAM.sv\n%Error: Exiting due to 1 error(s)\n" | 1,180 | module | module CLB#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter UID_WIDTH = 16,
parameter LUT_WIDTH = 4,
parameter DIMENSION_WIDTH = 2
) (
clk,
clk_en,
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
b_in,
b_out
);
parameter CONFIG_WORD_WIDTH = DIMENSION + LUT_WIDTH + 2;
input clk;
input clk_en;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [LUT_WIDTH-1:0] b_in;
output b_out;
wire w_lut_clk;
wire [LUT_WIDTH-1:0] w_lut_addr;
wire w_lut_rw;
wire [DIMENSION-1:0] w_lut_data_in;
wire [DIMENSION-1:0] w_lut_data_out;
reg [DIMENSION-1:0] configReg;
reg registeredOutput;
AsyncRAM#(LUT_WIDTH, DIMENSION) lut (
.clk(w_lut_clk),
.addr(w_lut_addr),
.rw(w_lut_rw),
.data_in(w_lut_data_in),
.data_out(w_lut_data_out)
);
assign w_lut_clk = c_clk;
assign w_lut_addr = mode? `C_BUS_LUT_ADDR : b_in;
assign w_lut_rw = mode && `C_BUS_RAM_WRITE && (UID == c_uid);
assign w_lut_data_in = `C_BUS_LUT_DATA;
assign b_out = (`CONFIGREG_OUTPUTTYPESELECTOR_DIM)? registeredOutput : w_lut_data_out[c_dimension];
always @(posedge c_clk) begin
if(mode && `C_BUS_REG_WRITE && (UID == c_uid)) begin
`CONFIGREG_OUTPUTTYPESELECTOR_FULL = `C_BUS_OUTPUTTYPESELECTOR;
end
end
always @(posedge clk or posedge mode) begin
if(mode) begin
registeredOutput <= 'b0;
end
else if(clk_en) begin
registeredOutput <= w_lut_data_out[c_dimension];
end
end
endmodule | module CLB#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter UID_WIDTH = 16,
parameter LUT_WIDTH = 4,
parameter DIMENSION_WIDTH = 2
) (
clk,
clk_en,
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
b_in,
b_out
); |
parameter CONFIG_WORD_WIDTH = DIMENSION + LUT_WIDTH + 2;
input clk;
input clk_en;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [LUT_WIDTH-1:0] b_in;
output b_out;
wire w_lut_clk;
wire [LUT_WIDTH-1:0] w_lut_addr;
wire w_lut_rw;
wire [DIMENSION-1:0] w_lut_data_in;
wire [DIMENSION-1:0] w_lut_data_out;
reg [DIMENSION-1:0] configReg;
reg registeredOutput;
AsyncRAM#(LUT_WIDTH, DIMENSION) lut (
.clk(w_lut_clk),
.addr(w_lut_addr),
.rw(w_lut_rw),
.data_in(w_lut_data_in),
.data_out(w_lut_data_out)
);
assign w_lut_clk = c_clk;
assign w_lut_addr = mode? `C_BUS_LUT_ADDR : b_in;
assign w_lut_rw = mode && `C_BUS_RAM_WRITE && (UID == c_uid);
assign w_lut_data_in = `C_BUS_LUT_DATA;
assign b_out = (`CONFIGREG_OUTPUTTYPESELECTOR_DIM)? registeredOutput : w_lut_data_out[c_dimension];
always @(posedge c_clk) begin
if(mode && `C_BUS_REG_WRITE && (UID == c_uid)) begin
`CONFIGREG_OUTPUTTYPESELECTOR_FULL = `C_BUS_OUTPUTTYPESELECTOR;
end
end
always @(posedge clk or posedge mode) begin
if(mode) begin
registeredOutput <= 'b0;
end
else if(clk_en) begin
registeredOutput <= w_lut_data_out[c_dimension];
end
end
endmodule | 0 |
3,469 | data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v | 104,784,866 | CLB_tb.v | v | 225 | 100 | [] | [] | [] | null | line:59: before: "@" | null | 1: b'%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("CLB_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:59: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:63: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:67: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:70: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:73: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:76: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:79: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:83: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:87: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:90: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:93: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:96: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:101: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:105: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:109: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:113: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:116: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:119: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:122: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:127: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:131: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:135: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:139: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:142: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:145: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:148: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:153: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:157: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:161: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:165: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:168: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:171: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:174: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:179: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:179: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:183: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:187: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:187: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:191: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:191: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:194: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:197: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:200: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:203: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:206: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:209: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:212: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:212: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:215: syntax error, unexpected \'@\'\n #200 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:215: Unsupported: Ignoring delay on this delayed statement.\n #200 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/CLB/Verilog/src/CLB_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n #50 r_clk <= ~r_clk;\n ^\n%Error: Exiting due to 47 error(s), 46 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,181 | module | module CLB_tb;
reg r_clk;
reg r_clk_en;
reg r_mode;
reg [7:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_b_in;
wire w_b_out;
CLB#(0, 4, 1, 2, 2) inst (
.clk(r_clk),
.clk_en(r_clk_en),
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_uid(1'b0),
.c_dimension(r_c_dimension),
.b_in(r_b_in),
.b_out(w_b_out)
);
initial begin
$dumpfile("CLB_tb.vcd");
$dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);
r_clk <= 'b1;
r_clk_en <= 'b0;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_b_in <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h0, 4'h1};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h1, 4'hd};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h2, 4'hd};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h3, 4'hb};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 1'b0, 2'h0, 4'h4};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_clk_en <= 'b1;
#50 @(posedge r_clk);
r_clk_en <= 'b0;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_clk_en <= 'b1;
#50 @(posedge r_clk);
r_clk_en <= 'b0;
#50 @(posedge r_clk);
#200 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | module CLB_tb; |
reg r_clk;
reg r_clk_en;
reg r_mode;
reg [7:0] r_c_bus;
reg [1:0] r_c_dimension;
reg [1:0] r_b_in;
wire w_b_out;
CLB#(0, 4, 1, 2, 2) inst (
.clk(r_clk),
.clk_en(r_clk_en),
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_uid(1'b0),
.c_dimension(r_c_dimension),
.b_in(r_b_in),
.b_out(w_b_out)
);
initial begin
$dumpfile("CLB_tb.vcd");
$dumpvars(1, r_clk, r_clk_en, r_mode, r_c_bus, r_c_dimension, r_b_in, w_b_out, inst);
r_clk <= 'b1;
r_clk_en <= 'b0;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'h0;
r_b_in <= 'h0;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h0, 4'h1};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h1, 4'hd};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h2, 4'hd};
#50 @(posedge r_clk);
r_c_bus <= {1'b0, 1'b1, 2'h3, 4'hb};
#50 @(posedge r_clk);
r_c_bus <= {1'b1, 1'b0, 2'h0, 4'h4};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h2;
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_b_in <= 'h0;
#50 @(posedge r_clk);
r_b_in <= 'h1;
#50 @(posedge r_clk);
r_clk_en <= 'b1;
#50 @(posedge r_clk);
r_clk_en <= 'b0;
#50 @(posedge r_clk);
r_b_in <= 'h2;
#50 @(posedge r_clk);
r_b_in <= 'h3;
#50 @(posedge r_clk);
r_clk_en <= 'b1;
#50 @(posedge r_clk);
r_clk_en <= 'b0;
#50 @(posedge r_clk);
#200 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | 0 |
3,470 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2/TOP.v | 104,784,866 | TOP.v | v | 71 | 66 | [] | [] | [] | [(1, 70)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2/TOP.v:29: Cannot find file containing module: 'NovaCOREBlaster'\n NovaCOREBlaster blaster(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2,data/full_repos/permissive/104784866/NovaCOREBlaster\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2,data/full_repos/permissive/104784866/NovaCOREBlaster.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2,data/full_repos/permissive/104784866/NovaCOREBlaster.sv\n NovaCOREBlaster\n NovaCOREBlaster.v\n NovaCOREBlaster.sv\n obj_dir/NovaCOREBlaster\n obj_dir/NovaCOREBlaster.v\n obj_dir/NovaCOREBlaster.sv\n%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2/TOP.v:41: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(4, 2, 4, 2, 2, 2, 1, 4) fpga(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 1,183 | module | module TOP(
clkin_50,
user_pb,
user_led
);
input clkin_50;
input [2:0] user_pb;
output [15:0] user_led;
wire w_mode;
wire [27:0] w_c_bus;
wire [3:0] w_c_uid;
wire w_c_clk;
wire [3:0] w_c_dimension;
wire w_c_dimswitch;
wire [7:0] w_user_led_n;
wire [1:0] w_user_pb_n;
reg [31:0] counter;
assign user_led[7:0] = {4'hf, ~counter[27:26], ~counter[27:26]};
assign user_led[15:8] = ~w_user_led_n;
assign w_user_pb_n = ~user_pb[2:1];
NovaCOREBlaster blaster(
.clk_clk(clkin_50),
.reset_reset_n(user_pb[0]),
.mode_export(w_mode),
.c_bus_export(w_c_bus),
.c_uid_export(w_c_uid),
.c_clk_export(w_c_clk),
.c_dimension_export(w_c_dimension),
.c_dimswitch_export(w_c_dimswitch)
);
NovaCORE#(4, 2, 4, 2, 2, 2, 1, 4) fpga(
.clk(clkin_50),
.mode(w_mode),
.c_clk(w_c_clk),
.c_bus(w_c_bus),
.c_uid(w_c_uid),
.c_dimension(w_c_dimension),
.c_dimswitch(w_c_dimswitch),
.io_up_n(),
.io_up_s(),
.io_dn_n({w_user_pb_n, 2'b11}),
.io_dn_s(),
.io_lt_n(w_user_led_n[7:4]),
.io_lt_s(),
.io_rt_n({counter[27:26], counter[27:26]}),
.io_rt_s(w_user_led_n[3:0])
);
always @(posedge clkin_50 or negedge user_pb[0]) begin
if(!user_pb[0]) begin
counter <= 'h0;
end
else begin
counter <= counter + 'h1;
end
end
endmodule | module TOP(
clkin_50,
user_pb,
user_led
); |
input clkin_50;
input [2:0] user_pb;
output [15:0] user_led;
wire w_mode;
wire [27:0] w_c_bus;
wire [3:0] w_c_uid;
wire w_c_clk;
wire [3:0] w_c_dimension;
wire w_c_dimswitch;
wire [7:0] w_user_led_n;
wire [1:0] w_user_pb_n;
reg [31:0] counter;
assign user_led[7:0] = {4'hf, ~counter[27:26], ~counter[27:26]};
assign user_led[15:8] = ~w_user_led_n;
assign w_user_pb_n = ~user_pb[2:1];
NovaCOREBlaster blaster(
.clk_clk(clkin_50),
.reset_reset_n(user_pb[0]),
.mode_export(w_mode),
.c_bus_export(w_c_bus),
.c_uid_export(w_c_uid),
.c_clk_export(w_c_clk),
.c_dimension_export(w_c_dimension),
.c_dimswitch_export(w_c_dimswitch)
);
NovaCORE#(4, 2, 4, 2, 2, 2, 1, 4) fpga(
.clk(clkin_50),
.mode(w_mode),
.c_clk(w_c_clk),
.c_bus(w_c_bus),
.c_uid(w_c_uid),
.c_dimension(w_c_dimension),
.c_dimswitch(w_c_dimswitch),
.io_up_n(),
.io_up_s(),
.io_dn_n({w_user_pb_n, 2'b11}),
.io_dn_s(),
.io_lt_n(w_user_led_n[7:4]),
.io_lt_s(),
.io_rt_n({counter[27:26], counter[27:26]}),
.io_rt_s(w_user_led_n[3:0])
);
always @(posedge clkin_50 or negedge user_pb[0]) begin
if(!user_pb[0]) begin
counter <= 'h0;
end
else begin
counter <= counter + 'h1;
end
end
endmodule | 0 |
3,471 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Full/2x2/NovaCOREBlaster/NovaCOREBlaster_bb.v | 104,784,866 | NovaCOREBlaster_bb.v | v | 21 | 34 | [] | [] | [] | [(2, 20)] | null | data/verilator_xmls/5b997db6-06d6-4f46-9ba5-117f569a7fd7.xml | null | 1,184 | module | module NovaCOREBlaster (
c_bus_export,
c_clk_export,
c_dimension_export,
c_dimswitch_export,
c_uid_export,
clk_clk,
mode_export,
reset_reset_n);
output [27:0] c_bus_export;
output c_clk_export;
output [3:0] c_dimension_export;
output c_dimswitch_export;
output [3:0] c_uid_export;
input clk_clk;
output mode_export;
input reset_reset_n;
endmodule | module NovaCOREBlaster (
c_bus_export,
c_clk_export,
c_dimension_export,
c_dimswitch_export,
c_uid_export,
clk_clk,
mode_export,
reset_reset_n); |
output [27:0] c_bus_export;
output c_clk_export;
output [3:0] c_dimension_export;
output c_dimswitch_export;
output [3:0] c_uid_export;
input clk_clk;
output mode_export;
input reset_reset_n;
endmodule | 0 |
3,472 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/10x10/TOP.v | 104,784,866 | TOP.v | v | 60 | 43 | [] | [] | [] | [(1, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/10x10/TOP.v:39: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(4, 10, 20, 2, 2, 5, 1, 9) fpga(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/10x10,data/full_repos/permissive/104784866/NovaCORE\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/10x10,data/full_repos/permissive/104784866/NovaCORE.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/10x10,data/full_repos/permissive/104784866/NovaCORE.sv\n NovaCORE\n NovaCORE.v\n NovaCORE.sv\n obj_dir/NovaCORE\n obj_dir/NovaCORE.v\n obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n" | 1,225 | module | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
c_dimension,
c_dimswitch,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
input clk;
input mode;
input [81:0] c_bus;
input [8:0] c_uid;
input c_clk;
input [1:0] c_dimension;
input c_dimswitch;
output [99:0] io_up_n;
input [99:0] io_up_s;
input [99:0] io_dn_n;
output [99:0] io_dn_s;
output [99:0] io_lt_n;
input [99:0] io_lt_s;
input [99:0] io_rt_n;
output [99:0] io_rt_s;
NovaCORE#(4, 10, 20, 2, 2, 5, 1, 9) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.c_dimension(c_dimension),
.c_dimswitch(c_dimswitch),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
c_dimension,
c_dimswitch,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
input clk;
input mode;
input [81:0] c_bus;
input [8:0] c_uid;
input c_clk;
input [1:0] c_dimension;
input c_dimswitch;
output [99:0] io_up_n;
input [99:0] io_up_s;
input [99:0] io_dn_n;
output [99:0] io_dn_s;
output [99:0] io_lt_n;
input [99:0] io_lt_s;
input [99:0] io_rt_n;
output [99:0] io_rt_s;
NovaCORE#(4, 10, 20, 2, 2, 5, 1, 9) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.c_dimension(c_dimension),
.c_dimswitch(c_dimswitch),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | 0 |
3,473 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/2x2_Unidimensional/TOP.v | 104,784,866 | TOP.v | v | 54 | 41 | [] | [] | [] | [(1, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/2x2_Unidimensional/TOP.v:35: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(1, 2, 4, 2, 1, 2, 1, 4) fpga(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/2x2_Unidimensional,data/full_repos/permissive/104784866/NovaCORE\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/2x2_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/2x2_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.sv\n NovaCORE\n NovaCORE.v\n NovaCORE.sv\n obj_dir/NovaCORE\n obj_dir/NovaCORE.v\n obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n" | 1,228 | module | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
input clk;
input mode;
input [17:0] c_bus;
input [3:0] c_uid;
input c_clk;
output [3:0] io_up_n;
input [3:0] io_up_s;
input [3:0] io_dn_n;
output [3:0] io_dn_s;
output [3:0] io_lt_n;
input [3:0] io_lt_s;
input [3:0] io_rt_n;
output [3:0] io_rt_s;
NovaCORE#(1, 2, 4, 2, 1, 2, 1, 4) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
input clk;
input mode;
input [17:0] c_bus;
input [3:0] c_uid;
input c_clk;
output [3:0] io_up_n;
input [3:0] io_up_s;
input [3:0] io_dn_n;
output [3:0] io_dn_s;
output [3:0] io_lt_n;
input [3:0] io_lt_s;
input [3:0] io_rt_n;
output [3:0] io_rt_s;
NovaCORE#(1, 2, 4, 2, 1, 2, 1, 4) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | 0 |
3,474 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional/TOP.v | 104,784,866 | TOP.v | v | 54 | 42 | [] | [] | [] | [(1, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional/TOP.v:35: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/5x5_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.sv\n NovaCORE\n NovaCORE.v\n NovaCORE.sv\n obj_dir/NovaCORE\n obj_dir/NovaCORE.v\n obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n" | 1,230 | module | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
input clk;
input mode;
input [41:0] c_bus;
input [6:0] c_uid;
input c_clk;
output [24:0] io_up_n;
input [24:0] io_up_s;
input [24:0] io_dn_n;
output [24:0] io_dn_s;
output [24:0] io_lt_n;
input [24:0] io_lt_s;
input [24:0] io_rt_n;
output [24:0] io_rt_s;
NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
input clk;
input mode;
input [41:0] c_bus;
input [6:0] c_uid;
input c_clk;
output [24:0] io_up_n;
input [24:0] io_up_s;
input [24:0] io_dn_n;
output [24:0] io_dn_s;
output [24:0] io_lt_n;
input [24:0] io_lt_s;
input [24:0] io_rt_n;
output [24:0] io_rt_s;
NovaCORE#(1, 5, 10, 2, 1, 4, 1, 7) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | 0 |
3,475 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/7x7_Unidimensional/TOP.v | 104,784,866 | TOP.v | v | 54 | 42 | [] | [] | [] | [(1, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/7x7_Unidimensional/TOP.v:35: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(1, 7, 14, 2, 1, 4, 1, 8) fpga(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/7x7_Unidimensional,data/full_repos/permissive/104784866/NovaCORE\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/7x7_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/7x7_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.sv\n NovaCORE\n NovaCORE.v\n NovaCORE.sv\n obj_dir/NovaCORE\n obj_dir/NovaCORE.v\n obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n" | 1,232 | module | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
input clk;
input mode;
input [57:0] c_bus;
input [7:0] c_uid;
input c_clk;
output [48:0] io_up_n;
input [48:0] io_up_s;
input [48:0] io_dn_n;
output [48:0] io_dn_s;
output [48:0] io_lt_n;
input [48:0] io_lt_s;
input [48:0] io_rt_n;
output [48:0] io_rt_s;
NovaCORE#(1, 7, 14, 2, 1, 4, 1, 8) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
input clk;
input mode;
input [57:0] c_bus;
input [7:0] c_uid;
input c_clk;
output [48:0] io_up_n;
input [48:0] io_up_s;
input [48:0] io_dn_n;
output [48:0] io_dn_s;
output [48:0] io_lt_n;
input [48:0] io_lt_s;
input [48:0] io_rt_n;
output [48:0] io_rt_s;
NovaCORE#(1, 7, 14, 2, 1, 4, 1, 8) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | 0 |
3,476 | data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/9x9_Unidimensional/TOP.v | 104,784,866 | TOP.v | v | 54 | 42 | [] | [] | [] | [(1, 53)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/9x9_Unidimensional/TOP.v:35: Cannot find file containing module: 'NovaCORE'\n NovaCORE#(1, 9, 18, 2, 1, 5, 1, 9) fpga(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/9x9_Unidimensional,data/full_repos/permissive/104784866/NovaCORE\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/9x9_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.v\n data/full_repos/permissive/104784866/NovaCORE/Quartus/Standalone/9x9_Unidimensional,data/full_repos/permissive/104784866/NovaCORE.sv\n NovaCORE\n NovaCORE.v\n NovaCORE.sv\n obj_dir/NovaCORE\n obj_dir/NovaCORE.v\n obj_dir/NovaCORE.sv\n%Error: Exiting due to 1 error(s)\n" | 1,234 | module | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
input clk;
input mode;
input [73:0] c_bus;
input [8:0] c_uid;
input c_clk;
output [80:0] io_up_n;
input [80:0] io_up_s;
input [80:0] io_dn_n;
output [80:0] io_dn_s;
output [80:0] io_lt_n;
input [80:0] io_lt_s;
input [80:0] io_rt_n;
output [80:0] io_rt_s;
NovaCORE#(1, 9, 18, 2, 1, 5, 1, 9) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | module TOP(
clk,
mode,
c_bus,
c_uid,
c_clk,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
input clk;
input mode;
input [73:0] c_bus;
input [8:0] c_uid;
input c_clk;
output [80:0] io_up_n;
input [80:0] io_up_s;
input [80:0] io_dn_n;
output [80:0] io_dn_s;
output [80:0] io_lt_n;
input [80:0] io_lt_s;
input [80:0] io_rt_n;
output [80:0] io_rt_s;
NovaCORE#(1, 9, 18, 2, 1, 5, 1, 9) fpga(
.clk(clk),
.mode(mode),
.c_bus(c_bus),
.c_uid(c_uid),
.c_clk(c_clk),
.io_up_n(io_up_n),
.io_up_s(io_up_s),
.io_dn_n(io_dn_n),
.io_dn_s(io_dn_s),
.io_lt_n(io_lt_n),
.io_lt_s(io_lt_s),
.io_rt_n(io_rt_n),
.io_rt_s(io_rt_s)
);
endmodule | 0 |
3,477 | data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v | 104,784,866 | NovaCORE.v | v | 221 | 156 | [] | [] | [] | [(33, 220)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:142: Cannot find file containing module: 'CBox'\n CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(\n ^~~~\n ... Looked in:\n data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox\n data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox.v\n data/full_repos/permissive/104784866/NovaCORE/Verilog/src,data/full_repos/permissive/104784866/CBox.sv\n CBox\n CBox.v\n CBox.sv\n obj_dir/CBox\n obj_dir/CBox.v\n obj_dir/CBox.sv\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:158: Cannot find file containing module: 'SBox'\n SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(\n ^~~~\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:176: Cannot find file containing module: 'CLB'\n CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(\n ^~~\n%Error: data/full_repos/permissive/104784866/NovaCORE/Verilog/src/NovaCORE.v:190: Cannot find file containing module: 'CBox'\n CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 1,235 | module | module NovaCORE#(
parameter DIMENSION = 4,
parameter CLB_WIDTH = 16,
parameter CH_WIDTH = 4,
parameter LUT_WIDTH = 2,
parameter DIMENSION_WIDTH = 2,
parameter CH_WIDTH_WIDTH = 2,
parameter LUT_WIDTH_WIDTH = 1,
parameter UID_WIDTH = 16
) (
clk,
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
c_dimswitch,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
);
parameter CONFIG_WORD_WIDTH = (`CLB_CONFIG_WORD_WIDTH > `CBOX_CONFIG_WORD_WIDTH)?
(`CLB_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
`CLB_CONFIG_WORD_WIDTH
:
`SBOX_CONFIG_WORD_WIDTH
:
(`CBOX_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
`CBOX_CONFIG_WORD_WIDTH
:
`SBOX_CONFIG_WORD_WIDTH;
input clk;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
input c_dimswitch;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_n;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_s;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_n;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_s;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_n;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_s;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_n;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_s;
generate
if(DIMENSION != 1) begin : configRegGen
reg [DIMENSION_WIDTH-1:0] configReg;
always @(posedge c_dimswitch) begin
if(mode) begin
`CONFIGREG_DIMENSION = c_dimension;
end
end
end
else begin : configRegGen
wire configReg;
assign configReg = 'b0;
end
endgenerate
wire [(CH_WIDTH>>1)-1:0] vUpChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
wire [(CH_WIDTH>>1)-1:0] vDnChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
wire [(CH_WIDTH>>1)-1:0] hLtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
wire [(CH_WIDTH>>1)-1:0] hRtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
wire [LUT_WIDTH:0] vCLBIn [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
wire hCLBOut [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
genvar i, j;
generate
for(i = 0; i < (CLB_WIDTH << 1); i = i+2) begin : ArrayGen
for(j = 0; j < (CLB_WIDTH << 1); j = j+2) begin : CBoxGen
CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CBOX_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(hLtChannels[i>>1][j]),
.ch_up_s(hLtChannels[i>>1][j+1]),
.ch_dn_n(hRtChannels[i>>1][j]),
.ch_dn_s(hRtChannels[i>>1][j+1]),
.clb_in(vCLBIn[(i >> 1)][(j >> 1)]),
.clb_out()
);
SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`SBOX_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(vUpChannels[i][j>>1]),
.ch_up_s(vUpChannels[i+1][j>>1]),
.ch_dn_n(vDnChannels[i][j>>1]),
.ch_dn_s(vDnChannels[i+1][j>>1]),
.ch_lt_n(hLtChannels[i>>1][j+1]),
.ch_lt_s(hLtChannels[i>>1][j+2]),
.ch_rt_n(hRtChannels[i>>1][j+1]),
.ch_rt_s(hRtChannels[i>>1][j+2])
);
CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(
.clk(clk),
.clk_en(vCLBIn[(i >> 1)][(j >> 1)][2]),
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CLB_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.b_in(vCLBIn[(i >> 1)][(j >> 1)][1:0]),
.b_out(hCLBOut[(i >> 1)][(j >> 1)])
);
CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CBOX2_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(vUpChannels[i+1][j>>1]),
.ch_up_s(vUpChannels[i+2][j>>1]),
.ch_dn_n(vDnChannels[i+1][j>>1]),
.ch_dn_s(vDnChannels[i+2][j>>1]),
.clb_in(),
.clb_out(hCLBOut[(i >> 1)][(j >> 1)])
);
end
end
for(i = 0; i < CLB_WIDTH; i = i+1) begin : IOGen
assign io_up_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vUpChannels[0][CLB_WIDTH-i-1];
assign vUpChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1] = io_up_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign vDnChannels[0][CLB_WIDTH-i-1] = io_dn_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign io_dn_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vDnChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1];
assign io_lt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hLtChannels[i][0];
assign hLtChannels[i][(CLB_WIDTH<<1)] = io_lt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign hRtChannels[i][0] = io_rt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign io_rt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hRtChannels[i][(CLB_WIDTH<<1)];
end
endgenerate
endmodule | module NovaCORE#(
parameter DIMENSION = 4,
parameter CLB_WIDTH = 16,
parameter CH_WIDTH = 4,
parameter LUT_WIDTH = 2,
parameter DIMENSION_WIDTH = 2,
parameter CH_WIDTH_WIDTH = 2,
parameter LUT_WIDTH_WIDTH = 1,
parameter UID_WIDTH = 16
) (
clk,
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
c_dimswitch,
io_up_n,
io_up_s,
io_dn_n,
io_dn_s,
io_lt_n,
io_lt_s,
io_rt_n,
io_rt_s
); |
parameter CONFIG_WORD_WIDTH = (`CLB_CONFIG_WORD_WIDTH > `CBOX_CONFIG_WORD_WIDTH)?
(`CLB_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
`CLB_CONFIG_WORD_WIDTH
:
`SBOX_CONFIG_WORD_WIDTH
:
(`CBOX_CONFIG_WORD_WIDTH > `SBOX_CONFIG_WORD_WIDTH)?
`CBOX_CONFIG_WORD_WIDTH
:
`SBOX_CONFIG_WORD_WIDTH;
input clk;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
input c_dimswitch;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_n;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_up_s;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_n;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_dn_s;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_n;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_lt_s;
input [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_n;
output [(CLB_WIDTH*(CH_WIDTH>>1))-1:0] io_rt_s;
generate
if(DIMENSION != 1) begin : configRegGen
reg [DIMENSION_WIDTH-1:0] configReg;
always @(posedge c_dimswitch) begin
if(mode) begin
`CONFIGREG_DIMENSION = c_dimension;
end
end
end
else begin : configRegGen
wire configReg;
assign configReg = 'b0;
end
endgenerate
wire [(CH_WIDTH>>1)-1:0] vUpChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
wire [(CH_WIDTH>>1)-1:0] vDnChannels [0:(CLB_WIDTH<<2)][0:CLB_WIDTH-1];
wire [(CH_WIDTH>>1)-1:0] hLtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
wire [(CH_WIDTH>>1)-1:0] hRtChannels [0:CLB_WIDTH-1][0:(CLB_WIDTH<<2)];
wire [LUT_WIDTH:0] vCLBIn [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
wire hCLBOut [0:CLB_WIDTH-1][0:CLB_WIDTH-1];
genvar i, j;
generate
for(i = 0; i < (CLB_WIDTH << 1); i = i+2) begin : ArrayGen
for(j = 0; j < (CLB_WIDTH << 1); j = j+2) begin : CBoxGen
CBox#(((CLB_WIDTH << 1) * i) + j, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), LUT_WIDTH+1, 1, LUT_WIDTH_WIDTH+1, UID_WIDTH, DIMENSION_WIDTH) cboxInst(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CBOX_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(hLtChannels[i>>1][j]),
.ch_up_s(hLtChannels[i>>1][j+1]),
.ch_dn_n(hRtChannels[i>>1][j]),
.ch_dn_s(hRtChannels[i>>1][j+1]),
.clb_in(vCLBIn[(i >> 1)][(j >> 1)]),
.clb_out()
);
SBox#(((CLB_WIDTH << 1) * i) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), UID_WIDTH, DIMENSION_WIDTH, CH_WIDTH_WIDTH) sboxInst(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`SBOX_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(vUpChannels[i][j>>1]),
.ch_up_s(vUpChannels[i+1][j>>1]),
.ch_dn_n(vDnChannels[i][j>>1]),
.ch_dn_s(vDnChannels[i+1][j>>1]),
.ch_lt_n(hLtChannels[i>>1][j+1]),
.ch_lt_s(hLtChannels[i>>1][j+2]),
.ch_rt_n(hRtChannels[i>>1][j+1]),
.ch_rt_s(hRtChannels[i>>1][j+2])
);
CLB#(((CLB_WIDTH << 1) * (i + 1)) + j, DIMENSION, UID_WIDTH, LUT_WIDTH, DIMENSION_WIDTH) clbInst(
.clk(clk),
.clk_en(vCLBIn[(i >> 1)][(j >> 1)][2]),
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CLB_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.b_in(vCLBIn[(i >> 1)][(j >> 1)][1:0]),
.b_out(hCLBOut[(i >> 1)][(j >> 1)])
);
CBox#(((CLB_WIDTH << 1) * (i + 1)) + j + 1, DIMENSION, (CH_WIDTH >> 1), (CH_WIDTH >> 1), 1, 1, 1, UID_WIDTH, DIMENSION_WIDTH) cboxInst2(
.mode(mode),
.c_clk(c_clk),
.c_bus(c_bus[`CBOX2_CONFIG_WORD_WIDTH-1:0]),
.c_uid(c_uid),
.c_dimension(`CONFIGREG_DIMENSION),
.ch_up_n(vUpChannels[i+1][j>>1]),
.ch_up_s(vUpChannels[i+2][j>>1]),
.ch_dn_n(vDnChannels[i+1][j>>1]),
.ch_dn_s(vDnChannels[i+2][j>>1]),
.clb_in(),
.clb_out(hCLBOut[(i >> 1)][(j >> 1)])
);
end
end
for(i = 0; i < CLB_WIDTH; i = i+1) begin : IOGen
assign io_up_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vUpChannels[0][CLB_WIDTH-i-1];
assign vUpChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1] = io_up_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign vDnChannels[0][CLB_WIDTH-i-1] = io_dn_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign io_dn_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = vDnChannels[(CLB_WIDTH<<1)][CLB_WIDTH-i-1];
assign io_lt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hLtChannels[i][0];
assign hLtChannels[i][(CLB_WIDTH<<1)] = io_lt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign hRtChannels[i][0] = io_rt_n[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)];
assign io_rt_s[((CH_WIDTH>>1)*(i+1))-1:((CH_WIDTH>>1)*i)] = hRtChannels[i][(CLB_WIDTH<<1)];
end
endgenerate
endmodule | 0 |
3,478 | data/full_repos/permissive/104784866/SBox/Verilog/src/MDimMux.v | 104,784,866 | MDimMux.v | v | 90 | 127 | [] | [] | [] | [(32, 89)] | null | data/verilator_xmls/03985fbd-b68e-487c-96f5-73f274a65ed6.xml | null | 1,236 | module | module MDimMux#(
parameter DIMENSION = 4,
parameter CH_IN_WIDTH = 8,
parameter DIMENSION_WIDTH = 2,
parameter CH_IN_WIDTH_WIDTH = 3
) (
mode,
c_clk,
c_bus,
c_dimension,
ch_in,
ch_out
);
parameter CONFIG_WORD_WIDTH = DIMENSION*CH_IN_WIDTH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [CH_IN_WIDTH-1:0] ch_in;
output ch_out;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
wire [CH_IN_WIDTH-1:0] muxWires;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_MUX_VALUE = `C_BUS_MUX_VALUE;
end
end
genvar i;
generate
for(i = 0; i < CH_IN_WIDTH; i = i+1) begin : muxWiresGen
assign muxWires[i] = (i == ((`CONFIGREG_MUX_VALUE >> (c_dimension * CH_IN_WIDTH_WIDTH)) & CH_IN_WIDTH-1))? ch_in[i] : 1'b0;
end
endgenerate
assign ch_out = (| muxWires);
endmodule | module MDimMux#(
parameter DIMENSION = 4,
parameter CH_IN_WIDTH = 8,
parameter DIMENSION_WIDTH = 2,
parameter CH_IN_WIDTH_WIDTH = 3
) (
mode,
c_clk,
c_bus,
c_dimension,
ch_in,
ch_out
); |
parameter CONFIG_WORD_WIDTH = DIMENSION*CH_IN_WIDTH_WIDTH;
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [DIMENSION_WIDTH-1:0] c_dimension;
input [CH_IN_WIDTH-1:0] ch_in;
output ch_out;
reg [CONFIG_WORD_WIDTH-1:0] configReg;
wire [CH_IN_WIDTH-1:0] muxWires;
always @(posedge c_clk) begin
if(mode) begin
`CONFIGREG_MUX_VALUE = `C_BUS_MUX_VALUE;
end
end
genvar i;
generate
for(i = 0; i < CH_IN_WIDTH; i = i+1) begin : muxWiresGen
assign muxWires[i] = (i == ((`CONFIGREG_MUX_VALUE >> (c_dimension * CH_IN_WIDTH_WIDTH)) & CH_IN_WIDTH-1))? ch_in[i] : 1'b0;
end
endgenerate
assign ch_out = (| muxWires);
endmodule | 0 |
3,479 | data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v | 104,784,866 | SBox.v | v | 168 | 134 | [] | [] | [] | [(52, 167)] | null | null | 1: b"%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:116: Cannot find file containing module: 'MDimMux'\n MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux\n data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux.v\n data/full_repos/permissive/104784866/SBox/Verilog/src,data/full_repos/permissive/104784866/MDimMux.sv\n MDimMux\n MDimMux.v\n MDimMux.sv\n obj_dir/MDimMux\n obj_dir/MDimMux.v\n obj_dir/MDimMux.sv\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:129: Cannot find file containing module: 'MDimMux'\n MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n ^~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:142: Cannot find file containing module: 'MDimMux'\n MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n ^~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox.v:155: Cannot find file containing module: 'MDimMux'\n MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 1,237 | module | module SBox#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter UID_WIDTH = 16,
parameter DIMENSION_WIDTH = 2,
parameter CH_WIDTH_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
ch_lt_n,
ch_lt_s,
ch_rt_n,
ch_rt_s
);
parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_WIDTH_WIDTH+1))+(CH_WIDTH_WIDTH+1);
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
output [CH_UP_WIDTH-1:0] ch_lt_n;
input [CH_UP_WIDTH-1:0] ch_lt_s;
input [CH_DN_WIDTH-1:0] ch_rt_n;
output [CH_DN_WIDTH-1:0] ch_rt_s;
genvar i;
generate
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen
wire filteredClk = c_clk && (i == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_up_n[i])
);
end
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen2
wire filteredClk = c_clk && ((i + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_lt_n[i])
);
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen3
wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_dn_s[i])
);
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen4
wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH + CH_DN_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_rt_s[i])
);
end
endgenerate
endmodule | module SBox#(
parameter UID = 0,
parameter DIMENSION = 4,
parameter CH_UP_WIDTH = 2,
parameter CH_DN_WIDTH = 2,
parameter UID_WIDTH = 16,
parameter DIMENSION_WIDTH = 2,
parameter CH_WIDTH_WIDTH = 2
) (
mode,
c_clk,
c_bus,
c_uid,
c_dimension,
ch_up_n,
ch_up_s,
ch_dn_n,
ch_dn_s,
ch_lt_n,
ch_lt_s,
ch_rt_n,
ch_rt_s
); |
parameter CONFIG_WORD_WIDTH = (DIMENSION*(CH_WIDTH_WIDTH+1))+(CH_WIDTH_WIDTH+1);
input mode;
input c_clk;
input [CONFIG_WORD_WIDTH-1:0] c_bus;
input [UID_WIDTH-1:0] c_uid;
input [DIMENSION_WIDTH-1:0] c_dimension;
output [CH_UP_WIDTH-1:0] ch_up_n;
input [CH_UP_WIDTH-1:0] ch_up_s;
input [CH_DN_WIDTH-1:0] ch_dn_n;
output [CH_DN_WIDTH-1:0] ch_dn_s;
output [CH_UP_WIDTH-1:0] ch_lt_n;
input [CH_UP_WIDTH-1:0] ch_lt_s;
input [CH_DN_WIDTH-1:0] ch_rt_n;
output [CH_DN_WIDTH-1:0] ch_rt_s;
genvar i;
generate
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen
wire filteredClk = c_clk && (i == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_up_n[i])
);
end
for(i = 0; i < CH_UP_WIDTH; i = i+1) begin : MDimMuxGen2
wire filteredClk = c_clk && ((i + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_lt_n[i])
);
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen3
wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_dn_s[i])
);
end
for(i = 0; i < CH_DN_WIDTH; i = i+1) begin : MDimMuxGen4
wire filteredClk = c_clk && ((i + CH_UP_WIDTH + CH_UP_WIDTH + CH_DN_WIDTH) == `C_BUS_MUX_ADDR) && (UID == c_uid);
MDimMux#(DIMENSION, (CH_UP_WIDTH+CH_DN_WIDTH)*2, DIMENSION_WIDTH, CH_WIDTH_WIDTH+1) inst(
.mode(mode),
.c_clk(filteredClk),
.c_bus(`C_BUS_MUX_SWITCH),
.c_dimension(c_dimension),
.ch_in({ch_lt_s, ch_up_s, ch_rt_n, ch_dn_n}),
.ch_out(ch_rt_s[i])
);
end
endgenerate
endmodule | 0 |
3,480 | data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v | 104,784,866 | SBox_tb.v | v | 252 | 162 | [] | [] | [] | null | line:101: before: "@" | null | 1: b'%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:91: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("SBox_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:92: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:101: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:105: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:109: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:112: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:115: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:118: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:121: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:124: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:127: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:130: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:134: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:141: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:150: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:159: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:168: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:177: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:185: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:189: syntax error, unexpected \'@\'\n #50@(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:189: Unsupported: Ignoring delay on this delayed statement.\n #50@(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:193: syntax error, unexpected \'@\'\n #100 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n #100 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:200: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:200: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:209: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:218: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:227: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:236: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:236: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Error: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:242: syntax error, unexpected \'@\'\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n #50 @(posedge r_clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/104784866/SBox/Verilog/src/SBox_tb.v:248: Unsupported: Ignoring delay on this delayed statement.\n #50 r_clk <= ~r_clk;\n ^\n%Error: Exiting due to 27 error(s), 26 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,238 | module | module SBox_tb;
reg r_clk;
reg r_mode;
reg [8:0] r_c_bus;
reg r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg [1:0] r_ch_lt_s;
reg [1:0] r_ch_rt_n;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
wire [1:0] w_ch_lt_n;
wire [1:0] w_ch_rt_s;
SBox#(0, 2, 2, 2, 16, 1, 2) inst(
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.ch_lt_n(w_ch_lt_n),
.ch_lt_s(r_ch_lt_s),
.ch_rt_n(r_ch_rt_n),
.ch_rt_s(w_ch_rt_s)
);
initial begin
$dumpfile("SBox_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'b0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_ch_lt_s <= 'h3;
r_ch_rt_n <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {3'h0, 6'b100110};
#50 @(posedge r_clk);
r_c_bus <= {3'h1, 6'b100101};
#50 @(posedge r_clk);
r_c_bus <= {3'h2, 6'b100101};
#50 @(posedge r_clk);
r_c_bus <= {3'h3, 6'b100001};
#50 @(posedge r_clk);
r_c_bus <= {3'h4, 6'b100110};
#50 @(posedge r_clk);
r_c_bus <= {3'h5, 6'b100011};
#50 @(posedge r_clk);
r_c_bus <= {3'h6, 6'b100010};
#50 @(posedge r_clk);
r_c_bus <= {3'h7, 6'b100010};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_ch_dn_n <= 'h0;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h1;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h2;
r_ch_lt_s <= 'h3;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h1;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h1;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_ch_dn_n <= 'h0;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h1;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h2;
r_ch_lt_s <= 'h3;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h1;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h1;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | module SBox_tb; |
reg r_clk;
reg r_mode;
reg [8:0] r_c_bus;
reg r_c_dimension;
reg [1:0] r_ch_up_s;
reg [1:0] r_ch_dn_n;
reg [1:0] r_ch_lt_s;
reg [1:0] r_ch_rt_n;
wire [1:0] w_ch_up_n;
wire [1:0] w_ch_dn_s;
wire [1:0] w_ch_lt_n;
wire [1:0] w_ch_rt_s;
SBox#(0, 2, 2, 2, 16, 1, 2) inst(
.mode(r_mode),
.c_clk(r_clk),
.c_bus(r_c_bus),
.c_dimension(r_c_dimension),
.ch_up_n(w_ch_up_n),
.ch_up_s(r_ch_up_s),
.ch_dn_n(r_ch_dn_n),
.ch_dn_s(w_ch_dn_s),
.ch_lt_n(w_ch_lt_n),
.ch_lt_s(r_ch_lt_s),
.ch_rt_n(r_ch_rt_n),
.ch_rt_s(w_ch_rt_s)
);
initial begin
$dumpfile("SBox_tb.vcd");
$dumpvars(1, r_clk, r_mode, r_c_bus, r_c_dimension, r_ch_up_s, r_ch_dn_n, r_ch_lt_s, r_ch_rt_n, w_ch_up_n, w_ch_dn_s, w_ch_lt_n, w_ch_rt_s);
r_clk <= 'b1;
r_mode <= 'b0;
r_c_bus <= 'h0;
r_c_dimension <= 'b0;
r_ch_up_s <= 'h3;
r_ch_dn_n <= 'h3;
r_ch_lt_s <= 'h3;
r_ch_rt_n <= 'h3;
#100 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_bus <= {3'h0, 6'b100110};
#50 @(posedge r_clk);
r_c_bus <= {3'h1, 6'b100101};
#50 @(posedge r_clk);
r_c_bus <= {3'h2, 6'b100101};
#50 @(posedge r_clk);
r_c_bus <= {3'h3, 6'b100001};
#50 @(posedge r_clk);
r_c_bus <= {3'h4, 6'b100110};
#50 @(posedge r_clk);
r_c_bus <= {3'h5, 6'b100011};
#50 @(posedge r_clk);
r_c_bus <= {3'h6, 6'b100010};
#50 @(posedge r_clk);
r_c_bus <= {3'h7, 6'b100010};
#50 @(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_ch_dn_n <= 'h0;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h1;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h2;
r_ch_lt_s <= 'h3;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h1;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h1;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_mode <= 'b1;
#100 @(posedge r_clk);
r_c_dimension <= 'h1;
#50@(posedge r_clk);
r_mode <= 'b0;
#100 @(posedge r_clk);
r_ch_dn_n <= 'h0;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h1;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h0;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h2;
r_ch_rt_n <= 'h3;
r_ch_up_s <= 'h2;
r_ch_lt_s <= 'h3;
#50 @(posedge r_clk);
r_ch_dn_n <= 'h1;
r_ch_rt_n <= 'h0;
r_ch_up_s <= 'h1;
r_ch_lt_s <= 'h0;
#50 @(posedge r_clk);
#50 @(posedge r_clk);
$finish;
end
always begin
#50 r_clk <= ~r_clk;
end
endmodule | 0 |
3,484 | data/full_repos/permissive/10490967/src/timer.v | 10,490,967 | timer.v | v | 80 | 81 | [] | [] | [] | [(20, 77)] | null | data/verilator_xmls/48d7408d-1ef8-42b8-80a4-a3c094f5ae53.xml | null | 1,244 | module | module timer
#(parameter
TIMEOUT = 100)
(input clk,
input rst,
input up_req,
output up_grant,
input up_ack,
output down_req,
input down_grant,
output down_ack
);
`ifdef VERBOSE
initial $display("Bus timer with timeout %d", TIMEOUT);
`endif
wire timeout;
reg [31:0] counter;
assign up_grant = down_grant;
assign down_ack = up_ack;
assign timeout = (TIMEOUT == counter);
assign down_req = up_req & ~timeout;
always @(posedge clk)
if (rst) counter <= 'b0;
else begin
counter <= 'b0;
if (down_grant & ~timeout) begin
counter <= counter + 1'b1;
end
end
endmodule | module timer
#(parameter
TIMEOUT = 100)
(input clk,
input rst,
input up_req,
output up_grant,
input up_ack,
output down_req,
input down_grant,
output down_ack
); |
`ifdef VERBOSE
initial $display("Bus timer with timeout %d", TIMEOUT);
`endif
wire timeout;
reg [31:0] counter;
assign up_grant = down_grant;
assign down_ack = up_ack;
assign timeout = (TIMEOUT == counter);
assign down_req = up_req & ~timeout;
always @(posedge clk)
if (rst) counter <= 'b0;
else begin
counter <= 'b0;
if (down_grant & ~timeout) begin
counter <= counter + 1'b1;
end
end
endmodule | 28 |
3,485 | data/full_repos/permissive/10490967/src/timer_tb.v | 10,490,967 | timer_tb.v | v | 167 | 55 | [] | [] | [] | null | line:110: before: ";" | null | 1: b'%Error: data/full_repos/permissive/10490967/src/timer_tb.v:18: Cannot find include file: timer.v\n`include "timer.v" \n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v\n data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v.v\n data/full_repos/permissive/10490967/src,data/full_repos/permissive/10490967/timer.v.sv\n timer.v\n timer.v.v\n timer.v.sv\n obj_dir/timer.v\n obj_dir/timer.v.v\n obj_dir/timer.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/10490967/src/timer_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:32: Unsupported: event data types\n event end_trigger;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/10490967/src/timer_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n initial #1 display_header();\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n );\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:136: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:138: syntax error, unexpected \'@\'\n repeat(10) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:141: syntax error, unexpected \'@\'\n repeat(20) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:149: syntax error, unexpected \'@\'\n repeat(5) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:151: syntax error, unexpected \'@\'\n repeat(15) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:153: syntax error, unexpected \'@\'\n repeat(15) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:155: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/10490967/src/timer_tb.v:162: syntax error, unexpected ->\n -> end_trigger;\n ^~\n%Error: Exiting due to 11 error(s), 2 warning(s)\n' | 1,245 | module | module timer_tb;
reg clk;
always #1 clk = !clk;
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
initial #1 display_header();
always @(end_trigger) display_header();
always @(posedge clk) display_signals();
`endif
parameter TIMEOUT = 10;
`ifdef TB_VERBOSE
initial $display("Testbench for unit 'timer'");
`endif
reg rst;
reg up_req;
wire up_grant;
wire down_req;
wire down_grant;
timer #(
.TIMEOUT (TIMEOUT))
uut (
.clk (clk),
.rst (rst),
.up_req (up_req),
.up_grant (up_grant),
.up_ack (),
.down_req (down_req),
.down_grant (down_grant),
.down_ack ()
);
task display_signals;
$display(
"%d\t%d",
$time, rst,
"\t%b\t%b",
up_req,
down_req,
"\t%b\t%b",
up_grant,
down_grant,
);
endtask
task display_header;
$display({
"\t\ttime\trst",
""});
endtask
assign down_grant = down_req;
initial begin
clk = 0;
rst = 0;
up_req = 1'b0;
`ifdef TB_VERBOSE
$display("RESET");
`endif
repeat(10) @(posedge clk);
rst <= 1'b1;
repeat(10) @(posedge clk);
rst <= 1'b0;
repeat(20) @(posedge clk);
`ifdef TB_VERBOSE
$display("TEST different ports request priority");
`endif
up_req = 1'b1;
repeat(5) @(posedge clk);
up_req = 1'b0;
repeat(15) @(posedge clk);
up_req = 1'b1;
repeat(15) @(posedge clk);
up_req = 1'b0;
@(posedge clk);
@(posedge clk);
`ifdef TB_VERBOSE
$display("END");
`endif
-> end_trigger;
end
endmodule | module timer_tb; |
reg clk;
always #1 clk = !clk;
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
initial #1 display_header();
always @(end_trigger) display_header();
always @(posedge clk) display_signals();
`endif
parameter TIMEOUT = 10;
`ifdef TB_VERBOSE
initial $display("Testbench for unit 'timer'");
`endif
reg rst;
reg up_req;
wire up_grant;
wire down_req;
wire down_grant;
timer #(
.TIMEOUT (TIMEOUT))
uut (
.clk (clk),
.rst (rst),
.up_req (up_req),
.up_grant (up_grant),
.up_ack (),
.down_req (down_req),
.down_grant (down_grant),
.down_ack ()
);
task display_signals;
$display(
"%d\t%d",
$time, rst,
"\t%b\t%b",
up_req,
down_req,
"\t%b\t%b",
up_grant,
down_grant,
);
endtask
task display_header;
$display({
"\t\ttime\trst",
""});
endtask
assign down_grant = down_req;
initial begin
clk = 0;
rst = 0;
up_req = 1'b0;
`ifdef TB_VERBOSE
$display("RESET");
`endif
repeat(10) @(posedge clk);
rst <= 1'b1;
repeat(10) @(posedge clk);
rst <= 1'b0;
repeat(20) @(posedge clk);
`ifdef TB_VERBOSE
$display("TEST different ports request priority");
`endif
up_req = 1'b1;
repeat(5) @(posedge clk);
up_req = 1'b0;
repeat(15) @(posedge clk);
up_req = 1'b1;
repeat(15) @(posedge clk);
up_req = 1'b0;
@(posedge clk);
@(posedge clk);
`ifdef TB_VERBOSE
$display("END");
`endif
-> end_trigger;
end
endmodule | 28 |
3,486 | data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds .v | 105,090,390 | PiscaLeds .v | v | 52 | 35 | [] | [] | [] | [(1, 27), (30, 47)] | null | null | 1: b'%Error: Cannot find file containing module: data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n ... Looked in:\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n%Error: Cannot find file containing module: .v\n%Error: Exiting due to 2 error(s)\n' | 1,247 | module | module PiscaLeds(
input CLOCK_50,
input[3:0] KEY,
input [9:0]SW,
output [7:0] LEDG,
output [9:0] LEDR
);
reg [25:0] cont = 0;
reg luz;
assign LEDG = luz;
assign LEDR = SW;
always @(posedge CLOCK_50) begin
if (cont == 50000000) begin
luz = ~luz;
cont = 0;
end
else begin
cont = cont + 1;
end
end
endmodule | module PiscaLeds(
input CLOCK_50,
input[3:0] KEY,
input [9:0]SW,
output [7:0] LEDG,
output [9:0] LEDR
); |
reg [25:0] cont = 0;
reg luz;
assign LEDG = luz;
assign LEDR = SW;
always @(posedge CLOCK_50) begin
if (cont == 50000000) begin
luz = ~luz;
cont = 0;
end
else begin
cont = cont + 1;
end
end
endmodule | 0 |
3,487 | data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds .v | 105,090,390 | PiscaLeds .v | v | 52 | 35 | [] | [] | [] | [(1, 27), (30, 47)] | null | null | 1: b'%Error: Cannot find file containing module: data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n ... Looked in:\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n data/full_repos/permissive/105090390/TrabalhosDeSistemas,data/full_repos/permissive/105090390/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.v\n obj_dir/data/full_repos/permissive/105090390/TrabalhosDeSistemas/PiscaLeds.sv\n%Error: Cannot find file containing module: .v\n%Error: Exiting due to 2 error(s)\n' | 1,247 | module | module testbench;
wire led;
reg clk = 0;
PiscaLeds Leds1(clk, led);
always #50000 clk = ~clk;
initial begin
$dumpvars;
clk <= 0;
#100000;
$finish;
end
endmodule | module testbench; |
wire led;
reg clk = 0;
PiscaLeds Leds1(clk, led);
always #50000 clk = ~clk;
initial begin
$dumpvars;
clk <= 0;
#100000;
$finish;
end
endmodule | 0 |
3,488 | data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v | 105,090,390 | triangulo.v | v | 115 | 102 | [] | [] | [] | null | line:112: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,248 | module | module sing(
input [11:0] PTX,
input [11:0] PTY,
input [11:0] P1X,
input [11:0] P1Y,
input [11:0] P2X,
input [11:0] P2Y,
output sin
);
wire signed [11:0] Sub1;
wire signed [11:0] Sub2;
wire signed [11:0] Sub3;
wire signed [11:0] Sub4;
wire signed [22:0] Sub5;
wire signed [22:0] Mult1;
wire signed [22:0] Mult2;
assign Sub1 = PTX - P2X;
assign Sub2 = P1Y - P2Y;
assign Sub3 = P1X - P2X;
assign Sub4 = PTY - P2Y;
assign Mult1 = Sub1 * Sub2;
assign Mult2 = Sub3 * Sub4;
assign Sub5 = Mult1 - Mult2;
assign sin = (Sub5 >= 0) ? 1 : 0;
endmodule | module sing(
input [11:0] PTX,
input [11:0] PTY,
input [11:0] P1X,
input [11:0] P1Y,
input [11:0] P2X,
input [11:0] P2Y,
output sin
); |
wire signed [11:0] Sub1;
wire signed [11:0] Sub2;
wire signed [11:0] Sub3;
wire signed [11:0] Sub4;
wire signed [22:0] Sub5;
wire signed [22:0] Mult1;
wire signed [22:0] Mult2;
assign Sub1 = PTX - P2X;
assign Sub2 = P1Y - P2Y;
assign Sub3 = P1X - P2X;
assign Sub4 = PTY - P2Y;
assign Mult1 = Sub1 * Sub2;
assign Mult2 = Sub3 * Sub4;
assign Sub5 = Mult1 - Mult2;
assign sin = (Sub5 >= 0) ? 1 : 0;
endmodule | 0 |
3,489 | data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v | 105,090,390 | triangulo.v | v | 115 | 102 | [] | [] | [] | null | line:112: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,248 | module | module TesteTriangulo (
input [11:0] Ponto1X,
input [11:0] Ponto1Y,
input [11:0] Ponto2X,
input [11:0] Ponto2Y,
input [11:0] Ponto3X,
input [11:0] Ponto3Y,
input [11:0] PontoTX,
input [11:0] PontoTY,
output dentro
);
wire sinal1;
wire sinal2;
wire sinal3;
assign dentro = (sinal1 == 1 && sinal2 == 1 && sinal3 == 1) ? 1:0;
sinal S1(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, PontoTX, PontoTY, sinal1);
sinal S2(Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, sinal2);
sinal S3(Ponto3X, Ponto3Y, Ponto1X, Ponto1Y, PontoTX, PontoTY, sinal3);
endmodule | module TesteTriangulo (
input [11:0] Ponto1X,
input [11:0] Ponto1Y,
input [11:0] Ponto2X,
input [11:0] Ponto2Y,
input [11:0] Ponto3X,
input [11:0] Ponto3Y,
input [11:0] PontoTX,
input [11:0] PontoTY,
output dentro
); |
wire sinal1;
wire sinal2;
wire sinal3;
assign dentro = (sinal1 == 1 && sinal2 == 1 && sinal3 == 1) ? 1:0;
sinal S1(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, PontoTX, PontoTY, sinal1);
sinal S2(Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, sinal2);
sinal S3(Ponto3X, Ponto3Y, Ponto1X, Ponto1Y, PontoTX, PontoTY, sinal3);
endmodule | 0 |
3,490 | data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v | 105,090,390 | triangulo.v | v | 115 | 102 | [] | [] | [] | null | line:112: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:87: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:99: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:102: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:105: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:108: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105090390/TrabalhosDeSistemas/triangulo.v:111: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,248 | module | module Teste;
reg [11:0] Ponto1X;
reg [11:0] Ponto1Y;
reg [11:0] Ponto2X;
reg [11:0] Ponto2Y;
reg [11:0] Ponto3X;
reg [11:0] Ponto3Y;
reg [11:0] PontoTX;
reg [11:0] PontoTY;
wire Dentro;
TesteTriangulo A(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, Dentro);
initial
begin
$dumpvars(0,A);
#1
Ponto1X <= 10;
Ponto1Y <= 10;
Ponto2X <= 30;
Ponto2Y <= 10;
Ponto3X <= 20;
Ponto3Y <= 30;
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 9;
PontoTY <= 15;
#1
PontoTX <= 10;
PontoTY <= 11;
#1
PontoTX <= 30;
PontoTY <= 11;
#40
$finish;
end
endmodule | module Teste; |
reg [11:0] Ponto1X;
reg [11:0] Ponto1Y;
reg [11:0] Ponto2X;
reg [11:0] Ponto2Y;
reg [11:0] Ponto3X;
reg [11:0] Ponto3Y;
reg [11:0] PontoTX;
reg [11:0] PontoTY;
wire Dentro;
TesteTriangulo A(Ponto1X, Ponto1Y, Ponto2X, Ponto2Y, Ponto3X, Ponto3Y, PontoTX, PontoTY, Dentro);
initial
begin
$dumpvars(0,A);
#1
Ponto1X <= 10;
Ponto1Y <= 10;
Ponto2X <= 30;
Ponto2Y <= 10;
Ponto3X <= 20;
Ponto3Y <= 30;
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 15;
PontoTY <= 15;
#1
PontoTX <= 9;
PontoTY <= 15;
#1
PontoTX <= 10;
PontoTY <= 11;
#1
PontoTX <= 30;
PontoTY <= 11;
#40
$finish;
end
endmodule | 0 |
3,491 | data/full_repos/permissive/105152503/core/fifo.v | 105,152,503 | fifo.v | v | 58 | 72 | [] | [] | [] | [(15, 57)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105152503/core/fifo.v:50: Operator ASSIGNDLY expects 1024 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n : ... In instance fifo\n mem<= { WIDTH {1\'b0} };\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105152503/core/fifo.v:53: Bit extraction of var[1023:0] requires 10 bit index, not 128 bits.\n : ... In instance fifo\n mem[ctr*WIDTH-1-:WIDTH]<= idata;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 1,249 | module | module fifo(
input wire rst ,
input wire clk ,
input wire [WIDTH-1:0] idata ,
output wire [WIDTH-1:0] odata ,
input wire next ,
input wire wr_en ,
output wire full ,
output wire empty
);
parameter WIDTH = 8 ;
parameter NCBIT = 7 ;
parameter NWRD = 1<<NCBIT ;
parameter SIZE = WIDTH*NWRD ;
reg [SIZE-1 :0] mem ;
reg [NWRD-1 :0] ctr ;
assign empty = ctr== 0 ? 1'b1 : 1'b0;
assign full = ctr== NWRD ? 1'b1 : 1'b0;
assign odata = mem[WIDTH-1-:WIDTH] ;
always @ (posedge next) begin
if(~empty) begin
mem<= mem>>WIDTH;
ctr<= ctr- 1'b1;
end
end
always @ (posedge clk) begin
if(rst) begin
mem<= { WIDTH {1'b0} };
ctr<= { NWRD {1'b0} };
end else if(wr_en) begin
mem[ctr*WIDTH-1-:WIDTH]<= idata;
ctr<= ctr+ 1'b1;
end
end
endmodule | module fifo(
input wire rst ,
input wire clk ,
input wire [WIDTH-1:0] idata ,
output wire [WIDTH-1:0] odata ,
input wire next ,
input wire wr_en ,
output wire full ,
output wire empty
); |
parameter WIDTH = 8 ;
parameter NCBIT = 7 ;
parameter NWRD = 1<<NCBIT ;
parameter SIZE = WIDTH*NWRD ;
reg [SIZE-1 :0] mem ;
reg [NWRD-1 :0] ctr ;
assign empty = ctr== 0 ? 1'b1 : 1'b0;
assign full = ctr== NWRD ? 1'b1 : 1'b0;
assign odata = mem[WIDTH-1-:WIDTH] ;
always @ (posedge next) begin
if(~empty) begin
mem<= mem>>WIDTH;
ctr<= ctr- 1'b1;
end
end
always @ (posedge clk) begin
if(rst) begin
mem<= { WIDTH {1'b0} };
ctr<= { NWRD {1'b0} };
end else if(wr_en) begin
mem[ctr*WIDTH-1-:WIDTH]<= idata;
ctr<= ctr+ 1'b1;
end
end
endmodule | 0 |
3,492 | data/full_repos/permissive/105152503/core/fifo_test.v | 105,152,503 | fifo_test.v | v | 65 | 110 | [] | [] | [] | null | line:92: before: "$" | null | 1: b'%Error: data/full_repos/permissive/105152503/core/fifo_test.v:6: Cannot find include file: fifo.v\n`include "fifo.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v.v\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/fifo.v.sv\n fifo.v\n fifo.v.v\n fifo.v.sv\n obj_dir/fifo.v\n obj_dir/fifo.v.v\n obj_dir/fifo.v.sv\n%Error: data/full_repos/permissive/105152503/core/fifo_test.v:17: Unsupported or unknown PLI call: $monitor\n $monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #10 rst= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #20 wr_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n #30 wr_en= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100 rd_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n #140 rd_en= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #148 rd_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #149 rd_en= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n #200 wr_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n #200 rd_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/fifo_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~ clk;\n ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n' | 1,250 | module | module uart_test();
reg clk, rst, wr_en, rd_en;
reg [7:0] idata;
wire [7:0] odata;
reg [7:0] omem ;
wire full, empty;
initial begin
$monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);
idata= 0;
clk = 1;
rst = 1;
rd_en= 0;
wr_en= 0;
#10 rst= 0;
#20 wr_en= 1;
#30 wr_en= 0;
#100 rd_en= 1;
#140 rd_en= 0;
#148 rd_en= 1;
#149 rd_en= 0;
#200 wr_en= 1;
#200 rd_en= 1;
#1000 $finish;
end
always begin
#5 clk=~ clk;
end
always @ (posedge clk) begin
idata<= idata+ 1'b1;
if(idata> 8'hf) begin
rd_en<= ~rd_en;
end
if(~empty) begin
omem<= odata;
end
end
fifo #(.WIDTH(8), .NCBIT(7)) f0(
.rst(rst),
.clk(clk),
.idata(idata),
.odata(odata),
.next(rd_en),
.wr_en(wr_en),
.full(full),
.empty(empty)
);
endmodule | module uart_test(); |
reg clk, rst, wr_en, rd_en;
reg [7:0] idata;
wire [7:0] odata;
reg [7:0] omem ;
wire full, empty;
initial begin
$monitor("%4g %4x %1b %1b %1b %1b %3x %3x %3x", $time, clk, full, empty, wr_en, rd_en, idata, odata, omem);
idata= 0;
clk = 1;
rst = 1;
rd_en= 0;
wr_en= 0;
#10 rst= 0;
#20 wr_en= 1;
#30 wr_en= 0;
#100 rd_en= 1;
#140 rd_en= 0;
#148 rd_en= 1;
#149 rd_en= 0;
#200 wr_en= 1;
#200 rd_en= 1;
#1000 $finish;
end
always begin
#5 clk=~ clk;
end
always @ (posedge clk) begin
idata<= idata+ 1'b1;
if(idata> 8'hf) begin
rd_en<= ~rd_en;
end
if(~empty) begin
omem<= odata;
end
end
fifo #(.WIDTH(8), .NCBIT(7)) f0(
.rst(rst),
.clk(clk),
.idata(idata),
.odata(odata),
.next(rd_en),
.wr_en(wr_en),
.full(full),
.empty(empty)
);
endmodule | 0 |
3,493 | data/full_repos/permissive/105152503/core/uart.v | 105,152,503 | uart.v | v | 75 | 40 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/393817ef-996b-4d80-bbeb-9620fec192de.xml | null | 1,251 | module | module uart(
input wire clk ,
input wire rst ,
input wire [ 7:0] tx_data ,
input wire tx_en ,
output reg tx_ready ,
output reg tx ,
output reg [ 4:0] stage ,
output reg [10:0] ctr
);
parameter BAUD_THRESHOLD= 10;
reg [ 7:0] tx_buffer ;
task reset;
begin
tx <= 1;
tx_ready <= 1;
ctr <= 0;
stage <= 0;
tx_buffer<= 0;
end
endtask
always @ (posedge tx_en) begin
tx_ready<= 0;
tx_buffer<= tx_data;
end
always @ (posedge clk) begin
if(rst) begin
reset;
end else if(~tx_ready) begin
ctr<= ctr+ 1'b1;
case(stage)
5'h0 : tx<= 0;
5'h1 : tx<= tx_buffer[0];
5'h2 : tx<= tx_buffer[1];
5'h3 : tx<= tx_buffer[2];
5'h4 : tx<= tx_buffer[3];
5'h5 : tx<= tx_buffer[4];
5'h6 : tx<= tx_buffer[5];
5'h7 : tx<= tx_buffer[6];
5'h8 : tx<= tx_buffer[7];
5'h9 : tx<= 0;
5'ha : tx<= 0;
5'hb : reset;
default : tx<= 1;
endcase
end else begin
tx<= 1;
end
if(ctr== BAUD_THRESHOLD) begin
stage<= stage+1'b1;
ctr<= 0;
end
end
endmodule | module uart(
input wire clk ,
input wire rst ,
input wire [ 7:0] tx_data ,
input wire tx_en ,
output reg tx_ready ,
output reg tx ,
output reg [ 4:0] stage ,
output reg [10:0] ctr
); |
parameter BAUD_THRESHOLD= 10;
reg [ 7:0] tx_buffer ;
task reset;
begin
tx <= 1;
tx_ready <= 1;
ctr <= 0;
stage <= 0;
tx_buffer<= 0;
end
endtask
always @ (posedge tx_en) begin
tx_ready<= 0;
tx_buffer<= tx_data;
end
always @ (posedge clk) begin
if(rst) begin
reset;
end else if(~tx_ready) begin
ctr<= ctr+ 1'b1;
case(stage)
5'h0 : tx<= 0;
5'h1 : tx<= tx_buffer[0];
5'h2 : tx<= tx_buffer[1];
5'h3 : tx<= tx_buffer[2];
5'h4 : tx<= tx_buffer[3];
5'h5 : tx<= tx_buffer[4];
5'h6 : tx<= tx_buffer[5];
5'h7 : tx<= tx_buffer[6];
5'h8 : tx<= tx_buffer[7];
5'h9 : tx<= 0;
5'ha : tx<= 0;
5'hb : reset;
default : tx<= 1;
endcase
end else begin
tx<= 1;
end
if(ctr== BAUD_THRESHOLD) begin
stage<= stage+1'b1;
ctr<= 0;
end
end
endmodule | 0 |
3,494 | data/full_repos/permissive/105152503/core/uart_test.v | 105,152,503 | uart_test.v | v | 46 | 92 | [] | [] | [] | null | line:47: before: ";" | null | 1: b'%Error: data/full_repos/permissive/105152503/core/uart_test.v:6: Cannot find include file: uart.v\n`include "uart.v" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v.v\n data/full_repos/permissive/105152503/core,data/full_repos/permissive/105152503/uart.v.sv\n uart.v\n uart.v.v\n uart.v.sv\n obj_dir/uart.v\n obj_dir/uart.v.v\n obj_dir/uart.v.sv\n%Error: data/full_repos/permissive/105152503/core/uart_test.v:18: Unsupported or unknown PLI call: $monitor\n $monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 rst= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 rst= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n #100 tx_en= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #105 tx_data= 8\'hf;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n #1000 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105152503/core/uart_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~ clk;\n ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n' | 1,252 | module | module uart_test();
reg clk, rst, tx_en;
reg [7:0] tx_data;
wire tx_ready;
wire tx;
wire [10:0] ctr;
wire [ 4:0] stage;
initial begin
$monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);
clk= 1;
rst= 0;
tx_en= 0;
tx_data= 8'b01010101;
#5 rst= 1;
#10 rst= 0;
#100 tx_en= 1;
#105 tx_data= 8'hf;
#1000 $finish;
end
always begin
#5 clk=~ clk;
end
uart #(.BAUD_THRESHOLD(4)) u0(
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.tx_en(tx_en),
.tx(tx),
.tx_ready(tx_ready),
.ctr(ctr),
.stage(stage)
);
endmodule | module uart_test(); |
reg clk, rst, tx_en;
reg [7:0] tx_data;
wire tx_ready;
wire tx;
wire [10:0] ctr;
wire [ 4:0] stage;
initial begin
$monitor("%4g %1b %1b %10b %5b %10b %1b", $time, clk, tx_ready, ctr, stage, tx_data, tx);
clk= 1;
rst= 0;
tx_en= 0;
tx_data= 8'b01010101;
#5 rst= 1;
#10 rst= 0;
#100 tx_en= 1;
#105 tx_data= 8'hf;
#1000 $finish;
end
always begin
#5 clk=~ clk;
end
uart #(.BAUD_THRESHOLD(4)) u0(
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.tx_en(tx_en),
.tx(tx),
.tx_ready(tx_ready),
.ctr(ctr),
.stage(stage)
);
endmodule | 0 |
3,495 | data/full_repos/permissive/105269489/src/TEST/All modules v0.0 2 iterations/modules/BRAM.v | 105,269,489 | BRAM.v | v | 56 | 86 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: Cannot find file containing module: modules\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/All/modules\n data/full_repos/permissive/105269489/src/TEST/All/modules.v\n data/full_repos/permissive/105269489/src/TEST/All/modules.sv\n modules\n modules.v\n modules.sv\n obj_dir/modules\n obj_dir/modules.v\n obj_dir/modules.sv\n%Error: Cannot find file containing module: v0.0\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: iterations/modules,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/TEST/All\n%Error: Cannot find file containing module: iterations/modules/BRAM.v\n%Error: Exiting due to 6 error(s)\n' | 1,253 | module | module BRAM( i_wrEnable,
i_CLK,
i_writeAdd,
i_readAdd,
i_data,
o_data );
parameter RAM_WIDTH = `RAM_WIDTH;
parameter NB_ADDRESS= 10;
parameter INIT_FILE = "";
localparam RAM_DEPTH=(2**NB_ADDRESS)-1;
input i_wrEnable;
input i_CLK;
input [NB_ADDRESS-1:0] i_writeAdd;
input [NB_ADDRESS-1:0] i_readAdd;
input [RAM_WIDTH - 1:0] i_data;
output [RAM_WIDTH-1:0] o_data;
reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH:0];
reg [RAM_WIDTH-1:0] dout_reg;
integer ram_index;
generate
if (INIT_FILE != "") begin: use_init_file
initial
$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
end else begin: init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge i_CLK) begin
dout_reg<=BRAM[i_readAdd];
if(i_wrEnable) begin
BRAM[i_writeAdd]<=i_data;
end
end
assign{o_data}=dout_reg;
endmodule | module BRAM( i_wrEnable,
i_CLK,
i_writeAdd,
i_readAdd,
i_data,
o_data ); |
parameter RAM_WIDTH = `RAM_WIDTH;
parameter NB_ADDRESS= 10;
parameter INIT_FILE = "";
localparam RAM_DEPTH=(2**NB_ADDRESS)-1;
input i_wrEnable;
input i_CLK;
input [NB_ADDRESS-1:0] i_writeAdd;
input [NB_ADDRESS-1:0] i_readAdd;
input [RAM_WIDTH - 1:0] i_data;
output [RAM_WIDTH-1:0] o_data;
reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH:0];
reg [RAM_WIDTH-1:0] dout_reg;
integer ram_index;
generate
if (INIT_FILE != "") begin: use_init_file
initial
$readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
end else begin: init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge i_CLK) begin
dout_reg<=BRAM[i_readAdd];
if(i_wrEnable) begin
BRAM[i_writeAdd]<=i_data;
end
end
assign{o_data}=dout_reg;
endmodule | 18 |
3,497 | data/full_repos/permissive/105269489/src/TEST/All modules v0.0 2 iterations/modules/FSM.v | 105,269,489 | FSM.v | v | 176 | 94 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf3 in position 3555: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: modules\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/All/modules\n data/full_repos/permissive/105269489/src/TEST/All/modules.v\n data/full_repos/permissive/105269489/src/TEST/All/modules.sv\n modules\n modules.v\n modules.sv\n obj_dir/modules\n obj_dir/modules.v\n obj_dir/modules.sv\n%Error: Cannot find file containing module: v0.0\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: iterations/modules,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/TEST/All\n%Error: Cannot find file containing module: iterations/modules/FSM.v\n%Error: Exiting due to 6 error(s)\n' | 1,256 | module | module FSM#(
parameter NB_ADDRESS= `NB_ADDRESS,
parameter NB_IMAGE = `NB_IMAGE,
parameter NB_STATES = `NB_STATES,
parameter N_CONV = `N_CONV,
parameter LATENCIA = `LATENCIA
)(
output [NB_ADDRESS-1:0] o_writeAdd,
output [NB_ADDRESS-1:0] o_readAdd,
output o_EoP,
output [2:0] o_led,
output o_fsm_SOP,
output o_changeBlock,
output o_FSM_valid_conv,
input [NB_IMAGE-1:0] i_imgLength,
input i_CLK,
input i_reset,
input i_SoP,
input i_valid,
input i_load
);
reg [NB_ADDRESS-1:0] counterAdd;
reg [NB_ADDRESS-1:0] counter_with_latency;
reg [N_CONV-1:0] endOfProcess;
reg changeBlock;
reg sopControl;
reg valid_previous_state;
reg fms2conVld;
reg [NB_STATES-1:0] states;
reg w_eop;
integer nconv;
initial begin
counterAdd = `NB_ADDRESS'd0;
counter_with_latency = `NB_ADDRESS'd0;
endOfProcess = `N_CONV'd0;
changeBlock = 1'b0;
sopControl = 1'b0;
valid_previous_state = 1'b0;
fms2conVld = 1'b0;
states = `NB_STATES'd0;
end
always @(posedge i_CLK) begin
valid_previous_state<=i_valid;
if(i_reset)begin
counterAdd <= `NB_ADDRESS'd0;
counter_with_latency <= `NB_ADDRESS'd0;
endOfProcess <= `N_CONV'd0;
changeBlock <= 1'b0;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
states <= `NB_STATES'd0;
end
else begin
if(states == 2'b00) begin
counter_with_latency <= `NB_ADDRESS'd0;
counterAdd <= `NB_ADDRESS'd0;
changeBlock <= 1'b0;
if(i_load && ~i_SoP && endOfProcess==0) begin
states <= 2'b01;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
else if(~i_load && i_SoP && endOfProcess==0) begin
states <= 2'b10;
sopControl <= 1'b1;
fms2conVld <= 1'b1;
end
else if(~i_load && ~i_SoP && endOfProcess>0)begin
endOfProcess <= endOfProcess-1;
states <= 2'b01;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
else begin
states <= states;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
end
else if(states == 2'b01)begin
if (i_valid && !valid_previous_state) begin
if (endOfProcess > 0 && counterAdd==i_imgLength-2)begin
counterAdd <= counterAdd;
changeBlock <= 1'b1;
states <= 2'b00;
end
else if (counterAdd == i_imgLength) begin
counterAdd <= counterAdd;
changeBlock <= 1'b1;
states <= 2'b00;
end
else begin
counterAdd <= counterAdd+1;
changeBlock <= changeBlock;
states <= states;
end
end
else
counterAdd <= counterAdd;
end
else if(states == 2'b10) begin
if(counterAdd < i_imgLength)
counterAdd <= counterAdd+1;
else
counterAdd <= counterAdd;
if(counterAdd>=LATENCIA && counter_with_latency < i_imgLength-2) begin
counter_with_latency <= counter_with_latency +1;
fms2conVld <= fms2conVld;
states <= states;
end
else if(counter_with_latency == i_imgLength-2)begin
changeBlock <= 1'b1;
counter_with_latency <= counter_with_latency;
fms2conVld <= 1'b0;
states <= 2'b11;
end
else begin
counter_with_latency <= counter_with_latency;
fms2conVld <= fms2conVld;
states <= states;
end
end
else if(states == 2'b11)begin
endOfProcess <= N_CONV+1;
if (~i_SoP)
states <= 2'b00;
else
states <= states;
end
end
end
always @(*) begin
w_eop = 0;
for(nconv=0; nconv<N_CONV; nconv = nconv +1)
w_eop = w_eop | endOfProcess[nconv];
end
assign {o_writeAdd} = (sopControl) ? counter_with_latency:counterAdd;
assign {o_readAdd} = counterAdd;
assign {o_EoP} = w_eop;
assign {o_changeBlock} = changeBlock;
assign o_FSM_valid_conv = fms2conVld;
assign o_fsm_SOP = sopControl;
assign o_led[0] = i_load;
assign o_led[1] = w_eop;
assign o_led[2] = sopControl;
endmodule | module FSM#(
parameter NB_ADDRESS= `NB_ADDRESS,
parameter NB_IMAGE = `NB_IMAGE,
parameter NB_STATES = `NB_STATES,
parameter N_CONV = `N_CONV,
parameter LATENCIA = `LATENCIA
)(
output [NB_ADDRESS-1:0] o_writeAdd,
output [NB_ADDRESS-1:0] o_readAdd,
output o_EoP,
output [2:0] o_led,
output o_fsm_SOP,
output o_changeBlock,
output o_FSM_valid_conv,
input [NB_IMAGE-1:0] i_imgLength,
input i_CLK,
input i_reset,
input i_SoP,
input i_valid,
input i_load
); |
reg [NB_ADDRESS-1:0] counterAdd;
reg [NB_ADDRESS-1:0] counter_with_latency;
reg [N_CONV-1:0] endOfProcess;
reg changeBlock;
reg sopControl;
reg valid_previous_state;
reg fms2conVld;
reg [NB_STATES-1:0] states;
reg w_eop;
integer nconv;
initial begin
counterAdd = `NB_ADDRESS'd0;
counter_with_latency = `NB_ADDRESS'd0;
endOfProcess = `N_CONV'd0;
changeBlock = 1'b0;
sopControl = 1'b0;
valid_previous_state = 1'b0;
fms2conVld = 1'b0;
states = `NB_STATES'd0;
end
always @(posedge i_CLK) begin
valid_previous_state<=i_valid;
if(i_reset)begin
counterAdd <= `NB_ADDRESS'd0;
counter_with_latency <= `NB_ADDRESS'd0;
endOfProcess <= `N_CONV'd0;
changeBlock <= 1'b0;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
states <= `NB_STATES'd0;
end
else begin
if(states == 2'b00) begin
counter_with_latency <= `NB_ADDRESS'd0;
counterAdd <= `NB_ADDRESS'd0;
changeBlock <= 1'b0;
if(i_load && ~i_SoP && endOfProcess==0) begin
states <= 2'b01;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
else if(~i_load && i_SoP && endOfProcess==0) begin
states <= 2'b10;
sopControl <= 1'b1;
fms2conVld <= 1'b1;
end
else if(~i_load && ~i_SoP && endOfProcess>0)begin
endOfProcess <= endOfProcess-1;
states <= 2'b01;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
else begin
states <= states;
sopControl <= 1'b0;
fms2conVld <= 1'b0;
end
end
else if(states == 2'b01)begin
if (i_valid && !valid_previous_state) begin
if (endOfProcess > 0 && counterAdd==i_imgLength-2)begin
counterAdd <= counterAdd;
changeBlock <= 1'b1;
states <= 2'b00;
end
else if (counterAdd == i_imgLength) begin
counterAdd <= counterAdd;
changeBlock <= 1'b1;
states <= 2'b00;
end
else begin
counterAdd <= counterAdd+1;
changeBlock <= changeBlock;
states <= states;
end
end
else
counterAdd <= counterAdd;
end
else if(states == 2'b10) begin
if(counterAdd < i_imgLength)
counterAdd <= counterAdd+1;
else
counterAdd <= counterAdd;
if(counterAdd>=LATENCIA && counter_with_latency < i_imgLength-2) begin
counter_with_latency <= counter_with_latency +1;
fms2conVld <= fms2conVld;
states <= states;
end
else if(counter_with_latency == i_imgLength-2)begin
changeBlock <= 1'b1;
counter_with_latency <= counter_with_latency;
fms2conVld <= 1'b0;
states <= 2'b11;
end
else begin
counter_with_latency <= counter_with_latency;
fms2conVld <= fms2conVld;
states <= states;
end
end
else if(states == 2'b11)begin
endOfProcess <= N_CONV+1;
if (~i_SoP)
states <= 2'b00;
else
states <= states;
end
end
end
always @(*) begin
w_eop = 0;
for(nconv=0; nconv<N_CONV; nconv = nconv +1)
w_eop = w_eop | endOfProcess[nconv];
end
assign {o_writeAdd} = (sopControl) ? counter_with_latency:counterAdd;
assign {o_readAdd} = counterAdd;
assign {o_EoP} = w_eop;
assign {o_changeBlock} = changeBlock;
assign o_FSM_valid_conv = fms2conVld;
assign o_fsm_SOP = sopControl;
assign o_led[0] = i_load;
assign o_led[1] = w_eop;
assign o_led[2] = sopControl;
endmodule | 18 |
3,498 | data/full_repos/permissive/105269489/src/TEST/All modules v0.0 2 iterations/modules/MCU.v | 105,269,489 | MCU.v | v | 78 | 102 | [] | [] | [] | null | line:73: before: "integer" | null | 1: b'%Error: Cannot find file containing module: modules\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/All/modules\n data/full_repos/permissive/105269489/src/TEST/All/modules.v\n data/full_repos/permissive/105269489/src/TEST/All/modules.sv\n modules\n modules.v\n modules.sv\n obj_dir/modules\n obj_dir/modules.v\n obj_dir/modules.sv\n%Error: Cannot find file containing module: v0.0\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: iterations/modules,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/TEST/All\n%Error: Cannot find file containing module: iterations/modules/MCU.v\n%Error: Exiting due to 6 error(s)\n' | 1,257 | module | module MCU
#(
parameter N = 2,
parameter STATES = 3,
parameter BITS_IMAGEN = 8,
parameter BITS_DATA = 13,
parameter BITS_ADDR = 10
)(
input [N*BITS_DATA-1:0] i_DataConv,
input [BITS_IMAGEN-1:0] i_Data,
input [(N+2)*BITS_DATA-1:0] i_MemData,
input [BITS_ADDR-1:0] i_WAddr, i_RAddr,
input i_chblk, i_sop, i_eop, rst, clk,
output [3*N*BITS_IMAGEN-1:0] o_DataConv,
output [BITS_DATA-1:0] o_Data,
output [N+1:0] o_we,
output [BITS_ADDR-1:0] o_WAddr, o_RAddr,
output [(N+2)*BITS_DATA-1:0] o_MemData
);
wire [clog2(STATES-1)-1:0] state;
wire [clog2(N/2)-1: 0] substate;
wire [clog2(N+1)-1:0] memSelect;
assign o_WAddr = i_WAddr;
assign o_RAddr = i_RAddr;
MUX_ARRAY
#(
.N(N),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.STATES(STATES)
)
u_MUX_ARRAY
(
.i_DataConv(i_DataConv),
.i_MemData(i_MemData),
.i_Data(i_Data),
.i_state(state),
.i_substate(substate),
.i_memSelect(memSelect),
.o_DataConv(o_DataConv),
.o_MemData(o_MemData),
.o_Data(o_Data)
);
MCU_CTRL
#(
.N(N),
.STATES(STATES)
)
u_MCU_CTRL
(
.i_sop(i_sop),
.i_eop(i_eop),
.i_chblk(i_chblk),
.clk(clk),
.rst(rst),
.o_we(o_we),
.o_state(state),
.o_substate(substate),
.o_memSelect(memSelect)
);
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | module MCU
#(
parameter N = 2,
parameter STATES = 3,
parameter BITS_IMAGEN = 8,
parameter BITS_DATA = 13,
parameter BITS_ADDR = 10
)(
input [N*BITS_DATA-1:0] i_DataConv,
input [BITS_IMAGEN-1:0] i_Data,
input [(N+2)*BITS_DATA-1:0] i_MemData,
input [BITS_ADDR-1:0] i_WAddr, i_RAddr,
input i_chblk, i_sop, i_eop, rst, clk,
output [3*N*BITS_IMAGEN-1:0] o_DataConv,
output [BITS_DATA-1:0] o_Data,
output [N+1:0] o_we,
output [BITS_ADDR-1:0] o_WAddr, o_RAddr,
output [(N+2)*BITS_DATA-1:0] o_MemData
); |
wire [clog2(STATES-1)-1:0] state;
wire [clog2(N/2)-1: 0] substate;
wire [clog2(N+1)-1:0] memSelect;
assign o_WAddr = i_WAddr;
assign o_RAddr = i_RAddr;
MUX_ARRAY
#(
.N(N),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.STATES(STATES)
)
u_MUX_ARRAY
(
.i_DataConv(i_DataConv),
.i_MemData(i_MemData),
.i_Data(i_Data),
.i_state(state),
.i_substate(substate),
.i_memSelect(memSelect),
.o_DataConv(o_DataConv),
.o_MemData(o_MemData),
.o_Data(o_Data)
);
MCU_CTRL
#(
.N(N),
.STATES(STATES)
)
u_MCU_CTRL
(
.i_sop(i_sop),
.i_eop(i_eop),
.i_chblk(i_chblk),
.clk(clk),
.rst(rst),
.o_we(o_we),
.o_state(state),
.o_substate(substate),
.o_memSelect(memSelect)
);
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | 18 |
3,499 | data/full_repos/permissive/105269489/src/TEST/All modules v0.0 2 iterations/modules/MCU.v | 105,269,489 | MCU.v | v | 78 | 102 | [] | [] | [] | null | line:73: before: "integer" | null | 1: b'%Error: Cannot find file containing module: modules\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/All/modules\n data/full_repos/permissive/105269489/src/TEST/All/modules.v\n data/full_repos/permissive/105269489/src/TEST/All/modules.sv\n modules\n modules.v\n modules.sv\n obj_dir/modules\n obj_dir/modules.v\n obj_dir/modules.sv\n%Error: Cannot find file containing module: v0.0\n%Error: Cannot find file containing module: 2\n%Error: Cannot find file containing module: iterations/modules,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/TEST/All\n%Error: Cannot find file containing module: iterations/modules/MCU.v\n%Error: Exiting due to 6 error(s)\n' | 1,257 | function | function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | function integer clog2; |
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | 18 |
3,504 | data/full_repos/permissive/105269489/src/TEST/CONV + CONTROL + FSM + MEMORIAS/modulos/micro_all.v | 105,269,489 | micro_all.v | v | 321 | 162 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Invalid Option: +\n' | 1,266 | module | module micro_all#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH_TOP = `RAM_WIDTH_TOP,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEM0 = 1,
localparam MEM1 = 2,
localparam MEM2 = 3,
localparam Kernel_load = 0,
localparam ImgSize_load = 1,
localparam Img_load = 2,
localparam Data_request = 3,
localparam LoadFinish_goToRun = 4
)(
output[GPIO_D-1:0] gpio_i_data_tri_i,
output[2:0] o_led,
input i_CLK,
input [GPIO_D-1:0] gpio_o_data_tri_o
);
reg [RAM_WIDTH_TOP-1:0] i_data_mem0, i_data_mem1, i_data_mem2;
wire signed [RAM_WIDTH_TOP-1:0] mem0_o,mem1_o,mem2_o;
reg wen_0,wen_1,wen_2;
wire [1:0] sel;
wire signed [(BIT_LEN*3)-1:0] dmicro;
reg signed [RAM_WIDTH_TOP-1:0] reg_aux;
wire signed [BIT_LEN-1:0] dato0, dato1, dato2;
wire signed [RAM_WIDTH_TOP-1:0] data_oc;
wire valid_toCONV;
wire [NB_ADDRESS-1:0] writeAddress_fromFSM_toCONV;
wire [NB_ADDRESS-1:0] readAddress_fromFSM_toCONV;
wire load_wire_fromCTRL_toFSM,SOP_fromFSM_wire,valid_fromFSM_toCONV;
reg [23:0] KernelData_latch;
reg [12:0] MCUdata_latch;
wire validGPIO;
wire rst_all;
wire [2:0] GPIOctrl;
wire [23:0] GPIOdata;
wire EOP_fromFSM_toCTRL;
wire [23:0] krnlData_fromCTRL;
wire [9:0]imgLength_fromCTRL_toFSM;
wire [2:0]ledFSM;
wire EoP_to_MCU;
wire SOP_fromCTRL_toFSM;
wire valid_fromCTRL_toFSM;
wire valid_fromCTRL_toCONV;
wire KorI_fromCTRL_toCONV;
wire changeBlock_fromFSM_toMCU;
wire [12:0] output_MCUdata;
wire [31:0] outGPIOctrl;
reg [12:0] inputdata_fromMCU;
assign rst_all = gpio_o_data_tri_o[0];
assign sel[0] = gpio_o_data_tri_o[25];
assign sel[1] = gpio_o_data_tri_o[26];
assign GPIOdata = gpio_o_data_tri_o[24:1];
assign GPIOctrl = gpio_o_data_tri_o[31:29];
assign validGPIO = gpio_o_data_tri_o[28];
assign {o_led} = ledFSM;
assign dato0 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[BIT_LEN:0]:mem0_o[BIT_LEN-1:0];
assign dato1 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[(2*BIT_LEN)-1:BIT_LEN]:mem1_o[BIT_LEN-1:0];
assign dato2 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[(3*BIT_LEN)-1:(2*BIT_LEN)]:mem2_o[BIT_LEN-1:0];
assign gpio_i_data_tri_i[RAM_WIDTH_TOP-1:0] = mem0_o;
assign gpio_i_data_tri_i[GPIO_D-1:RAM_WIDTH_TOP] = 19'h0;
assign valid_toCONV = (GPIOctrl==LoadFinish_goToRun)? valid_fromFSM_toCONV:valid_fromCTRL_toCONV;
initial begin
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
i_data_mem0 = 13'h0;
reg_aux = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b0;
inputdata_fromMCU = 'd0;
KernelData_latch = 'd0;
MCUdata_latch = 'd0;
end
always @(posedge i_CLK) begin
reg_aux <= data_oc;
case(GPIOctrl)
Kernel_load: begin
KernelData_latch<= krnlData_fromCTRL;
end
Data_request: begin
MCUdata_latch<=output_MCUdata;
end
default :;
endcase
end
always @(*) begin
case(sel)
2'b00: begin
i_data_mem0 = reg_aux;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = valid_fromFSM_toCONV;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b01:begin
i_data_mem0 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = 1'b1;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b10:begin
i_data_mem0 = 13'h0;
i_data_mem1 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
i_data_mem2 = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b1;
wen_2 = 1'b0;
end
2'b11:begin
i_data_mem0 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b1;
end
endcase
end
FSMv2
u_fsmv(.o_writeAdd(writeAddress_fromFSM_toCONV),
.o_readAdd(readAddress_fromFSM_toCONV),
.o_EoP(EOP_fromFSM_toCTRL),
.o_changeBlock(changeBlock_fromFSM_toMCU),
.o_valid_fromFSM_toCONV(valid_fromFSM_toCONV),
.o_SOP_fromFSM(SOP_fromFSM_wire),
.i_imgLength(imgLength_fromCTRL_toFSM),
.o_led(ledFSM),
.i_CLK(i_CLK),
.i_reset(rst_all),
.i_SoP(SOP_fromCTRL_toFSM),
.i_valid(valid_fromCTRL_toFSM),
.i_load(load_wire_fromCTRL_toFSM));
Convolutor
u_conv(.o_data(data_oc),
.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(KorI_fromCTRL_toCONV),
.i_reset(rst_all),
.i_valid(valid_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM0))
u_bram_0
(.o_data(mem0_o),
.i_wrEnable(wen_0),
.i_data(i_data_mem0),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM1))
u_bram_1
(.o_data(mem1_o),
.i_wrEnable(wen_1),
.i_data(i_data_mem1),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM2))
u_bram_2
(.o_data(mem2_o),
.i_wrEnable(wen_2),
.i_data(i_data_mem2),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
ControlBlock
u_RegisterFile
(
.i_GPIOdata(GPIOdata),
.i_MCUdata(inputdata_fromMCU),
.i_GPIOctrl(GPIOctrl),
.i_GPIOvalid(validGPIO),
.i_rst(rst_all),
.i_CLK(i_CLK),
.i_EOP_from_FSM(EOP_fromFSM_toCTRL),
.o_GPIOdata(outGPIOctrl),
.o_load(load_wire_fromCTRL_toFSM),
.o_KNLdata(dmicro),
.o_imgLength(imgLength_fromCTRL_toFSM),
.o_EOP_to_MCU(EoP_to_MCU),
.o_run(SOP_fromCTRL_toFSM),
.o_valid_to_FSM(valid_fromCTRL_toFSM),
.o_valid_to_CONV(valid_fromCTRL_toCONV),
.o_KNorIMG(KorI_fromCTRL_toCONV),
.o_MCUdata(output_MCUdata)
);
endmodule | module micro_all#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH_TOP = `RAM_WIDTH_TOP,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEM0 = 1,
localparam MEM1 = 2,
localparam MEM2 = 3,
localparam Kernel_load = 0,
localparam ImgSize_load = 1,
localparam Img_load = 2,
localparam Data_request = 3,
localparam LoadFinish_goToRun = 4
)(
output[GPIO_D-1:0] gpio_i_data_tri_i,
output[2:0] o_led,
input i_CLK,
input [GPIO_D-1:0] gpio_o_data_tri_o
); |
reg [RAM_WIDTH_TOP-1:0] i_data_mem0, i_data_mem1, i_data_mem2;
wire signed [RAM_WIDTH_TOP-1:0] mem0_o,mem1_o,mem2_o;
reg wen_0,wen_1,wen_2;
wire [1:0] sel;
wire signed [(BIT_LEN*3)-1:0] dmicro;
reg signed [RAM_WIDTH_TOP-1:0] reg_aux;
wire signed [BIT_LEN-1:0] dato0, dato1, dato2;
wire signed [RAM_WIDTH_TOP-1:0] data_oc;
wire valid_toCONV;
wire [NB_ADDRESS-1:0] writeAddress_fromFSM_toCONV;
wire [NB_ADDRESS-1:0] readAddress_fromFSM_toCONV;
wire load_wire_fromCTRL_toFSM,SOP_fromFSM_wire,valid_fromFSM_toCONV;
reg [23:0] KernelData_latch;
reg [12:0] MCUdata_latch;
wire validGPIO;
wire rst_all;
wire [2:0] GPIOctrl;
wire [23:0] GPIOdata;
wire EOP_fromFSM_toCTRL;
wire [23:0] krnlData_fromCTRL;
wire [9:0]imgLength_fromCTRL_toFSM;
wire [2:0]ledFSM;
wire EoP_to_MCU;
wire SOP_fromCTRL_toFSM;
wire valid_fromCTRL_toFSM;
wire valid_fromCTRL_toCONV;
wire KorI_fromCTRL_toCONV;
wire changeBlock_fromFSM_toMCU;
wire [12:0] output_MCUdata;
wire [31:0] outGPIOctrl;
reg [12:0] inputdata_fromMCU;
assign rst_all = gpio_o_data_tri_o[0];
assign sel[0] = gpio_o_data_tri_o[25];
assign sel[1] = gpio_o_data_tri_o[26];
assign GPIOdata = gpio_o_data_tri_o[24:1];
assign GPIOctrl = gpio_o_data_tri_o[31:29];
assign validGPIO = gpio_o_data_tri_o[28];
assign {o_led} = ledFSM;
assign dato0 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[BIT_LEN:0]:mem0_o[BIT_LEN-1:0];
assign dato1 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[(2*BIT_LEN)-1:BIT_LEN]:mem1_o[BIT_LEN-1:0];
assign dato2 = (KorI_fromCTRL_toCONV==1'b0)?dmicro[(3*BIT_LEN)-1:(2*BIT_LEN)]:mem2_o[BIT_LEN-1:0];
assign gpio_i_data_tri_i[RAM_WIDTH_TOP-1:0] = mem0_o;
assign gpio_i_data_tri_i[GPIO_D-1:RAM_WIDTH_TOP] = 19'h0;
assign valid_toCONV = (GPIOctrl==LoadFinish_goToRun)? valid_fromFSM_toCONV:valid_fromCTRL_toCONV;
initial begin
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
i_data_mem0 = 13'h0;
reg_aux = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b0;
inputdata_fromMCU = 'd0;
KernelData_latch = 'd0;
MCUdata_latch = 'd0;
end
always @(posedge i_CLK) begin
reg_aux <= data_oc;
case(GPIOctrl)
Kernel_load: begin
KernelData_latch<= krnlData_fromCTRL;
end
Data_request: begin
MCUdata_latch<=output_MCUdata;
end
default :;
endcase
end
always @(*) begin
case(sel)
2'b00: begin
i_data_mem0 = reg_aux;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = valid_fromFSM_toCONV;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b01:begin
i_data_mem0 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = 1'b1;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b10:begin
i_data_mem0 = 13'h0;
i_data_mem1 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
i_data_mem2 = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b1;
wen_2 = 1'b0;
end
2'b11:begin
i_data_mem0 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = gpio_o_data_tri_o[RAM_WIDTH_TOP:1];
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b1;
end
endcase
end
FSMv2
u_fsmv(.o_writeAdd(writeAddress_fromFSM_toCONV),
.o_readAdd(readAddress_fromFSM_toCONV),
.o_EoP(EOP_fromFSM_toCTRL),
.o_changeBlock(changeBlock_fromFSM_toMCU),
.o_valid_fromFSM_toCONV(valid_fromFSM_toCONV),
.o_SOP_fromFSM(SOP_fromFSM_wire),
.i_imgLength(imgLength_fromCTRL_toFSM),
.o_led(ledFSM),
.i_CLK(i_CLK),
.i_reset(rst_all),
.i_SoP(SOP_fromCTRL_toFSM),
.i_valid(valid_fromCTRL_toFSM),
.i_load(load_wire_fromCTRL_toFSM));
Convolutor
u_conv(.o_data(data_oc),
.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(KorI_fromCTRL_toCONV),
.i_reset(rst_all),
.i_valid(valid_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM0))
u_bram_0
(.o_data(mem0_o),
.i_wrEnable(wen_0),
.i_data(i_data_mem0),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM1))
u_bram_1
(.o_data(mem1_o),
.i_wrEnable(wen_1),
.i_data(i_data_mem1),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
bram_memory#(
.INIT(MEM2))
u_bram_2
(.o_data(mem2_o),
.i_wrEnable(wen_2),
.i_data(i_data_mem2),
.i_writeAdd(writeAddress_fromFSM_toCONV),
.i_readAdd(readAddress_fromFSM_toCONV),
.i_CLK(i_CLK));
ControlBlock
u_RegisterFile
(
.i_GPIOdata(GPIOdata),
.i_MCUdata(inputdata_fromMCU),
.i_GPIOctrl(GPIOctrl),
.i_GPIOvalid(validGPIO),
.i_rst(rst_all),
.i_CLK(i_CLK),
.i_EOP_from_FSM(EOP_fromFSM_toCTRL),
.o_GPIOdata(outGPIOctrl),
.o_load(load_wire_fromCTRL_toFSM),
.o_KNLdata(dmicro),
.o_imgLength(imgLength_fromCTRL_toFSM),
.o_EOP_to_MCU(EoP_to_MCU),
.o_run(SOP_fromCTRL_toFSM),
.o_valid_to_FSM(valid_fromCTRL_toFSM),
.o_valid_to_CONV(valid_fromCTRL_toCONV),
.o_KNorIMG(KorI_fromCTRL_toCONV),
.o_MCUdata(output_MCUdata)
);
endmodule | 18 |
3,505 | data/full_repos/permissive/105269489/src/TEST/CONV + CONTROL + FSM + MEMORIAS/modulos/top_microblaze_all.v | 105,269,489 | top_microblaze_all.v | v | 71 | 60 | [] | [] | [] | [(8, 71)] | null | null | 1: b'%Error: Invalid Option: +\n' | 1,267 | module | module top_microblaze_all
(
input i_CLK,
input [3:0] sw,
input [3:0] btn,
output [3:0] o_led,
output uart_rxd_out,
input uart_txd_in,
input ck_rst
);
parameter BITS_ADDRESS= `NB_ADDRESS;
parameter BITS_IMAGE = `NB_IMAGE;
wire [31:0]gpio_i_data_tri_i;
wire [31:0]gpio_o_data_tri_o;
wire rst;
wire sys_clock;
wire uart_rtl_rxd;
wire uart_rtl_txd;
wire [2:0] ledstates;
wire led_warning;
wire valid;
wire reset_sw;
wire clock1;
wire clock2;
assign rst = ck_rst;
assign sys_clock = i_CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign o_led[3] = led_warning;
assign o_led[2:0] = ledstates;
design_1
u_microblaze
(.clock100(clock2),
.gpio_rtl_tri_i(gpio_i_data_tri_i),
.gpio_rtl_tri_o(gpio_o_data_tri_o),
.o_lock_clock(led_warning),
.reset(rst),
.sys_clock(sys_clock),
.usb_uart_rxd(uart_rtl_rxd),
.usb_uart_txd(uart_rtl_txd)
);
micro_all
u_topMicro(
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(ledstates),
.i_CLK(clock2),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule | module top_microblaze_all
(
input i_CLK,
input [3:0] sw,
input [3:0] btn,
output [3:0] o_led,
output uart_rxd_out,
input uart_txd_in,
input ck_rst
); |
parameter BITS_ADDRESS= `NB_ADDRESS;
parameter BITS_IMAGE = `NB_IMAGE;
wire [31:0]gpio_i_data_tri_i;
wire [31:0]gpio_o_data_tri_o;
wire rst;
wire sys_clock;
wire uart_rtl_rxd;
wire uart_rtl_txd;
wire [2:0] ledstates;
wire led_warning;
wire valid;
wire reset_sw;
wire clock1;
wire clock2;
assign rst = ck_rst;
assign sys_clock = i_CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign o_led[3] = led_warning;
assign o_led[2:0] = ledstates;
design_1
u_microblaze
(.clock100(clock2),
.gpio_rtl_tri_i(gpio_i_data_tri_i),
.gpio_rtl_tri_o(gpio_o_data_tri_o),
.o_lock_clock(led_warning),
.reset(rst),
.sys_clock(sys_clock),
.usb_uart_rxd(uart_rtl_rxd),
.usb_uart_txd(uart_rtl_txd)
);
micro_all
u_topMicro(
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(ledstates),
.i_CLK(clock2),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule | 18 |
3,506 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/bram_memory.v | 105,269,489 | bram_memory.v | v | 98 | 81 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf3 in position 227: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/bram_memory.v:35: Operator NEQ expects 72 bits on the RHS, but RHS\'s CONST \'?1?h0\' generates 1 bits.\n : ... In instance bram_memory\n if (INIT_FILE != "") begin: use_init_file\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 1,273 | module | module bram_memory#(
parameter RAM_WIDTH = `RAM_WIDTH,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter INIT = `INIT,
parameter INIT_FILE = "mem_0.txt",
localparam RAM_DEPTH=(2**NB_ADDRESS)-1
)(
output [RAM_WIDTH-1:0] o_data,
input i_wrEnable,
input i_CLK,
input [NB_ADDRESS-1:0] i_writeAdd,
input [NB_ADDRESS-1:0] i_readAdd,
input [RAM_WIDTH - 1:0] i_data
);
reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH:0];
reg [RAM_WIDTH-1:0] dout_reg;
integer ram_index;
generate
if (INIT_FILE != "") begin: use_init_file
initial begin
case (INIT)
1: $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
2: $readmemh("mem_1.txt", BRAM, 0, RAM_DEPTH);
3: $readmemh("mem_2.txt", BRAM, 0, RAM_DEPTH);
default: begin
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endcase
end
end
else begin: init_bram_to_zero
initial
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endgenerate
always @(posedge i_CLK) begin
dout_reg<=BRAM[i_readAdd];
if(i_wrEnable) begin
BRAM[i_writeAdd]<=i_data;
end
end
assign{o_data}= dout_reg;
endmodule | module bram_memory#(
parameter RAM_WIDTH = `RAM_WIDTH,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter INIT = `INIT,
parameter INIT_FILE = "mem_0.txt",
localparam RAM_DEPTH=(2**NB_ADDRESS)-1
)(
output [RAM_WIDTH-1:0] o_data,
input i_wrEnable,
input i_CLK,
input [NB_ADDRESS-1:0] i_writeAdd,
input [NB_ADDRESS-1:0] i_readAdd,
input [RAM_WIDTH - 1:0] i_data
); |
reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH:0];
reg [RAM_WIDTH-1:0] dout_reg;
integer ram_index;
generate
if (INIT_FILE != "") begin: use_init_file
initial begin
case (INIT)
1: $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
2: $readmemh("mem_1.txt", BRAM, 0, RAM_DEPTH);
3: $readmemh("mem_2.txt", BRAM, 0, RAM_DEPTH);
default: begin
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endcase
end
end
else begin: init_bram_to_zero
initial
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endgenerate
always @(posedge i_CLK) begin
dout_reg<=BRAM[i_readAdd];
if(i_wrEnable) begin
BRAM[i_writeAdd]<=i_data;
end
end
assign{o_data}= dout_reg;
endmodule | 18 |
3,508 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v | 105,269,489 | tb_topmicro.v | v | 83 | 59 | [] | [] | [] | null | line:72: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20 gpio_o_data_tri_o = 32\'h1E;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:34: Unsupported: Ignoring delay on this delayed statement.\n #3210 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:35: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:36: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:41: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:51: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:56: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:57: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:60: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:61: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:62: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:63: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:65: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:66: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:67: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:68: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:69: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:71: Unsupported: Ignoring delay on this delayed statement.\n #5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32\'h100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:72: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:76: Unsupported: Ignoring delay on this delayed statement.\n always #2.5 CLK100MHZ = ~CLK100MHZ;\n ^\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/tb_topmicro.v:77: Cannot find file containing module: \'micro_sim\'\n micro_sim\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/micro_sim\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/micro_sim.v\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/micro_sim.sv\n micro_sim\n micro_sim.v\n micro_sim.sv\n obj_dir/micro_sim\n obj_dir/micro_sim.v\n obj_dir/micro_sim.sv\n%Error: Exiting due to 1 error(s), 41 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,277 | module | module tb_topmicro#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
)();
wire [GPIO_D-1:0] gpio_i_data_tri_i;
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'h9;
#20 gpio_o_data_tri_o = 32'h1E;
#3210 gpio_o_data_tri_o = 32'h0;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#20 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim
u_micro_sim(.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o));
endmodule | module tb_topmicro#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
)(); |
wire [GPIO_D-1:0] gpio_i_data_tri_i;
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'h9;
#20 gpio_o_data_tri_o = 32'h1E;
#3210 gpio_o_data_tri_o = 32'h0;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#5 gpio_o_data_tri_o = gpio_o_data_tri_o + 32'h100;
#20 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim
u_micro_sim(.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o));
endmodule | 18 |
3,510 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v | 105,269,489 | test_Conv.v | v | 164 | 81 | [] | [] | [] | null | line:119: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 rst = 1\'b0; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:42: Unsupported: Ignoring delay on this delayed statement.\n #5 valid = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 dato0 = 8\'b00100000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5dato0 = 8\'b00000000; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5 KI = 1\'b1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5 valid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:65: Unsupported: Ignoring delay on this delayed statement.\n #5dato0 = 8\'b01111111;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5dato0 = 8\'b01111110; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:75: Unsupported: Ignoring delay on this delayed statement.\n #5 valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:78: Unsupported: Ignoring delay on this delayed statement.\n #5 valid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:80: Unsupported: Ignoring delay on this delayed statement.\n #25dato0 = 8\'b01111111; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:84: Unsupported: Ignoring delay on this delayed statement.\n #45dato0 = 8\'b01111110; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:88: Unsupported: Ignoring delay on this delayed statement.\n #30dato0 = 8\'b01111111; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:92: Unsupported: Ignoring delay on this delayed statement.\n #20dato0 = 8\'b01111110; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:96: Unsupported: Ignoring delay on this delayed statement.\n #15dato0 = 8\'b01111101; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10dato0 = 8\'b01111110; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:104: Unsupported: Ignoring delay on this delayed statement.\n #5dato0 = 8\'b01111111; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10 valid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:119: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:122: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 CLK100MHZ = ~CLK100MHZ;\n ^\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test/test_Conv.v:124: Cannot find file containing module: \'Conv\'\nConv\n^~~~\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv.v\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV/Verilog/test,data/full_repos/permissive/105269489/Conv.sv\n Conv\n Conv.v\n Conv.sv\n obj_dir/Conv\n obj_dir/Conv.v\n obj_dir/Conv.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,279 | module | module test_Conv #(
parameter BIT_LEN =`BIT_LEN,
parameter CONV_LEN =`CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN
)();
reg signed [BIT_LEN-1:0]dato0;
reg signed [BIT_LEN-1:0]dato1;
reg signed [BIT_LEN-1:0]dato2;
reg CLK100MHZ;
reg KI;
reg rst;
reg valid;
wire [CONV_LPOS-1:0] data;
initial begin
CLK100MHZ = 1'b1;
dato0 = 8'b00000000;
dato1 = 8'b00100000;
dato2 = 8'b00000000;
rst = 1'b1;
valid = 1'b0;
KI = 1'b0;
#5 rst = 1'b0;
#5 valid = 1'b1;
#5 dato0 = 8'b00100000;
dato1 = 8'b10000000;
dato2 = 8'b00100000;
#5dato0 = 8'b00000000;
dato1 = 8'b00100000;
dato2 = 8'b00000000;
#5 valid = 1'b0;
#5 KI = 1'b1;
#5 valid = 1'b1;
dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#5dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#5dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#5 valid = 1'b0;
#5 valid = 1'b1;
#25dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#45dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#30dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#20dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#15dato0 = 8'b01111101;
dato1 = 8'b01111101;
dato2 = 8'b01111101;
#10dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#5dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#10 valid = 1'b0;
KI = 1'b0;
#20 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
Conv
u_conv(.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(KI),
.i_reset(rst),
.i_valid(valid),
.CLK100MHZ(CLK100MHZ),
.o_data(data));
endmodule | module test_Conv #(
parameter BIT_LEN =`BIT_LEN,
parameter CONV_LEN =`CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN
)(); |
reg signed [BIT_LEN-1:0]dato0;
reg signed [BIT_LEN-1:0]dato1;
reg signed [BIT_LEN-1:0]dato2;
reg CLK100MHZ;
reg KI;
reg rst;
reg valid;
wire [CONV_LPOS-1:0] data;
initial begin
CLK100MHZ = 1'b1;
dato0 = 8'b00000000;
dato1 = 8'b00100000;
dato2 = 8'b00000000;
rst = 1'b1;
valid = 1'b0;
KI = 1'b0;
#5 rst = 1'b0;
#5 valid = 1'b1;
#5 dato0 = 8'b00100000;
dato1 = 8'b10000000;
dato2 = 8'b00100000;
#5dato0 = 8'b00000000;
dato1 = 8'b00100000;
dato2 = 8'b00000000;
#5 valid = 1'b0;
#5 KI = 1'b1;
#5 valid = 1'b1;
dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#5dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#5dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#5 valid = 1'b0;
#5 valid = 1'b1;
#25dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#45dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#30dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#20dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#15dato0 = 8'b01111101;
dato1 = 8'b01111101;
dato2 = 8'b01111101;
#10dato0 = 8'b01111110;
dato1 = 8'b01111110;
dato2 = 8'b01111110;
#5dato0 = 8'b01111111;
dato1 = 8'b01111111;
dato2 = 8'b01111111;
#10 valid = 1'b0;
KI = 1'b0;
#20 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
Conv
u_conv(.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(KI),
.i_reset(rst),
.i_valid(valid),
.CLK100MHZ(CLK100MHZ),
.o_data(data));
endmodule | 18 |
3,511 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v | 105,269,489 | micro_fms.v | v | 209 | 90 | [] | [] | [] | null | line:21: before: "localparam" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:90: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance Micro_fms\n dmicro0 = 13\'h0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:91: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance Micro_fms\n dmicro1 = 13\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:92: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance Micro_fms\n dmicro2 = 13\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:106: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 13 bits.\n : ... In instance Micro_fms\n imgLength <= gpio_o_data_tri_o[RAM_WIDTH+7:8];\n ^~\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:151: Cannot find file containing module: \'Fsmv\'\n Fsmv#( .NB_ADDRESS(NB_ADDRESS),\n ^~~~\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog,data/full_repos/permissive/105269489/Fsmv\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog,data/full_repos/permissive/105269489/Fsmv.v\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog,data/full_repos/permissive/105269489/Fsmv.sv\n Fsmv\n Fsmv.v\n Fsmv.sv\n obj_dir/Fsmv\n obj_dir/Fsmv.v\n obj_dir/Fsmv.sv\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:168: Cannot find file containing module: \'Conv\'\n Conv\n ^~~~\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:179: Cannot find file containing module: \'bram_memory\'\n bram_memory#(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:189: Cannot find file containing module: \'bram_memory\'\n bram_memory#(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/micro_fms.v:198: Cannot find file containing module: \'bram_memory\'\n bram_memory#(\n ^~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n' | 1,283 | module | module Micro_fms#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEM0 = 1,
localparam MEM1 = 2,
localparam MEM2 = 3
)(
output[GPIO_D-1:0] gpio_i_data_tri_i,
output[3:0] o_led,
input CLK100MHZ,
input [GPIO_D-1:0] gpio_o_data_tri_o
);
reg [RAM_WIDTH-1:0] i_data_mem0, i_data_mem1, i_data_mem2;
wire signed [RAM_WIDTH-1:0] mem0_o,mem1_o,mem2_o;
reg wen_0,wen_1,wen_2;
wire rstm;
wire [1:0] sel;
reg signed [BIT_LEN-1:0] dmicro0,dmicro1,dmicro2;
reg signed [RAM_WIDTH-1:0] reg_aux;
wire k_i;
wire valid_conv;
wire rst_conv;
wire signed [BIT_LEN-1:0] dato0, dato1, dato2;
wire signed [RAM_WIDTH-1:0] data_oc;
reg [NB_IMAGE-1:0] imgLength;
wire [NB_ADDRESS-1:0] write_add_fsm2conv;
wire [NB_ADDRESS-1:0] read_add_fsm2conv;
wire rst_fsm, valid_fsm, sop, load;
assign rst_conv = gpio_o_data_tri_o[0];
assign k_i = gpio_o_data_tri_o[1];
assign rst_fsm = gpio_o_data_tri_o[2];
assign sop = gpio_o_data_tri_o[3];
assign valid_fsm = gpio_o_data_tri_o[4];
assign sel[0] = gpio_o_data_tri_o[5];
assign sel[1] = gpio_o_data_tri_o[6];
assign load = gpio_o_data_tri_o[7];
assign dato0 = (k_i==1'b0)?dmicro0:mem0_o[BIT_LEN-1:0];
assign dato1 = (k_i==1'b0)?dmicro1:mem1_o[BIT_LEN-1:0];
assign dato2 = (k_i==1'b0)?dmicro2:mem2_o[BIT_LEN-1:0];
assign {o_led[3],o_led[0]} = {1'b0, wen_0};
assign gpio_i_data_tri_i[RAM_WIDTH-1:0] = mem0_o;
assign gpio_i_data_tri_i[GPIO_D-1:RAM_WIDTH] = 19'h0;
initial begin
dmicro0 = 13'h0;
dmicro1 = 13'h0;
dmicro2 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
i_data_mem0 = 13'h0;
imgLength = 10'd10;
reg_aux = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
always @(posedge CLK100MHZ) begin
reg_aux <= data_oc;
if(rst_fsm)
imgLength <= gpio_o_data_tri_o[RAM_WIDTH+7:8];
else
imgLength <= imgLength;
end
always @(*) begin
case(sel)
2'b00: begin
i_data_mem0 = reg_aux;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = valid_conv;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b01:begin
i_data_mem0 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = 1'b1;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b10:begin
i_data_mem0 = 13'h0;
i_data_mem1 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
i_data_mem2 = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b1;
wen_2 = 1'b0;
end
2'b11:begin
i_data_mem0 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b1;
end
endcase
end
Fsmv#( .NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE(NB_IMAGE),
.LATENCIA(6))
u_fsmv(.o_writeAdd(write_add_fsm2conv),
.o_readAdd(read_add_fsm2conv),
.o_EoP(o_led[2]),
.o_sopross(o_led[1]),
.o_fms2conVld(valid_conv),
.i_imgLength(imgLength),
.i_CLK(CLK100MHZ),
.i_reset(rst_fsm),
.i_SoP(sop),
.i_valid(valid_fsm),
.i_load(load));
Conv
u_conv(.o_data(data_oc),
.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(k_i),
.i_reset(rst_conv),
.i_valid(valid_conv),
.CLK100MHZ(CLK100MHZ));
bram_memory#(
.INIT(MEM0))
u_bram_0
(.o_data(mem0_o),
.i_wrEnable(wen_0),
.i_data(i_data_mem0),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
bram_memory#(
.INIT(MEM1))
u_bram_1(.o_data(mem1_o),
.i_wrEnable(wen_1),
.i_data(i_data_mem1),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
bram_memory#(
.INIT(MEM2))
u_bram_2(.o_data(mem2_o),
.i_wrEnable(wen_2),
.i_data(i_data_mem2),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
endmodule | module Micro_fms#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEM0 = 1,
localparam MEM1 = 2,
localparam MEM2 = 3
)(
output[GPIO_D-1:0] gpio_i_data_tri_i,
output[3:0] o_led,
input CLK100MHZ,
input [GPIO_D-1:0] gpio_o_data_tri_o
); |
reg [RAM_WIDTH-1:0] i_data_mem0, i_data_mem1, i_data_mem2;
wire signed [RAM_WIDTH-1:0] mem0_o,mem1_o,mem2_o;
reg wen_0,wen_1,wen_2;
wire rstm;
wire [1:0] sel;
reg signed [BIT_LEN-1:0] dmicro0,dmicro1,dmicro2;
reg signed [RAM_WIDTH-1:0] reg_aux;
wire k_i;
wire valid_conv;
wire rst_conv;
wire signed [BIT_LEN-1:0] dato0, dato1, dato2;
wire signed [RAM_WIDTH-1:0] data_oc;
reg [NB_IMAGE-1:0] imgLength;
wire [NB_ADDRESS-1:0] write_add_fsm2conv;
wire [NB_ADDRESS-1:0] read_add_fsm2conv;
wire rst_fsm, valid_fsm, sop, load;
assign rst_conv = gpio_o_data_tri_o[0];
assign k_i = gpio_o_data_tri_o[1];
assign rst_fsm = gpio_o_data_tri_o[2];
assign sop = gpio_o_data_tri_o[3];
assign valid_fsm = gpio_o_data_tri_o[4];
assign sel[0] = gpio_o_data_tri_o[5];
assign sel[1] = gpio_o_data_tri_o[6];
assign load = gpio_o_data_tri_o[7];
assign dato0 = (k_i==1'b0)?dmicro0:mem0_o[BIT_LEN-1:0];
assign dato1 = (k_i==1'b0)?dmicro1:mem1_o[BIT_LEN-1:0];
assign dato2 = (k_i==1'b0)?dmicro2:mem2_o[BIT_LEN-1:0];
assign {o_led[3],o_led[0]} = {1'b0, wen_0};
assign gpio_i_data_tri_i[RAM_WIDTH-1:0] = mem0_o;
assign gpio_i_data_tri_i[GPIO_D-1:RAM_WIDTH] = 19'h0;
initial begin
dmicro0 = 13'h0;
dmicro1 = 13'h0;
dmicro2 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
i_data_mem0 = 13'h0;
imgLength = 10'd10;
reg_aux = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
always @(posedge CLK100MHZ) begin
reg_aux <= data_oc;
if(rst_fsm)
imgLength <= gpio_o_data_tri_o[RAM_WIDTH+7:8];
else
imgLength <= imgLength;
end
always @(*) begin
case(sel)
2'b00: begin
i_data_mem0 = reg_aux;
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = valid_conv;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b01:begin
i_data_mem0 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
i_data_mem1 = 13'h0;
i_data_mem2 = 13'h0;
wen_0 = 1'b1;
wen_1 = 1'b0;
wen_2 = 1'b0;
end
2'b10:begin
i_data_mem0 = 13'h0;
i_data_mem1 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
i_data_mem2 = 13'h0;
wen_0 = 1'b0;
wen_1 = 1'b1;
wen_2 = 1'b0;
end
2'b11:begin
i_data_mem0 = 13'h0;
i_data_mem1 = 13'h0;
i_data_mem2 = gpio_o_data_tri_o[RAM_WIDTH+7:8];
wen_0 = 1'b0;
wen_1 = 1'b0;
wen_2 = 1'b1;
end
endcase
end
Fsmv#( .NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE(NB_IMAGE),
.LATENCIA(6))
u_fsmv(.o_writeAdd(write_add_fsm2conv),
.o_readAdd(read_add_fsm2conv),
.o_EoP(o_led[2]),
.o_sopross(o_led[1]),
.o_fms2conVld(valid_conv),
.i_imgLength(imgLength),
.i_CLK(CLK100MHZ),
.i_reset(rst_fsm),
.i_SoP(sop),
.i_valid(valid_fsm),
.i_load(load));
Conv
u_conv(.o_data(data_oc),
.i_dato0(dato0),
.i_dato1(dato1),
.i_dato2(dato2),
.i_selecK_I(k_i),
.i_reset(rst_conv),
.i_valid(valid_conv),
.CLK100MHZ(CLK100MHZ));
bram_memory#(
.INIT(MEM0))
u_bram_0
(.o_data(mem0_o),
.i_wrEnable(wen_0),
.i_data(i_data_mem0),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
bram_memory#(
.INIT(MEM1))
u_bram_1(.o_data(mem1_o),
.i_wrEnable(wen_1),
.i_data(i_data_mem1),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
bram_memory#(
.INIT(MEM2))
u_bram_2(.o_data(mem2_o),
.i_wrEnable(wen_2),
.i_data(i_data_mem2),
.i_writeAdd(write_add_fsm2conv),
.i_readAdd(read_add_fsm2conv),
.i_CLK(CLK100MHZ));
endmodule | 18 |
3,512 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v | 105,269,489 | tb_microfsmv.v | v | 202 | 69 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20 gpio_o_data_tri_o = 32\'h1b705;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:41: Unsupported: Ignoring delay on this delayed statement.\n #20 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:161: Unsupported: Ignoring delay on this delayed statement.\n #500 gpio_o_data_tri_o = 32\'h0A;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:162: Unsupported: Ignoring delay on this delayed statement.\n #500 gpio_o_data_tri_o = 32\'h02;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:165: Unsupported: Ignoring delay on this delayed statement.\n #1500 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:166: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:167: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:168: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:169: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:170: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:171: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:172: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:173: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:174: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:175: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:176: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:177: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:178: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:179: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:181: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:182: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:183: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:184: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:187: Unsupported: Ignoring delay on this delayed statement.\n #10 gpio_o_data_tri_o = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:190: Unsupported: Ignoring delay on this delayed statement.\n #200 $finish; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:192: Unsupported: Ignoring delay on this delayed statement.\n always #2.5 CLK100MHZ=~CLK100MHZ;\n ^\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb/tb_microfsmv.v:194: Cannot find file containing module: \'Micro_fms\'\n Micro_fms\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb,data/full_repos/permissive/105269489/Micro_fms\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb,data/full_repos/permissive/105269489/Micro_fms.v\n data/full_repos/permissive/105269489/src/TEST/MEM_CONV_FMS/verliog/tb,data/full_repos/permissive/105269489/Micro_fms.sv\n Micro_fms\n Micro_fms.v\n Micro_fms.sv\n obj_dir/Micro_fms\n obj_dir/Micro_fms.v\n obj_dir/Micro_fms.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,286 | module | module tb_microfsmv# (
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEMO = 1,
localparam MEM1 = 2,
localparam MEM2 = 3)
();
reg[GPIO_D-1:0] gpio_o_data_tri_o;
reg CLK100MHZ;
wire[GPIO_D-1:0] gpio_i_data_tri_i;
wire[3:0] led;
initial begin
CLK100MHZ = 1;
gpio_o_data_tri_o = 32'h5;
#20 gpio_o_data_tri_o = 32'h1b705;
#20 gpio_o_data_tri_o = 32'h0;
#500 gpio_o_data_tri_o = 32'h0A;
#500 gpio_o_data_tri_o = 32'h02;
#1500 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#200 $finish;
end
always #2.5 CLK100MHZ=~CLK100MHZ;
Micro_fms
u_micro_fsm(
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(led),
.CLK100MHZ(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule | module tb_microfsmv# (
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter NB_IMAGE = `NB_IMAGE,
localparam MEMO = 1,
localparam MEM1 = 2,
localparam MEM2 = 3)
(); |
reg[GPIO_D-1:0] gpio_o_data_tri_o;
reg CLK100MHZ;
wire[GPIO_D-1:0] gpio_i_data_tri_i;
wire[3:0] led;
initial begin
CLK100MHZ = 1;
gpio_o_data_tri_o = 32'h5;
#20 gpio_o_data_tri_o = 32'h1b705;
#20 gpio_o_data_tri_o = 32'h0;
#500 gpio_o_data_tri_o = 32'h0A;
#500 gpio_o_data_tri_o = 32'h02;
#1500 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#10 gpio_o_data_tri_o = 32'h10;
#10 gpio_o_data_tri_o = 32'h0;
#200 $finish;
end
always #2.5 CLK100MHZ=~CLK100MHZ;
Micro_fms
u_micro_fsm(
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(led),
.CLK100MHZ(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o)
);
endmodule | 18 |
3,513 | data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v | 105,269,489 | tb_micro_sim.v | v | 127 | 86 | [] | [] | [] | null | line:25: before: "[" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:39: Unsupported: Ignoring delay on this delayed statement.\n #100 rst = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:42: Unsupported: Ignoring delay on this delayed statement.\n #200 i_GPIOctrl = 3\'b000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:46: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:48: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOdata = 24\'h208020;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:52: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOdata = 24\'h002000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:57: Unsupported: Ignoring delay on this delayed statement.\n #500 i_GPIOctrl = 3\'b001;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:67: Unsupported: Ignoring delay on this delayed statement.\n #500 i_GPIOctrl = 3\'b010;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:80: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOctrl = 100; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:81: Unsupported: Ignoring delay on this delayed statement.\n #100 $fscanf(file[j], "%h", i_GPIOdata);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:82: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:83: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b0;\n ^\n%Error: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:91: Unsupported: wait statements\n wait(o_led);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:92: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOctrl = 011;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:103: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:104: Unsupported: Ignoring delay on this delayed statement.\n #100 i_GPIOvalid = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/105269489/src/TEST/MEM_CONV_MCU/tb_micro_sim.v:114: Unsupported: Ignoring delay on this delayed statement.\n always #2 CLK100MHZ = ~CLK100MHZ;\n ^\n%Error: Exiting due to 1 error(s), 21 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,288 | module | module micro_sim_tb();
parameter GPIO_D = `GPIO_D;
parameter N = 4;
parameter IMG_SIZE = 439;
localparam PATH = "/home/ivan/XilinxProjects/2dconv-FPGA/src/TEST/MEM_CONV_MCU/";
localparam FILENAME = "mem0";
localparam OUTFNAME = "out_mem0";
wire [GPIO_D-1:0] gpio_i_data_tri_i;
wire o_led;
reg CLK100MHZ;
wire [GPIO_D-1:0] gpio_o_data_tri_o;
reg [23:0] i_GPIOdata;
reg [2:0] i_GPIOctrl;
reg i_GPIOvalid;
reg rst;
integer i, j, k, aux, aux_name;
integer file[0:N+1];
assign gpio_o_data_tri_o = {i_GPIOctrl,i_GPIOvalid, 3'b0, i_GPIOdata, rst};
initial begin
CLK100MHZ = 1'b0;
i_GPIOdata = 24'b0;
i_GPIOctrl = 3'b0;
i_GPIOvalid = 1'b0;
rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#200 i_GPIOctrl = 3'b000;
i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h208020;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#500 i_GPIOctrl = 3'b001;
i_GPIOdata = IMG_SIZE;
for(k = 0; k < 2; k = k+1) begin
if(k == 0)
aux = N+2;
else
aux = N;
#500 i_GPIOctrl = 3'b010;
for (j = 0; j < aux; j = j+1) begin
if(k == 0)
file[j] = $fopen({PATH, FILENAME+j,".txt"}, "r");
else
file[j] = $fopen({PATH, FILENAME+N+2+j+aux*(k-1),".txt"}, "r");
if(!file[j]) begin
$display("Error abriendo archivo");
$stop;
end else begin
for (i = 0; i <= IMG_SIZE; i = i+1) begin
if(i == IMG_SIZE && j == aux-1)
#100 i_GPIOctrl = 100;
#100 $fscanf(file[j], "%h", i_GPIOdata);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
end
end
for (j = 0; j < N+2; j = j+1) begin
$fclose(file[j]);
end
wait(o_led);
#100 i_GPIOctrl = 011;
for (j = 0; j < N; j = j+1) begin
file[j] = $fopen({PATH, OUTFNAME+j+k*N,".txt"}, "w");
end
j = 0;
for (i = 0; i < N*(IMG_SIZE-1); i = i+1) begin
if (i % (IMG_SIZE-1) == 0 && i > IMG_SIZE-2) begin
j = j+1;
$display("Paso a memoria %d", j);
end
$fwrite(file[j], "%h\n", gpio_i_data_tri_i[12:0]);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
for (j = 0; j < N; j = j+1) begin
$fclose(file[j]);
end
end
$finish;
end
always #2 CLK100MHZ = ~CLK100MHZ;
micro_sim#(.N(N))
u_micro
(
.gpio_o_data_tri_o(gpio_o_data_tri_o),
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ)
);
endmodule | module micro_sim_tb(); |
parameter GPIO_D = `GPIO_D;
parameter N = 4;
parameter IMG_SIZE = 439;
localparam PATH = "/home/ivan/XilinxProjects/2dconv-FPGA/src/TEST/MEM_CONV_MCU/";
localparam FILENAME = "mem0";
localparam OUTFNAME = "out_mem0";
wire [GPIO_D-1:0] gpio_i_data_tri_i;
wire o_led;
reg CLK100MHZ;
wire [GPIO_D-1:0] gpio_o_data_tri_o;
reg [23:0] i_GPIOdata;
reg [2:0] i_GPIOctrl;
reg i_GPIOvalid;
reg rst;
integer i, j, k, aux, aux_name;
integer file[0:N+1];
assign gpio_o_data_tri_o = {i_GPIOctrl,i_GPIOvalid, 3'b0, i_GPIOdata, rst};
initial begin
CLK100MHZ = 1'b0;
i_GPIOdata = 24'b0;
i_GPIOctrl = 3'b0;
i_GPIOvalid = 1'b0;
rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#200 i_GPIOctrl = 3'b000;
i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h208020;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#500 i_GPIOctrl = 3'b001;
i_GPIOdata = IMG_SIZE;
for(k = 0; k < 2; k = k+1) begin
if(k == 0)
aux = N+2;
else
aux = N;
#500 i_GPIOctrl = 3'b010;
for (j = 0; j < aux; j = j+1) begin
if(k == 0)
file[j] = $fopen({PATH, FILENAME+j,".txt"}, "r");
else
file[j] = $fopen({PATH, FILENAME+N+2+j+aux*(k-1),".txt"}, "r");
if(!file[j]) begin
$display("Error abriendo archivo");
$stop;
end else begin
for (i = 0; i <= IMG_SIZE; i = i+1) begin
if(i == IMG_SIZE && j == aux-1)
#100 i_GPIOctrl = 100;
#100 $fscanf(file[j], "%h", i_GPIOdata);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
end
end
for (j = 0; j < N+2; j = j+1) begin
$fclose(file[j]);
end
wait(o_led);
#100 i_GPIOctrl = 011;
for (j = 0; j < N; j = j+1) begin
file[j] = $fopen({PATH, OUTFNAME+j+k*N,".txt"}, "w");
end
j = 0;
for (i = 0; i < N*(IMG_SIZE-1); i = i+1) begin
if (i % (IMG_SIZE-1) == 0 && i > IMG_SIZE-2) begin
j = j+1;
$display("Paso a memoria %d", j);
end
$fwrite(file[j], "%h\n", gpio_i_data_tri_i[12:0]);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
for (j = 0; j < N; j = j+1) begin
$fclose(file[j]);
end
end
$finish;
end
always #2 CLK100MHZ = ~CLK100MHZ;
micro_sim#(.N(N))
u_micro
(
.gpio_o_data_tri_o(gpio_o_data_tri_o),
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ)
);
endmodule | 18 |
3,515 | data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v | 105,269,489 | Convolutor.v | v | 121 | 107 | [] | [] | [] | null | line:13: before: "localparam" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:108: Operator ADD expects 18 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n : ... In instance Convolutor\n parcial0 = parcial0 + array_prod[ptr0];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:115: Operator ADD expects 18 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n : ... In instance Convolutor\n parcial1 = parcial1 + array_prod[4+ptr1]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the LHS, but LHS\'s VARREF \'parcial0\' generates 18 bits.\n : ... In instance Convolutor\n assign resultado = parcial0 + parcial1 + array_prod[8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s VARREF \'parcial1\' generates 18 bits.\n : ... In instance Convolutor\n assign resultado = parcial0 + parcial1 + array_prod[8];\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/Convolutor/Convolutor.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s ARRAYSEL generates 16 bits.\n : ... In instance Convolutor\n assign resultado = parcial0 + parcial1 + array_prod[8];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 1,295 | module | module Convolutor #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
localparam BIT_ARRAY = BIT_LEN*M_LEN
)(
output [CONV_LPOS-1:0] o_data,
input [BIT_LEN-1:0] i_dato0,
input [BIT_LEN-1:0] i_dato1,
input [BIT_LEN-1:0] i_dato2,
input i_selecK_I,
input i_reset,
input i_valid,
input i_CLK
);
reg signed [BIT_ARRAY-1:0] kernel [0:M_LEN-1];
reg signed [BIT_ARRAY-1:0] imagen [0:M_LEN-1];
reg signed [CONV_LPOS-1:0] conv_reg;
reg signed [CONV_LEN-3:0] parcial0,parcial1;
wire signed [CONV_LEN-1:0] resultado;
reg signed [(2*BIT_LEN)-1:0] array_prod [0:(M_LEN*M_LEN)-1];
integer ptr0 , ptr1, i;
integer shift;
assign {o_data[CONV_LPOS-1],o_data[CONV_LPOS-2:0]}= {~conv_reg[CONV_LPOS-1], conv_reg[CONV_LPOS-2:0]};
always @( posedge i_CLK) begin
if(i_reset) begin
for(shift=0; shift < M_LEN; shift = shift +1) begin
imagen[shift]<={BIT_ARRAY{1'b0}};
kernel[shift]<={BIT_ARRAY{1'b0}};
end
conv_reg<={CONV_LPOS{1'b0}};
end
else if(i_valid)begin
case (i_selecK_I)
1'b1: begin
for( shift = 0; shift < M_LEN-1; shift = shift +1)
imagen[shift]<=imagen[shift+1];
imagen[M_LEN-1]<={i_dato2,i_dato1,i_dato0};
conv_reg<= resultado[CONV_LEN-2:CONV_LEN-CONV_LPOS-1];
end
1'b0: begin
for( shift = 0; shift < M_LEN-1; shift = shift +1)
kernel[shift]<=kernel[shift+1];
kernel[M_LEN-1]<={i_dato2,i_dato1,i_dato0};
conv_reg<=conv_reg;
end
endcase
end
else begin
for (shift =0 ; shift<M_LEN;shift=shift+1) begin: elseequ
imagen[shift]<=imagen[shift];
kernel[shift]<=kernel[shift];
end
conv_reg<=conv_reg;
end
end
always@(posedge i_CLK)
for(i = 0 ; i < (M_LEN*M_LEN) ; i=i+1) begin
array_prod[i] =
$signed(kernel[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN])*
$signed(imagen[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN]);
end
always @(*) begin
parcial0=0;
for(ptr0 = 0 ; ptr0 < 4; ptr0 = ptr0 +1)begin
parcial0 = parcial0 + array_prod[ptr0];
end
end
always @(*) begin
parcial1=0;
for(ptr1 = 0 ; ptr1 < 4; ptr1 = ptr1 +1)begin
parcial1 = parcial1 + array_prod[4+ptr1];
end
end
assign resultado = parcial0 + parcial1 + array_prod[8];
endmodule | module Convolutor #(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
localparam BIT_ARRAY = BIT_LEN*M_LEN
)(
output [CONV_LPOS-1:0] o_data,
input [BIT_LEN-1:0] i_dato0,
input [BIT_LEN-1:0] i_dato1,
input [BIT_LEN-1:0] i_dato2,
input i_selecK_I,
input i_reset,
input i_valid,
input i_CLK
); |
reg signed [BIT_ARRAY-1:0] kernel [0:M_LEN-1];
reg signed [BIT_ARRAY-1:0] imagen [0:M_LEN-1];
reg signed [CONV_LPOS-1:0] conv_reg;
reg signed [CONV_LEN-3:0] parcial0,parcial1;
wire signed [CONV_LEN-1:0] resultado;
reg signed [(2*BIT_LEN)-1:0] array_prod [0:(M_LEN*M_LEN)-1];
integer ptr0 , ptr1, i;
integer shift;
assign {o_data[CONV_LPOS-1],o_data[CONV_LPOS-2:0]}= {~conv_reg[CONV_LPOS-1], conv_reg[CONV_LPOS-2:0]};
always @( posedge i_CLK) begin
if(i_reset) begin
for(shift=0; shift < M_LEN; shift = shift +1) begin
imagen[shift]<={BIT_ARRAY{1'b0}};
kernel[shift]<={BIT_ARRAY{1'b0}};
end
conv_reg<={CONV_LPOS{1'b0}};
end
else if(i_valid)begin
case (i_selecK_I)
1'b1: begin
for( shift = 0; shift < M_LEN-1; shift = shift +1)
imagen[shift]<=imagen[shift+1];
imagen[M_LEN-1]<={i_dato2,i_dato1,i_dato0};
conv_reg<= resultado[CONV_LEN-2:CONV_LEN-CONV_LPOS-1];
end
1'b0: begin
for( shift = 0; shift < M_LEN-1; shift = shift +1)
kernel[shift]<=kernel[shift+1];
kernel[M_LEN-1]<={i_dato2,i_dato1,i_dato0};
conv_reg<=conv_reg;
end
endcase
end
else begin
for (shift =0 ; shift<M_LEN;shift=shift+1) begin: elseequ
imagen[shift]<=imagen[shift];
kernel[shift]<=kernel[shift];
end
conv_reg<=conv_reg;
end
end
always@(posedge i_CLK)
for(i = 0 ; i < (M_LEN*M_LEN) ; i=i+1) begin
array_prod[i] =
$signed(kernel[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN])*
$signed(imagen[i/3][((i%3)+1)*BIT_LEN-1 -: BIT_LEN]);
end
always @(*) begin
parcial0=0;
for(ptr0 = 0 ; ptr0 < 4; ptr0 = ptr0 +1)begin
parcial0 = parcial0 + array_prod[ptr0];
end
end
always @(*) begin
parcial1=0;
for(ptr1 = 0 ; ptr1 < 4; ptr1 = ptr1 +1)begin
parcial1 = parcial1 + array_prod[4+ptr1];
end
end
assign resultado = parcial0 + parcial1 + array_prod[8];
endmodule | 18 |
3,516 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v | 105,269,489 | MCU_CTRL.v | v | 112 | 115 | [] | [] | [] | null | line:5: before: "localparam" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:65: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'substate\' generates 4 bits.\n : ... In instance MCU_CTRL\n substate <= (substate == SUB-1) ? {clog2(SUB-1){1\'b0}} : substate + 1;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:90: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance MCU_CTRL\n o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:100: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance MCU_CTRL\n o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n ^\n%Error: Exiting due to 3 warning(s)\n' | 1,298 | module | module MCU_CTRL
#(
parameter N = 16,
parameter STATES = 3,
localparam LOAD = 2'b00,
localparam PROC = 2'b01,
localparam OUT = 2'b10,
localparam SUB = N/2 + 1
)(
input i_sop, i_eop, clk, rst, i_chblk,
output reg [N+1:0] o_we,
output [clog2(STATES-1)-1:0] o_state,
output [clog2(SUB-1) - 1:0] o_substate,
output reg [clog2(N+1) - 1:0] o_memSelect
);
reg [N+1:0] we_rw_status;
reg [N+1:0] we_proc_status;
reg [clog2(N+1) - 1:0] memSelect_load, memSelect_out;
reg [clog2(SUB-1) - 1:0] substate;
reg [clog2(STATES-1)-1:0] state;
reg [clog2(STATES-1)-1:0] next_state;
reg chblk;
assign o_state = state;
assign o_substate = substate;
always @ (posedge clk) begin
if(rst) begin
substate <= {clog2(SUB-1){1'b0}};
next_state <= {clog2(STATES-1){1'b0}};
memSelect_load <= {clog2(N+1){1'b0}};
memSelect_out <= {clog2(N+1){1'b0}};
we_rw_status <= {{(N+1){1'b0}}, 1'b1};
we_proc_status <= {2'b00, {N{1'b1}}};
chblk <= 1'b0;
end
else begin
chblk <= i_chblk;
case(state)
LOAD: begin
if(next_state == state) begin
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end
else begin
if(i_chblk && (i_chblk != chblk)) begin
we_rw_status <= {we_rw_status[N:0], we_rw_status[N+1]};
memSelect_load <= (memSelect_load == N + 1) ? {clog2(N+1){1'b0}} : memSelect_load + 1;
end
end
end
PROC: begin
if(next_state == state) begin
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end else begin
if(i_chblk && (i_chblk != chblk))
we_proc_status <= {we_proc_status[1:0], we_proc_status[N+1:2]};
end
end
OUT: begin
if(next_state == state) begin
substate <= (substate == SUB-1) ? {clog2(SUB-1){1'b0}} : substate + 1;
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end
else begin
if(i_chblk && (i_chblk != chblk))
memSelect_out <= (memSelect_out == N + 1) ? 0 : memSelect_out + 1;
end
end
endcase
end
end
always @ (*)
state = {i_eop, i_sop};
always @ (*) begin
case(state)
LOAD: begin
o_memSelect = memSelect_load;
o_we = we_rw_status;
end
PROC: begin
o_we = we_proc_status;
o_memSelect = {(clog2(N+1) - 1){1'b0}};
end
OUT: begin
o_we = {(N+2){1'b0}};
o_memSelect = memSelect_out;
end
default: begin
o_we = {(N+2){1'b0}};
o_memSelect = {(clog2(N+1) - 1){1'b0}};
end
endcase
end
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | module MCU_CTRL
#(
parameter N = 16,
parameter STATES = 3,
localparam LOAD = 2'b00,
localparam PROC = 2'b01,
localparam OUT = 2'b10,
localparam SUB = N/2 + 1
)(
input i_sop, i_eop, clk, rst, i_chblk,
output reg [N+1:0] o_we,
output [clog2(STATES-1)-1:0] o_state,
output [clog2(SUB-1) - 1:0] o_substate,
output reg [clog2(N+1) - 1:0] o_memSelect
); |
reg [N+1:0] we_rw_status;
reg [N+1:0] we_proc_status;
reg [clog2(N+1) - 1:0] memSelect_load, memSelect_out;
reg [clog2(SUB-1) - 1:0] substate;
reg [clog2(STATES-1)-1:0] state;
reg [clog2(STATES-1)-1:0] next_state;
reg chblk;
assign o_state = state;
assign o_substate = substate;
always @ (posedge clk) begin
if(rst) begin
substate <= {clog2(SUB-1){1'b0}};
next_state <= {clog2(STATES-1){1'b0}};
memSelect_load <= {clog2(N+1){1'b0}};
memSelect_out <= {clog2(N+1){1'b0}};
we_rw_status <= {{(N+1){1'b0}}, 1'b1};
we_proc_status <= {2'b00, {N{1'b1}}};
chblk <= 1'b0;
end
else begin
chblk <= i_chblk;
case(state)
LOAD: begin
if(next_state == state) begin
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end
else begin
if(i_chblk && (i_chblk != chblk)) begin
we_rw_status <= {we_rw_status[N:0], we_rw_status[N+1]};
memSelect_load <= (memSelect_load == N + 1) ? {clog2(N+1){1'b0}} : memSelect_load + 1;
end
end
end
PROC: begin
if(next_state == state) begin
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end else begin
if(i_chblk && (i_chblk != chblk))
we_proc_status <= {we_proc_status[1:0], we_proc_status[N+1:2]};
end
end
OUT: begin
if(next_state == state) begin
substate <= (substate == SUB-1) ? {clog2(SUB-1){1'b0}} : substate + 1;
next_state <= (next_state == STATES - 1) ? {clog2(STATES-1){1'b0}} : next_state + 1;
end
else begin
if(i_chblk && (i_chblk != chblk))
memSelect_out <= (memSelect_out == N + 1) ? 0 : memSelect_out + 1;
end
end
endcase
end
end
always @ (*)
state = {i_eop, i_sop};
always @ (*) begin
case(state)
LOAD: begin
o_memSelect = memSelect_load;
o_we = we_rw_status;
end
PROC: begin
o_we = we_proc_status;
o_memSelect = {(clog2(N+1) - 1){1'b0}};
end
OUT: begin
o_we = {(N+2){1'b0}};
o_memSelect = memSelect_out;
end
default: begin
o_we = {(N+2){1'b0}};
o_memSelect = {(clog2(N+1) - 1){1'b0}};
end
endcase
end
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | 18 |
3,517 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v | 105,269,489 | MCU_CTRL.v | v | 112 | 115 | [] | [] | [] | null | line:5: before: "localparam" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:65: Operator EQ expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'substate\' generates 4 bits.\n : ... In instance MCU_CTRL\n substate <= (substate == SUB-1) ? {clog2(SUB-1){1\'b0}} : substate + 1;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:90: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance MCU_CTRL\n o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n ^\n%Warning-WIDTH: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/MCU_CTRL.v:100: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n : ... In instance MCU_CTRL\n o_memSelect = {(clog2(N+1) - 1){1\'b0}};\n ^\n%Error: Exiting due to 3 warning(s)\n' | 1,298 | function | function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | function integer clog2; |
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | 18 |
3,518 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/HARDTEST/top_microblaze.v | 105,269,489 | top_microblaze.v | v | 152 | 83 | [] | [] | [] | null | line:126: before: "memory" | null | 1: b"%Error: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/HARDTEST/top_microblaze.v:126: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n memory begin\n ^~~~~~\n%Error: Cannot continue\n" | 1,300 | module | module top_microblaze
#(
parameter N = 2,
parameter STATES = 3,
parameter BITS_IMAGEN = 11,
parameter BITS_DATA = BITS_IMAGEN,
parameter BITS_ADDR = 10
)(
input CLK,
input [3:0] sw,
input [3:0] btn,
output [3:0] o_led,
output uart_rxd_out,
input uart_txd_in
);
wire [31:0] gpio_i_data_tri_i;
wire [31:0] gpio_o_data_tri_o;
wire reset;
wire sys_clock;
wire uart_rtl_rxd;
wire uart_rtl_txd;
wire led_warning;
wire led_m1;
wire led_m2;
wire valid;
wire enable;
wire init;
wire reset_sw;
wire clock1;
wire clock2;
wire [N*BITS_IMAGEN-1:0] DataConv;
wire [BITS_DATA-1:0] Data;
wire [(N+2)*BITS_IMAGEN-1:0] MemData;
wire [BITS_ADDR-1:0] WAddr;
wire RAddr;
wire chblk;
wire sop;
wire eop;
wire [3*N*BITS_IMAGEN-1:0] DataConv;
wire [BITS_DATA-1:0] Data;
wire [N+1:0] we;
wire [BITS_ADDR-1:0] WAddr, RAddr;
wire [(N+2)*BITS_IMAGEN-1:0] MemData;
assign reset = sw[0];
assign sys_clock = CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign i_dA_m1=16'b1111111111111111;
assign i_dA_m2=16'b1010101010101010;
assign reset_sw = gpio_o_data_tri_o[0];
assign enable = gpio_o_data_tri_o[1];
assign init = gpio_o_data_tri_o[2];
assign valid = gpio_o_data_tri_o[3];
assign i_addressB = gpio_o_data_tri_o[19:4];
assign reset = sw[0];
assign sys_clock = CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign o_led[0] = led_m1&led_m2;
assign o_led[1] = led_warning;
design_1
u_MCU
(.clock100(clock2),
.gpio_rtl_tri_i(gpio_i_data_tri_i),
.gpio_rtl_tri_o(gpio_o_data_tri_o),
.o_lock_clock(led_warning),
.reset(reset),
.sys_clock(sys_clock),
.usb_uart_rxd(uart_rtl_rxd),
.usb_uart_txd(uart_rtl_txd)
);
MCU
u_MemCU
(
.i_DataConv(DataConv),
.i_Data(Data),
.i_MemData(MemData),
.i_WAddr(WAddr),
.i_RAddr(RAddr),
.i_chblk(chblk),
.i_sop(sop),
.i_eop(eop),
.rst(),
.clk(clock2),
.o_DataConv(),
.o_Data(),
.o_we(),
.o_WAddr(),
.o_RAddr(),
.o_MemData()
)
memory begin
u_memory_1
(
.i_wrEnable(),
.i_CLK(),
.i_writeAdd(),
.i_readAdd(),
.i_data(),
.o_data(),
);
u_memory_2
(
.i_wrEnable(),
.i_CLK(),
.i_writeAdd(),
.i_readAdd(),
.i_data(),
.o_data(),
);
end
endmodule | module top_microblaze
#(
parameter N = 2,
parameter STATES = 3,
parameter BITS_IMAGEN = 11,
parameter BITS_DATA = BITS_IMAGEN,
parameter BITS_ADDR = 10
)(
input CLK,
input [3:0] sw,
input [3:0] btn,
output [3:0] o_led,
output uart_rxd_out,
input uart_txd_in
); |
wire [31:0] gpio_i_data_tri_i;
wire [31:0] gpio_o_data_tri_o;
wire reset;
wire sys_clock;
wire uart_rtl_rxd;
wire uart_rtl_txd;
wire led_warning;
wire led_m1;
wire led_m2;
wire valid;
wire enable;
wire init;
wire reset_sw;
wire clock1;
wire clock2;
wire [N*BITS_IMAGEN-1:0] DataConv;
wire [BITS_DATA-1:0] Data;
wire [(N+2)*BITS_IMAGEN-1:0] MemData;
wire [BITS_ADDR-1:0] WAddr;
wire RAddr;
wire chblk;
wire sop;
wire eop;
wire [3*N*BITS_IMAGEN-1:0] DataConv;
wire [BITS_DATA-1:0] Data;
wire [N+1:0] we;
wire [BITS_ADDR-1:0] WAddr, RAddr;
wire [(N+2)*BITS_IMAGEN-1:0] MemData;
assign reset = sw[0];
assign sys_clock = CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign i_dA_m1=16'b1111111111111111;
assign i_dA_m2=16'b1010101010101010;
assign reset_sw = gpio_o_data_tri_o[0];
assign enable = gpio_o_data_tri_o[1];
assign init = gpio_o_data_tri_o[2];
assign valid = gpio_o_data_tri_o[3];
assign i_addressB = gpio_o_data_tri_o[19:4];
assign reset = sw[0];
assign sys_clock = CLK;
assign uart_rtl_rxd = uart_txd_in;
assign uart_rxd_out = uart_rtl_txd;
assign o_led[0] = led_m1&led_m2;
assign o_led[1] = led_warning;
design_1
u_MCU
(.clock100(clock2),
.gpio_rtl_tri_i(gpio_i_data_tri_i),
.gpio_rtl_tri_o(gpio_o_data_tri_o),
.o_lock_clock(led_warning),
.reset(reset),
.sys_clock(sys_clock),
.usb_uart_rxd(uart_rtl_rxd),
.usb_uart_txd(uart_rtl_txd)
);
MCU
u_MemCU
(
.i_DataConv(DataConv),
.i_Data(Data),
.i_MemData(MemData),
.i_WAddr(WAddr),
.i_RAddr(RAddr),
.i_chblk(chblk),
.i_sop(sop),
.i_eop(eop),
.rst(),
.clk(clock2),
.o_DataConv(),
.o_Data(),
.o_we(),
.o_WAddr(),
.o_RAddr(),
.o_MemData()
)
memory begin
u_memory_1
(
.i_wrEnable(),
.i_CLK(),
.i_writeAdd(),
.i_readAdd(),
.i_data(),
.o_data(),
);
u_memory_2
(
.i_wrEnable(),
.i_CLK(),
.i_writeAdd(),
.i_readAdd(),
.i_data(),
.o_data(),
);
end
endmodule | 18 |
3,519 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner TB/MCU_CTRL_TB.v | 105,269,489 | MCU_CTRL_TB.v | v | 107 | 66 | [] | [] | [] | null | line:80: before: "$" | null | 1: b'%Error: Cannot find file containing module: TB,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.sv\n TB,data/full_repos/permissive/105269489\n TB,data/full_repos/permissive/105269489.v\n TB,data/full_repos/permissive/105269489.sv\n obj_dir/TB,data/full_repos/permissive/105269489\n obj_dir/TB,data/full_repos/permissive/105269489.v\n obj_dir/TB,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner\n%Error: Cannot find file containing module: TB/MCU_CTRL_TB.v\n%Error: Exiting due to 3 error(s)\n' | 1,301 | module | module tb_MCU_CTRL();
parameter N = 2;
parameter STATES = 3;
reg i_sop, i_eop, clk, rst, i_chblk;
wire [N+1:0] o_we;
wire [$clog2(STATES)-1:0] o_state;
wire [$clog2(N/2+1) - 1:0] o_substate;
wire [$clog2(N+2) - 1:0] o_memSelect;
initial begin
i_sop = 1'b0;
i_eop = 1'b0;
rst = 1'b0;
i_chblk = 1'b0;
clk = 1'b0;
#10 rst = 1'b1;
#20 rst = 1'b0;
#100 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#100 i_sop = 1'b0;
i_eop = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#500 $finish;
end
always #2.5 clk = ~clk;
MCU_CTRL
#(
.N(N),
.STATES(STATES)
)
u_MCU_CTRL
(
.i_sop(i_sop),
.i_eop(i_eop),
.i_chblk(i_chblk),
.clk(clk),
.rst(rst),
.o_we(o_we),
.o_state(o_state),
.o_substate(o_substate),
.o_memSelect(o_memSelect)
);
endmodule | module tb_MCU_CTRL(); |
parameter N = 2;
parameter STATES = 3;
reg i_sop, i_eop, clk, rst, i_chblk;
wire [N+1:0] o_we;
wire [$clog2(STATES)-1:0] o_state;
wire [$clog2(N/2+1) - 1:0] o_substate;
wire [$clog2(N+2) - 1:0] o_memSelect;
initial begin
i_sop = 1'b0;
i_eop = 1'b0;
rst = 1'b0;
i_chblk = 1'b0;
clk = 1'b0;
#10 rst = 1'b1;
#20 rst = 1'b0;
#100 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#100 i_sop = 1'b0;
i_eop = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#500 $finish;
end
always #2.5 clk = ~clk;
MCU_CTRL
#(
.N(N),
.STATES(STATES)
)
u_MCU_CTRL
(
.i_sop(i_sop),
.i_eop(i_eop),
.i_chblk(i_chblk),
.clk(clk),
.rst(rst),
.o_we(o_we),
.o_state(o_state),
.o_substate(o_substate),
.o_memSelect(o_memSelect)
);
endmodule | 18 |
3,520 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner TB/MCU_MUX_ARRAY_TB.v | 105,269,489 | MCU_MUX_ARRAY_TB.v | v | 79 | 56 | [] | [] | [] | null | line:46: before: "$" | null | 1: b'%Error: Cannot find file containing module: TB,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.sv\n TB,data/full_repos/permissive/105269489\n TB,data/full_repos/permissive/105269489.v\n TB,data/full_repos/permissive/105269489.sv\n obj_dir/TB,data/full_repos/permissive/105269489\n obj_dir/TB,data/full_repos/permissive/105269489.v\n obj_dir/TB,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner\n%Error: Cannot find file containing module: TB/MCU_MUX_ARRAY_TB.v\n%Error: Exiting due to 3 error(s)\n' | 1,302 | module | module tb_MUX_ARRAY();
parameter N = 4;
parameter BITS_IMAGEN = 8;
parameter STATES = 3;
parameter BITS_DATA = 13;
reg [N*BITS_DATA-1:0] i_DataConv;
reg [(N+2)*BITS_DATA-1:0] i_MemData;
reg [BITS_IMAGEN-1:0] i_Data;
reg [clog2(STATES-1)-1:0] i_state;
reg [clog2(N/2) - 1:0] i_substate;
reg [clog2(N+1)-1:0] i_memSelect;
wire [3*N*BITS_IMAGEN-1:0] o_DataConv;
wire [(N+2)*BITS_DATA-1:0] o_MemData;
wire [BITS_DATA-1:0] o_Data;
initial begin
$display("%d", 2**clog2(N/2));
i_Data = {BITS_IMAGEN{1'b1,1'b0}};
i_MemData = {13'b0, 13'b1, 13'b0, 13'b1};
i_DataConv = {13'h3,13'h2,13'h1,13'h0};
i_state = 0;
i_substate = 0;
i_memSelect = 0;
#100 i_memSelect = 1;
#200 i_memSelect = 2;
#300 i_memSelect = 3;
#350 i_state = 1;
#500 i_substate = 1;
#600 i_state = 2;
i_memSelect = 0;
#650 i_memSelect = 1;
#700 i_memSelect = 2;
#800 $finish;
end
MUX_ARRAY
#(
.N(N),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.STATES(STATES)
)
u_MUX_ARRAY
(
.i_DataConv(i_DataConv),
.i_MemData(i_MemData),
.i_Data(i_Data),
.i_state(i_state),
.i_substate(i_substate),
.i_memSelect(i_memSelect),
.o_DataConv(o_DataConv),
.o_MemData(o_MemData),
.o_Data(o_Data)
);
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | module tb_MUX_ARRAY(); |
parameter N = 4;
parameter BITS_IMAGEN = 8;
parameter STATES = 3;
parameter BITS_DATA = 13;
reg [N*BITS_DATA-1:0] i_DataConv;
reg [(N+2)*BITS_DATA-1:0] i_MemData;
reg [BITS_IMAGEN-1:0] i_Data;
reg [clog2(STATES-1)-1:0] i_state;
reg [clog2(N/2) - 1:0] i_substate;
reg [clog2(N+1)-1:0] i_memSelect;
wire [3*N*BITS_IMAGEN-1:0] o_DataConv;
wire [(N+2)*BITS_DATA-1:0] o_MemData;
wire [BITS_DATA-1:0] o_Data;
initial begin
$display("%d", 2**clog2(N/2));
i_Data = {BITS_IMAGEN{1'b1,1'b0}};
i_MemData = {13'b0, 13'b1, 13'b0, 13'b1};
i_DataConv = {13'h3,13'h2,13'h1,13'h0};
i_state = 0;
i_substate = 0;
i_memSelect = 0;
#100 i_memSelect = 1;
#200 i_memSelect = 2;
#300 i_memSelect = 3;
#350 i_state = 1;
#500 i_substate = 1;
#600 i_state = 2;
i_memSelect = 0;
#650 i_memSelect = 1;
#700 i_memSelect = 2;
#800 $finish;
end
MUX_ARRAY
#(
.N(N),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.STATES(STATES)
)
u_MUX_ARRAY
(
.i_DataConv(i_DataConv),
.i_MemData(i_MemData),
.i_Data(i_Data),
.i_state(i_state),
.i_substate(i_substate),
.i_memSelect(i_memSelect),
.o_DataConv(o_DataConv),
.o_MemData(o_MemData),
.o_Data(o_Data)
);
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | 18 |
3,521 | data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner TB/MCU_MUX_ARRAY_TB.v | 105,269,489 | MCU_MUX_ARRAY_TB.v | v | 79 | 56 | [] | [] | [] | null | line:46: before: "$" | null | 1: b'%Error: Cannot find file containing module: TB,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner/TB,data/full_repos/permissive/105269489.sv\n TB,data/full_repos/permissive/105269489\n TB,data/full_repos/permissive/105269489.v\n TB,data/full_repos/permissive/105269489.sv\n obj_dir/TB,data/full_repos/permissive/105269489\n obj_dir/TB,data/full_repos/permissive/105269489.v\n obj_dir/TB,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Modules/MCU/inner\n%Error: Cannot find file containing module: TB/MCU_MUX_ARRAY_TB.v\n%Error: Exiting due to 3 error(s)\n' | 1,302 | function | function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | function integer clog2; |
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | 18 |
3,523 | data/full_repos/permissive/105269489/src/verilog/Test benches/tb_Fsmv.v | 105,269,489 | tb_Fsmv.v | v | 69 | 81 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xed in position 215: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: benches,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.sv\n benches,data/full_repos/permissive/105269489\n benches,data/full_repos/permissive/105269489.v\n benches,data/full_repos/permissive/105269489.sv\n obj_dir/benches,data/full_repos/permissive/105269489\n obj_dir/benches,data/full_repos/permissive/105269489.v\n obj_dir/benches,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_Fsmv.v\n%Error: Exiting due to 3 error(s)\n' | 1,306 | module | module tb_FSM();
parameter NB_ADDRESS= 10;
parameter NB_IMAGE = 10;
reg CLK;
reg reset;
reg SOP;
reg [NB_IMAGE-1:0] imgLength;
reg valid;
reg load;
wire [NB_ADDRESS-1:0] writeAddress;
wire [NB_ADDRESS-1:0] readAddress;
wire EOP;
wire chblock;
wire vld;
integer i;
initial begin
CLK = 1'b0;
SOP = 1'b0;
imgLength = 10'hf;
valid = 1'b0;
load = 1'b0;
reset = 1'b1;
#10 reset = 1'b0;
#5 load = 1'b1;
for(i=0; i<= imgLength; i=i+1)begin
#5 valid = 1'b1;
#5 valid = 1'b0;
end
load = 1'b0;
#30 SOP = 1'b1;
#20 SOP = 1'b0;
#200 $finish;
end
always #2.5 CLK=~CLK;
Fsmv#(
.NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE (NB_IMAGE),
.N_CONV (4))
u_Fsmv(
.o_readAdd(readAddress),
.o_writeAdd(writeAddress),
.o_EoP(EOP),
.o_changeBlock(chblock),
.o_fms2conVld(vld),
.i_CLK(CLK),
.i_reset(reset),
.i_SoP(SOP),
.i_imgLength(imgLength),
.i_valid(valid),
.i_load(load));
endmodule | module tb_FSM(); |
parameter NB_ADDRESS= 10;
parameter NB_IMAGE = 10;
reg CLK;
reg reset;
reg SOP;
reg [NB_IMAGE-1:0] imgLength;
reg valid;
reg load;
wire [NB_ADDRESS-1:0] writeAddress;
wire [NB_ADDRESS-1:0] readAddress;
wire EOP;
wire chblock;
wire vld;
integer i;
initial begin
CLK = 1'b0;
SOP = 1'b0;
imgLength = 10'hf;
valid = 1'b0;
load = 1'b0;
reset = 1'b1;
#10 reset = 1'b0;
#5 load = 1'b1;
for(i=0; i<= imgLength; i=i+1)begin
#5 valid = 1'b1;
#5 valid = 1'b0;
end
load = 1'b0;
#30 SOP = 1'b1;
#20 SOP = 1'b0;
#200 $finish;
end
always #2.5 CLK=~CLK;
Fsmv#(
.NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE (NB_IMAGE),
.N_CONV (4))
u_Fsmv(
.o_readAdd(readAddress),
.o_writeAdd(writeAddress),
.o_EoP(EOP),
.o_changeBlock(chblock),
.o_fms2conVld(vld),
.i_CLK(CLK),
.i_reset(reset),
.i_SoP(SOP),
.i_imgLength(imgLength),
.i_valid(valid),
.i_load(load));
endmodule | 18 |
3,524 | data/full_repos/permissive/105269489/src/verilog/Test benches/tb_MCU.v | 105,269,489 | tb_MCU.v | v | 132 | 66 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: Cannot find file containing module: benches,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.sv\n benches,data/full_repos/permissive/105269489\n benches,data/full_repos/permissive/105269489.v\n benches,data/full_repos/permissive/105269489.sv\n obj_dir/benches,data/full_repos/permissive/105269489\n obj_dir/benches,data/full_repos/permissive/105269489.v\n obj_dir/benches,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_MCU.v\n%Error: Exiting due to 3 error(s)\n' | 1,307 | module | module tb_MCU();
parameter N = 2;
parameter STATES = 3;
parameter BITS_IMAGEN = 8;
parameter BITS_DATA = 13;
parameter BITS_ADDR = 10;
reg [N*BITS_DATA-1:0] i_DataConv;
reg [BITS_IMAGEN-1:0] i_Data;
reg [(N+2)*BITS_DATA-1:0] i_MemData;
reg [BITS_ADDR-1:0] i_WAddr, i_RAddr;
reg i_chblk, i_sop, i_eop, rst, clk;
wire [3*N*BITS_IMAGEN-1:0] o_DataConv;
wire [BITS_DATA-1:0] o_Data;
wire [N+1:0] o_we;
wire [BITS_ADDR-1:0] o_WAddr, o_RAddr;
wire [(N+2)*BITS_DATA-1:0] o_MemData;
initial begin
i_Data = {BITS_IMAGEN/2{1'b1,1'b0}};
i_MemData = {13'h3,13'h2,13'h1,13'h0};
i_DataConv = {13'hc1,13'hc0};
i_WAddr = 1;
i_RAddr = 1;
i_sop = 1'b0;
i_eop = 1'b0;
rst = 1'b0;
i_chblk = 1'b0;
clk = 1'b0;
#10 rst = 1'b1;
#20 rst = 1'b0;
#100 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#100 i_sop = 1'b0;
i_eop = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#500 $finish;
end
always #2.5 clk = ~clk;
MCU
#(
.N(N),
.STATES(STATES),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.BITS_ADDR(BITS_ADDR)
)
u_MCU
(
.i_DataConv(i_DataConv),
.i_Data(i_Data),
.i_MemData(i_MemData),
.i_WAddr(i_WAddr),
.i_RAddr(i_RAddr),
.i_chblk(i_chblk),
.i_sop(i_sop),
.i_eop(i_eop),
.rst(rst),
.clk(clk),
.o_DataConv(o_DataConv),
.o_Data(o_Data),
.o_we(o_we),
.o_WAddr(o_WAddr),
.o_RAddr(o_RAddr),
.o_MemData(o_MemData)
);
endmodule | module tb_MCU(); |
parameter N = 2;
parameter STATES = 3;
parameter BITS_IMAGEN = 8;
parameter BITS_DATA = 13;
parameter BITS_ADDR = 10;
reg [N*BITS_DATA-1:0] i_DataConv;
reg [BITS_IMAGEN-1:0] i_Data;
reg [(N+2)*BITS_DATA-1:0] i_MemData;
reg [BITS_ADDR-1:0] i_WAddr, i_RAddr;
reg i_chblk, i_sop, i_eop, rst, clk;
wire [3*N*BITS_IMAGEN-1:0] o_DataConv;
wire [BITS_DATA-1:0] o_Data;
wire [N+1:0] o_we;
wire [BITS_ADDR-1:0] o_WAddr, o_RAddr;
wire [(N+2)*BITS_DATA-1:0] o_MemData;
initial begin
i_Data = {BITS_IMAGEN/2{1'b1,1'b0}};
i_MemData = {13'h3,13'h2,13'h1,13'h0};
i_DataConv = {13'hc1,13'hc0};
i_WAddr = 1;
i_RAddr = 1;
i_sop = 1'b0;
i_eop = 1'b0;
rst = 1'b0;
i_chblk = 1'b0;
clk = 1'b0;
#10 rst = 1'b1;
#20 rst = 1'b0;
#100 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#100 i_sop = 1'b0;
i_eop = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#200 i_sop = 1'b1;
#300 i_sop = 1'b0;
i_eop = 1'b1;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#10 i_chblk = 1'b1;
#10 i_chblk = 1'b0;
#500 $finish;
end
always #2.5 clk = ~clk;
MCU
#(
.N(N),
.STATES(STATES),
.BITS_IMAGEN(BITS_IMAGEN),
.BITS_DATA(BITS_DATA),
.BITS_ADDR(BITS_ADDR)
)
u_MCU
(
.i_DataConv(i_DataConv),
.i_Data(i_Data),
.i_MemData(i_MemData),
.i_WAddr(i_WAddr),
.i_RAddr(i_RAddr),
.i_chblk(i_chblk),
.i_sop(i_sop),
.i_eop(i_eop),
.rst(rst),
.clk(clk),
.o_DataConv(o_DataConv),
.o_Data(o_Data),
.o_we(o_we),
.o_WAddr(o_WAddr),
.o_RAddr(o_RAddr),
.o_MemData(o_MemData)
);
endmodule | 18 |
3,525 | data/full_repos/permissive/105269489/src/verilog/Test benches/tb_memory.v | 105,269,489 | tb_memory.v | v | 83 | 68 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xed in position 216: invalid continuation byte | null | 1: b'%Error: Cannot find file containing module: benches,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Test/benches,data/full_repos/permissive/105269489.sv\n benches,data/full_repos/permissive/105269489\n benches,data/full_repos/permissive/105269489.v\n benches,data/full_repos/permissive/105269489.sv\n obj_dir/benches,data/full_repos/permissive/105269489\n obj_dir/benches,data/full_repos/permissive/105269489.v\n obj_dir/benches,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_memory.v\n%Error: Exiting due to 3 error(s)\n' | 1,308 | module | module tb_memory();
parameter RAM_WIDTH = `RAM_WIDTH;
parameter NB_ADDRESS= `NB_ADDRESS;
wire[RAM_WIDTH-1:0] output_data;
reg[NB_ADDRESS-1:0] write_address;
reg[NB_ADDRESS-1:0] read_address;
reg input_CLK;
reg writeEnable;
reg [RAM_WIDTH-1:0] input_data;
initial begin
write_address =10'd0;
read_address =10'd0;
writeEnable =1'b0;
input_data =8'h0;
input_CLK= 1'b0;
#10 writeEnable=1'b1;
#10 writeEnable = 1'b0;
#50 input_data=8'hFF;
#50 write_address = write_address + 1;
#50 read_address = read_address + 1;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#50 input_data=8'b10000001;
#50 write_address = write_address + 1;
#50 read_address = read_address + 1;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#50 input_data=8'b11100111;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#10000000000 $finish;
end
always #2.5 input_CLK=~input_CLK;
memory
#(
.NB_ADDRESS(NB_ADDRESS),
.RAM_WIDTH (RAM_WIDTH)
)
u_bram
(
.i_data(input_data),
.i_writeAdd(write_address),
.i_readAdd(read_address),
.i_CLK(input_CLK),
.i_wrEnable(writeEnable),
.o_data(output_data)
);
endmodule | module tb_memory(); |
parameter RAM_WIDTH = `RAM_WIDTH;
parameter NB_ADDRESS= `NB_ADDRESS;
wire[RAM_WIDTH-1:0] output_data;
reg[NB_ADDRESS-1:0] write_address;
reg[NB_ADDRESS-1:0] read_address;
reg input_CLK;
reg writeEnable;
reg [RAM_WIDTH-1:0] input_data;
initial begin
write_address =10'd0;
read_address =10'd0;
writeEnable =1'b0;
input_data =8'h0;
input_CLK= 1'b0;
#10 writeEnable=1'b1;
#10 writeEnable = 1'b0;
#50 input_data=8'hFF;
#50 write_address = write_address + 1;
#50 read_address = read_address + 1;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#50 input_data=8'b10000001;
#50 write_address = write_address + 1;
#50 read_address = read_address + 1;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#50 input_data=8'b11100111;
#20 writeEnable = 1'b1;
#20 writeEnable = 1'b0;
#10000000000 $finish;
end
always #2.5 input_CLK=~input_CLK;
memory
#(
.NB_ADDRESS(NB_ADDRESS),
.RAM_WIDTH (RAM_WIDTH)
)
u_bram
(
.i_data(input_data),
.i_writeAdd(write_address),
.i_readAdd(read_address),
.i_CLK(input_CLK),
.i_wrEnable(writeEnable),
.o_data(output_data)
);
endmodule | 18 |
3,528 | data/full_repos/permissive/105269489/src/verilog/Test benches/tb_FSMandControl/Módulos involucrados/micro_sim.v | 105,269,489 | micro_sim.v | v | 186 | 102 | [] | [] | [] | null | line:23: before: "localparam" | null | 1: b'%Error: Cannot find file containing module: benches/tb_FSMandControl/M\xc3\xb3dulos\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/M\xc3\xb3dulos\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/M\xc3\xb3dulos.v\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/M\xc3\xb3dulos.sv\n benches/tb_FSMandControl/M\xc3\xb3dulos\n benches/tb_FSMandControl/M\xc3\xb3dulos.v\n benches/tb_FSMandControl/M\xc3\xb3dulos.sv\n obj_dir/benches/tb_FSMandControl/M\xc3\xb3dulos\n obj_dir/benches/tb_FSMandControl/M\xc3\xb3dulos.v\n obj_dir/benches/tb_FSMandControl/M\xc3\xb3dulos.sv\n%Error: Cannot find file containing module: involucrados,data/full_repos/permissive/105269489\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: involucrados/micro_sim.v\n%Error: Exiting due to 4 error(s)\n' | 1,314 | module | module micro_sim#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter BITS_IMAGE = `BITS_IMAGE,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter BITS_STATES = `BITS_STATES,
localparam limit = 16384
)(
output o_led,
input i_CLK,
input [GPIO_D-1:0] gpio_o_data_tri_o
);
reg [12:0] MCUdata;
reg [14:0] counter;
reg valid_output_latch;
reg sop_fromfsm_latch;
reg [31:0] controlGPIOoutput_latch;
reg [12:0] MCUoutput_latch;
reg changeBlock_latch;
reg EOP_fromFSM_latch;
wire load_net;
wire sop_fromFSM;
wire valid_for_conv;
wire [NB_ADDRESS-1:0] wrAdd;
wire [NB_ADDRESS-1:0] rdAdd;
wire EOP_from_FSM_to_CTRL;
wire [23:0] krnlData;
wire [9:0]imgLength_from_CTRL_to_FSM;
wire ledControl;
wire EoP_to_MCU;
wire SOP_from_CTRL;
wire valid_from_ctrl_to_FSM;
wire validCONV;
wire KorI;
wire changeBlock;
wire [12:0] output_MCUdata;
wire validGPIO;
wire rst_sw;
wire [2:0] GPIOctrl;
wire [23:0] GPIOdata;
wire [31:0] outGPIOctrl;
assign rst_sw = gpio_o_data_tri_o[0];
assign GPIOctrl = gpio_o_data_tri_o[31:29];
assign validGPIO = gpio_o_data_tri_o[28];
assign GPIOdata = gpio_o_data_tri_o[24:1];
initial begin
MCUdata <= 13'd0;
counter <= 13'd0;
sop_fromfsm_latch<=1'b0;
valid_output_latch<=1'b0;
controlGPIOoutput_latch<='d0;
MCUoutput_latch<='d0;
changeBlock_latch<='d0;
EOP_fromFSM_latch<='d0;
end
always @(posedge i_CLK ) begin
valid_output_latch <= valid_for_conv;
MCUoutput_latch<= output_MCUdata;
controlGPIOoutput_latch <= outGPIOctrl;
changeBlock_latch <= changeBlock;
EOP_fromFSM_latch <=EOP_from_FSM_to_CTRL;
sop_fromfsm_latch<=sop_fromFSM;
if (rst_sw) begin
MCUdata <= 13'd0;
counter <= 13'd0;
sop_fromfsm_latch<=1'b0;
valid_output_latch<=1'b0;
controlGPIOoutput_latch<='d0;
MCUoutput_latch<='d0;
changeBlock_latch<='d0;
EOP_fromFSM_latch<='d0;
end
else begin
counter <= counter + 1;
if (counter == limit) begin
MCUdata<=MCUdata+1;
if (MCUdata==13'b1111111111111)
MCUdata<='d0;
end
end
end
ControlBlock
u_RegisterFile
(
.i_GPIOdata(GPIOdata),
.i_MCUdata(MCUdata),
.i_GPIOctrl(GPIOctrl),
.i_GPIOvalid(validGPIO),
.i_rst(rst_sw),
.i_CLK(i_CLK),
.i_EOP_from_FSM(EOP_from_FSM_to_CTRL),
.o_GPIOdata(outGPIOctrl),
.o_KNLdata(krnlData),
.o_imgLength(imgLength_from_CTRL_to_FSM),
.o_led(ledControl),
.o_load(load_net),
.o_EOP_to_MCU(EoP_to_MCU),
.o_run(SOP_from_CTRL),
.o_valid_to_FSM(valid_from_ctrl_to_FSM),
.o_valid_to_CONV(validCONV),
.o_KNorIMG(KorI),
.o_MCUdata(output_MCUdata)
);
FSMv2
#(
.NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE (BITS_IMAGE),
.NB_STATES(BITS_STATES)
)
u_FSM
(
.i_CLK(i_CLK),
.i_load(load_net),
.i_reset(rst_sw),
.i_SoP(SOP_from_CTRL),
.i_imgLength(imgLength_from_CTRL_to_FSM),
.i_valid(valid_from_ctrl_to_FSM),
.o_valid_fromFSM_toCONV(valid_for_conv),
.o_readAdd(rdAdd),
.o_SOP_fromFSM(sop_fromFSM),
.o_writeAdd(wrAdd),
.o_EoP(EOP_from_FSM_to_CTRL),
.o_changeBlock(changeBlock)
);
endmodule | module micro_sim#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter BITS_IMAGE = `BITS_IMAGE,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D,
parameter BITS_STATES = `BITS_STATES,
localparam limit = 16384
)(
output o_led,
input i_CLK,
input [GPIO_D-1:0] gpio_o_data_tri_o
); |
reg [12:0] MCUdata;
reg [14:0] counter;
reg valid_output_latch;
reg sop_fromfsm_latch;
reg [31:0] controlGPIOoutput_latch;
reg [12:0] MCUoutput_latch;
reg changeBlock_latch;
reg EOP_fromFSM_latch;
wire load_net;
wire sop_fromFSM;
wire valid_for_conv;
wire [NB_ADDRESS-1:0] wrAdd;
wire [NB_ADDRESS-1:0] rdAdd;
wire EOP_from_FSM_to_CTRL;
wire [23:0] krnlData;
wire [9:0]imgLength_from_CTRL_to_FSM;
wire ledControl;
wire EoP_to_MCU;
wire SOP_from_CTRL;
wire valid_from_ctrl_to_FSM;
wire validCONV;
wire KorI;
wire changeBlock;
wire [12:0] output_MCUdata;
wire validGPIO;
wire rst_sw;
wire [2:0] GPIOctrl;
wire [23:0] GPIOdata;
wire [31:0] outGPIOctrl;
assign rst_sw = gpio_o_data_tri_o[0];
assign GPIOctrl = gpio_o_data_tri_o[31:29];
assign validGPIO = gpio_o_data_tri_o[28];
assign GPIOdata = gpio_o_data_tri_o[24:1];
initial begin
MCUdata <= 13'd0;
counter <= 13'd0;
sop_fromfsm_latch<=1'b0;
valid_output_latch<=1'b0;
controlGPIOoutput_latch<='d0;
MCUoutput_latch<='d0;
changeBlock_latch<='d0;
EOP_fromFSM_latch<='d0;
end
always @(posedge i_CLK ) begin
valid_output_latch <= valid_for_conv;
MCUoutput_latch<= output_MCUdata;
controlGPIOoutput_latch <= outGPIOctrl;
changeBlock_latch <= changeBlock;
EOP_fromFSM_latch <=EOP_from_FSM_to_CTRL;
sop_fromfsm_latch<=sop_fromFSM;
if (rst_sw) begin
MCUdata <= 13'd0;
counter <= 13'd0;
sop_fromfsm_latch<=1'b0;
valid_output_latch<=1'b0;
controlGPIOoutput_latch<='d0;
MCUoutput_latch<='d0;
changeBlock_latch<='d0;
EOP_fromFSM_latch<='d0;
end
else begin
counter <= counter + 1;
if (counter == limit) begin
MCUdata<=MCUdata+1;
if (MCUdata==13'b1111111111111)
MCUdata<='d0;
end
end
end
ControlBlock
u_RegisterFile
(
.i_GPIOdata(GPIOdata),
.i_MCUdata(MCUdata),
.i_GPIOctrl(GPIOctrl),
.i_GPIOvalid(validGPIO),
.i_rst(rst_sw),
.i_CLK(i_CLK),
.i_EOP_from_FSM(EOP_from_FSM_to_CTRL),
.o_GPIOdata(outGPIOctrl),
.o_KNLdata(krnlData),
.o_imgLength(imgLength_from_CTRL_to_FSM),
.o_led(ledControl),
.o_load(load_net),
.o_EOP_to_MCU(EoP_to_MCU),
.o_run(SOP_from_CTRL),
.o_valid_to_FSM(valid_from_ctrl_to_FSM),
.o_valid_to_CONV(validCONV),
.o_KNorIMG(KorI),
.o_MCUdata(output_MCUdata)
);
FSMv2
#(
.NB_ADDRESS(NB_ADDRESS),
.NB_IMAGE (BITS_IMAGE),
.NB_STATES(BITS_STATES)
)
u_FSM
(
.i_CLK(i_CLK),
.i_load(load_net),
.i_reset(rst_sw),
.i_SoP(SOP_from_CTRL),
.i_imgLength(imgLength_from_CTRL_to_FSM),
.i_valid(valid_from_ctrl_to_FSM),
.o_valid_fromFSM_toCONV(valid_for_conv),
.o_readAdd(rdAdd),
.o_SOP_fromFSM(sop_fromFSM),
.o_writeAdd(wrAdd),
.o_EoP(EOP_from_FSM_to_CTRL),
.o_changeBlock(changeBlock)
);
endmodule | 18 |
3,529 | data/full_repos/permissive/105269489/src/verilog/Test benches/tb_FSMandControl/sim_1/new/tb_fusion.v | 105,269,489 | tb_fusion.v | v | 105 | 71 | [] | [] | [] | null | line:91: before: "$" | null | 1: b'%Error: Cannot find file containing module: benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489\n ... Looked in:\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.v\n data/full_repos/permissive/105269489/src/verilog/Test/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.sv\n benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489\n benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.v\n benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.sv\n obj_dir/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489\n obj_dir/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.v\n obj_dir/benches/tb_FSMandControl/sim_1/new,data/full_repos/permissive/105269489.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/105269489/src/verilog/Test\n%Error: Cannot find file containing module: benches/tb_FSMandControl/sim_1/new/tb_fusion.v\n%Error: Exiting due to 3 error(s)\n' | 1,315 | module | module tb_fusion#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
)();
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'd1;
#25 gpio_o_data_tri_o = 32'd0;
#500 gpio_o_data_tri_o = 32'b00000000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000001000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000001000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000000000;
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000001110;
#500 gpio_o_data_tri_o = 32'b00100000000000000000000000001110;
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011000010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01010000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01000000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01010000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000111100011111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b10000000000111111111111111111110;
#2500 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim
u_micro_sim(
.o_led(o_led),
.i_CLK(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o));
endmodule | module tb_fusion#(
parameter BIT_LEN = `BIT_LEN,
parameter CONV_LEN = `CONV_LEN,
parameter CONV_LPOS = `CONV_LPOS,
parameter M_LEN = `M_LEN,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter RAM_WIDTH = `RAM_WIDTH,
parameter GPIO_D = `GPIO_D
)(); |
reg [GPIO_D-1:0] gpio_o_data_tri_o;
wire o_led;
reg CLK100MHZ;
initial begin
CLK100MHZ = 1'b0;
gpio_o_data_tri_o = 32'd1;
#25 gpio_o_data_tri_o = 32'd0;
#500 gpio_o_data_tri_o = 32'b00000000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000011111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000101000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000111111000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000001000000010;
#500 gpio_o_data_tri_o = 32'b00010000000000000000001000000010;
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000000000;
#500 gpio_o_data_tri_o = 32'b00000000000000000000000000001110;
#500 gpio_o_data_tri_o = 32'b00100000000000000000000000001110;
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000011011000010;
#500 gpio_o_data_tri_o = 32'b01010000000000000000011011011010;
#500 gpio_o_data_tri_o = 32'b01000000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01010000000000000000010000000000;
#500 gpio_o_data_tri_o = 32'b01000000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01010000000010101010010101010100;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01000000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01010000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000111111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000111100011111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01100000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b01110000000101111111111111111110;
#500 gpio_o_data_tri_o = 32'b10000000000111111111111111111110;
#2500 $finish;
end
always #2.5 CLK100MHZ = ~CLK100MHZ;
micro_sim
u_micro_sim(
.o_led(o_led),
.i_CLK(CLK100MHZ),
.gpio_o_data_tri_o(gpio_o_data_tri_o));
endmodule | 18 |
3,530 | data/full_repos/permissive/105546923/infra/hdl/clks.v | 105,546,923 | clks.v | v | 113 | 63 | [] | [] | [] | [(37, 833)] | null | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/clks.v:1: Cannot find include file: top.vh\n`include "top.vh" \n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/top.vh\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/top.vh.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/top.vh.sv\n top.vh\n top.vh.v\n top.vh.sv\n obj_dir/top.vh\n obj_dir/top.vh.v\n obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/105546923/infra/hdl/clks.v:43: Define or directive not defined: \'`SIM\'\n if (PLL_EN == 1 & `SIM == 0)\n ^~~~\n%Error: data/full_repos/permissive/105546923/infra/hdl/clks.v:43: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n if (PLL_EN == 1 & `SIM == 0)\n ^~\n%Error: data/full_repos/permissive/105546923/infra/hdl/clks.v:67: syntax error, unexpected end\n end \n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/105546923/infra/hdl/clks.v:76: Unsupported: Ignoring delay on this delayed statement.\n #(1.0/MULT) pll_clk = ~pll_clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/105546923/infra/hdl/clks.v:91: syntax error, unexpected end\n end \n ^~~\n%Error: Cannot continue\n' | 1,319 | module | module clks(
input clk_i,
output clk_o
);
parameter PLL_EN = 0;
parameter GBUFF_EN = 0;
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0111111;
parameter DIVQ = 3'b011;
parameter T = 1;
reg s_clk_o = 0;
wire pll_clk_o;
reg [$clog2(T) - 1 : 0] ctr = 0;
generate
if (GBUFF_EN == 1)
begin: GB
SB_GB gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(s_clk_o),
.GLOBAL_BUFFER_OUTPUT (clk_o)
);
end
else
begin: NO_GB
assign clk_o = s_clk_o;
end
endgenerate
generate
if (PLL_EN == 1 & `SIM == 0)
begin: PLL
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(DIVR),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(3'b001)
) uut (
.REFERENCECLK(clk_i),
.PLLOUTCORE(pll_clk_o),
.RESETB(1'b1),
.BYPASS(1'b0),
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'b00000000),
.LATCHINPUTVALUE(1'b0),
.SDI(1'b0),
.SCLK(1'b0)
);
always @*
begin
s_clk_o <= pll_clk_o;
end
end
else if (PLL_EN == 1)
begin
localparam MULT = (DIVF + 1) / ( (2**DIVQ) * (DIVR + 1) );
reg pll_clk = 1'b0;
always
begin
#(1.0/MULT) pll_clk = ~pll_clk;
end
assign pll_clk_o = pll_clk;
always @*
begin
s_clk_o <= pll_clk_o;
end
always @*
begin
s_clk_o <= pll_clk_o;
end
end
else
begin: CTR
always @ (posedge clk_i)
begin
if (ctr == T - 1)
begin
ctr <= 0;
s_clk_o <= ~s_clk_o;
end
else
begin
ctr <= ctr + 1;
end
end
end
endgenerate
endmodule | module clks(
input clk_i,
output clk_o
); |
parameter PLL_EN = 0;
parameter GBUFF_EN = 0;
parameter DIVR = 4'b0000;
parameter DIVF = 7'b0111111;
parameter DIVQ = 3'b011;
parameter T = 1;
reg s_clk_o = 0;
wire pll_clk_o;
reg [$clog2(T) - 1 : 0] ctr = 0;
generate
if (GBUFF_EN == 1)
begin: GB
SB_GB gb (
.USER_SIGNAL_TO_GLOBAL_BUFFER(s_clk_o),
.GLOBAL_BUFFER_OUTPUT (clk_o)
);
end
else
begin: NO_GB
assign clk_o = s_clk_o;
end
endgenerate
generate
if (PLL_EN == 1 & `SIM == 0)
begin: PLL
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
.DIVR(DIVR),
.DIVF(DIVF),
.DIVQ(DIVQ),
.FILTER_RANGE(3'b001)
) uut (
.REFERENCECLK(clk_i),
.PLLOUTCORE(pll_clk_o),
.RESETB(1'b1),
.BYPASS(1'b0),
.EXTFEEDBACK(1'b0),
.DYNAMICDELAY(8'b00000000),
.LATCHINPUTVALUE(1'b0),
.SDI(1'b0),
.SCLK(1'b0)
);
always @*
begin
s_clk_o <= pll_clk_o;
end
end
else if (PLL_EN == 1)
begin
localparam MULT = (DIVF + 1) / ( (2**DIVQ) * (DIVR + 1) );
reg pll_clk = 1'b0;
always
begin
#(1.0/MULT) pll_clk = ~pll_clk;
end
assign pll_clk_o = pll_clk;
always @*
begin
s_clk_o <= pll_clk_o;
end
always @*
begin
s_clk_o <= pll_clk_o;
end
end
else
begin: CTR
always @ (posedge clk_i)
begin
if (ctr == T - 1)
begin
ctr <= 0;
s_clk_o <= ~s_clk_o;
end
else
begin
ctr <= ctr + 1;
end
end
end
endgenerate
endmodule | 0 |
3,531 | data/full_repos/permissive/105546923/infra/hdl/fifo.v | 105,546,923 | fifo.v | v | 285 | 71 | [] | [] | [] | null | line:176: before: "," | null | 1: b'%Error: data/full_repos/permissive/105546923/infra/hdl/fifo.v:179: Cannot find file containing module: \'SB_RAM40_4K\'\n SB_RAM40_4K #(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.v\n data/full_repos/permissive/105546923/infra/hdl,data/full_repos/permissive/105546923/SB_RAM40_4K.sv\n SB_RAM40_4K\n SB_RAM40_4K.v\n SB_RAM40_4K.sv\n obj_dir/SB_RAM40_4K\n obj_dir/SB_RAM40_4K.v\n obj_dir/SB_RAM40_4K.sv\n%Warning-SELRANGE: data/full_repos/permissive/105546923/infra/hdl/fifo.v:119: Selection index out of range: 1:1 outside 0:0\n : ... In instance fifo\n assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1\'b0;\n ^\n ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 1,320 | module | module fifo(
input w_clk,
input r_clk,
input we,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [15 :0] mask,
output [DATA_WIDTH - 1 : 0] q,
output empty,
output full
);
parameter DATA_WIDTH = 1;
parameter ASYNC = 0;
wire [15:0] _d, _q;
genvar i;
generate
if (DATA_WIDTH <= 16 & DATA_WIDTH > 8)
begin
assign _d = { {(16 - DATA_WIDTH){1'b0}}, {d} };
assign q = { {(16 - DATA_WIDTH){1'b0}}, {_q} };
fifo_#(
.MODE(0),
.ADDR_WIDTH(8),
.ASYNC(ASYNC)
) fifo_256x16_(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(mask)
);
end
else if ( DATA_WIDTH <= 8 & DATA_WIDTH > 4)
begin
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = i < DATA_WIDTH ? d[i] : 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 2];
end
end
fifo_#(
.MODE(1),
.ADDR_WIDTH(9),
.ASYNC(ASYNC)
) fifo_512x8(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
else if ( DATA_WIDTH <= 4 & DATA_WIDTH > 2)
begin
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 4 + 1];
end
end
fifo_#(
.MODE(2),
.ADDR_WIDTH(10),
.ASYNC(ASYNC)
) fifo_1024x4(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
else if ( DATA_WIDTH <= 2 & DATA_WIDTH > 0)
begin
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 8 + 3];
end
end
fifo_#(
.MODE(3),
.ADDR_WIDTH(11),
.ASYNC(ASYNC)
) fifo_2048x2(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
endgenerate
endmodule | module fifo(
input w_clk,
input r_clk,
input we,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [15 :0] mask,
output [DATA_WIDTH - 1 : 0] q,
output empty,
output full
); |
parameter DATA_WIDTH = 1;
parameter ASYNC = 0;
wire [15:0] _d, _q;
genvar i;
generate
if (DATA_WIDTH <= 16 & DATA_WIDTH > 8)
begin
assign _d = { {(16 - DATA_WIDTH){1'b0}}, {d} };
assign q = { {(16 - DATA_WIDTH){1'b0}}, {_q} };
fifo_#(
.MODE(0),
.ADDR_WIDTH(8),
.ASYNC(ASYNC)
) fifo_256x16_(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(mask)
);
end
else if ( DATA_WIDTH <= 8 & DATA_WIDTH > 4)
begin
for (i = 0; i < 8; i=i+1)
begin
assign _d[i * 2 + 1] = 1'b0;
assign _d[i * 2] = i < DATA_WIDTH ? d[i] : 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 2];
end
end
fifo_#(
.MODE(1),
.ADDR_WIDTH(9),
.ASYNC(ASYNC)
) fifo_512x8(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
else if ( DATA_WIDTH <= 4 & DATA_WIDTH > 2)
begin
for (i = 0; i < 4; i=i+1)
begin
assign _d[i * 4 + 0] = 1'b0;
assign _d[i * 4 + 1] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 4 + 2] = 1'b0;
assign _d[i * 4 + 3] = 1'b0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 4 + 1];
end
end
fifo_#(
.MODE(2),
.ADDR_WIDTH(10),
.ASYNC(ASYNC)
) fifo_1024x4(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
else if ( DATA_WIDTH <= 2 & DATA_WIDTH > 0)
begin
for (i = 0; i < 2; i=i+1)
begin
assign _d[i * 8 + 2 : i * 8] = 0;
assign _d[i * 8 + 3] = i < DATA_WIDTH ? d[i] : 1'b0;
assign _d[i * 8 + 7 : i * 8 + 4] = 0;
if (i < DATA_WIDTH)
begin
assign q[i] = _q[i * 8 + 3];
end
end
fifo_#(
.MODE(3),
.ADDR_WIDTH(11),
.ASYNC(ASYNC)
) fifo_2048x2(
.w_clk(w_clk),
.r_clk(r_clk),
.we(we),
.d(_d),
.re(re),
.q(_q),
.empty(empty),
.full(full),
.mask(16'b0)
);
end
endgenerate
endmodule | 0 |
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