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3,076 | data/full_repos/permissive/102821975/Processor/DataMemory.v | 102,821,975 | DataMemory.v | v | 33 | 71 | [] | [] | [] | [(3, 33)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/DataMemory.v:27: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'DataIn\' generates 32 bits.\n : ... In instance DataMemory\n Memory[MemoryAddress]=DataIn;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 822 | module | module DataMemory(clk,Reset,MemoryAddress,memWD,memRD,DataOut,DataIn);
output reg [31:0] DataOut;
input [31:0] MemoryAddress,DataIn;
input memRD, memWD,Reset,clk;
reg [6:0] Memory [0:60348];
initial begin
DataOut=32'd0;
$readmemb("text.txt",Memory);
end
always @ (posedge clk)begin
if (memRD)begin
DataOut[6:0]=Memory[MemoryAddress];
DataOut[31:7]=25'd0;
end
else if (memWD)begin
Memory[MemoryAddress]=DataIn;
DataOut=32'd0;
end
else DataOut=MemoryAddress;
end
endmodule | module DataMemory(clk,Reset,MemoryAddress,memWD,memRD,DataOut,DataIn); |
output reg [31:0] DataOut;
input [31:0] MemoryAddress,DataIn;
input memRD, memWD,Reset,clk;
reg [6:0] Memory [0:60348];
initial begin
DataOut=32'd0;
$readmemb("text.txt",Memory);
end
always @ (posedge clk)begin
if (memRD)begin
DataOut[6:0]=Memory[MemoryAddress];
DataOut[31:7]=25'd0;
end
else if (memWD)begin
Memory[MemoryAddress]=DataIn;
DataOut=32'd0;
end
else DataOut=MemoryAddress;
end
endmodule | 1 |
3,078 | data/full_repos/permissive/102821975/Processor/ID_Ex.v | 102,821,975 | ID_Ex.v | v | 56 | 165 | [] | [] | [] | [(3, 56)] | null | data/verilator_xmls/5e37bc14-cfa9-4e14-a9a3-de26f2ac2e80.xml | null | 824 | module | module ID_Ex(clk,Reset,Enable, Opcode,BSelector,Rd,RValue1,RValue2,ImmValue,MemRD,memWD,RegWrite,OPCODE,BSELECTOR,RD,RVALUE1,RVALUE2,IMMVALUE,MEMWD,MEMRD,REGWRITE);
input wire clk, Reset, Enable;
input [4:0] Opcode;
input [0:0] BSelector;
input [4:0] Rd;
input [31:0] RValue1,RValue2;
input [31:0] ImmValue;
input [0:0] MemRD,memWD,RegWrite;
output reg[4:0] OPCODE;
output reg[0:0] REGWRITE,MEMWD,MEMRD;
output reg[0:0] BSELECTOR;
output reg[4:0] RD;
output reg[31:0] RVALUE1,RVALUE2,IMMVALUE;
initial begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
always @ (negedge clk) begin
if(Reset)begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
else if (Enable)begin
OPCODE=Opcode;
BSELECTOR=BSelector;
RVALUE1=RValue1;
RVALUE2=RValue2;
IMMVALUE=ImmValue;
MEMWD=memWD;
MEMRD=MemRD;
REGWRITE=RegWrite;
RD=Rd;
end
end
endmodule | module ID_Ex(clk,Reset,Enable, Opcode,BSelector,Rd,RValue1,RValue2,ImmValue,MemRD,memWD,RegWrite,OPCODE,BSELECTOR,RD,RVALUE1,RVALUE2,IMMVALUE,MEMWD,MEMRD,REGWRITE); |
input wire clk, Reset, Enable;
input [4:0] Opcode;
input [0:0] BSelector;
input [4:0] Rd;
input [31:0] RValue1,RValue2;
input [31:0] ImmValue;
input [0:0] MemRD,memWD,RegWrite;
output reg[4:0] OPCODE;
output reg[0:0] REGWRITE,MEMWD,MEMRD;
output reg[0:0] BSELECTOR;
output reg[4:0] RD;
output reg[31:0] RVALUE1,RVALUE2,IMMVALUE;
initial begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
always @ (negedge clk) begin
if(Reset)begin
OPCODE=5'b11111;
BSELECTOR=1'd0;
RD=5'd0;
RVALUE1=32'd0;
RVALUE2=32'd0;
IMMVALUE=32'd0;
MEMWD=1'd0;
MEMRD=1'd0;
REGWRITE=1'd0;
end
else if (Enable)begin
OPCODE=Opcode;
BSELECTOR=BSelector;
RVALUE1=RValue1;
RVALUE2=RValue2;
IMMVALUE=ImmValue;
MEMWD=memWD;
MEMRD=MemRD;
REGWRITE=RegWrite;
RD=Rd;
end
end
endmodule | 1 |
3,084 | data/full_repos/permissive/102821975/Processor/Processor.v | 102,821,975 | Processor.v | v | 264 | 98 | [] | [] | [] | [(3, 264)] | null | null | 1: b'%Error: data/full_repos/permissive/102821975/Processor/Processor.v:81: Cannot find file containing module: \'MuxData\'\n MuxData pcselectmux(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/102821975/Processor,data/full_repos/permissive/102821975/MuxData\n data/full_repos/permissive/102821975/Processor,data/full_repos/permissive/102821975/MuxData.v\n data/full_repos/permissive/102821975/Processor,data/full_repos/permissive/102821975/MuxData.sv\n MuxData\n MuxData.v\n MuxData.sv\n obj_dir/MuxData\n obj_dir/MuxData.v\n obj_dir/MuxData.sv\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:89: Cannot find file containing module: \'SimpleReg\'\n SimpleReg pcreg(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:98: Cannot find file containing module: \'InstructionMem\'\n InstructionMem insmem(\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/102821975/Processor/Processor.v:111: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'pcselect\' generates 1 bits.\n : ... In instance Processor\n assign pss=pcselect;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:113: Cannot find file containing module: \'IF_ID\'\n IF_ID ifid(.clk(clk),\n ^~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:133: Cannot find file containing module: \'SignExt\'\n SignExt signext(.SEin(imm1),.SEout(immvalue1));\n ^~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:136: Cannot find file containing module: \'ControlUnit\'\n ControlUnit ctrlunit(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:154: Cannot find file containing module: \'MuxReg\'\n MuxReg reg1(.Output(muxout1), .Input0(rs1), .Input1(rd1), .Input2(rs1),.Selector(regselector));\n ^~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:155: Cannot find file containing module: \'MuxReg\'\n MuxReg reg2(.Output(muxout2), .Input0(rt1), .Input1(rs1), .Input2(rd1),.Selector(regselector));\n ^~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:164: Cannot find file containing module: \'RegisterBanc\'\n RegisterBanc regbank(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:178: Cannot find file containing module: \'ID_Ex\'\n ID_Ex idex(\n ^~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:204: Cannot find file containing module: \'MuxData\'\n MuxData alumuxB(.Output(alumuxout), .Input0(rvalue21),.Input1(immvalue2),.Selector(bselector1));\n ^~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:207: Cannot find file containing module: \'ALU\'\n ALU alu(.A(rvalue11), .B(alumuxout), .ALUOp(opcode2) ,\n ^~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:215: Cannot find file containing module: \'EX_MEM\'\n EX_MEM exmen(\n ^~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:235: Cannot find file containing module: \'DataMemory\'\n DataMemory datamen(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/102821975/Processor/Processor.v:246: Cannot find file containing module: \'MEM_WB\'\n MEM_WB menwb(\n ^~~~~~\n%Error: Exiting due to 15 error(s), 1 warning(s)\n' | 830 | module | module Processor(clk,Reset,inst,pss,wa,imme,dat, a, b,sb,add,val,rr);
input clk, Reset;
output [31:0] inst;
output [31:0] pss;
output [4:0] wa;
output [31:0] imme;
output [31:0] dat;
output [31:0] a,b;
output sb;
output [4:0] add;
output [31:0]val,rr;
reg [0:0] newClock;
reg [5:0] move_cont;
always @ (posedge clk) begin
move_cont = move_cont + 1'b1;
newClock = move_cont[2];
end
wire [31:0] pcsignal;
wire [31:0] pc;
wire [4:0]opcode;
wire [4:0] rs,rt,rd;
wire [31:0] instruction;
wire [16:0] imm;
wire [31:0] jaddr;
wire [31:0] newpc;
wire [4:0] opcode1;
wire [4:0] rs1,rt1,rd1;
wire [16:0] imm1;
wire [31:0] jaddr1;
wire [0:0] enable1,enable2,enable3,enable4;
wire [0:0] bselector;
wire [1:0] regselector;
wire [0:0] pcselect;
wire [0:0] memrd,memwd,regwrite;
wire [4:0] muxout1;
wire [4:0] muxout2;
wire [31:0] rdata1,rdata2;
wire [0:0] bselector1;
wire [31:0] rvalue11,rvalue21;
wire [4:0] rd2;
wire [0:0] memrd1,memwd1,regwrite1;
wire [4:0] opcode2;
wire [31:0] immvalue1;
wire [31:0] immvalue2;
wire [31:0] alumuxout;
wire [0:0] zero;
wire [31:0] aluout;
wire [0:0] memrd2,memwd2,regwrite2;
wire [31:0] datain;
wire [31:0] memoryaddress;
wire [4:0] writeaddress;
wire [31:0] dataout;
wire [31:0] writedata;
wire [0:0] regwrite3;
wire [4:0] writeaddress1;
MuxData pcselectmux(
.Output(pcsignal),
.Input0(newpc),
.Input1(immvalue2),
.Selector(pcselect)
);
SimpleReg pcreg(
.clk(clk),
.Reset(Reset),
.DataIn(pcsignal),
.DataOut(pc)
);
InstructionMem insmem(
.Pc(pc),
.clk(clk),
.OpCode(opcode),
.RS(rs),
.RT(rt),
.RD(rd),
.IMM(imm),
.JADDR(jaddr),
.UsableInstruc(instruction),
.NEWPC(newpc)
);
assign inst=instruction;
assign pss=pcselect;
IF_ID ifid(.clk(clk),
.Reset(Reset),
.Enable(enable1),
.Rd(rd),
.Rs(rs),
.Rt(rt),
.Imm(imm),
.Jaddr(jaddr),
.Opcode(opcode),
.Pc(pc),
.RD(rd1),
.RS(rs1),
.RT(rt1),
.IMM(imm1),
.JADDR(jaddr1),
.OPCODE(opcode1),
.PC()
);
assign wa=rd1;
SignExt signext(.SEin(imm1),.SEout(immvalue1));
ControlUnit ctrlunit(
.clk(clk),
.OPCODE(opcode1),
.BOpCode(opcode2),
.Zero(zero),
.BSelector(bselector),
.MemRD(memrd),
.MemWD(memwd),
.RegWrite(regwrite),
.RegSelector(regselector),
.PCSelect(pcselect),
.Enable1(enable1),
.Enable2(enable2),
.Enable3(enable3),
.Enable4(enable4)
);
MuxReg reg1(.Output(muxout1), .Input0(rs1), .Input1(rd1), .Input2(rs1),.Selector(regselector));
MuxReg reg2(.Output(muxout2), .Input0(rt1), .Input1(rs1), .Input2(rd1),.Selector(regselector));
wire [31:0] r;
RegisterBanc regbank(
.ReadData1(rdata1),
.ReadData2(rdata2),
.WriteData(writedata),
.ReadAddr1(muxout1),
.ReadAddr2(muxout2),
.WriteAddr(writeaddress1),
.RegWrite(regwrite3),
.clk(clk),
.ro(r)
);
assign rr=r;
ID_Ex idex(
.clk(clk),
.Reset(Reset),
.Enable(enable2),
.Opcode(opcode1),
.BSelector(bselector),
.Rd(rd1),
.RValue1(rdata1),
.RValue2(rdata2),
.ImmValue(immvalue1),
.MemRD(memrd),
.memWD(memwd),
.RegWrite(regwrite),
.OPCODE(opcode2),
.BSELECTOR(bselector1),
.RD(rd2),
.RVALUE1(rvalue11),
.RVALUE2(rvalue21),
.IMMVALUE(immvalue2),
.MEMWD(memwd1),
.MEMRD(memrd1),
.REGWRITE(regwrite1)
);
assign imme=immvalue2;
MuxData alumuxB(.Output(alumuxout), .Input0(rvalue21),.Input1(immvalue2),.Selector(bselector1));
ALU alu(.A(rvalue11), .B(alumuxout), .ALUOp(opcode2) ,
.ALUOut(aluout), .Zero(zero));
assign sb=bselector1;
assign a=rvalue11;
assign b=alumuxout;
assign dat=aluout;
EX_MEM exmen(
.clk(clk),
.Reset(Reset),
.Enable(enable3),
.MemoryAddress(aluout),
.WriteAddress(rd2),
.DataIn(rvalue21),
.MemRD(memrd1),
.MemWD(memwd1),
.RegWrite(regwrite1),
.MEMORYADDRESS(memoryaddress),
.WRITEADDRESS(writeaddress),
.DATAIN(datain),
.MEMRD(memrd2),
.MEMWD(memwd2),
.REGWRITE(regwrite2)
);
DataMemory datamen(
.clk(clk),
.Reset(Reset),
.MemoryAddress(memoryaddress),
.memWD(memwd2),
.memRD(memrd2),
.DataOut(dataout),
.DataIn(datain)
);
MEM_WB menwb(
.clk(clk),
.Reset(Reset),
.Enable(enable4),
.RegWrite(regwrite2),
.WriteAddress(writeaddress),
.WriteData(dataout),
.REGWRITE(regwrite3),
.WRITEADDRESS(writeaddress1),
.WRITEDATA(writedata)
);
assign add=writeaddress1;
assign val=writedata;
endmodule | module Processor(clk,Reset,inst,pss,wa,imme,dat, a, b,sb,add,val,rr); |
input clk, Reset;
output [31:0] inst;
output [31:0] pss;
output [4:0] wa;
output [31:0] imme;
output [31:0] dat;
output [31:0] a,b;
output sb;
output [4:0] add;
output [31:0]val,rr;
reg [0:0] newClock;
reg [5:0] move_cont;
always @ (posedge clk) begin
move_cont = move_cont + 1'b1;
newClock = move_cont[2];
end
wire [31:0] pcsignal;
wire [31:0] pc;
wire [4:0]opcode;
wire [4:0] rs,rt,rd;
wire [31:0] instruction;
wire [16:0] imm;
wire [31:0] jaddr;
wire [31:0] newpc;
wire [4:0] opcode1;
wire [4:0] rs1,rt1,rd1;
wire [16:0] imm1;
wire [31:0] jaddr1;
wire [0:0] enable1,enable2,enable3,enable4;
wire [0:0] bselector;
wire [1:0] regselector;
wire [0:0] pcselect;
wire [0:0] memrd,memwd,regwrite;
wire [4:0] muxout1;
wire [4:0] muxout2;
wire [31:0] rdata1,rdata2;
wire [0:0] bselector1;
wire [31:0] rvalue11,rvalue21;
wire [4:0] rd2;
wire [0:0] memrd1,memwd1,regwrite1;
wire [4:0] opcode2;
wire [31:0] immvalue1;
wire [31:0] immvalue2;
wire [31:0] alumuxout;
wire [0:0] zero;
wire [31:0] aluout;
wire [0:0] memrd2,memwd2,regwrite2;
wire [31:0] datain;
wire [31:0] memoryaddress;
wire [4:0] writeaddress;
wire [31:0] dataout;
wire [31:0] writedata;
wire [0:0] regwrite3;
wire [4:0] writeaddress1;
MuxData pcselectmux(
.Output(pcsignal),
.Input0(newpc),
.Input1(immvalue2),
.Selector(pcselect)
);
SimpleReg pcreg(
.clk(clk),
.Reset(Reset),
.DataIn(pcsignal),
.DataOut(pc)
);
InstructionMem insmem(
.Pc(pc),
.clk(clk),
.OpCode(opcode),
.RS(rs),
.RT(rt),
.RD(rd),
.IMM(imm),
.JADDR(jaddr),
.UsableInstruc(instruction),
.NEWPC(newpc)
);
assign inst=instruction;
assign pss=pcselect;
IF_ID ifid(.clk(clk),
.Reset(Reset),
.Enable(enable1),
.Rd(rd),
.Rs(rs),
.Rt(rt),
.Imm(imm),
.Jaddr(jaddr),
.Opcode(opcode),
.Pc(pc),
.RD(rd1),
.RS(rs1),
.RT(rt1),
.IMM(imm1),
.JADDR(jaddr1),
.OPCODE(opcode1),
.PC()
);
assign wa=rd1;
SignExt signext(.SEin(imm1),.SEout(immvalue1));
ControlUnit ctrlunit(
.clk(clk),
.OPCODE(opcode1),
.BOpCode(opcode2),
.Zero(zero),
.BSelector(bselector),
.MemRD(memrd),
.MemWD(memwd),
.RegWrite(regwrite),
.RegSelector(regselector),
.PCSelect(pcselect),
.Enable1(enable1),
.Enable2(enable2),
.Enable3(enable3),
.Enable4(enable4)
);
MuxReg reg1(.Output(muxout1), .Input0(rs1), .Input1(rd1), .Input2(rs1),.Selector(regselector));
MuxReg reg2(.Output(muxout2), .Input0(rt1), .Input1(rs1), .Input2(rd1),.Selector(regselector));
wire [31:0] r;
RegisterBanc regbank(
.ReadData1(rdata1),
.ReadData2(rdata2),
.WriteData(writedata),
.ReadAddr1(muxout1),
.ReadAddr2(muxout2),
.WriteAddr(writeaddress1),
.RegWrite(regwrite3),
.clk(clk),
.ro(r)
);
assign rr=r;
ID_Ex idex(
.clk(clk),
.Reset(Reset),
.Enable(enable2),
.Opcode(opcode1),
.BSelector(bselector),
.Rd(rd1),
.RValue1(rdata1),
.RValue2(rdata2),
.ImmValue(immvalue1),
.MemRD(memrd),
.memWD(memwd),
.RegWrite(regwrite),
.OPCODE(opcode2),
.BSELECTOR(bselector1),
.RD(rd2),
.RVALUE1(rvalue11),
.RVALUE2(rvalue21),
.IMMVALUE(immvalue2),
.MEMWD(memwd1),
.MEMRD(memrd1),
.REGWRITE(regwrite1)
);
assign imme=immvalue2;
MuxData alumuxB(.Output(alumuxout), .Input0(rvalue21),.Input1(immvalue2),.Selector(bselector1));
ALU alu(.A(rvalue11), .B(alumuxout), .ALUOp(opcode2) ,
.ALUOut(aluout), .Zero(zero));
assign sb=bselector1;
assign a=rvalue11;
assign b=alumuxout;
assign dat=aluout;
EX_MEM exmen(
.clk(clk),
.Reset(Reset),
.Enable(enable3),
.MemoryAddress(aluout),
.WriteAddress(rd2),
.DataIn(rvalue21),
.MemRD(memrd1),
.MemWD(memwd1),
.RegWrite(regwrite1),
.MEMORYADDRESS(memoryaddress),
.WRITEADDRESS(writeaddress),
.DATAIN(datain),
.MEMRD(memrd2),
.MEMWD(memwd2),
.REGWRITE(regwrite2)
);
DataMemory datamen(
.clk(clk),
.Reset(Reset),
.MemoryAddress(memoryaddress),
.memWD(memwd2),
.memRD(memrd2),
.DataOut(dataout),
.DataIn(datain)
);
MEM_WB menwb(
.clk(clk),
.Reset(Reset),
.Enable(enable4),
.RegWrite(regwrite2),
.WriteAddress(writeaddress),
.WriteData(dataout),
.REGWRITE(regwrite3),
.WRITEADDRESS(writeaddress1),
.WRITEDATA(writedata)
);
assign add=writeaddress1;
assign val=writedata;
endmodule | 1 |
3,089 | data/full_repos/permissive/102821975/Processor/unsaved/unsaved_bb.v | 102,821,975 | unsaved_bb.v | v | 27 | 28 | [] | [] | [] | [(2, 26)] | null | data/verilator_xmls/112f86f8-c2b9-4669-ab2a-37ca2482b9cf.xml | null | 840 | module | module unsaved (
clk_clk,
pc_address,
pc_debugaccess,
pc_clken,
pc_chipselect,
pc_write,
pc_readdata,
pc_writedata,
pc_byteenable,
reset_reset,
reset_reset_req);
input clk_clk;
input [4:0] pc_address;
input pc_debugaccess;
input pc_clken;
input pc_chipselect;
input pc_write;
output [31:0] pc_readdata;
input [31:0] pc_writedata;
input [3:0] pc_byteenable;
input reset_reset;
input reset_reset_req;
endmodule | module unsaved (
clk_clk,
pc_address,
pc_debugaccess,
pc_clken,
pc_chipselect,
pc_write,
pc_readdata,
pc_writedata,
pc_byteenable,
reset_reset,
reset_reset_req); |
input clk_clk;
input [4:0] pc_address;
input pc_debugaccess;
input pc_clken;
input pc_chipselect;
input pc_write;
output [31:0] pc_readdata;
input [31:0] pc_writedata;
input [3:0] pc_byteenable;
input reset_reset;
input reset_reset_req;
endmodule | 1 |
3,091 | data/full_repos/permissive/102870077/docs/misc/mult_acc.v | 102,870,077 | mult_acc.v | v | 55 | 43 | [] | [] | [] | null | line:48: before: "$" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102870077/docs/misc/mult_acc.v:21: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 8 bits.\n : ... In instance mult_acc\n r = b;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102870077/docs/misc/mult_acc.v:27: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n : ... In instance mult_acc\n r = r +b <<i ; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 846 | module | module mult_acc (out, ina, inb, clk, clr);
input [7:0] ina, inb;
input clk, clr;
output [15:0] out;
wire [15:0] mult_out, adder_out;
reg [15:0] out;
parameter set = 10;
parameter hld = 20;
function [15:0] mult;
input [7:0] a, b ;
reg [15:0] r;
integer i ;
begin
if (a[0] == 1)
r = b;
else
r = 0 ;
for (i =1; i <=7; i = i + 1)
begin
if (a[i] == 1)
r = r +b <<i ;
end
mult = r;
end
endfunction
assign adder_out = mult_out + out;
always @ (posedge clk or posedge clr)
begin
if (clr)
out <= 16'h0000;
else
out <= adder_out;
end
assign mult_out = mult (ina, inb);
specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify
endmodule | module mult_acc (out, ina, inb, clk, clr); |
input [7:0] ina, inb;
input clk, clr;
output [15:0] out;
wire [15:0] mult_out, adder_out;
reg [15:0] out;
parameter set = 10;
parameter hld = 20;
function [15:0] mult;
input [7:0] a, b ;
reg [15:0] r;
integer i ;
begin
if (a[0] == 1)
r = b;
else
r = 0 ;
for (i =1; i <=7; i = i + 1)
begin
if (a[i] == 1)
r = r +b <<i ;
end
mult = r;
end
endfunction
assign adder_out = mult_out + out;
always @ (posedge clk or posedge clr)
begin
if (clr)
out <= 16'h0000;
else
out <= adder_out;
end
assign mult_out = mult (ina, inb);
specify
$setup (ina, posedge clk, set);
$hold (posedge clk, ina, hld);
$setup (inb, posedge clk, set);
$hold (posedge clk, inb, hld);
endspecify
endmodule | 3 |
3,092 | data/full_repos/permissive/102870077/docs/misc/mult_acc.v | 102,870,077 | mult_acc.v | v | 55 | 43 | [] | [] | [] | null | line:48: before: "$" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102870077/docs/misc/mult_acc.v:21: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 8 bits.\n : ... In instance mult_acc\n r = b;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102870077/docs/misc/mult_acc.v:27: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'b\' generates 8 bits.\n : ... In instance mult_acc\n r = r +b <<i ; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 846 | function | function [15:0] mult;
input [7:0] a, b ;
reg [15:0] r;
integer i ;
begin
if (a[0] == 1)
r = b;
else
r = 0 ;
for (i =1; i <=7; i = i + 1)
begin
if (a[i] == 1)
r = r +b <<i ;
end
mult = r;
end
endfunction | function [15:0] mult; |
input [7:0] a, b ;
reg [15:0] r;
integer i ;
begin
if (a[0] == 1)
r = b;
else
r = 0 ;
for (i =1; i <=7; i = i + 1)
begin
if (a[i] == 1)
r = r +b <<i ;
end
mult = r;
end
endfunction | 3 |
3,094 | data/full_repos/permissive/102870077/docs/misc/timer.v | 102,870,077 | timer.v | v | 101 | 120 | [] | [] | [] | [(1, 100)] | null | data/verilator_xmls/3ad0e536-cc56-4e19-b8da-f6081dcfbb5b.xml | null | 848 | module | module timer(
input wire input_clk,
input wire reset,
input wire start_elapse,
input wire stop_elapse,
output reg[4:0] out_H_min,
output reg[4:0] out_L_min,
output reg[4:0] out_H_sec,
output reg[4:0] out_L_sec,
output reg[4:0] out_sign
);
reg[4:0] H_min;
reg[4:0] L_min;
reg[4:0] H_sec;
reg[4:0] L_sec;
reg[4:0] sign;
reg end_time;
reg stoped_elapse;
initial begin
stoped_elapse <= 1'b0;
end_time <= 1'b0;
H_min <= 5'b00000;
L_min <= 5'b00001;
H_sec <= 5'b00000;
L_sec <= 5'b00000;
sign <= 5'b11111;
end
always @(posedge input_clk) begin
if (reset) begin
stoped_elapse = 1'b0;
end_time = 1'b0;
H_min = 5'b00010;
L_min = 5'b00000;
H_sec = 5'b00000;
L_sec = 5'b00000;
end
if (stop_elapse) begin
stoped_elapse = 1'b1;
end
if (start_elapse && !stoped_elapse) begin
if (!end_time) begin
sign = 5'b11111;
if (L_sec > 5'b00000) begin
L_sec = L_sec - 1'b1;
end else begin
if (H_sec > 5'b00000) begin
H_sec = H_sec - 1'b1;
L_sec = 5'b01001;
end else begin
if (L_min > 5'b00000) begin
L_min = L_min - 1'b1;
H_sec = 5'b00101;
L_sec = 5'b01001;
end else begin
if (H_min > 5'b00000) begin
H_min = H_min - 1'b1;
L_min = 5'b01001;
H_sec = 5'b00101;
L_sec = 5'b01001;
end else begin
end_time = 1'b1;
out_sign = 5'b10001;
end
end
end
end
end else begin
sign = 5'b10001;
if (L_sec < 5'b01001) begin
L_sec = L_sec + 1'b1;
end else begin
if (H_sec < 5'b00101) begin
L_sec = 5'b00000;
H_sec = H_sec + 1'b1;
end else begin
if (L_min < 5'b01001) begin
L_sec = 5'b00000;
H_sec = 5'b00000;
L_min = L_min + 1'b1;
end else begin
L_sec = 5'b00000;
H_sec = 5'b00000;
L_min = 5'b00000;
H_min = H_min + 1'b1;
end
end
end
end
end
out_H_min = H_min;
out_L_min = L_min;
out_H_sec = H_sec;
out_L_sec = L_sec;
out_sign = sign;
end
endmodule | module timer(
input wire input_clk,
input wire reset,
input wire start_elapse,
input wire stop_elapse,
output reg[4:0] out_H_min,
output reg[4:0] out_L_min,
output reg[4:0] out_H_sec,
output reg[4:0] out_L_sec,
output reg[4:0] out_sign
); |
reg[4:0] H_min;
reg[4:0] L_min;
reg[4:0] H_sec;
reg[4:0] L_sec;
reg[4:0] sign;
reg end_time;
reg stoped_elapse;
initial begin
stoped_elapse <= 1'b0;
end_time <= 1'b0;
H_min <= 5'b00000;
L_min <= 5'b00001;
H_sec <= 5'b00000;
L_sec <= 5'b00000;
sign <= 5'b11111;
end
always @(posedge input_clk) begin
if (reset) begin
stoped_elapse = 1'b0;
end_time = 1'b0;
H_min = 5'b00010;
L_min = 5'b00000;
H_sec = 5'b00000;
L_sec = 5'b00000;
end
if (stop_elapse) begin
stoped_elapse = 1'b1;
end
if (start_elapse && !stoped_elapse) begin
if (!end_time) begin
sign = 5'b11111;
if (L_sec > 5'b00000) begin
L_sec = L_sec - 1'b1;
end else begin
if (H_sec > 5'b00000) begin
H_sec = H_sec - 1'b1;
L_sec = 5'b01001;
end else begin
if (L_min > 5'b00000) begin
L_min = L_min - 1'b1;
H_sec = 5'b00101;
L_sec = 5'b01001;
end else begin
if (H_min > 5'b00000) begin
H_min = H_min - 1'b1;
L_min = 5'b01001;
H_sec = 5'b00101;
L_sec = 5'b01001;
end else begin
end_time = 1'b1;
out_sign = 5'b10001;
end
end
end
end
end else begin
sign = 5'b10001;
if (L_sec < 5'b01001) begin
L_sec = L_sec + 1'b1;
end else begin
if (H_sec < 5'b00101) begin
L_sec = 5'b00000;
H_sec = H_sec + 1'b1;
end else begin
if (L_min < 5'b01001) begin
L_sec = 5'b00000;
H_sec = 5'b00000;
L_min = L_min + 1'b1;
end else begin
L_sec = 5'b00000;
H_sec = 5'b00000;
L_min = 5'b00000;
H_min = H_min + 1'b1;
end
end
end
end
end
out_H_min = H_min;
out_L_min = L_min;
out_H_sec = H_sec;
out_L_sec = L_sec;
out_sign = sign;
end
endmodule | 3 |
3,096 | data/full_repos/permissive/102870077/engine/static/school_mips/irq/sm_ram.v | 102,870,077 | sm_ram.v | v | 22 | 33 | [] | [] | [] | null | None: at end of input | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102870077/engine/static/school_mips/irq/sm_ram.v:15: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n : ... In instance sm_ram\n assign rd = ram [a[31:2]];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102870077/engine/static/school_mips/irq/sm_ram.v:19: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n : ... In instance sm_ram\n ram[a[31:2]] <= wd;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 853 | module | module sm_ram
#(
parameter SIZE = 64
)
(
input clk,
input [31:0] a,
input we,
input [31:0] wd,
output [31:0] rd
);
reg [31:0] ram [SIZE - 1:0];
assign rd = ram [a[31:2]];
always @(posedge clk)
if (we)
ram[a[31:2]] <= wd;
endmodule | module sm_ram
#(
parameter SIZE = 64
)
(
input clk,
input [31:0] a,
input we,
input [31:0] wd,
output [31:0] rd
); |
reg [31:0] ram [SIZE - 1:0];
assign rd = ram [a[31:2]];
always @(posedge clk)
if (we)
ram[a[31:2]] <= wd;
endmodule | 3 |
3,100 | data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v | 102,870,077 | sm_gpio.v | v | 43 | 98 | [] | [] | [] | [(13, 47)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:3: Cannot find include file: sm_config.vh\n`include "sm_config.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/mmio,data/full_repos/permissive/102870077/sm_config.vh.sv\n sm_config.vh\n sm_config.vh.v\n sm_config.vh.sv\n obj_dir/sm_config.vh\n obj_dir/sm_config.vh.v\n obj_dir/sm_config.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:20: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n input [`SM_GPIO_WIDTH - 1:0] gpioInput,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:21: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:23: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioIn; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:25: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioOut; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:27: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:30: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_debouncer #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:31: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/mmio/sm_gpio.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^\n%Error: Exiting due to 10 error(s)\n' | 862 | module | module sm_gpio
(
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
wire [`SM_GPIO_WIDTH - 1:0] gpioIn;
wire gpioOutWe;
wire [`SM_GPIO_WIDTH - 1:0] gpioOut;
assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);
sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @ (*)
case(bAddr[3:0])
default : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_INPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_OUTPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
endcase
endmodule | module sm_gpio
(
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
); |
wire [`SM_GPIO_WIDTH - 1:0] gpioIn;
wire gpioOutWe;
wire [`SM_GPIO_WIDTH - 1:0] gpioOut;
assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(.SIZE(`SM_GPIO_WIDTH)) debounce(clk, gpioInput, gpioIn);
sm_register_we #(.SIZE(`SM_GPIO_WIDTH)) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @ (*)
case(bAddr[3:0])
default : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_INPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_OUTPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
endcase
endmodule | 3 |
3,112 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v | 102,870,077 | sm_pcpu.v | v | 356 | 105 | [] | [] | [] | [(69, 349), (352, 411)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:182: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:186: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:326: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:330: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n' | 873 | module | module sm_pcpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
input [31:0] dmRData
);
wire cw_pcSrc_D;
wire hz_stall_n_F;
wire hz_stall_n_D;
wire hz_flush_n_D;
wire [31:0] pc_F;
wire [31:0] pcBranch_D;
wire [31:0] pcNext_F = pc_F + 4;
wire [31:0] pcNew_F = ~cw_pcSrc_D ? pcNext_F : pcBranch_D;
sm_register_we #(32) r_pc_f (clk ,rst_n, hz_stall_n_F, pcNew_F, pc_F);
assign imAddr = pc_F >> 2;
wire [31:0] instr_F = imData;
wire [31:0] pcNext_D;
wire [31:0] instr_D;
sm_register_wes #(32) r_pcNext_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pcNext_F, pcNext_D);
sm_register_wes #(32) r_instr_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, instr_F, instr_D);
wire [31:0] regData0_D;
assign regData = (regAddr != 0) ? regData0_D : pc_F;
wire cw_regWrite_W;
wire cw_branch_D;
wire hz_forwardA_D;
wire hz_forwardB_D;
wire [ 5:0] instrOp_D = instr_D[31:26];
wire [ 5:0] instrFn_D = instr_D[ 5:0 ];
wire [ 4:0] instrRs_D = instr_D[25:21];
wire [ 4:0] instrRt_D = instr_D[20:16];
wire [ 4:0] instrRd_D = instr_D[15:11];
wire [15:0] instrImm_D = instr_D[15:0 ];
wire [ 4:0] instrSa_D = instr_D[10:6 ];
wire [ 4:0] writeReg_W;
wire [31:0] regData1_D;
wire [31:0] regData2_D;
wire [31:0] writeData_W;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instrRs_D ),
.a2 ( instrRt_D ),
.a3 ( writeReg_W ),
.rd0 ( regData0_D ),
.rd1 ( regData1_D ),
.rd2 ( regData2_D ),
.wd3 ( writeData_W ),
.we3 ( cw_regWrite_W )
);
wire [31:0] signImm_D = { {16 { instrImm_D[15] }}, instrImm_D };
assign pcBranch_D = pcNext_D + (signImm_D << 2);
wire [31:0] aluResult_M;
wire [31:0] regData1F_D = hz_forwardA_D ? aluResult_M : regData1_D;
wire [31:0] regData2F_D = hz_forwardB_D ? aluResult_M : regData2_D;
wire aluZero_D = ( regData1F_D == regData2F_D );
wire cw_regDst_D;
wire cw_regWrite_D;
wire cw_aluSrc_D;
wire [ 2:0] cw_aluCtrl_D;
wire cw_memWrite_D;
wire cw_memToReg_D;
sm_control sm_control
(
.cmdOper ( instrOp_D ),
.cmdFunk ( instrFn_D ),
.aluZero ( aluZero_D ),
.pcSrc ( cw_pcSrc_D ),
.regDst ( cw_regDst_D ),
.regWrite ( cw_regWrite_D ),
.aluSrc ( cw_aluSrc_D ),
.aluControl ( cw_aluCtrl_D ),
.memWrite ( cw_memWrite_D ),
.memToReg ( cw_memToReg_D ),
.branch ( cw_branch_D )
);
wire [31:0] pcNext_E;
wire [31:0] regData1_E;
wire [31:0] regData2_E;
wire [31:0] signImm_E;
wire [ 4:0] instrRs_E;
wire [ 4:0] instrRt_E;
wire [ 4:0] instrRd_E;
wire [ 4:0] instrSa_E;
sm_register_cs #(32) r_pcNext_E (clk, rst_n, hz_flush_n_E, pcNext_D, pcNext_E);
sm_register_cs #(32) r_regData1_E(clk, rst_n, hz_flush_n_E, regData1_D, regData1_E);
sm_register_cs #(32) r_regData2_E(clk, rst_n, hz_flush_n_E, regData2_D, regData2_E);
sm_register_cs #(32) r_signImm_E (clk, rst_n, hz_flush_n_E, signImm_D, signImm_E);
sm_register_cs #( 5) r_instrRs_E (clk, rst_n, hz_flush_n_E, instrRs_D, instrRs_E);
sm_register_cs #( 5) r_instrRt_E (clk, rst_n, hz_flush_n_E, instrRt_D, instrRt_E);
sm_register_cs #( 5) r_instrRd_E (clk, rst_n, hz_flush_n_E, instrRd_D, instrRd_E);
sm_register_cs #( 5) r_instrSa_E (clk, rst_n, hz_flush_n_E, instrSa_D, instrSa_E);
wire cw_regWrite_E;
wire cw_regDst_E;
wire cw_aluSrc_E;
wire [2:0] cw_aluCtrl_E;
wire cw_memWrite_E;
wire cw_memToReg_E;
sm_register_cs r_cw_regWrite_E (clk, rst_n, hz_flush_n_E, cw_regWrite_D, cw_regWrite_E);
sm_register_cs r_cw_regDst_E (clk, rst_n, hz_flush_n_E, cw_regDst_D, cw_regDst_E);
sm_register_cs r_cw_aluSrc_E (clk, rst_n, hz_flush_n_E, cw_aluSrc_D, cw_aluSrc_E);
sm_register_cs #(3) r_cw_aluCtrl_E (clk, rst_n, hz_flush_n_E, cw_aluCtrl_D, cw_aluCtrl_E);
sm_register_cs r_cw_memWrite_E (clk, rst_n, hz_flush_n_E, cw_memWrite_D, cw_memWrite_E);
sm_register_cs r_cw_memToReg_E (clk, rst_n, hz_flush_n_E, cw_memToReg_D, cw_memToReg_E);
wire [31:0] instr_E;
sm_register_cs #(32) r_instr_E (clk, rst_n, hz_flush_n_E, instr_D, instr_E);
wire [ 1:0] hz_forwardA_E;
wire [ 1:0] hz_forwardB_E;
wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );
wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );
wire [31:0] aluSrcB_E = cw_aluSrc_E ? signImm_E : writeData_E;
wire aluZero_E;
wire [31:0] aluResult_E;
sm_alu alu
(
.srcA ( aluSrcA_E ),
.srcB ( aluSrcB_E ),
.oper ( cw_aluCtrl_E ),
.shift ( instrSa_E ),
.zero ( aluZero_E ),
.result ( aluResult_E )
);
wire [ 4:0] writeReg_E = cw_regDst_E ? instrRd_E : instrRt_E;
wire [31:0] writeData_M;
wire [ 4:0] writeReg_M;
sm_register #(32) r_aluResult_M (clk, aluResult_E, aluResult_M);
sm_register #(32) r_writeData_M (clk, writeData_E, writeData_M);
sm_register #( 5) r_writeReg_M (clk, writeReg_E, writeReg_M);
wire cw_regWrite_M;
wire cw_memWrite_M;
wire cw_memToReg_M;
sm_register_c r_cw_regWrite_M (clk, rst_n, cw_regWrite_E, cw_regWrite_M);
sm_register_c r_cw_memWrite_M (clk, rst_n, cw_memWrite_E, cw_memWrite_M);
sm_register_c r_cw_memToReg_M (clk, rst_n, cw_memToReg_E, cw_memToReg_M);
wire [31:0] instr_M;
sm_register #(32) r_instr_M (clk, instr_E, instr_M);
wire [31:0] readData_M = dmRData;
assign dmWe = cw_memWrite_M;
assign dmAddr = aluResult_M;
assign dmWData = writeData_M;
wire [31:0] aluResult_W;
wire [31:0] readData_W;
sm_register #(32) r_aluResult_W (clk, aluResult_M, aluResult_W);
sm_register #(32) r_readData_W (clk, readData_M, readData_W);
sm_register #(5) r_writeReg_W (clk, writeReg_M, writeReg_W);
wire cw_memToReg_W;
sm_register_c r_cw_memToReg_W (clk, rst_n, cw_memToReg_M, cw_memToReg_W);
sm_register_c r_cw_regWrite_W (clk, rst_n, cw_regWrite_M, cw_regWrite_W);
wire [31:0] instr_W;
sm_register #(32) r_instr_W (clk, instr_M, instr_W);
assign writeData_W = cw_memToReg_W ? readData_W : aluResult_W;
sm_hazard_unit sm_hazard_unit
(
.instrRs_E ( instrRs_E ),
.instrRt_E ( instrRt_E ),
.writeReg_M ( writeReg_M ),
.writeReg_W ( writeReg_W ),
.cw_regWrite_M ( cw_regWrite_M ),
.cw_regWrite_W ( cw_regWrite_W ),
.hz_forwardA_E ( hz_forwardA_E ),
.hz_forwardB_E ( hz_forwardB_E ),
.instrRs_D ( instrRs_D ),
.instrRt_D ( instrRt_D ),
.writeReg_E ( writeReg_E ),
.cw_memToReg_E ( cw_memToReg_E ),
.hz_stall_n_F ( hz_stall_n_F ),
.hz_stall_n_D ( hz_stall_n_D ),
.hz_flush_n_E ( hz_flush_n_E ),
.cw_branch_D ( cw_branch_D ),
.cw_regWrite_E ( cw_regWrite_E ),
.cw_memToReg_M ( cw_memToReg_M ),
.hz_forwardA_D ( hz_forwardA_D ),
.hz_forwardB_D ( hz_forwardB_D ),
.cw_pcSrc_D ( cw_pcSrc_D ),
.hz_flush_n_D ( hz_flush_n_D )
);
endmodule | module sm_pcpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
input [31:0] dmRData
); |
wire cw_pcSrc_D;
wire hz_stall_n_F;
wire hz_stall_n_D;
wire hz_flush_n_D;
wire [31:0] pc_F;
wire [31:0] pcBranch_D;
wire [31:0] pcNext_F = pc_F + 4;
wire [31:0] pcNew_F = ~cw_pcSrc_D ? pcNext_F : pcBranch_D;
sm_register_we #(32) r_pc_f (clk ,rst_n, hz_stall_n_F, pcNew_F, pc_F);
assign imAddr = pc_F >> 2;
wire [31:0] instr_F = imData;
wire [31:0] pcNext_D;
wire [31:0] instr_D;
sm_register_wes #(32) r_pcNext_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pcNext_F, pcNext_D);
sm_register_wes #(32) r_instr_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, instr_F, instr_D);
wire [31:0] regData0_D;
assign regData = (regAddr != 0) ? regData0_D : pc_F;
wire cw_regWrite_W;
wire cw_branch_D;
wire hz_forwardA_D;
wire hz_forwardB_D;
wire [ 5:0] instrOp_D = instr_D[31:26];
wire [ 5:0] instrFn_D = instr_D[ 5:0 ];
wire [ 4:0] instrRs_D = instr_D[25:21];
wire [ 4:0] instrRt_D = instr_D[20:16];
wire [ 4:0] instrRd_D = instr_D[15:11];
wire [15:0] instrImm_D = instr_D[15:0 ];
wire [ 4:0] instrSa_D = instr_D[10:6 ];
wire [ 4:0] writeReg_W;
wire [31:0] regData1_D;
wire [31:0] regData2_D;
wire [31:0] writeData_W;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instrRs_D ),
.a2 ( instrRt_D ),
.a3 ( writeReg_W ),
.rd0 ( regData0_D ),
.rd1 ( regData1_D ),
.rd2 ( regData2_D ),
.wd3 ( writeData_W ),
.we3 ( cw_regWrite_W )
);
wire [31:0] signImm_D = { {16 { instrImm_D[15] }}, instrImm_D };
assign pcBranch_D = pcNext_D + (signImm_D << 2);
wire [31:0] aluResult_M;
wire [31:0] regData1F_D = hz_forwardA_D ? aluResult_M : regData1_D;
wire [31:0] regData2F_D = hz_forwardB_D ? aluResult_M : regData2_D;
wire aluZero_D = ( regData1F_D == regData2F_D );
wire cw_regDst_D;
wire cw_regWrite_D;
wire cw_aluSrc_D;
wire [ 2:0] cw_aluCtrl_D;
wire cw_memWrite_D;
wire cw_memToReg_D;
sm_control sm_control
(
.cmdOper ( instrOp_D ),
.cmdFunk ( instrFn_D ),
.aluZero ( aluZero_D ),
.pcSrc ( cw_pcSrc_D ),
.regDst ( cw_regDst_D ),
.regWrite ( cw_regWrite_D ),
.aluSrc ( cw_aluSrc_D ),
.aluControl ( cw_aluCtrl_D ),
.memWrite ( cw_memWrite_D ),
.memToReg ( cw_memToReg_D ),
.branch ( cw_branch_D )
);
wire [31:0] pcNext_E;
wire [31:0] regData1_E;
wire [31:0] regData2_E;
wire [31:0] signImm_E;
wire [ 4:0] instrRs_E;
wire [ 4:0] instrRt_E;
wire [ 4:0] instrRd_E;
wire [ 4:0] instrSa_E;
sm_register_cs #(32) r_pcNext_E (clk, rst_n, hz_flush_n_E, pcNext_D, pcNext_E);
sm_register_cs #(32) r_regData1_E(clk, rst_n, hz_flush_n_E, regData1_D, regData1_E);
sm_register_cs #(32) r_regData2_E(clk, rst_n, hz_flush_n_E, regData2_D, regData2_E);
sm_register_cs #(32) r_signImm_E (clk, rst_n, hz_flush_n_E, signImm_D, signImm_E);
sm_register_cs #( 5) r_instrRs_E (clk, rst_n, hz_flush_n_E, instrRs_D, instrRs_E);
sm_register_cs #( 5) r_instrRt_E (clk, rst_n, hz_flush_n_E, instrRt_D, instrRt_E);
sm_register_cs #( 5) r_instrRd_E (clk, rst_n, hz_flush_n_E, instrRd_D, instrRd_E);
sm_register_cs #( 5) r_instrSa_E (clk, rst_n, hz_flush_n_E, instrSa_D, instrSa_E);
wire cw_regWrite_E;
wire cw_regDst_E;
wire cw_aluSrc_E;
wire [2:0] cw_aluCtrl_E;
wire cw_memWrite_E;
wire cw_memToReg_E;
sm_register_cs r_cw_regWrite_E (clk, rst_n, hz_flush_n_E, cw_regWrite_D, cw_regWrite_E);
sm_register_cs r_cw_regDst_E (clk, rst_n, hz_flush_n_E, cw_regDst_D, cw_regDst_E);
sm_register_cs r_cw_aluSrc_E (clk, rst_n, hz_flush_n_E, cw_aluSrc_D, cw_aluSrc_E);
sm_register_cs #(3) r_cw_aluCtrl_E (clk, rst_n, hz_flush_n_E, cw_aluCtrl_D, cw_aluCtrl_E);
sm_register_cs r_cw_memWrite_E (clk, rst_n, hz_flush_n_E, cw_memWrite_D, cw_memWrite_E);
sm_register_cs r_cw_memToReg_E (clk, rst_n, hz_flush_n_E, cw_memToReg_D, cw_memToReg_E);
wire [31:0] instr_E;
sm_register_cs #(32) r_instr_E (clk, rst_n, hz_flush_n_E, instr_D, instr_E);
wire [ 1:0] hz_forwardA_E;
wire [ 1:0] hz_forwardB_E;
wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );
wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );
wire [31:0] aluSrcB_E = cw_aluSrc_E ? signImm_E : writeData_E;
wire aluZero_E;
wire [31:0] aluResult_E;
sm_alu alu
(
.srcA ( aluSrcA_E ),
.srcB ( aluSrcB_E ),
.oper ( cw_aluCtrl_E ),
.shift ( instrSa_E ),
.zero ( aluZero_E ),
.result ( aluResult_E )
);
wire [ 4:0] writeReg_E = cw_regDst_E ? instrRd_E : instrRt_E;
wire [31:0] writeData_M;
wire [ 4:0] writeReg_M;
sm_register #(32) r_aluResult_M (clk, aluResult_E, aluResult_M);
sm_register #(32) r_writeData_M (clk, writeData_E, writeData_M);
sm_register #( 5) r_writeReg_M (clk, writeReg_E, writeReg_M);
wire cw_regWrite_M;
wire cw_memWrite_M;
wire cw_memToReg_M;
sm_register_c r_cw_regWrite_M (clk, rst_n, cw_regWrite_E, cw_regWrite_M);
sm_register_c r_cw_memWrite_M (clk, rst_n, cw_memWrite_E, cw_memWrite_M);
sm_register_c r_cw_memToReg_M (clk, rst_n, cw_memToReg_E, cw_memToReg_M);
wire [31:0] instr_M;
sm_register #(32) r_instr_M (clk, instr_E, instr_M);
wire [31:0] readData_M = dmRData;
assign dmWe = cw_memWrite_M;
assign dmAddr = aluResult_M;
assign dmWData = writeData_M;
wire [31:0] aluResult_W;
wire [31:0] readData_W;
sm_register #(32) r_aluResult_W (clk, aluResult_M, aluResult_W);
sm_register #(32) r_readData_W (clk, readData_M, readData_W);
sm_register #(5) r_writeReg_W (clk, writeReg_M, writeReg_W);
wire cw_memToReg_W;
sm_register_c r_cw_memToReg_W (clk, rst_n, cw_memToReg_M, cw_memToReg_W);
sm_register_c r_cw_regWrite_W (clk, rst_n, cw_regWrite_M, cw_regWrite_W);
wire [31:0] instr_W;
sm_register #(32) r_instr_W (clk, instr_M, instr_W);
assign writeData_W = cw_memToReg_W ? readData_W : aluResult_W;
sm_hazard_unit sm_hazard_unit
(
.instrRs_E ( instrRs_E ),
.instrRt_E ( instrRt_E ),
.writeReg_M ( writeReg_M ),
.writeReg_W ( writeReg_W ),
.cw_regWrite_M ( cw_regWrite_M ),
.cw_regWrite_W ( cw_regWrite_W ),
.hz_forwardA_E ( hz_forwardA_E ),
.hz_forwardB_E ( hz_forwardB_E ),
.instrRs_D ( instrRs_D ),
.instrRt_D ( instrRt_D ),
.writeReg_E ( writeReg_E ),
.cw_memToReg_E ( cw_memToReg_E ),
.hz_stall_n_F ( hz_stall_n_F ),
.hz_stall_n_D ( hz_stall_n_D ),
.hz_flush_n_E ( hz_flush_n_E ),
.cw_branch_D ( cw_branch_D ),
.cw_regWrite_E ( cw_regWrite_E ),
.cw_memToReg_M ( cw_memToReg_M ),
.hz_forwardA_D ( hz_forwardA_D ),
.hz_forwardB_D ( hz_forwardB_D ),
.cw_pcSrc_D ( cw_pcSrc_D ),
.hz_flush_n_D ( hz_flush_n_D )
);
endmodule | 3 |
3,113 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v | 102,870,077 | sm_pcpu.v | v | 356 | 105 | [] | [] | [] | [(69, 349), (352, 411)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:181: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:182: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:185: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:186: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:325: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:326: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:327: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:329: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:330: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_pcpu.v:331: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n' | 873 | module | module sm_hazard_unit
(
input [ 4:0] instrRs_E,
input [ 4:0] instrRt_E,
input [ 4:0] writeReg_M,
input [ 4:0] writeReg_W,
input cw_regWrite_M,
input cw_regWrite_W,
output [ 1:0] hz_forwardA_E,
output [ 1:0] hz_forwardB_E,
input [ 4:0] instrRs_D,
input [ 4:0] instrRt_D,
input [ 4:0] writeReg_E,
input cw_memToReg_E,
output hz_stall_n_F,
output hz_stall_n_D,
output hz_flush_n_E,
input cw_branch_D,
input cw_regWrite_E,
input cw_memToReg_M,
output hz_forwardA_D,
output hz_forwardB_D,
input cw_pcSrc_D,
output hz_flush_n_D
);
assign hz_forwardA_E = ( instrRs_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
assign hz_forwardB_E = ( instrRt_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
wire hz_mem_stall = cw_memToReg_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );
assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );
wire hz_branch_stall = cw_branch_D && (
( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
|| ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
);
wire hz_stall = hz_mem_stall || hz_branch_stall;
assign hz_flush_n_D = ~cw_pcSrc_D;
assign hz_stall_n_F = ~hz_stall;
assign hz_stall_n_D = ~hz_stall;
assign hz_flush_n_E = ~hz_stall;
endmodule | module sm_hazard_unit
(
input [ 4:0] instrRs_E,
input [ 4:0] instrRt_E,
input [ 4:0] writeReg_M,
input [ 4:0] writeReg_W,
input cw_regWrite_M,
input cw_regWrite_W,
output [ 1:0] hz_forwardA_E,
output [ 1:0] hz_forwardB_E,
input [ 4:0] instrRs_D,
input [ 4:0] instrRt_D,
input [ 4:0] writeReg_E,
input cw_memToReg_E,
output hz_stall_n_F,
output hz_stall_n_D,
output hz_flush_n_E,
input cw_branch_D,
input cw_regWrite_E,
input cw_memToReg_M,
output hz_forwardA_D,
output hz_forwardB_D,
input cw_pcSrc_D,
output hz_flush_n_D
); |
assign hz_forwardA_E = ( instrRs_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
assign hz_forwardB_E = ( instrRt_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
wire hz_mem_stall = cw_memToReg_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );
assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );
wire hz_branch_stall = cw_branch_D && (
( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
|| ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
);
wire hz_stall = hz_mem_stall || hz_branch_stall;
assign hz_flush_n_D = ~cw_pcSrc_D;
assign hz_stall_n_F = ~hz_stall;
assign hz_stall_n_D = ~hz_stall;
assign hz_flush_n_E = ~hz_stall;
endmodule | 3 |
3,114 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v | 102,870,077 | sm_top.v | v | 119 | 71 | [] | [] | [] | [(33, 97), (100, 116), (119, 137)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:47: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:64: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:66: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: Exiting due to 4 error(s)\n' | 879 | module | module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
);
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);
wire [31:0] dmAddr;
wire dmWe;
wire [31:0] dmWData;
wire [31:0] dmRData;
sm_ram data_ram
(
.clk ( clk ),
.a ( dmAddr ),
.we ( dmWe ),
.wd ( dmWData ),
.rd ( dmRData )
);
`SM_CPU sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.dmAddr ( dmAddr ),
.dmWe ( dmWe ),
.dmWData ( dmWData ),
.dmRData ( dmRData )
);
endmodule | module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData
); |
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);
wire [31:0] dmAddr;
wire dmWe;
wire [31:0] dmWData;
wire [31:0] dmRData;
sm_ram data_ram
(
.clk ( clk ),
.a ( dmAddr ),
.we ( dmWe ),
.wd ( dmWData ),
.rd ( dmRData )
);
`SM_CPU sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.dmAddr ( dmAddr ),
.dmWe ( dmWe ),
.dmWData ( dmWData ),
.dmRData ( dmRData )
);
endmodule | 3 |
3,115 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v | 102,870,077 | sm_top.v | v | 119 | 71 | [] | [] | [] | [(33, 97), (100, 116), (119, 137)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:47: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:64: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:66: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: Exiting due to 4 error(s)\n' | 879 | module | module sm_debouncer
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule | module sm_debouncer
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
); |
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule | 3 |
3,116 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v | 102,870,077 | sm_top.v | v | 119 | 71 | [] | [] | [] | [(33, 97), (100, 116), (119, 137)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:47: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:64: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline/sm_top.v:66: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: Exiting due to 4 error(s)\n' | 879 | module | module sm_clk_divider
#(
parameter shift = 16,
bypass = 0
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we #(32) r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = bypass ? clkIn
: cntr[shift + devide];
endmodule | module sm_clk_divider
#(
parameter shift = 16,
bypass = 0
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
); |
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we #(32) r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = bypass ? clkIn
: cntr[shift + devide];
endmodule | 3 |
3,117 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v | 102,870,077 | ahb_gpio.v | v | 115 | 91 | [] | [] | [] | [(138, 199), (202, 236)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:10: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:32: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n output [`SM_GPIO_WIDTH - 1:0] port_gpioOut\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: Define or directive not defined: \'`HTRANS_IDLE\'\n wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:92: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n input [`SM_GPIO_WIDTH - 1:0] gpioInput,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:93: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:95: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioIn; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:97: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioOut; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:99: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:102: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_debouncer #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:103: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^\n%Error: Exiting due to 15 error(s)\n' | 880 | module | module ahb_gpio
(
input HCLK,
input HRESETn,
input HSEL,
input HWRITE,
input HREADY,
input [ 1:0] HTRANS,
input [31:0] HADDR,
output [31:0] HRDATA,
input [31:0] HWDATA,
output HREADYOUT,
output HRESP,
input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
output [`SM_GPIO_WIDTH - 1:0] port_gpioOut
);
wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;
wire request_r = request & !HWRITE;
wire request_w;
wire request_w_new = request & HWRITE;
sm_register_c r_request_w (HCLK, HRESETn, request_w_new, request_w);
wire [31:0] addr_w;
wire [31:0] addr_r = HADDR;
sm_register_we #(32) r_addr_w (HCLK, HRESETn, request, HADDR, addr_w);
wire pm_we = request_w;
wire [31:0] pm_wd = HWDATA;
wire [31:0] pm_addr = request_w ? addr_w : addr_r;
wire pm_valid = request_r | request_w;
wire [31:0] pm_rd;
sm_gpio gpio
(
.clk ( HCLK ),
.rst_n ( HRESETn ),
.bSel ( pm_valid ),
.bAddr ( pm_addr ),
.bWrite ( pm_we ),
.bWData ( pm_wd ),
.bRData ( pm_rd ),
.gpioInput ( port_gpioIn ),
.gpioOutput ( port_gpioOut )
);
wire hz_raw;
wire hz_raw_new = (request_r & request_w) | request_w_new;
sm_register_c r_hz_raw (HCLK, HRESETn, hz_raw_new, hz_raw );
assign HREADYOUT = ~hz_raw;
assign HRDATA = pm_rd;
assign HRESP = 1'b0;
endmodule | module ahb_gpio
(
input HCLK,
input HRESETn,
input HSEL,
input HWRITE,
input HREADY,
input [ 1:0] HTRANS,
input [31:0] HADDR,
output [31:0] HRDATA,
input [31:0] HWDATA,
output HREADYOUT,
output HRESP,
input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
output [`SM_GPIO_WIDTH - 1:0] port_gpioOut
); |
wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;
wire request_r = request & !HWRITE;
wire request_w;
wire request_w_new = request & HWRITE;
sm_register_c r_request_w (HCLK, HRESETn, request_w_new, request_w);
wire [31:0] addr_w;
wire [31:0] addr_r = HADDR;
sm_register_we #(32) r_addr_w (HCLK, HRESETn, request, HADDR, addr_w);
wire pm_we = request_w;
wire [31:0] pm_wd = HWDATA;
wire [31:0] pm_addr = request_w ? addr_w : addr_r;
wire pm_valid = request_r | request_w;
wire [31:0] pm_rd;
sm_gpio gpio
(
.clk ( HCLK ),
.rst_n ( HRESETn ),
.bSel ( pm_valid ),
.bAddr ( pm_addr ),
.bWrite ( pm_we ),
.bWData ( pm_wd ),
.bRData ( pm_rd ),
.gpioInput ( port_gpioIn ),
.gpioOutput ( port_gpioOut )
);
wire hz_raw;
wire hz_raw_new = (request_r & request_w) | request_w_new;
sm_register_c r_hz_raw (HCLK, HRESETn, hz_raw_new, hz_raw );
assign HREADYOUT = ~hz_raw;
assign HRDATA = pm_rd;
assign HRESP = 1'b0;
endmodule | 3 |
3,118 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v | 102,870,077 | ahb_gpio.v | v | 115 | 91 | [] | [] | [] | [(138, 199), (202, 236)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:10: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:11: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:32: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:33: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n output [`SM_GPIO_WIDTH - 1:0] port_gpioOut\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: Define or directive not defined: \'`HTRANS_IDLE\'\n wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wire request = HREADY & HSEL & HTRANS != `HTRANS_IDLE;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:92: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n input [`SM_GPIO_WIDTH - 1:0] gpioInput,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:93: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n output [`SM_GPIO_WIDTH - 1:0] gpioOutput\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:95: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioIn; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:97: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n wire [`SM_GPIO_WIDTH - 1:0] gpioOut; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:99: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:102: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_debouncer #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:103: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: Define or directive not defined: \'`SM_GPIO_WIDTH\'\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/ahb_gpio.v:105: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;\n ^\n%Error: Exiting due to 15 error(s)\n' | 880 | module | module sm_gpio
(
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
);
wire [`SM_GPIO_WIDTH - 1:0] gpioIn;
wire gpioOutWe;
wire [`SM_GPIO_WIDTH - 1:0] gpioOut;
assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);
sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @ (*)
case(bAddr[3:0])
default : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_INPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_OUTPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
endcase
endmodule | module sm_gpio
(
input clk,
input rst_n,
input bSel,
input [31:0] bAddr,
input bWrite,
input [31:0] bWData,
output reg [31:0] bRData,
input [`SM_GPIO_WIDTH - 1:0] gpioInput,
output [`SM_GPIO_WIDTH - 1:0] gpioOutput
); |
wire [`SM_GPIO_WIDTH - 1:0] gpioIn;
wire gpioOutWe;
wire [`SM_GPIO_WIDTH - 1:0] gpioOut;
assign gpioOut = bWData [`SM_GPIO_WIDTH - 1:0];
assign gpioOutWe = bSel & bWrite & (bAddr[3:0] == `SM_GPIO_REG_OUTPUT);
sm_debouncer #(`SM_GPIO_WIDTH) debounce(clk, gpioInput, gpioIn);
sm_register_we #(`SM_GPIO_WIDTH) r_output(clk, rst_n, gpioOutWe, gpioOut, gpioOutput);
localparam BLANK_WIDTH = 32 - `SM_GPIO_WIDTH;
always @ (*)
case(bAddr[3:0])
default : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_INPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioIn };
`SM_GPIO_REG_OUTPUT : bRData = { { BLANK_WIDTH {1'b0}}, gpioOut };
endcase
endmodule | 3 |
3,123 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v | 102,870,077 | sm_ahb_master.v | v | 58 | 88 | [] | [] | [] | [(34, 77)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:12: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: Define or directive not defined: \'`HTRANS_NONSEQ\'\n assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE; \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE; \n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ahb_master.v:39: Define or directive not defined: \'`HTRANS_IDLE\'\n assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE; \n ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 884 | module | module sm_ahb_master
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd,
output HCLK,
output HRESETn,
output HWRITE,
output [ 1:0] HTRANS,
output [31:0] HADDR,
input [31:0] HRDATA,
output [31:0] HWDATA,
input HREADY,
input HRESP
);
assign HCLK = clk;
assign HRESETn = rst_n;
assign HWRITE = we;
assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;
assign HADDR = a;
wire ahbReady = HREADY & ~HRESP;
wire memStart = valid;
wire memEnd = ~valid & ahbReady;
wire memWait;
wire memWait_next = memStart ? 1 :
memEnd ? 0 : memWait;
sm_register_c r_memWait(clk, rst_n, memWait_next, memWait);
assign ready = memWait ? ahbReady : 1'b1;
assign rd = HRDATA;
sm_register_we #(32) r_hwdata (clk, rst_n, valid, wd, HWDATA);
endmodule | module sm_ahb_master
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd,
output HCLK,
output HRESETn,
output HWRITE,
output [ 1:0] HTRANS,
output [31:0] HADDR,
input [31:0] HRDATA,
output [31:0] HWDATA,
input HREADY,
input HRESP
); |
assign HCLK = clk;
assign HRESETn = rst_n;
assign HWRITE = we;
assign HTRANS = valid ? `HTRANS_NONSEQ : `HTRANS_IDLE;
assign HADDR = a;
wire ahbReady = HREADY & ~HRESP;
wire memStart = valid;
wire memEnd = ~valid & ahbReady;
wire memWait;
wire memWait_next = memStart ? 1 :
memEnd ? 0 : memWait;
sm_register_c r_memWait(clk, rst_n, memWait_next, memWait);
assign ready = memWait ? ahbReady : 1'b1;
assign rd = HRDATA;
sm_register_we #(32) r_hwdata (clk, rst_n, valid, wd, HWDATA);
endmodule | 3 |
3,124 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v | 102,870,077 | sm_cpu.v | v | 339 | 110 | [] | [] | [] | [(200, 388), (390, 465), (468, 491), (493, 524)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n pcExc == `PC_ERET ? cp0_EPC :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n assign pcExc = exception ? `PC_EXC :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign pcExc = exception ? `PC_EXC :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n aluControl = `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n aluControl = `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n { `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 885 | module | module sm_cpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
output dmValid,
input dmReady,
input [31:0] dmRData
);
wire pcSrc;
wire [ 1:0] pcExc;
wire regDst;
wire regWrite;
wire aluSrc;
wire aluZero;
wire [ 2:0] aluControl;
wire memToReg;
wire memWrite;
wire memAccess;
wire hz_stall;
wire hz_mem_en;
wire [31:0] pc;
wire [31:0] pcBranch;
wire [31:0] pcNext = pc + 4;
wire [31:0] pc_new;
wire [31:0] pc_flow = ~pcSrc ? pcNext : pcBranch;
sm_register_we #(32) r_pc(clk ,rst_n, ~hz_stall, pc_new, pc);
assign imAddr = pc >> 2;
wire [31:0] instr = imData;
wire [31:0] rd0;
assign regData = (regAddr != 0) ? rd0 : pc;
wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16];
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instr[25:21] ),
.a2 ( instr[20:16] ),
.a3 ( a3 ),
.rd0 ( rd0 ),
.rd1 ( rd1 ),
.rd2 ( rd2 ),
.wd3 ( wd3 ),
.we3 ( regWrite )
);
wire [31:0] signImm = { {16 { instr[15] }}, instr[15:0] };
assign pcBranch = pcNext + (signImm << 2);
wire [31:0] aluResult;
wire [31:0] srcB = aluSrc ? signImm : rd2;
sm_alu alu
(
.srcA ( rd1 ),
.srcB ( srcB ),
.oper ( aluControl ),
.shift ( instr[10:6 ] ),
.zero ( aluZero ),
.result ( aluResult )
);
assign dmWe = memWrite;
assign dmAddr = aluResult;
assign dmWData = rd2;
assign dmValid = hz_mem_en;
wire cw_cpzToReg;
wire cw_cpzRegWrite;
wire cp0_ExcAsync;
wire cp0_ExcSync;
wire cw_cpzExcEret;
wire excRiFound;
wire cw_epcSrc;
wire cw_branch;
sm_control sm_control
(
.cmdOper ( instr[31:26] ),
.cmdRegS ( instr[25:21] ),
.cmdFunk ( instr[ 5:0 ] ),
.aluZero ( aluZero ),
.pcSrc ( pcSrc ),
.pcExc ( pcExc ),
.regDst ( regDst ),
.regWrite ( regWrite ),
.aluSrc ( aluSrc ),
.aluControl ( aluControl ),
.memWrite ( memWrite ),
.memToReg ( memToReg ),
.memAccess ( memAccess ),
.branch ( cw_branch ),
.cw_cpzToReg ( cw_cpzToReg ),
.cw_cpzRegWrite ( cw_cpzRegWrite ),
.cw_cpzExcEret ( cw_cpzExcEret ),
.excAsync ( cp0_ExcAsync ),
.excSync ( cp0_ExcSync ),
.cw_epcSrc ( cw_epcSrc ),
.excRiFound ( excRiFound )
);
wire [31:0] cp0_EPC;
wire [31:0] cp0_ExcHandler;
wire [ 4:0] cp0_regNum = instr[15:11];
wire [ 2:0] cp0_regSel = instr[ 2:0 ];
wire [31:0] cp0_regRD;
wire [31:0] cp0_regWD = rd2;
wire cp0_TI;
wire [ 5:0] cp0_ExcIP = { cp0_TI, 5'b0 };
wire cp0_ExcRI = excRiFound;
wire cp0_ExcOv = 1'b0;
wire cp0_ExcAsyncRq;
wire [31:0] cp0_PC = cw_epcSrc ? pc : pc_flow;
sm_cpz sm_cpz
(
.clk ( clk ),
.rst_n ( rst_n ),
.cp0_PC ( cp0_PC ),
.cp0_EPC ( cp0_EPC ),
.cp0_ExcHandler ( cp0_ExcHandler ),
.cp0_ExcAsyncReq( cp0_ExcAsyncRq ),
.cp0_ExcAsyncAck( cp0_ExcAsyncRq ),
.cp0_ExcAsync ( cp0_ExcAsync ),
.cp0_ExcSync ( cp0_ExcSync ),
.cp0_ExcEret ( cw_cpzExcEret ),
.cp0_regNum ( cp0_regNum ),
.cp0_regSel ( cp0_regSel ),
.cp0_regRD ( cp0_regRD ),
.cp0_regWD ( cp0_regWD ),
.cp0_regWE ( cw_cpzRegWrite ),
.cp0_ExcIP ( cp0_ExcIP ),
.cp0_ExcRI ( cp0_ExcRI ),
.cp0_ExcOv ( cp0_ExcOv ),
.cp0_TI ( cp0_TI )
);
assign wd3 = memToReg ? dmRData :
( cw_cpzToReg ? cp0_regRD : aluResult );
assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :
pcExc == `PC_ERET ? cp0_EPC :
pc_flow;
wire memWait;
wire memAccessStart = ~memWait & memAccess;
wire memAccessDone = memWait & dmReady;
wire memAccessProgress = memWait & ~dmReady;
wire memWait_new = memAccessStart ? 1 :
memAccessDone ? 0 :
memWait;
sm_register_c r_memWait(clk ,rst_n, memWait_new, memWait);
assign hz_stall = memAccessStart | memAccessProgress;
assign hz_mem_en = memAccessStart;
endmodule | module sm_cpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
output dmValid,
input dmReady,
input [31:0] dmRData
); |
wire pcSrc;
wire [ 1:0] pcExc;
wire regDst;
wire regWrite;
wire aluSrc;
wire aluZero;
wire [ 2:0] aluControl;
wire memToReg;
wire memWrite;
wire memAccess;
wire hz_stall;
wire hz_mem_en;
wire [31:0] pc;
wire [31:0] pcBranch;
wire [31:0] pcNext = pc + 4;
wire [31:0] pc_new;
wire [31:0] pc_flow = ~pcSrc ? pcNext : pcBranch;
sm_register_we #(32) r_pc(clk ,rst_n, ~hz_stall, pc_new, pc);
assign imAddr = pc >> 2;
wire [31:0] instr = imData;
wire [31:0] rd0;
assign regData = (regAddr != 0) ? rd0 : pc;
wire [ 4:0] a3 = regDst ? instr[15:11] : instr[20:16];
wire [31:0] rd1;
wire [31:0] rd2;
wire [31:0] wd3;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instr[25:21] ),
.a2 ( instr[20:16] ),
.a3 ( a3 ),
.rd0 ( rd0 ),
.rd1 ( rd1 ),
.rd2 ( rd2 ),
.wd3 ( wd3 ),
.we3 ( regWrite )
);
wire [31:0] signImm = { {16 { instr[15] }}, instr[15:0] };
assign pcBranch = pcNext + (signImm << 2);
wire [31:0] aluResult;
wire [31:0] srcB = aluSrc ? signImm : rd2;
sm_alu alu
(
.srcA ( rd1 ),
.srcB ( srcB ),
.oper ( aluControl ),
.shift ( instr[10:6 ] ),
.zero ( aluZero ),
.result ( aluResult )
);
assign dmWe = memWrite;
assign dmAddr = aluResult;
assign dmWData = rd2;
assign dmValid = hz_mem_en;
wire cw_cpzToReg;
wire cw_cpzRegWrite;
wire cp0_ExcAsync;
wire cp0_ExcSync;
wire cw_cpzExcEret;
wire excRiFound;
wire cw_epcSrc;
wire cw_branch;
sm_control sm_control
(
.cmdOper ( instr[31:26] ),
.cmdRegS ( instr[25:21] ),
.cmdFunk ( instr[ 5:0 ] ),
.aluZero ( aluZero ),
.pcSrc ( pcSrc ),
.pcExc ( pcExc ),
.regDst ( regDst ),
.regWrite ( regWrite ),
.aluSrc ( aluSrc ),
.aluControl ( aluControl ),
.memWrite ( memWrite ),
.memToReg ( memToReg ),
.memAccess ( memAccess ),
.branch ( cw_branch ),
.cw_cpzToReg ( cw_cpzToReg ),
.cw_cpzRegWrite ( cw_cpzRegWrite ),
.cw_cpzExcEret ( cw_cpzExcEret ),
.excAsync ( cp0_ExcAsync ),
.excSync ( cp0_ExcSync ),
.cw_epcSrc ( cw_epcSrc ),
.excRiFound ( excRiFound )
);
wire [31:0] cp0_EPC;
wire [31:0] cp0_ExcHandler;
wire [ 4:0] cp0_regNum = instr[15:11];
wire [ 2:0] cp0_regSel = instr[ 2:0 ];
wire [31:0] cp0_regRD;
wire [31:0] cp0_regWD = rd2;
wire cp0_TI;
wire [ 5:0] cp0_ExcIP = { cp0_TI, 5'b0 };
wire cp0_ExcRI = excRiFound;
wire cp0_ExcOv = 1'b0;
wire cp0_ExcAsyncRq;
wire [31:0] cp0_PC = cw_epcSrc ? pc : pc_flow;
sm_cpz sm_cpz
(
.clk ( clk ),
.rst_n ( rst_n ),
.cp0_PC ( cp0_PC ),
.cp0_EPC ( cp0_EPC ),
.cp0_ExcHandler ( cp0_ExcHandler ),
.cp0_ExcAsyncReq( cp0_ExcAsyncRq ),
.cp0_ExcAsyncAck( cp0_ExcAsyncRq ),
.cp0_ExcAsync ( cp0_ExcAsync ),
.cp0_ExcSync ( cp0_ExcSync ),
.cp0_ExcEret ( cw_cpzExcEret ),
.cp0_regNum ( cp0_regNum ),
.cp0_regSel ( cp0_regSel ),
.cp0_regRD ( cp0_regRD ),
.cp0_regWD ( cp0_regWD ),
.cp0_regWE ( cw_cpzRegWrite ),
.cp0_ExcIP ( cp0_ExcIP ),
.cp0_ExcRI ( cp0_ExcRI ),
.cp0_ExcOv ( cp0_ExcOv ),
.cp0_TI ( cp0_TI )
);
assign wd3 = memToReg ? dmRData :
( cw_cpzToReg ? cp0_regRD : aluResult );
assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :
pcExc == `PC_ERET ? cp0_EPC :
pc_flow;
wire memWait;
wire memAccessStart = ~memWait & memAccess;
wire memAccessDone = memWait & dmReady;
wire memAccessProgress = memWait & ~dmReady;
wire memWait_new = memAccessStart ? 1 :
memAccessDone ? 0 :
memWait;
sm_register_c r_memWait(clk ,rst_n, memWait_new, memWait);
assign hz_stall = memAccessStart | memAccessProgress;
assign hz_mem_en = memAccessStart;
endmodule | 3 |
3,125 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v | 102,870,077 | sm_cpu.v | v | 339 | 110 | [] | [] | [] | [(200, 388), (390, 465), (468, 491), (493, 524)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n pcExc == `PC_ERET ? cp0_EPC :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n assign pcExc = exception ? `PC_EXC :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign pcExc = exception ? `PC_EXC :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n aluControl = `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n aluControl = `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n { `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 885 | module | module sm_control
(
input [5:0] cmdOper,
input [4:0] cmdRegS,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output [1:0] pcExc,
output reg regDst,
output reg regWrite,
output reg aluSrc,
output reg [2:0] aluControl,
output reg memWrite,
output reg memToReg,
output reg memAccess,
output reg branch,
output reg cw_cpzToReg,
output reg cw_cpzRegWrite,
output reg cw_cpzExcEret,
input excAsync,
input excSync,
output cw_epcSrc,
output reg excRiFound
);
reg condZero;
assign pcSrc = branch & (aluZero == condZero);
assign cw_epcSrc = excSync;
wire exception = excAsync | excSync;
assign pcExc = exception ? `PC_EXC :
cw_cpzExcEret ? `PC_ERET : `PC_FLOW;
always @ (*) begin
branch = 1'b0;
condZero = 1'b0;
regDst = 1'b0;
regWrite = 1'b0;
aluSrc = 1'b0;
aluControl = `ALU_ADD;
memWrite = 1'b0;
memToReg = 1'b0;
memAccess = 1'b0;
cw_cpzToReg = 1'b0;
cw_cpzRegWrite = 1'b0;
cw_cpzExcEret = 1'b0;
excRiFound = 1'b0;
casez( {cmdOper,cmdFunk, cmdRegS} )
default : excRiFound = 1'b1;
{ `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end
{ `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end
{ `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end
{ `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLL; end
{ `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
{ `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
{ `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end
{ `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end
{ `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;
memToReg = 1'b1; memAccess = 1'b1; end
{ `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;
memAccess = 1'b1; end
{ `C_BEQ, `F_ANY, `S_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BNE, `F_ANY, `S_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
{ `C_COP0, `F_ANY, `S_COP0_MF } : begin cw_cpzToReg = 1'b1; regWrite = 1'b1; end
{ `C_COP0, `F_ANY, `S_COP0_MT } : begin cw_cpzRegWrite = 1'b1; end
{ `C_COP0, `F_ERET, `S_ERET } : begin cw_cpzExcEret = 1'b1; end
{ `C_NOP, `F_NOP, `S_NOP } : ;
endcase
end
endmodule | module sm_control
(
input [5:0] cmdOper,
input [4:0] cmdRegS,
input [5:0] cmdFunk,
input aluZero,
output pcSrc,
output [1:0] pcExc,
output reg regDst,
output reg regWrite,
output reg aluSrc,
output reg [2:0] aluControl,
output reg memWrite,
output reg memToReg,
output reg memAccess,
output reg branch,
output reg cw_cpzToReg,
output reg cw_cpzRegWrite,
output reg cw_cpzExcEret,
input excAsync,
input excSync,
output cw_epcSrc,
output reg excRiFound
); |
reg condZero;
assign pcSrc = branch & (aluZero == condZero);
assign cw_epcSrc = excSync;
wire exception = excAsync | excSync;
assign pcExc = exception ? `PC_EXC :
cw_cpzExcEret ? `PC_ERET : `PC_FLOW;
always @ (*) begin
branch = 1'b0;
condZero = 1'b0;
regDst = 1'b0;
regWrite = 1'b0;
aluSrc = 1'b0;
aluControl = `ALU_ADD;
memWrite = 1'b0;
memToReg = 1'b0;
memAccess = 1'b0;
cw_cpzToReg = 1'b0;
cw_cpzRegWrite = 1'b0;
cw_cpzExcEret = 1'b0;
excRiFound = 1'b0;
casez( {cmdOper,cmdFunk, cmdRegS} )
default : excRiFound = 1'b1;
{ `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_ADD; end
{ `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_OR; end
{ `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL; end
{ `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLL; end
{ `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
{ `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
{ `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD; end
{ `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI; end
{ `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;
memToReg = 1'b1; memAccess = 1'b1; end
{ `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;
memAccess = 1'b1; end
{ `C_BEQ, `F_ANY, `S_ANY } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
{ `C_BNE, `F_ANY, `S_ANY } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
{ `C_COP0, `F_ANY, `S_COP0_MF } : begin cw_cpzToReg = 1'b1; regWrite = 1'b1; end
{ `C_COP0, `F_ANY, `S_COP0_MT } : begin cw_cpzRegWrite = 1'b1; end
{ `C_COP0, `F_ERET, `S_ERET } : begin cw_cpzExcEret = 1'b1; end
{ `C_NOP, `F_NOP, `S_NOP } : ;
endcase
end
endmodule | 3 |
3,126 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v | 102,870,077 | sm_cpu.v | v | 339 | 110 | [] | [] | [] | [(200, 388), (390, 465), (468, 491), (493, 524)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n pcExc == `PC_ERET ? cp0_EPC :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n assign pcExc = exception ? `PC_EXC :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign pcExc = exception ? `PC_EXC :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n aluControl = `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n aluControl = `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n { `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 885 | module | module sm_alu
(
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
);
always @ (*) begin
case (oper)
default : result = srcA + srcB;
`ALU_ADD : result = srcA + srcB;
`ALU_OR : result = srcA | srcB;
`ALU_LUI : result = (srcB << 16);
`ALU_SRL : result = srcB >> shift;
`ALU_SLL : result = srcB << shift;
`ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU : result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule | module sm_alu
(
input [31:0] srcA,
input [31:0] srcB,
input [ 2:0] oper,
input [ 4:0] shift,
output zero,
output reg [31:0] result
); |
always @ (*) begin
case (oper)
default : result = srcA + srcB;
`ALU_ADD : result = srcA + srcB;
`ALU_OR : result = srcA | srcB;
`ALU_LUI : result = (srcB << 16);
`ALU_SRL : result = srcB >> shift;
`ALU_SLL : result = srcB << shift;
`ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
`ALU_SUBU : result = srcA - srcB;
endcase
end
assign zero = (result == 0);
endmodule | 3 |
3,127 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v | 102,870,077 | sm_cpu.v | v | 339 | 110 | [] | [] | [] | [(200, 388), (390, 465), (468, 491), (493, 524)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:11: Cannot find include file: sm_cpu.vh\n`include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:12: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: Define or directive not defined: \'`PC_EXC\'\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:178: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign pc_new = pcExc == `PC_EXC ? cp0_ExcHandler :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:179: Define or directive not defined: \'`PC_ERET\'\n pcExc == `PC_ERET ? cp0_EPC :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: Define or directive not defined: \'`PC_EXC\'\n assign pcExc = exception ? `PC_EXC :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:235: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign pcExc = exception ? `PC_EXC :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_ERET\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:236: Define or directive not defined: \'`PC_FLOW\'\n cw_cpzExcEret ? `PC_ERET : `PC_FLOW;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: Define or directive not defined: \'`ALU_ADD\'\n aluControl = `ALU_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:244: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n aluControl = `ALU_ADD;\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`F_ADDU\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: Define or directive not defined: \'`ALU_ADD\'\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:256: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n { `C_SPEC, `F_ADDU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_ADD; end\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`F_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:257: Define or directive not defined: \'`ALU_OR\'\n { `C_SPEC, `F_OR, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_OR; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`F_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:258: Define or directive not defined: \'`ALU_SRL\'\n { `C_SPEC, `F_SRL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SRL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`F_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:259: Define or directive not defined: \'`ALU_SLL\'\n { `C_SPEC, `F_SLL, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLL; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`F_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:260: Define or directive not defined: \'`ALU_SLTU\'\n { `C_SPEC, `F_SLTU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SLTU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`C_SPEC\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`F_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`S_ANY\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:261: Define or directive not defined: \'`ALU_SUBU\'\n { `C_SPEC, `F_SUBU, `S_ANY } : begin regDst = 1\'b1; regWrite = 1\'b1; aluControl = `ALU_SUBU; end\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`C_ADDIU\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`F_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`S_ANY\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:263: Define or directive not defined: \'`ALU_ADD\'\n { `C_ADDIU, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`C_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`F_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`S_ANY\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:264: Define or directive not defined: \'`ALU_LUI\'\n { `C_LUI, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_LUI; end\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`C_LW\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`F_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`S_ANY\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:265: Define or directive not defined: \'`ALU_ADD\'\n { `C_LW, `F_ANY, `S_ANY } : begin regWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_cpu.v:267: Define or directive not defined: \'`C_SW\'\n { `C_SW, `F_ANY, `S_ANY } : begin memWrite = 1\'b1; aluSrc = 1\'b1; aluControl = `ALU_ADD; \n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 885 | module | module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
);
reg [31:0] rf [31:0];
`ifdef SM_FORCE_RF_RDW
assign rd0 = ( a0 == 5'b0 ) ? 32'b0 :
( a0 == a3 && we3 ) ? wd3 : rf [a0];
assign rd1 = ( a1 == 5'b0 ) ? 32'b0 :
( a1 == a3 && we3 ) ? wd3 : rf [a1];
assign rd2 = ( a2 == 5'b0 ) ? 32'b0 :
( a2 == a3 && we3 ) ? wd3 : rf [a2];
`else
assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
`endif
always @ (posedge clk)
if(we3) rf [a3] <= wd3;
endmodule | module sm_register_file
(
input clk,
input [ 4:0] a0,
input [ 4:0] a1,
input [ 4:0] a2,
input [ 4:0] a3,
output [31:0] rd0,
output [31:0] rd1,
output [31:0] rd2,
input [31:0] wd3,
input we3
); |
reg [31:0] rf [31:0];
`ifdef SM_FORCE_RF_RDW
assign rd0 = ( a0 == 5'b0 ) ? 32'b0 :
( a0 == a3 && we3 ) ? wd3 : rf [a0];
assign rd1 = ( a1 == 5'b0 ) ? 32'b0 :
( a1 == a3 && we3 ) ? wd3 : rf [a1];
assign rd2 = ( a2 == 5'b0 ) ? 32'b0 :
( a2 == a3 && we3 ) ? wd3 : rf [a2];
`else
assign rd0 = (a0 != 0) ? rf [a0] : 32'b0;
assign rd1 = (a1 != 0) ? rf [a1] : 32'b0;
assign rd2 = (a2 != 0) ? rf [a2] : 32'b0;
`endif
always @ (posedge clk)
if(we3) rf [a3] <= wd3;
endmodule | 3 |
3,128 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v | 102,870,077 | sm_matrix.v | v | 140 | 80 | [] | [] | [] | null | line:139: before: "?" | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:13: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: Define or directive not defined: \'`SM_MEM_SCRATCHPAD\'\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^\n%Error: Exiting due to 3 error(s)\n' | 889 | module | module sm_matrix
#(
parameter SIZE = 64
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd,
output HCLK,
output HRESETn,
output HWRITE,
output [ 1:0] HTRANS,
output [31:0] HADDR,
input [31:0] HRDATA,
output [31:0] HWDATA,
input HREADY,
input HRESP
);
wire [ 1:0] sel;
wire [ 1:0] sel_r;
wire [ 1:0] sel_a;
assign sel = valid ? sel_a : 2'b0;
wire [ 1:0] readyout;
wire [31:0] rdata;
wire [31:0] rdata0;
wire [31:0] rdata1;
sm_ram_outbuf scratchpad_ram
(
.clk ( clk ),
.rst_n ( rst_n ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.valid ( sel [0] ),
.ready ( readyout [0] ),
.rd ( rdata0 )
);
sm_ahb_master ahb_master
(
.clk ( clk ),
.rst_n ( rst_n ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.valid ( sel [1] ),
.ready ( readyout[1] ),
.rd ( rdata1 ),
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HWRITE ( HWRITE ),
.HTRANS ( HTRANS ),
.HADDR ( HADDR ),
.HRDATA ( HRDATA ),
.HWDATA ( HWDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP )
);
sm_matrix_decoder decoder ( a, sel_a);
sm_register_we #(2) r_sel ( clk, rst_n, ready, sel, sel_r );
sm_response_mux response_mux
(
.sel ( sel_r ),
.rdata0 ( rdata0 ),
.rdata1 ( rdata1 ),
.readyout ( readyout ),
.rdata ( rd ),
.ready ( ready )
);
endmodule | module sm_matrix
#(
parameter SIZE = 64
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd,
output HCLK,
output HRESETn,
output HWRITE,
output [ 1:0] HTRANS,
output [31:0] HADDR,
input [31:0] HRDATA,
output [31:0] HWDATA,
input HREADY,
input HRESP
); |
wire [ 1:0] sel;
wire [ 1:0] sel_r;
wire [ 1:0] sel_a;
assign sel = valid ? sel_a : 2'b0;
wire [ 1:0] readyout;
wire [31:0] rdata;
wire [31:0] rdata0;
wire [31:0] rdata1;
sm_ram_outbuf scratchpad_ram
(
.clk ( clk ),
.rst_n ( rst_n ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.valid ( sel [0] ),
.ready ( readyout [0] ),
.rd ( rdata0 )
);
sm_ahb_master ahb_master
(
.clk ( clk ),
.rst_n ( rst_n ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.valid ( sel [1] ),
.ready ( readyout[1] ),
.rd ( rdata1 ),
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.HWRITE ( HWRITE ),
.HTRANS ( HTRANS ),
.HADDR ( HADDR ),
.HRDATA ( HRDATA ),
.HWDATA ( HWDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP )
);
sm_matrix_decoder decoder ( a, sel_a);
sm_register_we #(2) r_sel ( clk, rst_n, ready, sel, sel_r );
sm_response_mux response_mux
(
.sel ( sel_r ),
.rdata0 ( rdata0 ),
.rdata1 ( rdata1 ),
.readyout ( readyout ),
.rdata ( rd ),
.ready ( ready )
);
endmodule | 3 |
3,129 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v | 102,870,077 | sm_matrix.v | v | 140 | 80 | [] | [] | [] | null | line:139: before: "?" | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:13: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: Define or directive not defined: \'`SM_MEM_SCRATCHPAD\'\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^\n%Error: Exiting due to 3 error(s)\n' | 889 | module | module sm_matrix_decoder
(
input [ 31:0 ] addr,
output [ 1:0 ] sel
);
localparam SEL_AHB = 2'b10;
localparam SEL_SCR = 2'b01;
assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;
endmodule | module sm_matrix_decoder
(
input [ 31:0 ] addr,
output [ 1:0 ] sel
); |
localparam SEL_AHB = 2'b10;
localparam SEL_SCR = 2'b01;
assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;
endmodule | 3 |
3,130 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v | 102,870,077 | sm_matrix.v | v | 140 | 80 | [] | [] | [] | null | line:139: before: "?" | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:13: Cannot find include file: ahb_lite.vh\n`include "ahb_lite.vh" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/ahb_lite.vh.sv\n ahb_lite.vh\n ahb_lite.vh.v\n ahb_lite.vh.sv\n obj_dir/ahb_lite.vh\n obj_dir/ahb_lite.vh.v\n obj_dir/ahb_lite.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: Define or directive not defined: \'`SM_MEM_SCRATCHPAD\'\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_matrix.v:119: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign sel = `SM_MEM_SCRATCHPAD ? SEL_SCR : SEL_AHB;\n ^\n%Error: Exiting due to 3 error(s)\n' | 889 | module | module sm_response_mux
(
input [ 1:0 ] sel,
input [ 31:0 ] rdata0,
input [ 31:0 ] rdata1,
input [ 1:0 ] readyout,
output reg [ 31:0 ] rdata,
output reg ready
);
always @ (*)
casez (sel)
default : begin rdata = rdata0; ready = readyout[0]; end
2'b?1 : begin rdata = rdata0; ready = readyout[0]; end
2'b10 : begin rdata = rdata1; ready = readyout[1]; end
endcase
endmodule | module sm_response_mux
(
input [ 1:0 ] sel,
input [ 31:0 ] rdata0,
input [ 31:0 ] rdata1,
input [ 1:0 ] readyout,
output reg [ 31:0 ] rdata,
output reg ready
); |
always @ (*)
casez (sel)
default : begin rdata = rdata0; ready = readyout[0]; end
2'b?1 : begin rdata = rdata0; ready = readyout[0]; end
2'b10 : begin rdata = rdata1; ready = readyout[1]; end
endcase
endmodule | 3 |
3,132 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v | 102,870,077 | sm_ram_busy.v | v | 125 | 75 | [] | [] | [] | [(117, 167), (169, 195), (198, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:10: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:39: Define or directive not defined: \'`SM_CONFIG_BUSY_RAM_DELAY\'\n sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 893 | module | module sm_ram_busy
#(
parameter WIDTH = 6
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd
);
wire ibuf_we;
wire [31:0] ram_a;
wire [31:0] ram_wd;
wire ram_we;
sm_register_we #(32) r_ram_a (clk, rst_n, ibuf_we, a, ram_a );
sm_register_we #(32) r_ram_wd (clk, rst_n, ibuf_we, wd, ram_wd);
sm_register_we r_ram_we (clk, rst_n, ibuf_we, we, ram_we);
sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly
(
.clk ( clk ),
.rst_n ( rst_n ),
.valid ( valid ),
.ready ( ready ),
.start ( ibuf_we )
);
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram
(
.clk ( clk ),
.a ( ram_a ),
.we ( ram_we ),
.wd ( ram_wd ),
.rd ( ram_rd )
);
`ifdef SIMULATION
assign rd = ready & ~ram_we ? ram_rd : 32'bx;
`else
assign rd = ram_rd;
`endif
endmodule | module sm_ram_busy
#(
parameter WIDTH = 6
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd
); |
wire ibuf_we;
wire [31:0] ram_a;
wire [31:0] ram_wd;
wire ram_we;
sm_register_we #(32) r_ram_a (clk, rst_n, ibuf_we, a, ram_a );
sm_register_we #(32) r_ram_wd (clk, rst_n, ibuf_we, wd, ram_wd);
sm_register_we r_ram_we (clk, rst_n, ibuf_we, we, ram_we);
sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly
(
.clk ( clk ),
.rst_n ( rst_n ),
.valid ( valid ),
.ready ( ready ),
.start ( ibuf_we )
);
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram
(
.clk ( clk ),
.a ( ram_a ),
.we ( ram_we ),
.wd ( ram_wd ),
.rd ( ram_rd )
);
`ifdef SIMULATION
assign rd = ready & ~ram_we ? ram_rd : 32'bx;
`else
assign rd = ram_rd;
`endif
endmodule | 3 |
3,133 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v | 102,870,077 | sm_ram_busy.v | v | 125 | 75 | [] | [] | [] | [(117, 167), (169, 195), (198, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:10: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:39: Define or directive not defined: \'`SM_CONFIG_BUSY_RAM_DELAY\'\n sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 893 | module | module sm_delay
#(
parameter DELAY = 2
)
(
input clk,
input rst_n,
input valid,
output ready,
output start
);
localparam EFFECTIVE_DELAY = (DELAY > 255) ? 255 : DELAY;
wire [7:0] delay;
wire delay_min = (delay == 0);
wire delay_max = (delay == EFFECTIVE_DELAY);
wire [7:0] delay_next = delay_max ? 0 :
delay_min & ~valid ? 0 :
delay + 1;
sm_register_c #(8) r_delay (clk, rst_n, delay_next, delay);
assign ready = delay_min;
assign start = delay_min & valid;
endmodule | module sm_delay
#(
parameter DELAY = 2
)
(
input clk,
input rst_n,
input valid,
output ready,
output start
); |
localparam EFFECTIVE_DELAY = (DELAY > 255) ? 255 : DELAY;
wire [7:0] delay;
wire delay_min = (delay == 0);
wire delay_max = (delay == EFFECTIVE_DELAY);
wire [7:0] delay_next = delay_max ? 0 :
delay_min & ~valid ? 0 :
delay + 1;
sm_register_c #(8) r_delay (clk, rst_n, delay_next, delay);
assign ready = delay_min;
assign start = delay_min & valid;
endmodule | 3 |
3,134 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v | 102,870,077 | sm_ram_busy.v | v | 125 | 75 | [] | [] | [] | [(117, 167), (169, 195), (198, 226)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:10: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_ram_busy.v:39: Define or directive not defined: \'`SM_CONFIG_BUSY_RAM_DELAY\'\n sm_delay #(`SM_CONFIG_BUSY_RAM_DELAY) dly \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 893 | module | module sm_ram_outbuf
#(
parameter WIDTH = 6
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd
);
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram
(
.clk ( clk ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.rd ( ram_rd )
);
assign ready = 1'b1;
sm_register_we #(32) r_ram_rd (clk, rst_n, valid, ram_rd, rd);
endmodule | module sm_ram_outbuf
#(
parameter WIDTH = 6
)
(
input clk,
input rst_n,
input [31:0] a,
input we,
input [31:0] wd,
input valid,
output ready,
output [31:0] rd
); |
wire [31:0] ram_rd;
sm_ram #(WIDTH) ram
(
.clk ( clk ),
.a ( a ),
.we ( we ),
.wd ( wd ),
.rd ( ram_rd )
);
assign ready = 1'b1;
sm_register_we #(32) r_ram_rd (clk, rst_n, valid, ram_rd, rd);
endmodule | 3 |
3,135 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v | 102,870,077 | sm_register.v | v | 100 | 68 | [] | [] | [] | [(10, 21), (24, 41), (44, 62), (64, 80), (82, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v:64: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sm_register\'\nmodule sm_register\n ^~~~~~~~~~~\n : ... Top module \'sm_register_cs\'\nmodule sm_register_cs\n ^~~~~~~~~~~~~~\n : ... Top module \'sm_register_wes\'\nmodule sm_register_wes\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 894 | module | module sm_register
#(
parameter WIDTH = 1
)
(
input clk,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
);
always @ (posedge clk)
q <= d;
endmodule | module sm_register
#(
parameter WIDTH = 1
)
(
input clk,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
); |
always @ (posedge clk)
q <= d;
endmodule | 3 |
3,136 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v | 102,870,077 | sm_register.v | v | 100 | 68 | [] | [] | [] | [(10, 21), (24, 41), (44, 62), (64, 80), (82, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v:64: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sm_register\'\nmodule sm_register\n ^~~~~~~~~~~\n : ... Top module \'sm_register_cs\'\nmodule sm_register_cs\n ^~~~~~~~~~~~~~\n : ... Top module \'sm_register_wes\'\nmodule sm_register_wes\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 894 | module | module sm_register_c
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
);
localparam RESET = { WIDTH { 1'b0 } };
always @ (posedge clk or negedge rst_n)
if(~rst_n)
q <= RESET;
else
q <= d;
endmodule | module sm_register_c
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
); |
localparam RESET = { WIDTH { 1'b0 } };
always @ (posedge clk or negedge rst_n)
if(~rst_n)
q <= RESET;
else
q <= d;
endmodule | 3 |
3,137 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v | 102,870,077 | sm_register.v | v | 100 | 68 | [] | [] | [] | [(10, 21), (24, 41), (44, 62), (64, 80), (82, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v:64: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sm_register\'\nmodule sm_register\n ^~~~~~~~~~~\n : ... Top module \'sm_register_cs\'\nmodule sm_register_cs\n ^~~~~~~~~~~~~~\n : ... Top module \'sm_register_wes\'\nmodule sm_register_wes\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 894 | module | module sm_register_we
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input we,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
);
localparam RESET = { WIDTH { 1'b0 } };
always @ (posedge clk or negedge rst_n)
if(~rst_n)
q <= RESET;
else
if(we) q <= d;
endmodule | module sm_register_we
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input we,
input [ WIDTH - 1 : 0 ] d,
output reg [ WIDTH - 1 : 0 ] q
); |
localparam RESET = { WIDTH { 1'b0 } };
always @ (posedge clk or negedge rst_n)
if(~rst_n)
q <= RESET;
else
if(we) q <= d;
endmodule | 3 |
3,138 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v | 102,870,077 | sm_register.v | v | 100 | 68 | [] | [] | [] | [(10, 21), (24, 41), (44, 62), (64, 80), (82, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v:64: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sm_register\'\nmodule sm_register\n ^~~~~~~~~~~\n : ... Top module \'sm_register_cs\'\nmodule sm_register_cs\n ^~~~~~~~~~~~~~\n : ... Top module \'sm_register_wes\'\nmodule sm_register_wes\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 894 | module | module sm_register_cs
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input clr_n,
input [ WIDTH - 1 : 0 ] d,
output [ WIDTH - 1 : 0 ] q
);
localparam RESET = { WIDTH { 1'b0 } };
wire [ WIDTH - 1 : 0 ] dc = ~clr_n ? RESET : d;
sm_register_c #(WIDTH) r_cs (clk, rst_n, dc, q);
endmodule | module sm_register_cs
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input clr_n,
input [ WIDTH - 1 : 0 ] d,
output [ WIDTH - 1 : 0 ] q
); |
localparam RESET = { WIDTH { 1'b0 } };
wire [ WIDTH - 1 : 0 ] dc = ~clr_n ? RESET : d;
sm_register_c #(WIDTH) r_cs (clk, rst_n, dc, q);
endmodule | 3 |
3,139 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v | 102,870,077 | sm_register.v | v | 100 | 68 | [] | [] | [] | [(10, 21), (24, 41), (44, 62), (64, 80), (82, 99)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_register.v:64: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'sm_register\'\nmodule sm_register\n ^~~~~~~~~~~\n : ... Top module \'sm_register_cs\'\nmodule sm_register_cs\n ^~~~~~~~~~~~~~\n : ... Top module \'sm_register_wes\'\nmodule sm_register_wes\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 894 | module | module sm_register_wes
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input clr_n,
input we,
input [ WIDTH - 1 : 0 ] d,
output [ WIDTH - 1 : 0 ] q
);
localparam RESET = { WIDTH { 1'b0 } };
wire [ WIDTH - 1 : 0 ] dc = ~clr_n ? RESET : d;
sm_register_we #(WIDTH) r_cs (clk, rst_n, we, dc, q);
endmodule | module sm_register_wes
#(
parameter WIDTH = 1
)
(
input clk,
input rst_n,
input clr_n,
input we,
input [ WIDTH - 1 : 0 ] d,
output [ WIDTH - 1 : 0 ] q
); |
localparam RESET = { WIDTH { 1'b0 } };
wire [ WIDTH - 1 : 0 ] dc = ~clr_n ? RESET : d;
sm_register_we #(WIDTH) r_cs (clk, rst_n, we, dc, q);
endmodule | 3 |
3,141 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v | 102,870,077 | sm_top.v | v | 183 | 71 | [] | [] | [] | [(117, 244), (247, 263), (266, 284)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:13: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:54: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:100: Define or directive not defined: \'`SM_RAM\'\n `SM_RAM data_ram\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:102: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:126: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 897 | module | module sm_top
(
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData,
`ifdef SM_CONFIG_AHB_GPIO
input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
output [`SM_GPIO_WIDTH - 1:0] port_gpioOut,
`endif
input clkIn,
input rst_n
);
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);
wire [31:0] dmAddr;
wire dmWe;
wire [31:0] dmWData;
wire [31:0] dmRData;
wire dmValid;
wire dmReady;
`ifdef SM_CONFIG_AHB_LITE
wire HCLK;
wire HRESETn;
wire HWRITE;
wire [ 1:0] HTRANS;
wire [31:0] HADDR;
wire [31:0] HRDATA;
wire [31:0] HWDATA;
wire HREADY;
wire HRESP;
ahb_matrix ahb_matrix
(
.HWRITE ( HWRITE ),
.HTRANS ( HTRANS ),
.HADDR ( HADDR ),
.HRDATA ( HRDATA ),
.HWDATA ( HWDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
`ifdef SM_CONFIG_AHB_GPIO
.port_gpioIn ( port_gpioIn ),
.port_gpioOut ( port_gpioOut ),
`endif
.HCLK ( HCLK ),
.HRESETn ( HRESETn )
);
`endif
`SM_RAM data_ram
(
.clk ( clk ),
.rst_n ( rst_n ),
`ifdef SM_CONFIG_AHB_LITE
.HCLK (HCLK ),
.HRESETn (HRESETn ),
.HWRITE (HWRITE ),
.HTRANS (HTRANS ),
.HADDR (HADDR ),
.HRDATA (HRDATA ),
.HWDATA (HWDATA ),
.HREADY (HREADY ),
.HRESP (HRESP ),
`endif
.a ( dmAddr ),
.we ( dmWe ),
.wd ( dmWData ),
.valid ( dmValid ),
.ready ( dmReady ),
.rd ( dmRData )
);
`SM_CPU sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.dmAddr ( dmAddr ),
.dmWe ( dmWe ),
.dmWData ( dmWData ),
.dmValid ( dmValid ),
.dmReady ( dmReady ),
.dmRData ( dmRData )
);
endmodule | module sm_top
(
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData,
`ifdef SM_CONFIG_AHB_GPIO
input [`SM_GPIO_WIDTH - 1:0] port_gpioIn,
output [`SM_GPIO_WIDTH - 1:0] port_gpioOut,
`endif
input clkIn,
input rst_n
); |
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_debouncer #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_debouncer #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_debouncer #(.SIZE(5)) f2(clkIn, regAddr, addr );
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);
wire [31:0] dmAddr;
wire dmWe;
wire [31:0] dmWData;
wire [31:0] dmRData;
wire dmValid;
wire dmReady;
`ifdef SM_CONFIG_AHB_LITE
wire HCLK;
wire HRESETn;
wire HWRITE;
wire [ 1:0] HTRANS;
wire [31:0] HADDR;
wire [31:0] HRDATA;
wire [31:0] HWDATA;
wire HREADY;
wire HRESP;
ahb_matrix ahb_matrix
(
.HWRITE ( HWRITE ),
.HTRANS ( HTRANS ),
.HADDR ( HADDR ),
.HRDATA ( HRDATA ),
.HWDATA ( HWDATA ),
.HREADY ( HREADY ),
.HRESP ( HRESP ),
`ifdef SM_CONFIG_AHB_GPIO
.port_gpioIn ( port_gpioIn ),
.port_gpioOut ( port_gpioOut ),
`endif
.HCLK ( HCLK ),
.HRESETn ( HRESETn )
);
`endif
`SM_RAM data_ram
(
.clk ( clk ),
.rst_n ( rst_n ),
`ifdef SM_CONFIG_AHB_LITE
.HCLK (HCLK ),
.HRESETn (HRESETn ),
.HWRITE (HWRITE ),
.HTRANS (HTRANS ),
.HADDR (HADDR ),
.HRDATA (HRDATA ),
.HWDATA (HWDATA ),
.HREADY (HREADY ),
.HRESP (HRESP ),
`endif
.a ( dmAddr ),
.we ( dmWe ),
.wd ( dmWData ),
.valid ( dmValid ),
.ready ( dmReady ),
.rd ( dmRData )
);
`SM_CPU sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.dmAddr ( dmAddr ),
.dmWe ( dmWe ),
.dmWData ( dmWData ),
.dmValid ( dmValid ),
.dmReady ( dmReady ),
.dmRData ( dmRData )
);
endmodule | 3 |
3,142 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v | 102,870,077 | sm_top.v | v | 183 | 71 | [] | [] | [] | [(117, 244), (247, 263), (266, 284)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:13: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:54: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:100: Define or directive not defined: \'`SM_RAM\'\n `SM_RAM data_ram\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:102: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:126: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 897 | module | module sm_debouncer
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule | module sm_debouncer
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
); |
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule | 3 |
3,143 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v | 102,870,077 | sm_top.v | v | 183 | 71 | [] | [] | [] | [(117, 244), (247, 263), (266, 284)] | null | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:13: Cannot find include file: sm_settings.vh\n`include "sm_settings.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb,data/full_repos/permissive/102870077/sm_settings.vh.sv\n sm_settings.vh\n sm_settings.vh.v\n sm_settings.vh.sv\n obj_dir/sm_settings.vh\n obj_dir/sm_settings.vh.v\n obj_dir/sm_settings.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:54: Define or directive not defined: \'`SM_CONFIG_ROM_SIZE\'\n sm_rom #(`SM_CONFIG_ROM_SIZE) reset_rom(imAddr, imData);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:100: Define or directive not defined: \'`SM_RAM\'\n `SM_RAM data_ram\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:102: syntax error, unexpected \'(\', expecting IDENTIFIER\n .clk ( clk ),\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_ahb/sm_top.v:126: Define or directive not defined: \'`SM_CPU\'\n `SM_CPU sm_cpu\n ^~~~~~~\n%Error: Exiting due to 5 error(s)\n' | 897 | module | module sm_clk_divider
#(
parameter shift = 16,
bypass = 0
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we #(32) r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = bypass ? clkIn
: cntr[shift + devide];
endmodule | module sm_clk_divider
#(
parameter shift = 16,
bypass = 0
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
); |
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we #(32) r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = bypass ? clkIn
: cntr[shift + devide];
endmodule | 3 |
3,144 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v | 102,870,077 | sm_pcpu.v | v | 513 | 121 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: Define or directive not defined: \'`HZ_FW_EF\'\n wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:53: Define or directive not defined: \'`HZ_FW_MF\'\n ( hz_forwardEPC_F == `HZ_FW_MF ) ? writeData_M :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: Define or directive not defined: \'`PC_EXC\'\n wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:57: Define or directive not defined: \'`PC_ERET\'\n cw_pcExc_D == `PC_ERET ? EPC_F :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:236: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: Define or directive not defined: \'`HZ_FW_WE\'\n assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:240: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:464: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:468: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n instrRd_E == `CP0_REG_NUM_EPC && \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n instrRd_E == `CP0_REG_NUM_EPC && \n ^~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`HZ_FW_EF\'\n instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:504: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n instrRd_M == `CP0_REG_NUM_EPC && \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_MF\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_NONE\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n' | 902 | module | module sm_pcpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
input [31:0] dmRData
);
wire cw_pcSrc_D;
wire [ 1:0] cw_pcExc_D;
wire hz_stall_n_F;
wire hz_cancel_branch_F;
wire hz_stall_n_D;
wire hz_flush_n_D;
wire [1:0] hz_forwardEPC_F;
wire [31:0] pc_F;
wire [31:0] pcBranch_D;
wire [31:0] pcNext_F = pc_F + 4;
wire [31:0] pcFlow_F = cw_pcSrc_D & ~hz_cancel_branch_F ? pcBranch_D : pcNext_F;
wire [31:0] cp0_ExcHandler_M;
wire [31:0] cp0_EPC_M;
wire [31:0] writeData_E;
wire [31:0] writeData_M;
wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :
( hz_forwardEPC_F == `HZ_FW_MF ) ? writeData_M :
cp0_EPC_M;
wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :
cw_pcExc_D == `PC_ERET ? EPC_F :
pcFlow_F;
sm_register_we #(32) r_pc_f (clk ,rst_n, hz_stall_n_F, pcNew_F, pc_F);
assign imAddr = pc_F >> 2;
wire [31:0] instr_F = imData;
wire [31:0] pc_D;
wire [31:0] pcNext_D;
wire [31:0] instr_D;
sm_register_wes #(32) r_pc_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pc_F, pc_D);
sm_register_wes #(32) r_pcNext_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pcNext_F, pcNext_D);
sm_register_wes #(32) r_instr_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, instr_F, instr_D);
wire [31:0] regData0_D;
assign regData = (regAddr != 0) ? regData0_D : pc_F;
wire cw_regWrite_W;
wire cw_branch_D;
wire hz_forwardA_D;
wire hz_forwardB_D;
wire hz_irq_disable_D;
wire hz_flush_n_E;
wire [ 5:0] instrOp_D = instr_D[31:26];
wire [ 5:0] instrFn_D = instr_D[ 5:0 ];
wire [ 4:0] instrRs_D = instr_D[25:21];
wire [ 4:0] instrRt_D = instr_D[20:16];
wire [ 4:0] instrRd_D = instr_D[15:11];
wire [15:0] instrImm_D = instr_D[15:0 ];
wire [ 4:0] instrSa_D = instr_D[10:6 ];
wire [ 2:0] instrSel_D = instr_D[ 2:0 ];
wire [ 4:0] writeReg_W;
wire [31:0] regData1_D;
wire [31:0] regData2_D;
wire [31:0] writeData_W;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instrRs_D ),
.a2 ( instrRt_D ),
.a3 ( writeReg_W ),
.rd0 ( regData0_D ),
.rd1 ( regData1_D ),
.rd2 ( regData2_D ),
.wd3 ( writeData_W ),
.we3 ( cw_regWrite_W )
);
wire [31:0] signImm_D = { {16 { instrImm_D[15] }}, instrImm_D };
assign pcBranch_D = pcNext_D + (signImm_D << 2);
wire [31:0] aluResult_M;
wire [31:0] regData1F_D = hz_forwardA_D ? aluResult_M : regData1_D;
wire [31:0] regData2F_D = hz_forwardB_D ? aluResult_M : regData2_D;
wire aluZero_D = ( regData1F_D == regData2F_D );
wire cw_regDst_D;
wire cw_regWrite_D;
wire cw_aluSrc_D;
wire [ 2:0] cw_aluCtrl_D;
wire cw_memWrite_D;
wire cw_memToReg_D;
wire cw_cpzToReg_D;
wire cw_cpzRegWrite_D;
wire cw_cpzExcEret_D;
wire excRiFound_D;
wire cp0_ExcAsyncReq_M;
wire irqRequest_D = cp0_ExcAsyncReq_M & ~hz_irq_disable_D;
wire excSync_D = excRiFound_D;
wire cw_epcSrc_D;
wire [31:0] epcNext_D = cw_epcSrc_D ? pc_D : pcFlow_F;
sm_control sm_control
(
.cmdOper ( instrOp_D ),
.cmdRegS ( instrRs_D ),
.cmdFunk ( instrFn_D ),
.aluZero ( aluZero_D ),
.pcSrc ( cw_pcSrc_D ),
.pcExc ( cw_pcExc_D ),
.regDst ( cw_regDst_D ),
.regWrite ( cw_regWrite_D ),
.aluSrc ( cw_aluSrc_D ),
.aluControl ( cw_aluCtrl_D ),
.memWrite ( cw_memWrite_D ),
.memToReg ( cw_memToReg_D ),
.branch ( cw_branch_D ),
.cw_cpzToReg ( cw_cpzToReg_D ),
.cw_cpzRegWrite ( cw_cpzRegWrite_D ),
.cw_cpzExcEret ( cw_cpzExcEret_D ),
.excAsync ( irqRequest_D ),
.excSync ( excSync_D ),
.cw_epcSrc ( cw_epcSrc_D ),
.excRiFound ( excRiFound_D )
);
wire [31:0] epcNext_E;
wire [31:0] regData1_E;
wire [31:0] regData2_E;
wire [31:0] signImm_E;
wire [ 4:0] instrRs_E;
wire [ 4:0] instrRt_E;
wire [ 4:0] instrRd_E;
wire [ 4:0] instrSa_E;
wire [ 2:0] instrSel_E;
wire excRiFound_E;
wire irqRequest_E;
sm_register_cs #(32) r_epcNext_E (clk, rst_n, hz_flush_n_E, epcNext_D, epcNext_E);
sm_register_cs #(32) r_regData1_E(clk, rst_n, hz_flush_n_E, regData1_D, regData1_E);
sm_register_cs #(32) r_regData2_E(clk, rst_n, hz_flush_n_E, regData2_D, regData2_E);
sm_register_cs #(32) r_signImm_E (clk, rst_n, hz_flush_n_E, signImm_D, signImm_E);
sm_register_cs #( 5) r_instrRs_E (clk, rst_n, hz_flush_n_E, instrRs_D, instrRs_E);
sm_register_cs #( 5) r_instrRt_E (clk, rst_n, hz_flush_n_E, instrRt_D, instrRt_E);
sm_register_cs #( 5) r_instrRd_E (clk, rst_n, hz_flush_n_E, instrRd_D, instrRd_E);
sm_register_cs #( 5) r_instrSa_E (clk, rst_n, hz_flush_n_E, instrSa_D, instrSa_E);
sm_register_cs #( 3) r_instrSel_E(clk, rst_n, hz_flush_n_E, instrSel_D, instrSel_E);
sm_register_cs r_excRiFound_E (clk, rst_n, hz_flush_n_E, excRiFound_D, excRiFound_E);
sm_register_cs r_irqRequest_E (clk, rst_n, hz_flush_n_E, irqRequest_D, irqRequest_E);
wire cw_regWrite_E;
wire cw_regDst_E;
wire cw_aluSrc_E;
wire [2:0] cw_aluCtrl_E;
wire cw_memWrite_E;
wire cw_memToReg_E;
wire cw_cpzRegWrite_E;
wire cw_cpzExcEret_E;
wire cw_cpzToReg_E;
sm_register_cs r_cw_regWrite_E (clk, rst_n, hz_flush_n_E, cw_regWrite_D, cw_regWrite_E);
sm_register_cs r_cw_regDst_E (clk, rst_n, hz_flush_n_E, cw_regDst_D, cw_regDst_E);
sm_register_cs r_cw_aluSrc_E (clk, rst_n, hz_flush_n_E, cw_aluSrc_D, cw_aluSrc_E);
sm_register_cs #(3) r_cw_aluCtrl_E (clk, rst_n, hz_flush_n_E, cw_aluCtrl_D, cw_aluCtrl_E);
sm_register_cs r_cw_memWrite_E (clk, rst_n, hz_flush_n_E, cw_memWrite_D, cw_memWrite_E);
sm_register_cs r_cw_memToReg_E (clk, rst_n, hz_flush_n_E, cw_memToReg_D, cw_memToReg_E);
sm_register_cs r_cw_cpzRegWrite_E (clk, rst_n, hz_flush_n_E, cw_cpzRegWrite_D, cw_cpzRegWrite_E);
sm_register_cs r_cw_cpzExcEret_E (clk, rst_n, hz_flush_n_E, cw_cpzExcEret_D, cw_cpzExcEret_E);
sm_register_cs r_cw_cpzToReg_E (clk, rst_n, hz_flush_n_E, cw_cpzToReg_D, cw_cpzToReg_E);
wire [31:0] instr_E;
sm_register_cs #(32) r_instr_E (clk, rst_n, hz_flush_n_E, instr_D, instr_E);
wire [ 1:0] hz_forwardA_E;
wire [ 1:0] hz_forwardB_E;
wire hz_forwardEPC_E;
wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );
assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );
wire [31:0] aluSrcB_E = cw_aluSrc_E ? signImm_E : writeData_E;
wire aluZero_E;
wire [31:0] aluResult_E;
sm_alu alu
(
.srcA ( aluSrcA_E ),
.srcB ( aluSrcB_E ),
.oper ( cw_aluCtrl_E ),
.shift ( instrSa_E ),
.zero ( aluZero_E ),
.result ( aluResult_E )
);
wire [ 4:0] writeReg_E = cw_regDst_E ? instrRd_E : instrRt_E;
wire [31:0] epcNext_f_E = hz_forwardEPC_E ? pcBranch_D : epcNext_E;
wire [31:0] epcNext_M;
wire [ 4:0] writeReg_M;
wire [ 4:0] instrRd_M;
wire [ 2:0] instrSel_M;
wire excRiFound_M;
wire irqRequest_M;
sm_register #(32) r_epcNext_M (clk, epcNext_f_E, epcNext_M);
sm_register #(32) r_aluResult_M (clk, aluResult_E, aluResult_M);
sm_register #(32) r_writeData_M (clk, writeData_E, writeData_M);
sm_register #( 5) r_writeReg_M (clk, writeReg_E, writeReg_M);
sm_register #( 5) r_instrRd_M (clk, instrRd_E, instrRd_M);
sm_register #( 3) r_instrSel_M (clk, instrSel_E, instrSel_M);
sm_register r_excRiFound_M(clk, excRiFound_E, excRiFound_M);
sm_register_c r_irqRequest_M (clk, rst_n, irqRequest_E, irqRequest_M);
wire cw_regWrite_M;
wire cw_memWrite_M;
wire cw_memToReg_M;
wire cw_cpzRegWrite_M;
wire cw_cpzExcEret_M;
wire cw_cpzToReg_M;
sm_register_c r_cw_regWrite_M (clk, rst_n, cw_regWrite_E, cw_regWrite_M);
sm_register_c r_cw_memWrite_M (clk, rst_n, cw_memWrite_E, cw_memWrite_M);
sm_register_c r_cw_memToReg_M (clk, rst_n, cw_memToReg_E, cw_memToReg_M);
sm_register_c r_cw_cpzRegWrite_M (clk, rst_n, cw_cpzRegWrite_E, cw_cpzRegWrite_M);
sm_register_c r_cw_cpzExcEret_M (clk, rst_n, cw_cpzExcEret_E, cw_cpzExcEret_M);
sm_register_c r_cw_cpzToReg_M (clk, rst_n, cw_cpzToReg_E, cw_cpzToReg_M);
wire [31:0] instr_M;
sm_register #(32) r_instr_M (clk, instr_E, instr_M);
wire [31:0] readData_M = dmRData;
assign dmWe = cw_memWrite_M;
assign dmAddr = aluResult_M;
assign dmWData = writeData_M;
wire cp0_ExcSync_M;
wire cp0_ExcAsync_M;
wire cp0_ExcOv_M = 1'b0;
wire [31:0] cp0_Data_M;
wire cp0_TI_M;
wire [5:0] cp0_ExcIP_M = { cp0_TI_M, 5'b0 };
sm_cpz sm_cpz
(
.clk ( clk ),
.rst_n ( rst_n ),
.cp0_PC ( epcNext_M ),
.cp0_EPC ( cp0_EPC_M ),
.cp0_ExcHandler ( cp0_ExcHandler_M ),
.cp0_ExcAsyncReq ( cp0_ExcAsyncReq_M ),
.cp0_ExcAsyncAck ( irqRequest_M ),
.cp0_ExcAsync ( cp0_ExcAsync_M ),
.cp0_ExcSync ( cp0_ExcSync_M ),
.cp0_ExcEret ( cw_cpzExcEret_M ),
.cp0_regNum ( instrRd_M ),
.cp0_regSel ( instrSel_M ),
.cp0_regRD ( cp0_Data_M ),
.cp0_regWD ( writeData_M ),
.cp0_regWE ( cw_cpzRegWrite_M ),
.cp0_ExcIP ( cp0_ExcIP_M ),
.cp0_ExcRI ( excRiFound_M ),
.cp0_ExcOv ( cp0_ExcOv_M ),
.cp0_TI ( cp0_TI_M )
);
wire [31:0] aluResult_W;
wire [31:0] readData_W;
wire [31:0] cp0_Data_W;
sm_register #(32) r_aluResult_W (clk, aluResult_M, aluResult_W);
sm_register #(32) r_readData_W (clk, readData_M, readData_W);
sm_register #(32) r_cp0_Data_W (clk, cp0_Data_M, cp0_Data_W);
sm_register #(5) r_writeReg_W (clk, writeReg_M, writeReg_W);
wire cw_memToReg_W;
wire cw_cpzToReg_W;
sm_register_c r_cw_memToReg_W (clk, rst_n, cw_memToReg_M, cw_memToReg_W);
sm_register_c r_cw_cpzToReg_W (clk, rst_n, cw_cpzToReg_M, cw_cpzToReg_W);
sm_register_c r_cw_regWrite_W (clk, rst_n, cw_regWrite_M, cw_regWrite_W);
wire [31:0] instr_W;
sm_register #(32) r_instr_W (clk, instr_M, instr_W);
assign writeData_W = cw_memToReg_W ? readData_W :
cw_cpzToReg_W ? cp0_Data_W : aluResult_W;
sm_hazard_unit sm_hazard_unit
(
.instrRs_E ( instrRs_E ),
.instrRt_E ( instrRt_E ),
.writeReg_M ( writeReg_M ),
.writeReg_W ( writeReg_W ),
.cw_regWrite_M ( cw_regWrite_M ),
.cw_regWrite_W ( cw_regWrite_W ),
.hz_forwardA_E ( hz_forwardA_E ),
.hz_forwardB_E ( hz_forwardB_E ),
.instrRs_D ( instrRs_D ),
.instrRt_D ( instrRt_D ),
.writeReg_E ( writeReg_E ),
.cw_memToReg_E ( cw_memToReg_E ),
.hz_stall_n_F ( hz_stall_n_F ),
.hz_stall_n_D ( hz_stall_n_D ),
.hz_flush_n_E ( hz_flush_n_E ),
.cw_branch_D ( cw_branch_D ),
.cw_regWrite_E ( cw_regWrite_E ),
.cw_memToReg_M ( cw_memToReg_M ),
.hz_forwardA_D ( hz_forwardA_D ),
.hz_forwardB_D ( hz_forwardB_D ),
.cw_cpzToReg_E ( cw_cpzToReg_E ),
.cw_pcSrc_D ( cw_pcSrc_D ),
.irqRequest_E ( irqRequest_E ),
.irqRequest_M ( irqRequest_M ),
.hz_flush_n_D ( hz_flush_n_D ),
.cw_cpzExcEret_D ( cw_cpzExcEret_D ),
.excSync_D ( excSync_D ),
.hz_cancel_branch_F ( hz_cancel_branch_F ),
.hz_forwardEPC_E ( hz_forwardEPC_E ),
.hz_irq_disable_D ( hz_irq_disable_D ),
.hz_forwardEPC_F ( hz_forwardEPC_F ),
.cw_cpzRegWrite_E ( cw_cpzRegWrite_E ),
.cw_cpzRegWrite_M ( cw_cpzRegWrite_M ),
.instrRd_E ( instrRd_E ),
.instrRd_M ( instrRd_M ),
.instrSel_E ( instrSel_E ),
.instrSel_M ( instrSel_M )
);
endmodule | module sm_pcpu
(
input clk,
input rst_n,
input [ 4:0] regAddr,
output [31:0] regData,
output [31:0] imAddr,
input [31:0] imData,
output [31:0] dmAddr,
output dmWe,
output [31:0] dmWData,
input [31:0] dmRData
); |
wire cw_pcSrc_D;
wire [ 1:0] cw_pcExc_D;
wire hz_stall_n_F;
wire hz_cancel_branch_F;
wire hz_stall_n_D;
wire hz_flush_n_D;
wire [1:0] hz_forwardEPC_F;
wire [31:0] pc_F;
wire [31:0] pcBranch_D;
wire [31:0] pcNext_F = pc_F + 4;
wire [31:0] pcFlow_F = cw_pcSrc_D & ~hz_cancel_branch_F ? pcBranch_D : pcNext_F;
wire [31:0] cp0_ExcHandler_M;
wire [31:0] cp0_EPC_M;
wire [31:0] writeData_E;
wire [31:0] writeData_M;
wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :
( hz_forwardEPC_F == `HZ_FW_MF ) ? writeData_M :
cp0_EPC_M;
wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :
cw_pcExc_D == `PC_ERET ? EPC_F :
pcFlow_F;
sm_register_we #(32) r_pc_f (clk ,rst_n, hz_stall_n_F, pcNew_F, pc_F);
assign imAddr = pc_F >> 2;
wire [31:0] instr_F = imData;
wire [31:0] pc_D;
wire [31:0] pcNext_D;
wire [31:0] instr_D;
sm_register_wes #(32) r_pc_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pc_F, pc_D);
sm_register_wes #(32) r_pcNext_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, pcNext_F, pcNext_D);
sm_register_wes #(32) r_instr_D (clk, rst_n, hz_flush_n_D, hz_stall_n_D, instr_F, instr_D);
wire [31:0] regData0_D;
assign regData = (regAddr != 0) ? regData0_D : pc_F;
wire cw_regWrite_W;
wire cw_branch_D;
wire hz_forwardA_D;
wire hz_forwardB_D;
wire hz_irq_disable_D;
wire hz_flush_n_E;
wire [ 5:0] instrOp_D = instr_D[31:26];
wire [ 5:0] instrFn_D = instr_D[ 5:0 ];
wire [ 4:0] instrRs_D = instr_D[25:21];
wire [ 4:0] instrRt_D = instr_D[20:16];
wire [ 4:0] instrRd_D = instr_D[15:11];
wire [15:0] instrImm_D = instr_D[15:0 ];
wire [ 4:0] instrSa_D = instr_D[10:6 ];
wire [ 2:0] instrSel_D = instr_D[ 2:0 ];
wire [ 4:0] writeReg_W;
wire [31:0] regData1_D;
wire [31:0] regData2_D;
wire [31:0] writeData_W;
sm_register_file rf
(
.clk ( clk ),
.a0 ( regAddr ),
.a1 ( instrRs_D ),
.a2 ( instrRt_D ),
.a3 ( writeReg_W ),
.rd0 ( regData0_D ),
.rd1 ( regData1_D ),
.rd2 ( regData2_D ),
.wd3 ( writeData_W ),
.we3 ( cw_regWrite_W )
);
wire [31:0] signImm_D = { {16 { instrImm_D[15] }}, instrImm_D };
assign pcBranch_D = pcNext_D + (signImm_D << 2);
wire [31:0] aluResult_M;
wire [31:0] regData1F_D = hz_forwardA_D ? aluResult_M : regData1_D;
wire [31:0] regData2F_D = hz_forwardB_D ? aluResult_M : regData2_D;
wire aluZero_D = ( regData1F_D == regData2F_D );
wire cw_regDst_D;
wire cw_regWrite_D;
wire cw_aluSrc_D;
wire [ 2:0] cw_aluCtrl_D;
wire cw_memWrite_D;
wire cw_memToReg_D;
wire cw_cpzToReg_D;
wire cw_cpzRegWrite_D;
wire cw_cpzExcEret_D;
wire excRiFound_D;
wire cp0_ExcAsyncReq_M;
wire irqRequest_D = cp0_ExcAsyncReq_M & ~hz_irq_disable_D;
wire excSync_D = excRiFound_D;
wire cw_epcSrc_D;
wire [31:0] epcNext_D = cw_epcSrc_D ? pc_D : pcFlow_F;
sm_control sm_control
(
.cmdOper ( instrOp_D ),
.cmdRegS ( instrRs_D ),
.cmdFunk ( instrFn_D ),
.aluZero ( aluZero_D ),
.pcSrc ( cw_pcSrc_D ),
.pcExc ( cw_pcExc_D ),
.regDst ( cw_regDst_D ),
.regWrite ( cw_regWrite_D ),
.aluSrc ( cw_aluSrc_D ),
.aluControl ( cw_aluCtrl_D ),
.memWrite ( cw_memWrite_D ),
.memToReg ( cw_memToReg_D ),
.branch ( cw_branch_D ),
.cw_cpzToReg ( cw_cpzToReg_D ),
.cw_cpzRegWrite ( cw_cpzRegWrite_D ),
.cw_cpzExcEret ( cw_cpzExcEret_D ),
.excAsync ( irqRequest_D ),
.excSync ( excSync_D ),
.cw_epcSrc ( cw_epcSrc_D ),
.excRiFound ( excRiFound_D )
);
wire [31:0] epcNext_E;
wire [31:0] regData1_E;
wire [31:0] regData2_E;
wire [31:0] signImm_E;
wire [ 4:0] instrRs_E;
wire [ 4:0] instrRt_E;
wire [ 4:0] instrRd_E;
wire [ 4:0] instrSa_E;
wire [ 2:0] instrSel_E;
wire excRiFound_E;
wire irqRequest_E;
sm_register_cs #(32) r_epcNext_E (clk, rst_n, hz_flush_n_E, epcNext_D, epcNext_E);
sm_register_cs #(32) r_regData1_E(clk, rst_n, hz_flush_n_E, regData1_D, regData1_E);
sm_register_cs #(32) r_regData2_E(clk, rst_n, hz_flush_n_E, regData2_D, regData2_E);
sm_register_cs #(32) r_signImm_E (clk, rst_n, hz_flush_n_E, signImm_D, signImm_E);
sm_register_cs #( 5) r_instrRs_E (clk, rst_n, hz_flush_n_E, instrRs_D, instrRs_E);
sm_register_cs #( 5) r_instrRt_E (clk, rst_n, hz_flush_n_E, instrRt_D, instrRt_E);
sm_register_cs #( 5) r_instrRd_E (clk, rst_n, hz_flush_n_E, instrRd_D, instrRd_E);
sm_register_cs #( 5) r_instrSa_E (clk, rst_n, hz_flush_n_E, instrSa_D, instrSa_E);
sm_register_cs #( 3) r_instrSel_E(clk, rst_n, hz_flush_n_E, instrSel_D, instrSel_E);
sm_register_cs r_excRiFound_E (clk, rst_n, hz_flush_n_E, excRiFound_D, excRiFound_E);
sm_register_cs r_irqRequest_E (clk, rst_n, hz_flush_n_E, irqRequest_D, irqRequest_E);
wire cw_regWrite_E;
wire cw_regDst_E;
wire cw_aluSrc_E;
wire [2:0] cw_aluCtrl_E;
wire cw_memWrite_E;
wire cw_memToReg_E;
wire cw_cpzRegWrite_E;
wire cw_cpzExcEret_E;
wire cw_cpzToReg_E;
sm_register_cs r_cw_regWrite_E (clk, rst_n, hz_flush_n_E, cw_regWrite_D, cw_regWrite_E);
sm_register_cs r_cw_regDst_E (clk, rst_n, hz_flush_n_E, cw_regDst_D, cw_regDst_E);
sm_register_cs r_cw_aluSrc_E (clk, rst_n, hz_flush_n_E, cw_aluSrc_D, cw_aluSrc_E);
sm_register_cs #(3) r_cw_aluCtrl_E (clk, rst_n, hz_flush_n_E, cw_aluCtrl_D, cw_aluCtrl_E);
sm_register_cs r_cw_memWrite_E (clk, rst_n, hz_flush_n_E, cw_memWrite_D, cw_memWrite_E);
sm_register_cs r_cw_memToReg_E (clk, rst_n, hz_flush_n_E, cw_memToReg_D, cw_memToReg_E);
sm_register_cs r_cw_cpzRegWrite_E (clk, rst_n, hz_flush_n_E, cw_cpzRegWrite_D, cw_cpzRegWrite_E);
sm_register_cs r_cw_cpzExcEret_E (clk, rst_n, hz_flush_n_E, cw_cpzExcEret_D, cw_cpzExcEret_E);
sm_register_cs r_cw_cpzToReg_E (clk, rst_n, hz_flush_n_E, cw_cpzToReg_D, cw_cpzToReg_E);
wire [31:0] instr_E;
sm_register_cs #(32) r_instr_E (clk, rst_n, hz_flush_n_E, instr_D, instr_E);
wire [ 1:0] hz_forwardA_E;
wire [ 1:0] hz_forwardB_E;
wire hz_forwardEPC_E;
wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );
assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (
( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );
wire [31:0] aluSrcB_E = cw_aluSrc_E ? signImm_E : writeData_E;
wire aluZero_E;
wire [31:0] aluResult_E;
sm_alu alu
(
.srcA ( aluSrcA_E ),
.srcB ( aluSrcB_E ),
.oper ( cw_aluCtrl_E ),
.shift ( instrSa_E ),
.zero ( aluZero_E ),
.result ( aluResult_E )
);
wire [ 4:0] writeReg_E = cw_regDst_E ? instrRd_E : instrRt_E;
wire [31:0] epcNext_f_E = hz_forwardEPC_E ? pcBranch_D : epcNext_E;
wire [31:0] epcNext_M;
wire [ 4:0] writeReg_M;
wire [ 4:0] instrRd_M;
wire [ 2:0] instrSel_M;
wire excRiFound_M;
wire irqRequest_M;
sm_register #(32) r_epcNext_M (clk, epcNext_f_E, epcNext_M);
sm_register #(32) r_aluResult_M (clk, aluResult_E, aluResult_M);
sm_register #(32) r_writeData_M (clk, writeData_E, writeData_M);
sm_register #( 5) r_writeReg_M (clk, writeReg_E, writeReg_M);
sm_register #( 5) r_instrRd_M (clk, instrRd_E, instrRd_M);
sm_register #( 3) r_instrSel_M (clk, instrSel_E, instrSel_M);
sm_register r_excRiFound_M(clk, excRiFound_E, excRiFound_M);
sm_register_c r_irqRequest_M (clk, rst_n, irqRequest_E, irqRequest_M);
wire cw_regWrite_M;
wire cw_memWrite_M;
wire cw_memToReg_M;
wire cw_cpzRegWrite_M;
wire cw_cpzExcEret_M;
wire cw_cpzToReg_M;
sm_register_c r_cw_regWrite_M (clk, rst_n, cw_regWrite_E, cw_regWrite_M);
sm_register_c r_cw_memWrite_M (clk, rst_n, cw_memWrite_E, cw_memWrite_M);
sm_register_c r_cw_memToReg_M (clk, rst_n, cw_memToReg_E, cw_memToReg_M);
sm_register_c r_cw_cpzRegWrite_M (clk, rst_n, cw_cpzRegWrite_E, cw_cpzRegWrite_M);
sm_register_c r_cw_cpzExcEret_M (clk, rst_n, cw_cpzExcEret_E, cw_cpzExcEret_M);
sm_register_c r_cw_cpzToReg_M (clk, rst_n, cw_cpzToReg_E, cw_cpzToReg_M);
wire [31:0] instr_M;
sm_register #(32) r_instr_M (clk, instr_E, instr_M);
wire [31:0] readData_M = dmRData;
assign dmWe = cw_memWrite_M;
assign dmAddr = aluResult_M;
assign dmWData = writeData_M;
wire cp0_ExcSync_M;
wire cp0_ExcAsync_M;
wire cp0_ExcOv_M = 1'b0;
wire [31:0] cp0_Data_M;
wire cp0_TI_M;
wire [5:0] cp0_ExcIP_M = { cp0_TI_M, 5'b0 };
sm_cpz sm_cpz
(
.clk ( clk ),
.rst_n ( rst_n ),
.cp0_PC ( epcNext_M ),
.cp0_EPC ( cp0_EPC_M ),
.cp0_ExcHandler ( cp0_ExcHandler_M ),
.cp0_ExcAsyncReq ( cp0_ExcAsyncReq_M ),
.cp0_ExcAsyncAck ( irqRequest_M ),
.cp0_ExcAsync ( cp0_ExcAsync_M ),
.cp0_ExcSync ( cp0_ExcSync_M ),
.cp0_ExcEret ( cw_cpzExcEret_M ),
.cp0_regNum ( instrRd_M ),
.cp0_regSel ( instrSel_M ),
.cp0_regRD ( cp0_Data_M ),
.cp0_regWD ( writeData_M ),
.cp0_regWE ( cw_cpzRegWrite_M ),
.cp0_ExcIP ( cp0_ExcIP_M ),
.cp0_ExcRI ( excRiFound_M ),
.cp0_ExcOv ( cp0_ExcOv_M ),
.cp0_TI ( cp0_TI_M )
);
wire [31:0] aluResult_W;
wire [31:0] readData_W;
wire [31:0] cp0_Data_W;
sm_register #(32) r_aluResult_W (clk, aluResult_M, aluResult_W);
sm_register #(32) r_readData_W (clk, readData_M, readData_W);
sm_register #(32) r_cp0_Data_W (clk, cp0_Data_M, cp0_Data_W);
sm_register #(5) r_writeReg_W (clk, writeReg_M, writeReg_W);
wire cw_memToReg_W;
wire cw_cpzToReg_W;
sm_register_c r_cw_memToReg_W (clk, rst_n, cw_memToReg_M, cw_memToReg_W);
sm_register_c r_cw_cpzToReg_W (clk, rst_n, cw_cpzToReg_M, cw_cpzToReg_W);
sm_register_c r_cw_regWrite_W (clk, rst_n, cw_regWrite_M, cw_regWrite_W);
wire [31:0] instr_W;
sm_register #(32) r_instr_W (clk, instr_M, instr_W);
assign writeData_W = cw_memToReg_W ? readData_W :
cw_cpzToReg_W ? cp0_Data_W : aluResult_W;
sm_hazard_unit sm_hazard_unit
(
.instrRs_E ( instrRs_E ),
.instrRt_E ( instrRt_E ),
.writeReg_M ( writeReg_M ),
.writeReg_W ( writeReg_W ),
.cw_regWrite_M ( cw_regWrite_M ),
.cw_regWrite_W ( cw_regWrite_W ),
.hz_forwardA_E ( hz_forwardA_E ),
.hz_forwardB_E ( hz_forwardB_E ),
.instrRs_D ( instrRs_D ),
.instrRt_D ( instrRt_D ),
.writeReg_E ( writeReg_E ),
.cw_memToReg_E ( cw_memToReg_E ),
.hz_stall_n_F ( hz_stall_n_F ),
.hz_stall_n_D ( hz_stall_n_D ),
.hz_flush_n_E ( hz_flush_n_E ),
.cw_branch_D ( cw_branch_D ),
.cw_regWrite_E ( cw_regWrite_E ),
.cw_memToReg_M ( cw_memToReg_M ),
.hz_forwardA_D ( hz_forwardA_D ),
.hz_forwardB_D ( hz_forwardB_D ),
.cw_cpzToReg_E ( cw_cpzToReg_E ),
.cw_pcSrc_D ( cw_pcSrc_D ),
.irqRequest_E ( irqRequest_E ),
.irqRequest_M ( irqRequest_M ),
.hz_flush_n_D ( hz_flush_n_D ),
.cw_cpzExcEret_D ( cw_cpzExcEret_D ),
.excSync_D ( excSync_D ),
.hz_cancel_branch_F ( hz_cancel_branch_F ),
.hz_forwardEPC_E ( hz_forwardEPC_E ),
.hz_irq_disable_D ( hz_irq_disable_D ),
.hz_forwardEPC_F ( hz_forwardEPC_F ),
.cw_cpzRegWrite_E ( cw_cpzRegWrite_E ),
.cw_cpzRegWrite_M ( cw_cpzRegWrite_M ),
.instrRd_E ( instrRd_E ),
.instrRd_M ( instrRd_M ),
.instrSel_E ( instrSel_E ),
.instrSel_M ( instrSel_M )
);
endmodule | 3 |
3,145 | data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v | 102,870,077 | sm_pcpu.v | v | 513 | 121 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:10: Cannot find include file: sm_cpu.vh\n `include "sm_cpu.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.v\n data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq,data/full_repos/permissive/102870077/sm_cpu.vh.sv\n sm_cpu.vh\n sm_cpu.vh.v\n sm_cpu.vh.sv\n obj_dir/sm_cpu.vh\n obj_dir/sm_cpu.vh.v\n obj_dir/sm_cpu.vh.sv\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:11: Cannot find include file: sm_pcpu.vh\n `include "sm_pcpu.vh" \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: Define or directive not defined: \'`HZ_FW_EF\'\n wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] EPC_F = ( hz_forwardEPC_F == `HZ_FW_EF ) ? writeData_E :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:53: Define or directive not defined: \'`HZ_FW_MF\'\n ( hz_forwardEPC_F == `HZ_FW_MF ) ? writeData_M :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: Define or directive not defined: \'`PC_EXC\'\n wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :\n ^~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:56: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n wire [31:0] pcNew_F = cw_pcExc_D == `PC_EXC ? cp0_ExcHandler_M :\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:57: Define or directive not defined: \'`PC_ERET\'\n cw_pcExc_D == `PC_ERET ? EPC_F :\n ^~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: Define or directive not defined: \'`HZ_FW_WE\'\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:235: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [31:0] aluSrcA_E = ( hz_forwardA_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:236: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardA_E == `HZ_FW_ME ) ? aluResult_M : regData1_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: Define or directive not defined: \'`HZ_FW_WE\'\n assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:239: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign writeData_E = ( hz_forwardB_E == `HZ_FW_WE ) ? writeData_W : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:240: Define or directive not defined: \'`HZ_FW_ME\'\n ( hz_forwardB_E == `HZ_FW_ME ) ? aluResult_M : regData2_E );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:463: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardA_E = ( instrRs_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:464: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:465: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: Define or directive not defined: \'`HZ_FW_NONE\'\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:467: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign hz_forwardB_E = ( instrRt_E == 5\'b0 ) ? `HZ_FW_NONE : (\n ^\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:468: Define or directive not defined: \'`HZ_FW_ME\'\n ( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_WE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:469: Define or directive not defined: \'`HZ_FW_NONE\'\n ( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n instrRd_E == `CP0_REG_NUM_EPC && \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:501: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n instrRd_E == `CP0_REG_NUM_EPC && \n ^~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:502: Define or directive not defined: \'`HZ_FW_EF\'\n instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:504: Define or directive not defined: \'`CP0_REG_NUM_EPC\'\n instrRd_M == `CP0_REG_NUM_EPC && \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`CP0_REG_SEL_EPC\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_MF\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102870077/engine/static/school_mips/pipeline_irq/sm_pcpu.v:505: Define or directive not defined: \'`HZ_FW_NONE\'\n instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;\n ^~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n' | 902 | module | module sm_hazard_unit
(
input [ 4:0] instrRs_E,
input [ 4:0] instrRt_E,
input [ 4:0] writeReg_M,
input [ 4:0] writeReg_W,
input cw_regWrite_M,
input cw_regWrite_W,
output [ 1:0] hz_forwardA_E,
output [ 1:0] hz_forwardB_E,
input [ 4:0] instrRs_D,
input [ 4:0] instrRt_D,
input [ 4:0] writeReg_E,
input cw_memToReg_E,
output hz_stall_n_F,
output hz_stall_n_D,
output hz_flush_n_E,
input cw_branch_D,
input cw_regWrite_E,
input cw_memToReg_M,
output hz_forwardA_D,
output hz_forwardB_D,
input cw_cpzToReg_E,
input cw_pcSrc_D,
input irqRequest_E,
input irqRequest_M,
output hz_flush_n_D,
input cw_cpzExcEret_D,
input excSync_D,
output hz_cancel_branch_F,
output hz_forwardEPC_E,
output hz_irq_disable_D,
output [ 1:0] hz_forwardEPC_F,
input cw_cpzRegWrite_E,
input cw_cpzRegWrite_M,
input [ 4:0] instrRd_E,
input [ 4:0] instrRd_M,
input [ 2:0] instrSel_E,
input [ 2:0] instrSel_M
);
assign hz_forwardA_E = ( instrRs_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
assign hz_forwardB_E = ( instrRt_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
wire hz_mem_stall = ( cw_cpzToReg_E || cw_memToReg_E ) && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );
assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );
wire hz_branch_stall = cw_branch_D && (
( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
|| ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
);
wire hz_stall = hz_mem_stall || hz_branch_stall;
wire hz_branch_after_irq = cw_pcSrc_D & irqRequest_E;
assign hz_cancel_branch_F = hz_branch_after_irq;
assign hz_forwardEPC_E = hz_branch_after_irq;
assign hz_irq_disable_D = irqRequest_E | irqRequest_M;
assign hz_flush_n_D = ~((cw_pcSrc_D & ~irqRequest_E)
| cw_cpzExcEret_D
| excSync_D );
assign hz_forwardEPC_F = ( cw_cpzExcEret_D && cw_cpzRegWrite_E &&
instrRd_E == `CP0_REG_NUM_EPC &&
instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :
( cw_cpzExcEret_D && cw_cpzRegWrite_M &&
instrRd_M == `CP0_REG_NUM_EPC &&
instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;
assign hz_stall_n_F = ~hz_stall;
assign hz_stall_n_D = ~hz_stall;
assign hz_flush_n_E = ~hz_stall;
endmodule | module sm_hazard_unit
(
input [ 4:0] instrRs_E,
input [ 4:0] instrRt_E,
input [ 4:0] writeReg_M,
input [ 4:0] writeReg_W,
input cw_regWrite_M,
input cw_regWrite_W,
output [ 1:0] hz_forwardA_E,
output [ 1:0] hz_forwardB_E,
input [ 4:0] instrRs_D,
input [ 4:0] instrRt_D,
input [ 4:0] writeReg_E,
input cw_memToReg_E,
output hz_stall_n_F,
output hz_stall_n_D,
output hz_flush_n_E,
input cw_branch_D,
input cw_regWrite_E,
input cw_memToReg_M,
output hz_forwardA_D,
output hz_forwardB_D,
input cw_cpzToReg_E,
input cw_pcSrc_D,
input irqRequest_E,
input irqRequest_M,
output hz_flush_n_D,
input cw_cpzExcEret_D,
input excSync_D,
output hz_cancel_branch_F,
output hz_forwardEPC_E,
output hz_irq_disable_D,
output [ 1:0] hz_forwardEPC_F,
input cw_cpzRegWrite_E,
input cw_cpzRegWrite_M,
input [ 4:0] instrRd_E,
input [ 4:0] instrRd_M,
input [ 2:0] instrSel_E,
input [ 2:0] instrSel_M
); |
assign hz_forwardA_E = ( instrRs_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRs_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRs_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
assign hz_forwardB_E = ( instrRt_E == 5'b0 ) ? `HZ_FW_NONE : (
( instrRt_E == writeReg_M && cw_regWrite_M ) ? `HZ_FW_ME : (
( instrRt_E == writeReg_W && cw_regWrite_W ) ? `HZ_FW_WE : `HZ_FW_NONE ));
wire hz_mem_stall = ( cw_cpzToReg_E || cw_memToReg_E ) && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E );
assign hz_forwardA_D = ( instrRs_D != 5'b0 && instrRs_D == writeReg_M && cw_regWrite_M );
assign hz_forwardB_D = ( instrRt_D != 5'b0 && instrRt_D == writeReg_M && cw_regWrite_M );
wire hz_branch_stall = cw_branch_D && (
( cw_regWrite_E && ( instrRs_D == writeReg_E || instrRt_D == writeReg_E ))
|| ( cw_memToReg_M && ( instrRs_D == writeReg_M || instrRt_D == writeReg_M ))
);
wire hz_stall = hz_mem_stall || hz_branch_stall;
wire hz_branch_after_irq = cw_pcSrc_D & irqRequest_E;
assign hz_cancel_branch_F = hz_branch_after_irq;
assign hz_forwardEPC_E = hz_branch_after_irq;
assign hz_irq_disable_D = irqRequest_E | irqRequest_M;
assign hz_flush_n_D = ~((cw_pcSrc_D & ~irqRequest_E)
| cw_cpzExcEret_D
| excSync_D );
assign hz_forwardEPC_F = ( cw_cpzExcEret_D && cw_cpzRegWrite_E &&
instrRd_E == `CP0_REG_NUM_EPC &&
instrSel_E == `CP0_REG_SEL_EPC ) ? `HZ_FW_EF :
( cw_cpzExcEret_D && cw_cpzRegWrite_M &&
instrRd_M == `CP0_REG_NUM_EPC &&
instrSel_M == `CP0_REG_SEL_EPC ) ? `HZ_FW_MF : `HZ_FW_NONE;
assign hz_stall_n_F = ~hz_stall;
assign hz_stall_n_D = ~hz_stall;
assign hz_flush_n_E = ~hz_stall;
endmodule | 3 |
3,150 | data/full_repos/permissive/102955443/decodeASCII.v | 102,955,443 | decodeASCII.v | v | 6 | 33 | [] | [] | [] | [(1, 6)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/decodeASCII.v:5: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'code\' generates 5 bits.\n : ... In instance decodeASCII\n assign ascii = 8\'h41 + code; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 927 | module | module decodeASCII(code, ascii);
input [4:0] code;
output [7:0] ascii;
assign ascii = 8'h41 + code;
endmodule | module decodeASCII(code, ascii); |
input [4:0] code;
output [7:0] ascii;
assign ascii = 8'h41 + code;
endmodule | 23 |
3,151 | data/full_repos/permissive/102955443/encode.v | 102,955,443 | encode.v | v | 42 | 123 | [] | [] | [] | [(1, 22), (24, 41)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator SUB expects 7 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'ring_position\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'rotor\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator ADD expects 7 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'ring_position\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'rotor\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Error: data/full_repos/permissive/102955443/encode.v:38: Cannot find file containing module: \'rotorEncode\'\n rotorEncode #(.REVERSE(REVERSE)) rotEncode(.code(calculated_input),.val(outval),.rotor_type(rotor_type));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode.v\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode.sv\n rotorEncode\n rotorEncode.v\n rotorEncode.sv\n obj_dir/rotorEncode\n obj_dir/rotorEncode.v\n obj_dir/rotorEncode.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 928 | module | module calculate_val #(
parameter INPUT = 1
) (
input [4:0] value,
input [4:0] rotor,
output reg [4:0] out,
input [4:0] ring_position
);
reg signed [6:0] val = 7'b0000000;
always @*
begin
if (INPUT==1)
val = value - ring_position + rotor;
else
val = value + ring_position - rotor;
if (val < 0 ) val = val + 7'd26;
if (val > 7'd25) val = val - 7'd26;
out = val[4:0];
end
endmodule | module calculate_val #(
parameter INPUT = 1
) (
input [4:0] value,
input [4:0] rotor,
output reg [4:0] out,
input [4:0] ring_position
); |
reg signed [6:0] val = 7'b0000000;
always @*
begin
if (INPUT==1)
val = value - ring_position + rotor;
else
val = value + ring_position - rotor;
if (val < 0 ) val = val + 7'd26;
if (val > 7'd25) val = val - 7'd26;
out = val[4:0];
end
endmodule | 23 |
3,152 | data/full_repos/permissive/102955443/encode.v | 102,955,443 | encode.v | v | 42 | 123 | [] | [] | [] | [(1, 22), (24, 41)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator SUB expects 7 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'ring_position\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:14: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'rotor\' generates 5 bits.\n : ... In instance encode.coutput\n val = value - ring_position + rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator ADD expects 7 bits on the LHS, but LHS\'s VARREF \'value\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'ring_position\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/encode.v:16: Operator SUB expects 7 bits on the RHS, but RHS\'s VARREF \'rotor\' generates 5 bits.\n : ... In instance encode.coutput\n val = value + ring_position - rotor;\n ^\n%Error: data/full_repos/permissive/102955443/encode.v:38: Cannot find file containing module: \'rotorEncode\'\n rotorEncode #(.REVERSE(REVERSE)) rotEncode(.code(calculated_input),.val(outval),.rotor_type(rotor_type));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode.v\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/rotorEncode.sv\n rotorEncode\n rotorEncode.v\n rotorEncode.sv\n obj_dir/rotorEncode\n obj_dir/rotorEncode.v\n obj_dir/rotorEncode.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 928 | module | module encode #(
parameter REVERSE = 0
) (
input [4:0] inputValue,
input [4:0] rotor,
output [4:0] outputValue,
input [2:0] rotor_type,
input [4:0] ring_position
);
wire [4:0] calculated_input;
wire [4:0] outval;
calculate_val #(.INPUT(1)) cinput(.value(inputValue),.rotor(rotor),.out(calculated_input),.ring_position(ring_position));
rotorEncode #(.REVERSE(REVERSE)) rotEncode(.code(calculated_input),.val(outval),.rotor_type(rotor_type));
calculate_val #(.INPUT(0)) coutput(.value(outval),.rotor(rotor),.out(outputValue),.ring_position(ring_position));
endmodule | module encode #(
parameter REVERSE = 0
) (
input [4:0] inputValue,
input [4:0] rotor,
output [4:0] outputValue,
input [2:0] rotor_type,
input [4:0] ring_position
); |
wire [4:0] calculated_input;
wire [4:0] outval;
calculate_val #(.INPUT(1)) cinput(.value(inputValue),.rotor(rotor),.out(calculated_input),.ring_position(ring_position));
rotorEncode #(.REVERSE(REVERSE)) rotEncode(.code(calculated_input),.val(outval),.rotor_type(rotor_type));
calculate_val #(.INPUT(0)) coutput(.value(outval),.rotor(rotor),.out(outputValue),.ring_position(ring_position));
endmodule | 23 |
3,155 | data/full_repos/permissive/102955443/enigma_top_bi.v | 102,955,443 | enigma_top_bi.v | v | 70 | 141 | [] | [] | [] | null | line:37: before: ")" | null | 1: b"%Error: data/full_repos/permissive/102955443/enigma_top_bi.v:25: Cannot find file containing module: 'SB_PLL40_CORE'\n SB_PLL40_CORE #(\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/SB_PLL40_CORE\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/SB_PLL40_CORE.v\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/SB_PLL40_CORE.sv\n SB_PLL40_CORE\n SB_PLL40_CORE.v\n SB_PLL40_CORE.sv\n obj_dir/SB_PLL40_CORE\n obj_dir/SB_PLL40_CORE.v\n obj_dir/SB_PLL40_CORE.sv\n%Error: data/full_repos/permissive/102955443/enigma_top_bi.v:47: Cannot find file containing module: 'uart_rx'\n uart_rx #(.CLKS_PER_BIT(217)) UART_RX_Inst\n ^~~~~~~\n%Error: data/full_repos/permissive/102955443/enigma_top_bi.v:53: Cannot find file containing module: 'state_machine'\n state_machine st(.i_clock(w_clk),.i_ready(w_RX_DV),.i_inputData(w_RX_Byte),.o_ready(o_ready),.o_outputData(outputData),.o_valid(o_valid));\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102955443/enigma_top_bi.v:55: Cannot find file containing module: 'uart_tx'\n uart_tx #(.CLKS_PER_BIT(217)) UART_TX_Inst\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 931 | module | module enigma_top_bi
(input i_Clk,
input i_UART_RX,
output o_UART_TX,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
);
wire w_RX_DV;
wire [7:0] w_RX_Byte;
wire w_TX_Active, w_TX_Serial;
wire o_ready;
wire o_valid;
wire [7:0] outputData;
wire w_clk;
wire wegate;
wire PLL_BYPASS = 0;
wire PLL_RESETB = 1;
wire LOCK;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b0000),
.FDA_RELATIVE(4'b0000),
.DIVR(4'b0000),
.DIVF(7'b0000111),
.DIVQ(3'b101),
.FILTER_RANGE(3'b101),
) uut (
.REFERENCECLK (i_Clk),
.PLLOUTGLOBAL (w_clk),
.PLLOUTCORE (wegate),
.BYPASS (PLL_BYPASS),
.RESETB (PLL_RESETB),
.LOCK (LOCK)
);
uart_rx #(.CLKS_PER_BIT(217)) UART_RX_Inst
(.i_Clock(w_clk),
.i_Rx_Serial(i_UART_RX),
.o_Rx_DV(w_RX_DV),
.o_Rx_Byte(w_RX_Byte));
state_machine st(.i_clock(w_clk),.i_ready(w_RX_DV),.i_inputData(w_RX_Byte),.o_ready(o_ready),.o_outputData(outputData),.o_valid(o_valid));
uart_tx #(.CLKS_PER_BIT(217)) UART_TX_Inst
(.i_Clock(w_clk),
.i_Tx_DV(o_ready),
.i_Tx_Byte(outputData),
.o_Tx_Active(w_TX_Active),
.o_Tx_Serial(w_TX_Serial),
.o_Tx_Done());
assign o_UART_TX = w_TX_Active ? w_TX_Serial : 1'b1;
assign o_LED_1 = 1'b0;
assign o_LED_2 = 1'b0;
assign o_LED_3 = o_valid;
assign o_LED_4 = 1'b0;
endmodule | module enigma_top_bi
(input i_Clk,
input i_UART_RX,
output o_UART_TX,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
); |
wire w_RX_DV;
wire [7:0] w_RX_Byte;
wire w_TX_Active, w_TX_Serial;
wire o_ready;
wire o_valid;
wire [7:0] outputData;
wire w_clk;
wire wegate;
wire PLL_BYPASS = 0;
wire PLL_RESETB = 1;
wire LOCK;
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT("GENCLK"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b0000),
.FDA_RELATIVE(4'b0000),
.DIVR(4'b0000),
.DIVF(7'b0000111),
.DIVQ(3'b101),
.FILTER_RANGE(3'b101),
) uut (
.REFERENCECLK (i_Clk),
.PLLOUTGLOBAL (w_clk),
.PLLOUTCORE (wegate),
.BYPASS (PLL_BYPASS),
.RESETB (PLL_RESETB),
.LOCK (LOCK)
);
uart_rx #(.CLKS_PER_BIT(217)) UART_RX_Inst
(.i_Clock(w_clk),
.i_Rx_Serial(i_UART_RX),
.o_Rx_DV(w_RX_DV),
.o_Rx_Byte(w_RX_Byte));
state_machine st(.i_clock(w_clk),.i_ready(w_RX_DV),.i_inputData(w_RX_Byte),.o_ready(o_ready),.o_outputData(outputData),.o_valid(o_valid));
uart_tx #(.CLKS_PER_BIT(217)) UART_TX_Inst
(.i_Clock(w_clk),
.i_Tx_DV(o_ready),
.i_Tx_Byte(outputData),
.o_Tx_Active(w_TX_Active),
.o_Tx_Serial(w_TX_Serial),
.o_Tx_Done());
assign o_UART_TX = w_TX_Active ? w_TX_Serial : 1'b1;
assign o_LED_1 = 1'b0;
assign o_LED_2 = 1'b0;
assign o_LED_3 = o_valid;
assign o_LED_4 = 1'b0;
endmodule | 23 |
3,157 | data/full_repos/permissive/102955443/reflectorEncode.v | 102,955,443 | reflectorEncode.v | v | 74 | 52 | [] | [] | [] | [(1, 73)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:12: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 0 : val = "Y" - 8\'h41;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:13: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 1 : val = "R" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:14: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 2 : val = "U" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:15: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 3 : val = "H" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:16: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 4 : val = "Q" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 5 : val = "S" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 6 : val = "L" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:19: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 7 : val = "D" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:20: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 8 : val = "P" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:21: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 9 : val = "X" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:22: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 10: val = "N" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:23: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 11: val = "G" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:24: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 12: val = "O" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:25: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 13: val = "K" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:26: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 14: val = "M" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:27: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 15: val = "I" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:28: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 16: val = "E" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:29: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 17: val = "B" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:30: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 18: val = "F" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 19: val = "Z" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:32: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 20: val = "C" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:33: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 21: val = "W" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:34: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 22: val = "V" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:35: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 23: val = "J" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:36: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 24: val = "A" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 25: val = "T" - 8\'h41; \n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:44: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 0 : val = "F" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:45: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 1 : val = "V" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:46: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 2 : val = "P" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:47: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 3 : val = "J" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:48: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 4 : val = "I" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:49: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 5 : val = "A" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:50: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 6 : val = "O" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:51: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 7 : val = "Y" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:52: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 8 : val = "E" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:53: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 9 : val = "D" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:54: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 10: val = "R" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:55: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 11: val = "Z" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:56: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 12: val = "X" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:57: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 13: val = "W" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:58: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 14: val = "G" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:59: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 15: val = "C" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:60: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 16: val = "T" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:61: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 17: val = "K" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:62: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 18: val = "U" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:63: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 19: val = "Q" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:64: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 20: val = "S" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:65: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 21: val = "B" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:66: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 22: val = "N" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:67: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 23: val = "M" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:68: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 24: val = "H" - 8\'h41;\n ^\n%Warning-WIDTH: data/full_repos/permissive/102955443/reflectorEncode.v:69: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n : ... In instance reflectorEncode\n 25: val = "L" - 8\'h41; \n ^\n%Error: Exiting due to 52 warning(s)\n' | 934 | module | module reflectorEncode (code, val, reflector_type);
input [4:0] code;
output reg [4:0] val;
input reflector_type;
always @*
begin
if (reflector_type == 1'b0)
begin
case (code)
0 : val = "Y" - 8'h41;
1 : val = "R" - 8'h41;
2 : val = "U" - 8'h41;
3 : val = "H" - 8'h41;
4 : val = "Q" - 8'h41;
5 : val = "S" - 8'h41;
6 : val = "L" - 8'h41;
7 : val = "D" - 8'h41;
8 : val = "P" - 8'h41;
9 : val = "X" - 8'h41;
10: val = "N" - 8'h41;
11: val = "G" - 8'h41;
12: val = "O" - 8'h41;
13: val = "K" - 8'h41;
14: val = "M" - 8'h41;
15: val = "I" - 8'h41;
16: val = "E" - 8'h41;
17: val = "B" - 8'h41;
18: val = "F" - 8'h41;
19: val = "Z" - 8'h41;
20: val = "C" - 8'h41;
21: val = "W" - 8'h41;
22: val = "V" - 8'h41;
23: val = "J" - 8'h41;
24: val = "A" - 8'h41;
25: val = "T" - 8'h41;
endcase
end
else
begin
case (code)
0 : val = "F" - 8'h41;
1 : val = "V" - 8'h41;
2 : val = "P" - 8'h41;
3 : val = "J" - 8'h41;
4 : val = "I" - 8'h41;
5 : val = "A" - 8'h41;
6 : val = "O" - 8'h41;
7 : val = "Y" - 8'h41;
8 : val = "E" - 8'h41;
9 : val = "D" - 8'h41;
10: val = "R" - 8'h41;
11: val = "Z" - 8'h41;
12: val = "X" - 8'h41;
13: val = "W" - 8'h41;
14: val = "G" - 8'h41;
15: val = "C" - 8'h41;
16: val = "T" - 8'h41;
17: val = "K" - 8'h41;
18: val = "U" - 8'h41;
19: val = "Q" - 8'h41;
20: val = "S" - 8'h41;
21: val = "B" - 8'h41;
22: val = "N" - 8'h41;
23: val = "M" - 8'h41;
24: val = "H" - 8'h41;
25: val = "L" - 8'h41;
endcase
end
end
endmodule | module reflectorEncode (code, val, reflector_type); |
input [4:0] code;
output reg [4:0] val;
input reflector_type;
always @*
begin
if (reflector_type == 1'b0)
begin
case (code)
0 : val = "Y" - 8'h41;
1 : val = "R" - 8'h41;
2 : val = "U" - 8'h41;
3 : val = "H" - 8'h41;
4 : val = "Q" - 8'h41;
5 : val = "S" - 8'h41;
6 : val = "L" - 8'h41;
7 : val = "D" - 8'h41;
8 : val = "P" - 8'h41;
9 : val = "X" - 8'h41;
10: val = "N" - 8'h41;
11: val = "G" - 8'h41;
12: val = "O" - 8'h41;
13: val = "K" - 8'h41;
14: val = "M" - 8'h41;
15: val = "I" - 8'h41;
16: val = "E" - 8'h41;
17: val = "B" - 8'h41;
18: val = "F" - 8'h41;
19: val = "Z" - 8'h41;
20: val = "C" - 8'h41;
21: val = "W" - 8'h41;
22: val = "V" - 8'h41;
23: val = "J" - 8'h41;
24: val = "A" - 8'h41;
25: val = "T" - 8'h41;
endcase
end
else
begin
case (code)
0 : val = "F" - 8'h41;
1 : val = "V" - 8'h41;
2 : val = "P" - 8'h41;
3 : val = "J" - 8'h41;
4 : val = "I" - 8'h41;
5 : val = "A" - 8'h41;
6 : val = "O" - 8'h41;
7 : val = "Y" - 8'h41;
8 : val = "E" - 8'h41;
9 : val = "D" - 8'h41;
10: val = "R" - 8'h41;
11: val = "Z" - 8'h41;
12: val = "X" - 8'h41;
13: val = "W" - 8'h41;
14: val = "G" - 8'h41;
15: val = "C" - 8'h41;
16: val = "T" - 8'h41;
17: val = "K" - 8'h41;
18: val = "U" - 8'h41;
19: val = "Q" - 8'h41;
20: val = "S" - 8'h41;
21: val = "B" - 8'h41;
22: val = "N" - 8'h41;
23: val = "M" - 8'h41;
24: val = "H" - 8'h41;
25: val = "L" - 8'h41;
endcase
end
end
endmodule | 23 |
3,159 | data/full_repos/permissive/102955443/rotorEncode.v | 102,955,443 | rotorEncode.v | v | 17 | 69 | [] | [] | [] | [(1, 16)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/102955443/rotorEncode.v:11: Operator NEQ expects 80 bits on the RHS, but RHS\'s CONST \'?1?h0\' generates 1 bits.\n : ... In instance rotorEncode\n if (MEM_INIT_FILE != "")\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/102955443/rotorEncode.v:15: Operator ADD expects 32 or 8 bits on the RHS, but RHS\'s VARREF \'code\' generates 5 bits.\n : ... In instance rotorEncode\n val = rotor_data[((REVERSE) ? 208 : 0) + rotor_type*26 + code];\n ^\n%Error: Exiting due to 2 warning(s)\n' | 936 | module | module rotorEncode #(parameter REVERSE = 0) (code, rotor_type, val);
input [4:0] code;
output reg [4:0] val;
input [2:0] rotor_type;
parameter MEM_INIT_FILE = "rotors.mem";
reg [4:0] rotor_data[0:415];
initial
if (MEM_INIT_FILE != "")
$readmemh(MEM_INIT_FILE, rotor_data);
always @*
val = rotor_data[((REVERSE) ? 208 : 0) + rotor_type*26 + code];
endmodule | module rotorEncode #(parameter REVERSE = 0) (code, rotor_type, val); |
input [4:0] code;
output reg [4:0] val;
input [2:0] rotor_type;
parameter MEM_INIT_FILE = "rotors.mem";
reg [4:0] rotor_data[0:415];
initial
if (MEM_INIT_FILE != "")
$readmemh(MEM_INIT_FILE, rotor_data);
always @*
val = rotor_data[((REVERSE) ? 208 : 0) + rotor_type*26 + code];
endmodule | 23 |
3,160 | data/full_repos/permissive/102955443/state_machine.v | 102,955,443 | state_machine.v | v | 137 | 153 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/102955443/state_machine.v:51: Cannot find file containing module: 'encodeASCII'\n encodeASCII encode(.ascii(i_inputData), .code(inputCode), .valid(valid));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/encodeASCII\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/encodeASCII.v\n data/full_repos/permissive/102955443,data/full_repos/permissive/102955443/encodeASCII.sv\n encodeASCII\n encodeASCII.v\n encodeASCII.sv\n obj_dir/encodeASCII\n obj_dir/encodeASCII.v\n obj_dir/encodeASCII.sv\n%Error: data/full_repos/permissive/102955443/state_machine.v:53: Cannot find file containing module: 'rotor'\n rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),.reset(reset),.rotate(rotate),\n ^~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:58: Cannot find file containing module: 'plugboardEncode'\n plugboardEncode plugboard(.code(inputCode),.val(value0)); \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:59: Cannot find file containing module: 'encode'\n encode #(.REVERSE(0)) rot3Encode(.inputValue(value0),.rotor(rotor3),.outputValue(value1),.rotor_type(rotor_type_3),.ring_position(ring_position_3));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:60: Cannot find file containing module: 'encode'\n encode #(.REVERSE(0)) rot2Encode(.inputValue(value1),.rotor(rotor2),.outputValue(value2),.rotor_type(rotor_type_2),.ring_position(ring_position_2));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:61: Cannot find file containing module: 'encode'\n encode #(.REVERSE(0)) rot1Encode(.inputValue(value2),.rotor(rotor1),.outputValue(value3),.rotor_type(rotor_type_1),.ring_position(ring_position_1));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:62: Cannot find file containing module: 'reflectorEncode'\n reflectorEncode reflector(.code(value3),.val(value4),.reflector_type(reflector_type));\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:63: Cannot find file containing module: 'encode'\n encode #(.REVERSE(1)) rot1EncodeRev(.inputValue(value4),.rotor(rotor1),.outputValue(value5),.rotor_type(rotor_type_1),.ring_position(ring_position_1));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:64: Cannot find file containing module: 'encode'\n encode #(.REVERSE(1)) rot2EncodeRev(.inputValue(value5),.rotor(rotor2),.outputValue(value6),.rotor_type(rotor_type_2),.ring_position(ring_position_2));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:65: Cannot find file containing module: 'encode'\n encode #(.REVERSE(1)) rot3EncodeRev(.inputValue(value6),.rotor(rotor3),.outputValue(value7),.rotor_type(rotor_type_3),.ring_position(ring_position_3));\n ^~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:66: Cannot find file containing module: 'plugboardEncode'\n plugboardEncode plugboard2(.code(value7),.val(value8)); \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/102955443/state_machine.v:68: Cannot find file containing module: 'decodeASCII'\n decodeASCII decode(.code(value8), .ascii(final_ascii));\n ^~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n" | 937 | module | module state_machine(
input i_clock,
input i_ready,
input [7:0] i_inputData,
output reg o_ready,
output reg [7:0] o_outputData,
output reg o_valid
);
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [2:0] rotor_type_1 = 3'b000;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
reg reset = 1'b1;
reg rotate = 1'b0;
wire [4:0] value0;
wire [4:0] value1;
wire [4:0] value2;
wire [4:0] value3;
wire [4:0] value4;
wire [4:0] value5;
wire [4:0] value6;
wire [4:0] value7;
wire [4:0] value8;
parameter STATE_RESET = 2'b00;
parameter STATE_IDLE = 2'b01;
parameter STATE_ENCODE = 2'b10;
parameter STATE_CHECKKEY= 2'b11;
reg [1:0] state = STATE_RESET;
wire [4:0] inputCode;
wire valid;
wire [7:0] final_ascii;
encodeASCII encode(.ascii(i_inputData), .code(inputCode), .valid(valid));
rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),.reset(reset),.rotate(rotate),
.rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
);
plugboardEncode plugboard(.code(inputCode),.val(value0));
encode #(.REVERSE(0)) rot3Encode(.inputValue(value0),.rotor(rotor3),.outputValue(value1),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
encode #(.REVERSE(0)) rot2Encode(.inputValue(value1),.rotor(rotor2),.outputValue(value2),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(0)) rot1Encode(.inputValue(value2),.rotor(rotor1),.outputValue(value3),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
reflectorEncode reflector(.code(value3),.val(value4),.reflector_type(reflector_type));
encode #(.REVERSE(1)) rot1EncodeRev(.inputValue(value4),.rotor(rotor1),.outputValue(value5),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
encode #(.REVERSE(1)) rot2EncodeRev(.inputValue(value5),.rotor(rotor2),.outputValue(value6),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(1)) rot3EncodeRev(.inputValue(value6),.rotor(rotor3),.outputValue(value7),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
plugboardEncode plugboard2(.code(value7),.val(value8));
decodeASCII decode(.code(value8), .ascii(final_ascii));
always @(posedge i_clock)
begin
case (state)
STATE_RESET :
begin
reset <= 1'b0;
state <= STATE_IDLE;
o_ready <= 1'b0;
o_outputData <= 8'b00000000;
o_valid <= 1'b0;
rotate <= 1'b1;
end
STATE_IDLE :
begin
o_ready <= 1'b0;
state <= i_ready ? STATE_CHECKKEY : STATE_IDLE;
o_valid <= valid;
rotate <= 1'b0;
end
STATE_CHECKKEY :
begin
o_ready <= 1'b0;
rotate <= 1'b0;
if (valid)
begin
state <= STATE_ENCODE;
end
else
begin
case(i_inputData)
8'd27:
begin
reset <= 1'b1;
state <= STATE_RESET;
o_ready <= 1'b1;
o_outputData <= 8'd10;
end
8'd13:
begin
state <= STATE_IDLE;
o_ready <= 1'b1;
o_outputData <= 8'd13;
end
default:
state <= STATE_IDLE;
endcase
end
o_valid <= valid;
end
STATE_ENCODE :
begin
rotate <= 1'b1;
o_ready <= 1'b1;
o_outputData <= final_ascii;
state <= STATE_IDLE;
end
endcase
end
endmodule | module state_machine(
input i_clock,
input i_ready,
input [7:0] i_inputData,
output reg o_ready,
output reg [7:0] o_outputData,
output reg o_valid
); |
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [2:0] rotor_type_1 = 3'b000;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
reg reset = 1'b1;
reg rotate = 1'b0;
wire [4:0] value0;
wire [4:0] value1;
wire [4:0] value2;
wire [4:0] value3;
wire [4:0] value4;
wire [4:0] value5;
wire [4:0] value6;
wire [4:0] value7;
wire [4:0] value8;
parameter STATE_RESET = 2'b00;
parameter STATE_IDLE = 2'b01;
parameter STATE_ENCODE = 2'b10;
parameter STATE_CHECKKEY= 2'b11;
reg [1:0] state = STATE_RESET;
wire [4:0] inputCode;
wire valid;
wire [7:0] final_ascii;
encodeASCII encode(.ascii(i_inputData), .code(inputCode), .valid(valid));
rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),.reset(reset),.rotate(rotate),
.rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
);
plugboardEncode plugboard(.code(inputCode),.val(value0));
encode #(.REVERSE(0)) rot3Encode(.inputValue(value0),.rotor(rotor3),.outputValue(value1),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
encode #(.REVERSE(0)) rot2Encode(.inputValue(value1),.rotor(rotor2),.outputValue(value2),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(0)) rot1Encode(.inputValue(value2),.rotor(rotor1),.outputValue(value3),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
reflectorEncode reflector(.code(value3),.val(value4),.reflector_type(reflector_type));
encode #(.REVERSE(1)) rot1EncodeRev(.inputValue(value4),.rotor(rotor1),.outputValue(value5),.rotor_type(rotor_type_1),.ring_position(ring_position_1));
encode #(.REVERSE(1)) rot2EncodeRev(.inputValue(value5),.rotor(rotor2),.outputValue(value6),.rotor_type(rotor_type_2),.ring_position(ring_position_2));
encode #(.REVERSE(1)) rot3EncodeRev(.inputValue(value6),.rotor(rotor3),.outputValue(value7),.rotor_type(rotor_type_3),.ring_position(ring_position_3));
plugboardEncode plugboard2(.code(value7),.val(value8));
decodeASCII decode(.code(value8), .ascii(final_ascii));
always @(posedge i_clock)
begin
case (state)
STATE_RESET :
begin
reset <= 1'b0;
state <= STATE_IDLE;
o_ready <= 1'b0;
o_outputData <= 8'b00000000;
o_valid <= 1'b0;
rotate <= 1'b1;
end
STATE_IDLE :
begin
o_ready <= 1'b0;
state <= i_ready ? STATE_CHECKKEY : STATE_IDLE;
o_valid <= valid;
rotate <= 1'b0;
end
STATE_CHECKKEY :
begin
o_ready <= 1'b0;
rotate <= 1'b0;
if (valid)
begin
state <= STATE_ENCODE;
end
else
begin
case(i_inputData)
8'd27:
begin
reset <= 1'b1;
state <= STATE_RESET;
o_ready <= 1'b1;
o_outputData <= 8'd10;
end
8'd13:
begin
state <= STATE_IDLE;
o_ready <= 1'b1;
o_outputData <= 8'd13;
end
default:
state <= STATE_IDLE;
endcase
end
o_valid <= valid;
end
STATE_ENCODE :
begin
rotate <= 1'b1;
o_ready <= 1'b1;
o_outputData <= final_ascii;
state <= STATE_IDLE;
end
endcase
end
endmodule | 23 |
3,161 | data/full_repos/permissive/102955443/test.v | 102,955,443 | test.v | v | 34 | 124 | [] | [] | [] | null | line:32: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:12: Unsupported: Ignoring delay on this delayed statement.\n #(5) r_Clock <= !r_Clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102955443/test.v:21: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("enigma.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102955443/test.v:22: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:26: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:28: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #260\n ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 938 | module | module test();
reg i_ready = 0;
reg [7:0] inputData;
reg r_Clock = 0;
wire o_ready;
wire [7:0] outputData;
integer i;
state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
always
#(5) r_Clock <= !r_Clock;
always @(posedge o_ready)
begin
$display("data is [%c]",outputData);
end
initial
begin
$dumpfile("enigma.vcd");
$dumpvars(0,test);
inputData = "A";
for (i = 0; i < 20; i = i + 1)
begin
#10
i_ready = 1;
#30
i_ready = 0;
end
#260
$finish;
end
endmodule | module test(); |
reg i_ready = 0;
reg [7:0] inputData;
reg r_Clock = 0;
wire o_ready;
wire [7:0] outputData;
integer i;
state_machine st(.i_clock(r_Clock),.i_ready(i_ready),.i_inputData(inputData),.o_ready(o_ready),.o_outputData(outputData));
always
#(5) r_Clock <= !r_Clock;
always @(posedge o_ready)
begin
$display("data is [%c]",outputData);
end
initial
begin
$dumpfile("enigma.vcd");
$dumpvars(0,test);
inputData = "A";
for (i = 0; i < 20; i = i + 1)
begin
#10
i_ready = 1;
#30
i_ready = 0;
end
#260
$finish;
end
endmodule | 23 |
3,162 | data/full_repos/permissive/102955443/testrotor.v | 102,955,443 | testrotor.v | v | 58 | 96 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(5) i_clock <= !i_clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/102955443/testrotor.v:36: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("testrotor.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/102955443/testrotor.v:37: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,testrotor);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:49: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/102955443/testrotor.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 939 | module | module testrotor();
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
reg i_clock = 0;
reg reset;
reg rotate = 0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
integer i;
rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),
.reset(reset),.rotate(rotate),
.rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
);
always
#(5) i_clock <= !i_clock;
initial
begin
$dumpfile("testrotor.vcd");
$dumpvars(0,testrotor);
#5
reset = 1;
#10
reset = 0;
for (i = 0; i < 128; i = i + 1)
begin
#10
rotate = 1;
#10
rotate = 0;
#20
$display("Rotors [%c] [%c] [%c]",rotor1+65,rotor2+65,rotor3+65);
end
#10
$finish;
end
endmodule | module testrotor(); |
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
reg i_clock = 0;
reg reset;
reg rotate = 0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
integer i;
rotor rotorcontrol(.clock(i_clock),.rotor1(rotor1),.rotor2(rotor2),.rotor3(rotor3),
.reset(reset),.rotate(rotate),
.rotor_type_2(rotor_type_2),.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),.rotor_start_2(rotor_start_2),.rotor_start_3(rotor_start_3)
);
always
#(5) i_clock <= !i_clock;
initial
begin
$dumpfile("testrotor.vcd");
$dumpvars(0,testrotor);
#5
reset = 1;
#10
reset = 0;
for (i = 0; i < 128; i = i + 1)
begin
#10
rotate = 1;
#10
rotate = 0;
#20
$display("Rotors [%c] [%c] [%c]",rotor1+65,rotor2+65,rotor3+65);
end
#10
$finish;
end
endmodule | 23 |
3,165 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/ddr3_eim_cs1.v | 10,301,314 | ddr3_eim_cs1.v | v | 202 | 103 | [] | [] | [] | [(3, 201)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/ddr3_eim_cs1.v:44: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n : ... In instance ddr3_eim_cs1\n assign status = {readcount,\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 943 | module | module ddr3_eim_cs1(
input wire clk,
input wire [63:0] ctl,
input wire ctl_stb,
output wire [63:0] burst_rd,
input wire rd_stb,
output wire [63:0] status,
output wire [2:0] ddr3_rd_cmd,
output wire [5:0] ddr3_rd_bl,
output wire [29:0] ddr3_rd_adr,
output wire ddr3_rd_cmd_en,
input wire ddr3_rd_cmd_empty,
input wire ddr3_rd_cmd_full,
input wire [31:0] ddr3_rd_data,
input wire [6:0] ddr3_rd_count,
input wire ddr3_rd_empty,
input wire ddr3_rd_full,
output reg ddr3_rd_en,
input wire reset
);
reg [29:0] cmd_adr;
reg [4:0] num_pkts;
reg [4:0] outstanding;
reg [63:0] rd_cache;
reg cmd_go;
reg reset_errors;
reg cmd_err;
reg [7:0] readcount;
assign burst_rd[63:0] = rd_cache[63:0];
assign status = {readcount,
3'b0,cmd_err,
ddr3_rd_cmd_empty, ddr3_rd_cmd_full, ddr3_rd_empty, ddr3_rd_full,
1'b0, ddr3_rd_count[6:0]};
always @(posedge clk) begin
if( ctl_stb ) begin
readcount <= 8'b0;
end else if( rd_stb ) begin
readcount <= readcount + 8'b1;
end else begin
readcount <= readcount;
end
end
always @(posedge clk) begin
if( ctl_stb ) begin
cmd_adr <= ctl[29:0];
num_pkts <= ctl[36:32];
end else begin
cmd_adr <= cmd_adr;
num_pkts <= num_pkts;
end
cmd_go <= ctl_stb && (ctl[36:32] != 5'b0);
end
assign ddr3_rd_cmd = 3'b001;
assign ddr3_rd_adr = {cmd_adr[29:2],2'b00};
assign ddr3_rd_bl[5:0] = {num_pkts[4:0],1'b0} - 6'b1;
assign ddr3_rd_cmd_en = cmd_go;
parameter READ_IDLE = 6'b1 << 0;
parameter READ_PENDING = 6'b1 << 1;
parameter READ_FETCH = 6'b1 << 2;
parameter READ_UPDATE_LSB = 6'b1 << 3;
parameter READ_UPDATE_MSB = 6'b1 << 4;
parameter READ_WAIT = 6'b1 << 5;
parameter READ_nSTATES = 6;
reg [(READ_nSTATES - 1):0] cstate;
reg [(READ_nSTATES - 1):0] nstate;
always @(posedge clk) begin
cstate <= nstate;
end
always @(*) begin
case(cstate)
READ_IDLE: begin
if( cmd_go ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_IDLE;
end
end
READ_PENDING: begin
if( outstanding != 5'b0 ) begin
if( ddr3_rd_count[6:0] < 7'b10 ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_FETCH;
end
end else begin
nstate <= READ_IDLE;
end
end
READ_FETCH: begin
nstate <= READ_UPDATE_LSB;
end
READ_UPDATE_LSB: begin
nstate <= READ_UPDATE_MSB;
end
READ_UPDATE_MSB: begin
nstate <= READ_WAIT;
end
READ_WAIT: begin
if( rd_stb ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_WAIT;
end
end
default: begin
nstate <= READ_IDLE;
end
endcase
end
always @(posedge clk) begin
case(cstate)
READ_IDLE: begin
outstanding[4:0] <= num_pkts[4:0];
rd_cache <= rd_cache;
if( ddr3_rd_count[6:0] > 7'b0 ) begin
ddr3_rd_en <= 1'b1;
end else begin
ddr3_rd_en <= 1'b0;
end
end
READ_PENDING: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
READ_FETCH: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_LSB: begin
outstanding <= outstanding;
rd_cache[63:0] <= {rd_cache[63:32],ddr3_rd_data[31:0]};
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_MSB: begin
outstanding <= outstanding - 5'b1;
rd_cache[63:0] <= {ddr3_rd_data[31:0],rd_cache[31:0]};
ddr3_rd_en <= 1'b0;
end
READ_WAIT: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
default: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
endcase
end
always @(posedge clk) begin
reset_errors <= ctl[63];
if( reset_errors ) begin
cmd_err <= 1'b0;
end else begin
if( cmd_go && ddr3_rd_cmd_full ) begin
cmd_err <= 1'b1;
end else begin
cmd_err <= cmd_err;
end
end
end
endmodule | module ddr3_eim_cs1(
input wire clk,
input wire [63:0] ctl,
input wire ctl_stb,
output wire [63:0] burst_rd,
input wire rd_stb,
output wire [63:0] status,
output wire [2:0] ddr3_rd_cmd,
output wire [5:0] ddr3_rd_bl,
output wire [29:0] ddr3_rd_adr,
output wire ddr3_rd_cmd_en,
input wire ddr3_rd_cmd_empty,
input wire ddr3_rd_cmd_full,
input wire [31:0] ddr3_rd_data,
input wire [6:0] ddr3_rd_count,
input wire ddr3_rd_empty,
input wire ddr3_rd_full,
output reg ddr3_rd_en,
input wire reset
); |
reg [29:0] cmd_adr;
reg [4:0] num_pkts;
reg [4:0] outstanding;
reg [63:0] rd_cache;
reg cmd_go;
reg reset_errors;
reg cmd_err;
reg [7:0] readcount;
assign burst_rd[63:0] = rd_cache[63:0];
assign status = {readcount,
3'b0,cmd_err,
ddr3_rd_cmd_empty, ddr3_rd_cmd_full, ddr3_rd_empty, ddr3_rd_full,
1'b0, ddr3_rd_count[6:0]};
always @(posedge clk) begin
if( ctl_stb ) begin
readcount <= 8'b0;
end else if( rd_stb ) begin
readcount <= readcount + 8'b1;
end else begin
readcount <= readcount;
end
end
always @(posedge clk) begin
if( ctl_stb ) begin
cmd_adr <= ctl[29:0];
num_pkts <= ctl[36:32];
end else begin
cmd_adr <= cmd_adr;
num_pkts <= num_pkts;
end
cmd_go <= ctl_stb && (ctl[36:32] != 5'b0);
end
assign ddr3_rd_cmd = 3'b001;
assign ddr3_rd_adr = {cmd_adr[29:2],2'b00};
assign ddr3_rd_bl[5:0] = {num_pkts[4:0],1'b0} - 6'b1;
assign ddr3_rd_cmd_en = cmd_go;
parameter READ_IDLE = 6'b1 << 0;
parameter READ_PENDING = 6'b1 << 1;
parameter READ_FETCH = 6'b1 << 2;
parameter READ_UPDATE_LSB = 6'b1 << 3;
parameter READ_UPDATE_MSB = 6'b1 << 4;
parameter READ_WAIT = 6'b1 << 5;
parameter READ_nSTATES = 6;
reg [(READ_nSTATES - 1):0] cstate;
reg [(READ_nSTATES - 1):0] nstate;
always @(posedge clk) begin
cstate <= nstate;
end
always @(*) begin
case(cstate)
READ_IDLE: begin
if( cmd_go ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_IDLE;
end
end
READ_PENDING: begin
if( outstanding != 5'b0 ) begin
if( ddr3_rd_count[6:0] < 7'b10 ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_FETCH;
end
end else begin
nstate <= READ_IDLE;
end
end
READ_FETCH: begin
nstate <= READ_UPDATE_LSB;
end
READ_UPDATE_LSB: begin
nstate <= READ_UPDATE_MSB;
end
READ_UPDATE_MSB: begin
nstate <= READ_WAIT;
end
READ_WAIT: begin
if( rd_stb ) begin
nstate <= READ_PENDING;
end else begin
nstate <= READ_WAIT;
end
end
default: begin
nstate <= READ_IDLE;
end
endcase
end
always @(posedge clk) begin
case(cstate)
READ_IDLE: begin
outstanding[4:0] <= num_pkts[4:0];
rd_cache <= rd_cache;
if( ddr3_rd_count[6:0] > 7'b0 ) begin
ddr3_rd_en <= 1'b1;
end else begin
ddr3_rd_en <= 1'b0;
end
end
READ_PENDING: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
READ_FETCH: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_LSB: begin
outstanding <= outstanding;
rd_cache[63:0] <= {rd_cache[63:32],ddr3_rd_data[31:0]};
ddr3_rd_en <= 1'b1;
end
READ_UPDATE_MSB: begin
outstanding <= outstanding - 5'b1;
rd_cache[63:0] <= {ddr3_rd_data[31:0],rd_cache[31:0]};
ddr3_rd_en <= 1'b0;
end
READ_WAIT: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
default: begin
outstanding <= outstanding;
rd_cache <= rd_cache;
ddr3_rd_en <= 1'b0;
end
endcase
end
always @(posedge clk) begin
reset_errors <= ctl[63];
if( reset_errors ) begin
cmd_err <= 1'b0;
end else begin
if( cmd_go && ddr3_rd_cmd_full ) begin
cmd_err <= 1'b1;
end else begin
cmd_err <= cmd_err;
end
end
end
endmodule | 4 |
3,166 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log.v | 10,301,314 | nand_log.v | v | 385 | 104 | [] | ['apache license'] | [] | [(21, 383)] | null | null | 1: b"%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log.v:59: Cannot find file containing module: 'sync_reset'\n sync_reset log_bclk_res_sync( .glbl_reset(reset), .clk(bclk), .reset(bclk_reset) );\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset.v\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset.sv\n sync_reset\n sync_reset.v\n sync_reset.sv\n obj_dir/sync_reset\n obj_dir/sync_reset.v\n obj_dir/sync_reset.sv\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log.v:60: Cannot find file containing module: 'sync_reset'\n sync_reset log_clk100_res_sync( .glbl_reset(reset), .clk(clk100), .reset(clk100_reset) );\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 944 | module | module nand_log(
input wire bclk,
input wire clk100,
input wire nand_re,
input wire nand_we,
input wire nand_ale,
input wire nand_cle,
input wire nand_cs,
input wire nand_rb,
input wire [7:0] nand_din,
input wire [9:0] nand_uk,
input wire log_reset,
input wire log_run,
output reg log_cmd_error,
output reg log_data_error,
output reg [26:0] log_entries,
output wire [3:0] ddr3_wr_mask,
output wire [31:0] ddr3_wr_data,
output wire ddr3_wr_en,
input wire ddr3_wr_full,
input wire ddr3_wr_empty,
input wire [6:0] ddr3_wr_count,
output wire ddr3_cmd_clk,
output wire [2:0] ddr3_cmd_instr,
output wire ddr3_cmd_en,
output wire [5:0] ddr3_cmd_burstlen,
output wire [29:0] ddr3_cmd_addr,
input wire ddr3_cmd_full,
input wire ddr3_cmd_empty,
output wire [63:0] time_t_clk100,
input wire reset
);
wire bclk_reset, clk100_reset;
sync_reset log_bclk_res_sync( .glbl_reset(reset), .clk(bclk), .reset(bclk_reset) );
sync_reset log_clk100_res_sync( .glbl_reset(reset), .clk(clk100), .reset(clk100_reset) );
reg [7:0] cap_wr_din;
reg [9:0] cap_wr_uk;
reg cap_wr_ale;
reg cap_wr_cle;
reg cap_wr_cs;
reg cap_wr_rb;
reg [7:0] cap_rd_din;
reg [9:0] cap_rd_uk;
reg cap_rd_ale;
reg cap_rd_cle;
reg cap_rd_cs;
reg cap_rd_rb;
reg [7:0] log_din;
reg [9:0] log_uk;
reg log_ale;
reg log_cle;
reg log_cs;
reg log_rb;
reg log_we;
reg log_re;
reg log_capture_pulse;
wire cap_we;
wire cap_re;
reg cap_wed2, cap_wed1, cap_wedA;
reg cap_red2, cap_red1, cap_redA;
wire time_we;
wire time_re;
always @(posedge nand_we) begin
cap_wr_din[7:0] <= nand_din[7:0];
cap_wr_uk[9:0] <= nand_uk[9:0];
cap_wr_ale <= nand_ale;
cap_wr_cle <= nand_cle;
cap_wr_cs <= nand_cs;
cap_wr_rb <= nand_rb;
end
always @(posedge nand_re) begin
cap_rd_din[7:0] <= nand_din[7:0];
cap_rd_uk[9:0] <= nand_uk[9:0];
cap_rd_ale <= nand_ale;
cap_rd_cle <= nand_cle;
cap_rd_cs <= nand_cs;
cap_rd_rb <= nand_rb;
end
always @(posedge bclk) begin
cap_wed1 <= nand_we;
cap_red1 <= nand_re;
cap_wed2 <= cap_wed1;
cap_red2 <= cap_red1;
end
assign cap_we = !cap_wed2 & cap_wed1;
assign cap_re = !cap_red2 & cap_red1;
always @(posedge bclk) begin
log_capture_pulse <= cap_we || cap_re;
if( cap_we ) begin
log_din <= cap_wr_din;
log_uk <= cap_wr_uk;
log_ale <= cap_wr_ale;
log_cle <= cap_wr_cle;
log_cs <= cap_wr_cs;
log_rb <= cap_wr_rb;
log_we <= 1'b0;
log_re <= 1'b1;
end else if( cap_re ) begin
log_din <= cap_rd_din;
log_uk <= cap_rd_uk;
log_ale <= cap_rd_ale;
log_cle <= cap_rd_cle;
log_cs <= cap_rd_cs;
log_rb <= cap_rd_rb;
log_we <= 1'b1;
log_re <= 1'b0;
end else begin
log_din <= log_din;
log_uk <= log_uk;
log_ale <= log_ale;
log_cle <= log_cle;
log_cs <= log_cs;
log_rb <= log_rb;
log_we <= log_we;
log_re <= log_re;
end
end
wire [22:0] ddr3_log_data;
reg [40:0] ddr3_log_time;
wire [63:0] ddr3_log_entry;
reg [63:0] time_t_clk100_cap;
always @(posedge bclk) begin
if( cap_we || cap_re ) begin
ddr3_log_time[40:0] <= time_t_clk100_cap[40:0];
end else begin
ddr3_log_time <= ddr3_log_time;
end
end
assign ddr3_log_data[7:0] = log_din[7:0];
assign ddr3_log_data[8] = log_ale;
assign ddr3_log_data[9] = log_cle;
assign ddr3_log_data[10] = log_we;
assign ddr3_log_data[11] = log_re;
assign ddr3_log_data[12] = log_cs;
assign ddr3_log_data[22:13] = log_uk[9:0];
assign ddr3_log_entry[63:0] = {ddr3_log_time, ddr3_log_data};
parameter LOG_DATA = 4'b1 << 0;
parameter LOG_TIME = 4'b1 << 1;
parameter LOG_nSTATES = 4;
reg [(LOG_nSTATES - 1):0] cstate;
reg [(LOG_nSTATES - 1):0] nstate;
always @(posedge bclk or posedge bclk_reset) begin
if( bclk_reset ) begin
cstate <= LOG_DATA;
end else if( log_reset ) begin
cstate <= LOG_DATA;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
nstate <= LOG_TIME;
end else begin
nstate <= LOG_DATA;
end
end
LOG_TIME: begin
nstate <= LOG_DATA;
end
endcase
end
always @(posedge bclk) begin
if( log_reset ) begin
end else begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
end
end
endcase
end
end
reg [29:0] log_address;
reg cmd_delay;
reg cmd_flush;
assign ddr3_cmd_clk = bclk;
assign ddr3_wr_data = (cstate == LOG_DATA) ? ddr3_log_entry[31:0] : ddr3_log_entry[63:32];
assign ddr3_wr_mask = 4'b0;
assign ddr3_wr_en = (((cstate == LOG_DATA) && log_capture_pulse) || (cstate == LOG_TIME)) &
log_run;
assign ddr3_cmd_instr = 3'b000;
assign ddr3_cmd_burstlen = 6'h1;
assign ddr3_cmd_en = cmd_delay & log_run | cmd_flush;
assign ddr3_cmd_addr = log_address;
reg still_resetting;
always @(posedge bclk) begin
cmd_delay <= (cstate == LOG_TIME);
if( log_reset ) begin
log_address <= 30'h0F00_0000;
log_entries <= 27'h0;
end else if( cmd_delay ) begin
if( log_address < 30'h0FFF_FFF8 ) begin
log_address <= log_address + 30'h8;
end else begin
log_address <= log_address;
end
log_entries <= log_entries + 27'h1;
end else begin
log_address <= log_address;
log_entries <= log_entries;
end
if( log_reset ) begin
log_cmd_error <= 1'b0;
end else if( ddr3_cmd_full ) begin
log_cmd_error <= 1'b1;
end else begin
log_cmd_error <= log_cmd_error;
end
if( log_reset ) begin
log_data_error <= 1'b0;
still_resetting <= 1'b1;
end else if( still_resetting & ddr3_wr_full ) begin
still_resetting <= 1'b1;
log_data_error <= 1'b0;
end else if( !still_resetting & ddr3_wr_full ) begin
log_data_error <= 1'b1;
still_resetting <= 1'b0;
end else begin
log_data_error <= log_data_error;
still_resetting <= 1'b0;
end
end
reg [31:0] time_ns;
reg [31:0] time_s;
reg log_reset_clk100;
reg log_run_clk100;
wire time_we_clk100;
wire time_re_clk100;
reg clk100_wed1, clk100_wed2;
reg clk100_red1, clk100_red2;
assign time_we_clk100 = clk100_wed2 & !clk100_wed1;
assign time_re_clk100 = clk100_red2 & !clk100_red1;
always @(posedge clk100) begin
log_reset_clk100 <= log_reset;
log_run_clk100 <= log_run;
clk100_wed1 <= nand_we;
clk100_red1 <= nand_re;
clk100_wed2 <= clk100_wed1;
clk100_red2 <= clk100_red1;
if( time_we_clk100 || time_re_clk100 ) begin
time_t_clk100_cap <= {time_s, time_ns};
end else begin
time_t_clk100_cap <= time_t_clk100_cap;
end
if( log_reset_clk100 ) begin
time_ns <= 32'b0;
time_s <= 32'b0;
end else begin
if( log_run_clk100 ) begin
if( time_ns < 32'd999_999_999 ) begin
time_ns <= time_ns + 32'd10;
time_s <= time_s;
end else begin
time_ns <= 32'd0;
time_s <= time_s + 32'd1;
end
end else begin
time_ns <= time_ns;
time_s <= time_s;
end
end
end
assign time_t_clk100 = {time_s, time_ns};
endmodule | module nand_log(
input wire bclk,
input wire clk100,
input wire nand_re,
input wire nand_we,
input wire nand_ale,
input wire nand_cle,
input wire nand_cs,
input wire nand_rb,
input wire [7:0] nand_din,
input wire [9:0] nand_uk,
input wire log_reset,
input wire log_run,
output reg log_cmd_error,
output reg log_data_error,
output reg [26:0] log_entries,
output wire [3:0] ddr3_wr_mask,
output wire [31:0] ddr3_wr_data,
output wire ddr3_wr_en,
input wire ddr3_wr_full,
input wire ddr3_wr_empty,
input wire [6:0] ddr3_wr_count,
output wire ddr3_cmd_clk,
output wire [2:0] ddr3_cmd_instr,
output wire ddr3_cmd_en,
output wire [5:0] ddr3_cmd_burstlen,
output wire [29:0] ddr3_cmd_addr,
input wire ddr3_cmd_full,
input wire ddr3_cmd_empty,
output wire [63:0] time_t_clk100,
input wire reset
); |
wire bclk_reset, clk100_reset;
sync_reset log_bclk_res_sync( .glbl_reset(reset), .clk(bclk), .reset(bclk_reset) );
sync_reset log_clk100_res_sync( .glbl_reset(reset), .clk(clk100), .reset(clk100_reset) );
reg [7:0] cap_wr_din;
reg [9:0] cap_wr_uk;
reg cap_wr_ale;
reg cap_wr_cle;
reg cap_wr_cs;
reg cap_wr_rb;
reg [7:0] cap_rd_din;
reg [9:0] cap_rd_uk;
reg cap_rd_ale;
reg cap_rd_cle;
reg cap_rd_cs;
reg cap_rd_rb;
reg [7:0] log_din;
reg [9:0] log_uk;
reg log_ale;
reg log_cle;
reg log_cs;
reg log_rb;
reg log_we;
reg log_re;
reg log_capture_pulse;
wire cap_we;
wire cap_re;
reg cap_wed2, cap_wed1, cap_wedA;
reg cap_red2, cap_red1, cap_redA;
wire time_we;
wire time_re;
always @(posedge nand_we) begin
cap_wr_din[7:0] <= nand_din[7:0];
cap_wr_uk[9:0] <= nand_uk[9:0];
cap_wr_ale <= nand_ale;
cap_wr_cle <= nand_cle;
cap_wr_cs <= nand_cs;
cap_wr_rb <= nand_rb;
end
always @(posedge nand_re) begin
cap_rd_din[7:0] <= nand_din[7:0];
cap_rd_uk[9:0] <= nand_uk[9:0];
cap_rd_ale <= nand_ale;
cap_rd_cle <= nand_cle;
cap_rd_cs <= nand_cs;
cap_rd_rb <= nand_rb;
end
always @(posedge bclk) begin
cap_wed1 <= nand_we;
cap_red1 <= nand_re;
cap_wed2 <= cap_wed1;
cap_red2 <= cap_red1;
end
assign cap_we = !cap_wed2 & cap_wed1;
assign cap_re = !cap_red2 & cap_red1;
always @(posedge bclk) begin
log_capture_pulse <= cap_we || cap_re;
if( cap_we ) begin
log_din <= cap_wr_din;
log_uk <= cap_wr_uk;
log_ale <= cap_wr_ale;
log_cle <= cap_wr_cle;
log_cs <= cap_wr_cs;
log_rb <= cap_wr_rb;
log_we <= 1'b0;
log_re <= 1'b1;
end else if( cap_re ) begin
log_din <= cap_rd_din;
log_uk <= cap_rd_uk;
log_ale <= cap_rd_ale;
log_cle <= cap_rd_cle;
log_cs <= cap_rd_cs;
log_rb <= cap_rd_rb;
log_we <= 1'b1;
log_re <= 1'b0;
end else begin
log_din <= log_din;
log_uk <= log_uk;
log_ale <= log_ale;
log_cle <= log_cle;
log_cs <= log_cs;
log_rb <= log_rb;
log_we <= log_we;
log_re <= log_re;
end
end
wire [22:0] ddr3_log_data;
reg [40:0] ddr3_log_time;
wire [63:0] ddr3_log_entry;
reg [63:0] time_t_clk100_cap;
always @(posedge bclk) begin
if( cap_we || cap_re ) begin
ddr3_log_time[40:0] <= time_t_clk100_cap[40:0];
end else begin
ddr3_log_time <= ddr3_log_time;
end
end
assign ddr3_log_data[7:0] = log_din[7:0];
assign ddr3_log_data[8] = log_ale;
assign ddr3_log_data[9] = log_cle;
assign ddr3_log_data[10] = log_we;
assign ddr3_log_data[11] = log_re;
assign ddr3_log_data[12] = log_cs;
assign ddr3_log_data[22:13] = log_uk[9:0];
assign ddr3_log_entry[63:0] = {ddr3_log_time, ddr3_log_data};
parameter LOG_DATA = 4'b1 << 0;
parameter LOG_TIME = 4'b1 << 1;
parameter LOG_nSTATES = 4;
reg [(LOG_nSTATES - 1):0] cstate;
reg [(LOG_nSTATES - 1):0] nstate;
always @(posedge bclk or posedge bclk_reset) begin
if( bclk_reset ) begin
cstate <= LOG_DATA;
end else if( log_reset ) begin
cstate <= LOG_DATA;
end else begin
cstate <= nstate;
end
end
always @(*) begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
nstate <= LOG_TIME;
end else begin
nstate <= LOG_DATA;
end
end
LOG_TIME: begin
nstate <= LOG_DATA;
end
endcase
end
always @(posedge bclk) begin
if( log_reset ) begin
end else begin
case (cstate)
LOG_DATA: begin
if( log_capture_pulse ) begin
end
end
endcase
end
end
reg [29:0] log_address;
reg cmd_delay;
reg cmd_flush;
assign ddr3_cmd_clk = bclk;
assign ddr3_wr_data = (cstate == LOG_DATA) ? ddr3_log_entry[31:0] : ddr3_log_entry[63:32];
assign ddr3_wr_mask = 4'b0;
assign ddr3_wr_en = (((cstate == LOG_DATA) && log_capture_pulse) || (cstate == LOG_TIME)) &
log_run;
assign ddr3_cmd_instr = 3'b000;
assign ddr3_cmd_burstlen = 6'h1;
assign ddr3_cmd_en = cmd_delay & log_run | cmd_flush;
assign ddr3_cmd_addr = log_address;
reg still_resetting;
always @(posedge bclk) begin
cmd_delay <= (cstate == LOG_TIME);
if( log_reset ) begin
log_address <= 30'h0F00_0000;
log_entries <= 27'h0;
end else if( cmd_delay ) begin
if( log_address < 30'h0FFF_FFF8 ) begin
log_address <= log_address + 30'h8;
end else begin
log_address <= log_address;
end
log_entries <= log_entries + 27'h1;
end else begin
log_address <= log_address;
log_entries <= log_entries;
end
if( log_reset ) begin
log_cmd_error <= 1'b0;
end else if( ddr3_cmd_full ) begin
log_cmd_error <= 1'b1;
end else begin
log_cmd_error <= log_cmd_error;
end
if( log_reset ) begin
log_data_error <= 1'b0;
still_resetting <= 1'b1;
end else if( still_resetting & ddr3_wr_full ) begin
still_resetting <= 1'b1;
log_data_error <= 1'b0;
end else if( !still_resetting & ddr3_wr_full ) begin
log_data_error <= 1'b1;
still_resetting <= 1'b0;
end else begin
log_data_error <= log_data_error;
still_resetting <= 1'b0;
end
end
reg [31:0] time_ns;
reg [31:0] time_s;
reg log_reset_clk100;
reg log_run_clk100;
wire time_we_clk100;
wire time_re_clk100;
reg clk100_wed1, clk100_wed2;
reg clk100_red1, clk100_red2;
assign time_we_clk100 = clk100_wed2 & !clk100_wed1;
assign time_re_clk100 = clk100_red2 & !clk100_red1;
always @(posedge clk100) begin
log_reset_clk100 <= log_reset;
log_run_clk100 <= log_run;
clk100_wed1 <= nand_we;
clk100_red1 <= nand_re;
clk100_wed2 <= clk100_wed1;
clk100_red2 <= clk100_red1;
if( time_we_clk100 || time_re_clk100 ) begin
time_t_clk100_cap <= {time_s, time_ns};
end else begin
time_t_clk100_cap <= time_t_clk100_cap;
end
if( log_reset_clk100 ) begin
time_ns <= 32'b0;
time_s <= 32'b0;
end else begin
if( log_run_clk100 ) begin
if( time_ns < 32'd999_999_999 ) begin
time_ns <= time_ns + 32'd10;
time_s <= time_s;
end else begin
time_ns <= 32'd0;
time_s <= time_s + 32'd1;
end
end else begin
time_ns <= time_ns;
time_s <= time_s;
end
end
end
assign time_t_clk100 = {time_s, time_ns};
endmodule | 4 |
3,167 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v | 10,301,314 | nand_log_tb.v | v | 226 | 82 | [] | ['apache license'] | [] | null | line:189: before: ";" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_BCLK/2) bclk = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_BCLK/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK100/2) clk100 = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK100/2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:173: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:175: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:183: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:185: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:208: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:211: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:214: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:219: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/nand_log_tb.v:55: Cannot find file containing module: \'nand_log\'\nnand_log uut(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log.v\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/nand_log.sv\n nand_log\n nand_log.v\n nand_log.sv\n obj_dir/nand_log\n obj_dir/nand_log.v\n obj_dir/nand_log.sv\n%Error: Exiting due to 1 error(s), 28 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 945 | module | module nand_log_tb;
reg bclk;
reg clk100;
reg nand_re;
reg nand_we;
reg nand_ale;
reg nand_cle;
reg nand_cs;
reg nand_rb;
reg [7:0] nand_din;
reg [9:0] nand_uk;
reg log_reset;
reg log_run;
wire log_cmd_error;
wire log_data_error;
wire [26:0] log_entries;
wire [3:0] ddr3_wr_mask;
wire [31:0] ddr3_wr_data;
wire ddr3_wr_en;
reg ddr3_wr_full;
reg [6:0] ddr3_wr_count;
wire ddr3_cmd_clk;
wire [2:0] ddr3_cmd_instr;
wire ddr3_cmd_en;
wire [5:0] ddr3_cmd_burstlen;
wire [29:0] ddr3_cmd_addr;
reg ddr3_cmd_full;
wire [63:0] time_t_clk100;
reg reset;
nand_log uut(
bclk,
clk100,
nand_re,
nand_we,
nand_ale,
nand_cle,
nand_cs,
nand_rb,
nand_din,
nand_uk,
log_reset,
log_run,
log_cmd_error,
log_data_error,
log_entries,
ddr3_wr_mask,
ddr3_wr_data,
ddr3_wr_en,
ddr3_wr_full,
ddr3_wr_count,
ddr3_cmd_clk,
ddr3_cmd_instr,
ddr3_cmd_en,
ddr3_cmd_burstlen,
ddr3_cmd_addr,
ddr3_cmd_full,
time_t_clk100,
reset
);
parameter PERIOD_BCLK = 16'd8;
always begin
bclk = 1'b0;
#(PERIOD_BCLK/2) bclk = 1'b1;
#(PERIOD_BCLK/2);
end
parameter PERIOD_CLK100 = 16'd10;
always begin
clk100 = 1'b0;
#(PERIOD_CLK100/2) clk100 = 1'b1;
#(PERIOD_CLK100/2);
end
task nand_reset;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
log_reset = 1'b1;
log_run = 1'b0;
#1000;
log_reset = 1'b0;
log_run = 1'b1;
#1000;
end
endtask
task nand_idle;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
end
endtask
task nand_read_id;
begin
nand_cs = 1'b0;
nand_cle = 1'b1;
nand_we = 1'b0;
nand_din = 8'h90;
#25;
nand_we = 1'b1;
#5;
nand_cle = 1'b0;
nand_din = 8'h01;
#20;
nand_ale = 1'b1;
#25;
nand_we = 1'b0;
nand_din = 8'h00;
#25;
nand_we = 1'b1;
#5;
nand_din = 8'h23;
#20;
nand_ale = 1'b0;
#10;
nand_re = 1'b0;
nand_din = 8'h45;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h67;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h89;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hAB;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hCD;
#25;
nand_re = 1'b1;
#25;
nand_cs = 1'b1;
end
endtask;
initial begin
nand_re = 1;
nand_we = 1;
nand_ale = 0;
nand_cle = 0;
nand_rb = 1;
nand_din = 8'h00;
nand_uk[9:0] = 10'h0;
nand_cs = 1;
log_reset = 1'b0;
log_run = 1'b0;
ddr3_wr_full = 1'b0;
ddr3_wr_count = 7'b0;
ddr3_cmd_full = 1'b0;
reset = 1;
#1000;
reset = 0;
nand_reset();
#1000;
nand_idle();
#200;
nand_read_id();
$stop;
#1000;
$stop;
end
endmodule | module nand_log_tb; |
reg bclk;
reg clk100;
reg nand_re;
reg nand_we;
reg nand_ale;
reg nand_cle;
reg nand_cs;
reg nand_rb;
reg [7:0] nand_din;
reg [9:0] nand_uk;
reg log_reset;
reg log_run;
wire log_cmd_error;
wire log_data_error;
wire [26:0] log_entries;
wire [3:0] ddr3_wr_mask;
wire [31:0] ddr3_wr_data;
wire ddr3_wr_en;
reg ddr3_wr_full;
reg [6:0] ddr3_wr_count;
wire ddr3_cmd_clk;
wire [2:0] ddr3_cmd_instr;
wire ddr3_cmd_en;
wire [5:0] ddr3_cmd_burstlen;
wire [29:0] ddr3_cmd_addr;
reg ddr3_cmd_full;
wire [63:0] time_t_clk100;
reg reset;
nand_log uut(
bclk,
clk100,
nand_re,
nand_we,
nand_ale,
nand_cle,
nand_cs,
nand_rb,
nand_din,
nand_uk,
log_reset,
log_run,
log_cmd_error,
log_data_error,
log_entries,
ddr3_wr_mask,
ddr3_wr_data,
ddr3_wr_en,
ddr3_wr_full,
ddr3_wr_count,
ddr3_cmd_clk,
ddr3_cmd_instr,
ddr3_cmd_en,
ddr3_cmd_burstlen,
ddr3_cmd_addr,
ddr3_cmd_full,
time_t_clk100,
reset
);
parameter PERIOD_BCLK = 16'd8;
always begin
bclk = 1'b0;
#(PERIOD_BCLK/2) bclk = 1'b1;
#(PERIOD_BCLK/2);
end
parameter PERIOD_CLK100 = 16'd10;
always begin
clk100 = 1'b0;
#(PERIOD_CLK100/2) clk100 = 1'b1;
#(PERIOD_CLK100/2);
end
task nand_reset;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
log_reset = 1'b1;
log_run = 1'b0;
#1000;
log_reset = 1'b0;
log_run = 1'b1;
#1000;
end
endtask
task nand_idle;
begin
nand_we = 1'b1;
nand_re = 1'b1;
nand_ale = 1'b0;
nand_cle = 1'b0;
nand_cs = 1'b1;
nand_din = 8'hZZ;
end
endtask
task nand_read_id;
begin
nand_cs = 1'b0;
nand_cle = 1'b1;
nand_we = 1'b0;
nand_din = 8'h90;
#25;
nand_we = 1'b1;
#5;
nand_cle = 1'b0;
nand_din = 8'h01;
#20;
nand_ale = 1'b1;
#25;
nand_we = 1'b0;
nand_din = 8'h00;
#25;
nand_we = 1'b1;
#5;
nand_din = 8'h23;
#20;
nand_ale = 1'b0;
#10;
nand_re = 1'b0;
nand_din = 8'h45;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h67;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'h89;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hAB;
#25;
nand_re = 1'b1;
#25;
nand_re = 1'b0;
nand_din = 8'hCD;
#25;
nand_re = 1'b1;
#25;
nand_cs = 1'b1;
end
endtask;
initial begin
nand_re = 1;
nand_we = 1;
nand_ale = 0;
nand_cle = 0;
nand_rb = 1;
nand_din = 8'h00;
nand_uk[9:0] = 10'h0;
nand_cs = 1;
log_reset = 1'b0;
log_run = 1'b0;
ddr3_wr_full = 1'b0;
ddr3_wr_count = 7'b0;
ddr3_cmd_full = 1'b0;
reset = 1;
#1000;
reset = 0;
nand_reset();
#1000;
nand_idle();
#200;
nand_read_id();
$stop;
#1000;
$stop;
end
endmodule | 4 |
3,168 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v | 10,301,314 | novena_fpga.v | v | 1,383 | 117 | [] | ['apache license'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:193: Cannot find file containing module: 'sync_reset'\n sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset.v\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports,data/full_repos/permissive/10301314/sync_reset.sv\n sync_reset\n sync_reset.v\n sync_reset.sv\n obj_dir/sync_reset\n obj_dir/sync_reset.v\n obj_dir/sync_reset.sv\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:202: Cannot find file containing module: 'IBUFG'\n IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );\n ^~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:203: Cannot find file containing module: 'BUFG'\n BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );\n ^~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:205: Cannot find file containing module: 'bclk_dll'\n bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),\n ^~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:214: Cannot find file containing module: 'dcm_delay'\n dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:218: Cannot find file containing module: 'dcm_delay'\n dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:223: Cannot find file containing module: 'BUFIO2FB'\n BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));\n ^~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:263: Cannot find file containing module: 'IBUFG'\n IBUFG nand_we_ibufgp(.I(F_LVDS_PB), .O(nand_we_ibufg) );\n ^~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:264: Cannot find file containing module: 'BUFG'\n BUFG nand_we_bufgp(.I(nand_we_ibufg), .O(nand_we) );\n ^~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:265: Cannot find file containing module: 'IBUFG'\n IBUFG nand_re_ibufgp(.I(F_LVDS_CK_P1), .O(nand_re_ibufg) );\n ^~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:266: Cannot find file containing module: 'BUFG'\n BUFG nand_re_bufgp(.I(nand_re_ibufg), .O(nand_re) );\n ^~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:312: Cannot find file containing module: 'romulator_ddr3'\n romulator_ddr3 romulator_ddr3(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:428: Cannot find file containing module: 'nand_log'\n nand_log nand_log(\n ^~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:487: Cannot find file containing module: 'cmd_fifo_exp'\n cmd_fifo_exp cmd_fifo_exp(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:570: Cannot find file containing module: 'nandadr_fifo'\n nandadr_fifo nandadr_fifo(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:600: Cannot find file containing module: 'uk_fifo'\n uk_fifo cmd_fifo(\n ^~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:630: Cannot find file containing module: 'uk_fifo'\n uk_fifo uk_fifo(\n ^~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:706: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:710: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:716: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:720: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40012),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:727: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40020),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:732: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40022 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40022),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:736: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40024 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40024),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:740: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40026 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40026),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:744: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40028 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40028),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:748: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_4002A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:752: Cannot find file containing module: 'reg_r_det'\n reg_r_det reg_det_4102A (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:759: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40030),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:765: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40032),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:769: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40034),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:775: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40036 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40036),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:785: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40100),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:792: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40102),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:797: Cannot find file containing module: 'reg_wo'\n reg_wo reg_wo_40200 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40200),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:803: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:807: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:815: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41004 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41004),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:820: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41010),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:825: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41020),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:834: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41030),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:842: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41032),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:846: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:850: Cannot find file containing module: 'reg_r_det'\n reg_r_det reg_det_41034 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:855: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:859: Cannot find file containing module: 'reg_r_det'\n reg_r_det reg_det_41100 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:863: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:867: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),\n ^~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:871: Cannot find file containing module: 'reg_r_det'\n reg_r_det reg_det_41104 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/novena_fpga.v:875: Cannot find file containing module: 'reg_ro'\n reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),\n ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 947 | module | module novena_fpga(
output wire APOPTOSIS,
input wire AUD6_TFS,
input wire AUD6_TXC,
input wire AUD6_TXD,
input wire AUD_MCLK,
input wire AUD_MIC_CLK,
input wire AUD_MIC_DAT,
input wire BATT_NRST,
input wire BATT_REFLASH_ALRT,
input wire CLK2_N,
input wire CLK2_P,
input wire DDC_SCL,
input wire DDC_SDA,
output wire ECSPI3_MISO,
input wire ECSPI3_MOSI,
input wire ECSPI3_RDY,
input wire ECSPI3_SCLK,
input wire ECSPI3_SS2,
input wire EIM_BCLK,
input wire [1:0] EIM_CS,
inout wire [15:0] EIM_DA,
input wire [18:16] EIM_A,
input wire EIM_LBA,
input wire EIM_OE,
input wire EIM_RW,
input wire EIM_WAIT,
output wire FPGA_LED2,
input wire FPGA_LSPI_CLK,
input wire FPGA_LSPI_CS,
input wire FPGA_LSPI_HOLD,
input wire FPGA_LSPI_MISO,
input wire FPGA_LSPI_MOSI,
input wire FPGA_LSPI_WP,
input wire I2C3_SCL,
input wire I2C3_SDA,
input wire SMB_SCL,
input wire SMB_SDA,
input wire UART4_CTS,
input wire UART4_RTS,
input wire UART4_RXD,
input wire UART4_TXD,
inout wire F_LVDS_N2,
inout wire F_DX14,
inout wire F_LVDS_P4,
inout wire F_LVDS_N4,
inout wire F_LVDS_P1,
inout wire F_LVDS_N1,
inout wire F_DX0,
inout wire F_DX3,
inout wire F_DX2,
inout wire F_DX11,
inout wire F_LVDS_N11,
inout wire F_DX1,
inout wire F_LVDS_NC,
inout wire F_LVDS_PC,
inout wire F_LVDS_N0,
input wire F_LVDS_P0,
input wire F_LVDS_CK_P1,
input wire F_LVDS_P15,
input wire F_LVDS_NB,
input wire F_LVDS_PB,
input wire F_DX17,
inout wire [15:0] F_DDR3_D,
inout wire F_UDQS_N,
inout wire F_UDQS_P,
inout wire F_LDQS_N,
inout wire F_LDQS_P,
output wire F_UDM,
output wire F_LDM,
output wire [2:0] F_BA,
output wire F_CAS_N,
output wire [13:0] F_DDR3_A,
output wire F_DDR3_CKE,
output wire F_DDR3_CK_N,
output wire F_DDR3_CK_P,
output wire F_DDR3_ODT,
output wire F_RAS_N,
output wire F_WE_N,
inout wire F_DDR3_RZQ,
inout wire F_DDR3_ZIO,
output wire F_DDR3_RST_N,
input wire RESETBMCU
);
reg [15:0] eim_dout;
wire [15:0] eim_din;
wire clk;
wire clk50;
wire clk100;
wire bclk;
reg [23:0] counter;
wire eim_d_t;
wire ddr3_dll_locked;
wire ddr3clk;
wire ddr3_calib_done;
wire ddr3_p2_cmd_en;
wire [2:0] ddr3_p2_cmd_instr;
wire [5:0] ddr3_p2_cmd_bl;
wire [29:0] ddr3_p2_cmd_byte_addr;
wire ddr3_p2_cmd_empty;
wire ddr3_p2_cmd_full;
wire ddr3_p2_wr_en;
wire [3:0] ddr3_p2_wr_mask;
wire [31:0] ddr3_p2_wr_data;
wire ddr3_p2_wr_full;
wire ddr3_p2_wr_empty;
wire [6:0] ddr3_p2_wr_count;
wire ddr3_p2_wr_underrun;
wire ddr3_p2_wr_error;
wire ddr3_p2_wr_pulse;
wire p2_wr_pulse_gate;
wire ddr3_p3_cmd_en;
wire [2:0] ddr3_p3_cmd_instr;
wire [5:0] ddr3_p3_cmd_bl;
wire [29:0] ddr3_p3_cmd_byte_addr;
wire ddr3_p3_cmd_empty;
wire ddr3_p3_cmd_full;
wire ddr3_p3_rd_en;
wire [31:0] ddr3_p3_rd_data;
wire ddr3_p3_rd_full;
wire ddr3_p3_rd_empty;
wire [6:0] ddr3_p3_rd_count;
wire ddr3_p3_rd_overflow;
wire ddr3_p3_rd_error;
wire ddr3_p3_rd_pulse;
wire p3_rd_pulse_gate;
wire reset;
wire [15:0] gpioA_din;
wire [15:0] gpioA_dout;
wire [15:0] gpioA_dir;
sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );
wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
wire bclk_early;
wire bclk_int_in, bclk_io_in;
IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
.RESET(reset), .LOCKED(bclk_locked));
wire i_reset, i_locked;
wire o_reset, o_locked;
wire bclk_i, bclk_o;
wire i_fbk_out, i_fbk_in;
wire o_fbk_out, o_fbk_in;
dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
.CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
.RESET(i_reset), .LOCKED(i_locked));
dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
.CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
.RESET(o_reset), .LOCKED(o_locked));
BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
assign i_fbk_in = bclk_i;
wire [7:0] nand_din;
wire [7:0] nand_dout;
wire nand_drive_out;
wire nand_rb;
wire romulator_on;
wire nand_re, nand_re_ibufg;
wire nand_we, nand_we_ibufg;
wire nand_powered_on;
wire bypass_rb;
assign romulator_on = 1'b1;
assign nand_din = {F_DX0, F_DX3, F_DX2, F_DX11, F_LVDS_N11, F_DX1, F_LVDS_NC, F_LVDS_PC};
assign F_LVDS_PC = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[0] : 1'bZ;
assign F_LVDS_NC = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[1] : 1'bZ;
assign F_DX1 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[2] : 1'bZ;
assign F_LVDS_N11 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[3] : 1'bZ;
assign F_DX11 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[4] : 1'bZ;
assign F_DX2 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[5] : 1'bZ;
assign F_DX3 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[6] : 1'bZ;
assign F_DX0 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[7] : 1'bZ;
reg nand_rb_r;
always @(posedge bclk_dll) begin
nand_rb_r <= nand_rb;
end
assign F_LVDS_N0 = romulator_on & nand_powered_on ? (nand_rb_r | bypass_rb) : 1'bZ;
IBUFG nand_we_ibufgp(.I(F_LVDS_PB), .O(nand_we_ibufg) );
BUFG nand_we_bufgp(.I(nand_we_ibufg), .O(nand_we) );
IBUFG nand_re_ibufgp(.I(F_LVDS_CK_P1), .O(nand_re_ibufg) );
BUFG nand_re_bufgp(.I(nand_re_ibufg), .O(nand_re) );
wire [7:0] nand_uk_cmd;
wire nand_uk_updated;
wire [7:0] nand_known_cmd;
wire nand_cmd_updated;
wire [29:0] nand_adr;
wire nand_adr_updated;
wire nand_cs;
assign nand_cs = F_LVDS_P0;
wire rom_ddr3_reset;
wire page_addra_over;
wire outstanding_under;
wire ddr3_wr_clk;
wire ddr3_wr_cmd_en;
wire [2:0] ddr3_wr_cmd_instr;
wire [5:0] ddr3_wr_cmd_bl;
wire [29:0] ddr3_wr_adr;
wire ddr3_wr_cmd_full;
wire ddr3_wr_cmd_empty;
wire ddr3_wr_dat_en;
wire [31:0] ddr3_wr_dat;
wire ddr3_wr_full;
wire ddr3_wr_empty;
wire [6:0] ddr3_wr_dat_count;
wire [3:0] ddr3_wr_mask;
wire ddr3_rd_clk;
wire ddr3_rd_cmd_en;
wire [2:0] ddr3_rd_cmd_instr;
wire [5:0] ddr3_rd_cmd_bl;
wire [29:0] ddr3_rd_adr;
wire ddr3_rd_cmd_full;
wire ddr3_rd_dat_en;
wire [31:0] ddr3_rd_dat;
wire ddr3_rd_dat_empty;
wire [6:0] ddr3_rd_dat_count;
wire ddr3_rd_dat_full;
wire ddr3_rd_dat_overflow;
wire [2:0] ddr_cstate;
`ifdef USE_ROMULATOR
romulator_ddr3 romulator_ddr3(
.clk(bclk_dll),
.nand_we(nand_we),
.nand_re(nand_re),
.nand_cs(nand_cs),
.nand_ale(F_LVDS_NB),
.nand_cle(F_LVDS_P15),
.nand_rb(nand_rb),
.nand_wp(F_DX17),
.nand_din(nand_din),
.nand_dout(nand_dout),
.nand_drive_out(nand_drive_out),
.rom_ddr3_reset(rom_ddr3_reset),
.ddr3_wr_clk(ddr3_wr_clk),
.ddr3_wr_cmd_en(ddr3_wr_cmd_en),
.ddr3_wr_cmd_instr(ddr3_wr_cmd_instr[2:0]),
.ddr3_wr_cmd_bl(ddr3_wr_cmd_bl[5:0]),
.ddr3_wr_adr(ddr3_wr_adr[29:0]),
.ddr3_wr_cmd_full(ddr3_wr_cmd_full),
.ddr3_wr_cmd_empty(ddr3_wr_cmd_empty),
.ddr3_wr_dat_en(ddr3_wr_dat_en),
.ddr3_wr_dat(ddr3_wr_dat[31:0]),
.ddr3_wr_full(ddr3_wr_full),
.ddr3_wr_empty(ddr3_wr_empty),
.ddr3_wr_mask(ddr3_wr_mask[3:0]),
.ddr3_rd_clk(ddr3_rd_clk),
.ddr3_rd_cmd_en(ddr3_rd_cmd_en),
.ddr3_rd_cmd_instr(ddr3_rd_cmd_instr[2:0]),
.ddr3_rd_cmd_bl(ddr3_rd_cmd_bl[5:0]),
.ddr3_rd_adr(ddr3_rd_adr[29:0]),
.ddr3_rd_cmd_full(ddr3_rd_cmd_full),
.ddr3_rd_dat_en(ddr3_rd_dat_en),
.ddr3_rd_dat(ddr3_rd_dat[31:0]),
.ddr3_rd_dat_empty(ddr3_rd_dat_empty),
.ddr3_rd_dat_count(ddr3_rd_dat_count[6:0]),
.ddr3_rd_dat_full(ddr3_rd_dat_full),
.ddr3_rd_dat_overflow(ddr3_rd_dat_overflow),
.page_addra_over(page_addra_over),
.outstanding_under(outstanding_under),
.nand_uk_cmd(nand_uk_cmd),
.nand_uk_cmd_updated(nand_uk_updated),
.nand_known_cmd(nand_known_cmd),
.nand_cmd_updated(nand_cmd_updated),
.nand_adr(nand_adr),
.nand_adr_updated(nand_adr_updated),
.ddr_cstate_dbg(ddr_cstate),
.reset(reset)
);
`endif
reg page_addra_over_caught;
reg outstanding_under_caught;
always @(posedge bclk_dll) begin
if(rom_ddr3_reset) begin
page_addra_over_caught <= 1'b0;
outstanding_under_caught <= 1'b0;
end else begin
if( page_addra_over ) begin
page_addra_over_caught <= 1'b1;
end else begin
page_addra_over_caught <= page_addra_over_caught;
end
if( outstanding_under ) begin
outstanding_under_caught <= 1'b1;
end else begin
outstanding_under_caught <= outstanding_under_caught;
end
end
end
wire [3:0] log_wr_mask;
wire [31:0] log_wr_data;
wire log_wr_en;
wire [6:0] log_wr_count;
wire log_cmd_clk;
wire [2:0] log_cmd_instr;
wire log_cmd_en;
wire [5:0] log_cmd_burstlen;
wire [29:0] log_cmd_addr;
wire log_cmd_full;
wire [2:0] logbuf_cmd_instr;
wire logbuf_cmd_en;
wire [5:0] logbuf_cmd_burstlen;
wire [29:0] logbuf_cmd_addr;
wire logbuf_cmd_full;
wire logbuf_empty;
wire [63:0] time_t_clk100;
wire log_reset;
wire log_run;
wire log_cmd_error;
wire log_data_error;
wire [26:0] log_entries;
reg [63:0] time_t_bclk;
wire time_t_update;
assign logbuf_cmd_full = ddr3_p2_cmd_full;
`ifdef USE_NANDLOG
nand_log nand_log(
.bclk(bclk_dll),
.clk100(clk100),
.nand_re(nand_re),
.nand_we(nand_we),
.nand_cs(nand_cs),
.nand_ale(F_LVDS_NB),
.nand_cle(F_LVDS_P15),
.nand_rb(F_LVDS_N0),
.nand_din(nand_din),
.nand_uk(10'b0),
.log_reset(log_reset),
.log_run(log_run),
.log_cmd_error(log_cmd_error),
.log_data_error(log_data_error),
.log_entries(log_entries),
.ddr3_wr_mask(log_wr_mask),
.ddr3_wr_data(log_wr_data),
.ddr3_wr_en(log_wr_en),
.ddr3_wr_count(ddr3_p2_wr_count),
.ddr3_wr_full(ddr3_p2_wr_full),
.ddr3_wr_empty(ddr3_p2_wr_empty),
.ddr3_cmd_clk(log_cmd_clk),
.ddr3_cmd_instr(log_cmd_instr),
.ddr3_cmd_en(log_cmd_en),
.ddr3_cmd_burstlen(log_cmd_burstlen),
.ddr3_cmd_addr(log_cmd_addr),
.ddr3_cmd_full(ddr3_p2_cmd_full),
.ddr3_cmd_empty(ddr2_p2_cmd_empty),
.time_t_clk100(time_t_clk100),
.reset(reset)
);
`endif
assign log_wr_count = ddr3_p2_wr_count;
always @(posedge bclk_dll) begin
if( time_t_update ) begin
time_t_bclk <= time_t_clk100;
end else begin
time_t_bclk <= time_t_bclk;
end
end
wire log_cmd_overflow, log_cmd_underflow;
reg log_cmd_overflowed, log_cmd_underflowed;
wire [4:0] log_cmd_data_count;
reg [4:0] log_cmd_peak_data_count;
reg [6:0] log_wr_peak_count;
cmd_fifo_exp cmd_fifo_exp(
.clk(log_cmd_clk),
.srst(log_reset),
.din({log_cmd_addr[29:0], log_cmd_burstlen[5:0], log_cmd_instr[2:0]}),
.wr_en(log_cmd_en),
.rd_en(!logbuf_empty && !logbuf_cmd_full),
.dout({logbuf_cmd_addr[29:0], logbuf_cmd_burstlen[5:0], logbuf_cmd_instr[2:0]}),
.full(log_cmd_full),
.overflow(log_cmd_overflow),
.empty(logbuf_empty),
.underflow(log_cmd_underflow),
.data_count(log_cmd_data_count[4:0])
);
always @(posedge log_cmd_clk) begin
if( log_reset ) begin
log_cmd_overflowed <= 1'b0;
log_cmd_underflowed <= 1'b0;
log_cmd_peak_data_count <= 5'b0;
log_wr_peak_count <= 7'b0;
end else begin
if( log_cmd_overflow ) begin
log_cmd_overflowed <= 1'b1;
end else begin
log_cmd_overflowed <= log_cmd_overflowed;
end
if( log_cmd_underflow ) begin
log_cmd_underflowed <= 1'b1;
end else begin
log_cmd_underflowed <= log_cmd_underflowed;
end
if( log_cmd_data_count > log_cmd_peak_data_count ) begin
log_cmd_peak_data_count <= log_cmd_data_count;
end else begin
log_cmd_peak_data_count <= log_cmd_peak_data_count;
end
if( log_wr_count > log_wr_peak_count ) begin
log_wr_peak_count <= log_wr_count;
end else begin
log_wr_peak_count <= log_wr_peak_count;
end
end
end
wire nand_adr_updated_pulse;
reg nadr_up_d;
wire adrfifo_full, adrfifo_over, adrfifo_empty, adrfifo_rst;
wire adrfifo_rd_pulse;
wire [13:0] adrfifo_count;
wire [29:0] adrfifo_data;
wire log_adr_end;
reg nand_cs_clean;
reg nand_adr_up_clean;
always @(posedge bclk_dll) begin
nand_cs_clean <= nand_cs;
nand_adr_up_clean <= nand_adr_updated;
if( log_adr_end ) begin
nadr_up_d <= nand_adr_up_clean & !nand_cs_clean;
end else begin
nadr_up_d <= nand_adr_up_clean;
end
end
assign nand_adr_updated_pulse = log_adr_end ? (!nadr_up_d & (nand_adr_up_clean & !nand_cs_clean)) |
(nadr_up_d & !(nand_adr_up_clean & !nand_cs_clean)) :
(!nadr_up_d & nand_adr_up_clean);
reg [29:0] nand_adr_pipe;
reg nand_adr_updated_pulse_pipe;
always @(posedge bclk_dll) begin
nand_adr_pipe <= nand_adr;
nand_adr_updated_pulse_pipe <= nand_adr_updated_pulse;
end
nandadr_fifo nandadr_fifo(
.rst(adrfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_adr_pipe[29:0]),
.wr_en(nand_adr_updated_pulse_pipe),
.rd_en(adrfifo_rd_pulse),
.dout(adrfifo_data[29:0]),
.full(adrfifo_full),
.overflow(adrfifo_over),
.empty(adrfifo_empty),
.rd_data_count(adrfifo_count[13:0])
);
wire nand_cmd_updated_pulse;
reg ncmd_up_d;
wire cmdfifo_full, cmdfifo_over, cmdfifo_empty, cmdfifo_rst;
wire cmdfifo_rd_pulse;
wire [11:0] cmdfifo_count;
wire [7:0] cmdfifo_data;
always @(posedge bclk_dll) begin
ncmd_up_d <= nand_cmd_updated;
end
assign nand_cmd_updated_pulse = !ncmd_up_d && nand_cmd_updated;
uk_fifo cmd_fifo(
.rst(cmdfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_known_cmd[7:0]),
.wr_en(nand_cmd_updated_pulse),
.rd_en(cmdfifo_rd_pulse),
.dout(cmdfifo_data[7:0]),
.full(cmdfifo_full),
.overflow(cmdfifo_over),
.empty(cmdfifo_empty),
.rd_data_count(cmdfifo_count[11:0])
);
wire nand_uk_updated_pulse;
reg nuk_up_d;
wire ukfifo_full, ukfifo_over, ukfifo_empty, ukfifo_rst;
wire ukfifo_rd_pulse;
wire [11:0] ukfifo_count;
wire [7:0] ukfifo_data;
always @(posedge bclk_dll) begin
nuk_up_d <= nand_uk_updated;
end
assign nand_uk_updated_pulse = !nuk_up_d && nand_uk_updated;
uk_fifo uk_fifo(
.rst(ukfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_uk_cmd[7:0]),
.wr_en(nand_uk_updated_pulse),
.rd_en(ukfifo_rd_pulse),
.dout(ukfifo_data[7:0]),
.full(ukfifo_full),
.overflow(ukfifo_over),
.empty(ukfifo_empty),
.rd_data_count(ukfifo_count[11:0])
);
assign gpioA_din[0] = F_LVDS_P4;
assign gpioA_din[1] = F_DX14;
assign gpioA_din[2] = F_LVDS_N2;
assign gpioA_din[3] = F_LVDS_N1;
assign gpioA_din[4] = F_LVDS_N4;
assign gpioA_din[5] = F_LVDS_P1;
assign F_LVDS_P4 = gpioA_dir[0] & nand_powered_on ? gpioA_dout[0] : 1'bZ;
assign F_DX14 = gpioA_dir[1] & nand_powered_on ? gpioA_dout[1] : 1'bZ;
assign F_LVDS_N2 = gpioA_dir[2] & nand_powered_on ? gpioA_dout[2] : 1'bZ;
assign F_LVDS_N1 = gpioA_dir[3] & nand_powered_on ? gpioA_dout[3] : 1'bZ;
assign F_LVDS_N4 = gpioA_dir[4] & nand_powered_on ? gpioA_dout[4] : 1'bZ;
assign F_LVDS_P1 = gpioA_dir[5] & nand_powered_on ? gpioA_dout[5] : 1'bZ;
reg cs0_r, rw_r;
reg [15:0] din_r;
reg [18:0] bus_addr_r;
reg adv_r;
reg cs0_in, rw_in, adv_in;
reg [15:0] din_in;
reg [2:0] a_in;
always @(posedge bclk_i) begin
cs0_in <= EIM_CS[0];
rw_in <= EIM_RW;
din_in <= eim_din;
adv_in <= !EIM_LBA;
a_in <= EIM_A[18:16];
cs0_r <= cs0_in;
rw_r <= rw_in;
din_r <= din_in;
adv_r <= adv_in;
end
always @(posedge bclk_i) begin
if( adv_in ) begin
bus_addr_r <= {a_in, din_in};
end else begin
bus_addr_r <= bus_addr_r;
end
end
wire [15:0] r40000wo;
wire [15:0] r40002wo;
wire [15:0] ro_d;
reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( r40000wo[15:0] ) );
reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d),
.reg_d( r40002wo[15:0] ) );
reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( gpioA_dout[15:0] ) );
reg_wo reg_wo_40012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40012),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( gpioA_dir[15:0] ) );
wire [1:0] dummy_40020;
reg_wo reg_wo_40020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40020),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {p2_wr_pulse_gate, dummy_40020[1:0], ddr3_p2_cmd_bl[5:0],
ddr3_p2_cmd_en, ddr3_p2_cmd_instr[2:0] } ) );
reg_wo reg_wo_40022 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40022),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_cmd_byte_addr[15:0] ) );
reg_wo reg_wo_40024 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40024),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_cmd_byte_addr[29:16] ) );
reg_wo reg_wo_40026 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40026),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {ddr3_p2_wr_en, ddr3_p2_wr_mask[3:0]} ) );
reg_wo reg_wo_40028 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40028),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_wr_data[15:0] ) );
reg_wo reg_wo_4002A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_wr_data[31:16] ) );
reg_r_det reg_det_4102A (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),
.ena(!cs0_r && !rw_r),
.pulse( ddr3_p2_wr_pulse ) );
wire burst_mode;
wire [3:0] reg_40030_dummy;
reg_wo reg_wo_40030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40030),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {burst_mode, reg_40030_dummy[3:2], p3_rd_pulse_gate,
reg_40030_dummy[1:0], ddr3_p3_cmd_bl[5:0],
ddr3_p3_cmd_en, ddr3_p3_cmd_instr[2:0] } ) );
reg_wo reg_wo_40032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40032),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p3_cmd_byte_addr[15:0] ) );
reg_wo reg_wo_40034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40034),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p3_cmd_byte_addr[29:16] ) );
wire [3:0] ddr3_p3_dummy;
reg_wo reg_wo_40036 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40036),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {ddr3_p3_rd_en, ddr3_p3_dummy[3:0]} ) );
reg_wo reg_wo_40100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40100),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {rom_ddr3_reset, adrfifo_rst,
bypass_rb, cmdfifo_rst, ukfifo_rst, log_adr_end} ) );
reg_wo reg_wo_40102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40102),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {nand_powered_on} ) );
reg_wo reg_wo_40200 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40200),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {log_run, log_reset} ) );
reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40000wo[15:0] ) );
reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40002wo[15:0] ) );
reg_ro reg_ro_41004 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41004),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_calib_done, ddr3_dll_locked} ) );
reg_ro reg_ro_41010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41010),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( gpioA_din[15:0] ) );
reg_ro reg_ro_41020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41020),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_p2_wr_count[6:0],
2'b00,
ddr3_p2_cmd_empty, ddr3_p2_cmd_full,
ddr3_p2_wr_full, ddr3_p2_wr_empty,
ddr3_p2_wr_underrun, ddr3_p2_wr_error} ) );
reg_ro reg_ro_41030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41030),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_p3_rd_count[6:0],
2'b00,
ddr3_p3_cmd_empty, ddr3_p3_cmd_full,
ddr3_p3_rd_full, ddr3_p3_rd_empty,
ddr3_p3_rd_overflow, ddr3_p3_rd_error} ) );
reg_ro reg_ro_41032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41032),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( ddr3_p3_rd_data[15:0] ) );
reg_ro reg_ro_41034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( ddr3_p3_rd_data[31:16] ) );
reg_r_det reg_det_41034 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),
.ena(!cs0_r && rw_r),
.pulse( ddr3_p3_rd_pulse ) );
reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {8'b0, ukfifo_data[7:0]} ) );
reg_r_det reg_det_41100 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
.ena(!cs0_r && rw_r),
.pulse( ukfifo_rd_pulse ) );
reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {1'b0, ukfifo_full, ukfifo_over, ukfifo_empty, ukfifo_count[11:0]} ) );
reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {8'b0, cmdfifo_data[7:0]} ) );
reg_r_det reg_det_41104 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
.ena(!cs0_r && rw_r),
.pulse( cmdfifo_rd_pulse ) );
reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {1'b0, cmdfifo_full, cmdfifo_over, cmdfifo_empty, cmdfifo_count[11:0]} ) );
reg_ro reg_ro_41108 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41108),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {adrfifo_full, adrfifo_empty, adrfifo_count[13:0]} ) );
reg_ro reg_ro_4110A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110A),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {adrfifo_data[15:0]} ) );
reg_ro reg_ro_4110C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {2'b0,adrfifo_data[29:16]} ) );
reg_r_det reg_det_4110C (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
.ena(!cs0_r && rw_r),
.pulse( adrfifo_rd_pulse ) );
reg_ro reg_ro_4110E ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110E),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {page_addra_over_caught, outstanding_under_caught} ) );
reg_ro reg_ro_41110 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41110),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_rd_cmd_full, ddr3_rd_dat_en,
ddr3_rd_dat_full, ddr3_rd_dat_empty,
ddr3_rd_dat_count[6:0]} ) );
reg_ro reg_ro_41112 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41112),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr_cstate[2:0], 1'b0,
ddr3_wr_cmd_full, ddr3_wr_dat_en,
ddr3_wr_full, ddr3_wr_empty,
ddr3_wr_dat_count[6:0]} ) );
reg_ro reg_ro_41200 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41200),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {log_wr_peak_count[6:0], log_cmd_peak_data_count[4:0],
log_cmd_overflowed, log_cmd_underflowed,
log_cmd_error, log_data_error} ) );
reg_ro reg_ro_41202 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41202),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( log_entries[15:0] ) );
reg_ro reg_ro_41204 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41204),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( log_entries[26:16] ) );
reg_ro reg_ro_41206 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41206),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[15:0] ) );
reg_ro reg_ro_41220 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41220),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {log_cmd_full, log_wr_full} ) );
reg_r_det_early reg_det_41206 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41206),
.ena(!cs0_r && rw_r),
.pulse( time_t_update ) );
reg_ro reg_ro_41208 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41208),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[31:16] ) );
reg_ro reg_ro_4120A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4120A),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[47:32] ) );
reg_ro reg_ro_4120C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4120C),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[63:48] ) );
wire [63:0] rC04_0000wo;
wire [63:0] rC04_0008wo;
wire [15:0] ro_d_b;
reg_wo_4burst reg_wo_4b_C04_0000( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_wo_4burst reg_wo_4b_C04_0008( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
wire [63:0] burst_ctl;
wire burst_stb;
reg_wo_4burst reg_wo_4b_C04_0100( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0100),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_ctl[63:0] ), .rbk_d(ro_d_b), .strobe(burst_stb) );
reg_ro_4burst reg_ro_4b_C04_1000( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_ro_4burst reg_ro_4b_C04_1008( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
wire [63:0] burst_status;
reg_ro_4burst reg_ro_4b_C04_1108( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1108),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_status ), .rbk_d(ro_d_b) );
wire [63:0] burst_data;
wire burst_data_stb;
reg_ro_4burst reg_ro_4b_C04_1100( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1100),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_data ), .rbk_d(ro_d_b), .strobe(burst_data_stb) );
reg_ro reg_ro_41FFC ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFC),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h001A ) );
reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h0001 ) );
reg [15:0] ro_d_r;
reg [15:0] ro_d_b_r;
reg [1:0] eim_rdcs;
reg [15:0] eim_dout_pipe;
reg [15:0] eim_dout_pipe2;
always @(posedge bclk_dll) begin
ro_d_r <= ro_d;
ro_d_b_r <= ro_d_b;
eim_rdcs[1:0] <= EIM_CS[1:0];
eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
end
always @(posedge bclk_o) begin
eim_dout_pipe2 <= eim_dout_pipe;
eim_dout <= eim_dout_pipe2;
end;
always @(posedge clk50) begin
counter <= counter + 1;
end
assign FPGA_LED2 = counter[23];
IBUFGDS clkibufgds( .I(CLK2_P), .IB(CLK2_N), .O(clk) );
assign eim_d_t = EIM_OE | !EIM_LBA;
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
wire c1_clk0, c1_rst0;
ddr3_clkgen ddr3_clkgen (
.clk50in(clk),
.clk50(clk50),
.clk400(ddr3clk),
.clk100(clk100),
.RESET(reset),
.LOCKED(ddr3_dll_locked)
);
wire p2_cmd_en_pulse, p2_wr_en_pulse, p3_cmd_en_pulse, p3_rd_en_pulse;
rising_edge p2cmdp2e( .clk(bclk_dll), .level(ddr3_p2_cmd_en), .pulse(p2_cmd_en_pulse) );
rising_edge p2wrp2e( .clk(bclk_dll), .level(ddr3_p2_wr_en), .pulse(p2_wr_en_pulse) );
rising_edge p3cmdp2e( .clk(bclk_dll), .level(ddr3_p3_cmd_en), .pulse(p3_cmd_en_pulse) );
rising_edge p2rdp2e( .clk(bclk_dll), .level(ddr3_p3_rd_en), .pulse(p3_rd_en_pulse) );
wire p2_cmd_en;
wire [2:0] p2_cmd_instr;
wire [5:0] p2_cmd_bl;
wire [29:0] p2_cmd_byte_addr;
wire p2_wr_en;
wire [3:0] p2_wr_mask;
wire [31:0] p2_wr_data;
reg log_cmd_en_delay;
always @(posedge bclk_dll) begin
log_cmd_en_delay <= !logbuf_empty && !logbuf_cmd_full;
end
assign p2_cmd_en = log_run ? log_cmd_en_delay : p2_cmd_en_pulse;
assign p2_cmd_instr[2:0] = log_run ? logbuf_cmd_instr[2:0] : ddr3_p2_cmd_instr[2:0];
assign p2_cmd_bl = log_run ? logbuf_cmd_burstlen : ddr3_p2_cmd_bl;
assign p2_cmd_byte_addr = log_run ? logbuf_cmd_addr : ddr3_p2_cmd_byte_addr;
assign p2_wr_en = log_run ? log_wr_en : (p2_wr_en_pulse || (ddr3_p2_wr_pulse & p2_wr_pulse_gate));
assign p2_wr_mask = log_run ? log_wr_mask : ddr3_p2_wr_mask;
assign p2_wr_data = log_run ? log_wr_data : ddr3_p2_wr_data;
wire p3_cmd_en;
wire p3_burst_cmd_en;
wire [2:0] p3_cmd_instr;
wire [2:0] p3_burst_cmd_instr;
wire [5:0] p3_cmd_bl;
wire [5:0] p3_burst_cmd_bl;
wire [29:0] p3_cmd_byte_addr;
wire [29:0] p3_burst_addr;
wire p3_rd_en;
wire p3_burst_rd_en;
assign p3_cmd_en = burst_mode ? p3_burst_cmd_en : p3_cmd_en_pulse;
assign p3_cmd_instr = burst_mode ? p3_burst_cmd_instr : ddr3_p3_cmd_instr;
assign p3_cmd_bl = burst_mode ? p3_burst_cmd_bl : ddr3_p3_cmd_bl;
assign p3_cmd_byte_addr = burst_mode ? p3_burst_addr : ddr3_p3_cmd_byte_addr;
assign p3_rd_en = burst_mode ? p3_burst_rd_en : (p3_rd_en_pulse || (ddr3_p3_rd_pulse & p3_rd_pulse_gate));
wire ddr3_reset_local;
ddr3_eim_cs1 cs1_adapter(.clk(bclk_dll),
.ctl(burst_ctl),
.ctl_stb(burst_stb),
.burst_rd(burst_data[63:0]),
.rd_stb(burst_data_stb),
.status(burst_status[63:0]),
.ddr3_rd_cmd(p3_burst_cmd_instr),
.ddr3_rd_bl(p3_burst_cmd_bl),
.ddr3_rd_adr(p3_burst_addr),
.ddr3_rd_cmd_en(p3_burst_cmd_en),
.ddr3_rd_cmd_empty(ddr3_p3_cmd_empty),
.ddr3_rd_cmd_full(ddr3_p3_cmd_full),
.ddr3_rd_data(ddr3_p3_rd_data[31:0]),
.ddr3_rd_count(ddr3_p3_rd_count),
.ddr3_rd_empty(ddr3_p3_rd_empty),
.ddr3_rd_full(ddr3_p3_rd_full),
.ddr3_rd_en(p3_burst_rd_en),
.reset(ddr3_reset_local)
);
sync_reset ddr3_res_sync( .glbl_reset(log_reset), .clk(ddr3clk), .reset(ddr3_reset_local) );
ddr3_if_4port # (
.C1_P0_MASK_SIZE(4),
.C1_P0_DATA_PORT_SIZE(32),
.C1_P1_MASK_SIZE(4),
.C1_P1_DATA_PORT_SIZE(32),
.DEBUG_EN(0),
.C1_MEMCLK_PERIOD(2500),
.C1_CALIB_SOFT_IP("TRUE"),
.C1_SIMULATION("FALSE"),
.C1_RST_ACT_LOW(0),
.C1_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C1_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
.C1_NUM_DQ_PINS(16),
.C1_MEM_ADDR_WIDTH(14),
.C1_MEM_BANKADDR_WIDTH(3)
)
u_ddr3_if (
.c1_sys_clk (ddr3clk),
.c1_sys_rst_i (reset),
.mcb1_dram_dq (F_DDR3_D[15:0]),
.mcb1_dram_a (F_DDR3_A[13:0]),
.mcb1_dram_ba (F_BA[2:0]),
.mcb1_dram_ras_n (F_RAS_N),
.mcb1_dram_cas_n (F_CAS_N),
.mcb1_dram_we_n (F_WE_N),
.mcb1_dram_odt (F_DDR3_ODT),
.mcb1_dram_cke (F_DDR3_CKE),
.mcb1_dram_ck (F_DDR3_CK_P),
.mcb1_dram_ck_n (F_DDR3_CK_N),
.mcb1_dram_dqs (F_LDQS_P),
.mcb1_dram_dqs_n (F_LDQS_N),
.mcb1_dram_udqs (F_UDQS_P),
.mcb1_dram_udqs_n (F_UDQS_N),
.mcb1_dram_udm (F_UDM),
.mcb1_dram_dm (F_LDM),
.mcb1_dram_reset_n (F_DDR3_RST_N),
.c1_clk0 (c1_clk0),
.c1_rst0 (c1_rst0),
.c1_calib_done (ddr3_calib_done),
.mcb1_rzq (F_DDR3_RZQ),
.mcb1_zio (F_DDR3_ZIO),
.c1_p2_cmd_clk (bclk_dll),
.c1_p2_cmd_en (p2_cmd_en),
.c1_p2_cmd_instr (p2_cmd_instr),
.c1_p2_cmd_bl (p2_cmd_bl),
.c1_p2_cmd_byte_addr (p2_cmd_byte_addr),
.c1_p2_cmd_empty (ddr3_p2_cmd_empty),
.c1_p2_cmd_full (ddr3_p2_cmd_full),
.c1_p2_wr_clk (bclk_dll),
.c1_p2_wr_en (p2_wr_en),
.c1_p2_wr_mask (p2_wr_mask),
.c1_p2_wr_data (p2_wr_data),
.c1_p2_wr_full (ddr3_p2_wr_full),
.c1_p2_wr_empty (ddr3_p2_wr_empty),
.c1_p2_wr_count (ddr3_p2_wr_count),
.c1_p2_wr_underrun (ddr3_p2_wr_underrun),
.c1_p2_wr_error (ddr3_p2_wr_error),
.c1_p3_cmd_clk (bclk_dll),
.c1_p3_cmd_en (p3_cmd_en),
.c1_p3_cmd_instr (p3_cmd_instr),
.c1_p3_cmd_bl (p3_cmd_bl),
.c1_p3_cmd_byte_addr (p3_cmd_byte_addr),
.c1_p3_cmd_empty (ddr3_p3_cmd_empty),
.c1_p3_cmd_full (ddr3_p3_cmd_full),
.c1_p3_rd_clk (bclk_dll),
.c1_p3_rd_en (p3_rd_en),
.c1_p3_rd_data (ddr3_p3_rd_data),
.c1_p3_rd_full (ddr3_p3_rd_full),
.c1_p3_rd_empty (ddr3_p3_rd_empty),
.c1_p3_rd_count (ddr3_p3_rd_count),
.c1_p3_rd_overflow (ddr3_p3_rd_overflow),
.c1_p3_rd_error (ddr3_p3_rd_error),
.c1_p4_cmd_clk (ddr3_wr_clk),
.c1_p4_cmd_en (ddr3_wr_cmd_en),
.c1_p4_cmd_instr (ddr3_wr_cmd_instr[2:0]),
.c1_p4_cmd_bl (ddr3_wr_cmd_bl[5:0]),
.c1_p4_cmd_byte_addr (ddr3_wr_adr[29:0]),
.c1_p4_cmd_empty (ddr3_wr_cmd_empty),
.c1_p4_cmd_full (ddr3_wr_cmd_full),
.c1_p4_wr_clk (ddr3_wr_clk),
.c1_p4_wr_en (ddr3_wr_dat_en),
.c1_p4_wr_mask (ddr3_wr_mask[3:0]),
.c1_p4_wr_data (ddr3_wr_dat[31:0]),
.c1_p4_wr_full (ddr3_wr_full),
.c1_p4_wr_empty (ddr3_wr_empty),
.c1_p4_wr_count (ddr3_wr_dat_count[6:0]),
.c1_p5_cmd_clk (ddr3_rd_clk),
.c1_p5_cmd_en (ddr3_rd_cmd_en),
.c1_p5_cmd_instr (ddr3_rd_cmd_instr[2:0]),
.c1_p5_cmd_bl (ddr3_rd_cmd_bl[5:0]),
.c1_p5_cmd_byte_addr (ddr3_rd_adr[29:0]),
.c1_p5_cmd_full (ddr3_rd_cmd_full),
.c1_p5_rd_clk (ddr3_rd_clk),
.c1_p5_rd_en (ddr3_rd_dat_en),
.c1_p5_rd_data (ddr3_rd_dat[31:0]),
.c1_p5_rd_full (ddr3_rd_dat_full),
.c1_p5_rd_empty (ddr3_rd_dat_empty),
.c1_p5_rd_count (ddr3_rd_dat_count[6:0]),
.c1_p5_rd_overflow (ddr3_rd_dat_overflow)
);
assign APOPTOSIS = 1'b0;
assign ECSPI3_MISO = 1'b0;
endmodule | module novena_fpga(
output wire APOPTOSIS,
input wire AUD6_TFS,
input wire AUD6_TXC,
input wire AUD6_TXD,
input wire AUD_MCLK,
input wire AUD_MIC_CLK,
input wire AUD_MIC_DAT,
input wire BATT_NRST,
input wire BATT_REFLASH_ALRT,
input wire CLK2_N,
input wire CLK2_P,
input wire DDC_SCL,
input wire DDC_SDA,
output wire ECSPI3_MISO,
input wire ECSPI3_MOSI,
input wire ECSPI3_RDY,
input wire ECSPI3_SCLK,
input wire ECSPI3_SS2,
input wire EIM_BCLK,
input wire [1:0] EIM_CS,
inout wire [15:0] EIM_DA,
input wire [18:16] EIM_A,
input wire EIM_LBA,
input wire EIM_OE,
input wire EIM_RW,
input wire EIM_WAIT,
output wire FPGA_LED2,
input wire FPGA_LSPI_CLK,
input wire FPGA_LSPI_CS,
input wire FPGA_LSPI_HOLD,
input wire FPGA_LSPI_MISO,
input wire FPGA_LSPI_MOSI,
input wire FPGA_LSPI_WP,
input wire I2C3_SCL,
input wire I2C3_SDA,
input wire SMB_SCL,
input wire SMB_SDA,
input wire UART4_CTS,
input wire UART4_RTS,
input wire UART4_RXD,
input wire UART4_TXD,
inout wire F_LVDS_N2,
inout wire F_DX14,
inout wire F_LVDS_P4,
inout wire F_LVDS_N4,
inout wire F_LVDS_P1,
inout wire F_LVDS_N1,
inout wire F_DX0,
inout wire F_DX3,
inout wire F_DX2,
inout wire F_DX11,
inout wire F_LVDS_N11,
inout wire F_DX1,
inout wire F_LVDS_NC,
inout wire F_LVDS_PC,
inout wire F_LVDS_N0,
input wire F_LVDS_P0,
input wire F_LVDS_CK_P1,
input wire F_LVDS_P15,
input wire F_LVDS_NB,
input wire F_LVDS_PB,
input wire F_DX17,
inout wire [15:0] F_DDR3_D,
inout wire F_UDQS_N,
inout wire F_UDQS_P,
inout wire F_LDQS_N,
inout wire F_LDQS_P,
output wire F_UDM,
output wire F_LDM,
output wire [2:0] F_BA,
output wire F_CAS_N,
output wire [13:0] F_DDR3_A,
output wire F_DDR3_CKE,
output wire F_DDR3_CK_N,
output wire F_DDR3_CK_P,
output wire F_DDR3_ODT,
output wire F_RAS_N,
output wire F_WE_N,
inout wire F_DDR3_RZQ,
inout wire F_DDR3_ZIO,
output wire F_DDR3_RST_N,
input wire RESETBMCU
); |
reg [15:0] eim_dout;
wire [15:0] eim_din;
wire clk;
wire clk50;
wire clk100;
wire bclk;
reg [23:0] counter;
wire eim_d_t;
wire ddr3_dll_locked;
wire ddr3clk;
wire ddr3_calib_done;
wire ddr3_p2_cmd_en;
wire [2:0] ddr3_p2_cmd_instr;
wire [5:0] ddr3_p2_cmd_bl;
wire [29:0] ddr3_p2_cmd_byte_addr;
wire ddr3_p2_cmd_empty;
wire ddr3_p2_cmd_full;
wire ddr3_p2_wr_en;
wire [3:0] ddr3_p2_wr_mask;
wire [31:0] ddr3_p2_wr_data;
wire ddr3_p2_wr_full;
wire ddr3_p2_wr_empty;
wire [6:0] ddr3_p2_wr_count;
wire ddr3_p2_wr_underrun;
wire ddr3_p2_wr_error;
wire ddr3_p2_wr_pulse;
wire p2_wr_pulse_gate;
wire ddr3_p3_cmd_en;
wire [2:0] ddr3_p3_cmd_instr;
wire [5:0] ddr3_p3_cmd_bl;
wire [29:0] ddr3_p3_cmd_byte_addr;
wire ddr3_p3_cmd_empty;
wire ddr3_p3_cmd_full;
wire ddr3_p3_rd_en;
wire [31:0] ddr3_p3_rd_data;
wire ddr3_p3_rd_full;
wire ddr3_p3_rd_empty;
wire [6:0] ddr3_p3_rd_count;
wire ddr3_p3_rd_overflow;
wire ddr3_p3_rd_error;
wire ddr3_p3_rd_pulse;
wire p3_rd_pulse_gate;
wire reset;
wire [15:0] gpioA_din;
wire [15:0] gpioA_dout;
wire [15:0] gpioA_dir;
sync_reset master_res_sync( .glbl_reset(!RESETBMCU), .clk(clk), .reset(reset) );
wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
wire bclk_early;
wire bclk_int_in, bclk_io_in;
IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
.RESET(reset), .LOCKED(bclk_locked));
wire i_reset, i_locked;
wire o_reset, o_locked;
wire bclk_i, bclk_o;
wire i_fbk_out, i_fbk_in;
wire o_fbk_out, o_fbk_in;
dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
.CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
.RESET(i_reset), .LOCKED(i_locked));
dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
.CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
.RESET(o_reset), .LOCKED(o_locked));
BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in));
assign i_fbk_in = bclk_i;
wire [7:0] nand_din;
wire [7:0] nand_dout;
wire nand_drive_out;
wire nand_rb;
wire romulator_on;
wire nand_re, nand_re_ibufg;
wire nand_we, nand_we_ibufg;
wire nand_powered_on;
wire bypass_rb;
assign romulator_on = 1'b1;
assign nand_din = {F_DX0, F_DX3, F_DX2, F_DX11, F_LVDS_N11, F_DX1, F_LVDS_NC, F_LVDS_PC};
assign F_LVDS_PC = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[0] : 1'bZ;
assign F_LVDS_NC = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[1] : 1'bZ;
assign F_DX1 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[2] : 1'bZ;
assign F_LVDS_N11 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[3] : 1'bZ;
assign F_DX11 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[4] : 1'bZ;
assign F_DX2 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[5] : 1'bZ;
assign F_DX3 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[6] : 1'bZ;
assign F_DX0 = (nand_drive_out & romulator_on & nand_powered_on) ? nand_dout[7] : 1'bZ;
reg nand_rb_r;
always @(posedge bclk_dll) begin
nand_rb_r <= nand_rb;
end
assign F_LVDS_N0 = romulator_on & nand_powered_on ? (nand_rb_r | bypass_rb) : 1'bZ;
IBUFG nand_we_ibufgp(.I(F_LVDS_PB), .O(nand_we_ibufg) );
BUFG nand_we_bufgp(.I(nand_we_ibufg), .O(nand_we) );
IBUFG nand_re_ibufgp(.I(F_LVDS_CK_P1), .O(nand_re_ibufg) );
BUFG nand_re_bufgp(.I(nand_re_ibufg), .O(nand_re) );
wire [7:0] nand_uk_cmd;
wire nand_uk_updated;
wire [7:0] nand_known_cmd;
wire nand_cmd_updated;
wire [29:0] nand_adr;
wire nand_adr_updated;
wire nand_cs;
assign nand_cs = F_LVDS_P0;
wire rom_ddr3_reset;
wire page_addra_over;
wire outstanding_under;
wire ddr3_wr_clk;
wire ddr3_wr_cmd_en;
wire [2:0] ddr3_wr_cmd_instr;
wire [5:0] ddr3_wr_cmd_bl;
wire [29:0] ddr3_wr_adr;
wire ddr3_wr_cmd_full;
wire ddr3_wr_cmd_empty;
wire ddr3_wr_dat_en;
wire [31:0] ddr3_wr_dat;
wire ddr3_wr_full;
wire ddr3_wr_empty;
wire [6:0] ddr3_wr_dat_count;
wire [3:0] ddr3_wr_mask;
wire ddr3_rd_clk;
wire ddr3_rd_cmd_en;
wire [2:0] ddr3_rd_cmd_instr;
wire [5:0] ddr3_rd_cmd_bl;
wire [29:0] ddr3_rd_adr;
wire ddr3_rd_cmd_full;
wire ddr3_rd_dat_en;
wire [31:0] ddr3_rd_dat;
wire ddr3_rd_dat_empty;
wire [6:0] ddr3_rd_dat_count;
wire ddr3_rd_dat_full;
wire ddr3_rd_dat_overflow;
wire [2:0] ddr_cstate;
`ifdef USE_ROMULATOR
romulator_ddr3 romulator_ddr3(
.clk(bclk_dll),
.nand_we(nand_we),
.nand_re(nand_re),
.nand_cs(nand_cs),
.nand_ale(F_LVDS_NB),
.nand_cle(F_LVDS_P15),
.nand_rb(nand_rb),
.nand_wp(F_DX17),
.nand_din(nand_din),
.nand_dout(nand_dout),
.nand_drive_out(nand_drive_out),
.rom_ddr3_reset(rom_ddr3_reset),
.ddr3_wr_clk(ddr3_wr_clk),
.ddr3_wr_cmd_en(ddr3_wr_cmd_en),
.ddr3_wr_cmd_instr(ddr3_wr_cmd_instr[2:0]),
.ddr3_wr_cmd_bl(ddr3_wr_cmd_bl[5:0]),
.ddr3_wr_adr(ddr3_wr_adr[29:0]),
.ddr3_wr_cmd_full(ddr3_wr_cmd_full),
.ddr3_wr_cmd_empty(ddr3_wr_cmd_empty),
.ddr3_wr_dat_en(ddr3_wr_dat_en),
.ddr3_wr_dat(ddr3_wr_dat[31:0]),
.ddr3_wr_full(ddr3_wr_full),
.ddr3_wr_empty(ddr3_wr_empty),
.ddr3_wr_mask(ddr3_wr_mask[3:0]),
.ddr3_rd_clk(ddr3_rd_clk),
.ddr3_rd_cmd_en(ddr3_rd_cmd_en),
.ddr3_rd_cmd_instr(ddr3_rd_cmd_instr[2:0]),
.ddr3_rd_cmd_bl(ddr3_rd_cmd_bl[5:0]),
.ddr3_rd_adr(ddr3_rd_adr[29:0]),
.ddr3_rd_cmd_full(ddr3_rd_cmd_full),
.ddr3_rd_dat_en(ddr3_rd_dat_en),
.ddr3_rd_dat(ddr3_rd_dat[31:0]),
.ddr3_rd_dat_empty(ddr3_rd_dat_empty),
.ddr3_rd_dat_count(ddr3_rd_dat_count[6:0]),
.ddr3_rd_dat_full(ddr3_rd_dat_full),
.ddr3_rd_dat_overflow(ddr3_rd_dat_overflow),
.page_addra_over(page_addra_over),
.outstanding_under(outstanding_under),
.nand_uk_cmd(nand_uk_cmd),
.nand_uk_cmd_updated(nand_uk_updated),
.nand_known_cmd(nand_known_cmd),
.nand_cmd_updated(nand_cmd_updated),
.nand_adr(nand_adr),
.nand_adr_updated(nand_adr_updated),
.ddr_cstate_dbg(ddr_cstate),
.reset(reset)
);
`endif
reg page_addra_over_caught;
reg outstanding_under_caught;
always @(posedge bclk_dll) begin
if(rom_ddr3_reset) begin
page_addra_over_caught <= 1'b0;
outstanding_under_caught <= 1'b0;
end else begin
if( page_addra_over ) begin
page_addra_over_caught <= 1'b1;
end else begin
page_addra_over_caught <= page_addra_over_caught;
end
if( outstanding_under ) begin
outstanding_under_caught <= 1'b1;
end else begin
outstanding_under_caught <= outstanding_under_caught;
end
end
end
wire [3:0] log_wr_mask;
wire [31:0] log_wr_data;
wire log_wr_en;
wire [6:0] log_wr_count;
wire log_cmd_clk;
wire [2:0] log_cmd_instr;
wire log_cmd_en;
wire [5:0] log_cmd_burstlen;
wire [29:0] log_cmd_addr;
wire log_cmd_full;
wire [2:0] logbuf_cmd_instr;
wire logbuf_cmd_en;
wire [5:0] logbuf_cmd_burstlen;
wire [29:0] logbuf_cmd_addr;
wire logbuf_cmd_full;
wire logbuf_empty;
wire [63:0] time_t_clk100;
wire log_reset;
wire log_run;
wire log_cmd_error;
wire log_data_error;
wire [26:0] log_entries;
reg [63:0] time_t_bclk;
wire time_t_update;
assign logbuf_cmd_full = ddr3_p2_cmd_full;
`ifdef USE_NANDLOG
nand_log nand_log(
.bclk(bclk_dll),
.clk100(clk100),
.nand_re(nand_re),
.nand_we(nand_we),
.nand_cs(nand_cs),
.nand_ale(F_LVDS_NB),
.nand_cle(F_LVDS_P15),
.nand_rb(F_LVDS_N0),
.nand_din(nand_din),
.nand_uk(10'b0),
.log_reset(log_reset),
.log_run(log_run),
.log_cmd_error(log_cmd_error),
.log_data_error(log_data_error),
.log_entries(log_entries),
.ddr3_wr_mask(log_wr_mask),
.ddr3_wr_data(log_wr_data),
.ddr3_wr_en(log_wr_en),
.ddr3_wr_count(ddr3_p2_wr_count),
.ddr3_wr_full(ddr3_p2_wr_full),
.ddr3_wr_empty(ddr3_p2_wr_empty),
.ddr3_cmd_clk(log_cmd_clk),
.ddr3_cmd_instr(log_cmd_instr),
.ddr3_cmd_en(log_cmd_en),
.ddr3_cmd_burstlen(log_cmd_burstlen),
.ddr3_cmd_addr(log_cmd_addr),
.ddr3_cmd_full(ddr3_p2_cmd_full),
.ddr3_cmd_empty(ddr2_p2_cmd_empty),
.time_t_clk100(time_t_clk100),
.reset(reset)
);
`endif
assign log_wr_count = ddr3_p2_wr_count;
always @(posedge bclk_dll) begin
if( time_t_update ) begin
time_t_bclk <= time_t_clk100;
end else begin
time_t_bclk <= time_t_bclk;
end
end
wire log_cmd_overflow, log_cmd_underflow;
reg log_cmd_overflowed, log_cmd_underflowed;
wire [4:0] log_cmd_data_count;
reg [4:0] log_cmd_peak_data_count;
reg [6:0] log_wr_peak_count;
cmd_fifo_exp cmd_fifo_exp(
.clk(log_cmd_clk),
.srst(log_reset),
.din({log_cmd_addr[29:0], log_cmd_burstlen[5:0], log_cmd_instr[2:0]}),
.wr_en(log_cmd_en),
.rd_en(!logbuf_empty && !logbuf_cmd_full),
.dout({logbuf_cmd_addr[29:0], logbuf_cmd_burstlen[5:0], logbuf_cmd_instr[2:0]}),
.full(log_cmd_full),
.overflow(log_cmd_overflow),
.empty(logbuf_empty),
.underflow(log_cmd_underflow),
.data_count(log_cmd_data_count[4:0])
);
always @(posedge log_cmd_clk) begin
if( log_reset ) begin
log_cmd_overflowed <= 1'b0;
log_cmd_underflowed <= 1'b0;
log_cmd_peak_data_count <= 5'b0;
log_wr_peak_count <= 7'b0;
end else begin
if( log_cmd_overflow ) begin
log_cmd_overflowed <= 1'b1;
end else begin
log_cmd_overflowed <= log_cmd_overflowed;
end
if( log_cmd_underflow ) begin
log_cmd_underflowed <= 1'b1;
end else begin
log_cmd_underflowed <= log_cmd_underflowed;
end
if( log_cmd_data_count > log_cmd_peak_data_count ) begin
log_cmd_peak_data_count <= log_cmd_data_count;
end else begin
log_cmd_peak_data_count <= log_cmd_peak_data_count;
end
if( log_wr_count > log_wr_peak_count ) begin
log_wr_peak_count <= log_wr_count;
end else begin
log_wr_peak_count <= log_wr_peak_count;
end
end
end
wire nand_adr_updated_pulse;
reg nadr_up_d;
wire adrfifo_full, adrfifo_over, adrfifo_empty, adrfifo_rst;
wire adrfifo_rd_pulse;
wire [13:0] adrfifo_count;
wire [29:0] adrfifo_data;
wire log_adr_end;
reg nand_cs_clean;
reg nand_adr_up_clean;
always @(posedge bclk_dll) begin
nand_cs_clean <= nand_cs;
nand_adr_up_clean <= nand_adr_updated;
if( log_adr_end ) begin
nadr_up_d <= nand_adr_up_clean & !nand_cs_clean;
end else begin
nadr_up_d <= nand_adr_up_clean;
end
end
assign nand_adr_updated_pulse = log_adr_end ? (!nadr_up_d & (nand_adr_up_clean & !nand_cs_clean)) |
(nadr_up_d & !(nand_adr_up_clean & !nand_cs_clean)) :
(!nadr_up_d & nand_adr_up_clean);
reg [29:0] nand_adr_pipe;
reg nand_adr_updated_pulse_pipe;
always @(posedge bclk_dll) begin
nand_adr_pipe <= nand_adr;
nand_adr_updated_pulse_pipe <= nand_adr_updated_pulse;
end
nandadr_fifo nandadr_fifo(
.rst(adrfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_adr_pipe[29:0]),
.wr_en(nand_adr_updated_pulse_pipe),
.rd_en(adrfifo_rd_pulse),
.dout(adrfifo_data[29:0]),
.full(adrfifo_full),
.overflow(adrfifo_over),
.empty(adrfifo_empty),
.rd_data_count(adrfifo_count[13:0])
);
wire nand_cmd_updated_pulse;
reg ncmd_up_d;
wire cmdfifo_full, cmdfifo_over, cmdfifo_empty, cmdfifo_rst;
wire cmdfifo_rd_pulse;
wire [11:0] cmdfifo_count;
wire [7:0] cmdfifo_data;
always @(posedge bclk_dll) begin
ncmd_up_d <= nand_cmd_updated;
end
assign nand_cmd_updated_pulse = !ncmd_up_d && nand_cmd_updated;
uk_fifo cmd_fifo(
.rst(cmdfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_known_cmd[7:0]),
.wr_en(nand_cmd_updated_pulse),
.rd_en(cmdfifo_rd_pulse),
.dout(cmdfifo_data[7:0]),
.full(cmdfifo_full),
.overflow(cmdfifo_over),
.empty(cmdfifo_empty),
.rd_data_count(cmdfifo_count[11:0])
);
wire nand_uk_updated_pulse;
reg nuk_up_d;
wire ukfifo_full, ukfifo_over, ukfifo_empty, ukfifo_rst;
wire ukfifo_rd_pulse;
wire [11:0] ukfifo_count;
wire [7:0] ukfifo_data;
always @(posedge bclk_dll) begin
nuk_up_d <= nand_uk_updated;
end
assign nand_uk_updated_pulse = !nuk_up_d && nand_uk_updated;
uk_fifo uk_fifo(
.rst(ukfifo_rst),
.wr_clk(bclk_dll),
.rd_clk(bclk_dll),
.din(nand_uk_cmd[7:0]),
.wr_en(nand_uk_updated_pulse),
.rd_en(ukfifo_rd_pulse),
.dout(ukfifo_data[7:0]),
.full(ukfifo_full),
.overflow(ukfifo_over),
.empty(ukfifo_empty),
.rd_data_count(ukfifo_count[11:0])
);
assign gpioA_din[0] = F_LVDS_P4;
assign gpioA_din[1] = F_DX14;
assign gpioA_din[2] = F_LVDS_N2;
assign gpioA_din[3] = F_LVDS_N1;
assign gpioA_din[4] = F_LVDS_N4;
assign gpioA_din[5] = F_LVDS_P1;
assign F_LVDS_P4 = gpioA_dir[0] & nand_powered_on ? gpioA_dout[0] : 1'bZ;
assign F_DX14 = gpioA_dir[1] & nand_powered_on ? gpioA_dout[1] : 1'bZ;
assign F_LVDS_N2 = gpioA_dir[2] & nand_powered_on ? gpioA_dout[2] : 1'bZ;
assign F_LVDS_N1 = gpioA_dir[3] & nand_powered_on ? gpioA_dout[3] : 1'bZ;
assign F_LVDS_N4 = gpioA_dir[4] & nand_powered_on ? gpioA_dout[4] : 1'bZ;
assign F_LVDS_P1 = gpioA_dir[5] & nand_powered_on ? gpioA_dout[5] : 1'bZ;
reg cs0_r, rw_r;
reg [15:0] din_r;
reg [18:0] bus_addr_r;
reg adv_r;
reg cs0_in, rw_in, adv_in;
reg [15:0] din_in;
reg [2:0] a_in;
always @(posedge bclk_i) begin
cs0_in <= EIM_CS[0];
rw_in <= EIM_RW;
din_in <= eim_din;
adv_in <= !EIM_LBA;
a_in <= EIM_A[18:16];
cs0_r <= cs0_in;
rw_r <= rw_in;
din_r <= din_in;
adv_r <= adv_in;
end
always @(posedge bclk_i) begin
if( adv_in ) begin
bus_addr_r <= {a_in, din_in};
end else begin
bus_addr_r <= bus_addr_r;
end
end
wire [15:0] r40000wo;
wire [15:0] r40002wo;
wire [15:0] ro_d;
reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( r40000wo[15:0] ) );
reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d),
.reg_d( r40002wo[15:0] ) );
reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( gpioA_dout[15:0] ) );
reg_wo reg_wo_40012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40012),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( gpioA_dir[15:0] ) );
wire [1:0] dummy_40020;
reg_wo reg_wo_40020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40020),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {p2_wr_pulse_gate, dummy_40020[1:0], ddr3_p2_cmd_bl[5:0],
ddr3_p2_cmd_en, ddr3_p2_cmd_instr[2:0] } ) );
reg_wo reg_wo_40022 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40022),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_cmd_byte_addr[15:0] ) );
reg_wo reg_wo_40024 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40024),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_cmd_byte_addr[29:16] ) );
reg_wo reg_wo_40026 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40026),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {ddr3_p2_wr_en, ddr3_p2_wr_mask[3:0]} ) );
reg_wo reg_wo_40028 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40028),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_wr_data[15:0] ) );
reg_wo reg_wo_4002A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p2_wr_data[31:16] ) );
reg_r_det reg_det_4102A (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4002A),
.ena(!cs0_r && !rw_r),
.pulse( ddr3_p2_wr_pulse ) );
wire burst_mode;
wire [3:0] reg_40030_dummy;
reg_wo reg_wo_40030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40030),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {burst_mode, reg_40030_dummy[3:2], p3_rd_pulse_gate,
reg_40030_dummy[1:0], ddr3_p3_cmd_bl[5:0],
ddr3_p3_cmd_en, ddr3_p3_cmd_instr[2:0] } ) );
reg_wo reg_wo_40032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40032),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p3_cmd_byte_addr[15:0] ) );
reg_wo reg_wo_40034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40034),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( ddr3_p3_cmd_byte_addr[29:16] ) );
wire [3:0] ddr3_p3_dummy;
reg_wo reg_wo_40036 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40036),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {ddr3_p3_rd_en, ddr3_p3_dummy[3:0]} ) );
reg_wo reg_wo_40100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40100),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {rom_ddr3_reset, adrfifo_rst,
bypass_rb, cmdfifo_rst, ukfifo_rst, log_adr_end} ) );
reg_wo reg_wo_40102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40102),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {nand_powered_on} ) );
reg_wo reg_wo_40200 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40200),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {log_run, log_reset} ) );
reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40000wo[15:0] ) );
reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40002wo[15:0] ) );
reg_ro reg_ro_41004 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41004),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_calib_done, ddr3_dll_locked} ) );
reg_ro reg_ro_41010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41010),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( gpioA_din[15:0] ) );
reg_ro reg_ro_41020 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41020),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_p2_wr_count[6:0],
2'b00,
ddr3_p2_cmd_empty, ddr3_p2_cmd_full,
ddr3_p2_wr_full, ddr3_p2_wr_empty,
ddr3_p2_wr_underrun, ddr3_p2_wr_error} ) );
reg_ro reg_ro_41030 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41030),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_p3_rd_count[6:0],
2'b00,
ddr3_p3_cmd_empty, ddr3_p3_cmd_full,
ddr3_p3_rd_full, ddr3_p3_rd_empty,
ddr3_p3_rd_overflow, ddr3_p3_rd_error} ) );
reg_ro reg_ro_41032 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41032),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( ddr3_p3_rd_data[15:0] ) );
reg_ro reg_ro_41034 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( ddr3_p3_rd_data[31:16] ) );
reg_r_det reg_det_41034 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41034),
.ena(!cs0_r && rw_r),
.pulse( ddr3_p3_rd_pulse ) );
reg_ro reg_ro_41100 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {8'b0, ukfifo_data[7:0]} ) );
reg_r_det reg_det_41100 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41100),
.ena(!cs0_r && rw_r),
.pulse( ukfifo_rd_pulse ) );
reg_ro reg_ro_41102 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41102),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {1'b0, ukfifo_full, ukfifo_over, ukfifo_empty, ukfifo_count[11:0]} ) );
reg_ro reg_ro_41104 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {8'b0, cmdfifo_data[7:0]} ) );
reg_r_det reg_det_41104 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41104),
.ena(!cs0_r && rw_r),
.pulse( cmdfifo_rd_pulse ) );
reg_ro reg_ro_41106 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41106),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {1'b0, cmdfifo_full, cmdfifo_over, cmdfifo_empty, cmdfifo_count[11:0]} ) );
reg_ro reg_ro_41108 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41108),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {adrfifo_full, adrfifo_empty, adrfifo_count[13:0]} ) );
reg_ro reg_ro_4110A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110A),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {adrfifo_data[15:0]} ) );
reg_ro reg_ro_4110C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {2'b0,adrfifo_data[29:16]} ) );
reg_r_det reg_det_4110C (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110C),
.ena(!cs0_r && rw_r),
.pulse( adrfifo_rd_pulse ) );
reg_ro reg_ro_4110E ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4110E),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {page_addra_over_caught, outstanding_under_caught} ) );
reg_ro reg_ro_41110 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41110),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr3_rd_cmd_full, ddr3_rd_dat_en,
ddr3_rd_dat_full, ddr3_rd_dat_empty,
ddr3_rd_dat_count[6:0]} ) );
reg_ro reg_ro_41112 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41112),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {ddr_cstate[2:0], 1'b0,
ddr3_wr_cmd_full, ddr3_wr_dat_en,
ddr3_wr_full, ddr3_wr_empty,
ddr3_wr_dat_count[6:0]} ) );
reg_ro reg_ro_41200 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41200),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {log_wr_peak_count[6:0], log_cmd_peak_data_count[4:0],
log_cmd_overflowed, log_cmd_underflowed,
log_cmd_error, log_data_error} ) );
reg_ro reg_ro_41202 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41202),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( log_entries[15:0] ) );
reg_ro reg_ro_41204 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41204),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( log_entries[26:16] ) );
reg_ro reg_ro_41206 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41206),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[15:0] ) );
reg_ro reg_ro_41220 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41220),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {log_cmd_full, log_wr_full} ) );
reg_r_det_early reg_det_41206 (.clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41206),
.ena(!cs0_r && rw_r),
.pulse( time_t_update ) );
reg_ro reg_ro_41208 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41208),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[31:16] ) );
reg_ro reg_ro_4120A ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4120A),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[47:32] ) );
reg_ro reg_ro_4120C ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h4120C),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( time_t_bclk[63:48] ) );
wire [63:0] rC04_0000wo;
wire [63:0] rC04_0008wo;
wire [15:0] ro_d_b;
reg_wo_4burst reg_wo_4b_C04_0000( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_wo_4burst reg_wo_4b_C04_0008( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
wire [63:0] burst_ctl;
wire burst_stb;
reg_wo_4burst reg_wo_4b_C04_0100( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_0100),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_ctl[63:0] ), .rbk_d(ro_d_b), .strobe(burst_stb) );
reg_ro_4burst reg_ro_4b_C04_1000( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_ro_4burst reg_ro_4b_C04_1008( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
wire [63:0] burst_status;
reg_ro_4burst reg_ro_4b_C04_1108( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1108),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_status ), .rbk_d(ro_d_b) );
wire [63:0] burst_data;
wire burst_data_stb;
reg_ro_4burst reg_ro_4b_C04_1100( .clk(bclk_dll), .bus_ad(eim_din), .my_a(19'h4_1100),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( burst_data ), .rbk_d(ro_d_b), .strobe(burst_data_stb) );
reg_ro reg_ro_41FFC ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFC),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h001A ) );
reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h0001 ) );
reg [15:0] ro_d_r;
reg [15:0] ro_d_b_r;
reg [1:0] eim_rdcs;
reg [15:0] eim_dout_pipe;
reg [15:0] eim_dout_pipe2;
always @(posedge bclk_dll) begin
ro_d_r <= ro_d;
ro_d_b_r <= ro_d_b;
eim_rdcs[1:0] <= EIM_CS[1:0];
eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
end
always @(posedge bclk_o) begin
eim_dout_pipe2 <= eim_dout_pipe;
eim_dout <= eim_dout_pipe2;
end;
always @(posedge clk50) begin
counter <= counter + 1;
end
assign FPGA_LED2 = counter[23];
IBUFGDS clkibufgds( .I(CLK2_P), .IB(CLK2_N), .O(clk) );
assign eim_d_t = EIM_OE | !EIM_LBA;
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t), .O(eim_din[ 0]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t), .O(eim_din[ 1]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t), .O(eim_din[ 2]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t), .O(eim_din[ 3]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t), .O(eim_din[ 4]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t), .O(eim_din[ 5]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t), .O(eim_din[ 6]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t), .O(eim_din[ 7]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t), .O(eim_din[ 8]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t), .O(eim_din[ 9]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t), .O(eim_din[10]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t), .O(eim_din[11]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t), .O(eim_din[12]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t), .O(eim_din[13]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t), .O(eim_din[14]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t), .O(eim_din[15]));
wire c1_clk0, c1_rst0;
ddr3_clkgen ddr3_clkgen (
.clk50in(clk),
.clk50(clk50),
.clk400(ddr3clk),
.clk100(clk100),
.RESET(reset),
.LOCKED(ddr3_dll_locked)
);
wire p2_cmd_en_pulse, p2_wr_en_pulse, p3_cmd_en_pulse, p3_rd_en_pulse;
rising_edge p2cmdp2e( .clk(bclk_dll), .level(ddr3_p2_cmd_en), .pulse(p2_cmd_en_pulse) );
rising_edge p2wrp2e( .clk(bclk_dll), .level(ddr3_p2_wr_en), .pulse(p2_wr_en_pulse) );
rising_edge p3cmdp2e( .clk(bclk_dll), .level(ddr3_p3_cmd_en), .pulse(p3_cmd_en_pulse) );
rising_edge p2rdp2e( .clk(bclk_dll), .level(ddr3_p3_rd_en), .pulse(p3_rd_en_pulse) );
wire p2_cmd_en;
wire [2:0] p2_cmd_instr;
wire [5:0] p2_cmd_bl;
wire [29:0] p2_cmd_byte_addr;
wire p2_wr_en;
wire [3:0] p2_wr_mask;
wire [31:0] p2_wr_data;
reg log_cmd_en_delay;
always @(posedge bclk_dll) begin
log_cmd_en_delay <= !logbuf_empty && !logbuf_cmd_full;
end
assign p2_cmd_en = log_run ? log_cmd_en_delay : p2_cmd_en_pulse;
assign p2_cmd_instr[2:0] = log_run ? logbuf_cmd_instr[2:0] : ddr3_p2_cmd_instr[2:0];
assign p2_cmd_bl = log_run ? logbuf_cmd_burstlen : ddr3_p2_cmd_bl;
assign p2_cmd_byte_addr = log_run ? logbuf_cmd_addr : ddr3_p2_cmd_byte_addr;
assign p2_wr_en = log_run ? log_wr_en : (p2_wr_en_pulse || (ddr3_p2_wr_pulse & p2_wr_pulse_gate));
assign p2_wr_mask = log_run ? log_wr_mask : ddr3_p2_wr_mask;
assign p2_wr_data = log_run ? log_wr_data : ddr3_p2_wr_data;
wire p3_cmd_en;
wire p3_burst_cmd_en;
wire [2:0] p3_cmd_instr;
wire [2:0] p3_burst_cmd_instr;
wire [5:0] p3_cmd_bl;
wire [5:0] p3_burst_cmd_bl;
wire [29:0] p3_cmd_byte_addr;
wire [29:0] p3_burst_addr;
wire p3_rd_en;
wire p3_burst_rd_en;
assign p3_cmd_en = burst_mode ? p3_burst_cmd_en : p3_cmd_en_pulse;
assign p3_cmd_instr = burst_mode ? p3_burst_cmd_instr : ddr3_p3_cmd_instr;
assign p3_cmd_bl = burst_mode ? p3_burst_cmd_bl : ddr3_p3_cmd_bl;
assign p3_cmd_byte_addr = burst_mode ? p3_burst_addr : ddr3_p3_cmd_byte_addr;
assign p3_rd_en = burst_mode ? p3_burst_rd_en : (p3_rd_en_pulse || (ddr3_p3_rd_pulse & p3_rd_pulse_gate));
wire ddr3_reset_local;
ddr3_eim_cs1 cs1_adapter(.clk(bclk_dll),
.ctl(burst_ctl),
.ctl_stb(burst_stb),
.burst_rd(burst_data[63:0]),
.rd_stb(burst_data_stb),
.status(burst_status[63:0]),
.ddr3_rd_cmd(p3_burst_cmd_instr),
.ddr3_rd_bl(p3_burst_cmd_bl),
.ddr3_rd_adr(p3_burst_addr),
.ddr3_rd_cmd_en(p3_burst_cmd_en),
.ddr3_rd_cmd_empty(ddr3_p3_cmd_empty),
.ddr3_rd_cmd_full(ddr3_p3_cmd_full),
.ddr3_rd_data(ddr3_p3_rd_data[31:0]),
.ddr3_rd_count(ddr3_p3_rd_count),
.ddr3_rd_empty(ddr3_p3_rd_empty),
.ddr3_rd_full(ddr3_p3_rd_full),
.ddr3_rd_en(p3_burst_rd_en),
.reset(ddr3_reset_local)
);
sync_reset ddr3_res_sync( .glbl_reset(log_reset), .clk(ddr3clk), .reset(ddr3_reset_local) );
ddr3_if_4port # (
.C1_P0_MASK_SIZE(4),
.C1_P0_DATA_PORT_SIZE(32),
.C1_P1_MASK_SIZE(4),
.C1_P1_DATA_PORT_SIZE(32),
.DEBUG_EN(0),
.C1_MEMCLK_PERIOD(2500),
.C1_CALIB_SOFT_IP("TRUE"),
.C1_SIMULATION("FALSE"),
.C1_RST_ACT_LOW(0),
.C1_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C1_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
.C1_NUM_DQ_PINS(16),
.C1_MEM_ADDR_WIDTH(14),
.C1_MEM_BANKADDR_WIDTH(3)
)
u_ddr3_if (
.c1_sys_clk (ddr3clk),
.c1_sys_rst_i (reset),
.mcb1_dram_dq (F_DDR3_D[15:0]),
.mcb1_dram_a (F_DDR3_A[13:0]),
.mcb1_dram_ba (F_BA[2:0]),
.mcb1_dram_ras_n (F_RAS_N),
.mcb1_dram_cas_n (F_CAS_N),
.mcb1_dram_we_n (F_WE_N),
.mcb1_dram_odt (F_DDR3_ODT),
.mcb1_dram_cke (F_DDR3_CKE),
.mcb1_dram_ck (F_DDR3_CK_P),
.mcb1_dram_ck_n (F_DDR3_CK_N),
.mcb1_dram_dqs (F_LDQS_P),
.mcb1_dram_dqs_n (F_LDQS_N),
.mcb1_dram_udqs (F_UDQS_P),
.mcb1_dram_udqs_n (F_UDQS_N),
.mcb1_dram_udm (F_UDM),
.mcb1_dram_dm (F_LDM),
.mcb1_dram_reset_n (F_DDR3_RST_N),
.c1_clk0 (c1_clk0),
.c1_rst0 (c1_rst0),
.c1_calib_done (ddr3_calib_done),
.mcb1_rzq (F_DDR3_RZQ),
.mcb1_zio (F_DDR3_ZIO),
.c1_p2_cmd_clk (bclk_dll),
.c1_p2_cmd_en (p2_cmd_en),
.c1_p2_cmd_instr (p2_cmd_instr),
.c1_p2_cmd_bl (p2_cmd_bl),
.c1_p2_cmd_byte_addr (p2_cmd_byte_addr),
.c1_p2_cmd_empty (ddr3_p2_cmd_empty),
.c1_p2_cmd_full (ddr3_p2_cmd_full),
.c1_p2_wr_clk (bclk_dll),
.c1_p2_wr_en (p2_wr_en),
.c1_p2_wr_mask (p2_wr_mask),
.c1_p2_wr_data (p2_wr_data),
.c1_p2_wr_full (ddr3_p2_wr_full),
.c1_p2_wr_empty (ddr3_p2_wr_empty),
.c1_p2_wr_count (ddr3_p2_wr_count),
.c1_p2_wr_underrun (ddr3_p2_wr_underrun),
.c1_p2_wr_error (ddr3_p2_wr_error),
.c1_p3_cmd_clk (bclk_dll),
.c1_p3_cmd_en (p3_cmd_en),
.c1_p3_cmd_instr (p3_cmd_instr),
.c1_p3_cmd_bl (p3_cmd_bl),
.c1_p3_cmd_byte_addr (p3_cmd_byte_addr),
.c1_p3_cmd_empty (ddr3_p3_cmd_empty),
.c1_p3_cmd_full (ddr3_p3_cmd_full),
.c1_p3_rd_clk (bclk_dll),
.c1_p3_rd_en (p3_rd_en),
.c1_p3_rd_data (ddr3_p3_rd_data),
.c1_p3_rd_full (ddr3_p3_rd_full),
.c1_p3_rd_empty (ddr3_p3_rd_empty),
.c1_p3_rd_count (ddr3_p3_rd_count),
.c1_p3_rd_overflow (ddr3_p3_rd_overflow),
.c1_p3_rd_error (ddr3_p3_rd_error),
.c1_p4_cmd_clk (ddr3_wr_clk),
.c1_p4_cmd_en (ddr3_wr_cmd_en),
.c1_p4_cmd_instr (ddr3_wr_cmd_instr[2:0]),
.c1_p4_cmd_bl (ddr3_wr_cmd_bl[5:0]),
.c1_p4_cmd_byte_addr (ddr3_wr_adr[29:0]),
.c1_p4_cmd_empty (ddr3_wr_cmd_empty),
.c1_p4_cmd_full (ddr3_wr_cmd_full),
.c1_p4_wr_clk (ddr3_wr_clk),
.c1_p4_wr_en (ddr3_wr_dat_en),
.c1_p4_wr_mask (ddr3_wr_mask[3:0]),
.c1_p4_wr_data (ddr3_wr_dat[31:0]),
.c1_p4_wr_full (ddr3_wr_full),
.c1_p4_wr_empty (ddr3_wr_empty),
.c1_p4_wr_count (ddr3_wr_dat_count[6:0]),
.c1_p5_cmd_clk (ddr3_rd_clk),
.c1_p5_cmd_en (ddr3_rd_cmd_en),
.c1_p5_cmd_instr (ddr3_rd_cmd_instr[2:0]),
.c1_p5_cmd_bl (ddr3_rd_cmd_bl[5:0]),
.c1_p5_cmd_byte_addr (ddr3_rd_adr[29:0]),
.c1_p5_cmd_full (ddr3_rd_cmd_full),
.c1_p5_rd_clk (ddr3_rd_clk),
.c1_p5_rd_en (ddr3_rd_dat_en),
.c1_p5_rd_data (ddr3_rd_dat[31:0]),
.c1_p5_rd_full (ddr3_rd_dat_full),
.c1_p5_rd_empty (ddr3_rd_dat_empty),
.c1_p5_rd_count (ddr3_rd_dat_count[6:0]),
.c1_p5_rd_overflow (ddr3_rd_dat_overflow)
);
assign APOPTOSIS = 1'b0;
assign ECSPI3_MISO = 1'b0;
endmodule | 4 |
3,173 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_ro.v | 10,301,314 | reg_ro.v | v | 25 | 52 | [] | [] | [] | [(1, 24)] | null | data/verilator_xmls/2f65b9a7-8f37-48aa-bf71-19d4bca4cbbc.xml | null | 952 | module | module reg_ro(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire [15:0] reg_d,
input wire re,
output reg [15:0] bus_d
);
reg [15:0] state;
always @(posedge clk) begin
state <= reg_d;
end
always @(bus_a or my_a or re) begin
if( (bus_a[18:1] == my_a[18:1]) && re ) begin
bus_d = state;
end else begin
bus_d = 16'hZZZZ;
end
end
endmodule | module reg_ro(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire [15:0] reg_d,
input wire re,
output reg [15:0] bus_d
); |
reg [15:0] state;
always @(posedge clk) begin
state <= reg_d;
end
always @(bus_a or my_a or re) begin
if( (bus_a[18:1] == my_a[18:1]) && re ) begin
bus_d = state;
end else begin
bus_d = 16'hZZZZ;
end
end
endmodule | 4 |
3,175 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_r_det_early.v | 10,301,314 | reg_r_det_early.v | v | 33 | 74 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/3480a8c0-9940-49fc-a51c-4fe9bfe727b8.xml | null | 955 | module | module reg_r_det_early(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire ena,
output wire pulse
);
reg gotread, gotread_d;
reg [7:0] state;
always @(posedge clk) begin
if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
gotread <= 1'b1;
end else begin
gotread <= 1'b0;
end
end
always @(posedge clk) begin
gotread_d <= gotread;
end
assign pulse = !gotread_d && gotread;
endmodule | module reg_r_det_early(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire ena,
output wire pulse
); |
reg gotread, gotread_d;
reg [7:0] state;
always @(posedge clk) begin
if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
gotread <= 1'b1;
end else begin
gotread <= 1'b0;
end
end
always @(posedge clk) begin
gotread_d <= gotread;
end
assign pulse = !gotread_d && gotread;
endmodule | 4 |
3,177 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_wo_4burst.v | 10,301,314 | reg_wo_4burst.v | v | 107 | 83 | [] | [] | [] | [(1, 105)] | null | null | 1: b'%Warning-CMPCONST: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_wo_4burst.v:46: Comparison is constant due to limited range\n : ... In instance reg_wo_4burst\n if( bcount <= 3\'b111 ) begin \n ^~\n ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 957 | module | module reg_wo_4burst(
input wire clk,
input wire [15:0] bus_ad,
input wire [18:0] my_a,
input wire [2:0] bus_a,
input wire adv,
input wire rw,
input wire cs,
output wire [63:0] reg_d,
output reg [15:0] rbk_d,
output wire strobe
);
reg [63:0] bstate;
reg [2:0] bcount;
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
reg activated_d;
always @(posedge clk) begin
activated_d <= activated;
end
assign strobe = activated_d & !activated;
always @(posedge clk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r} == my_a) ) begin
activated <= 1'b1;
bcount <= 3'b0;
end else if( !cs_r ) begin
activated <= 1'b0;
bcount <= 3'b0;
end else begin
activated <= activated;
if( bcount <= 3'b111 ) begin
bcount <= bcount + 3'b01;
end else begin
bcount <= bcount;
end
end
end
always @(posedge clk) begin
if( activated && !rw_r ) begin
case (bcount)
3'b00: begin
bstate[15:0] <= bus_ad_r;
end
3'b01: begin
bstate[31:16] <= bus_ad_r;
end
3'b10: begin
bstate[47:32] <= bus_ad_r;
end
3'b11: begin
bstate[63:48] <= bus_ad_r;
end
default: begin
bstate <= bstate;
end
endcase
end else begin
bstate <= bstate;
end
end
assign reg_d = bstate;
always @(activated or bcount or rw_r or bstate) begin
if( activated && rw_r ) begin
case (bcount)
3'b0001: begin
rbk_d = bstate[15:0];
end
3'b010: begin
rbk_d = bstate[31:16];
end
3'b011: begin
rbk_d = bstate[47:32];
end
3'b100: begin
rbk_d = bstate[63:48];
end
default: begin
rbk_d = 16'hZZZZ;
end
endcase
end else begin
rbk_d = 16'hZZZZ;
end
end
endmodule | module reg_wo_4burst(
input wire clk,
input wire [15:0] bus_ad,
input wire [18:0] my_a,
input wire [2:0] bus_a,
input wire adv,
input wire rw,
input wire cs,
output wire [63:0] reg_d,
output reg [15:0] rbk_d,
output wire strobe
); |
reg [63:0] bstate;
reg [2:0] bcount;
reg activated;
reg [15:0] bus_ad_r;
reg cs_r;
reg [2:0] bus_a_r;
reg rw_r;
reg adv_r;
reg activated_d;
always @(posedge clk) begin
activated_d <= activated;
end
assign strobe = activated_d & !activated;
always @(posedge clk) begin
bus_ad_r <= bus_ad;
bus_a_r <= bus_a;
cs_r <= cs;
rw_r <= rw;
adv_r <= adv;
if( cs_r && adv_r && ({bus_a_r, bus_ad_r} == my_a) ) begin
activated <= 1'b1;
bcount <= 3'b0;
end else if( !cs_r ) begin
activated <= 1'b0;
bcount <= 3'b0;
end else begin
activated <= activated;
if( bcount <= 3'b111 ) begin
bcount <= bcount + 3'b01;
end else begin
bcount <= bcount;
end
end
end
always @(posedge clk) begin
if( activated && !rw_r ) begin
case (bcount)
3'b00: begin
bstate[15:0] <= bus_ad_r;
end
3'b01: begin
bstate[31:16] <= bus_ad_r;
end
3'b10: begin
bstate[47:32] <= bus_ad_r;
end
3'b11: begin
bstate[63:48] <= bus_ad_r;
end
default: begin
bstate <= bstate;
end
endcase
end else begin
bstate <= bstate;
end
end
assign reg_d = bstate;
always @(activated or bcount or rw_r or bstate) begin
if( activated && rw_r ) begin
case (bcount)
3'b0001: begin
rbk_d = bstate[15:0];
end
3'b010: begin
rbk_d = bstate[31:16];
end
3'b011: begin
rbk_d = bstate[47:32];
end
3'b100: begin
rbk_d = bstate[63:48];
end
default: begin
rbk_d = 16'hZZZZ;
end
endcase
end else begin
rbk_d = 16'hZZZZ;
end
end
endmodule | 4 |
3,178 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_w_det.v | 10,301,314 | reg_w_det.v | v | 35 | 94 | [] | [] | [] | [(1, 31)] | null | null | 1: b"%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/reg_w_det.v:29: Can't find definition of variable: 'bitmask'\n assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 958 | module | module reg_w_det(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire [15:0] bus_d,
input wire ena,
input wire [7:0] trigger,
output wire pulse
);
reg gotwrite, gotwrite_d;
reg [7:0] state;
always @(posedge clk) begin
if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
state <= bus_d;
gotwrite <= 1'b0;
end else begin
state <= state;
gotwrite <= 1'b1;
end
end
always @(posedge clk) begin
gotwrite_d <= gotwrite;
end
assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);
endmodule | module reg_w_det(
input wire clk,
input wire [18:0] bus_a,
input wire [18:0] my_a,
input wire [15:0] bus_d,
input wire ena,
input wire [7:0] trigger,
output wire pulse
); |
reg gotwrite, gotwrite_d;
reg [7:0] state;
always @(posedge clk) begin
if( (bus_a[18:1] == my_a[18:1]) && ena ) begin
state <= bus_d;
gotwrite <= 1'b0;
end else begin
state <= state;
gotwrite <= 1'b1;
end
end
always @(posedge clk) begin
gotwrite_d <= gotwrite;
end
assign pulse = (state == bitmask) && (!gotwrite_d && gotwrite);
endmodule | 4 |
3,180 | data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/sync_reset.v | 10,301,314 | sync_reset.v | v | 62 | 90 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(46, 61)] | null | null | 1: b"%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/sync_reset.v:54: Cannot find file containing module: 'FDPE'\n FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) );\n ^~~~\n ... Looked in:\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common,data/full_repos/permissive/10301314/FDPE\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common,data/full_repos/permissive/10301314/FDPE.v\n data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common,data/full_repos/permissive/10301314/FDPE.sv\n FDPE\n FDPE.v\n FDPE.sv\n obj_dir/FDPE\n obj_dir/FDPE.v\n obj_dir/FDPE.sv\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/sync_reset.v:55: Cannot find file containing module: 'FDPE'\n FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) );\n ^~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/sync_reset.v:56: Cannot find file containing module: 'FDPE'\n FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) );\n ^~~~\n%Error: data/full_repos/permissive/10301314/novena-sd.srcs/sources_1/imports/common/sync_reset.v:57: Cannot find file containing module: 'FDPE'\n FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) );\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 960 | module | module sync_reset (
input wire glbl_reset,
input wire clk,
output wire reset
);
wire [3:0] reschain;
FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) );
FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) );
FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) );
FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) );
assign reset = reschain[3];
endmodule | module sync_reset (
input wire glbl_reset,
input wire clk,
output wire reset
); |
wire [3:0] reschain;
FDPE fdres0( .Q(reschain[0]), .C(clk), .CE(1'b1), .D(1'b0), .PRE(glbl_reset) );
FDPE fdres1( .Q(reschain[1]), .C(clk), .CE(1'b1), .D(reschain[0]), .PRE(glbl_reset) );
FDPE fdres2( .Q(reschain[2]), .C(clk), .CE(1'b1), .D(reschain[1]), .PRE(glbl_reset) );
FDPE fdres3( .Q(reschain[3]), .C(clk), .CE(1'b1), .D(reschain[2]), .PRE(glbl_reset) );
assign reset = reschain[3];
endmodule | 4 |
3,181 | data/full_repos/permissive/103021115/src/counter.v | 103,021,115 | counter.v | v | 116 | 57 | [] | [] | [] | [(9, 115)] | null | data/verilator_xmls/fef8be64-f74a-4c6a-8170-14933bc80c20.xml | null | 976 | module | module Counter7SD(
clock,
reset,
pause,
reverse,
data
);
input clock;
input reset;
input pause;
input reverse;
output reg [6:0] data;
reg [6:0] temp_data;
parameter ZERO = 7'b1111110;
parameter ONE = 7'b0110000;
parameter TWO = 7'b1101101;
parameter THREE = 7'b1101101;
parameter FOUR = 7'b0110011;
parameter FIVE = 7'b1011011;
parameter SIX = 7'b1011011;
parameter SEVEN = 7'b1110000;
parameter EIGHT = 7'b1111111;
parameter NINE = 7'b1111011;
parameter PAUSE = 7'b1100111;
parameter HOLD = 7'b0110111;
always @ ( posedge clock ) begin
if (pause==0)
data <= PAUSE;
else
data <= temp_data;
case(reset)
0: temp_data <= HOLD;
1: case (pause)
0: temp_data <= temp_data;
default: case (temp_data)
HOLD: case (reverse)
0: temp_data <= ZERO;
default: temp_data <= NINE;
endcase
ZERO: case (reverse)
0: temp_data <= ONE;
default: temp_data <= NINE;
endcase
ONE: case (reverse)
0: temp_data <= TWO;
default: temp_data <= ZERO;
endcase
TWO: case (reverse)
0: temp_data <= THREE;
default: temp_data <= ONE;
endcase
THREE: case (reverse)
0: temp_data <= FOUR;
default: temp_data <= TWO;
endcase
FOUR: case (reverse)
0: temp_data <= FIVE;
default: temp_data <= THREE;
endcase
FIVE: case (reverse)
0: temp_data <= SIX;
default: temp_data <= FOUR;
endcase
SIX: case (reverse)
0: temp_data <= SEVEN;
default: temp_data <= FIVE;
endcase
SEVEN: case (reverse)
0: temp_data <= EIGHT;
default: temp_data <= SIX;
endcase
EIGHT: case (reverse)
0: temp_data <= NINE;
default: temp_data <= SEVEN;
endcase
NINE: case (reverse)
0: temp_data <= ZERO;
default: temp_data <= EIGHT;
endcase
default:temp_data <= HOLD;
endcase
endcase
endcase
end
endmodule | module Counter7SD(
clock,
reset,
pause,
reverse,
data
); |
input clock;
input reset;
input pause;
input reverse;
output reg [6:0] data;
reg [6:0] temp_data;
parameter ZERO = 7'b1111110;
parameter ONE = 7'b0110000;
parameter TWO = 7'b1101101;
parameter THREE = 7'b1101101;
parameter FOUR = 7'b0110011;
parameter FIVE = 7'b1011011;
parameter SIX = 7'b1011011;
parameter SEVEN = 7'b1110000;
parameter EIGHT = 7'b1111111;
parameter NINE = 7'b1111011;
parameter PAUSE = 7'b1100111;
parameter HOLD = 7'b0110111;
always @ ( posedge clock ) begin
if (pause==0)
data <= PAUSE;
else
data <= temp_data;
case(reset)
0: temp_data <= HOLD;
1: case (pause)
0: temp_data <= temp_data;
default: case (temp_data)
HOLD: case (reverse)
0: temp_data <= ZERO;
default: temp_data <= NINE;
endcase
ZERO: case (reverse)
0: temp_data <= ONE;
default: temp_data <= NINE;
endcase
ONE: case (reverse)
0: temp_data <= TWO;
default: temp_data <= ZERO;
endcase
TWO: case (reverse)
0: temp_data <= THREE;
default: temp_data <= ONE;
endcase
THREE: case (reverse)
0: temp_data <= FOUR;
default: temp_data <= TWO;
endcase
FOUR: case (reverse)
0: temp_data <= FIVE;
default: temp_data <= THREE;
endcase
FIVE: case (reverse)
0: temp_data <= SIX;
default: temp_data <= FOUR;
endcase
SIX: case (reverse)
0: temp_data <= SEVEN;
default: temp_data <= FIVE;
endcase
SEVEN: case (reverse)
0: temp_data <= EIGHT;
default: temp_data <= SIX;
endcase
EIGHT: case (reverse)
0: temp_data <= NINE;
default: temp_data <= SEVEN;
endcase
NINE: case (reverse)
0: temp_data <= ZERO;
default: temp_data <= EIGHT;
endcase
default:temp_data <= HOLD;
endcase
endcase
endcase
end
endmodule | 0 |
3,182 | data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v | 103,021,115 | tb_simple_counter_sim.v | v | 33 | 49 | [] | [] | [] | null | line:30: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clock = ~ clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:15: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("out.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:16: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,simple_sim);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:23: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:24: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:25: Unsupported: Ignoring delay on this delayed statement.\n #50 pause = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:26: Unsupported: Ignoring delay on this delayed statement.\n #50 pause = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_counter_sim.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10 $finish;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 978 | module | module simple_sim ();
reg clock;
reg reset;
reg pause;
reg reverse;
wire [6:0] data;
Counter7SD C7SD(clock,reset,pause,reverse,data);
always #3 clock = ~ clock;
initial
begin
$dumpfile("out.vcd");
$dumpvars(0,simple_sim);
end
initial begin
clock = 1;
#5 reset = 0;
#5 reset = 1;
#50 pause = 0;
#50 pause = 1;
#100 reset = 0;
#10 $finish;
end
endmodule | module simple_sim (); |
reg clock;
reg reset;
reg pause;
reg reverse;
wire [6:0] data;
Counter7SD C7SD(clock,reset,pause,reverse,data);
always #3 clock = ~ clock;
initial
begin
$dumpfile("out.vcd");
$dumpvars(0,simple_sim);
end
initial begin
clock = 1;
#5 reset = 0;
#5 reset = 1;
#50 pause = 0;
#50 pause = 1;
#100 reset = 0;
#10 $finish;
end
endmodule | 0 |
3,183 | data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v | 103,021,115 | tb_simple_task_counter_sim.v | v | 44 | 65 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:12: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("sim/waveform/out.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:13: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,simple_sim);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:17: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clock = ~ clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:34: syntax error, unexpected \'@\'\n @(posedge clock)\n ^\n%Error: data/full_repos/permissive/103021115/tb/tb_simple_task_counter_sim.v:36: syntax error, unexpected \'@\'\n repeat(12)@(posedge clock)\n ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 979 | module | module simple_sim ();
reg clock;
reg reset;
reg pause;
reg reverse;
wire [6:0] data;
Counter7SD C7SD(clock,reset,pause,reverse,data);
initial
begin
$dumpfile("sim/waveform/out.vcd");
$dumpvars(0,simple_sim);
$display("clock\treset\tpause\treverse\tdata");
end
always #5 clock = ~ clock;
always @ ( clock ) begin
$display("%b\t%b\t%b\t%b\t%b",clock,reset,pause,reverse,data);
end
initial begin
start;
simple_flow;
$finish;
end
task start;
clock = 1;
endtask
task simple_flow; begin
@(posedge clock)
reset = 0;
repeat(12)@(posedge clock)
reset = 1;
@(posedge clock)
#10;
end
endtask
endmodule | module simple_sim (); |
reg clock;
reg reset;
reg pause;
reg reverse;
wire [6:0] data;
Counter7SD C7SD(clock,reset,pause,reverse,data);
initial
begin
$dumpfile("sim/waveform/out.vcd");
$dumpvars(0,simple_sim);
$display("clock\treset\tpause\treverse\tdata");
end
always #5 clock = ~ clock;
always @ ( clock ) begin
$display("%b\t%b\t%b\t%b\t%b",clock,reset,pause,reverse,data);
end
initial begin
start;
simple_flow;
$finish;
end
task start;
clock = 1;
endtask
task simple_flow; begin
@(posedge clock)
reset = 0;
repeat(12)@(posedge clock)
reset = 1;
@(posedge clock)
#10;
end
endtask
endmodule | 0 |
3,185 | data/full_repos/permissive/103257524/sim/sim_memory.v | 103,257,524 | sim_memory.v | v | 105 | 122 | [] | [] | [] | [(23, 104)] | null | null | 1: b'%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:36: Cannot find file containing module: \'uart_comm\'\n uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.v\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.sv\n uart_comm\n uart_comm.v\n uart_comm.sv\n obj_dir/uart_comm\n obj_dir/uart_comm.v\n obj_dir/uart_comm.sv\n%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:71: Cannot find file containing module: \'multchan_comm\'\n multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/103257524/sim/sim_memory.v:88: Operator ASSIGNDLY expects 72 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'getDWORD\' generates 32 bits.\n : ... In instance sim_memory\n write_data <= getDWORD(read_data[31:0]);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 981 | module | module sim_memory(
input CLK,
input RST,
output Tx,
input Rx
);
wire send_flag;
wire [7:0] send_data;
wire recv_flag;
wire [7:0] recv_data;
wire recvable, sendable;
uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);
reg read_flag;
wire [4:0] read_data_length;
wire [71:0] read_data;
reg write_flag;
reg [4:0] write_data_length;
reg [71:0] write_data;
wire readable;
wire writable;
wire _trash, _trash2;
reg [7:0] memory[2047:0];
reg [7:0] memory_stack[2047:0];
integer i;
initial begin
for(i=0;i<2048;i=i+1) begin
memory[i] = 0;
memory_stack[i] = 0;
end
$readmemh("D:\\Project\\Vivado\\mips_cpu\\testcase\\mips.data", memory);
end
function [31:0] getDWORD;
input [31:0] addr;
getDWORD = {memory[addr+3], memory[addr+2], memory[addr+1], memory[addr]};
endfunction
function [15:0] getWORD;
input [31:0] addr;
getWORD = {memory[addr+1], memory[addr]};
endfunction
multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(
CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable,
{1'b0, read_flag}, {read_data_length, read_data},
{1'b0, write_flag}, {write_data_length, write_data},
{_trash, readable}, {_trash2, writable});
always @(posedge CLK or posedge RST) begin
read_flag <= 0;
write_flag <= 0;
if(RST) begin
write_data <= 0;
end else begin
if(readable) begin
read_flag <= 1;
if(read_data_length == 5 && read_data[32] == 0) begin
$display("GET READ REQUEST, ADDR = 0x%x DATA = %x", read_data[31:0], getDWORD(read_data[31:0]));
write_flag <= 1;
write_data <= getDWORD(read_data[31:0]);
write_data_length <= 4;
end else begin
$display("GET WRITE REQUEST, ADDR = 0x%x DATA = %x MASK = %d", read_data[63:32], read_data[31:0], read_data[67:64]);
if(read_data[64])
memory[read_data[63:32]] <= read_data[7:0];
if(read_data[65])
memory[read_data[63:32]+1] <= read_data[15:8];
if(read_data[66])
memory[read_data[63:32]+2] <= read_data[23:16];
if(read_data[67])
memory[read_data[63:32]+3] <= read_data[31:24];
end
end
end
end
endmodule | module sim_memory(
input CLK,
input RST,
output Tx,
input Rx
); |
wire send_flag;
wire [7:0] send_data;
wire recv_flag;
wire [7:0] recv_data;
wire recvable, sendable;
uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);
reg read_flag;
wire [4:0] read_data_length;
wire [71:0] read_data;
reg write_flag;
reg [4:0] write_data_length;
reg [71:0] write_data;
wire readable;
wire writable;
wire _trash, _trash2;
reg [7:0] memory[2047:0];
reg [7:0] memory_stack[2047:0];
integer i;
initial begin
for(i=0;i<2048;i=i+1) begin
memory[i] = 0;
memory_stack[i] = 0;
end
$readmemh("D:\\Project\\Vivado\\mips_cpu\\testcase\\mips.data", memory);
end
function [31:0] getDWORD;
input [31:0] addr;
getDWORD = {memory[addr+3], memory[addr+2], memory[addr+1], memory[addr]};
endfunction
function [15:0] getWORD;
input [31:0] addr;
getWORD = {memory[addr+1], memory[addr]};
endfunction
multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(
CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable,
{1'b0, read_flag}, {read_data_length, read_data},
{1'b0, write_flag}, {write_data_length, write_data},
{_trash, readable}, {_trash2, writable});
always @(posedge CLK or posedge RST) begin
read_flag <= 0;
write_flag <= 0;
if(RST) begin
write_data <= 0;
end else begin
if(readable) begin
read_flag <= 1;
if(read_data_length == 5 && read_data[32] == 0) begin
$display("GET READ REQUEST, ADDR = 0x%x DATA = %x", read_data[31:0], getDWORD(read_data[31:0]));
write_flag <= 1;
write_data <= getDWORD(read_data[31:0]);
write_data_length <= 4;
end else begin
$display("GET WRITE REQUEST, ADDR = 0x%x DATA = %x MASK = %d", read_data[63:32], read_data[31:0], read_data[67:64]);
if(read_data[64])
memory[read_data[63:32]] <= read_data[7:0];
if(read_data[65])
memory[read_data[63:32]+1] <= read_data[15:8];
if(read_data[66])
memory[read_data[63:32]+2] <= read_data[23:16];
if(read_data[67])
memory[read_data[63:32]+3] <= read_data[31:24];
end
end
end
end
endmodule | 50 |
3,186 | data/full_repos/permissive/103257524/sim/sim_memory.v | 103,257,524 | sim_memory.v | v | 105 | 122 | [] | [] | [] | [(23, 104)] | null | null | 1: b'%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:36: Cannot find file containing module: \'uart_comm\'\n uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.v\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.sv\n uart_comm\n uart_comm.v\n uart_comm.sv\n obj_dir/uart_comm\n obj_dir/uart_comm.v\n obj_dir/uart_comm.sv\n%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:71: Cannot find file containing module: \'multchan_comm\'\n multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/103257524/sim/sim_memory.v:88: Operator ASSIGNDLY expects 72 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'getDWORD\' generates 32 bits.\n : ... In instance sim_memory\n write_data <= getDWORD(read_data[31:0]);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 981 | function | function [31:0] getDWORD;
input [31:0] addr;
getDWORD = {memory[addr+3], memory[addr+2], memory[addr+1], memory[addr]};
endfunction | function [31:0] getDWORD; |
input [31:0] addr;
getDWORD = {memory[addr+3], memory[addr+2], memory[addr+1], memory[addr]};
endfunction | 50 |
3,187 | data/full_repos/permissive/103257524/sim/sim_memory.v | 103,257,524 | sim_memory.v | v | 105 | 122 | [] | [] | [] | [(23, 104)] | null | null | 1: b'%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:36: Cannot find file containing module: \'uart_comm\'\n uart_comm #(.BAUDRATE(5000000)) uart(CLK, RST, send_flag, send_data, recv_flag, recv_data, sendable, recvable, Tx, Rx);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.v\n data/full_repos/permissive/103257524/sim,data/full_repos/permissive/103257524/uart_comm.sv\n uart_comm\n uart_comm.v\n uart_comm.sv\n obj_dir/uart_comm\n obj_dir/uart_comm.v\n obj_dir/uart_comm.sv\n%Error: data/full_repos/permissive/103257524/sim/sim_memory.v:71: Cannot find file containing module: \'multchan_comm\'\n multchan_comm #(.CHANNEL_BIT(1), .MESSAGE_BIT(72)) comm(\n ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/103257524/sim/sim_memory.v:88: Operator ASSIGNDLY expects 72 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'getDWORD\' generates 32 bits.\n : ... In instance sim_memory\n write_data <= getDWORD(read_data[31:0]);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 981 | function | function [15:0] getWORD;
input [31:0] addr;
getWORD = {memory[addr+1], memory[addr]};
endfunction | function [15:0] getWORD; |
input [31:0] addr;
getWORD = {memory[addr+1], memory[addr]};
endfunction | 50 |
3,195 | data/full_repos/permissive/103257524/src/cpu/cpu.v | 103,257,524 | cpu.v | v | 120 | 88 | [] | [] | [] | [(23, 119)] | null | null | 1: b"%Error: data/full_repos/permissive/103257524/src/cpu/cpu.v:46: Cannot find file containing module: 'clk_wiz_0'\n clk_wiz_0 clk(CLK, 1'b0, EXCLK);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/clk_wiz_0\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/clk_wiz_0.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/clk_wiz_0.sv\n clk_wiz_0\n clk_wiz_0.v\n clk_wiz_0.sv\n obj_dir/clk_wiz_0\n obj_dir/clk_wiz_0.v\n obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu.v:65: Cannot find file containing module: 'uart_comm'\n uart_comm #(.BAUDRATE(5000000 ), .CLOCKRATE(66667000)) UART(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu.v:85: Cannot find file containing module: 'multchan_comm'\n multchan_comm #(.MESSAGE_BIT(MESSAGE_BIT), .CHANNEL_BIT(CHANNEL_BIT)) COMM(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu.v:105: Cannot find file containing module: 'memory_controller'\n memory_controller MEM_CTRL(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu.v:114: Cannot find file containing module: 'cpu_core'\n cpu_core CORE(\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 986 | module | module cpu(
input EXCLK,
input button,
output Tx,
input Rx
);
reg RST;
reg RST_delay;
wire CLK;
clk_wiz_0 clk(CLK, 1'b0, EXCLK);
always @(posedge CLK or posedge button) begin
if(button) begin
RST <= 1;
RST_delay <= 1;
end else begin
RST_delay <= 0;
RST <= RST_delay;
end
end
wire UART_send_flag;
wire [7:0] UART_send_data;
wire UART_recv_flag;
wire [7:0] UART_recv_data;
wire UART_sendable;
wire UART_receivable;
uart_comm #(.BAUDRATE(5000000), .CLOCKRATE(66667000)) UART(
CLK, RST,
UART_send_flag, UART_send_data,
UART_recv_flag, UART_recv_data,
UART_sendable, UART_receivable,
Tx, Rx);
localparam CHANNEL_BIT = 1;
localparam MESSAGE_BIT = 72;
localparam CHANNEL = 1 << CHANNEL_BIT;
wire COMM_read_flag[CHANNEL-1:0];
wire [MESSAGE_BIT-1:0] COMM_read_data[CHANNEL-1:0];
wire [4:0] COMM_read_length[CHANNEL-1:0];
wire COMM_write_flag[CHANNEL-1:0];
wire [MESSAGE_BIT-1:0] COMM_write_data[CHANNEL-1:0];
wire [4:0] COMM_write_length[CHANNEL-1:0];
wire COMM_readable[CHANNEL-1:0];
wire COMM_writable[CHANNEL-1:0];
multchan_comm #(.MESSAGE_BIT(MESSAGE_BIT), .CHANNEL_BIT(CHANNEL_BIT)) COMM(
CLK, RST,
UART_send_flag, UART_send_data,
UART_recv_flag, UART_recv_data,
UART_sendable, UART_receivable,
{COMM_read_flag[1], COMM_read_flag[0]},
{COMM_read_length[1], COMM_read_data[1], COMM_read_length[0], COMM_read_data[0]},
{COMM_write_flag[1], COMM_write_flag[0]},
{COMM_write_length[1], COMM_write_data[1], COMM_write_length[0], COMM_write_data[0]},
{COMM_readable[1], COMM_readable[0]},
{COMM_writable[1], COMM_writable[0]});
wire [2*2-1:0] MEM_rw_flag;
wire [2*32-1:0] MEM_addr;
wire [2*32-1:0] MEM_read_data;
wire [2*32-1:0] MEM_write_data;
wire [2*4-1:0] MEM_write_mask;
wire [1:0] MEM_busy;
wire [1:0] MEM_done;
memory_controller MEM_CTRL(
CLK, RST,
COMM_write_flag[0], COMM_write_data[0], COMM_write_length[0],
COMM_read_flag[0], COMM_read_data[0], COMM_read_length[0],
COMM_writable[0], COMM_readable[0],
MEM_rw_flag, MEM_addr,
MEM_read_data, MEM_write_data, MEM_write_mask,
MEM_busy, MEM_done);
cpu_core CORE(
CLK, RST,
MEM_rw_flag, MEM_addr,
MEM_read_data, MEM_write_data, MEM_write_mask,
MEM_busy, MEM_done);
endmodule | module cpu(
input EXCLK,
input button,
output Tx,
input Rx
); |
reg RST;
reg RST_delay;
wire CLK;
clk_wiz_0 clk(CLK, 1'b0, EXCLK);
always @(posedge CLK or posedge button) begin
if(button) begin
RST <= 1;
RST_delay <= 1;
end else begin
RST_delay <= 0;
RST <= RST_delay;
end
end
wire UART_send_flag;
wire [7:0] UART_send_data;
wire UART_recv_flag;
wire [7:0] UART_recv_data;
wire UART_sendable;
wire UART_receivable;
uart_comm #(.BAUDRATE(5000000), .CLOCKRATE(66667000)) UART(
CLK, RST,
UART_send_flag, UART_send_data,
UART_recv_flag, UART_recv_data,
UART_sendable, UART_receivable,
Tx, Rx);
localparam CHANNEL_BIT = 1;
localparam MESSAGE_BIT = 72;
localparam CHANNEL = 1 << CHANNEL_BIT;
wire COMM_read_flag[CHANNEL-1:0];
wire [MESSAGE_BIT-1:0] COMM_read_data[CHANNEL-1:0];
wire [4:0] COMM_read_length[CHANNEL-1:0];
wire COMM_write_flag[CHANNEL-1:0];
wire [MESSAGE_BIT-1:0] COMM_write_data[CHANNEL-1:0];
wire [4:0] COMM_write_length[CHANNEL-1:0];
wire COMM_readable[CHANNEL-1:0];
wire COMM_writable[CHANNEL-1:0];
multchan_comm #(.MESSAGE_BIT(MESSAGE_BIT), .CHANNEL_BIT(CHANNEL_BIT)) COMM(
CLK, RST,
UART_send_flag, UART_send_data,
UART_recv_flag, UART_recv_data,
UART_sendable, UART_receivable,
{COMM_read_flag[1], COMM_read_flag[0]},
{COMM_read_length[1], COMM_read_data[1], COMM_read_length[0], COMM_read_data[0]},
{COMM_write_flag[1], COMM_write_flag[0]},
{COMM_write_length[1], COMM_write_data[1], COMM_write_length[0], COMM_write_data[0]},
{COMM_readable[1], COMM_readable[0]},
{COMM_writable[1], COMM_writable[0]});
wire [2*2-1:0] MEM_rw_flag;
wire [2*32-1:0] MEM_addr;
wire [2*32-1:0] MEM_read_data;
wire [2*32-1:0] MEM_write_data;
wire [2*4-1:0] MEM_write_mask;
wire [1:0] MEM_busy;
wire [1:0] MEM_done;
memory_controller MEM_CTRL(
CLK, RST,
COMM_write_flag[0], COMM_write_data[0], COMM_write_length[0],
COMM_read_flag[0], COMM_read_data[0], COMM_read_length[0],
COMM_writable[0], COMM_readable[0],
MEM_rw_flag, MEM_addr,
MEM_read_data, MEM_write_data, MEM_write_mask,
MEM_busy, MEM_done);
cpu_core CORE(
CLK, RST,
MEM_rw_flag, MEM_addr,
MEM_read_data, MEM_write_data, MEM_write_mask,
MEM_busy, MEM_done);
endmodule | 50 |
3,196 | data/full_repos/permissive/103257524/src/cpu/cpu_core.v | 103,257,524 | cpu_core.v | v | 181 | 113 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:87: Define or directive not defined: \'`ALU_OPCODE_WIDTH\'\n wire [`ALU_OPCODE_WIDTH-1:0] ID_EX_alu_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:94: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n wire [`MEM_OPCODE_WIDTH-1:0] ID_EX_mem_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:116: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n wire [`MEM_OPCODE_WIDTH-1:0] EX_MEM_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:176: Define or directive not defined: \'`MEM_NOP\'\n assign alu_forward_insn_id = EX_MEM_opcode == `MEM_NOP ? EX_MEM_insn_id : 3\'b111;\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/cpu_core.v:176: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n assign alu_forward_insn_id = EX_MEM_opcode == `MEM_NOP ? EX_MEM_insn_id : 3\'b111;\n ^\n%Error: Exiting due to 6 error(s)\n' | 987 | module | module cpu_core(
input CLK,
input RST,
output [2*2-1:0] rw_flag,
output [2*32-1:0] addr,
input [2*32-1:0] read_data,
output [2*32-1:0] write_data,
output [2*4-1:0] write_mask,
input [1:0] busy,
input [1:0] done
);
wire [2:0] writeback_insn_id;
wire [31:0] writeback_data;
wire [2:0] alu_forward_insn_id;
wire [31:0] alu_forward_data;
wire ID_IF_next_insn_enabled;
wire [31:0] ID_IF_next_insn;
wire ID_IF_busy;
wire [31:0] IF_ID_insn;
wire [31:0] IF_ID_insnPC;
wire IF_ID_placeholder_insn;
wire [1:0] ICACHE_rw_flag;
wire [31:0] ICACHE_addr;
wire [31:0] ICACHE_read_data;
wire [31:0] ICACHE_write_data;
wire [3:0] ICACHE_write_mask;
wire ICACHE_busy;
wire ICACHE_done;
wire ICACHE_flush_flag;
wire [31:0] ICACHE_flush_addr;
assign ICACHE_write_data = 0;
assign ICACHE_write_mask = 0;
assign ICACHE_rw_flag[1] = 0;
cache ICACHE(
CLK, RST,
ICACHE_rw_flag,
ICACHE_addr,
ICACHE_read_data,
ICACHE_write_data, ICACHE_write_mask,
ICACHE_busy, ICACHE_done,
ICACHE_flush_flag, ICACHE_flush_addr,
rw_flag[3:2], addr[63:32], read_data[63:32], write_data[63:32], write_mask[7:4], busy[1], done[1]);
pipeline_insnfetch IF(
CLK, RST,
ICACHE_rw_flag[0], ICACHE_addr, ICACHE_read_data, ICACHE_busy, ICACHE_done,
ID_IF_next_insn_enabled, ID_IF_next_insn, ID_IF_busy,
IF_ID_insn, IF_ID_insnPC, IF_ID_placeholder_insn);
wire EX_ID_busy;
wire [31:0] ID_EX_insnPC;
wire [2:0] ID_EX_insn_id;
wire [`ALU_OPCODE_WIDTH-1:0] ID_EX_alu_opcode;
wire [31:0] ID_EX_alu_src1;
wire ID_EX_alu_src1_forward;
wire [2:0] ID_EX_alu_src1_forward_from;
wire [31:0] ID_EX_alu_src2;
wire ID_EX_alu_src2_forward;
wire [2:0] ID_EX_alu_src2_forward_from;
wire [`MEM_OPCODE_WIDTH-1:0] ID_EX_mem_opcode;
wire [31:0] ID_EX_mem_src2;
wire ID_EX_mem_src2_forward;
wire [2:0] ID_EX_mem_src2_forward_from;
pipeline_decode ID(
CLK, RST,
IF_ID_insn, IF_ID_insnPC, IF_ID_placeholder_insn,
ID_IF_next_insn_enabled, ID_IF_next_insn, ID_IF_busy,
EX_ID_busy,
ID_EX_insnPC, ID_EX_insn_id,
ID_EX_alu_opcode,
ID_EX_alu_src1, ID_EX_alu_src1_forward, ID_EX_alu_src1_forward_from,
ID_EX_alu_src2, ID_EX_alu_src2_forward, ID_EX_alu_src2_forward_from,
ID_EX_mem_opcode,
ID_EX_mem_src2, ID_EX_mem_src2_forward, ID_EX_mem_src2_forward_from,
writeback_insn_id, writeback_data,
alu_forward_insn_id, alu_forward_data);
wire MEM_EX_busy;
wire [31:0] EX_MEM_insnPC;
wire [2:0] EX_MEM_insn_id;
wire [`MEM_OPCODE_WIDTH-1:0] EX_MEM_opcode;
wire [31:0] EX_MEM_src1;
wire [31:0] EX_MEM_src2;
wire EX_MEM_src2_forward;
wire [2:0] EX_MEM_src2_forward_from;
pipeline_exec EX(
CLK, RST,
EX_ID_busy,
ID_EX_insnPC, ID_EX_insn_id,
ID_EX_alu_opcode,
ID_EX_alu_src1, ID_EX_alu_src1_forward, ID_EX_alu_src1_forward_from,
ID_EX_alu_src2, ID_EX_alu_src2_forward, ID_EX_alu_src2_forward_from,
ID_EX_mem_opcode,
ID_EX_mem_src2, ID_EX_mem_src2_forward, ID_EX_mem_src2_forward_from,
MEM_EX_busy,
EX_MEM_insnPC, EX_MEM_insn_id,
EX_MEM_opcode,
EX_MEM_src1,
EX_MEM_src2, EX_MEM_src2_forward, EX_MEM_src2_forward_from,
writeback_insn_id, writeback_data,
alu_forward_insn_id, alu_forward_data);
wire [31:0] MEM_WB_insnPC;
wire [2:0] MEM_WB_insn_id;
wire [31:0] MEM_WB_mem_output;
wire [1:0] DCACHE_rw_flag;
wire [31:0] DCACHE_addr;
wire [31:0] DCACHE_read_data;
wire [31:0] DCACHE_write_data;
wire [4:0] DCACHE_write_mask;
wire DCACHE_busy;
wire DCACHE_done;
assign ICACHE_flush_flag = DCACHE_rw_flag[1];
assign ICACHE_flush_addr = DCACHE_addr;
cache DCACHE(
CLK, RST,
DCACHE_rw_flag,
DCACHE_addr,
DCACHE_read_data,
DCACHE_write_data, DCACHE_write_mask,
DCACHE_busy, DCACHE_done,
0, 32'b0,
rw_flag[1:0], addr[31:0], read_data[31:0], write_data[31:0], write_mask[3:0], busy[0], done[0]);
pipeline_mem MEM(
CLK, RST,
DCACHE_rw_flag, DCACHE_addr, DCACHE_read_data, DCACHE_write_data, DCACHE_write_mask, DCACHE_busy, DCACHE_done,
MEM_EX_busy,
EX_MEM_insnPC, EX_MEM_insn_id,
EX_MEM_opcode,
EX_MEM_src1,
EX_MEM_src2, EX_MEM_src2_forward, EX_MEM_src2_forward_from,
MEM_WB_insnPC, MEM_WB_insn_id, MEM_WB_mem_output,
writeback_insn_id, writeback_data);
assign alu_forward_insn_id = EX_MEM_opcode == `MEM_NOP ? EX_MEM_insn_id : 3'b111;
assign alu_forward_data = EX_MEM_src1;
assign writeback_insn_id = MEM_WB_insn_id;
assign writeback_data = MEM_WB_mem_output;
endmodule | module cpu_core(
input CLK,
input RST,
output [2*2-1:0] rw_flag,
output [2*32-1:0] addr,
input [2*32-1:0] read_data,
output [2*32-1:0] write_data,
output [2*4-1:0] write_mask,
input [1:0] busy,
input [1:0] done
); |
wire [2:0] writeback_insn_id;
wire [31:0] writeback_data;
wire [2:0] alu_forward_insn_id;
wire [31:0] alu_forward_data;
wire ID_IF_next_insn_enabled;
wire [31:0] ID_IF_next_insn;
wire ID_IF_busy;
wire [31:0] IF_ID_insn;
wire [31:0] IF_ID_insnPC;
wire IF_ID_placeholder_insn;
wire [1:0] ICACHE_rw_flag;
wire [31:0] ICACHE_addr;
wire [31:0] ICACHE_read_data;
wire [31:0] ICACHE_write_data;
wire [3:0] ICACHE_write_mask;
wire ICACHE_busy;
wire ICACHE_done;
wire ICACHE_flush_flag;
wire [31:0] ICACHE_flush_addr;
assign ICACHE_write_data = 0;
assign ICACHE_write_mask = 0;
assign ICACHE_rw_flag[1] = 0;
cache ICACHE(
CLK, RST,
ICACHE_rw_flag,
ICACHE_addr,
ICACHE_read_data,
ICACHE_write_data, ICACHE_write_mask,
ICACHE_busy, ICACHE_done,
ICACHE_flush_flag, ICACHE_flush_addr,
rw_flag[3:2], addr[63:32], read_data[63:32], write_data[63:32], write_mask[7:4], busy[1], done[1]);
pipeline_insnfetch IF(
CLK, RST,
ICACHE_rw_flag[0], ICACHE_addr, ICACHE_read_data, ICACHE_busy, ICACHE_done,
ID_IF_next_insn_enabled, ID_IF_next_insn, ID_IF_busy,
IF_ID_insn, IF_ID_insnPC, IF_ID_placeholder_insn);
wire EX_ID_busy;
wire [31:0] ID_EX_insnPC;
wire [2:0] ID_EX_insn_id;
wire [`ALU_OPCODE_WIDTH-1:0] ID_EX_alu_opcode;
wire [31:0] ID_EX_alu_src1;
wire ID_EX_alu_src1_forward;
wire [2:0] ID_EX_alu_src1_forward_from;
wire [31:0] ID_EX_alu_src2;
wire ID_EX_alu_src2_forward;
wire [2:0] ID_EX_alu_src2_forward_from;
wire [`MEM_OPCODE_WIDTH-1:0] ID_EX_mem_opcode;
wire [31:0] ID_EX_mem_src2;
wire ID_EX_mem_src2_forward;
wire [2:0] ID_EX_mem_src2_forward_from;
pipeline_decode ID(
CLK, RST,
IF_ID_insn, IF_ID_insnPC, IF_ID_placeholder_insn,
ID_IF_next_insn_enabled, ID_IF_next_insn, ID_IF_busy,
EX_ID_busy,
ID_EX_insnPC, ID_EX_insn_id,
ID_EX_alu_opcode,
ID_EX_alu_src1, ID_EX_alu_src1_forward, ID_EX_alu_src1_forward_from,
ID_EX_alu_src2, ID_EX_alu_src2_forward, ID_EX_alu_src2_forward_from,
ID_EX_mem_opcode,
ID_EX_mem_src2, ID_EX_mem_src2_forward, ID_EX_mem_src2_forward_from,
writeback_insn_id, writeback_data,
alu_forward_insn_id, alu_forward_data);
wire MEM_EX_busy;
wire [31:0] EX_MEM_insnPC;
wire [2:0] EX_MEM_insn_id;
wire [`MEM_OPCODE_WIDTH-1:0] EX_MEM_opcode;
wire [31:0] EX_MEM_src1;
wire [31:0] EX_MEM_src2;
wire EX_MEM_src2_forward;
wire [2:0] EX_MEM_src2_forward_from;
pipeline_exec EX(
CLK, RST,
EX_ID_busy,
ID_EX_insnPC, ID_EX_insn_id,
ID_EX_alu_opcode,
ID_EX_alu_src1, ID_EX_alu_src1_forward, ID_EX_alu_src1_forward_from,
ID_EX_alu_src2, ID_EX_alu_src2_forward, ID_EX_alu_src2_forward_from,
ID_EX_mem_opcode,
ID_EX_mem_src2, ID_EX_mem_src2_forward, ID_EX_mem_src2_forward_from,
MEM_EX_busy,
EX_MEM_insnPC, EX_MEM_insn_id,
EX_MEM_opcode,
EX_MEM_src1,
EX_MEM_src2, EX_MEM_src2_forward, EX_MEM_src2_forward_from,
writeback_insn_id, writeback_data,
alu_forward_insn_id, alu_forward_data);
wire [31:0] MEM_WB_insnPC;
wire [2:0] MEM_WB_insn_id;
wire [31:0] MEM_WB_mem_output;
wire [1:0] DCACHE_rw_flag;
wire [31:0] DCACHE_addr;
wire [31:0] DCACHE_read_data;
wire [31:0] DCACHE_write_data;
wire [4:0] DCACHE_write_mask;
wire DCACHE_busy;
wire DCACHE_done;
assign ICACHE_flush_flag = DCACHE_rw_flag[1];
assign ICACHE_flush_addr = DCACHE_addr;
cache DCACHE(
CLK, RST,
DCACHE_rw_flag,
DCACHE_addr,
DCACHE_read_data,
DCACHE_write_data, DCACHE_write_mask,
DCACHE_busy, DCACHE_done,
0, 32'b0,
rw_flag[1:0], addr[31:0], read_data[31:0], write_data[31:0], write_mask[3:0], busy[0], done[0]);
pipeline_mem MEM(
CLK, RST,
DCACHE_rw_flag, DCACHE_addr, DCACHE_read_data, DCACHE_write_data, DCACHE_write_mask, DCACHE_busy, DCACHE_done,
MEM_EX_busy,
EX_MEM_insnPC, EX_MEM_insn_id,
EX_MEM_opcode,
EX_MEM_src1,
EX_MEM_src2, EX_MEM_src2_forward, EX_MEM_src2_forward_from,
MEM_WB_insnPC, MEM_WB_insn_id, MEM_WB_mem_output,
writeback_insn_id, writeback_data);
assign alu_forward_insn_id = EX_MEM_opcode == `MEM_NOP ? EX_MEM_insn_id : 3'b111;
assign alu_forward_data = EX_MEM_src1;
assign writeback_insn_id = MEM_WB_insn_id;
assign writeback_data = MEM_WB_mem_output;
endmodule | 50 |
3,197 | data/full_repos/permissive/103257524/src/cpu/fifo.v | 103,257,524 | fifo.v | v | 78 | 83 | [] | [] | [] | [(23, 77)] | null | data/verilator_xmls/8d53c04d-19a6-48d2-a81c-a7a88d340254.xml | null | 988 | module | module fifo
#(
parameter SIZE_BIT = 3,
parameter WIDTH = 8
)
(
input CLK,
input RST,
input read_flag,
output [WIDTH-1:0] read_data,
input write_flag,
input [WIDTH-1:0] write_data,
output empty,
output full
);
localparam SIZE = 1 << SIZE_BIT;
reg [WIDTH-1:0] buffer[SIZE-1:0];
reg [SIZE_BIT-1:0] read_ptr;
reg [SIZE_BIT-1:0] write_ptr;
reg [SIZE_BIT:0] buffer_size;
assign empty = buffer_size == 0;
assign full = buffer_size == SIZE;
wire read, write;
assign read = read_flag && !empty;
assign write = write_flag && !full;
assign read_data = buffer[read_ptr];
integer i;
always @(negedge CLK or posedge RST) begin
if(RST) begin
read_ptr <= 0;
write_ptr <= 0;
buffer_size <= 0;
for(i=0; i<SIZE; i=i+1)
buffer[i] <= 0;
end else begin
if(read && write) begin
buffer[write_ptr] <= write_data;
read_ptr <= read_ptr + 1;
write_ptr <= write_ptr + 1;
end else if(read) begin
read_ptr <= read_ptr + 1;
buffer_size <= buffer_size - 1;
end else if(write) begin
buffer[write_ptr] <= write_data;
write_ptr <= write_ptr + 1;
buffer_size <= buffer_size + 1;
end
end
end
endmodule | module fifo
#(
parameter SIZE_BIT = 3,
parameter WIDTH = 8
)
(
input CLK,
input RST,
input read_flag,
output [WIDTH-1:0] read_data,
input write_flag,
input [WIDTH-1:0] write_data,
output empty,
output full
); |
localparam SIZE = 1 << SIZE_BIT;
reg [WIDTH-1:0] buffer[SIZE-1:0];
reg [SIZE_BIT-1:0] read_ptr;
reg [SIZE_BIT-1:0] write_ptr;
reg [SIZE_BIT:0] buffer_size;
assign empty = buffer_size == 0;
assign full = buffer_size == SIZE;
wire read, write;
assign read = read_flag && !empty;
assign write = write_flag && !full;
assign read_data = buffer[read_ptr];
integer i;
always @(negedge CLK or posedge RST) begin
if(RST) begin
read_ptr <= 0;
write_ptr <= 0;
buffer_size <= 0;
for(i=0; i<SIZE; i=i+1)
buffer[i] <= 0;
end else begin
if(read && write) begin
buffer[write_ptr] <= write_data;
read_ptr <= read_ptr + 1;
write_ptr <= write_ptr + 1;
end else if(read) begin
read_ptr <= read_ptr + 1;
buffer_size <= buffer_size - 1;
end else if(write) begin
buffer[write_ptr] <= write_data;
write_ptr <= write_ptr + 1;
buffer_size <= buffer_size + 1;
end
end
end
endmodule | 50 |
3,198 | data/full_repos/permissive/103257524/src/cpu/memory_controller.v | 103,257,524 | memory_controller.v | v | 230 | 133 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/memory_controller.v:22: Cannot find include file: common.h\n`include "common.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/common.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/common.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/common.h.sv\n common.h\n common.h.v\n common.h.sv\n obj_dir/common.h\n obj_dir/common.h.v\n obj_dir/common.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/memory_controller.v:53: Define or directive not defined: \'`CLOG2\'\n localparam LENGTH_WIDTH = `CLOG2(DATA_WIDTH_BYTE) + 1;\n ^~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/memory_controller.v:54: Define or directive not defined: \'`CLOG2\'\n localparam PORT_COUNT_BIT = `CLOG2(PORT_COUNT);\n ^~~~~~\n%Error: Exiting due to 3 error(s)\n' | 989 | module | module memory_controller
#(
parameter PORT_COUNT = 2,
parameter DATA_WIDTH_BYTE = 4,
parameter ADDR_WIDTH_BYTE = 4
)
(
CLK, RST,
send_flag, send_data, send_length,
recv_flag, recv_data, recv_length,
sendable, receivable,
rw_flag_,
addr_,
read_data_, write_data_, write_mask_,
busy, done
);
localparam DATA_WIDTH = 8 * DATA_WIDTH_BYTE;
localparam ADDR_WIDTH = 8 * ADDR_WIDTH_BYTE;
localparam LENGTH_WIDTH = `CLOG2(DATA_WIDTH_BYTE) + 1;
localparam PORT_COUNT_BIT = `CLOG2(PORT_COUNT);
localparam SEND_BYTE = DATA_WIDTH_BYTE + ADDR_WIDTH_BYTE + DATA_WIDTH_BYTE / 8 + 1;
input CLK, RST;
output reg send_flag;
output reg [SEND_BYTE*8-1:0] send_data;
output reg [4:0] send_length;
output reg recv_flag;
input [SEND_BYTE*8-1:0] recv_data;
input [4:0] recv_length;
input sendable, receivable;
input [PORT_COUNT*2-1:0] rw_flag_;
input [PORT_COUNT * ADDR_WIDTH-1:0] addr_;
output [PORT_COUNT * DATA_WIDTH-1:0] read_data_;
input [PORT_COUNT * DATA_WIDTH-1:0] write_data_;
input [PORT_COUNT * DATA_WIDTH_BYTE-1:0] write_mask_;
output reg [PORT_COUNT-1:0] busy;
output reg [PORT_COUNT-1:0] done;
wire [1:0] rw_flag[PORT_COUNT-1:0];
wire [ADDR_WIDTH-1:0] addr[PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] read_data[PORT_COUNT-1:0];
wire [DATA_WIDTH-1:0] write_data[PORT_COUNT-1:0];
wire [DATA_WIDTH_BYTE-1:0] write_mask[PORT_COUNT-1:0];
genvar j;
generate
for(j=0; j<PORT_COUNT; j=j+1) begin
assign rw_flag[j] = rw_flag_[(j+1)*2-1:j*2];
assign addr[j] = addr_[(j+1)*ADDR_WIDTH-1:j*ADDR_WIDTH];
assign read_data_[(j+1)*DATA_WIDTH-1:j*DATA_WIDTH] = read_data[j];
assign write_data[j] = write_data_[(j+1)*DATA_WIDTH-1:j*DATA_WIDTH];
assign write_mask[j] = write_mask_[(j+1)*DATA_WIDTH_BYTE-1:j*DATA_WIDTH_BYTE];
end
endgenerate
localparam NO_PORT = (1 << (PORT_COUNT_BIT + 1)) - 1;
wire [PORT_COUNT_BIT:0] wait_port;
reg [PORT_COUNT_BIT:0] serv_port;
reg [1:0] pending_flag[PORT_COUNT-1:0];
reg [ADDR_WIDTH-1:0] pending_addr[PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] pending_write_data[PORT_COUNT-1:0];
reg [DATA_WIDTH_BYTE-1:0] pending_write_mask[PORT_COUNT-1:0];
localparam STATE_IDLE = 0;
localparam STATE_WAIT_FOR_RECV = 1;
reg state;
wire [PORT_COUNT_BIT:0] wait_port_tmp[PORT_COUNT-1:0];
assign wait_port = wait_port_tmp[PORT_COUNT-1];
generate
assign wait_port_tmp[0] = (rw_flag[0] == 0 && pending_flag[0] == 0) ? NO_PORT : 0;
for(j=1; j<PORT_COUNT; j=j+1) begin
assign wait_port_tmp[j] = (wait_port_tmp[j-1] != NO_PORT || (rw_flag[j] == 0 && pending_flag[j] == 0)) ? wait_port_tmp[j-1] : j;
end
endgenerate
task set_pending;
input [PORT_COUNT_BIT:0] port_id;
begin
if(rw_flag[port_id] != 0 && busy[port_id] == 0) begin
pending_flag[port_id] <= rw_flag[port_id];
pending_addr[port_id] <= addr[port_id];
pending_write_data[port_id] <= write_data[port_id];
pending_write_mask[port_id] <= write_mask[port_id];
busy[port_id] <= 1;
end
end
endtask
task send_request;
input [1:0] in_flag;
input [ADDR_WIDTH-1:0] in_addr;
input [DATA_WIDTH-1:0] in_write_data;
input [DATA_WIDTH_BYTE-1:0] in_write_mask;
begin
if(in_flag == 1) begin
send_data <= {1'b0, in_addr};
send_length <= ADDR_WIDTH_BYTE + 1;
send_flag <= 1;
end else if(in_flag == 2) begin
send_data <= {1'b1, in_write_mask, in_addr, in_write_data};
send_length <= SEND_BYTE;
send_flag <= 1;
end
end
endtask
integer i;
always @(posedge CLK or posedge RST) begin
send_flag <= 0;
recv_flag <= 0;
done <= 0;
if(RST) begin
state <= STATE_IDLE;
send_data <= 0;
send_length <= 0;
serv_port <= NO_PORT;
busy <= 0;
for(i=0; i<PORT_COUNT; i=i+1) begin
read_data[i] <= 0;
pending_flag[i] <= 0;
pending_addr[i] <= 0;
pending_write_data[i] <= 0;
pending_write_mask[i] <= 0;
end
end else begin
if(state != STATE_IDLE) begin
for(i=0; i<PORT_COUNT; i=i+1)
set_pending(i);
end
case(state)
STATE_IDLE: begin
for(i=0; i<PORT_COUNT; i=i+1)
if(i != wait_port)
set_pending(i);
if(wait_port != NO_PORT) begin
if(sendable) begin
if(pending_flag[wait_port] != 0) begin
send_request(pending_flag[wait_port], pending_addr[wait_port], pending_write_data[wait_port], pending_write_mask[wait_port]);
if(pending_flag[wait_port] == 2) begin
pending_flag[wait_port] <= 0;
busy[wait_port] <= 0;
done[wait_port] <= 1;
end else begin
serv_port <= wait_port;
busy[wait_port] <= 1;
state <= STATE_WAIT_FOR_RECV;
end
end else begin
send_request(rw_flag[wait_port], addr[wait_port], write_data[wait_port], write_mask[wait_port]);
if(rw_flag[wait_port] == 2) begin
busy[wait_port] <= 0;
done[wait_port] <= 1;
end else begin
serv_port <= wait_port;
busy[wait_port] <= 1;
state <= STATE_WAIT_FOR_RECV;
end
end
end else begin
if(rw_flag[wait_port] != 0)
set_pending(wait_port);
end
end
end
STATE_WAIT_FOR_RECV: begin
if(receivable) begin
recv_flag <= 1;
read_data[serv_port] <= recv_data[DATA_WIDTH-1:0];
done[serv_port] <= 1;
busy[serv_port] <= 0;
pending_flag[serv_port] <= 0;
serv_port <= NO_PORT;
state <= STATE_IDLE;
end
end
endcase
end
end
endmodule | module memory_controller
#(
parameter PORT_COUNT = 2,
parameter DATA_WIDTH_BYTE = 4,
parameter ADDR_WIDTH_BYTE = 4
)
(
CLK, RST,
send_flag, send_data, send_length,
recv_flag, recv_data, recv_length,
sendable, receivable,
rw_flag_,
addr_,
read_data_, write_data_, write_mask_,
busy, done
); |
localparam DATA_WIDTH = 8 * DATA_WIDTH_BYTE;
localparam ADDR_WIDTH = 8 * ADDR_WIDTH_BYTE;
localparam LENGTH_WIDTH = `CLOG2(DATA_WIDTH_BYTE) + 1;
localparam PORT_COUNT_BIT = `CLOG2(PORT_COUNT);
localparam SEND_BYTE = DATA_WIDTH_BYTE + ADDR_WIDTH_BYTE + DATA_WIDTH_BYTE / 8 + 1;
input CLK, RST;
output reg send_flag;
output reg [SEND_BYTE*8-1:0] send_data;
output reg [4:0] send_length;
output reg recv_flag;
input [SEND_BYTE*8-1:0] recv_data;
input [4:0] recv_length;
input sendable, receivable;
input [PORT_COUNT*2-1:0] rw_flag_;
input [PORT_COUNT * ADDR_WIDTH-1:0] addr_;
output [PORT_COUNT * DATA_WIDTH-1:0] read_data_;
input [PORT_COUNT * DATA_WIDTH-1:0] write_data_;
input [PORT_COUNT * DATA_WIDTH_BYTE-1:0] write_mask_;
output reg [PORT_COUNT-1:0] busy;
output reg [PORT_COUNT-1:0] done;
wire [1:0] rw_flag[PORT_COUNT-1:0];
wire [ADDR_WIDTH-1:0] addr[PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] read_data[PORT_COUNT-1:0];
wire [DATA_WIDTH-1:0] write_data[PORT_COUNT-1:0];
wire [DATA_WIDTH_BYTE-1:0] write_mask[PORT_COUNT-1:0];
genvar j;
generate
for(j=0; j<PORT_COUNT; j=j+1) begin
assign rw_flag[j] = rw_flag_[(j+1)*2-1:j*2];
assign addr[j] = addr_[(j+1)*ADDR_WIDTH-1:j*ADDR_WIDTH];
assign read_data_[(j+1)*DATA_WIDTH-1:j*DATA_WIDTH] = read_data[j];
assign write_data[j] = write_data_[(j+1)*DATA_WIDTH-1:j*DATA_WIDTH];
assign write_mask[j] = write_mask_[(j+1)*DATA_WIDTH_BYTE-1:j*DATA_WIDTH_BYTE];
end
endgenerate
localparam NO_PORT = (1 << (PORT_COUNT_BIT + 1)) - 1;
wire [PORT_COUNT_BIT:0] wait_port;
reg [PORT_COUNT_BIT:0] serv_port;
reg [1:0] pending_flag[PORT_COUNT-1:0];
reg [ADDR_WIDTH-1:0] pending_addr[PORT_COUNT-1:0];
reg [DATA_WIDTH-1:0] pending_write_data[PORT_COUNT-1:0];
reg [DATA_WIDTH_BYTE-1:0] pending_write_mask[PORT_COUNT-1:0];
localparam STATE_IDLE = 0;
localparam STATE_WAIT_FOR_RECV = 1;
reg state;
wire [PORT_COUNT_BIT:0] wait_port_tmp[PORT_COUNT-1:0];
assign wait_port = wait_port_tmp[PORT_COUNT-1];
generate
assign wait_port_tmp[0] = (rw_flag[0] == 0 && pending_flag[0] == 0) ? NO_PORT : 0;
for(j=1; j<PORT_COUNT; j=j+1) begin
assign wait_port_tmp[j] = (wait_port_tmp[j-1] != NO_PORT || (rw_flag[j] == 0 && pending_flag[j] == 0)) ? wait_port_tmp[j-1] : j;
end
endgenerate
task set_pending;
input [PORT_COUNT_BIT:0] port_id;
begin
if(rw_flag[port_id] != 0 && busy[port_id] == 0) begin
pending_flag[port_id] <= rw_flag[port_id];
pending_addr[port_id] <= addr[port_id];
pending_write_data[port_id] <= write_data[port_id];
pending_write_mask[port_id] <= write_mask[port_id];
busy[port_id] <= 1;
end
end
endtask
task send_request;
input [1:0] in_flag;
input [ADDR_WIDTH-1:0] in_addr;
input [DATA_WIDTH-1:0] in_write_data;
input [DATA_WIDTH_BYTE-1:0] in_write_mask;
begin
if(in_flag == 1) begin
send_data <= {1'b0, in_addr};
send_length <= ADDR_WIDTH_BYTE + 1;
send_flag <= 1;
end else if(in_flag == 2) begin
send_data <= {1'b1, in_write_mask, in_addr, in_write_data};
send_length <= SEND_BYTE;
send_flag <= 1;
end
end
endtask
integer i;
always @(posedge CLK or posedge RST) begin
send_flag <= 0;
recv_flag <= 0;
done <= 0;
if(RST) begin
state <= STATE_IDLE;
send_data <= 0;
send_length <= 0;
serv_port <= NO_PORT;
busy <= 0;
for(i=0; i<PORT_COUNT; i=i+1) begin
read_data[i] <= 0;
pending_flag[i] <= 0;
pending_addr[i] <= 0;
pending_write_data[i] <= 0;
pending_write_mask[i] <= 0;
end
end else begin
if(state != STATE_IDLE) begin
for(i=0; i<PORT_COUNT; i=i+1)
set_pending(i);
end
case(state)
STATE_IDLE: begin
for(i=0; i<PORT_COUNT; i=i+1)
if(i != wait_port)
set_pending(i);
if(wait_port != NO_PORT) begin
if(sendable) begin
if(pending_flag[wait_port] != 0) begin
send_request(pending_flag[wait_port], pending_addr[wait_port], pending_write_data[wait_port], pending_write_mask[wait_port]);
if(pending_flag[wait_port] == 2) begin
pending_flag[wait_port] <= 0;
busy[wait_port] <= 0;
done[wait_port] <= 1;
end else begin
serv_port <= wait_port;
busy[wait_port] <= 1;
state <= STATE_WAIT_FOR_RECV;
end
end else begin
send_request(rw_flag[wait_port], addr[wait_port], write_data[wait_port], write_mask[wait_port]);
if(rw_flag[wait_port] == 2) begin
busy[wait_port] <= 0;
done[wait_port] <= 1;
end else begin
serv_port <= wait_port;
busy[wait_port] <= 1;
state <= STATE_WAIT_FOR_RECV;
end
end
end else begin
if(rw_flag[wait_port] != 0)
set_pending(wait_port);
end
end
end
STATE_WAIT_FOR_RECV: begin
if(receivable) begin
recv_flag <= 1;
read_data[serv_port] <= recv_data[DATA_WIDTH-1:0];
done[serv_port] <= 1;
busy[serv_port] <= 0;
pending_flag[serv_port] <= 0;
serv_port <= NO_PORT;
state <= STATE_IDLE;
end
end
endcase
end
end
endmodule | 50 |
3,202 | data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v | 103,257,524 | pipeline_decode.v | v | 1,177 | 135 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:38: Define or directive not defined: \'`ALU_OPCODE_WIDTH\'\n output reg [`ALU_OPCODE_WIDTH-1:0] alu_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:45: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n output reg [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:365: Define or directive not defined: \'`ALU_OPCODE_WIDTH\'\n input [`ALU_OPCODE_WIDTH-1:0] alu_op;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:366: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_op;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:386: Define or directive not defined: \'`ALU_OPCODE_WIDTH\'\n input [`ALU_OPCODE_WIDTH-1:0] alu_op;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:387: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_op;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:650: Define or directive not defined: \'`ALU_NOP\'\n alu_opcode <= `ALU_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:650: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n alu_opcode <= `ALU_NOP;\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:657: Define or directive not defined: \'`MEM_NOP\'\n mem_opcode <= `MEM_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:657: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mem_opcode <= `MEM_NOP;\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:669: Define or directive not defined: \'`ALU_ADD\'\n OPFUNC_ADD: decode_rtype(rd, 1, 1, `ALU_ADD, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:669: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_ADD: decode_rtype(rd, 1, 1, `ALU_ADD, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:670: Define or directive not defined: \'`ALU_ADDU\'\n OPFUNC_ADDU: decode_rtype(rd, 1, 1, `ALU_ADDU, `MEM_NOP);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:670: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_ADDU: decode_rtype(rd, 1, 1, `ALU_ADDU, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:671: Define or directive not defined: \'`ALU_SUB\'\n OPFUNC_SUB: decode_rtype(rd, 1, 1, `ALU_SUB, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:671: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_SUB: decode_rtype(rd, 1, 1, `ALU_SUB, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:672: Define or directive not defined: \'`ALU_SUBU\'\n OPFUNC_SUBU: decode_rtype(rd, 1, 1, `ALU_SUBU, `MEM_NOP);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:672: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_SUBU: decode_rtype(rd, 1, 1, `ALU_SUBU, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:673: Define or directive not defined: \'`ALU_SLL\'\n OPFUNC_SLLV: decode_rtype(rd, 1, 1, `ALU_SLL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:673: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_SLLV: decode_rtype(rd, 1, 1, `ALU_SLL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:674: Define or directive not defined: \'`ALU_ROR\'\n OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:674: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:674: Define or directive not defined: \'`ALU_SRL\'\n OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:674: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:675: Define or directive not defined: \'`ALU_SRA\'\n OPFUNC_SRAV: decode_rtype(rd, 1, 1, `ALU_SRA, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:675: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_SRAV: decode_rtype(rd, 1, 1, `ALU_SRA, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:676: Define or directive not defined: \'`ALU_AND\'\n OPFUNC_AND: decode_rtype(rd, 1, 1, `ALU_AND, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:676: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_AND: decode_rtype(rd, 1, 1, `ALU_AND, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:677: Define or directive not defined: \'`ALU_OR\'\n OPFUNC_OR: decode_rtype(rd, 1, 1, `ALU_OR, `MEM_NOP);\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:677: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_OR: decode_rtype(rd, 1, 1, `ALU_OR, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:678: Define or directive not defined: \'`ALU_NOR\'\n OPFUNC_NOR: decode_rtype(rd, 1, 1, `ALU_NOR, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:678: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_NOR: decode_rtype(rd, 1, 1, `ALU_NOR, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:679: Define or directive not defined: \'`ALU_XOR\'\n OPFUNC_XOR: decode_rtype(rd, 1, 1, `ALU_XOR, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:679: Define or directive not defined: \'`MEM_NOP\'\n OPFUNC_XOR: decode_rtype(rd, 1, 1, `ALU_XOR, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:681: Define or directive not defined: \'`ALU_SLL\'\n decode_rtype(rd, 0, 1, `ALU_SLL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:681: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 0, 1, `ALU_SLL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:685: Define or directive not defined: \'`ALU_ROR\'\n decode_rtype(rd, 0, 1, rs == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:685: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n decode_rtype(rd, 0, 1, rs == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:685: Define or directive not defined: \'`ALU_SRL\'\n decode_rtype(rd, 0, 1, rs == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:685: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 0, 1, rs == 5\'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:689: Define or directive not defined: \'`ALU_SRA\'\n decode_rtype(rd, 0, 1, `ALU_SRA, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:689: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 0, 1, `ALU_SRA, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:694: Define or directive not defined: \'`ALU_MULTL\'\n decode_rtype(rd, 1, 1, `ALU_MULTL, `MEM_NOP);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:694: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 1, 1, `ALU_MULTL, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:696: Define or directive not defined: \'`ALU_MULTH\'\n decode_rtype(rd, 1, 1, `ALU_MULTH, `MEM_NOP);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:696: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 1, 1, `ALU_MULTH, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:701: Define or directive not defined: \'`ALU_MULTLU\'\n decode_rtype(rd, 1, 1, `ALU_MULTLU, `MEM_NOP);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:701: Define or directive not defined: \'`MEM_NOP\'\n decode_rtype(rd, 1, 1, `ALU_MULTLU, `MEM_NOP);\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_decode.v:703: Define or directive not defined: \'`ALU_MULTHU\'\n decode_rtype(rd, 1, 1, `ALU_MULTHU, `MEM_NOP);\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 992 | module | module pipeline_decode(
input CLK,
input RST,
input [31:0] prev_insn,
input [31:0] prev_insnPC,
input prev_placeholder_insn,
output reg prev_next_insn_enabled,
output reg [31:0] prev_next_insn,
output prev_busy,
input next_busy,
output reg [31:0] next_insnPC,
output reg [2:0] next_insn_id,
output reg [`ALU_OPCODE_WIDTH-1:0] alu_opcode,
output reg [31:0] alu_src1,
output reg alu_src1_forward,
output reg [2:0] alu_src1_forward_from,
output reg [31:0] alu_src2,
output reg alu_src2_forward,
output reg [2:0] alu_src2_forward_from,
output reg [`MEM_OPCODE_WIDTH-1:0] mem_opcode,
output reg [31:0] mem_src2,
output reg mem_src2_forward,
output reg [2:0] mem_src2_forward_from,
input [2:0] writeback_insn_id,
input [31:0] writeback_data,
input [2:0] alu_forward_insn_id,
input [31:0] alu_forward_data
);
localparam OPCD_SPECIAL = 6'h00;
localparam OPCD_REGIMM = 6'h01;
localparam OPCD_BEQ = 6'h04;
localparam OPCD_BNE = 6'h05;
localparam OPCD_POP06 = 6'h06;
localparam OPCD_POP07 = 6'h07;
localparam OPCD_POP10 = 6'h08;
localparam OPCD_ADDIU = 6'h09;
localparam OPCD_SLTI = 6'h0A;
localparam OPCD_SLTIU = 6'h0B;
localparam OPCD_ANDI = 6'h0C;
localparam OPCD_ORI = 6'h0D;
localparam OPCD_XORI = 6'h0E;
localparam OPCD_AUI = 6'h0F;
localparam OPCD_POP26 = 6'h16;
localparam OPCD_POP27 = 6'h17;
localparam OPCD_POP30 = 6'h18;
localparam OPCD_LB = 6'h20;
localparam OPCD_LH = 6'h21;
localparam OPCD_LW = 6'h23;
localparam OPCD_LBU = 6'h24;
localparam OPCD_LHU = 6'h25;
localparam OPCD_SB = 6'h28;
localparam OPCD_SH = 6'h29;
localparam OPCD_SW = 6'h2B;
localparam OPCD_LWC1 = 6'h31;
localparam OPCD_SWC1 = 6'h39;
localparam OPCD_J = 6'h02;
localparam OPCD_JAL = 6'h03;
localparam OPCD_BC = 6'h32;
localparam OPCD_POP66 = 6'h36;
localparam OPCD_BALC = 6'h3A;
localparam OPCD_POP76 = 6'h3E;
localparam OPFUNC_SLL = 6'h00;
localparam OPFUNC_SRL = 6'h02;
localparam OPFUNC_SRA = 6'h03;
localparam OPFUNC_SLLV = 6'h04;
localparam OPFUNC_SRLV = 6'h06;
localparam OPFUNC_SRAV = 6'h07;
localparam OPFUNC_JR = 6'h08;
localparam OPFUNC_JALR = 6'h09;
localparam OPFUNC_SYSCALL = 6'h0C;
localparam OPFUNC_BREAK = 6'h0D;
localparam OPFUNC_SOP30 = 6'h18;
localparam OPFUNC_SOP31 = 6'h19;
localparam OPFUNC_SOP32 = 6'h1A;
localparam OPFUNC_SOP33 = 6'h1B;
localparam OPFUNC_ADD = 6'h20;
localparam OPFUNC_ADDU = 6'h21;
localparam OPFUNC_SUB = 6'h22;
localparam OPFUNC_SUBU = 6'h23;
localparam OPFUNC_AND = 6'h24;
localparam OPFUNC_OR = 6'h25;
localparam OPFUNC_XOR = 6'h26;
localparam OPFUNC_NOR = 6'h27;
localparam OPFUNC_SLT = 6'h2A;
localparam OPFUNC_SLTU = 6'h2B;
reg [31:0] insn;
reg [31:0] insnPC;
reg [2:0] insn_id;
reg [4:0] insn_write_reg[7:0];
reg insn_data_overrided[7:0];
reg [31:0] reg_file[31:1];
wire [31:0] GPR[31:0];
reg reg_lock[31:0];
reg [2:0] reg_lock_by[31:0];
reg [4:0] next_insn_write_reg;
reg [4:0] next_insn_write_reg_pending;
genvar j;
generate
for(j=1; j<32; j=j+1)
assign GPR[j] = reg_file[j];
endgenerate
assign GPR[0] = 0;
reg busy;
assign prev_busy = busy || next_busy;
wire writeback_flag =!insn_data_overrided[writeback_insn_id];
wire alu_forward_flag =!insn_data_overrided[alu_forward_insn_id];
wire [4:0] writeback_reg = insn_write_reg[writeback_insn_id];
wire [4:0] alu_forward_reg = insn_write_reg[alu_forward_insn_id];
integer i;
task write_register;
input [4:0] regid;
begin
next_insn_write_reg_pending <= regid;
end
endtask
reg drop_next_insn;
localparam NEVER = 0;
localparam ALWAYS = 1;
localparam RS_EQ_RT = 2;
localparam RS_NE_RT = 3;
localparam RS_GTU_RT = 4;
localparam RS_LTU_RT = 5;
localparam RS_GEU_RT = 6;
localparam RS_LEU_RT = 7;
localparam RS_GT_RT = 8;
localparam RS_LT_RT = 9;
localparam RS_GE_RT = 10;
localparam RS_LE_RT = 11;
localparam RS_EQ_ZERO = 12;
localparam RS_NE_ZERO = 13;
localparam RS_GT_ZERO = 14;
localparam RS_LT_ZERO = 15;
localparam RS_GE_ZERO = 16;
localparam RS_LE_ZERO = 17;
localparam RT_EQ_ZERO = 18;
localparam RT_NE_ZERO = 19;
localparam RT_GT_ZERO = 20;
localparam RT_LT_ZERO = 21;
localparam RT_GE_ZERO = 22;
localparam RT_LE_ZERO = 23;
reg [23:0] jump_cond;
reg [6:0] jump_cond_basic;
reg [4:0] jump_cond_id;
localparam JUMP_J = 0;
localparam JUMP_BC = 1;
localparam JUMP_BALC = 2;
localparam JUMP_BC_LONG = 4;
localparam JUMP_J_LONG = 8;
localparam JUMP_BC_VERY_LONG = 16;
localparam JUMP_GPR_RS = 32;
reg [5:0] jump_type;
reg [3:0] POP_insn_type;
reg [31:0] Branch_target;
reg [31:0] BC_target;
reg [31:0] BC_long_target;
reg [31:0] J_target;
reg [31:0] BC_very_long_target;
reg [31:0] GPR_rs, GPR_rt;
reg rs_lock, rt_lock;
reg [2:0] rs_lock_by, rt_lock_by;
reg [5:0] opcode;
reg [4:0] rs, rt, rd, sa;
reg [5:0] opfunc;
reg [15:0] imm;
reg [25:0] j_addr;
task fetch_rs;
begin
alu_src1 <= GPR_rs;
alu_src1_forward <= rs_lock;
alu_src1_forward_from <= rs_lock_by;
end
endtask
task fetch_rt;
begin
alu_src2 <= GPR_rt;
alu_src2_forward <= rt_lock;
alu_src2_forward_from <= rt_lock_by;
end
endtask
task decode_rtype;
input [4:0] dst;
input use_src1;
input use_src2;
input [`ALU_OPCODE_WIDTH-1:0] alu_op;
input [`MEM_OPCODE_WIDTH-1:0] mem_op;
begin
if(use_src1) begin
fetch_rs();
end
if(use_src2) begin
fetch_rt();
end
alu_opcode <= alu_op;
mem_opcode <= mem_op;
write_register(dst);
end
endtask
task decode_itype;
input [4:0] dst;
input use_src1;
input sign_extend;
input [`ALU_OPCODE_WIDTH-1:0] alu_op;
input [`MEM_OPCODE_WIDTH-1:0] mem_op;
begin
if(use_src1) begin
fetch_rs();
end
if(sign_extend)
alu_src2 <= {{16{imm[15]}}, imm};
else
alu_src2 <= {16'b0, imm};
alu_opcode <= alu_op;
mem_opcode <= mem_op;
write_register(dst);
end
endtask
reg tmp_busy;
reg [31:0] tmp_GPR_rs, tmp_GPR_rt;
reg clear_next_insn;
reg [31:0] last_next_insn;
reg last_next_insn_enabled;
reg last_drop_next_insn;
reg [31:0] insnPC_add_4;
always @(posedge CLK or posedge RST) begin
if(RST) begin
insn <= 0;
insnPC <= 0;
reg_lock[0] <= 0;
reg_lock_by[0] <= 0;
for(i=1; i<32; i=i+1) begin
reg_file[i] <= 0;
reg_lock[i] <= 0;
reg_lock_by[i] <= 0;
end
for(i=0; i<8; i=i+1) begin
insn_data_overrided[i] <= 1;
insn_write_reg[i] <= 0;
end
next_insnPC <= 0;
alu_opcode <= 0;
alu_src1 <= 0;
alu_src2 <= 0;
alu_src1_forward <= 0;
alu_src1_forward_from <= 0;
alu_src2_forward <= 0;
alu_src2_forward_from <= 0;
mem_opcode <= 0;
mem_src2 <= 0;
mem_src2_forward <= 0;
mem_src2_forward_from <= 0;
insn_id <= 0;
next_insn_id <= 0;
next_insn_write_reg_pending <= 0;
last_next_insn <= 0;
last_next_insn_enabled <= 0;
last_drop_next_insn <= 0;
clear_next_insn <= 1;
end else begin
if(writeback_flag) begin
if(writeback_reg == 0)
$display("Assertion Failed: Writeback_reg == 0");
reg_file[writeback_reg] <= writeback_data;
reg_lock[writeback_reg] <= 0;
end
if(alu_forward_flag) begin
if(alu_forward_reg == 0)
$display("Assertion Failed: ALU_forward_reg == 0");
reg_file[alu_forward_reg] <= alu_forward_data;
reg_lock[alu_forward_reg] <= 0;
end
if(!prev_busy) begin
insn = prev_insn;
insnPC = prev_insnPC;
if(next_insn_write_reg != 0) begin
insn_write_reg[next_insn_id] <= next_insn_write_reg;
insn_data_overrided[next_insn_id] <= 0;
reg_lock[next_insn_write_reg] <= 1;
if(reg_lock[next_insn_write_reg])
insn_data_overrided[reg_lock_by[next_insn_write_reg]] <= 1;
reg_lock_by[next_insn_write_reg] <= next_insn_id;
end else begin
insn_write_reg[next_insn_id] <= 0;
insn_data_overrided[next_insn_id] <= 1;
end
end
opcode = insn[31:26];
rs = insn[25:21];
rt = insn[20:16];
rd = insn[15:11];
sa = insn[10:6];
opfunc = insn[5:0];
imm = insn[15:0];
j_addr = insn[25:0];
case(1'b1)
writeback_flag && rs == writeback_reg: begin
GPR_rs = writeback_data;
rs_lock = 0;
rs_lock_by = 0;
end
alu_forward_flag && rs == alu_forward_reg: begin
GPR_rs = alu_forward_data;
rs_lock = 0;
rs_lock_by = 0;
end
default: begin
GPR_rs = GPR[rs];
rs_lock = reg_lock[rs];
rs_lock_by = reg_lock_by[rs];
end
endcase
case(1'b1)
writeback_flag && rt == writeback_reg: begin
GPR_rt = writeback_data;
rt_lock = 0;
rt_lock_by = 0;
end
alu_forward_flag && rt == alu_forward_reg: begin
GPR_rt = alu_forward_data;
rt_lock = 0;
rt_lock_by = 0;
end
default: begin
GPR_rt = GPR[rt];
rt_lock = reg_lock[rt];
rt_lock_by = reg_lock_by[rt];
end
endcase
if(!prev_busy) begin
if(next_insn_write_reg != 0 && rs == next_insn_write_reg) begin
rs_lock = 1;
rs_lock_by = next_insn_id;
end
if(next_insn_write_reg != 0 && rt == next_insn_write_reg) begin
rt_lock = 1;
rt_lock_by = next_insn_id;
end
end
insnPC_add_4 = insnPC + 4;
Branch_target <= insnPC_add_4 + {{14{imm[15]}}, imm, 2'b00};
BC_target <= insnPC_add_4 + {{14{imm[15]}}, imm, 2'b00};
BC_long_target <= insnPC_add_4 + {{9{rt[4]}}, rt, imm, 2'b00};
J_target <= {insnPC_add_4[31:28], rs, rt, imm, 2'b00};
BC_very_long_target <= insnPC_add_4 + {{4{rs[4]}}, rs, rt, imm, 2'b00};
jump_cond_basic[0] <= GPR_rs == GPR_rt;
jump_cond_basic[1] <= GPR_rs > GPR_rt;
jump_cond_basic[2] <= $signed(GPR_rs) > $signed(GPR_rt);
jump_cond_basic[3] <= GPR_rs == 0;
jump_cond_basic[4] <= $signed(GPR_rs) > 0;
jump_cond_basic[5] <= GPR_rt == 0;
jump_cond_basic[6] <= $signed(GPR_rt) > 0;
if(rt == 0)
POP_insn_type = rs_lock ? 4'd8 : 4'd0;
else if(rs == 0)
POP_insn_type = rt_lock ? 4'd8 : 4'd1;
else if(rs == rt)
POP_insn_type = rt_lock ? 4'd8 : 4'd2;
else
POP_insn_type = rs_lock || rt_lock ? 4'd8 : 4'd4;
tmp_busy = 0;
case(opcode)
OPCD_SPECIAL: begin
if(opfunc == OPFUNC_JR || opfunc == OPFUNC_JALR)
tmp_busy = rs_lock;
end
OPCD_REGIMM: tmp_busy = rs_lock;
OPCD_BEQ, OPCD_BNE: tmp_busy = rs_lock || rt_lock;
OPCD_POP06, OPCD_POP07,
OPCD_POP10, OPCD_POP26,
OPCD_POP27, OPCD_POP30,
OPCD_POP66, OPCD_POP76: tmp_busy = POP_insn_type[3];
endcase
busy <= tmp_busy;
jump_cond_id <= NEVER;
jump_type <= JUMP_J;
clear_next_insn <= 0;
if(!prev_placeholder_insn) begin
clear_next_insn <= 1;
end
if(!next_busy) begin
if(insn_id == 3'b011)
insn_id = 0;
else
insn_id = insn_id + 1;
end
next_insn_write_reg_pending <= 0;
alu_opcode <= `ALU_NOP;
alu_src1 <= 0;
alu_src2 <= 0;
alu_src1_forward <= 0;
alu_src2_forward <= 0;
alu_src1_forward_from <= 0;
alu_src2_forward_from <= 0;
mem_opcode <= `MEM_NOP;
mem_src2 <= 0;
mem_src2_forward <= 0;
mem_src2_forward_from <= 0;
next_insnPC <= insnPC;
next_insn_id <= busy ? 3'b111 : insn_id;
if(!drop_next_insn && !tmp_busy) begin
case(opcode)
OPCD_SPECIAL: begin
case(opfunc)
OPFUNC_ADD: decode_rtype(rd, 1, 1, `ALU_ADD, `MEM_NOP);
OPFUNC_ADDU: decode_rtype(rd, 1, 1, `ALU_ADDU, `MEM_NOP);
OPFUNC_SUB: decode_rtype(rd, 1, 1, `ALU_SUB, `MEM_NOP);
OPFUNC_SUBU: decode_rtype(rd, 1, 1, `ALU_SUBU, `MEM_NOP);
OPFUNC_SLLV: decode_rtype(rd, 1, 1, `ALU_SLL, `MEM_NOP);
OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);
OPFUNC_SRAV: decode_rtype(rd, 1, 1, `ALU_SRA, `MEM_NOP);
OPFUNC_AND: decode_rtype(rd, 1, 1, `ALU_AND, `MEM_NOP);
OPFUNC_OR: decode_rtype(rd, 1, 1, `ALU_OR, `MEM_NOP);
OPFUNC_NOR: decode_rtype(rd, 1, 1, `ALU_NOR, `MEM_NOP);
OPFUNC_XOR: decode_rtype(rd, 1, 1, `ALU_XOR, `MEM_NOP);
OPFUNC_SLL: begin
decode_rtype(rd, 0, 1, `ALU_SLL, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SRL: begin
decode_rtype(rd, 0, 1, rs == 5'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SRA: begin
decode_rtype(rd, 0, 1, `ALU_SRA, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SOP30: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_MULTL, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MULTH, `MEM_NOP);
end
OPFUNC_SOP31: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_MULTLU, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MULTHU, `MEM_NOP);
end
OPFUNC_SOP32: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_DIV, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MOD, `MEM_NOP);
end
OPFUNC_SOP33: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_DIVU, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MODU, `MEM_NOP);
end
OPFUNC_JR: begin
begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_GPR_RS;
end
end
OPFUNC_JALR: begin
begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_GPR_RS;
alu_src1 <= insnPC + 8;
write_register(31);
end
end
OPFUNC_SLT: decode_rtype(rd, 1, 1, `ALU_SLT, `MEM_NOP);
OPFUNC_SLTU: decode_rtype(rd, 1, 1, `ALU_SLTU, `MEM_NOP);
default:;
endcase
end
OPCD_ADDIU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_NOP);
OPCD_ANDI: decode_itype(rt, 1, 0, `ALU_AND, `MEM_NOP);
OPCD_ORI: decode_itype(rt, 1, 0, `ALU_OR, `MEM_NOP);
OPCD_XORI: decode_itype(rt, 1, 0, `ALU_XOR, `MEM_NOP);
OPCD_BEQ: begin
begin
jump_cond_id <= RS_EQ_RT;
jump_type <= JUMP_J;
end
end
OPCD_BNE: begin
begin
jump_cond_id <= RS_NE_RT;
jump_type <= JUMP_J;
end
end
OPCD_J: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_J_LONG;
end
OPCD_JAL: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_J_LONG;
alu_src1 <= insnPC + 8;
write_register(31);
end
OPCD_BC: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_BC_VERY_LONG;
end
OPCD_BALC: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_BC_VERY_LONG;
alu_src1 <= insnPC + 4;
write_register(31);
end
OPCD_REGIMM: begin
if(rt[0]) begin
begin
jump_cond_id <= RS_GE_ZERO;
jump_type <= JUMP_J;
end
end elsebegin
begin
jump_cond_id <= RS_LT_ZERO;
jump_type <= JUMP_J;
end
end
end
OPCD_POP06: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_LE_ZERO;
jump_type <= JUMP_J;
end
1: begin
jump_cond_id <= RT_LE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
2: begin
jump_cond_id <= RT_GE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_GEU_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP07: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_GT_ZERO;
jump_type <= JUMP_J;
end
1: begin
jump_cond_id <= RT_GT_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
2: begin
jump_cond_id <= RT_LT_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_LTU_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP10: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_EQ_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_EQ_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP30: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_NE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_NE_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP26: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_LE_ZERO;
jump_type <= JUMP_BC;
end
2: begin
jump_cond_id <= RT_GE_ZERO;
jump_type <= JUMP_BC;
end
4: begin
jump_cond_id <= RS_GE_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP27: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_GT_ZERO;
jump_type <= JUMP_BC;
end
2: begin
jump_cond_id <= RT_LT_ZERO;
jump_type <= JUMP_BC;
end
4: begin
jump_cond_id <= RS_LT_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP66: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_EQ_ZERO;
jump_type <= JUMP_BC_LONG;
end
endcase
end
OPCD_POP76: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_NE_ZERO;
jump_type <= JUMP_BC_LONG;
end
endcase
end
OPCD_SLTI: decode_itype(rt, 1, 1, `ALU_SLT, `MEM_NOP);
OPCD_SLTIU: decode_itype(rt, 1, 1, `ALU_SLTU, `MEM_NOP);
OPCD_LB: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LB);
OPCD_LBU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LBU);
OPCD_LH: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LH);
OPCD_LHU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LHU);
OPCD_LW: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LW);
OPCD_SB: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SB);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_SH: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SH);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_SW: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SW);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_AUI: begin
fetch_rs();
alu_src2 <= {imm, 16'b0};
alu_opcode <= `ALU_ADDU;
write_register(rt);
end
default:;
endcase
end
last_next_insn <= prev_next_insn;
last_next_insn_enabled <= prev_next_insn_enabled;
last_drop_next_insn <= drop_next_insn;
end
end
always @(*) begin
prev_next_insn = last_next_insn;
prev_next_insn_enabled = last_next_insn_enabled;
drop_next_insn = last_drop_next_insn;
if(clear_next_insn) begin
prev_next_insn = 0;
prev_next_insn_enabled = 0;
drop_next_insn = 0;
end
next_insn_write_reg = next_insn_write_reg_pending;
jump_cond[0] = 0;
jump_cond[1] = 1;
jump_cond[2] = jump_cond_basic[0];
jump_cond[3] = !jump_cond_basic[0];
jump_cond[4] = jump_cond_basic[1];
jump_cond[5] = !(jump_cond_basic[0] || jump_cond_basic[1]);
jump_cond[6] = jump_cond_basic[0] || jump_cond_basic[1];
jump_cond[7] = !jump_cond_basic[1];
jump_cond[8] = jump_cond_basic[2];
jump_cond[9] = !(jump_cond_basic[0] || jump_cond_basic[2]);
jump_cond[10] = jump_cond_basic[0] || jump_cond_basic[2];
jump_cond[11] = !jump_cond_basic[2];
jump_cond[12] = jump_cond_basic[3];
jump_cond[13] = !jump_cond_basic[3];
jump_cond[14] = jump_cond_basic[4];
jump_cond[15] = !(jump_cond_basic[3] || jump_cond_basic[4]);
jump_cond[16] = jump_cond_basic[3] || jump_cond_basic[4];
jump_cond[17] = !jump_cond_basic[4];
jump_cond[18] = jump_cond_basic[5];
jump_cond[19] = !jump_cond_basic[5];
jump_cond[20] = jump_cond_basic[6];
jump_cond[21] = !(jump_cond_basic[5] || jump_cond_basic[6]);
jump_cond[22] = jump_cond_basic[5] || jump_cond_basic[6];
jump_cond[23] = !jump_cond_basic[6];
if(jump_cond[jump_cond_id]) begin
case(jump_type)
JUMP_J: begin
prev_next_insn = Branch_target;
prev_next_insn_enabled = 1;
end
JUMP_BC: begin
prev_next_insn = BC_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
JUMP_BALC: begin
prev_next_insn = BC_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
next_insn_write_reg = 31;
end
JUMP_BC_LONG: begin
prev_next_insn = BC_long_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
JUMP_GPR_RS: begin
prev_next_insn = GPR_rs;
prev_next_insn_enabled = 1;
end
JUMP_J_LONG: begin
prev_next_insn = J_target;
prev_next_insn_enabled = 1;
end
JUMP_BC_VERY_LONG: begin
prev_next_insn = BC_very_long_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
default:;
endcase
end
end
endmodule | module pipeline_decode(
input CLK,
input RST,
input [31:0] prev_insn,
input [31:0] prev_insnPC,
input prev_placeholder_insn,
output reg prev_next_insn_enabled,
output reg [31:0] prev_next_insn,
output prev_busy,
input next_busy,
output reg [31:0] next_insnPC,
output reg [2:0] next_insn_id,
output reg [`ALU_OPCODE_WIDTH-1:0] alu_opcode,
output reg [31:0] alu_src1,
output reg alu_src1_forward,
output reg [2:0] alu_src1_forward_from,
output reg [31:0] alu_src2,
output reg alu_src2_forward,
output reg [2:0] alu_src2_forward_from,
output reg [`MEM_OPCODE_WIDTH-1:0] mem_opcode,
output reg [31:0] mem_src2,
output reg mem_src2_forward,
output reg [2:0] mem_src2_forward_from,
input [2:0] writeback_insn_id,
input [31:0] writeback_data,
input [2:0] alu_forward_insn_id,
input [31:0] alu_forward_data
); |
localparam OPCD_SPECIAL = 6'h00;
localparam OPCD_REGIMM = 6'h01;
localparam OPCD_BEQ = 6'h04;
localparam OPCD_BNE = 6'h05;
localparam OPCD_POP06 = 6'h06;
localparam OPCD_POP07 = 6'h07;
localparam OPCD_POP10 = 6'h08;
localparam OPCD_ADDIU = 6'h09;
localparam OPCD_SLTI = 6'h0A;
localparam OPCD_SLTIU = 6'h0B;
localparam OPCD_ANDI = 6'h0C;
localparam OPCD_ORI = 6'h0D;
localparam OPCD_XORI = 6'h0E;
localparam OPCD_AUI = 6'h0F;
localparam OPCD_POP26 = 6'h16;
localparam OPCD_POP27 = 6'h17;
localparam OPCD_POP30 = 6'h18;
localparam OPCD_LB = 6'h20;
localparam OPCD_LH = 6'h21;
localparam OPCD_LW = 6'h23;
localparam OPCD_LBU = 6'h24;
localparam OPCD_LHU = 6'h25;
localparam OPCD_SB = 6'h28;
localparam OPCD_SH = 6'h29;
localparam OPCD_SW = 6'h2B;
localparam OPCD_LWC1 = 6'h31;
localparam OPCD_SWC1 = 6'h39;
localparam OPCD_J = 6'h02;
localparam OPCD_JAL = 6'h03;
localparam OPCD_BC = 6'h32;
localparam OPCD_POP66 = 6'h36;
localparam OPCD_BALC = 6'h3A;
localparam OPCD_POP76 = 6'h3E;
localparam OPFUNC_SLL = 6'h00;
localparam OPFUNC_SRL = 6'h02;
localparam OPFUNC_SRA = 6'h03;
localparam OPFUNC_SLLV = 6'h04;
localparam OPFUNC_SRLV = 6'h06;
localparam OPFUNC_SRAV = 6'h07;
localparam OPFUNC_JR = 6'h08;
localparam OPFUNC_JALR = 6'h09;
localparam OPFUNC_SYSCALL = 6'h0C;
localparam OPFUNC_BREAK = 6'h0D;
localparam OPFUNC_SOP30 = 6'h18;
localparam OPFUNC_SOP31 = 6'h19;
localparam OPFUNC_SOP32 = 6'h1A;
localparam OPFUNC_SOP33 = 6'h1B;
localparam OPFUNC_ADD = 6'h20;
localparam OPFUNC_ADDU = 6'h21;
localparam OPFUNC_SUB = 6'h22;
localparam OPFUNC_SUBU = 6'h23;
localparam OPFUNC_AND = 6'h24;
localparam OPFUNC_OR = 6'h25;
localparam OPFUNC_XOR = 6'h26;
localparam OPFUNC_NOR = 6'h27;
localparam OPFUNC_SLT = 6'h2A;
localparam OPFUNC_SLTU = 6'h2B;
reg [31:0] insn;
reg [31:0] insnPC;
reg [2:0] insn_id;
reg [4:0] insn_write_reg[7:0];
reg insn_data_overrided[7:0];
reg [31:0] reg_file[31:1];
wire [31:0] GPR[31:0];
reg reg_lock[31:0];
reg [2:0] reg_lock_by[31:0];
reg [4:0] next_insn_write_reg;
reg [4:0] next_insn_write_reg_pending;
genvar j;
generate
for(j=1; j<32; j=j+1)
assign GPR[j] = reg_file[j];
endgenerate
assign GPR[0] = 0;
reg busy;
assign prev_busy = busy || next_busy;
wire writeback_flag =!insn_data_overrided[writeback_insn_id];
wire alu_forward_flag =!insn_data_overrided[alu_forward_insn_id];
wire [4:0] writeback_reg = insn_write_reg[writeback_insn_id];
wire [4:0] alu_forward_reg = insn_write_reg[alu_forward_insn_id];
integer i;
task write_register;
input [4:0] regid;
begin
next_insn_write_reg_pending <= regid;
end
endtask
reg drop_next_insn;
localparam NEVER = 0;
localparam ALWAYS = 1;
localparam RS_EQ_RT = 2;
localparam RS_NE_RT = 3;
localparam RS_GTU_RT = 4;
localparam RS_LTU_RT = 5;
localparam RS_GEU_RT = 6;
localparam RS_LEU_RT = 7;
localparam RS_GT_RT = 8;
localparam RS_LT_RT = 9;
localparam RS_GE_RT = 10;
localparam RS_LE_RT = 11;
localparam RS_EQ_ZERO = 12;
localparam RS_NE_ZERO = 13;
localparam RS_GT_ZERO = 14;
localparam RS_LT_ZERO = 15;
localparam RS_GE_ZERO = 16;
localparam RS_LE_ZERO = 17;
localparam RT_EQ_ZERO = 18;
localparam RT_NE_ZERO = 19;
localparam RT_GT_ZERO = 20;
localparam RT_LT_ZERO = 21;
localparam RT_GE_ZERO = 22;
localparam RT_LE_ZERO = 23;
reg [23:0] jump_cond;
reg [6:0] jump_cond_basic;
reg [4:0] jump_cond_id;
localparam JUMP_J = 0;
localparam JUMP_BC = 1;
localparam JUMP_BALC = 2;
localparam JUMP_BC_LONG = 4;
localparam JUMP_J_LONG = 8;
localparam JUMP_BC_VERY_LONG = 16;
localparam JUMP_GPR_RS = 32;
reg [5:0] jump_type;
reg [3:0] POP_insn_type;
reg [31:0] Branch_target;
reg [31:0] BC_target;
reg [31:0] BC_long_target;
reg [31:0] J_target;
reg [31:0] BC_very_long_target;
reg [31:0] GPR_rs, GPR_rt;
reg rs_lock, rt_lock;
reg [2:0] rs_lock_by, rt_lock_by;
reg [5:0] opcode;
reg [4:0] rs, rt, rd, sa;
reg [5:0] opfunc;
reg [15:0] imm;
reg [25:0] j_addr;
task fetch_rs;
begin
alu_src1 <= GPR_rs;
alu_src1_forward <= rs_lock;
alu_src1_forward_from <= rs_lock_by;
end
endtask
task fetch_rt;
begin
alu_src2 <= GPR_rt;
alu_src2_forward <= rt_lock;
alu_src2_forward_from <= rt_lock_by;
end
endtask
task decode_rtype;
input [4:0] dst;
input use_src1;
input use_src2;
input [`ALU_OPCODE_WIDTH-1:0] alu_op;
input [`MEM_OPCODE_WIDTH-1:0] mem_op;
begin
if(use_src1) begin
fetch_rs();
end
if(use_src2) begin
fetch_rt();
end
alu_opcode <= alu_op;
mem_opcode <= mem_op;
write_register(dst);
end
endtask
task decode_itype;
input [4:0] dst;
input use_src1;
input sign_extend;
input [`ALU_OPCODE_WIDTH-1:0] alu_op;
input [`MEM_OPCODE_WIDTH-1:0] mem_op;
begin
if(use_src1) begin
fetch_rs();
end
if(sign_extend)
alu_src2 <= {{16{imm[15]}}, imm};
else
alu_src2 <= {16'b0, imm};
alu_opcode <= alu_op;
mem_opcode <= mem_op;
write_register(dst);
end
endtask
reg tmp_busy;
reg [31:0] tmp_GPR_rs, tmp_GPR_rt;
reg clear_next_insn;
reg [31:0] last_next_insn;
reg last_next_insn_enabled;
reg last_drop_next_insn;
reg [31:0] insnPC_add_4;
always @(posedge CLK or posedge RST) begin
if(RST) begin
insn <= 0;
insnPC <= 0;
reg_lock[0] <= 0;
reg_lock_by[0] <= 0;
for(i=1; i<32; i=i+1) begin
reg_file[i] <= 0;
reg_lock[i] <= 0;
reg_lock_by[i] <= 0;
end
for(i=0; i<8; i=i+1) begin
insn_data_overrided[i] <= 1;
insn_write_reg[i] <= 0;
end
next_insnPC <= 0;
alu_opcode <= 0;
alu_src1 <= 0;
alu_src2 <= 0;
alu_src1_forward <= 0;
alu_src1_forward_from <= 0;
alu_src2_forward <= 0;
alu_src2_forward_from <= 0;
mem_opcode <= 0;
mem_src2 <= 0;
mem_src2_forward <= 0;
mem_src2_forward_from <= 0;
insn_id <= 0;
next_insn_id <= 0;
next_insn_write_reg_pending <= 0;
last_next_insn <= 0;
last_next_insn_enabled <= 0;
last_drop_next_insn <= 0;
clear_next_insn <= 1;
end else begin
if(writeback_flag) begin
if(writeback_reg == 0)
$display("Assertion Failed: Writeback_reg == 0");
reg_file[writeback_reg] <= writeback_data;
reg_lock[writeback_reg] <= 0;
end
if(alu_forward_flag) begin
if(alu_forward_reg == 0)
$display("Assertion Failed: ALU_forward_reg == 0");
reg_file[alu_forward_reg] <= alu_forward_data;
reg_lock[alu_forward_reg] <= 0;
end
if(!prev_busy) begin
insn = prev_insn;
insnPC = prev_insnPC;
if(next_insn_write_reg != 0) begin
insn_write_reg[next_insn_id] <= next_insn_write_reg;
insn_data_overrided[next_insn_id] <= 0;
reg_lock[next_insn_write_reg] <= 1;
if(reg_lock[next_insn_write_reg])
insn_data_overrided[reg_lock_by[next_insn_write_reg]] <= 1;
reg_lock_by[next_insn_write_reg] <= next_insn_id;
end else begin
insn_write_reg[next_insn_id] <= 0;
insn_data_overrided[next_insn_id] <= 1;
end
end
opcode = insn[31:26];
rs = insn[25:21];
rt = insn[20:16];
rd = insn[15:11];
sa = insn[10:6];
opfunc = insn[5:0];
imm = insn[15:0];
j_addr = insn[25:0];
case(1'b1)
writeback_flag && rs == writeback_reg: begin
GPR_rs = writeback_data;
rs_lock = 0;
rs_lock_by = 0;
end
alu_forward_flag && rs == alu_forward_reg: begin
GPR_rs = alu_forward_data;
rs_lock = 0;
rs_lock_by = 0;
end
default: begin
GPR_rs = GPR[rs];
rs_lock = reg_lock[rs];
rs_lock_by = reg_lock_by[rs];
end
endcase
case(1'b1)
writeback_flag && rt == writeback_reg: begin
GPR_rt = writeback_data;
rt_lock = 0;
rt_lock_by = 0;
end
alu_forward_flag && rt == alu_forward_reg: begin
GPR_rt = alu_forward_data;
rt_lock = 0;
rt_lock_by = 0;
end
default: begin
GPR_rt = GPR[rt];
rt_lock = reg_lock[rt];
rt_lock_by = reg_lock_by[rt];
end
endcase
if(!prev_busy) begin
if(next_insn_write_reg != 0 && rs == next_insn_write_reg) begin
rs_lock = 1;
rs_lock_by = next_insn_id;
end
if(next_insn_write_reg != 0 && rt == next_insn_write_reg) begin
rt_lock = 1;
rt_lock_by = next_insn_id;
end
end
insnPC_add_4 = insnPC + 4;
Branch_target <= insnPC_add_4 + {{14{imm[15]}}, imm, 2'b00};
BC_target <= insnPC_add_4 + {{14{imm[15]}}, imm, 2'b00};
BC_long_target <= insnPC_add_4 + {{9{rt[4]}}, rt, imm, 2'b00};
J_target <= {insnPC_add_4[31:28], rs, rt, imm, 2'b00};
BC_very_long_target <= insnPC_add_4 + {{4{rs[4]}}, rs, rt, imm, 2'b00};
jump_cond_basic[0] <= GPR_rs == GPR_rt;
jump_cond_basic[1] <= GPR_rs > GPR_rt;
jump_cond_basic[2] <= $signed(GPR_rs) > $signed(GPR_rt);
jump_cond_basic[3] <= GPR_rs == 0;
jump_cond_basic[4] <= $signed(GPR_rs) > 0;
jump_cond_basic[5] <= GPR_rt == 0;
jump_cond_basic[6] <= $signed(GPR_rt) > 0;
if(rt == 0)
POP_insn_type = rs_lock ? 4'd8 : 4'd0;
else if(rs == 0)
POP_insn_type = rt_lock ? 4'd8 : 4'd1;
else if(rs == rt)
POP_insn_type = rt_lock ? 4'd8 : 4'd2;
else
POP_insn_type = rs_lock || rt_lock ? 4'd8 : 4'd4;
tmp_busy = 0;
case(opcode)
OPCD_SPECIAL: begin
if(opfunc == OPFUNC_JR || opfunc == OPFUNC_JALR)
tmp_busy = rs_lock;
end
OPCD_REGIMM: tmp_busy = rs_lock;
OPCD_BEQ, OPCD_BNE: tmp_busy = rs_lock || rt_lock;
OPCD_POP06, OPCD_POP07,
OPCD_POP10, OPCD_POP26,
OPCD_POP27, OPCD_POP30,
OPCD_POP66, OPCD_POP76: tmp_busy = POP_insn_type[3];
endcase
busy <= tmp_busy;
jump_cond_id <= NEVER;
jump_type <= JUMP_J;
clear_next_insn <= 0;
if(!prev_placeholder_insn) begin
clear_next_insn <= 1;
end
if(!next_busy) begin
if(insn_id == 3'b011)
insn_id = 0;
else
insn_id = insn_id + 1;
end
next_insn_write_reg_pending <= 0;
alu_opcode <= `ALU_NOP;
alu_src1 <= 0;
alu_src2 <= 0;
alu_src1_forward <= 0;
alu_src2_forward <= 0;
alu_src1_forward_from <= 0;
alu_src2_forward_from <= 0;
mem_opcode <= `MEM_NOP;
mem_src2 <= 0;
mem_src2_forward <= 0;
mem_src2_forward_from <= 0;
next_insnPC <= insnPC;
next_insn_id <= busy ? 3'b111 : insn_id;
if(!drop_next_insn && !tmp_busy) begin
case(opcode)
OPCD_SPECIAL: begin
case(opfunc)
OPFUNC_ADD: decode_rtype(rd, 1, 1, `ALU_ADD, `MEM_NOP);
OPFUNC_ADDU: decode_rtype(rd, 1, 1, `ALU_ADDU, `MEM_NOP);
OPFUNC_SUB: decode_rtype(rd, 1, 1, `ALU_SUB, `MEM_NOP);
OPFUNC_SUBU: decode_rtype(rd, 1, 1, `ALU_SUBU, `MEM_NOP);
OPFUNC_SLLV: decode_rtype(rd, 1, 1, `ALU_SLL, `MEM_NOP);
OPFUNC_SRLV: decode_rtype(rd, 1, 1, sa == 5'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);
OPFUNC_SRAV: decode_rtype(rd, 1, 1, `ALU_SRA, `MEM_NOP);
OPFUNC_AND: decode_rtype(rd, 1, 1, `ALU_AND, `MEM_NOP);
OPFUNC_OR: decode_rtype(rd, 1, 1, `ALU_OR, `MEM_NOP);
OPFUNC_NOR: decode_rtype(rd, 1, 1, `ALU_NOR, `MEM_NOP);
OPFUNC_XOR: decode_rtype(rd, 1, 1, `ALU_XOR, `MEM_NOP);
OPFUNC_SLL: begin
decode_rtype(rd, 0, 1, `ALU_SLL, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SRL: begin
decode_rtype(rd, 0, 1, rs == 5'h01 ? `ALU_ROR : `ALU_SRL, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SRA: begin
decode_rtype(rd, 0, 1, `ALU_SRA, `MEM_NOP);
alu_src1 <= {27'b0, sa};
end
OPFUNC_SOP30: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_MULTL, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MULTH, `MEM_NOP);
end
OPFUNC_SOP31: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_MULTLU, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MULTHU, `MEM_NOP);
end
OPFUNC_SOP32: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_DIV, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MOD, `MEM_NOP);
end
OPFUNC_SOP33: begin
if(sa == 5'b00010)
decode_rtype(rd, 1, 1, `ALU_DIVU, `MEM_NOP);
else if(sa == 5'b00011)
decode_rtype(rd, 1, 1, `ALU_MODU, `MEM_NOP);
end
OPFUNC_JR: begin
begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_GPR_RS;
end
end
OPFUNC_JALR: begin
begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_GPR_RS;
alu_src1 <= insnPC + 8;
write_register(31);
end
end
OPFUNC_SLT: decode_rtype(rd, 1, 1, `ALU_SLT, `MEM_NOP);
OPFUNC_SLTU: decode_rtype(rd, 1, 1, `ALU_SLTU, `MEM_NOP);
default:;
endcase
end
OPCD_ADDIU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_NOP);
OPCD_ANDI: decode_itype(rt, 1, 0, `ALU_AND, `MEM_NOP);
OPCD_ORI: decode_itype(rt, 1, 0, `ALU_OR, `MEM_NOP);
OPCD_XORI: decode_itype(rt, 1, 0, `ALU_XOR, `MEM_NOP);
OPCD_BEQ: begin
begin
jump_cond_id <= RS_EQ_RT;
jump_type <= JUMP_J;
end
end
OPCD_BNE: begin
begin
jump_cond_id <= RS_NE_RT;
jump_type <= JUMP_J;
end
end
OPCD_J: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_J_LONG;
end
OPCD_JAL: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_J_LONG;
alu_src1 <= insnPC + 8;
write_register(31);
end
OPCD_BC: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_BC_VERY_LONG;
end
OPCD_BALC: begin
jump_cond_id <= ALWAYS;
jump_type <= JUMP_BC_VERY_LONG;
alu_src1 <= insnPC + 4;
write_register(31);
end
OPCD_REGIMM: begin
if(rt[0]) begin
begin
jump_cond_id <= RS_GE_ZERO;
jump_type <= JUMP_J;
end
end elsebegin
begin
jump_cond_id <= RS_LT_ZERO;
jump_type <= JUMP_J;
end
end
end
OPCD_POP06: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_LE_ZERO;
jump_type <= JUMP_J;
end
1: begin
jump_cond_id <= RT_LE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
2: begin
jump_cond_id <= RT_GE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_GEU_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP07: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_GT_ZERO;
jump_type <= JUMP_J;
end
1: begin
jump_cond_id <= RT_GT_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
2: begin
jump_cond_id <= RT_LT_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_LTU_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP10: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_EQ_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_EQ_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP30: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_NE_ZERO;
jump_type <= JUMP_BALC;
alu_src1 <= insnPC + 4;
end
4: begin
jump_cond_id <= RS_NE_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP26: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_LE_ZERO;
jump_type <= JUMP_BC;
end
2: begin
jump_cond_id <= RT_GE_ZERO;
jump_type <= JUMP_BC;
end
4: begin
jump_cond_id <= RS_GE_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP27: begin
case(POP_insn_type)
1: begin
jump_cond_id <= RT_GT_ZERO;
jump_type <= JUMP_BC;
end
2: begin
jump_cond_id <= RT_LT_ZERO;
jump_type <= JUMP_BC;
end
4: begin
jump_cond_id <= RS_LT_RT;
jump_type <= JUMP_BC;
end
endcase
end
OPCD_POP66: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_EQ_ZERO;
jump_type <= JUMP_BC_LONG;
end
endcase
end
OPCD_POP76: begin
case(POP_insn_type)
0: begin
jump_cond_id <= RS_NE_ZERO;
jump_type <= JUMP_BC_LONG;
end
endcase
end
OPCD_SLTI: decode_itype(rt, 1, 1, `ALU_SLT, `MEM_NOP);
OPCD_SLTIU: decode_itype(rt, 1, 1, `ALU_SLTU, `MEM_NOP);
OPCD_LB: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LB);
OPCD_LBU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LBU);
OPCD_LH: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LH);
OPCD_LHU: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LHU);
OPCD_LW: decode_itype(rt, 1, 1, `ALU_ADDU, `MEM_LW);
OPCD_SB: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SB);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_SH: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SH);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_SW: begin
decode_itype(0, 1, 1, `ALU_ADDU, `MEM_SW);
mem_src2 <= GPR_rt;
mem_src2_forward <= rt_lock;
mem_src2_forward_from <= rt_lock_by;
end
OPCD_AUI: begin
fetch_rs();
alu_src2 <= {imm, 16'b0};
alu_opcode <= `ALU_ADDU;
write_register(rt);
end
default:;
endcase
end
last_next_insn <= prev_next_insn;
last_next_insn_enabled <= prev_next_insn_enabled;
last_drop_next_insn <= drop_next_insn;
end
end
always @(*) begin
prev_next_insn = last_next_insn;
prev_next_insn_enabled = last_next_insn_enabled;
drop_next_insn = last_drop_next_insn;
if(clear_next_insn) begin
prev_next_insn = 0;
prev_next_insn_enabled = 0;
drop_next_insn = 0;
end
next_insn_write_reg = next_insn_write_reg_pending;
jump_cond[0] = 0;
jump_cond[1] = 1;
jump_cond[2] = jump_cond_basic[0];
jump_cond[3] = !jump_cond_basic[0];
jump_cond[4] = jump_cond_basic[1];
jump_cond[5] = !(jump_cond_basic[0] || jump_cond_basic[1]);
jump_cond[6] = jump_cond_basic[0] || jump_cond_basic[1];
jump_cond[7] = !jump_cond_basic[1];
jump_cond[8] = jump_cond_basic[2];
jump_cond[9] = !(jump_cond_basic[0] || jump_cond_basic[2]);
jump_cond[10] = jump_cond_basic[0] || jump_cond_basic[2];
jump_cond[11] = !jump_cond_basic[2];
jump_cond[12] = jump_cond_basic[3];
jump_cond[13] = !jump_cond_basic[3];
jump_cond[14] = jump_cond_basic[4];
jump_cond[15] = !(jump_cond_basic[3] || jump_cond_basic[4]);
jump_cond[16] = jump_cond_basic[3] || jump_cond_basic[4];
jump_cond[17] = !jump_cond_basic[4];
jump_cond[18] = jump_cond_basic[5];
jump_cond[19] = !jump_cond_basic[5];
jump_cond[20] = jump_cond_basic[6];
jump_cond[21] = !(jump_cond_basic[5] || jump_cond_basic[6]);
jump_cond[22] = jump_cond_basic[5] || jump_cond_basic[6];
jump_cond[23] = !jump_cond_basic[6];
if(jump_cond[jump_cond_id]) begin
case(jump_type)
JUMP_J: begin
prev_next_insn = Branch_target;
prev_next_insn_enabled = 1;
end
JUMP_BC: begin
prev_next_insn = BC_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
JUMP_BALC: begin
prev_next_insn = BC_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
next_insn_write_reg = 31;
end
JUMP_BC_LONG: begin
prev_next_insn = BC_long_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
JUMP_GPR_RS: begin
prev_next_insn = GPR_rs;
prev_next_insn_enabled = 1;
end
JUMP_J_LONG: begin
prev_next_insn = J_target;
prev_next_insn_enabled = 1;
end
JUMP_BC_VERY_LONG: begin
prev_next_insn = BC_very_long_target;
prev_next_insn_enabled = 1;
drop_next_insn = 1;
end
default:;
endcase
end
end
endmodule | 50 |
3,206 | data/full_repos/permissive/103257524/src/cpu/pipeline_insnfetch.v | 103,257,524 | pipeline_insnfetch.v | v | 109 | 83 | [] | [] | [] | [(23, 108)] | null | data/verilator_xmls/94c834e1-3c97-4f03-b015-4e6500637f9c.xml | null | 994 | module | module pipeline_insnfetch(
input CLK,
input RST,
output read_flag,
output [31:0] addr,
input [31:0] read_data,
input busy,
input done,
input next_insn_enabled,
input [31:0] next_insn,
input busy_in,
output reg [31:0] insn,
output reg [31:0] insnPC,
output reg placeholder_insn
);
reg [31:0] PC;
wire [31:0] nextPC;
assign nextPC = next_insn_enabled ? next_insn : PC + 4;
assign addr = nextPC;
assign read_flag = !busy_in && !busy;
always @(posedge CLK or posedge RST) begin
if(RST) begin
PC <= -32'd4;
end else if(!busy_in && !busy) begin
PC <= nextPC;
end
end
always @(*) begin
if(!busy) begin
insn = read_data;
insnPC = PC;
placeholder_insn = 0;
end else begin
insn = 0;
insnPC = 0;
placeholder_insn = 1;
end
end
endmodule | module pipeline_insnfetch(
input CLK,
input RST,
output read_flag,
output [31:0] addr,
input [31:0] read_data,
input busy,
input done,
input next_insn_enabled,
input [31:0] next_insn,
input busy_in,
output reg [31:0] insn,
output reg [31:0] insnPC,
output reg placeholder_insn
); |
reg [31:0] PC;
wire [31:0] nextPC;
assign nextPC = next_insn_enabled ? next_insn : PC + 4;
assign addr = nextPC;
assign read_flag = !busy_in && !busy;
always @(posedge CLK or posedge RST) begin
if(RST) begin
PC <= -32'd4;
end else if(!busy_in && !busy) begin
PC <= nextPC;
end
end
always @(*) begin
if(!busy) begin
insn = read_data;
insnPC = PC;
placeholder_insn = 0;
end else begin
insn = 0;
insnPC = 0;
placeholder_insn = 1;
end
end
endmodule | 50 |
3,207 | data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v | 103,257,524 | pipeline_mem.v | v | 223 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n `MEM_SB: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n `MEM_SH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n `MEM_SW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n if(buf_opcode == `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(buf_opcode == `MEM_NOP) begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n end else if(mem_done) begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n `MEM_LW: mem_output = read_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 995 | module | module pipeline_mem(
input CLK,
input RST,
output reg [1:0] rw_flag,
output [31:0] addr,
input [31:0] read_data,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input mem_busy,
input mem_done,
output prev_busy,
input [31:0] prev_insnPC,
input [2:0] prev_insn_id,
input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,
input [31:0] mem_src1,
input [31:0] mem_src2,
input mem_src2_forward,
input [2:0] mem_src2_forward_from,
output reg [31:0] next_insnPC,
output reg [2:0] next_insn_id,
output reg [31:0] mem_output,
input [2:0] write_back_insn_id,
input [31:0] write_back_data
);
wire src2_ready;
wire [31:0] src2;
assign src2_ready = !mem_src2_forward || mem_src2_forward_from == write_back_insn_id;
assign src2 = mem_src2_forward ? write_back_data : mem_src2;
assign prev_busy = mem_busy || !src2_ready;
assign addr = mem_src1 & ~(32'b11);
reg unaligned_addr;
always @(*) begin
unaligned_addr = 0;
write_mask = 0;
write_data = 0;
rw_flag = 0;
if(!prev_busy) begin
case(mem_opcode)
`MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin
if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2'b11)
|| (mem_opcode == `MEM_LW && mem_src1[1:0] != 2'b00)) begin
unaligned_addr = 1;
rw_flag = 0;
end else begin
rw_flag = 1;
write_mask = 0;
write_data = 0;
end
end
`MEM_SB: begin
rw_flag = 2;
if(mem_src1[1:0] == 2'b00) begin
write_mask = 4'b0001;
write_data = {24'b0, src2[7:0]};
end else if(mem_src1[1:0] == 2'b01) begin
write_mask = 4'b0010;
write_data = {16'b0, src2[7:0], 8'b0};
end else if(mem_src1[1:0] == 2'b10) begin
write_mask = 4'b0100;
write_data = {8'b0, src2[7:0], 16'b0};
end else begin
write_mask = 4'b1000;
write_data = {src2[7:0], 24'b0};
end
end
`MEM_SH: begin
rw_flag = 2;
if(mem_src1[1:0] == 2'b00) begin
write_mask = 4'b0011;
write_data = {16'b0, src2[15:0]};
end else if(mem_src1[1:0] == 2'b01) begin
write_mask = 4'b0110;
write_data = {8'b0, src2[15:0], 8'b0};
end else if(mem_src1[1:0] == 2'b10) begin
write_mask = 4'b1100;
write_data = {src2[15:0], 16'b0};
end else begin
rw_flag = 0;
unaligned_addr = 1;
end
end
`MEM_SW: begin
if(mem_src1[1:0] == 2'b00) begin
rw_flag = 2;
write_mask = 4'b1111;
write_data = src2;
end else begin
rw_flag = 0;
unaligned_addr = 1;
end
end
endcase
end
end
reg [31:0] buf_insnPC;
reg [2:0] buf_insn_id;
reg [31:0] buf_src1;
reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;
always @(posedge CLK or posedge RST) begin
if(RST) begin
buf_insnPC <= 0;
buf_insn_id <= 3'b111;
buf_src1 <= 0;
buf_opcode <= 0;
end else begin
if(!prev_busy) begin
buf_insnPC <= prev_insnPC;
buf_insn_id <= prev_insn_id;
buf_src1 <= mem_src1;
buf_opcode <= mem_opcode;
end
end
end
function [7:0] get_byte;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_byte = data[7:0];
2'b01: get_byte = data[15:8];
2'b10: get_byte = data[23:16];
2'b11: get_byte = data[31:24];
endcase
endfunction
function [15:0] get_half;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_half = data[15:0];
2'b01: get_half = data[23:8];
2'b10: get_half = data[31:16];
default: get_half = 16'b0;
endcase
endfunction
function [31:0] sext_byte;
input [7:0] in;
sext_byte = {{24{in[7]}}, in};
endfunction
function [31:0] sext_half;
input [15:0] in;
sext_half = {{16{in[15]}}, in};
endfunction
always @(*) begin
if(buf_opcode == `MEM_NOP) begin
next_insnPC = buf_insnPC;
next_insn_id = buf_insn_id;
mem_output = buf_src1;
end else if(mem_done) begin
next_insnPC = buf_insnPC;
next_insn_id = buf_insn_id;
case(buf_opcode)
`MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));
`MEM_LBU: mem_output = {24'b0, get_byte(buf_src1[1:0], read_data)};
`MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));
`MEM_LHU: mem_output = {16'b0, get_half(buf_src1[1:0], read_data)};
`MEM_LW: mem_output = read_data;
default: mem_output = 0;
endcase
end else begin
next_insnPC = 0;
next_insn_id = 3'b111;
mem_output = 0;
end
end
endmodule | module pipeline_mem(
input CLK,
input RST,
output reg [1:0] rw_flag,
output [31:0] addr,
input [31:0] read_data,
output reg [31:0] write_data,
output reg [3:0] write_mask,
input mem_busy,
input mem_done,
output prev_busy,
input [31:0] prev_insnPC,
input [2:0] prev_insn_id,
input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,
input [31:0] mem_src1,
input [31:0] mem_src2,
input mem_src2_forward,
input [2:0] mem_src2_forward_from,
output reg [31:0] next_insnPC,
output reg [2:0] next_insn_id,
output reg [31:0] mem_output,
input [2:0] write_back_insn_id,
input [31:0] write_back_data
); |
wire src2_ready;
wire [31:0] src2;
assign src2_ready = !mem_src2_forward || mem_src2_forward_from == write_back_insn_id;
assign src2 = mem_src2_forward ? write_back_data : mem_src2;
assign prev_busy = mem_busy || !src2_ready;
assign addr = mem_src1 & ~(32'b11);
reg unaligned_addr;
always @(*) begin
unaligned_addr = 0;
write_mask = 0;
write_data = 0;
rw_flag = 0;
if(!prev_busy) begin
case(mem_opcode)
`MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin
if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2'b11)
|| (mem_opcode == `MEM_LW && mem_src1[1:0] != 2'b00)) begin
unaligned_addr = 1;
rw_flag = 0;
end else begin
rw_flag = 1;
write_mask = 0;
write_data = 0;
end
end
`MEM_SB: begin
rw_flag = 2;
if(mem_src1[1:0] == 2'b00) begin
write_mask = 4'b0001;
write_data = {24'b0, src2[7:0]};
end else if(mem_src1[1:0] == 2'b01) begin
write_mask = 4'b0010;
write_data = {16'b0, src2[7:0], 8'b0};
end else if(mem_src1[1:0] == 2'b10) begin
write_mask = 4'b0100;
write_data = {8'b0, src2[7:0], 16'b0};
end else begin
write_mask = 4'b1000;
write_data = {src2[7:0], 24'b0};
end
end
`MEM_SH: begin
rw_flag = 2;
if(mem_src1[1:0] == 2'b00) begin
write_mask = 4'b0011;
write_data = {16'b0, src2[15:0]};
end else if(mem_src1[1:0] == 2'b01) begin
write_mask = 4'b0110;
write_data = {8'b0, src2[15:0], 8'b0};
end else if(mem_src1[1:0] == 2'b10) begin
write_mask = 4'b1100;
write_data = {src2[15:0], 16'b0};
end else begin
rw_flag = 0;
unaligned_addr = 1;
end
end
`MEM_SW: begin
if(mem_src1[1:0] == 2'b00) begin
rw_flag = 2;
write_mask = 4'b1111;
write_data = src2;
end else begin
rw_flag = 0;
unaligned_addr = 1;
end
end
endcase
end
end
reg [31:0] buf_insnPC;
reg [2:0] buf_insn_id;
reg [31:0] buf_src1;
reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;
always @(posedge CLK or posedge RST) begin
if(RST) begin
buf_insnPC <= 0;
buf_insn_id <= 3'b111;
buf_src1 <= 0;
buf_opcode <= 0;
end else begin
if(!prev_busy) begin
buf_insnPC <= prev_insnPC;
buf_insn_id <= prev_insn_id;
buf_src1 <= mem_src1;
buf_opcode <= mem_opcode;
end
end
end
function [7:0] get_byte;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_byte = data[7:0];
2'b01: get_byte = data[15:8];
2'b10: get_byte = data[23:16];
2'b11: get_byte = data[31:24];
endcase
endfunction
function [15:0] get_half;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_half = data[15:0];
2'b01: get_half = data[23:8];
2'b10: get_half = data[31:16];
default: get_half = 16'b0;
endcase
endfunction
function [31:0] sext_byte;
input [7:0] in;
sext_byte = {{24{in[7]}}, in};
endfunction
function [31:0] sext_half;
input [15:0] in;
sext_half = {{16{in[15]}}, in};
endfunction
always @(*) begin
if(buf_opcode == `MEM_NOP) begin
next_insnPC = buf_insnPC;
next_insn_id = buf_insn_id;
mem_output = buf_src1;
end else if(mem_done) begin
next_insnPC = buf_insnPC;
next_insn_id = buf_insn_id;
case(buf_opcode)
`MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));
`MEM_LBU: mem_output = {24'b0, get_byte(buf_src1[1:0], read_data)};
`MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));
`MEM_LHU: mem_output = {16'b0, get_half(buf_src1[1:0], read_data)};
`MEM_LW: mem_output = read_data;
default: mem_output = 0;
endcase
end else begin
next_insnPC = 0;
next_insn_id = 3'b111;
mem_output = 0;
end
end
endmodule | 50 |
3,208 | data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v | 103,257,524 | pipeline_mem.v | v | 223 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n `MEM_SB: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n `MEM_SH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n `MEM_SW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n if(buf_opcode == `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(buf_opcode == `MEM_NOP) begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n end else if(mem_done) begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n `MEM_LW: mem_output = read_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 995 | function | function [7:0] get_byte;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_byte = data[7:0];
2'b01: get_byte = data[15:8];
2'b10: get_byte = data[23:16];
2'b11: get_byte = data[31:24];
endcase
endfunction | function [7:0] get_byte; |
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_byte = data[7:0];
2'b01: get_byte = data[15:8];
2'b10: get_byte = data[23:16];
2'b11: get_byte = data[31:24];
endcase
endfunction | 50 |
3,209 | data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v | 103,257,524 | pipeline_mem.v | v | 223 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n `MEM_SB: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n `MEM_SH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n `MEM_SW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n if(buf_opcode == `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(buf_opcode == `MEM_NOP) begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n end else if(mem_done) begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n `MEM_LW: mem_output = read_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 995 | function | function [15:0] get_half;
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_half = data[15:0];
2'b01: get_half = data[23:8];
2'b10: get_half = data[31:16];
default: get_half = 16'b0;
endcase
endfunction | function [15:0] get_half; |
input [1:0] addr_suffix;
input [31:0] data;
case(addr_suffix)
2'b00: get_half = data[15:0];
2'b01: get_half = data[23:8];
2'b10: get_half = data[31:16];
default: get_half = 16'b0;
endcase
endfunction | 50 |
3,210 | data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v | 103,257,524 | pipeline_mem.v | v | 223 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n `MEM_SB: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n `MEM_SH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n `MEM_SW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n if(buf_opcode == `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(buf_opcode == `MEM_NOP) begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n end else if(mem_done) begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n `MEM_LW: mem_output = read_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 995 | function | function [31:0] sext_byte;
input [7:0] in;
sext_byte = {{24{in[7]}}, in};
endfunction | function [31:0] sext_byte; |
input [7:0] in;
sext_byte = {{24{in[7]}}, in};
endfunction | 50 |
3,211 | data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v | 103,257,524 | pipeline_mem.v | v | 223 | 87 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:22: Cannot find include file: opcode.h\n`include "opcode.h" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/opcode.h.sv\n opcode.h\n opcode.h.v\n opcode.h.sv\n obj_dir/opcode.h\n obj_dir/opcode.h.v\n obj_dir/opcode.h.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:39: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n input [`MEM_OPCODE_WIDTH-1:0] mem_opcode,\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: syntax error, unexpected \',\', expecting endcase\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LH\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:73: Define or directive not defined: \'`MEM_LW\'\n `MEM_LB, `MEM_LBU, `MEM_LH, `MEM_LHU, `MEM_LW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LH\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:74: Define or directive not defined: \'`MEM_LHU\'\n if(((mem_opcode == `MEM_LH || mem_opcode == `MEM_LHU) && mem_src1[1:0] == 2\'b11) \n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:75: Define or directive not defined: \'`MEM_LW\'\n || (mem_opcode == `MEM_LW && mem_src1[1:0] != 2\'b00)) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: Define or directive not defined: \'`MEM_SB\'\n `MEM_SB: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SB: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: Define or directive not defined: \'`MEM_SH\'\n `MEM_SH: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SH: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: Define or directive not defined: \'`MEM_SW\'\n `MEM_SW: begin\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:119: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `MEM_SW: begin\n ^~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:124: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:136: Define or directive not defined: \'`MEM_OPCODE_WIDTH\'\n reg [`MEM_OPCODE_WIDTH-1:0] buf_opcode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: Define or directive not defined: \'`MEM_NOP\'\n if(buf_opcode == `MEM_NOP) begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:189: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(buf_opcode == `MEM_NOP) begin\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:193: syntax error, unexpected else\n end else if(mem_done) begin\n ^~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: Define or directive not defined: \'`MEM_LB\'\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:197: syntax error, unexpected \':\', expecting endcase\n `MEM_LB: mem_output = sext_byte(get_byte(buf_src1[1:0], read_data));\n ^\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:198: Define or directive not defined: \'`MEM_LBU\'\n `MEM_LBU: mem_output = {24\'b0, get_byte(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:199: Define or directive not defined: \'`MEM_LH\'\n `MEM_LH: mem_output = sext_half(get_half(buf_src1[1:0], read_data));\n ^~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:200: Define or directive not defined: \'`MEM_LHU\'\n `MEM_LHU: mem_output = {16\'b0, get_half(buf_src1[1:0], read_data)};\n ^~~~~~~~\n%Error: data/full_repos/permissive/103257524/src/cpu/pipeline_mem.v:201: Define or directive not defined: \'`MEM_LW\'\n `MEM_LW: mem_output = read_data;\n ^~~~~~~\n%Error: Cannot continue\n' | 995 | function | function [31:0] sext_half;
input [15:0] in;
sext_half = {{16{in[15]}}, in};
endfunction | function [31:0] sext_half; |
input [15:0] in;
sext_half = {{16{in[15]}}, in};
endfunction | 50 |
3,212 | data/full_repos/permissive/103257524/src/cpu/uart_comm.v | 103,257,524 | uart_comm.v | v | 195 | 121 | [] | [] | [] | [(22, 194)] | null | null | 1: b"%Error: data/full_repos/permissive/103257524/src/cpu/uart_comm.v:45: Cannot find file containing module: 'fifo'\n fifo #(.WIDTH(8)) recv_buffer(CLK, RST, recv_flag, recv_data, recv_write_flag, recv_write_data, recv_empty, recv_full);\n ^~~~\n ... Looked in:\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/fifo\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/fifo.v\n data/full_repos/permissive/103257524/src/cpu,data/full_repos/permissive/103257524/fifo.sv\n fifo\n fifo.v\n fifo.sv\n obj_dir/fifo\n obj_dir/fifo.v\n obj_dir/fifo.sv\n%Error: data/full_repos/permissive/103257524/src/cpu/uart_comm.v:51: Cannot find file containing module: 'fifo'\n fifo #(.WIDTH(8)) send_buffer(CLK, RST, send_read_flag, send_read_data, send_flag, send_data, send_empty, send_full);\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 996 | module | module uart_comm
#(
parameter BAUDRATE = 9600,
parameter CLOCKRATE = 100000000
)(
input CLK,
input RST,
input send_flag,
input [7:0] send_data,
input recv_flag,
output [7:0] recv_data,
output sendable,
output receivable,
output reg Tx,
input Rx
);
reg recv_write_flag;
reg [7:0] recv_write_data;
wire recv_empty, recv_full;
fifo #(.WIDTH(8)) recv_buffer(CLK, RST, recv_flag, recv_data, recv_write_flag, recv_write_data, recv_empty, recv_full);
reg send_read_flag;
wire [7:0] send_read_data;
reg [7:0] send_read_data_buf;
wire send_empty, send_full;
fifo #(.WIDTH(8)) send_buffer(CLK, RST, send_read_flag, send_read_data, send_flag, send_data, send_empty, send_full);
assign receivable = !recv_empty;
assign sendable = !send_full;
localparam SAMPLE_INTERVAL = CLOCKRATE / BAUDRATE;
localparam STATUS_IDLE = 0;
localparam STATUS_BEGIN = 1;
localparam STATUS_DATA = 2;
localparam STATUS_VALID = 4;
localparam STATUS_END = 8;
reg [3:0] recv_status;
reg [2:0] recv_bit;
reg recv_parity;
integer recv_counter;
reg recv_clock;
wire sample = recv_counter == SAMPLE_INTERVAL / 2;
always @(posedge CLK or posedge RST) begin
if(RST) begin
recv_write_flag <= 0;
recv_write_data <= 0;
recv_status <= STATUS_IDLE;
recv_bit <= 0;
recv_parity <= 0;
recv_counter <= 0;
recv_clock <= 0;
end else begin
recv_write_flag <= 0;
if(recv_clock) begin
if(recv_counter == SAMPLE_INTERVAL - 1)
recv_counter <= 0;
else
recv_counter <= recv_counter + 1;
end
if(recv_status == STATUS_IDLE) begin
if(!Rx) begin
recv_status <= STATUS_BEGIN;
recv_counter <= 0;
recv_clock <= 1;
end
end else if(sample) begin
case(recv_status)
STATUS_BEGIN:begin
if(!Rx) begin
recv_status <= STATUS_DATA;
recv_bit <= 0;
recv_parity <= 0;
end else begin
recv_status <= STATUS_IDLE;
recv_clock <= 0;
end
end
STATUS_DATA:begin
recv_parity <= recv_parity ^ Rx;
recv_write_data[recv_bit] <= Rx;
recv_bit <= recv_bit + 1;
if(recv_bit == 7)
recv_status <= STATUS_VALID;
end
STATUS_VALID:begin
if(recv_parity == Rx && !recv_full)
recv_write_flag <= 1;
recv_status <= STATUS_END;
end
STATUS_END: begin
recv_status <= STATUS_IDLE;
recv_clock <= 0;
end
endcase
end
end
end
integer counter;
always @(posedge CLK or posedge RST) begin
if(RST) begin
counter <= 0;
end else begin
counter <= counter + 1;
if(counter == SAMPLE_INTERVAL - 1)
counter <= 0;
end
end
reg [3:0] send_status;
reg [2:0] send_bit;
reg send_parity;
reg tosend;
always @(posedge CLK or posedge RST) begin
if(RST) begin
send_read_flag <= 0;
send_read_data_buf <= 0;
send_status <= STATUS_IDLE;
send_bit <= 0;
send_parity <= 0;
tosend <= 0;
Tx <= 1;
end else begin
send_read_flag <= 0;
if(counter == 0) begin
case(send_status)
STATUS_IDLE:begin
if(!send_empty) begin
send_read_data_buf <= send_read_data;
send_read_flag <= 1;
Tx <= 0;
send_status <= STATUS_DATA;
send_bit <= 0;
send_parity <= 0;
end
end
STATUS_DATA:begin
Tx <= send_read_data_buf[send_bit];
send_parity <= send_parity ^ send_read_data_buf[send_bit];
send_bit <= send_bit + 1;
if(send_bit == 7)
send_status <= STATUS_VALID;
end
STATUS_VALID:begin
Tx <= send_parity;
send_status <= STATUS_END;
end
STATUS_END:begin
Tx <= 1;
send_status <= STATUS_IDLE;
tosend = 0;
end
endcase
end
end
end
endmodule | module uart_comm
#(
parameter BAUDRATE = 9600,
parameter CLOCKRATE = 100000000
)(
input CLK,
input RST,
input send_flag,
input [7:0] send_data,
input recv_flag,
output [7:0] recv_data,
output sendable,
output receivable,
output reg Tx,
input Rx
); |
reg recv_write_flag;
reg [7:0] recv_write_data;
wire recv_empty, recv_full;
fifo #(.WIDTH(8)) recv_buffer(CLK, RST, recv_flag, recv_data, recv_write_flag, recv_write_data, recv_empty, recv_full);
reg send_read_flag;
wire [7:0] send_read_data;
reg [7:0] send_read_data_buf;
wire send_empty, send_full;
fifo #(.WIDTH(8)) send_buffer(CLK, RST, send_read_flag, send_read_data, send_flag, send_data, send_empty, send_full);
assign receivable = !recv_empty;
assign sendable = !send_full;
localparam SAMPLE_INTERVAL = CLOCKRATE / BAUDRATE;
localparam STATUS_IDLE = 0;
localparam STATUS_BEGIN = 1;
localparam STATUS_DATA = 2;
localparam STATUS_VALID = 4;
localparam STATUS_END = 8;
reg [3:0] recv_status;
reg [2:0] recv_bit;
reg recv_parity;
integer recv_counter;
reg recv_clock;
wire sample = recv_counter == SAMPLE_INTERVAL / 2;
always @(posedge CLK or posedge RST) begin
if(RST) begin
recv_write_flag <= 0;
recv_write_data <= 0;
recv_status <= STATUS_IDLE;
recv_bit <= 0;
recv_parity <= 0;
recv_counter <= 0;
recv_clock <= 0;
end else begin
recv_write_flag <= 0;
if(recv_clock) begin
if(recv_counter == SAMPLE_INTERVAL - 1)
recv_counter <= 0;
else
recv_counter <= recv_counter + 1;
end
if(recv_status == STATUS_IDLE) begin
if(!Rx) begin
recv_status <= STATUS_BEGIN;
recv_counter <= 0;
recv_clock <= 1;
end
end else if(sample) begin
case(recv_status)
STATUS_BEGIN:begin
if(!Rx) begin
recv_status <= STATUS_DATA;
recv_bit <= 0;
recv_parity <= 0;
end else begin
recv_status <= STATUS_IDLE;
recv_clock <= 0;
end
end
STATUS_DATA:begin
recv_parity <= recv_parity ^ Rx;
recv_write_data[recv_bit] <= Rx;
recv_bit <= recv_bit + 1;
if(recv_bit == 7)
recv_status <= STATUS_VALID;
end
STATUS_VALID:begin
if(recv_parity == Rx && !recv_full)
recv_write_flag <= 1;
recv_status <= STATUS_END;
end
STATUS_END: begin
recv_status <= STATUS_IDLE;
recv_clock <= 0;
end
endcase
end
end
end
integer counter;
always @(posedge CLK or posedge RST) begin
if(RST) begin
counter <= 0;
end else begin
counter <= counter + 1;
if(counter == SAMPLE_INTERVAL - 1)
counter <= 0;
end
end
reg [3:0] send_status;
reg [2:0] send_bit;
reg send_parity;
reg tosend;
always @(posedge CLK or posedge RST) begin
if(RST) begin
send_read_flag <= 0;
send_read_data_buf <= 0;
send_status <= STATUS_IDLE;
send_bit <= 0;
send_parity <= 0;
tosend <= 0;
Tx <= 1;
end else begin
send_read_flag <= 0;
if(counter == 0) begin
case(send_status)
STATUS_IDLE:begin
if(!send_empty) begin
send_read_data_buf <= send_read_data;
send_read_flag <= 1;
Tx <= 0;
send_status <= STATUS_DATA;
send_bit <= 0;
send_parity <= 0;
end
end
STATUS_DATA:begin
Tx <= send_read_data_buf[send_bit];
send_parity <= send_parity ^ send_read_data_buf[send_bit];
send_bit <= send_bit + 1;
if(send_bit == 7)
send_status <= STATUS_VALID;
end
STATUS_VALID:begin
Tx <= send_parity;
send_status <= STATUS_END;
end
STATUS_END:begin
Tx <= 1;
send_status <= STATUS_IDLE;
tosend = 0;
end
endcase
end
end
end
endmodule | 50 |
3,213 | data/full_repos/permissive/103463431/axi_test.v | 103,463,431 | axi_test.v | v | 367 | 137 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/103463431/axi_test.v:1: Cannot find include file: Macros.v\n`include "Macros.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v\n data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v.v\n data/full_repos/permissive/103463431,data/full_repos/permissive/103463431/Macros.v.sv\n Macros.v\n Macros.v.v\n Macros.v.sv\n obj_dir/Macros.v\n obj_dir/Macros.v.v\n obj_dir/Macros.v.sv\n%Error: data/full_repos/permissive/103463431/axi_test.v:2: Cannot find include file: axi4dummy.v\n`include "axi4dummy.v" \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:199: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("axi_tester.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:200: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,axi_tester);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:209: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clock_axi = !clock_axi;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:218: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:220: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:237: syntax error, unexpected \'@\'\n @(posedge clock_axi) begin\n ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:247: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:281: Unsupported: fork statements\n fork \n ^~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:287: syntax error, unexpected \'@\'\n @(clock_axi);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:290: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:298: syntax error, unexpected \'@\'\n @(clock_axi);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:301: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:309: syntax error, unexpected \'@\'\n @(clock_axi);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:315: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/103463431/axi_test.v:340: Unsupported: fork statements\n fork \n ^~~~\n%Error: data/full_repos/permissive/103463431/axi_test.v:346: syntax error, unexpected \'@\'\n @(clock_axi);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:349: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:352: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103463431/axi_test.v:358: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: Exiting due to 12 error(s), 9 warning(s)\n' | 997 | module | module axi_tester ();
parameter
AWIDTH = 64,
DWIDTH = 64,
IDWIDTH = 4,
UWIDTH = 0,
NUM_WORDS = 24;
localparam
DBYTES = (DWIDTH/8),
AWID = IDWIDTH,
AWADDR = AWIDTH,
AWLEN = 8,
AWSIZE = 3,
AWBURST = 2,
AWCACHE = 4,
AWPROT = 3,
AWQOS = 4,
AWREGION = 4,
AWUSER = UWIDTH,
WDATA = DWIDTH,
WSTRB = DBYTES,
WUSER = UWIDTH,
BID = IDWIDTH,
BRESP = 2,
BUSER = UWIDTH,
ARID = IDWIDTH,
ARADDR = AWIDTH,
ARLEN = 8,
ARSIZE = 3,
ARBURST = 2,
ARCACHE = 4,
ARPROT = 3,
ARQOS = 4,
ARREGION = 4,
ARUSER = UWIDTH,
RID = IDWIDTH,
RDATA = DWIDTH,
RRESP = 2,
RUSER = UWIDTH,
DEBUG = 0;
reg [AWADDR-1:0] store_m_axi_awaddr;
reg [AWID-1:0] store_m_axi_awid;
reg [AWLEN-1:0] store_m_axi_awlen;
reg [AWSIZE-1:0] store_m_axi_awsize;
reg [AWBURST-1:0] store_m_axi_awburst;
reg store_m_axi_awlock;
reg [AWCACHE-1:0] store_m_axi_awcache;
reg [AWPROT-1:0] store_m_axi_awprot;
reg [AWQOS-1:0] store_m_axi_awqos;
reg [AWREGION-1:0] store_m_axi_awregion;
reg [AWUSER-1:0] store_m_axi_awuser;
reg store_m_axi_awvalid;
wire store_s_axi_awready;
reg [WDATA-1:0] store_m_axi_wdata;
reg [WSTRB-1:0] store_m_axi_wstrb;
reg store_m_axi_wlast;
reg [WUSER-1:0] store_m_axi_wuser;
reg store_m_axi_wvalid;
wire store_s_axi_wready;
wire [BID-1:0] store_s_axi_bid;
wire [BRESP-1:0] store_s_axi_bresp;
wire [BUSER-1:0] store_s_axi_buser;
wire store_s_axi_bvalid;
reg store_m_axi_bready;
reg [ARADDR-1:0] load_m_axi_araddr;
reg [ARID-1:0] load_m_axi_arid;
reg [ARLEN-1:0] load_m_axi_arlen;
reg [ARSIZE-1:0] load_m_axi_arsize;
reg [ARBURST-1:0] load_m_axi_arburst;
reg load_m_axi_arlock;
reg [ARCACHE-1:0] load_m_axi_arcache;
reg [ARPROT-1:0] load_m_axi_arprot;
reg [ARQOS-1:0] load_m_axi_arqos;
reg [ARREGION-1:0] load_m_axi_arregion;
reg [ARUSER-1:0] load_m_axi_aruser;
reg load_m_axi_arvalid;
wire load_s_axi_arready;
wire [RID-1:0] load_s_axi_rid;
reg [RID-1:0] read_id;
wire [RDATA-1:0] load_s_axi_rdata;
reg [RDATA-1:0] read_data;
wire [RRESP-1:0] load_s_axi_rresp;
wire load_s_axi_rlast;
wire [RUSER-1:0] load_s_axi_ruser;
wire load_s_axi_rvalid;
reg load_m_axi_rready;
reg [0:0] clock_axi;
reg [0:0] reset_axi_n;
axi4dummy #(
.NUM_WORDS( NUM_WORDS),
.AWIDTH( AWIDTH),
.DWIDTH( DWIDTH),
.IDWIDTH( IDWIDTH),
.INITIAL_VALUE( {(NUM_WORDS*DWIDTH){1'b0}})
) DUT (
.clock_axi( clock_axi),
.reset_axi_n( reset_axi_n),
.s_axi_awaddr( store_m_axi_awaddr),
.s_axi_awid( store_m_axi_awid),
.s_axi_awlen( store_m_axi_awlen),
.s_axi_awsize( store_m_axi_awsize),
.s_axi_awburst( store_m_axi_awburst),
.s_axi_awlock( store_m_axi_awlock),
.s_axi_awcache( store_m_axi_awcache),
.s_axi_awprot( store_m_axi_awprot),
.s_axi_awqos( store_m_axi_awqos),
.s_axi_awregion( store_m_axi_awregion),
.s_axi_awvalid( store_m_axi_awvalid),
.s_axi_awready( store_s_axi_awready),
.s_axi_awuser( store_m_axi_awuser),
.s_axi_wdata( store_m_axi_wdata),
.s_axi_wstrb( store_m_axi_wstrb),
.s_axi_wlast( store_m_axi_wlast),
.s_axi_wuser( store_m_axi_wuser),
.s_axi_wvalid( store_m_axi_wvalid),
.s_axi_wready( store_s_axi_wready),
.s_axi_bid( store_s_axi_bid),
.s_axi_bresp( store_s_axi_bresp),
.s_axi_buser( store_s_axi_buser),
.s_axi_bvalid( store_s_axi_bvalid),
.s_axi_bready( store_m_axi_bready),
.s_axi_araddr( load_m_axi_araddr),
.s_axi_arid( load_m_axi_arid),
.s_axi_arlen( load_m_axi_arlen),
.s_axi_arsize( load_m_axi_arsize),
.s_axi_arburst( load_m_axi_arburst),
.s_axi_arlock( load_m_axi_arlock),
.s_axi_arcache( load_m_axi_arcache),
.s_axi_arprot( load_m_axi_arprot),
.s_axi_arqos( load_m_axi_arqos),
.s_axi_arregion( load_m_axi_arregion),
.s_axi_arvalid( load_m_axi_arvalid),
.s_axi_arready( load_s_axi_arready),
.s_axi_rid( load_s_axi_rid),
.s_axi_rdata( load_s_axi_rdata),
.s_axi_rresp( load_s_axi_rresp),
.s_axi_rlast( load_s_axi_rlast),
.s_axi_ruser( load_s_axi_ruser),
.s_axi_rvalid( load_s_axi_rvalid),
.s_axi_rready( load_m_axi_rready)
);
initial
begin
$dumpfile("axi_tester.vcd");
$dumpvars(0,axi_tester);
end
initial
begin
clock_axi = 0;
store_m_axi_wlast = 0;
store_m_axi_bready = 1;
forever #1 clock_axi = !clock_axi;
end
initial begin
reset(2);
store(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000, 64'hDEAD_BEEF_DEAD_BEEF);
#10
load(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000);
#10
$finish;
end
task reset;
input [31:0] reset_cycles;
begin
reset_axi_n = 0;
repeat (reset_cycles)
@(posedge clock_axi) begin
load_m_axi_arvalid <= 0;
store_m_axi_awvalid <= 0;
store_m_axi_wvalid <= 0;
load_m_axi_rready <= 0;
end
reset_axi_n = 1;
$display ("");
$display("==== Reset complete, Time = %0d units", $time);
$display ("");
end
endtask
task automatic store;
input [AWID-1:0] awid;
input [AWLEN-1:0] awlen;
input [AWSIZE-1:0] awsize;
input [AWBURST-1:0] awburst;
input [AWADDR-1:0] awaddr;
input [WDATA-1:0] wdata;
begin
store_m_axi_awid = awid;
store_m_axi_awlen = awlen;
store_m_axi_awsize = awsize;
store_m_axi_awburst = awburst;
store_m_axi_bready <= 1;
store_m_axi_awvalid <= 1;
store_m_axi_awaddr <= awaddr;
store_m_axi_wdata <= wdata;
store_m_axi_wstrb <= 8'hFF;
store_m_axi_wlast <= 1'b1;
store_m_axi_wvalid <= 1'b1;
fork
begin
while (store_s_axi_awready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("AWREADY = %0d @ Time = %0d units", store_s_axi_awready, $time);
#1
store_m_axi_awvalid <= 0;
end
begin
while (store_s_axi_wready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("WREADY = %0d @ Time = %0d units", store_s_axi_wready, $time);
#1
store_m_axi_wlast <= 0;
store_m_axi_wvalid <= 0;
end
begin
while (store_s_axi_bvalid !=1)
@(clock_axi);
if (DEBUG == 1) if (store_s_axi_bresp === 2'b00) $display ("BRESP = %0d (OK) @ Time = %0d units", store_s_axi_bresp, $time);
end
join
#1
$display ("==== Store data = 0x%h, Address = 0x%h", wdata, awaddr);
$display ("");
end
endtask
task load;
input [ARID-1:0] arid;
input [ARLEN-1:0] arlen;
input [ARSIZE-1:0] arsize;
input [ARBURST-1:0] arburst;
input [ARADDR-1:0] araddr;
begin
load_m_axi_arid = arid;
load_m_axi_arlen = arlen;
load_m_axi_arsize = arsize;
load_m_axi_arburst = arburst;
load_m_axi_arvalid <= 1;
load_m_axi_araddr <= araddr;
fork
begin
while (load_s_axi_arready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("ARREADY = %0d @ Time = %0d units", load_s_axi_arready, $time);
#1
load_m_axi_arvalid <= 0;
load_m_axi_rready <= 1;
#1
if (DEBUG == 1) begin
if (load_s_axi_rresp === 2'b00) $display ("RRESP = %0d (OK) @ Time = %0d units", load_s_axi_rresp, $time);
end
$display ("==== Loaded data = 0x%h, Address = 0x%h", load_s_axi_rdata, araddr);
$display ("");
#1
load_m_axi_rready <= 0;
end
join
end
endtask
endmodule | module axi_tester (); |
parameter
AWIDTH = 64,
DWIDTH = 64,
IDWIDTH = 4,
UWIDTH = 0,
NUM_WORDS = 24;
localparam
DBYTES = (DWIDTH/8),
AWID = IDWIDTH,
AWADDR = AWIDTH,
AWLEN = 8,
AWSIZE = 3,
AWBURST = 2,
AWCACHE = 4,
AWPROT = 3,
AWQOS = 4,
AWREGION = 4,
AWUSER = UWIDTH,
WDATA = DWIDTH,
WSTRB = DBYTES,
WUSER = UWIDTH,
BID = IDWIDTH,
BRESP = 2,
BUSER = UWIDTH,
ARID = IDWIDTH,
ARADDR = AWIDTH,
ARLEN = 8,
ARSIZE = 3,
ARBURST = 2,
ARCACHE = 4,
ARPROT = 3,
ARQOS = 4,
ARREGION = 4,
ARUSER = UWIDTH,
RID = IDWIDTH,
RDATA = DWIDTH,
RRESP = 2,
RUSER = UWIDTH,
DEBUG = 0;
reg [AWADDR-1:0] store_m_axi_awaddr;
reg [AWID-1:0] store_m_axi_awid;
reg [AWLEN-1:0] store_m_axi_awlen;
reg [AWSIZE-1:0] store_m_axi_awsize;
reg [AWBURST-1:0] store_m_axi_awburst;
reg store_m_axi_awlock;
reg [AWCACHE-1:0] store_m_axi_awcache;
reg [AWPROT-1:0] store_m_axi_awprot;
reg [AWQOS-1:0] store_m_axi_awqos;
reg [AWREGION-1:0] store_m_axi_awregion;
reg [AWUSER-1:0] store_m_axi_awuser;
reg store_m_axi_awvalid;
wire store_s_axi_awready;
reg [WDATA-1:0] store_m_axi_wdata;
reg [WSTRB-1:0] store_m_axi_wstrb;
reg store_m_axi_wlast;
reg [WUSER-1:0] store_m_axi_wuser;
reg store_m_axi_wvalid;
wire store_s_axi_wready;
wire [BID-1:0] store_s_axi_bid;
wire [BRESP-1:0] store_s_axi_bresp;
wire [BUSER-1:0] store_s_axi_buser;
wire store_s_axi_bvalid;
reg store_m_axi_bready;
reg [ARADDR-1:0] load_m_axi_araddr;
reg [ARID-1:0] load_m_axi_arid;
reg [ARLEN-1:0] load_m_axi_arlen;
reg [ARSIZE-1:0] load_m_axi_arsize;
reg [ARBURST-1:0] load_m_axi_arburst;
reg load_m_axi_arlock;
reg [ARCACHE-1:0] load_m_axi_arcache;
reg [ARPROT-1:0] load_m_axi_arprot;
reg [ARQOS-1:0] load_m_axi_arqos;
reg [ARREGION-1:0] load_m_axi_arregion;
reg [ARUSER-1:0] load_m_axi_aruser;
reg load_m_axi_arvalid;
wire load_s_axi_arready;
wire [RID-1:0] load_s_axi_rid;
reg [RID-1:0] read_id;
wire [RDATA-1:0] load_s_axi_rdata;
reg [RDATA-1:0] read_data;
wire [RRESP-1:0] load_s_axi_rresp;
wire load_s_axi_rlast;
wire [RUSER-1:0] load_s_axi_ruser;
wire load_s_axi_rvalid;
reg load_m_axi_rready;
reg [0:0] clock_axi;
reg [0:0] reset_axi_n;
axi4dummy #(
.NUM_WORDS( NUM_WORDS),
.AWIDTH( AWIDTH),
.DWIDTH( DWIDTH),
.IDWIDTH( IDWIDTH),
.INITIAL_VALUE( {(NUM_WORDS*DWIDTH){1'b0}})
) DUT (
.clock_axi( clock_axi),
.reset_axi_n( reset_axi_n),
.s_axi_awaddr( store_m_axi_awaddr),
.s_axi_awid( store_m_axi_awid),
.s_axi_awlen( store_m_axi_awlen),
.s_axi_awsize( store_m_axi_awsize),
.s_axi_awburst( store_m_axi_awburst),
.s_axi_awlock( store_m_axi_awlock),
.s_axi_awcache( store_m_axi_awcache),
.s_axi_awprot( store_m_axi_awprot),
.s_axi_awqos( store_m_axi_awqos),
.s_axi_awregion( store_m_axi_awregion),
.s_axi_awvalid( store_m_axi_awvalid),
.s_axi_awready( store_s_axi_awready),
.s_axi_awuser( store_m_axi_awuser),
.s_axi_wdata( store_m_axi_wdata),
.s_axi_wstrb( store_m_axi_wstrb),
.s_axi_wlast( store_m_axi_wlast),
.s_axi_wuser( store_m_axi_wuser),
.s_axi_wvalid( store_m_axi_wvalid),
.s_axi_wready( store_s_axi_wready),
.s_axi_bid( store_s_axi_bid),
.s_axi_bresp( store_s_axi_bresp),
.s_axi_buser( store_s_axi_buser),
.s_axi_bvalid( store_s_axi_bvalid),
.s_axi_bready( store_m_axi_bready),
.s_axi_araddr( load_m_axi_araddr),
.s_axi_arid( load_m_axi_arid),
.s_axi_arlen( load_m_axi_arlen),
.s_axi_arsize( load_m_axi_arsize),
.s_axi_arburst( load_m_axi_arburst),
.s_axi_arlock( load_m_axi_arlock),
.s_axi_arcache( load_m_axi_arcache),
.s_axi_arprot( load_m_axi_arprot),
.s_axi_arqos( load_m_axi_arqos),
.s_axi_arregion( load_m_axi_arregion),
.s_axi_arvalid( load_m_axi_arvalid),
.s_axi_arready( load_s_axi_arready),
.s_axi_rid( load_s_axi_rid),
.s_axi_rdata( load_s_axi_rdata),
.s_axi_rresp( load_s_axi_rresp),
.s_axi_rlast( load_s_axi_rlast),
.s_axi_ruser( load_s_axi_ruser),
.s_axi_rvalid( load_s_axi_rvalid),
.s_axi_rready( load_m_axi_rready)
);
initial
begin
$dumpfile("axi_tester.vcd");
$dumpvars(0,axi_tester);
end
initial
begin
clock_axi = 0;
store_m_axi_wlast = 0;
store_m_axi_bready = 1;
forever #1 clock_axi = !clock_axi;
end
initial begin
reset(2);
store(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000, 64'hDEAD_BEEF_DEAD_BEEF);
#10
load(4'b0000,8'b00,3'b011, 2'b00, 64'h0000_0000_0000_0000);
#10
$finish;
end
task reset;
input [31:0] reset_cycles;
begin
reset_axi_n = 0;
repeat (reset_cycles)
@(posedge clock_axi) begin
load_m_axi_arvalid <= 0;
store_m_axi_awvalid <= 0;
store_m_axi_wvalid <= 0;
load_m_axi_rready <= 0;
end
reset_axi_n = 1;
$display ("");
$display("==== Reset complete, Time = %0d units", $time);
$display ("");
end
endtask
task automatic store;
input [AWID-1:0] awid;
input [AWLEN-1:0] awlen;
input [AWSIZE-1:0] awsize;
input [AWBURST-1:0] awburst;
input [AWADDR-1:0] awaddr;
input [WDATA-1:0] wdata;
begin
store_m_axi_awid = awid;
store_m_axi_awlen = awlen;
store_m_axi_awsize = awsize;
store_m_axi_awburst = awburst;
store_m_axi_bready <= 1;
store_m_axi_awvalid <= 1;
store_m_axi_awaddr <= awaddr;
store_m_axi_wdata <= wdata;
store_m_axi_wstrb <= 8'hFF;
store_m_axi_wlast <= 1'b1;
store_m_axi_wvalid <= 1'b1;
fork
begin
while (store_s_axi_awready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("AWREADY = %0d @ Time = %0d units", store_s_axi_awready, $time);
#1
store_m_axi_awvalid <= 0;
end
begin
while (store_s_axi_wready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("WREADY = %0d @ Time = %0d units", store_s_axi_wready, $time);
#1
store_m_axi_wlast <= 0;
store_m_axi_wvalid <= 0;
end
begin
while (store_s_axi_bvalid !=1)
@(clock_axi);
if (DEBUG == 1) if (store_s_axi_bresp === 2'b00) $display ("BRESP = %0d (OK) @ Time = %0d units", store_s_axi_bresp, $time);
end
join
#1
$display ("==== Store data = 0x%h, Address = 0x%h", wdata, awaddr);
$display ("");
end
endtask
task load;
input [ARID-1:0] arid;
input [ARLEN-1:0] arlen;
input [ARSIZE-1:0] arsize;
input [ARBURST-1:0] arburst;
input [ARADDR-1:0] araddr;
begin
load_m_axi_arid = arid;
load_m_axi_arlen = arlen;
load_m_axi_arsize = arsize;
load_m_axi_arburst = arburst;
load_m_axi_arvalid <= 1;
load_m_axi_araddr <= araddr;
fork
begin
while (load_s_axi_arready != 1)
begin
@(clock_axi);
end
if (DEBUG == 1) $display ("ARREADY = %0d @ Time = %0d units", load_s_axi_arready, $time);
#1
load_m_axi_arvalid <= 0;
load_m_axi_rready <= 1;
#1
if (DEBUG == 1) begin
if (load_s_axi_rresp === 2'b00) $display ("RRESP = %0d (OK) @ Time = %0d units", load_s_axi_rresp, $time);
end
$display ("==== Loaded data = 0x%h, Address = 0x%h", load_s_axi_rdata, araddr);
$display ("");
#1
load_m_axi_rready <= 0;
end
join
end
endtask
endmodule | 0 |
3,214 | data/full_repos/permissive/103559617/helloworld/helloworld.v | 103,559,617 | helloworld.v | v | 114 | 71 | [] | [] | [] | [(1, 113)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103559617/helloworld/helloworld.v:52: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'toggle\' generates 4 bits.\n : ... In instance helloworld\n i = i + toggle;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103559617/helloworld/helloworld.v:84: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'toggle\' generates 4 bits.\n : ... In instance helloworld\n i = i - toggle;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 998 | module | module helloworld (clk, led, dipswitch, key0, key1);
input clk;
input key0;
input key1;
input [3:0] dipswitch;
output reg [7:0] led;
reg [31:0] counter = 0;
integer i = 0;
reg [3:0] toggle = 0;
always @ (posedge clk)
begin
if (counter <= 25000000)
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
if (~key0)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
i = i + toggle;
if (i > 7)
begin
i = i - 8;
end
led[i] = 1;
end
else if (~key1)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
i = i - toggle;
if (i < 0)
begin
i = i + 8;
end
led[i] = 1;
end
else
begin
end
led[i] = ~led[i];
toggle = 0;
end
end
endmodule | module helloworld (clk, led, dipswitch, key0, key1); |
input clk;
input key0;
input key1;
input [3:0] dipswitch;
output reg [7:0] led;
reg [31:0] counter = 0;
integer i = 0;
reg [3:0] toggle = 0;
always @ (posedge clk)
begin
if (counter <= 25000000)
begin
counter <= counter + 1;
end
else
begin
counter <= 0;
if (~key0)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
i = i + toggle;
if (i > 7)
begin
i = i - 8;
end
led[i] = 1;
end
else if (~key1)
begin
led[i] = 0;
if (dipswitch[0] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[1] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[2] == 1)
begin
toggle = toggle + 1'b1;
end
if (dipswitch[3] == 1)
begin
toggle = toggle + 1'b1;
end
i = i - toggle;
if (i < 0)
begin
i = i + 8;
end
led[i] = 1;
end
else
begin
end
led[i] = ~led[i];
toggle = 0;
end
end
endmodule | 1 |
3,215 | data/full_repos/permissive/103649428/VendingMachine.v | 103,649,428 | VendingMachine.v | v | 763 | 131 | [] | [] | [] | [(7, 166), (168, 200), (203, 223), (225, 243), (245, 763)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11111101;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 999 | module | module VendingMachine(reset, clk, SEG, AN, item1, item2, coin1, coin2, confirm_flag, buy,
is_sale, power_on, op_start, cancel_flag, hold_ind, drinktk_ind, charge_ind, is_sale_xdc);
input reset, clk;
input item1, item2, coin1, coin2, buy;
input is_sale, op_start, cancel_flag, confirm_flag;
output [7:0]SEG;
output [7:0]AN;
output reg is_sale_xdc;
output reg power_on, hold_ind, charge_ind;
output drinktk_ind;
reg [2:0] state;
reg [4:0] chargeMoney;
reg [2:0] cnt;
reg cancel;
wire ck;
wire over;
wire [4:0] money;
reg hasBuy;
wire is_charge;
parameter off = 0,
start = 1,
toSale = 2,
chooseItem = 3,
pay = 4,
charge = 5;
initial begin
cnt = 0;
power_on = 0;
hold_ind = 0;
state = 0;
chargeMoney = 0;
is_sale_xdc = 0;
hasBuy = 0;
cancel = 0;
end
Time timing(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));
Divider #(200_000) divider(.clk(clk), .ck(ck));
Show show(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));
Pay paymoney(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));
always @(posedge clk) begin
case (state)
off: begin
power_on = 0;
hold_ind = 0;
is_sale_xdc = 0;
charge_ind = 0;
if(reset)
state = start;
else
state = off;
end
start: begin
power_on = 1;
hold_ind = 0;
is_sale_xdc = 0;
charge_ind = 0;
hasBuy = 0;
cancel = 0;
if(is_sale)
state = toSale;
else
state = start;
if(!reset)
state = off;
end
toSale: begin
power_on = 1;
hold_ind = 0;
is_sale_xdc = 1;
charge_ind = 0;
if(op_start)
state = chooseItem;
else
state = toSale;
if(!is_sale)
state = start;
if(!reset)
state = off;
end
chooseItem: begin
power_on = 1;
hold_ind = 1;
is_sale_xdc = 1;
charge_ind = 0;
if(confirm_flag)
state = pay;
else
state = chooseItem;
if(!op_start)
state = toSale;
if(!reset)
state = off;
end
pay: begin
power_on <= 1;
hold_ind <= 1;
is_sale_xdc <= 1;
if(cancel_flag) begin
cancel <= 1;
if(money > 0) begin
state <= charge;
hasBuy <= 0;
charge_ind <= 1;
end
else if(money == 0)
state <= start;
end
else begin
if(item1) begin
if (money >= 3) begin
hasBuy <= 1;
charge_ind <= 1;
state <= charge;
end
else if(money < 3)
state <= pay;
end
else if(item2)begin
if(money >= 5) begin
hasBuy <= 1;
if(money > 5)
charge_ind <= 1;
else if(money == 5)
charge_ind <= 0;
state <= charge;
end
else if(money < 5)
state <= pay;
end
end
end
charge: begin
power_on = 1;
hold_ind = 1;
is_sale_xdc = 1;
if(cancel) begin
chargeMoney = 2 * money;
end
else begin
if(item1) begin
chargeMoney = 2 * money - 5;
end
else if(item2)
chargeMoney = 2 * money - 10;
end
if(over)
state = start;
else
state = charge;
end
endcase
end
endmodule | module VendingMachine(reset, clk, SEG, AN, item1, item2, coin1, coin2, confirm_flag, buy,
is_sale, power_on, op_start, cancel_flag, hold_ind, drinktk_ind, charge_ind, is_sale_xdc); |
input reset, clk;
input item1, item2, coin1, coin2, buy;
input is_sale, op_start, cancel_flag, confirm_flag;
output [7:0]SEG;
output [7:0]AN;
output reg is_sale_xdc;
output reg power_on, hold_ind, charge_ind;
output drinktk_ind;
reg [2:0] state;
reg [4:0] chargeMoney;
reg [2:0] cnt;
reg cancel;
wire ck;
wire over;
wire [4:0] money;
reg hasBuy;
wire is_charge;
parameter off = 0,
start = 1,
toSale = 2,
chooseItem = 3,
pay = 4,
charge = 5;
initial begin
cnt = 0;
power_on = 0;
hold_ind = 0;
state = 0;
chargeMoney = 0;
is_sale_xdc = 0;
hasBuy = 0;
cancel = 0;
end
Time timing(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));
Divider #(200_000) divider(.clk(clk), .ck(ck));
Show show(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));
Pay paymoney(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));
always @(posedge clk) begin
case (state)
off: begin
power_on = 0;
hold_ind = 0;
is_sale_xdc = 0;
charge_ind = 0;
if(reset)
state = start;
else
state = off;
end
start: begin
power_on = 1;
hold_ind = 0;
is_sale_xdc = 0;
charge_ind = 0;
hasBuy = 0;
cancel = 0;
if(is_sale)
state = toSale;
else
state = start;
if(!reset)
state = off;
end
toSale: begin
power_on = 1;
hold_ind = 0;
is_sale_xdc = 1;
charge_ind = 0;
if(op_start)
state = chooseItem;
else
state = toSale;
if(!is_sale)
state = start;
if(!reset)
state = off;
end
chooseItem: begin
power_on = 1;
hold_ind = 1;
is_sale_xdc = 1;
charge_ind = 0;
if(confirm_flag)
state = pay;
else
state = chooseItem;
if(!op_start)
state = toSale;
if(!reset)
state = off;
end
pay: begin
power_on <= 1;
hold_ind <= 1;
is_sale_xdc <= 1;
if(cancel_flag) begin
cancel <= 1;
if(money > 0) begin
state <= charge;
hasBuy <= 0;
charge_ind <= 1;
end
else if(money == 0)
state <= start;
end
else begin
if(item1) begin
if (money >= 3) begin
hasBuy <= 1;
charge_ind <= 1;
state <= charge;
end
else if(money < 3)
state <= pay;
end
else if(item2)begin
if(money >= 5) begin
hasBuy <= 1;
if(money > 5)
charge_ind <= 1;
else if(money == 5)
charge_ind <= 0;
state <= charge;
end
else if(money < 5)
state <= pay;
end
end
end
charge: begin
power_on = 1;
hold_ind = 1;
is_sale_xdc = 1;
if(cancel) begin
chargeMoney = 2 * money;
end
else begin
if(item1) begin
chargeMoney = 2 * money - 5;
end
else if(item2)
chargeMoney = 2 * money - 10;
end
if(over)
state = start;
else
state = charge;
end
endcase
end
endmodule | 2 |
3,216 | data/full_repos/permissive/103649428/VendingMachine.v | 103,649,428 | VendingMachine.v | v | 763 | 131 | [] | [] | [] | [(7, 166), (168, 200), (203, 223), (225, 243), (245, 763)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11111101;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 999 | module | module Time(state, clk, hasBuy, drinktk_ind, over);
input clk, hasBuy;
input [2:0]state;
output reg drinktk_ind, over;
reg [31:0]cnt;
initial begin
drinktk_ind <= 0;
cnt <= 0;
over <= 0;
end
always@(posedge clk) begin
if (state == 5) begin
if(hasBuy)
drinktk_ind = 1;
else
drinktk_ind = 0;
if(cnt == 300_000_000) begin
cnt = 0;
over = 1;
end
else begin
cnt = cnt + 1;
over = 0;
end
end
else begin
drinktk_ind <= 0;
over <= 0;
end
end
endmodule | module Time(state, clk, hasBuy, drinktk_ind, over); |
input clk, hasBuy;
input [2:0]state;
output reg drinktk_ind, over;
reg [31:0]cnt;
initial begin
drinktk_ind <= 0;
cnt <= 0;
over <= 0;
end
always@(posedge clk) begin
if (state == 5) begin
if(hasBuy)
drinktk_ind = 1;
else
drinktk_ind = 0;
if(cnt == 300_000_000) begin
cnt = 0;
over = 1;
end
else begin
cnt = cnt + 1;
over = 0;
end
end
else begin
drinktk_ind <= 0;
over <= 0;
end
end
endmodule | 2 |
3,217 | data/full_repos/permissive/103649428/VendingMachine.v | 103,649,428 | VendingMachine.v | v | 763 | 131 | [] | [] | [] | [(7, 166), (168, 200), (203, 223), (225, 243), (245, 763)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11111101;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 999 | module | module Divider(clk, ck);
input clk;
output reg ck;
reg [31:0]cnt;
parameter dely1s = 200_000;
initial begin
cnt <= 0;
end
always @(posedge clk)
begin
cnt = cnt + 1;
if(cnt == dely1s)
begin
ck = ~ck;
cnt = 0;
end
end
endmodule | module Divider(clk, ck); |
input clk;
output reg ck;
reg [31:0]cnt;
parameter dely1s = 200_000;
initial begin
cnt <= 0;
end
always @(posedge clk)
begin
cnt = cnt + 1;
if(cnt == dely1s)
begin
ck = ~ck;
cnt = 0;
end
end
endmodule | 2 |
3,218 | data/full_repos/permissive/103649428/VendingMachine.v | 103,649,428 | VendingMachine.v | v | 763 | 131 | [] | [] | [] | [(7, 166), (168, 200), (203, 223), (225, 243), (245, 763)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11111101;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 999 | module | module Pay(state, buy, coin1, coin2, money);
input buy, coin1, coin2;
input [2:0] state;
output reg [4:0]money;
initial begin
money = 0;
end
always @(posedge buy) begin
if (state == 4) begin
if(coin1)
money = money + 1;
else if(coin2)
money = money + 10;
end
else begin
money = 0;
end
end
endmodule | module Pay(state, buy, coin1, coin2, money); |
input buy, coin1, coin2;
input [2:0] state;
output reg [4:0]money;
initial begin
money = 0;
end
always @(posedge buy) begin
if (state == 4) begin
if(coin1)
money = money + 1;
else if(coin2)
money = money + 10;
end
else begin
money = 0;
end
end
endmodule | 2 |
3,219 | data/full_repos/permissive/103649428/VendingMachine.v | 103,649,428 | VendingMachine.v | v | 763 | 131 | [] | [] | [] | [(7, 166), (168, 200), (203, 223), (225, 243), (245, 763)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:359: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hfd\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11111101;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:407: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:427: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:447: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:467: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:487: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:507: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:532: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'hdf\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b11011111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:672: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:715: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] <= 9\'b01111111;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:734: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/103649428/VendingMachine.v:753: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7f\' generates 9 bits.\n : ... In instance VendingMachine.show\n AN[7:0] = 9\'b01111111;\n ^\n%Error: Exiting due to 12 warning(s)\n' | 999 | module | module Show(ck, item1, item2, state, money, chargeMoney, SEG, AN);
input ck;
input item1, item2;
input [2:0]state;
input [4:0]money;
input [4:0]chargeMoney;
output reg [7:0]SEG;
output reg [7:0]AN;
reg [2:0]cnt;
initial begin
cnt = 0;
end
parameter off = 0,
start = 1,
toSale = 2,
chooseItem = 3,
pay = 4,
charge = 5;
always@(posedge ck) begin
case(state)
off: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111011;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10001110;
AN[7:0] <= 8'b11111101;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b10001110;
AN[7:0] <= 8'b11111110;
end
default: cnt = 0;
endcase
end
start: begin
case (cnt)
0:begin
cnt <= 1;
SEG[7:0]<=8'b11000000;
AN[7:0]<=8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111101;
end
2:begin
cnt <= 3;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111011;
end
3:begin
cnt <= 4;
SEG[7:0] <= 8'b10000110;
AN[7:0] <= 8'b11110111;
end
4:begin
cnt <= 0;
SEG[7:0] <= 8'b10001001;
AN[7:0] <= 8'b11101111;
end
default: cnt = 0;
endcase
end
toSale: begin
case (cnt)
0:begin
cnt <= 1;
SEG[7:0]<=8'b11000000;
AN[7:0]<=8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111101;
end
2:begin
cnt <= 3;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111011;
end
3:begin
cnt <= 4;
SEG[7:0] <= 8'b10000110;
AN[7:0] <= 8'b11110111;
end
4:begin
cnt <= 0;
SEG[7:0] <= 8'b10001001;
AN[7:0] <= 8'b11101111;
end
default: cnt = 0;
endcase
end
chooseItem: begin
if(item1) begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11111101;
end
default: cnt = 0;
endcase
end
else if(item2) begin
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
else begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 8'b11110111;
end
2:begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111011;
end
default: cnt = 0;
endcase
end
end
pay: begin
if(item1)begin
case (money)
0: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
1: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
2: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
3: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
4: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
5: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
10: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] = 8'b11000000;
AN[7:0] = 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] = 8'b11111001;
AN[7:0] = 8'b11111101;
end
2: begin
cnt <= 3;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
3: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
else if(item2) begin
case (money)
0: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
1: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
2: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
3: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
4: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
5: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
10: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] = 8'b11000000;
AN[7:0] = 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] = 8'b11111001;
AN[7:0] = 8'b11111101;
end
2: begin
cnt <= 0;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b11101111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
end
charge: begin
case(chargeMoney)
0: begin
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b01111111;
end
1: begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b10111111;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b01000000;
AN[7:0] <= 9'b01111111;
end
default: cnt = 0;
endcase
end
2: begin
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b01111111;
end
4: begin
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b01111111;
end
6: begin
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b01111111;
end
8: begin
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b01111111;
end
10: begin
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b01111111;
end
12: begin
SEG[7:0] = 8'b10000010;
AN[7:0] = 8'b01111111;
end
14: begin
SEG[7:0] = 8'b11111000;
AN[7:0] = 8'b01111111;
end
15: begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b10111111;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b01111000;
AN[7:0] <= 9'b01111111;
end
default: cnt = 0;
endcase
end
16: begin
SEG[7:0] = 8'b10000000;
AN[7:0] = 8'b01111111;
end
17: begin
case(cnt)
0:begin
cnt = 1;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b10111111;
end
1:begin
cnt = 0;
SEG[7:0] = 8'b00000000;
AN[7:0] = 9'b01111111;
end
default: cnt = 0;
endcase
end
18: begin
SEG[7:0] = 8'b10010000;
AN[7:0] = 8'b01111111;
end
19: begin
case(cnt)
0:begin
cnt = 1;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b10111111;
end
1:begin
cnt = 0;
SEG[7:0] = 8'b00010000;
AN[7:0] = 9'b01111111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
endcase
end
endmodule | module Show(ck, item1, item2, state, money, chargeMoney, SEG, AN); |
input ck;
input item1, item2;
input [2:0]state;
input [4:0]money;
input [4:0]chargeMoney;
output reg [7:0]SEG;
output reg [7:0]AN;
reg [2:0]cnt;
initial begin
cnt = 0;
end
parameter off = 0,
start = 1,
toSale = 2,
chooseItem = 3,
pay = 4,
charge = 5;
always@(posedge ck) begin
case(state)
off: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111011;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10001110;
AN[7:0] <= 8'b11111101;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b10001110;
AN[7:0] <= 8'b11111110;
end
default: cnt = 0;
endcase
end
start: begin
case (cnt)
0:begin
cnt <= 1;
SEG[7:0]<=8'b11000000;
AN[7:0]<=8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111101;
end
2:begin
cnt <= 3;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111011;
end
3:begin
cnt <= 4;
SEG[7:0] <= 8'b10000110;
AN[7:0] <= 8'b11110111;
end
4:begin
cnt <= 0;
SEG[7:0] <= 8'b10001001;
AN[7:0] <= 8'b11101111;
end
default: cnt = 0;
endcase
end
toSale: begin
case (cnt)
0:begin
cnt <= 1;
SEG[7:0]<=8'b11000000;
AN[7:0]<=8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111101;
end
2:begin
cnt <= 3;
SEG[7:0] <= 8'b11000111;
AN[7:0] <= 8'b11111011;
end
3:begin
cnt <= 4;
SEG[7:0] <= 8'b10000110;
AN[7:0] <= 8'b11110111;
end
4:begin
cnt <= 0;
SEG[7:0] <= 8'b10001001;
AN[7:0] <= 8'b11101111;
end
default: cnt = 0;
endcase
end
chooseItem: begin
if(item1) begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11111101;
end
default: cnt = 0;
endcase
end
else if(item2) begin
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
else begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1:begin
cnt <= 2;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 8'b11110111;
end
2:begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111011;
end
default: cnt = 0;
endcase
end
end
pay: begin
if(item1)begin
case (money)
0: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
1: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
2: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
3: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
4: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
5: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
2: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt <= 0;
endcase
end
10: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] = 8'b11000000;
AN[7:0] = 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] = 8'b11111001;
AN[7:0] = 8'b11111101;
end
2: begin
cnt <= 3;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
3: begin
cnt <= 0;
SEG[7:0] <= 8'b00100100;
AN[7:0] <= 9'b11011111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
else if(item2) begin
case (money)
0: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
1: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
2: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
3: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
4: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
5: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11111110;
end
1: begin
cnt <= 0;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b11101111;
end
default: cnt <= 0;
endcase
end
10: begin
case(cnt)
0: begin
cnt <= 1;
SEG[7:0] = 8'b11000000;
AN[7:0] = 8'b11111110;
end
1: begin
cnt <= 2;
SEG[7:0] = 8'b11111001;
AN[7:0] = 8'b11111101;
end
2: begin
cnt <= 0;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b11101111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
end
charge: begin
case(chargeMoney)
0: begin
SEG[7:0] <= 8'b11000000;
AN[7:0] <= 8'b01111111;
end
1: begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b10111111;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b01000000;
AN[7:0] <= 9'b01111111;
end
default: cnt = 0;
endcase
end
2: begin
SEG[7:0] <= 8'b11111001;
AN[7:0] <= 8'b01111111;
end
4: begin
SEG[7:0] <= 8'b10100100;
AN[7:0] <= 8'b01111111;
end
6: begin
SEG[7:0] <= 8'b10110000;
AN[7:0] <= 8'b01111111;
end
8: begin
SEG[7:0] <= 8'b10011001;
AN[7:0] <= 8'b01111111;
end
10: begin
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b01111111;
end
12: begin
SEG[7:0] = 8'b10000010;
AN[7:0] = 8'b01111111;
end
14: begin
SEG[7:0] = 8'b11111000;
AN[7:0] = 8'b01111111;
end
15: begin
case(cnt)
0:begin
cnt <= 1;
SEG[7:0] <= 8'b10010010;
AN[7:0] <= 8'b10111111;
end
1:begin
cnt <= 0;
SEG[7:0] <= 8'b01111000;
AN[7:0] <= 9'b01111111;
end
default: cnt = 0;
endcase
end
16: begin
SEG[7:0] = 8'b10000000;
AN[7:0] = 8'b01111111;
end
17: begin
case(cnt)
0:begin
cnt = 1;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b10111111;
end
1:begin
cnt = 0;
SEG[7:0] = 8'b00000000;
AN[7:0] = 9'b01111111;
end
default: cnt = 0;
endcase
end
18: begin
SEG[7:0] = 8'b10010000;
AN[7:0] = 8'b01111111;
end
19: begin
case(cnt)
0:begin
cnt = 1;
SEG[7:0] = 8'b10010010;
AN[7:0] = 8'b10111111;
end
1:begin
cnt = 0;
SEG[7:0] = 8'b00010000;
AN[7:0] = 9'b01111111;
end
default: cnt = 0;
endcase
end
default: cnt = 0;
endcase
end
endcase
end
endmodule | 2 |
3,220 | data/full_repos/permissive/103649428/VendingMachine_tb.v | 103,649,428 | VendingMachine_tb.v | v | 118 | 193 | [] | [] | [] | [(2, 40), (42, 61), (63, 84), (86, 118)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #2 is_sale = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #2 op_start = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2 item2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0.1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #7 coin1 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 coin2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1 buy = ~buy;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #6 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #0.5 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #0.5 item1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #0.5 money = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #3 chargeMoney = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #0.2 ck = ~ck;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/103649428/VendingMachine_tb.v:42: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'VendingMachine_tb\'\nmodule VendingMachine_tb();\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'Pay_tb\'\nmodule Pay_tb();\n ^~~~~~\n : ... Top module \'Time_tb\'\nmodule Time_tb();\n ^~~~~~~\n : ... Top module \'Show_tb\'\nmodule Show_tb();\n ^~~~~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:116: Cannot find file containing module: \'Show\'\n Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.v\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.sv\n Show\n Show.v\n Show.sv\n obj_dir/Show\n obj_dir/Show.v\n obj_dir/Show.sv\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:83: Cannot find file containing module: \'Time\'\n Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));\n ^~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:60: Cannot find file containing module: \'Pay\'\n Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));\n ^~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:38: Cannot find file containing module: \'VendingMachine\'\n VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy), \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 39 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,000 | module | module VendingMachine_tb();
reg reset, clk, item1, item2, coin1, coin2, buy;
reg is_sale, op_start, cancel_flag, confirm_flag;
wire [7:0]SEG;
wire [7:0]AN;
wire is_sale_xdc, power_on, hold_ind, charge_ind, drinktk_ind;
initial begin
reset <= 0;
clk <= 0;
item1 <= 0;
item2 <= 0;
coin1 <= 0;
coin2 <= 0;
buy <= 0 ;
is_sale <= 0;
op_start <= 0;
cancel_flag <= 0;
confirm_flag <= 0;
#2 reset = 1;
#2 is_sale = 1;
#2 op_start = 1;
#2 item2 = 1;
#2 confirm_flag = 1;#0.5 confirm_flag = 0;
#2 coin1 = 1;
#2 buy = 1; #0.5 buy = 0;
#2 buy = 1;#0.5 buy = 0;
#2 buy = 1;#0.5 buy = 0;
#2 cancel_flag = 1;#0.5 cancel_flag = 0;
end
always
#0.1 clk = ~clk;
VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy),
.is_sale(is_sale), .power_on(power_on), .op_start(op_start), .cancel_flag(cancel_flag), .hold_ind(hold_ind), .drinktk_ind(drinktk_ind), .charge_ind(charge_ind), .is_sale_xdc(is_sale_xdc));
endmodule | module VendingMachine_tb(); |
reg reset, clk, item1, item2, coin1, coin2, buy;
reg is_sale, op_start, cancel_flag, confirm_flag;
wire [7:0]SEG;
wire [7:0]AN;
wire is_sale_xdc, power_on, hold_ind, charge_ind, drinktk_ind;
initial begin
reset <= 0;
clk <= 0;
item1 <= 0;
item2 <= 0;
coin1 <= 0;
coin2 <= 0;
buy <= 0 ;
is_sale <= 0;
op_start <= 0;
cancel_flag <= 0;
confirm_flag <= 0;
#2 reset = 1;
#2 is_sale = 1;
#2 op_start = 1;
#2 item2 = 1;
#2 confirm_flag = 1;#0.5 confirm_flag = 0;
#2 coin1 = 1;
#2 buy = 1; #0.5 buy = 0;
#2 buy = 1;#0.5 buy = 0;
#2 buy = 1;#0.5 buy = 0;
#2 cancel_flag = 1;#0.5 cancel_flag = 0;
end
always
#0.1 clk = ~clk;
VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy),
.is_sale(is_sale), .power_on(power_on), .op_start(op_start), .cancel_flag(cancel_flag), .hold_ind(hold_ind), .drinktk_ind(drinktk_ind), .charge_ind(charge_ind), .is_sale_xdc(is_sale_xdc));
endmodule | 2 |
3,221 | data/full_repos/permissive/103649428/VendingMachine_tb.v | 103,649,428 | VendingMachine_tb.v | v | 118 | 193 | [] | [] | [] | [(2, 40), (42, 61), (63, 84), (86, 118)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #2 is_sale = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #2 op_start = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2 item2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0.1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #7 coin1 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 coin2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1 buy = ~buy;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #6 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #0.5 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #0.5 item1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #0.5 money = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #3 chargeMoney = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #0.2 ck = ~ck;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/103649428/VendingMachine_tb.v:42: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'VendingMachine_tb\'\nmodule VendingMachine_tb();\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'Pay_tb\'\nmodule Pay_tb();\n ^~~~~~\n : ... Top module \'Time_tb\'\nmodule Time_tb();\n ^~~~~~~\n : ... Top module \'Show_tb\'\nmodule Show_tb();\n ^~~~~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:116: Cannot find file containing module: \'Show\'\n Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.v\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.sv\n Show\n Show.v\n Show.sv\n obj_dir/Show\n obj_dir/Show.v\n obj_dir/Show.sv\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:83: Cannot find file containing module: \'Time\'\n Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));\n ^~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:60: Cannot find file containing module: \'Pay\'\n Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));\n ^~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:38: Cannot find file containing module: \'VendingMachine\'\n VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy), \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 39 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,000 | module | module Pay_tb();
reg [2:0]state;
reg coin1, coin2, buy;
wire [4:0]money;
initial begin
state <= 4;
coin1 <= 0;
coin2 <= 0;
buy <= 0;
#1 coin1 = 1;
#7 coin1 = 0;
#1 state = 0;
#1 state = 4;
#1 coin2 = 1;
end
always
#1 buy = ~buy;
Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));
endmodule | module Pay_tb(); |
reg [2:0]state;
reg coin1, coin2, buy;
wire [4:0]money;
initial begin
state <= 4;
coin1 <= 0;
coin2 <= 0;
buy <= 0;
#1 coin1 = 1;
#7 coin1 = 0;
#1 state = 0;
#1 state = 4;
#1 coin2 = 1;
end
always
#1 buy = ~buy;
Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));
endmodule | 2 |
3,222 | data/full_repos/permissive/103649428/VendingMachine_tb.v | 103,649,428 | VendingMachine_tb.v | v | 118 | 193 | [] | [] | [] | [(2, 40), (42, 61), (63, 84), (86, 118)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #2 is_sale = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #2 op_start = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2 item2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0.1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #7 coin1 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 coin2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1 buy = ~buy;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #6 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #0.5 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #0.5 item1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #0.5 money = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #3 chargeMoney = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #0.2 ck = ~ck;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/103649428/VendingMachine_tb.v:42: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'VendingMachine_tb\'\nmodule VendingMachine_tb();\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'Pay_tb\'\nmodule Pay_tb();\n ^~~~~~\n : ... Top module \'Time_tb\'\nmodule Time_tb();\n ^~~~~~~\n : ... Top module \'Show_tb\'\nmodule Show_tb();\n ^~~~~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:116: Cannot find file containing module: \'Show\'\n Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.v\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.sv\n Show\n Show.v\n Show.sv\n obj_dir/Show\n obj_dir/Show.v\n obj_dir/Show.sv\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:83: Cannot find file containing module: \'Time\'\n Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));\n ^~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:60: Cannot find file containing module: \'Pay\'\n Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));\n ^~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:38: Cannot find file containing module: \'VendingMachine\'\n VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy), \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 39 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,000 | module | module Time_tb();
reg clk, hasBuy;
reg [2:0]state;
wire drinktk_ind, over;
initial begin
state <= 5;
clk <= 0;
hasBuy <= 0;
#6 state = 0;
#1 state = 5;
#1 hasBuy = 1;
#1 state = 0;
#1 hasBuy = 0;
#1 state = 5;
end
always
#0.5 clk = ~clk;
Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));
endmodule | module Time_tb(); |
reg clk, hasBuy;
reg [2:0]state;
wire drinktk_ind, over;
initial begin
state <= 5;
clk <= 0;
hasBuy <= 0;
#6 state = 0;
#1 state = 5;
#1 hasBuy = 1;
#1 state = 0;
#1 hasBuy = 0;
#1 state = 5;
end
always
#0.5 clk = ~clk;
Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));
endmodule | 2 |
3,223 | data/full_repos/permissive/103649428/VendingMachine_tb.v | 103,649,428 | VendingMachine_tb.v | v | 118 | 193 | [] | [] | [] | [(2, 40), (42, 61), (63, 84), (86, 118)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #2 is_sale = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #2 op_start = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #2 item2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2 confirm_flag = 1;#0.5 confirm_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1; #0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2 buy = 1;#0.5 buy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #2 cancel_flag = 1;#0.5 cancel_flag = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0.1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 coin1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #7 coin1 = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 coin2 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #1 buy = ~buy;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #6 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #1 hasBuy = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 state = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #0.5 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #0.5 item1 = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #0.5 money = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #3 chargeMoney = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #3 state = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/103649428/VendingMachine_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #0.2 ck = ~ck;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/103649428/VendingMachine_tb.v:42: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'VendingMachine_tb\'\nmodule VendingMachine_tb();\n ^~~~~~~~~~~~~~~~~\n : ... Top module \'Pay_tb\'\nmodule Pay_tb();\n ^~~~~~\n : ... Top module \'Time_tb\'\nmodule Time_tb();\n ^~~~~~~\n : ... Top module \'Show_tb\'\nmodule Show_tb();\n ^~~~~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:116: Cannot find file containing module: \'Show\'\n Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));\n ^~~~\n ... Looked in:\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.v\n data/full_repos/permissive/103649428,data/full_repos/permissive/103649428/Show.sv\n Show\n Show.v\n Show.sv\n obj_dir/Show\n obj_dir/Show.v\n obj_dir/Show.sv\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:83: Cannot find file containing module: \'Time\'\n Time sim(.state(state), .clk(clk), .hasBuy(hasBuy), .drinktk_ind(drinktk_ind), .over(over));\n ^~~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:60: Cannot find file containing module: \'Pay\'\n Pay sim(.state(state), .buy(buy), .coin1(coin1), .coin2(coin2), .money(money));\n ^~~\n%Error: data/full_repos/permissive/103649428/VendingMachine_tb.v:38: Cannot find file containing module: \'VendingMachine\'\n VendingMachine sim(.reset(reset), .clk(clk), .SEG(SEG), .AN(AN), .item1(item1), .item2(item2), .coin1(coin1), .coin2(coin2), .confirm_flag(confirm_flag), .buy(buy), \n ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 39 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,000 | module | module Show_tb();
reg ck;
reg item1, item2;
reg [2:0]state;
reg [4:0]money;
reg [4:0]chargeMoney;
wire [7:0]SEG;
wire [7:0]AN;
initial begin
ck <= 0;
state <= 0;
item1 <= 0;
item2 <= 0;
money <= 0;
chargeMoney <= 0;
#3 state = 1;
#3 state = 2;
#3 state = 3;
#0.5 item1 = 1;
#3 state = 4;
#0.5 money = 3;
#3 chargeMoney = 1;
#3 state = 1;
end
always
#0.2 ck = ~ck;
Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));
endmodule | module Show_tb(); |
reg ck;
reg item1, item2;
reg [2:0]state;
reg [4:0]money;
reg [4:0]chargeMoney;
wire [7:0]SEG;
wire [7:0]AN;
initial begin
ck <= 0;
state <= 0;
item1 <= 0;
item2 <= 0;
money <= 0;
chargeMoney <= 0;
#3 state = 1;
#3 state = 2;
#3 state = 3;
#0.5 item1 = 1;
#3 state = 4;
#0.5 money = 3;
#3 chargeMoney = 1;
#3 state = 1;
end
always
#0.2 ck = ~ck;
Show sim(.ck(ck), .item1(item1), .item2(item2), .state(state), .money(money), .chargeMoney(chargeMoney), .SEG(SEG), .AN(AN));
endmodule | 2 |
3,224 | data/full_repos/permissive/10379745/testbench.sv | 10,379,745 | testbench.sv | sv | 31 | 43 | [] | [] | [] | null | line:9: before: ";" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/10379745/testbench.sv:9: Unsupported: Ignoring delay on this delayed statement.\n #10ns;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/10379745/testbench.sv:17: Unsupported: Ignoring delay on this delayed statement.\n #100ns;\n ^\n%Error: data/full_repos/permissive/10379745/testbench.sv:22: Can\'t find definition of \'INT_BTN\' in dotted variable: \'IO.INT_BTN\'\nassign IO.INT_BTN = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:23: Can\'t find definition of \'LEDS_RD\' in dotted variable: \'IO.LEDS_RD\'\nassign IO.LEDS_RD = 0;\n ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:26: Can\'t find definition of \'LEDS_WE\' in dotted variable: \'IO.LEDS_WE\'\n if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];\n ^~~~~~~\n%Error: data/full_repos/permissive/10379745/testbench.sv:26: Can\'t find definition of \'LEDS_WD\' in dotted variable: \'IO.LEDS_WD\'\n if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];\n ^~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,001 | module | module testbench;
logic CLK, RESET;
logic [7:0] leds;
if_io IO();
always
begin
#10ns;
CLK = ~CLK;
end
initial
begin
CLK = 0;
RESET = 1;
#100ns;
RESET = 0;
end
assign IO.INT_BTN = 0;
assign IO.LEDS_RD = 0;
always@(posedge CLK)
if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];
mcpu the_cpu(CLK, RESET, IO);
endmodule | module testbench; |
logic CLK, RESET;
logic [7:0] leds;
if_io IO();
always
begin
#10ns;
CLK = ~CLK;
end
initial
begin
CLK = 0;
RESET = 1;
#100ns;
RESET = 0;
end
assign IO.INT_BTN = 0;
assign IO.LEDS_RD = 0;
always@(posedge CLK)
if(IO.LEDS_WE) leds <= IO.LEDS_WD[7:0];
mcpu the_cpu(CLK, RESET, IO);
endmodule | 5 |
3,258 | data/full_repos/permissive/10379745/hard/exceptions.sv | 10,379,745 | exceptions.sv | sv | 56 | 89 | [] | [] | [] | null | line:3: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'exceptions\'\nmodule exceptions ( input CLK,\n ^~~~~~~~~~\n : ... Top module \'if_except\'\n if_except.excp EXC, \n ^~~~~~~~~\n : ... Top module \'if_debug\'\n if_debug.excp DEBUG ); \n ^~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Unsupported: Interfaced port on top level module\n if_except.excp EXC, \n ^~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:4: Unsupported: Interfaced port on top level module\n if_debug.excp DEBUG ); \n ^~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: Cannot find file containing interface: \'if_except\'\n if_except.excp EXC, \n ^~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/exceptions.sv:4: Cannot find file containing interface: \'if_debug\'\n if_debug.excp DEBUG ); \n ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/exceptions.sv:3: ../V3LinkDot.cpp:2055: Unlinked interface\n if_except.excp EXC, \n ^~~~~~~~~\n' | 1,008 | module | module exceptions ( input CLK,
input RESET,
if_except.excp EXC,
if_debug.excp DEBUG );
logic [31:0] epc, ejump_vector;
logic [7:0] e_vec;
logic [4:0] cause;
logic e_enter;
assign e_enter = RESET |
EXC.SYSCALL |
EXC.BREAK |
EXC.RI |
EXC.CpU |
EXC.OV |
EXC.IBE |
EXC.DBE |
EXC.INTERRUPT ;
assign e_vec = {EXC.IBE, EXC.RI, EXC.CpU, EXC.BREAK, EXC.SYSCALL,
EXC.OV, EXC.DBE, EXC.INTERRUPT};
always_comb
casex(e_vec)
8'b1XXXXXXX: cause = 5'd06;
8'b01XXXXXX: cause = 5'd10;
8'b001XXXXX: cause = 5'd11;
8'b0001XXXX: cause = 5'd09;
8'b00001XXX: cause = 5'd08;
8'b000001XX: cause = 5'd12;
8'b0000001X: cause = 5'd07;
8'b00000001: cause = 5'd00;
default: cause = 5'd31;
endcase
mux2 #(32) epc_sel( EXC.DELAY_SLOT, EXC.PC_WB, (EXC.PC_WB - 3'd4), epc );
mux2 #(32) vec_sel( RESET | DEBUG.INST_SUBST, 32'h00000100, 32'h00000000, ejump_vector);
assign EXC.RESET = e_enter | EXC.ERET;
assign EXC.E_ENTER = e_enter;
assign EXC.E_USE_VEC = e_enter | EXC.ERET | DEBUG.INST_SUBST;
assign EXC.VECTOR = EXC.ERET ? EXC.EPC_Q : ejump_vector;
assign EXC.CAUSE = cause;
assign EXC.EPC = epc;
endmodule | module exceptions ( input CLK,
input RESET,
if_except.excp EXC,
if_debug.excp DEBUG ); |
logic [31:0] epc, ejump_vector;
logic [7:0] e_vec;
logic [4:0] cause;
logic e_enter;
assign e_enter = RESET |
EXC.SYSCALL |
EXC.BREAK |
EXC.RI |
EXC.CpU |
EXC.OV |
EXC.IBE |
EXC.DBE |
EXC.INTERRUPT ;
assign e_vec = {EXC.IBE, EXC.RI, EXC.CpU, EXC.BREAK, EXC.SYSCALL,
EXC.OV, EXC.DBE, EXC.INTERRUPT};
always_comb
casex(e_vec)
8'b1XXXXXXX: cause = 5'd06;
8'b01XXXXXX: cause = 5'd10;
8'b001XXXXX: cause = 5'd11;
8'b0001XXXX: cause = 5'd09;
8'b00001XXX: cause = 5'd08;
8'b000001XX: cause = 5'd12;
8'b0000001X: cause = 5'd07;
8'b00000001: cause = 5'd00;
default: cause = 5'd31;
endcase
mux2 #(32) epc_sel( EXC.DELAY_SLOT, EXC.PC_WB, (EXC.PC_WB - 3'd4), epc );
mux2 #(32) vec_sel( RESET | DEBUG.INST_SUBST, 32'h00000100, 32'h00000000, ejump_vector);
assign EXC.RESET = e_enter | EXC.ERET;
assign EXC.E_ENTER = e_enter;
assign EXC.E_USE_VEC = e_enter | EXC.ERET | DEBUG.INST_SUBST;
assign EXC.VECTOR = EXC.ERET ? EXC.EPC_Q : ejump_vector;
assign EXC.CAUSE = cause;
assign EXC.EPC = epc;
endmodule | 5 |
3,259 | data/full_repos/permissive/10379745/hard/hazard_unit.sv | 10,379,745 | hazard_unit.sv | sv | 54 | 85 | [] | [] | [] | null | line:1: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'hazard_unit\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n ^~~~~~~~~~~\n : ... Top module \'if_hazard\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n ^~~~~~~~~\n%Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Unsupported: Interfaced port on top level module\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n ^~~~\n%Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: Cannot find file containing interface: \'if_hazard\'\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n ^~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/hazard_unit.sv:1: ../V3LinkDot.cpp:2055: Unlinked interface\nmodule hazard_unit ( if_hazard.hzrd HZRD );\n ^~~~~~~~~\n' | 1,009 | module | module hazard_unit ( if_hazard.hzrd HZRD );
assign HZRD.ALU_FWD_A =
((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
2'b00 ;
assign HZRD.ALU_FWD_B =
((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
2'b00 ;
logic lw_stall, mdiv_stall, load_or_mf_at_m, mfhl_at_m;
assign load_or_mf_at_m = ( HZRD.ALUORMEM_M | mfhl_at_m ) &
( ( HZRD.RS_E == HZRD.REGDST_M ) |
( HZRD.RT_E == HZRD.REGDST_M ) );
assign lw_stall = load_or_mf_at_m;
assign mfhl_at_m = ^HZRD.MFCOP_SEL_M;
assign mdiv_stall = HZRD.MDIV_BUSY_M & mfhl_at_m;
assign HZRD.STALL_FDE = lw_stall | mdiv_stall;
assign HZRD.STALL_M = mdiv_stall;
assign HZRD.RESET_M = lw_stall & ~mdiv_stall;
assign HZRD.RESET_W = mdiv_stall;
endmodule | module hazard_unit ( if_hazard.hzrd HZRD ); |
assign HZRD.ALU_FWD_A =
((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
((HZRD.RS_E != 0) && (HZRD.RS_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
2'b00 ;
assign HZRD.ALU_FWD_B =
((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_M ) && HZRD.WRITEREG_M ) ? 2'b01 :
((HZRD.RT_E != 0) && (HZRD.RT_E == HZRD.REGDST_W ) && HZRD.WRITEREG_W ) ? 2'b10 :
2'b00 ;
logic lw_stall, mdiv_stall, load_or_mf_at_m, mfhl_at_m;
assign load_or_mf_at_m = ( HZRD.ALUORMEM_M | mfhl_at_m ) &
( ( HZRD.RS_E == HZRD.REGDST_M ) |
( HZRD.RT_E == HZRD.REGDST_M ) );
assign lw_stall = load_or_mf_at_m;
assign mfhl_at_m = ^HZRD.MFCOP_SEL_M;
assign mdiv_stall = HZRD.MDIV_BUSY_M & mfhl_at_m;
assign HZRD.STALL_FDE = lw_stall | mdiv_stall;
assign HZRD.STALL_M = mdiv_stall;
assign HZRD.RESET_M = lw_stall & ~mdiv_stall;
assign HZRD.RESET_W = mdiv_stall;
endmodule | 5 |
3,260 | data/full_repos/permissive/10379745/hard/io_space.sv | 10,379,745 | io_space.sv | sv | 41 | 107 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hard/io_space.sv:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'io_space\'\nmodule io_space #( parameter RAM_DEPTH = 14 )\n ^~~~~~~~\n : ... Top module \'if_io\'\n if_io.io IO ); \n ^~~~~\n%Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: Unsupported: Interfaced port on top level module\n if_io.io IO ); \n ^~\n%Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: Cannot find file containing interface: \'if_io\'\n if_io.io IO ); \n ^~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hard/io_space.sv:11: ../V3LinkDot.cpp:2055: Unlinked interface\n if_io.io IO ); \n ^~~~~\n' | 1,011 | module | module io_space #( parameter RAM_DEPTH = 14 )
( input CLK,
input RESET,
input DBE,
input IO_REQ,
input IO_WE,
input IO_RE,
input [RAM_DEPTH-1:0] IO_ADDR,
input [31:0] IO_WD,
output [31:0] IO_RD,
if_io.io IO );
logic [RAM_DEPTH-1:0] addr_q;
logic [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select;
ffd #(4) ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32) data_fd(CLK, RESET, 1'b1, IO_WD, wd_q);
assign req_valid = ioreq_q & ~dbe_q;
assign leds_select = (addr_q[7:4] == 4'd0);
assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q;
assign IO.LEDS_A = addr_q[3:0];
mux8 #(32) read_mux( addr_q[6:4],
IO.LEDS_RD,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
IO_RD );
endmodule | module io_space #( parameter RAM_DEPTH = 14 )
( input CLK,
input RESET,
input DBE,
input IO_REQ,
input IO_WE,
input IO_RE,
input [RAM_DEPTH-1:0] IO_ADDR,
input [31:0] IO_WD,
output [31:0] IO_RD,
if_io.io IO ); |
logic [RAM_DEPTH-1:0] addr_q;
logic [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select;
ffd #(4) ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32) data_fd(CLK, RESET, 1'b1, IO_WD, wd_q);
assign req_valid = ioreq_q & ~dbe_q;
assign leds_select = (addr_q[7:4] == 4'd0);
assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q;
assign IO.LEDS_A = addr_q[3:0];
mux8 #(32) read_mux( addr_q[6:4],
IO.LEDS_RD,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
32'd0,
IO_RD );
endmodule | 5 |
3,266 | data/full_repos/permissive/10379745/hard/muldiv.sv | 10,379,745 | muldiv.sv | sv | 104 | 103 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/10379745/hard/muldiv.sv:70: Cannot find include file: hard/log2.inc\n`include "hard/log2.inc" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.v\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.sv\n hard/log2.inc\n hard/log2.inc.v\n hard/log2.inc.sv\n obj_dir/hard/log2.inc\n obj_dir/hard/log2.inc.v\n obj_dir/hard/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 1,014 | module | module muldiv ( input CLK,
input RESET,
input EN,
input [2:0] OP,
input signed [31:0] A,
input signed [31:0] B,
output [31:0] HI,
output [31:0] LO,
output BUSY );
logic busy_mul, busy_div, div_wr;
logic [2:0] op_q;
logic signed [63:0] mt_hilo, hilo, hilo_q;
logic signed [63:0] s_mult, s_mult_q, s_mad_q;
logic [31:0] quot, rem, a_q;
assign s_mult = A*B;
assign s_mad_q = s_mult_q + hilo_q;
ffd #( 3) op_reg(CLK, RESET, EN, OP, op_q);
ffd #( 32) mt_reg ( CLK, RESET, EN, A, a_q );
ffd #( 64) mul_reg ( CLK, RESET, EN, s_mult, s_mult_q );
ffd #( 1) busym_reg( CLK, RESET, 1'b1, EN & (OP[1:0] != 2'b11), busy_mul );
assign mt_hilo = op_q[2] ? {a_q, hilo_q[31:0]} : {hilo_q[63:32], a_q};
mc_div #(32) mc_div ( .CLK ( CLK ),
.RESET ( RESET ),
.GO ( EN & (OP[1:0] == 2'b11)),
.BUSY ( busy_div ),
.W_RESULT ( div_wr ),
.A ( A ),
.B ( B ),
.QUOT ( quot ),
.REM ( rem ) );
mux4 #(64) hilo_wr_mux ( .S ( op_q[1:0] ),
.D0 ( s_mult_q ),
.D1 ( s_mad_q ),
.D2 ( mt_hilo ),
.D3 ( {rem, quot} ),
.Y ( hilo ) );
ffd #( 64) hi_lo_reg(CLK, RESET, busy_mul | div_wr, hilo, hilo_q);
assign HI = hilo_q[63:32];
assign LO = hilo_q[31:0];
assign BUSY = busy_mul | busy_div;
endmodule | module muldiv ( input CLK,
input RESET,
input EN,
input [2:0] OP,
input signed [31:0] A,
input signed [31:0] B,
output [31:0] HI,
output [31:0] LO,
output BUSY ); |
logic busy_mul, busy_div, div_wr;
logic [2:0] op_q;
logic signed [63:0] mt_hilo, hilo, hilo_q;
logic signed [63:0] s_mult, s_mult_q, s_mad_q;
logic [31:0] quot, rem, a_q;
assign s_mult = A*B;
assign s_mad_q = s_mult_q + hilo_q;
ffd #( 3) op_reg(CLK, RESET, EN, OP, op_q);
ffd #( 32) mt_reg ( CLK, RESET, EN, A, a_q );
ffd #( 64) mul_reg ( CLK, RESET, EN, s_mult, s_mult_q );
ffd #( 1) busym_reg( CLK, RESET, 1'b1, EN & (OP[1:0] != 2'b11), busy_mul );
assign mt_hilo = op_q[2] ? {a_q, hilo_q[31:0]} : {hilo_q[63:32], a_q};
mc_div #(32) mc_div ( .CLK ( CLK ),
.RESET ( RESET ),
.GO ( EN & (OP[1:0] == 2'b11)),
.BUSY ( busy_div ),
.W_RESULT ( div_wr ),
.A ( A ),
.B ( B ),
.QUOT ( quot ),
.REM ( rem ) );
mux4 #(64) hilo_wr_mux ( .S ( op_q[1:0] ),
.D0 ( s_mult_q ),
.D1 ( s_mad_q ),
.D2 ( mt_hilo ),
.D3 ( {rem, quot} ),
.Y ( hilo ) );
ffd #( 64) hi_lo_reg(CLK, RESET, busy_mul | div_wr, hilo, hilo_q);
assign HI = hilo_q[63:32];
assign LO = hilo_q[31:0];
assign BUSY = busy_mul | busy_div;
endmodule | 5 |
3,267 | data/full_repos/permissive/10379745/hard/muldiv.sv | 10,379,745 | muldiv.sv | sv | 104 | 103 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/10379745/hard/muldiv.sv:70: Cannot find include file: hard/log2.inc\n`include "hard/log2.inc" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.v\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/hard/log2.inc.sv\n hard/log2.inc\n hard/log2.inc.v\n hard/log2.inc.sv\n obj_dir/hard/log2.inc\n obj_dir/hard/log2.inc.v\n obj_dir/hard/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 1,014 | module | module mc_div #( parameter W = 4 )
( input CLK,
input RESET,
input GO,
output BUSY,
output W_RESULT,
input [W-1:0] A,
input [W-1:0] B,
output [W-1:0] QUOT,
output [W-1:0] REM );
`include "hard/log2.inc"
localparam C = log2(W);
logic [2*W-1:0] nextval, Q;
logic [W-1:0] dvsr, hiword;
logic signed [W:0] diff;
logic [C-1:0] cnt;
logic busy;
assign hiword = Q[2*W-2:W-1];
assign diff = hiword - dvsr;
assign nextval = GO ? { {W{1'b0}}, A} :
diff[W] ? Q << 1 :
{diff[W-1:0], Q[W-2:0], 1'b1} ;
ffd #(W) dvsr_reg(CLK, RESET, GO, B, dvsr);
ffd #(2*W) result_reg(CLK, RESET, GO | busy, nextval, Q);
rsd busy_reg(CLK, RESET | W_RESULT, GO, busy );
counter #(C) counter( CLK, GO, busy, cnt );
assign BUSY = busy;
assign W_RESULT = (cnt == W);
assign REM = Q[2*W-1:W];
assign QUOT = Q[W-1:0];
endmodule | module mc_div #( parameter W = 4 )
( input CLK,
input RESET,
input GO,
output BUSY,
output W_RESULT,
input [W-1:0] A,
input [W-1:0] B,
output [W-1:0] QUOT,
output [W-1:0] REM ); |
`include "hard/log2.inc"
localparam C = log2(W);
logic [2*W-1:0] nextval, Q;
logic [W-1:0] dvsr, hiword;
logic signed [W:0] diff;
logic [C-1:0] cnt;
logic busy;
assign hiword = Q[2*W-2:W-1];
assign diff = hiword - dvsr;
assign nextval = GO ? { {W{1'b0}}, A} :
diff[W] ? Q << 1 :
{diff[W-1:0], Q[W-2:0], 1'b1} ;
ffd #(W) dvsr_reg(CLK, RESET, GO, B, dvsr);
ffd #(2*W) result_reg(CLK, RESET, GO | busy, nextval, Q);
rsd busy_reg(CLK, RESET | W_RESULT, GO, busy );
counter #(C) counter( CLK, GO, busy, cnt );
assign BUSY = busy;
assign W_RESULT = (cnt == W);
assign REM = Q[2*W-1:W];
assign QUOT = Q[W-1:0];
endmodule | 5 |
3,268 | data/full_repos/permissive/10379745/hard/onchip_ram.sv | 10,379,745 | onchip_ram.sv | sv | 41 | 76 | [] | [] | [] | null | line:15: before: "[" | data/verilator_xmls/395bb0bc-db76-4b35-9e08-585f344bf7d8.xml | null | 1,015 | module | module onchip_ram #( parameter D = 14 )
( input CLK,
input [D-1:0] I_ADDR,
output [31:0] I_RD,
input [D-1:0] D_ADDR,
input D_WE,
input [3:0] D_BE,
input [31:0] D_WD,
output [31:0] D_RD );
logic [3:0][7:0] RAM[0:2**D-1];
logic [31:0] rr_i, rr_d;
initial
$readmemh ("soft/program.txt", RAM);
always_ff@(posedge CLK)
begin
if (D_WE)
begin
if(D_BE[0]) RAM[D_ADDR][0] <= D_WD[07:00];
if(D_BE[1]) RAM[D_ADDR][1] <= D_WD[15:08];
if(D_BE[2]) RAM[D_ADDR][2] <= D_WD[23:16];
if(D_BE[3]) RAM[D_ADDR][3] <= D_WD[31:24];
end
rr_d <= RAM[D_ADDR];
end
always_ff@(posedge CLK)
rr_i <= RAM[I_ADDR];
assign D_RD = rr_d;
assign I_RD = rr_i;
endmodule | module onchip_ram #( parameter D = 14 )
( input CLK,
input [D-1:0] I_ADDR,
output [31:0] I_RD,
input [D-1:0] D_ADDR,
input D_WE,
input [3:0] D_BE,
input [31:0] D_WD,
output [31:0] D_RD ); |
logic [3:0][7:0] RAM[0:2**D-1];
logic [31:0] rr_i, rr_d;
initial
$readmemh ("soft/program.txt", RAM);
always_ff@(posedge CLK)
begin
if (D_WE)
begin
if(D_BE[0]) RAM[D_ADDR][0] <= D_WD[07:00];
if(D_BE[1]) RAM[D_ADDR][1] <= D_WD[15:08];
if(D_BE[2]) RAM[D_ADDR][2] <= D_WD[23:16];
if(D_BE[3]) RAM[D_ADDR][3] <= D_WD[31:24];
end
rr_d <= RAM[D_ADDR];
end
always_ff@(posedge CLK)
rr_i <= RAM[I_ADDR];
assign D_RD = rr_d;
assign I_RD = rr_i;
endmodule | 5 |
3,270 | data/full_repos/permissive/10379745/hard/regfile.sv | 10,379,745 | regfile.sv | sv | 138 | 92 | [] | [] | [] | null | line:65: before: "get_rname" | null | 1: b'%Error: data/full_repos/permissive/10379745/hard/regfile.sv:47: Cannot find file containing module: \'ffds\'\nffds #(5) aq1_reg(CLK, RD_ADDR_1, a1q );\n^~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.v\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.sv\n ffds\n ffds.v\n ffds.sv\n obj_dir/ffds\n obj_dir/ffds.v\n obj_dir/ffds.sv\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:48: Cannot find file containing module: \'ffds\'\nffds #(5) aq2_reg(CLK, RD_ADDR_2, a2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:49: Cannot find file containing module: \'ffds\'\nffds #(1) bp1_reg(CLK, bp_1_mem, bp_1_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:50: Cannot find file containing module: \'ffds\'\nffds #(1) bp2_reg(CLK, bp_2_mem, bp_2_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:51: Cannot find file containing module: \'ffds\'\nffds #(1) zr1_reg(CLK, zero_1, zero_1q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:52: Cannot find file containing module: \'ffds\'\nffds #(1) zr2_reg(CLK, zero_2, zero_2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:53: Cannot find file containing module: \'ffds\'\nffds #(32) bp_save(CLK, W_DATA, bypass_save );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:55: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:56: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:58: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:59: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:61: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_1(zero_1q, rd1_bp_cpu, 32\'d0, R_DATA_1);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:62: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_2(zero_2q, rd2_bp_cpu, 32\'d0, R_DATA_2);\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/10379745/hard/regfile.sv:106: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'WR_ADDR_3\' generates 5 bits.\n : ... In instance regfile\n if(WE && WR_ADDR_3)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 13 error(s), 1 warning(s)\n' | 1,017 | module | module regfile( input CLK,
input [4:0] RD_ADDR_1,
input [4:0] RD_ADDR_2,
input [4:0] WR_ADDR_3,
input [31:0] W_DATA,
input WE,
output [31:0] R_DATA_1,
output [31:0] R_DATA_2);
logic [31:0] rd1_mem, rd2_mem, rd1_bp_mem, rd2_bp_mem,
rd1_bp_cpu, rd2_bp_cpu, bypass_save;
logic [4:0] a1q, a2q;
logic bp_1_mem, bp_2_mem, bp_1_mem_q, bp_2_mem_q,
zero_1, zero_2, zero_1q, zero_2q,
bp_1_cpu, bp_2_cpu;
assign bp_1_cpu = WE & (WR_ADDR_3 == a1q );
assign bp_2_cpu = WE & (WR_ADDR_3 == a2q );
assign bp_1_mem = WE & (WR_ADDR_3 == RD_ADDR_1 );
assign bp_2_mem = WE & (WR_ADDR_3 == RD_ADDR_2 );
assign zero_1 = (RD_ADDR_1 == 5'd0);
assign zero_2 = (RD_ADDR_2 == 5'd0);
rf_memory rf_memory ( .CLK( CLK ),
.A1R( RD_ADDR_1 ),
.A2R( RD_ADDR_2 ),
.A3W( WR_ADDR_3 ),
.WD ( W_DATA ),
.WE ( WE ),
.RD1( rd1_mem ),
.RD2( rd2_mem ) );
ffds #(5) aq1_reg(CLK, RD_ADDR_1, a1q );
ffds #(5) aq2_reg(CLK, RD_ADDR_2, a2q );
ffds #(1) bp1_reg(CLK, bp_1_mem, bp_1_mem_q );
ffds #(1) bp2_reg(CLK, bp_2_mem, bp_2_mem_q );
ffds #(1) zr1_reg(CLK, zero_1, zero_1q );
ffds #(1) zr2_reg(CLK, zero_2, zero_2q );
ffds #(32) bp_save(CLK, W_DATA, bypass_save );
mux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);
mux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);
mux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);
mux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);
mux2 zero_mux_1(zero_1q, rd1_bp_cpu, 32'd0, R_DATA_1);
mux2 zero_mux_2(zero_2q, rd2_bp_cpu, 32'd0, R_DATA_2);
function string get_rname(input [4:0] idx);
begin
case(idx)
5'd00: get_rname = "$zero";
5'd01: get_rname = "$at";
5'd02: get_rname = "$v0";
5'd03: get_rname = "$v1";
5'd04: get_rname = "$a0";
5'd05: get_rname = "$a1";
5'd06: get_rname = "$a2";
5'd07: get_rname = "$a3";
5'd08: get_rname = "$t0";
5'd09: get_rname = "$t1";
5'd10: get_rname = "$t2";
5'd11: get_rname = "$t3";
5'd12: get_rname = "$t4";
5'd13: get_rname = "$t5";
5'd14: get_rname = "$t6";
5'd15: get_rname = "$t7";
5'd16: get_rname = "$s0";
5'd17: get_rname = "$s1";
5'd18: get_rname = "$s2";
5'd19: get_rname = "$s3";
5'd20: get_rname = "$s4";
5'd21: get_rname = "$s5";
5'd22: get_rname = "$s6";
5'd23: get_rname = "$s7";
5'd24: get_rname = "$t8";
5'd25: get_rname = "$t9";
5'd26: get_rname = "$k0";
5'd27: get_rname = "$k1";
5'd28: get_rname = "$gp";
5'd29: get_rname = "$sp";
5'd30: get_rname = "$fp";
5'd31: get_rname = "$ra";
endcase
end
endfunction
always_ff@ (posedge CLK)
if(WE && WR_ADDR_3)
$display("[%8tps] REFILE WR: %08x --> %s (r%02d)", $time,
W_DATA,
get_rname(WR_ADDR_3),
WR_ADDR_3);
endmodule | module regfile( input CLK,
input [4:0] RD_ADDR_1,
input [4:0] RD_ADDR_2,
input [4:0] WR_ADDR_3,
input [31:0] W_DATA,
input WE,
output [31:0] R_DATA_1,
output [31:0] R_DATA_2); |
logic [31:0] rd1_mem, rd2_mem, rd1_bp_mem, rd2_bp_mem,
rd1_bp_cpu, rd2_bp_cpu, bypass_save;
logic [4:0] a1q, a2q;
logic bp_1_mem, bp_2_mem, bp_1_mem_q, bp_2_mem_q,
zero_1, zero_2, zero_1q, zero_2q,
bp_1_cpu, bp_2_cpu;
assign bp_1_cpu = WE & (WR_ADDR_3 == a1q );
assign bp_2_cpu = WE & (WR_ADDR_3 == a2q );
assign bp_1_mem = WE & (WR_ADDR_3 == RD_ADDR_1 );
assign bp_2_mem = WE & (WR_ADDR_3 == RD_ADDR_2 );
assign zero_1 = (RD_ADDR_1 == 5'd0);
assign zero_2 = (RD_ADDR_2 == 5'd0);
rf_memory rf_memory ( .CLK( CLK ),
.A1R( RD_ADDR_1 ),
.A2R( RD_ADDR_2 ),
.A3W( WR_ADDR_3 ),
.WD ( W_DATA ),
.WE ( WE ),
.RD1( rd1_mem ),
.RD2( rd2_mem ) );
ffds #(5) aq1_reg(CLK, RD_ADDR_1, a1q );
ffds #(5) aq2_reg(CLK, RD_ADDR_2, a2q );
ffds #(1) bp1_reg(CLK, bp_1_mem, bp_1_mem_q );
ffds #(1) bp2_reg(CLK, bp_2_mem, bp_2_mem_q );
ffds #(1) zr1_reg(CLK, zero_1, zero_1q );
ffds #(1) zr2_reg(CLK, zero_2, zero_2q );
ffds #(32) bp_save(CLK, W_DATA, bypass_save );
mux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);
mux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);
mux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);
mux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);
mux2 zero_mux_1(zero_1q, rd1_bp_cpu, 32'd0, R_DATA_1);
mux2 zero_mux_2(zero_2q, rd2_bp_cpu, 32'd0, R_DATA_2);
function string get_rname(input [4:0] idx);
begin
case(idx)
5'd00: get_rname = "$zero";
5'd01: get_rname = "$at";
5'd02: get_rname = "$v0";
5'd03: get_rname = "$v1";
5'd04: get_rname = "$a0";
5'd05: get_rname = "$a1";
5'd06: get_rname = "$a2";
5'd07: get_rname = "$a3";
5'd08: get_rname = "$t0";
5'd09: get_rname = "$t1";
5'd10: get_rname = "$t2";
5'd11: get_rname = "$t3";
5'd12: get_rname = "$t4";
5'd13: get_rname = "$t5";
5'd14: get_rname = "$t6";
5'd15: get_rname = "$t7";
5'd16: get_rname = "$s0";
5'd17: get_rname = "$s1";
5'd18: get_rname = "$s2";
5'd19: get_rname = "$s3";
5'd20: get_rname = "$s4";
5'd21: get_rname = "$s5";
5'd22: get_rname = "$s6";
5'd23: get_rname = "$s7";
5'd24: get_rname = "$t8";
5'd25: get_rname = "$t9";
5'd26: get_rname = "$k0";
5'd27: get_rname = "$k1";
5'd28: get_rname = "$gp";
5'd29: get_rname = "$sp";
5'd30: get_rname = "$fp";
5'd31: get_rname = "$ra";
endcase
end
endfunction
always_ff@ (posedge CLK)
if(WE && WR_ADDR_3)
$display("[%8tps] REFILE WR: %08x --> %s (r%02d)", $time,
W_DATA,
get_rname(WR_ADDR_3),
WR_ADDR_3);
endmodule | 5 |
3,271 | data/full_repos/permissive/10379745/hard/regfile.sv | 10,379,745 | regfile.sv | sv | 138 | 92 | [] | [] | [] | null | line:65: before: "get_rname" | null | 1: b'%Error: data/full_repos/permissive/10379745/hard/regfile.sv:47: Cannot find file containing module: \'ffds\'\nffds #(5) aq1_reg(CLK, RD_ADDR_1, a1q );\n^~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.v\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.sv\n ffds\n ffds.v\n ffds.sv\n obj_dir/ffds\n obj_dir/ffds.v\n obj_dir/ffds.sv\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:48: Cannot find file containing module: \'ffds\'\nffds #(5) aq2_reg(CLK, RD_ADDR_2, a2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:49: Cannot find file containing module: \'ffds\'\nffds #(1) bp1_reg(CLK, bp_1_mem, bp_1_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:50: Cannot find file containing module: \'ffds\'\nffds #(1) bp2_reg(CLK, bp_2_mem, bp_2_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:51: Cannot find file containing module: \'ffds\'\nffds #(1) zr1_reg(CLK, zero_1, zero_1q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:52: Cannot find file containing module: \'ffds\'\nffds #(1) zr2_reg(CLK, zero_2, zero_2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:53: Cannot find file containing module: \'ffds\'\nffds #(32) bp_save(CLK, W_DATA, bypass_save );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:55: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:56: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:58: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:59: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:61: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_1(zero_1q, rd1_bp_cpu, 32\'d0, R_DATA_1);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:62: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_2(zero_2q, rd2_bp_cpu, 32\'d0, R_DATA_2);\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/10379745/hard/regfile.sv:106: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'WR_ADDR_3\' generates 5 bits.\n : ... In instance regfile\n if(WE && WR_ADDR_3)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 13 error(s), 1 warning(s)\n' | 1,017 | module | module rf_memory( input CLK,
input [4:0] A1R,
input [4:0] A2R,
input [4:0] A3W,
input [31:0] WD,
input WE,
output [31:0] RD1,
output [31:0] RD2 );
logic [31:0] rf[31:0];
logic [31:0] reg_rd1, reg_rd2;
always_ff@(posedge CLK)
begin
reg_rd1 <= rf[A1R];
reg_rd2 <= rf[A2R];
if(WE) rf[A3W] <= WD;
end
assign RD1 = reg_rd1;
assign RD2 = reg_rd2;
endmodule | module rf_memory( input CLK,
input [4:0] A1R,
input [4:0] A2R,
input [4:0] A3W,
input [31:0] WD,
input WE,
output [31:0] RD1,
output [31:0] RD2 ); |
logic [31:0] rf[31:0];
logic [31:0] reg_rd1, reg_rd2;
always_ff@(posedge CLK)
begin
reg_rd1 <= rf[A1R];
reg_rd2 <= rf[A2R];
if(WE) rf[A3W] <= WD;
end
assign RD1 = reg_rd1;
assign RD2 = reg_rd2;
endmodule | 5 |
3,272 | data/full_repos/permissive/10379745/hard/regfile.sv | 10,379,745 | regfile.sv | sv | 138 | 92 | [] | [] | [] | null | line:65: before: "get_rname" | null | 1: b'%Error: data/full_repos/permissive/10379745/hard/regfile.sv:47: Cannot find file containing module: \'ffds\'\nffds #(5) aq1_reg(CLK, RD_ADDR_1, a1q );\n^~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.v\n data/full_repos/permissive/10379745/hard,data/full_repos/permissive/10379745/ffds.sv\n ffds\n ffds.v\n ffds.sv\n obj_dir/ffds\n obj_dir/ffds.v\n obj_dir/ffds.sv\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:48: Cannot find file containing module: \'ffds\'\nffds #(5) aq2_reg(CLK, RD_ADDR_2, a2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:49: Cannot find file containing module: \'ffds\'\nffds #(1) bp1_reg(CLK, bp_1_mem, bp_1_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:50: Cannot find file containing module: \'ffds\'\nffds #(1) bp2_reg(CLK, bp_2_mem, bp_2_mem_q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:51: Cannot find file containing module: \'ffds\'\nffds #(1) zr1_reg(CLK, zero_1, zero_1q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:52: Cannot find file containing module: \'ffds\'\nffds #(1) zr2_reg(CLK, zero_2, zero_2q );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:53: Cannot find file containing module: \'ffds\'\nffds #(32) bp_save(CLK, W_DATA, bypass_save );\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:55: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_1(bp_1_mem_q, rd1_mem, bypass_save, rd1_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:56: Cannot find file containing module: \'mux2\'\nmux2 bp_mem_mux_2(bp_2_mem_q, rd2_mem, bypass_save, rd2_bp_mem);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:58: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_1(bp_1_cpu, rd1_bp_mem, W_DATA, rd1_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:59: Cannot find file containing module: \'mux2\'\nmux2 bp_cpu_mux_2(bp_2_cpu, rd2_bp_mem, W_DATA, rd2_bp_cpu);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:61: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_1(zero_1q, rd1_bp_cpu, 32\'d0, R_DATA_1);\n^~~~\n%Error: data/full_repos/permissive/10379745/hard/regfile.sv:62: Cannot find file containing module: \'mux2\'\nmux2 zero_mux_2(zero_2q, rd2_bp_cpu, 32\'d0, R_DATA_2);\n^~~~\n%Warning-WIDTH: data/full_repos/permissive/10379745/hard/regfile.sv:106: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'WR_ADDR_3\' generates 5 bits.\n : ... In instance regfile\n if(WE && WR_ADDR_3)\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 13 error(s), 1 warning(s)\n' | 1,017 | function | function string get_rname(input [4:0] idx);
begin
case(idx)
5'd00: get_rname = "$zero";
5'd01: get_rname = "$at";
5'd02: get_rname = "$v0";
5'd03: get_rname = "$v1";
5'd04: get_rname = "$a0";
5'd05: get_rname = "$a1";
5'd06: get_rname = "$a2";
5'd07: get_rname = "$a3";
5'd08: get_rname = "$t0";
5'd09: get_rname = "$t1";
5'd10: get_rname = "$t2";
5'd11: get_rname = "$t3";
5'd12: get_rname = "$t4";
5'd13: get_rname = "$t5";
5'd14: get_rname = "$t6";
5'd15: get_rname = "$t7";
5'd16: get_rname = "$s0";
5'd17: get_rname = "$s1";
5'd18: get_rname = "$s2";
5'd19: get_rname = "$s3";
5'd20: get_rname = "$s4";
5'd21: get_rname = "$s5";
5'd22: get_rname = "$s6";
5'd23: get_rname = "$s7";
5'd24: get_rname = "$t8";
5'd25: get_rname = "$t9";
5'd26: get_rname = "$k0";
5'd27: get_rname = "$k1";
5'd28: get_rname = "$gp";
5'd29: get_rname = "$sp";
5'd30: get_rname = "$fp";
5'd31: get_rname = "$ra";
endcase
end
endfunction | function string get_rname(input [4:0] idx); |
begin
case(idx)
5'd00: get_rname = "$zero";
5'd01: get_rname = "$at";
5'd02: get_rname = "$v0";
5'd03: get_rname = "$v1";
5'd04: get_rname = "$a0";
5'd05: get_rname = "$a1";
5'd06: get_rname = "$a2";
5'd07: get_rname = "$a3";
5'd08: get_rname = "$t0";
5'd09: get_rname = "$t1";
5'd10: get_rname = "$t2";
5'd11: get_rname = "$t3";
5'd12: get_rname = "$t4";
5'd13: get_rname = "$t5";
5'd14: get_rname = "$t6";
5'd15: get_rname = "$t7";
5'd16: get_rname = "$s0";
5'd17: get_rname = "$s1";
5'd18: get_rname = "$s2";
5'd19: get_rname = "$s3";
5'd20: get_rname = "$s4";
5'd21: get_rname = "$s5";
5'd22: get_rname = "$s6";
5'd23: get_rname = "$s7";
5'd24: get_rname = "$t8";
5'd25: get_rname = "$t9";
5'd26: get_rname = "$k0";
5'd27: get_rname = "$k1";
5'd28: get_rname = "$gp";
5'd29: get_rname = "$sp";
5'd30: get_rname = "$fp";
5'd31: get_rname = "$ra";
endcase
end
endfunction | 5 |
3,277 | data/full_repos/permissive/10379745/hard/board_io/seven_seg.sv | 10,379,745 | seven_seg.sv | sv | 60 | 51 | [] | [] | [] | [(1, 28), (30, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/10379745/hard/board_io/seven_seg.sv:17: Cannot find file containing module: 'ffd'\nffd #(32) value_fd(CLK, RESET, EN, VALUE, val_fd);\n^~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd.v\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd.sv\n ffd\n ffd.v\n ffd.sv\n obj_dir/ffd\n obj_dir/ffd.v\n obj_dir/ffd.sv\n%Error: Exiting due to 1 error(s)\n" | 1,021 | module | module seven_seg( input CLK,
input RESET,
input EN,
input [31:0] VALUE,
output [7:0] HEX_0,
output [7:0] HEX_1,
output [7:0] HEX_2,
output [7:0] HEX_3,
output [7:0] HEX_4,
output [7:0] HEX_5,
output [7:0] HEX_6,
output [7:0] HEX_7 );
logic [31:0] val_fd;
ffd #(32) value_fd(CLK, RESET, EN, VALUE, val_fd);
segment_logic sl0(val_fd[ 3:0 ], HEX_0);
segment_logic sl1(val_fd[ 7:4 ], HEX_1);
segment_logic sl2(val_fd[11:8 ], HEX_2);
segment_logic sl3(val_fd[15:12], HEX_3);
segment_logic sl4(val_fd[19:16], HEX_4);
segment_logic sl5(val_fd[23:20], HEX_5);
segment_logic sl6(val_fd[27:24], HEX_6);
segment_logic sl7(val_fd[31:28], HEX_7);
endmodule | module seven_seg( input CLK,
input RESET,
input EN,
input [31:0] VALUE,
output [7:0] HEX_0,
output [7:0] HEX_1,
output [7:0] HEX_2,
output [7:0] HEX_3,
output [7:0] HEX_4,
output [7:0] HEX_5,
output [7:0] HEX_6,
output [7:0] HEX_7 ); |
logic [31:0] val_fd;
ffd #(32) value_fd(CLK, RESET, EN, VALUE, val_fd);
segment_logic sl0(val_fd[ 3:0 ], HEX_0);
segment_logic sl1(val_fd[ 7:4 ], HEX_1);
segment_logic sl2(val_fd[11:8 ], HEX_2);
segment_logic sl3(val_fd[15:12], HEX_3);
segment_logic sl4(val_fd[19:16], HEX_4);
segment_logic sl5(val_fd[23:20], HEX_5);
segment_logic sl6(val_fd[27:24], HEX_6);
segment_logic sl7(val_fd[31:28], HEX_7);
endmodule | 5 |
3,278 | data/full_repos/permissive/10379745/hard/board_io/seven_seg.sv | 10,379,745 | seven_seg.sv | sv | 60 | 51 | [] | [] | [] | [(1, 28), (30, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/10379745/hard/board_io/seven_seg.sv:17: Cannot find file containing module: 'ffd'\nffd #(32) value_fd(CLK, RESET, EN, VALUE, val_fd);\n^~~\n ... Looked in:\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd.v\n data/full_repos/permissive/10379745/hard/board_io,data/full_repos/permissive/10379745/ffd.sv\n ffd\n ffd.v\n ffd.sv\n obj_dir/ffd\n obj_dir/ffd.v\n obj_dir/ffd.sv\n%Error: Exiting due to 1 error(s)\n" | 1,021 | module | module segment_logic( input [3:0] nibble,
output [7:0] seg );
logic [6:0] s;
always_comb
case(nibble)
4'h0: s = ~7'b1111110;
4'h1: s = ~7'b0110000;
4'h2: s = ~7'b1101101;
4'h3: s = ~7'b1111001;
4'h4: s = ~7'b0110011;
4'h5: s = ~7'b1011011;
4'h6: s = ~7'b1011111;
4'h7: s = ~7'b1110000;
4'h8: s = ~7'b1111111;
4'h9: s = ~7'b1111011;
4'hA: s = ~7'b1110111;
4'hB: s = ~7'b0011111;
4'hC: s = ~7'b1001110;
4'hD: s = ~7'b0111101;
4'hE: s = ~7'b1001111;
4'hF: s = ~7'b1000111;
default: s = ~7'b1111110;
endcase
assign seg = {1'b1, s};
endmodule | module segment_logic( input [3:0] nibble,
output [7:0] seg ); |
logic [6:0] s;
always_comb
case(nibble)
4'h0: s = ~7'b1111110;
4'h1: s = ~7'b0110000;
4'h2: s = ~7'b1101101;
4'h3: s = ~7'b1111001;
4'h4: s = ~7'b0110011;
4'h5: s = ~7'b1011011;
4'h6: s = ~7'b1011111;
4'h7: s = ~7'b1110000;
4'h8: s = ~7'b1111111;
4'h9: s = ~7'b1111011;
4'hA: s = ~7'b1110111;
4'hB: s = ~7'b0011111;
4'hC: s = ~7'b1001110;
4'hD: s = ~7'b0111101;
4'hE: s = ~7'b1001111;
4'hF: s = ~7'b1000111;
default: s = ~7'b1111110;
endcase
assign seg = {1'b1, s};
endmodule | 5 |
3,279 | data/full_repos/permissive/10379745/hw_de0/hard/io_space.sv | 10,379,745 | io_space.sv | sv | 59 | 107 | [] | [] | [] | null | line:11: before: "." | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/10379745/hw_de0/hard/io_space.sv:11: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'io_space\'\nmodule io_space #( parameter RAM_DEPTH = 14 )\n ^~~~~~~~\n : ... Top module \'if_io\'\n if_io.io IO ); \n ^~~~~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/io_space.sv:11: Unsupported: Interfaced port on top level module\n if_io.io IO ); \n ^~\n%Error: data/full_repos/permissive/10379745/hw_de0/hard/io_space.sv:11: Cannot find file containing interface: \'if_io\'\n if_io.io IO ); \n ^~~~~\n%Error: Internal Error: data/full_repos/permissive/10379745/hw_de0/hard/io_space.sv:11: ../V3LinkDot.cpp:2055: Unlinked interface\n if_io.io IO ); \n ^~~~~\n' | 1,031 | module | module io_space #( parameter RAM_DEPTH = 14 )
( input CLK,
input RESET,
input DBE,
input IO_REQ,
input IO_WE,
input IO_RE,
input [RAM_DEPTH-1:0] IO_ADDR,
input [31:0] IO_WD,
output [31:0] IO_RD,
if_io.io IO );
logic [RAM_DEPTH-1:0] addr_q;
logic [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select, uart_select, qcon_select, hp_select;
ffd #(4) ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32) data_fd(CLK, RESET, 1'b1, IO_WD, wd_q);
assign req_valid = ioreq_q & ~dbe_q;
assign leds_select = (addr_q[7:4] == 4'd0);
assign uart_select = (addr_q[7:4] == 4'd1);
assign qcon_select = (addr_q[7:4] == 4'd3);
assign hp_select = (addr_q[7:4] == 4'd4);
assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q[7:0];
assign IO.LEDS_A = addr_q[3:0];
assign IO.UART_WE = uart_select & iowe_q & req_valid;
assign IO.UART_RE = uart_select & iore_q & req_valid;
assign IO.UART_WD = wd_q;
assign IO.UART_A = addr_q[2:0];
assign IO.I2C_A = addr_q[3:0];
assign IO.QCON_WE = qcon_select & iowe_q & req_valid;
assign IO.QCON_WD = wd_q;
assign IO.QCON_A = addr_q[3:0];
assign IO.HP_WE = hp_select & iowe_q & req_valid;
assign IO.HP_WD = wd_q;
assign IO.HP_A = addr_q[3:0];
mux8 #(32) read_mux( addr_q[6:4],
IO.LEDS_RD,
IO.UART_RD,
IO.I2C_RD,
IO.QCON_RD,
IO.HP_RD,
32'd0,
32'd0,
32'd0,
IO_RD );
endmodule | module io_space #( parameter RAM_DEPTH = 14 )
( input CLK,
input RESET,
input DBE,
input IO_REQ,
input IO_WE,
input IO_RE,
input [RAM_DEPTH-1:0] IO_ADDR,
input [31:0] IO_WD,
output [31:0] IO_RD,
if_io.io IO ); |
logic [RAM_DEPTH-1:0] addr_q;
logic [31:0] wd_q;
logic ioreq_q, dbe_q, iowe_q, iore_q, req_valid;
logic leds_select, uart_select, qcon_select, hp_select;
ffd #(4) ctrl_fd(CLK, RESET, 1'b1, {IO_REQ, DBE, IO_WE, IO_RE}, {ioreq_q, dbe_q, iowe_q, iore_q});
ffd #(RAM_DEPTH) addr_fd(CLK, RESET, 1'b1, IO_ADDR, addr_q);
ffd #(32) data_fd(CLK, RESET, 1'b1, IO_WD, wd_q);
assign req_valid = ioreq_q & ~dbe_q;
assign leds_select = (addr_q[7:4] == 4'd0);
assign uart_select = (addr_q[7:4] == 4'd1);
assign qcon_select = (addr_q[7:4] == 4'd3);
assign hp_select = (addr_q[7:4] == 4'd4);
assign IO.LEDS_WE = leds_select & iowe_q & req_valid;
assign IO.LEDS_WD = wd_q[7:0];
assign IO.LEDS_A = addr_q[3:0];
assign IO.UART_WE = uart_select & iowe_q & req_valid;
assign IO.UART_RE = uart_select & iore_q & req_valid;
assign IO.UART_WD = wd_q;
assign IO.UART_A = addr_q[2:0];
assign IO.I2C_A = addr_q[3:0];
assign IO.QCON_WE = qcon_select & iowe_q & req_valid;
assign IO.QCON_WD = wd_q;
assign IO.QCON_A = addr_q[3:0];
assign IO.HP_WE = hp_select & iowe_q & req_valid;
assign IO.HP_WD = wd_q;
assign IO.HP_A = addr_q[3:0];
mux8 #(32) read_mux( addr_q[6:4],
IO.LEDS_RD,
IO.UART_RD,
IO.I2C_RD,
IO.QCON_RD,
IO.HP_RD,
32'd0,
32'd0,
32'd0,
IO_RD );
endmodule | 5 |
3,280 | data/full_repos/permissive/10379745/hw_de0/hard/mcpu.sv | 10,379,745 | mcpu.sv | sv | 65 | 83 | [] | [] | [] | null | line:3: before: "IO" | null | 1: b"%Error: data/full_repos/permissive/10379745/hw_de0/hard/mcpu.sv:11: syntax error, unexpected ::, expecting IDENTIFIER\ndef::c_inst INST_INFO; \n ^~\n : ... Perhaps 'def' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Exiting due to 1 error(s)\n" | 1,033 | module | module mcpu( input CLK,
input RESET,
if_io IO);
parameter RAM_DEPTH = 13;
logic jtag_reset, any_reset;
assign any_reset = jtag_reset | RESET;
def::c_inst INST_INFO;
def::ctrl CTRL_INFO;
if_hazard if_hazard();
if_except if_except();
if_cp0 if_cp0();
if_memory if_memory();
if_debug if_debug();
controller the_controller ( INST_INFO, CTRL_INFO );
hazard_unit the_hazard_unit( if_hazard );
datapath the_datapath ( .CLK ( CLK ),
.INST_O ( INST_INFO ),
.CI ( CTRL_INFO ),
.HZRD ( if_hazard ),
.CP0 ( if_cp0 ),
.EXC ( if_except ),
.MEM ( if_memory ),
.DEBUG ( if_debug ));
coprocessor0 #(RAM_DEPTH) cp0 ( .CLK ( CLK ),
.RESET ( any_reset ),
.CP0 ( if_cp0 ),
.EXC ( if_except ),
.IO ( IO ),
.DEBUG ( if_debug ));
exceptions excp_unit( .CLK ( CLK ),
.RESET ( any_reset ),
.EXC ( if_except ),
.DEBUG ( if_debug ));
phy_mem #(RAM_DEPTH) phy_mem(CLK, any_reset, if_memory, IO);
jtag jtag(CLK, RESET, jtag_reset, if_debug );
endmodule | module mcpu( input CLK,
input RESET,
if_io IO); |
parameter RAM_DEPTH = 13;
logic jtag_reset, any_reset;
assign any_reset = jtag_reset | RESET;
def::c_inst INST_INFO;
def::ctrl CTRL_INFO;
if_hazard if_hazard();
if_except if_except();
if_cp0 if_cp0();
if_memory if_memory();
if_debug if_debug();
controller the_controller ( INST_INFO, CTRL_INFO );
hazard_unit the_hazard_unit( if_hazard );
datapath the_datapath ( .CLK ( CLK ),
.INST_O ( INST_INFO ),
.CI ( CTRL_INFO ),
.HZRD ( if_hazard ),
.CP0 ( if_cp0 ),
.EXC ( if_except ),
.MEM ( if_memory ),
.DEBUG ( if_debug ));
coprocessor0 #(RAM_DEPTH) cp0 ( .CLK ( CLK ),
.RESET ( any_reset ),
.CP0 ( if_cp0 ),
.EXC ( if_except ),
.IO ( IO ),
.DEBUG ( if_debug ));
exceptions excp_unit( .CLK ( CLK ),
.RESET ( any_reset ),
.EXC ( if_except ),
.DEBUG ( if_debug ));
phy_mem #(RAM_DEPTH) phy_mem(CLK, any_reset, if_memory, IO);
jtag jtag(CLK, RESET, jtag_reset, if_debug );
endmodule | 5 |
3,284 | data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv | 10,379,745 | hp_display.sv | sv | 94 | 69 | [] | [] | [] | null | line:58 column:26: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv:74: Cannot find include file: log2.inc\n`include "log2.inc" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.v\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.sv\n log2.inc\n log2.inc.v\n log2.inc.sv\n obj_dir/log2.inc\n obj_dir/log2.inc.v\n obj_dir/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 1,042 | module | module hp_display ( input CLK,
input RESET,
input WE,
input [3:0] A,
input [31:0] WD,
output [31:0] RD,
output HP_CE,
output HP_RS,
output HP_RESET,
output HP_BLANK,
output HP_DO,
output HP_CLK );
logic [4:0] bits_q;
logic shift, shifting, done, dot_sel, ctrl_sel;
assign dot_sel = (A == 4'd0);
assign ctrl_sel = (A == 4'd1);
ffd #(5) bits_fd(CLK, RESET, WE & ctrl_sel, WD[4:0], bits_q);
rsd en_reg(CLK, RESET | (shift & done), WE & (A == 4'd0), shifting);
so_reg_left #(8) sreg( .CLK ( CLK ),
.UPDATE ( WE & dot_sel ),
.SHIFT ( shift ),
.DATA ( WD[7:0] ),
.OUT ( HP_DO ),
.EMPTY ( done ) );
hp_clk_div hp_clk_div( .CLK ( CLK ),
.RESET ( WE & dot_sel ),
.EN ( shifting ),
.SHIFT ( shift ),
.HP_CLK ( HP_CLK ) );
assign HP_RESET = ~bits_q[4];
assign HP_BLANK = bits_q[2];
assign HP_RS = bits_q[1];
assign HP_CE = ~bits_q[0];
assign RD = {31'd0, shifting};
endmodule | module hp_display ( input CLK,
input RESET,
input WE,
input [3:0] A,
input [31:0] WD,
output [31:0] RD,
output HP_CE,
output HP_RS,
output HP_RESET,
output HP_BLANK,
output HP_DO,
output HP_CLK ); |
logic [4:0] bits_q;
logic shift, shifting, done, dot_sel, ctrl_sel;
assign dot_sel = (A == 4'd0);
assign ctrl_sel = (A == 4'd1);
ffd #(5) bits_fd(CLK, RESET, WE & ctrl_sel, WD[4:0], bits_q);
rsd en_reg(CLK, RESET | (shift & done), WE & (A == 4'd0), shifting);
so_reg_left #(8) sreg( .CLK ( CLK ),
.UPDATE ( WE & dot_sel ),
.SHIFT ( shift ),
.DATA ( WD[7:0] ),
.OUT ( HP_DO ),
.EMPTY ( done ) );
hp_clk_div hp_clk_div( .CLK ( CLK ),
.RESET ( WE & dot_sel ),
.EN ( shifting ),
.SHIFT ( shift ),
.HP_CLK ( HP_CLK ) );
assign HP_RESET = ~bits_q[4];
assign HP_BLANK = bits_q[2];
assign HP_RS = bits_q[1];
assign HP_CE = ~bits_q[0];
assign RD = {31'd0, shifting};
endmodule | 5 |
3,285 | data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv | 10,379,745 | hp_display.sv | sv | 94 | 69 | [] | [] | [] | null | line:58 column:26: Illegal character "'" | null | 1: b'%Error: data/full_repos/permissive/10379745/hw_de0/hard/hp_display/hp_display.sv:74: Cannot find include file: log2.inc\n`include "log2.inc" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.v\n data/full_repos/permissive/10379745/hw_de0/hard/hp_display,data/full_repos/permissive/10379745/log2.inc.sv\n log2.inc\n log2.inc.v\n log2.inc.sv\n obj_dir/log2.inc\n obj_dir/log2.inc.v\n obj_dir/log2.inc.sv\n%Error: Exiting due to 1 error(s)\n' | 1,042 | module | module hp_clk_div( input CLK,
input RESET,
input EN,
output SHIFT,
output HP_CLK );
logic [5:0] clk_div;
always_ff@(posedge CLK)
if(RESET) clk_div <= '0;
else clk_div <= clk_div + EN;
assign HP_CLK = clk_div[5];
assign SHIFT = (clk_div == '1);
endmodule | module hp_clk_div( input CLK,
input RESET,
input EN,
output SHIFT,
output HP_CLK ); |
logic [5:0] clk_div;
always_ff@(posedge CLK)
if(RESET) clk_div <= '0;
else clk_div <= clk_div + EN;
assign HP_CLK = clk_div[5];
assign SHIFT = (clk_div == '1);
endmodule | 5 |
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