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2,611 | data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v | 100,331,186 | testffD.v | v | 179 | 82 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:26: Cannot find include file: modulos/ffD.v\n`include "modulos/ffD.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/ffD.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/ffD.v.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/ffD.v.sv\n modulos/ffD.v\n modulos/ffD.v.v\n modulos/ffD.v.sv\n obj_dir/modulos/ffD.v\n obj_dir/modulos/ffD.v.v\n obj_dir/modulos/ffD.v.sv\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:59: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/testFfD.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testFfD);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:103: Unsupported or unknown PLI call: $monitor\n $monitor("%t | %b | %b | %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:114: Unsupported: Ignoring delay on this delayed statement.\n # 0 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:116: Unsupported: Ignoring delay on this delayed statement.\n # 1000 d = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:117: Unsupported: Ignoring delay on this delayed statement.\n # 0 notpreset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:118: Unsupported: Ignoring delay on this delayed statement.\n # 0 notclear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:119: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:120: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:122: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:123: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:124: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:126: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:127: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:128: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:131: Unsupported: Ignoring delay on this delayed statement.\n # 1000 d = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:132: Unsupported: Ignoring delay on this delayed statement.\n # 0 notpreset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:133: Unsupported: Ignoring delay on this delayed statement.\n # 0 notclear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:134: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:135: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:137: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:138: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:139: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:141: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:142: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:143: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:146: Unsupported: Ignoring delay on this delayed statement.\n # 1000 d = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:147: Unsupported: Ignoring delay on this delayed statement.\n # 0 notpreset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:148: Unsupported: Ignoring delay on this delayed statement.\n # 0 notclear = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:149: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:150: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:152: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:153: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:154: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:156: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:157: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:158: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:161: Unsupported: Ignoring delay on this delayed statement.\n # 1000 d = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:162: Unsupported: Ignoring delay on this delayed statement.\n # 0 notpreset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:163: Unsupported: Ignoring delay on this delayed statement.\n # 0 notclear = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:164: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:165: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:167: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:168: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:169: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:171: Unsupported: Ignoring delay on this delayed statement.\n # 1000 clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:172: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:173: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testffD.v:175: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n%Error: Exiting due to 4 error(s), 46 warning(s)\n' | 43 | module | module testFfD;
initial begin
$display ("testFfD");
$dumpfile("tests/testFfD.vcd");
$dumpvars(0, testFfD);
end
reg d, clk, notpreset, notclear;
wire q, notq;
realtime inicio, retardo;
ffD ffD1 (
.d(d),
.clk(clk),
.notpreset(notpreset),
.notclear(notclear),
.q(q),
.notq(notq)
);
always @ (q) begin
retardo = $realtime-inicio;
end
initial begin
$monitor("%t | %b | %b | %b | %b | %b | %b | %f ns",
$time, d, clk, notpreset, notclear, q, notq, retardo);
$display("------------------------------------------");
$display("Test para el Flip Flop");
$display("---------------------+---+-----+------+------+----+----+--------");
$display(" Tiempo | d | clk | ~pre | ~clr | q | ~q | Retardo");
$display("---------------------+---+-----+------+------+----+----+--------");
# 0 clk = 0;
# 1000 d = 0;
# 0 notpreset = 1;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1;
# 0 notpreset = 1;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1'bx;
# 0 notpreset = 0;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1'bx;
# 0 notpreset = 1;
# 0 notclear = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 $finish;
end
endmodule | module testFfD; |
initial begin
$display ("testFfD");
$dumpfile("tests/testFfD.vcd");
$dumpvars(0, testFfD);
end
reg d, clk, notpreset, notclear;
wire q, notq;
realtime inicio, retardo;
ffD ffD1 (
.d(d),
.clk(clk),
.notpreset(notpreset),
.notclear(notclear),
.q(q),
.notq(notq)
);
always @ (q) begin
retardo = $realtime-inicio;
end
initial begin
$monitor("%t | %b | %b | %b | %b | %b | %b | %f ns",
$time, d, clk, notpreset, notclear, q, notq, retardo);
$display("------------------------------------------");
$display("Test para el Flip Flop");
$display("---------------------+---+-----+------+------+----+----+--------");
$display(" Tiempo | d | clk | ~pre | ~clr | q | ~q | Retardo");
$display("---------------------+---+-----+------+------+----+----+--------");
# 0 clk = 0;
# 1000 d = 0;
# 0 notpreset = 1;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1;
# 0 notpreset = 1;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1'bx;
# 0 notpreset = 0;
# 0 notclear = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 d = 1'bx;
# 0 notpreset = 1;
# 0 notclear = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 clk = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 $finish;
end
endmodule | 0 |
2,612 | data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v | 100,331,186 | testMux.v | v | 88 | 98 | [] | [] | [] | null | line:244: before: "/" | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:23: Cannot find include file: modulos/mux.v\n`include "modulos/mux.v" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/mux.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/mux.v.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/mux.v.sv\n modulos/mux.v\n modulos/mux.v.v\n modulos/mux.v.sv\n obj_dir/modulos/mux.v\n obj_dir/modulos/mux.v.v\n obj_dir/modulos/mux.v.sv\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/testMux.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testMux);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:40: Unsupported or unknown PLI call: $monitor\n $monitor("%t | %b | %b | %b | %b | %b | %f ns", $time, s, a[0], a[1], notoe, y, retardo);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:49: Unsupported: Ignoring delay on this delayed statement.\n # 1000 s = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:50: Unsupported: Ignoring delay on this delayed statement.\n # 0 a = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:51: Unsupported: Ignoring delay on this delayed statement.\n # 0 notoe = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:52: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:53: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 1000 s = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 0 a = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:57: Unsupported: Ignoring delay on this delayed statement.\n # 0 notoe = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:58: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:59: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:61: Unsupported: Ignoring delay on this delayed statement.\n # 1000 s = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:62: Unsupported: Ignoring delay on this delayed statement.\n # 0 a = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:63: Unsupported: Ignoring delay on this delayed statement.\n # 0 notoe = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:64: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:65: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:67: Unsupported: Ignoring delay on this delayed statement.\n # 1000 s = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:68: Unsupported: Ignoring delay on this delayed statement.\n # 0 a = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:69: Unsupported: Ignoring delay on this delayed statement.\n # 0 notoe = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:70: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:71: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:73: Unsupported: Ignoring delay on this delayed statement.\n # 1000 s = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:74: Unsupported: Ignoring delay on this delayed statement.\n # 0 a = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:75: Unsupported: Ignoring delay on this delayed statement.\n # 0 notoe = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:76: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:77: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testMux.v:79: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n%Error: Exiting due to 4 error(s), 26 warning(s)\n' | 44 | module | module testMux;
initial begin
$display ("testMux");
$dumpfile("tests/testMux.vcd");
$dumpvars(0, testMux);
end
reg s, notoe;
reg [1:0] a;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %b | %b | %b | %f ns", $time, s, a[0], a[1], notoe, y, retardo);
$display("------------------------------------------");
$display("Test para el MUX");
$display("---------------------+----+----+---+-----+---+--------");
$display(" Tiempo | a1 | a2 | s | ~oe | y | Retardo");
$display("---------------------+----+----+---+-----+---+--------");
# 1000 s = 0;
# 0 a = 2'b10;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 1;
# 0 a = 2'b10;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 1;
# 0 a = 2'b01;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 0;
# 0 a = 2'b01;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 0;
# 0 a = 2'b01;
# 0 notoe = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
mux mux1 (.s(s), .a(a), .notoe(notoe), .y(y));
endmodule | module testMux; |
initial begin
$display ("testMux");
$dumpfile("tests/testMux.vcd");
$dumpvars(0, testMux);
end
reg s, notoe;
reg [1:0] a;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %b | %b | %b | %f ns", $time, s, a[0], a[1], notoe, y, retardo);
$display("------------------------------------------");
$display("Test para el MUX");
$display("---------------------+----+----+---+-----+---+--------");
$display(" Tiempo | a1 | a2 | s | ~oe | y | Retardo");
$display("---------------------+----+----+---+-----+---+--------");
# 1000 s = 0;
# 0 a = 2'b10;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 1;
# 0 a = 2'b10;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 1;
# 0 a = 2'b01;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 0;
# 0 a = 2'b01;
# 0 notoe = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 s = 0;
# 0 a = 2'b01;
# 0 notoe = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
mux mux1 (.s(s), .a(a), .notoe(notoe), .y(y));
endmodule | 0 |
2,613 | data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v | 100,331,186 | testNorGate.v | v | 107 | 81 | [] | [] | [] | [(8, 64)] | null | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:23: Cannot find include file: modulos/norGate.v\n`include "modulos/norGate.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/norGate.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/norGate.v.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/norGate.v.sv\n modulos/norGate.v\n modulos/norGate.v.v\n modulos/norGate.v.sv\n obj_dir/modulos/norGate.v\n obj_dir/modulos/norGate.v.v\n obj_dir/modulos/norGate.v.sv\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:29: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/testNorGate.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:30: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testNorGate);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:40: Unsupported or unknown PLI call: $monitor\n $monitor("%t | %b | %b | %b | %f ns", $time, a, b, y, retardo);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:50: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:51: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:52: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:53: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:57: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:58: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:59: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:62: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:63: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:64: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:65: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:68: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:69: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:70: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:71: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:74: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:75: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:76: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:77: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:80: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:81: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:82: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:83: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:86: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:87: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:88: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:89: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:92: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:93: Unsupported: Ignoring delay on this delayed statement.\n # 0 b = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:94: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:95: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNorGate.v:98: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n%Error: Exiting due to 4 error(s), 33 warning(s)\n' | 46 | module | module testNorGate;
initial begin
$display ("testNorGate");
$dumpfile("tests/testNorGate.vcd");
$dumpvars(0, testNorGate);
end
reg a, b;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %b | %f ns", $time, a, b, y, retardo);
$display("------------------------------------------");
$display("Test para la compuerta NOR");
$display("---------------------+---+---+---+--------");
$display(" Tiempo | a | b | y | Retardo");
$display("---------------------+---+---+---+--------");
$display("x nor x = x");
# 1000 a = 0;
# 0 b = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor x = x");
# 1000 a = 1'bx;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("x nor 0 = x");
# 1000 a = 1;
# 0 b = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor x = 0");
# 1000 a = 1'bx;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("x nor 1 = 0");
# 1000 a = 0;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor 0 = 1");
# 1000 a = 1;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor 0 = 0");
# 1000 a = 0;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor 1 = 0");
# 1000 a = 1;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor 1 = 0");
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
norGate norGate1 (.a(a), .b(b), .y(y));
endmodule | module testNorGate; |
initial begin
$display ("testNorGate");
$dumpfile("tests/testNorGate.vcd");
$dumpvars(0, testNorGate);
end
reg a, b;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %b | %f ns", $time, a, b, y, retardo);
$display("------------------------------------------");
$display("Test para la compuerta NOR");
$display("---------------------+---+---+---+--------");
$display(" Tiempo | a | b | y | Retardo");
$display("---------------------+---+---+---+--------");
$display("x nor x = x");
# 1000 a = 0;
# 0 b = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor x = x");
# 1000 a = 1'bx;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("x nor 0 = x");
# 1000 a = 1;
# 0 b = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor x = 0");
# 1000 a = 1'bx;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("x nor 1 = 0");
# 1000 a = 0;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor 0 = 1");
# 1000 a = 1;
# 0 b = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor 0 = 0");
# 1000 a = 0;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("0 nor 1 = 0");
# 1000 a = 1;
# 0 b = 1;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("1 nor 1 = 0");
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
norGate norGate1 (.a(a), .b(b), .y(y));
endmodule | 0 |
2,614 | data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v | 100,331,186 | testNotGate.v | v | 68 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:23: Cannot find include file: modulos/notGate.v\n`include "modulos/notGate.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/notGate.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/notGate.v.v\n data/full_repos/permissive/100331186/tarea3/pruebas,data/full_repos/permissive/100331186/modulos/notGate.v.sv\n modulos/notGate.v\n modulos/notGate.v.v\n modulos/notGate.v.sv\n obj_dir/modulos/notGate.v\n obj_dir/modulos/notGate.v.v\n obj_dir/modulos/notGate.v.sv\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:28: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/testNotGate.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:29: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, testNotGate);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:39: Unsupported or unknown PLI call: $monitor\n $monitor("%t | %b | %b | %f ns", $time, a, y, retardo);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:49: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:50: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:51: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:54: Unsupported: Ignoring delay on this delayed statement.\n # 1000 a = 1\'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:55: Unsupported: Ignoring delay on this delayed statement.\n # 0 retardo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 0 inicio = $realtime;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea3/pruebas/testNotGate.v:59: Unsupported: Ignoring delay on this delayed statement.\n # 1000 $finish;\n ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n' | 47 | module | module testNotGate;
initial begin
$display ("testNotGate");
$dumpfile("tests/testNotGate.vcd");
$dumpvars(0, testNotGate);
end
reg a;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %f ns", $time, a, y, retardo);
$display("--------------------------------------");
$display("Test para el Inversor");
$display("---------------------+---+---+--------");
$display(" Tiempo | a | y | Retardo");
$display("---------------------+---+---+--------");
$display("not x = x");
# 1000 a = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("not 0 = 1");
# 1000 a = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("not 1 = 0");
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
notGate notGate1 (.a(a), .y(y));
endmodule | module testNotGate; |
initial begin
$display ("testNotGate");
$dumpfile("tests/testNotGate.vcd");
$dumpvars(0, testNotGate);
end
reg a;
wire y;
realtime inicio, retardo;
initial begin
inicio = $realtime;
$monitor("%t | %b | %b | %f ns", $time, a, y, retardo);
$display("--------------------------------------");
$display("Test para el Inversor");
$display("---------------------+---+---+--------");
$display(" Tiempo | a | y | Retardo");
$display("---------------------+---+---+--------");
$display("not x = x");
# 1000 a = 0;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("not 0 = 1");
# 1000 a = 1'bx;
# 0 retardo = 0;
# 0 inicio = $realtime;
$display("not 1 = 0");
# 1000 $finish;
end
always @ (y) begin
retardo = $realtime-inicio;
end
notGate notGate1 (.a(a), .y(y));
endmodule | 0 |
2,615 | data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v | 100,331,186 | bitHolder.v | v | 85 | 98 | [] | [] | [] | [(4, 84)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 's_der'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:5: ... Location of original declaration\n input s_der, \n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 's_izq'\n wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:16: ... Location of original declaration\n input s_izq, \n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'd_n'\n wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n ^~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:26: ... Location of original declaration\n input d_n, \n ^~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'dir'\n wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n ^~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:29: ... Location of original declaration\n input dir, \n ^~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:44: Duplicate declaration of signal: 'clkenb'\n wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;\n ^~~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:38: ... Location of original declaration\n input clkenb, \n ^~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:45: Duplicate declaration of signal: 'modo'\n wire [1:0] modo;\n ^~~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:31: ... Location of original declaration\n input [1:0] modo, \n ^~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:47: Duplicate declaration of signal: 's_out'\n wire s_out;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/bitHolder.v:41: ... Location of original declaration\n output s_out \n ^~~~~\n%Error: Exiting due to 7 error(s)\n" | 48 | module | module bitHolder (
input s_der,
input s_izq,
input d_n,
input dir,
input [1:0] modo,
input clkenb,
output s_out
);
wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;
wire [1:0] modo;
wire s_out;
parameter notoe = 1'b0;
wire d_in;
wire nand1Y;
ternarioDoble d_n_prima(
.a(s_der),
.b(s_izq),
.c(d_n),
.s1(dir),
.s2(modo[1]),
.y(d_in)
);
parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;
notGate ng1(.a(clkenb), .y(clkenb_not));
notGate ng2(.a(clkenb_not), .y(clkenb_ret));
ffD bitValue(
.d(d_in),
.clk(clkenb_ret),
.notpreset(notpreset),
.notclear(notclear),
.q(s_out),
.notq(notq)
);
endmodule | module bitHolder (
input s_der,
input s_izq,
input d_n,
input dir,
input [1:0] modo,
input clkenb,
output s_out
); |
wire s_der, s_izq, d_n, dir, clkenb, clkenb_not, clkenb_ret;
wire [1:0] modo;
wire s_out;
parameter notoe = 1'b0;
wire d_in;
wire nand1Y;
ternarioDoble d_n_prima(
.a(s_der),
.b(s_izq),
.c(d_n),
.s1(dir),
.s2(modo[1]),
.y(d_in)
);
parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;
notGate ng1(.a(clkenb), .y(clkenb_not));
notGate ng2(.a(clkenb_not), .y(clkenb_ret));
ffD bitValue(
.d(d_in),
.clk(clkenb_ret),
.notpreset(notpreset),
.notclear(notclear),
.q(s_out),
.notq(notq)
);
endmodule | 0 |
2,616 | data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v | 100,331,186 | registro4bits.v | v | 124 | 108 | [] | [] | [] | [(6, 123)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v:25: Duplicate declaration of signal: 's_out'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire clkenb,s_out;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/registro4bits.v:21: ... Location of original declaration\n output s_out \n ^~~~~\n%Error: Exiting due to 1 error(s)\n" | 50 | module | module registro4bits (
input clk,
input enb,
input dir,
input s_in,
input [1:0] modo,
input [3:0] d,
output [3:0] q,
output s_out
);
parameter bits = 4;
wire socMSBout, socLSBout;
wire clkenb,s_out;
serialOcontiguo socMSB(
.usual(q[0]),
.s_in(s_in),
.modo(modo),
.out(socMSBout)
);
serialOcontiguo socLSB(
.usual(q[3]),
.s_in(s_in),
.modo(modo),
.out(socLSBout)
);
enabler enabler1(
.clk(clk),
.enb(enb),
.eclk(clkenb)
);
bitHolder bitHolder0(
.s_der(socLSBout),
.s_izq(q[1]),
.d_n(d[0]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[0])
);
bitHolder bitHolder1(
.s_der(q[0]),
.s_izq(q[2]),
.d_n(d[1]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[1])
);
bitHolder bitHolder2(
.s_der(q[1]),
.s_izq(q[3]),
.d_n(d[2]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[2])
);
bitHolder bitHolder3(
.s_der(q[2]),
.s_izq(socMSBout),
.d_n(d[3]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[3])
);
wire [1:0] not_modo;
wire is_modo_00;
notGate notModo0(.a(modo[0]), .y(not_modo[0]));
notGate notModo1(.a(modo[1]), .y(not_modo[1]));
enabler modoCheck(.clk(not_modo[0]), .enb(not_modo[1]), .eclk(is_modo_00));
salidaSerial salida(
.modo(modo),
.s_der(q[0]),
.s_izq(q[3]),
.dir(dir),
.s_out(s_out)
);
parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;
wire s_out_ff;
ffD s_out_reg(
.d(s_out),
.clk(clkenb),
.notpreset(notpreset),
.notclear(notclear),
.q(s_out_ff),
.notq(notq)
);
endmodule | module registro4bits (
input clk,
input enb,
input dir,
input s_in,
input [1:0] modo,
input [3:0] d,
output [3:0] q,
output s_out
); |
parameter bits = 4;
wire socMSBout, socLSBout;
wire clkenb,s_out;
serialOcontiguo socMSB(
.usual(q[0]),
.s_in(s_in),
.modo(modo),
.out(socMSBout)
);
serialOcontiguo socLSB(
.usual(q[3]),
.s_in(s_in),
.modo(modo),
.out(socLSBout)
);
enabler enabler1(
.clk(clk),
.enb(enb),
.eclk(clkenb)
);
bitHolder bitHolder0(
.s_der(socLSBout),
.s_izq(q[1]),
.d_n(d[0]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[0])
);
bitHolder bitHolder1(
.s_der(q[0]),
.s_izq(q[2]),
.d_n(d[1]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[1])
);
bitHolder bitHolder2(
.s_der(q[1]),
.s_izq(q[3]),
.d_n(d[2]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[2])
);
bitHolder bitHolder3(
.s_der(q[2]),
.s_izq(socMSBout),
.d_n(d[3]),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(q[3])
);
wire [1:0] not_modo;
wire is_modo_00;
notGate notModo0(.a(modo[0]), .y(not_modo[0]));
notGate notModo1(.a(modo[1]), .y(not_modo[1]));
enabler modoCheck(.clk(not_modo[0]), .enb(not_modo[1]), .eclk(is_modo_00));
salidaSerial salida(
.modo(modo),
.s_der(q[0]),
.s_izq(q[3]),
.dir(dir),
.s_out(s_out)
);
parameter notpreset = 1'b1;
parameter notclear = 1'b1;
wire notq;
wire s_out_ff;
ffD s_out_reg(
.d(s_out),
.clk(clkenb),
.notpreset(notpreset),
.notclear(notclear),
.q(s_out_ff),
.notq(notq)
);
endmodule | 0 |
2,617 | data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v | 100,331,186 | salidaSerial.v | v | 38 | 48 | [] | [] | [] | [(1, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:11: Duplicate declaration of signal: 'modo'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire [1:0] modo;\n ^~~~\n data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:2: ... Location of original declaration\n input [1:0] modo,\n ^~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:12: Duplicate declaration of signal: 's_der'\n wire s_der, s_izq, s_out, dir;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:3: ... Location of original declaration\n input s_der,\n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:12: Duplicate declaration of signal: 's_izq'\n wire s_der, s_izq, s_out, dir;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:4: ... Location of original declaration\n input s_izq,\n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:12: Duplicate declaration of signal: 's_out'\n wire s_der, s_izq, s_out, dir;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:6: ... Location of original declaration\n output s_out\n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:12: Duplicate declaration of signal: 'dir'\n wire s_der, s_izq, s_out, dir;\n ^~~\n data/full_repos/permissive/100331186/tarea4/modulos/salidaSerial.v:5: ... Location of original declaration\n input dir,\n ^~~\n%Error: Exiting due to 5 error(s)\n" | 51 | module | module salidaSerial (
input [1:0] modo,
input s_der,
input s_izq,
input dir,
output s_out
);
wire [1:0] modo;
wire s_der, s_izq, s_out, dir;
wire outMux;
wire [1:0] canalesMux;
assign canalesMux[0] = s_izq;
assign canalesMux[1] = s_der;
parameter notoe = 1'b0;
mux derOizq(
.s(dir),
.a(canalesMux),
.notoe(notoe),
.y(outMux)
);
serialOcontiguo salida(
.usual(1'b0),
.s_in(outMux),
.modo(modo),
.out(s_out)
);
endmodule | module salidaSerial (
input [1:0] modo,
input s_der,
input s_izq,
input dir,
output s_out
); |
wire [1:0] modo;
wire s_der, s_izq, s_out, dir;
wire outMux;
wire [1:0] canalesMux;
assign canalesMux[0] = s_izq;
assign canalesMux[1] = s_der;
parameter notoe = 1'b0;
mux derOizq(
.s(dir),
.a(canalesMux),
.notoe(notoe),
.y(outMux)
);
serialOcontiguo salida(
.usual(1'b0),
.s_in(outMux),
.modo(modo),
.out(s_out)
);
endmodule | 0 |
2,618 | data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v | 100,331,186 | serialOcontiguo.v | v | 39 | 32 | [] | [] | [] | [(5, 38)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:12: Duplicate declaration of signal: 'usual'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire usual, s_in, out;\n ^~~~~\n data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:6: ... Location of original declaration\n input usual,\n ^~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:12: Duplicate declaration of signal: 's_in'\n wire usual, s_in, out;\n ^~~~\n data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:7: ... Location of original declaration\n input s_in,\n ^~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:12: Duplicate declaration of signal: 'out'\n wire usual, s_in, out;\n ^~~\n data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:9: ... Location of original declaration\n output out\n ^~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:13: Duplicate declaration of signal: 'modo'\n wire [1:0] modo;\n ^~~~\n data/full_repos/permissive/100331186/tarea4/modulos/serialOcontiguo.v:8: ... Location of original declaration\n input [1:0] modo,\n ^~~~\n%Error: Exiting due to 4 error(s)\n" | 52 | module | module serialOcontiguo(
input usual,
input s_in,
input [1:0] modo,
output out
);
wire usual, s_in, out;
wire [1:0] modo;
wire outNor;
wire outMux;
wire [1:0] canalesMux;
assign canalesMux[1] = s_in;
assign canalesMux[0] = usual;
parameter notoe = 1'b0;
norGate modeNor(
.a(modo[1]),
.b(modo[0]),
.y(outNor)
);
mux selector(
.s(outNor),
.a(canalesMux),
.notoe(notoe),
.y(outMux)
);
assign out = outMux;
endmodule | module serialOcontiguo(
input usual,
input s_in,
input [1:0] modo,
output out
); |
wire usual, s_in, out;
wire [1:0] modo;
wire outNor;
wire outMux;
wire [1:0] canalesMux;
assign canalesMux[1] = s_in;
assign canalesMux[0] = usual;
parameter notoe = 1'b0;
norGate modeNor(
.a(modo[1]),
.b(modo[0]),
.y(outNor)
);
mux selector(
.s(outNor),
.a(canalesMux),
.notoe(notoe),
.y(outMux)
);
assign out = outMux;
endmodule | 0 |
2,619 | data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v | 100,331,186 | sreg_tb.v | v | 62 | 118 | [] | [] | [] | null | line:40: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK <= ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:16: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("pruebashift.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:17: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,pruebashift);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:25: Unsupported or unknown PLI call: $monitor\n $monitor("%t: %b \\t Q: %b\\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #3 ENB = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #1 ENB = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #4 ENB = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #6 ENB = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #15\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/modulos/sreg_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Error: Exiting due to 3 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 54 | module | module pruebashift;
reg [3:0] D;
reg [1:0] MODE;
reg ENB;
reg S_IN;
reg CLK;
reg DIR;
wire [3:0] Q;
wire S_OUT;
rdesplazante r1(CLK,ENB, DIR, S_IN, MODE,D,Q,S_OUT);
always #1 CLK <= ~CLK;
initial begin
$dumpfile("pruebashift.vcd");
$dumpvars(0,pruebashift);
CLK = 0;
D = 4'b0001;
S_IN = 1;
MODE = 2'b00;
DIR = 1;
ENB = 0;
$monitor("%t: %b \t Q: %b\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);
$display("Desplazamiento hacia la derecha:");
#3 ENB = 1;
#1 ENB = 1;
#25
S_IN = 0;
$display("Desplazamiento hacia la izquierda:");
DIR = 0;
#25
S_IN = 1;
#4 ENB = 0;
#6 ENB = 1;
$display("Rotación circular hacia la izquierda:");
MODE = 2'b01;
#15
$display("Rotación circular hacia la derecha:");
DIR = 1;
#10
$display("Carga en paralelo:");
MODE = 22'b10;
D = 4'b1010;
#3;
D = 4'b0000;
#3;
D = 4'b1011;
#3;
D = 4'b1111;
#3;
D = 4'b1001;
#3;
S_IN = 0;
D = 4'b1111;
#4
$finish;
end
endmodule | module pruebashift; |
reg [3:0] D;
reg [1:0] MODE;
reg ENB;
reg S_IN;
reg CLK;
reg DIR;
wire [3:0] Q;
wire S_OUT;
rdesplazante r1(CLK,ENB, DIR, S_IN, MODE,D,Q,S_OUT);
always #1 CLK <= ~CLK;
initial begin
$dumpfile("pruebashift.vcd");
$dumpvars(0,pruebashift);
CLK = 0;
D = 4'b0001;
S_IN = 1;
MODE = 2'b00;
DIR = 1;
ENB = 0;
$monitor("%t: %b \t Q: %b\t Load: %b Sale: %b entra: %b enable %b Dir: %b", $time, CLK, Q, D,S_OUT, S_IN, ENB, DIR);
$display("Desplazamiento hacia la derecha:");
#3 ENB = 1;
#1 ENB = 1;
#25
S_IN = 0;
$display("Desplazamiento hacia la izquierda:");
DIR = 0;
#25
S_IN = 1;
#4 ENB = 0;
#6 ENB = 1;
$display("Rotación circular hacia la izquierda:");
MODE = 2'b01;
#15
$display("Rotación circular hacia la derecha:");
DIR = 1;
#10
$display("Carga en paralelo:");
MODE = 22'b10;
D = 4'b1010;
#3;
D = 4'b0000;
#3;
D = 4'b1011;
#3;
D = 4'b1111;
#3;
D = 4'b1001;
#3;
S_IN = 0;
D = 4'b1111;
#4
$finish;
end
endmodule | 0 |
2,620 | data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v | 100,331,186 | ternarioDoble.v | v | 48 | 66 | [] | [] | [] | [(14, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 'a'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire a, b, c, s1, s2, y;\n ^\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:15: ... Location of original declaration\n input a,\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 'b'\n wire a, b, c, s1, s2, y;\n ^\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:16: ... Location of original declaration\n input b,\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 'c'\n wire a, b, c, s1, s2, y;\n ^\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:17: ... Location of original declaration\n input c,\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 's1'\n wire a, b, c, s1, s2, y;\n ^~\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:18: ... Location of original declaration\n input s1,\n ^~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 's2'\n wire a, b, c, s1, s2, y;\n ^~\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:19: ... Location of original declaration\n input s2,\n ^~\n%Error: data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:24: Duplicate declaration of signal: 'y'\n wire a, b, c, s1, s2, y;\n ^\n data/full_repos/permissive/100331186/tarea4/modulos/ternarioDoble.v:20: ... Location of original declaration\n output y\n ^\n%Error: Exiting due to 6 error(s)\n" | 55 | module | module ternarioDoble (
input a,
input b,
input c,
input s1,
input s2,
output y
);
wire a, b, c, s1, s2, y;
wire mux1__mux2;
parameter notoe = 1'b0;
mux mux1(
.s(s1),
.a({b, a}),
.notoe(notoe),
.y(mux1__mux2)
);
mux mux2(
.s(s2),
.a({c, mux1__mux2}),
.notoe(notoe),
.y(y)
);
endmodule | module ternarioDoble (
input a,
input b,
input c,
input s1,
input s2,
output y
); |
wire a, b, c, s1, s2, y;
wire mux1__mux2;
parameter notoe = 1'b0;
mux mux1(
.s(s1),
.a({b, a}),
.notoe(notoe),
.y(mux1__mux2)
);
mux mux2(
.s(s2),
.a({c, mux1__mux2}),
.notoe(notoe),
.y(y)
);
endmodule | 0 |
2,621 | data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v | 100,331,186 | testbitHolder.v | v | 183 | 90 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:2: Cannot find include file: ./modulos/bitHolder.v\n `include "./modulos/bitHolder.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/bitHolder.v.sv\n ./modulos/bitHolder.v\n ./modulos/bitHolder.v.v\n ./modulos/bitHolder.v.sv\n obj_dir/./modulos/bitHolder.v\n obj_dir/./modulos/bitHolder.v.v\n obj_dir/./modulos/bitHolder.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:5: Cannot find include file: ../tarea3/modulos/notGate.v\n `include "../tarea3/modulos/notGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:8: Cannot find include file: ../tarea3/modulos/norGate.v\n `include "../tarea3/modulos/norGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:11: Cannot find include file: ../tarea3/modulos/mux.v\n `include "../tarea3/modulos/mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:14: Cannot find include file: ../tarea3/modulos/ffD.v\n `include "../tarea3/modulos/ffD.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:17: Cannot find include file: ./modulos/ternarioDoble.v\n `include "./modulos/ternarioDoble.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:45: Unsupported: Ignoring delay on this delayed statement.\n initial # 50 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:53: Unsupported: Ignoring delay on this delayed statement.\n always # 37 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:67: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:70: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:78: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:80: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:88: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:92: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:99: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:101: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:110: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:117: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:119: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:127: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:131: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:138: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:140: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:149: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:156: Unsupported: Ignoring delay on this delayed statement.\n # 70\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:158: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:166: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:167: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:173: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testbitHolder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:174: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testbitHolder.v:179: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Error: Exiting due to 20 error(s), 11 warning(s)\n' | 56 | module | module testbitHolder ();
reg s_der, s_izq, d_n, dir, clk, enb;
reg [1:0] modo;
wire clkenb, y;
assign clkenb = clk & enb;
bitHolder tester(
.s_der(s_der),
.s_izq(s_izq),
.d_n(d_n),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(s_out)
);
initial # 50 clk = 0;
always # 37 clk = ~clk;
initial begin
# 50;
enb <= 1;
$display("se carga un 0");
@(posedge clk);
modo <= 2'b1x;
s_der <= 1'bx;
s_izq <= 1'bx;
d_n <= 1'b0;
dir <= 1'bx;
# 50;
$display("se carga un 1");
@(posedge clk);
modo <= 2'b1x;
s_der <= 1'bx;
s_izq <= 1'bx;
d_n <= 1'b1;
dir <= 1'bx;
# 70
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_der = 0");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b0;
d_n <= 1'bx;
# 70
$display("con s_der = 1");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b1;
d_n <= 1'bx;
$display("Hacia la derecha");
$display("con s_izq = 0");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'b0;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("con s_izq = 1");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'b1;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("---\nModo de rotacion\n---");
$display("Hacia la izquierda");
$display("con s_der = 0");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b0;
d_n <= 1'bx;
# 70
$display("con s_der = 1");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b1;
d_n <= 1'bx;
$display("Hacia la derecha");
$display("con s_izq = 0");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'b0;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("con s_izq = 1");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'b1;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 150;
@(posedge clk);
$finish;
end
initial
begin
$dumpfile("./tests/testbitHolder.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo bitHolder --");
$display("------------------------------------");
$display ("\t tiempo | s_der | s_izq | d_n | dir | modo[1] | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",
$time, s_der, s_izq, d_n, dir, modo[1], s_out, $realtime);
end
endmodule | module testbitHolder (); |
reg s_der, s_izq, d_n, dir, clk, enb;
reg [1:0] modo;
wire clkenb, y;
assign clkenb = clk & enb;
bitHolder tester(
.s_der(s_der),
.s_izq(s_izq),
.d_n(d_n),
.dir(dir),
.modo(modo),
.clkenb(clkenb),
.s_out(s_out)
);
initial # 50 clk = 0;
always # 37 clk = ~clk;
initial begin
# 50;
enb <= 1;
$display("se carga un 0");
@(posedge clk);
modo <= 2'b1x;
s_der <= 1'bx;
s_izq <= 1'bx;
d_n <= 1'b0;
dir <= 1'bx;
# 50;
$display("se carga un 1");
@(posedge clk);
modo <= 2'b1x;
s_der <= 1'bx;
s_izq <= 1'bx;
d_n <= 1'b1;
dir <= 1'bx;
# 70
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_der = 0");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b0;
d_n <= 1'bx;
# 70
$display("con s_der = 1");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b1;
d_n <= 1'bx;
$display("Hacia la derecha");
$display("con s_izq = 0");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'b0;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("con s_izq = 1");
@(posedge clk);
modo <= 2'b00;
s_izq <= 1'b1;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("---\nModo de rotacion\n---");
$display("Hacia la izquierda");
$display("con s_der = 0");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b0;
d_n <= 1'bx;
# 70
$display("con s_der = 1");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'bx;
dir <= 1'b0;
s_der <= 1'b1;
d_n <= 1'bx;
$display("Hacia la derecha");
$display("con s_izq = 0");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'b0;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 70
$display("con s_izq = 1");
@(posedge clk);
modo <= 2'b01;
s_izq <= 1'b1;
dir <= 1'b1;
s_der <= 1'bx;
d_n <= 1'bx;
# 150;
@(posedge clk);
$finish;
end
initial
begin
$dumpfile("./tests/testbitHolder.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo bitHolder --");
$display("------------------------------------");
$display ("\t tiempo | s_der | s_izq | d_n | dir | modo[1] | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",
$time, s_der, s_izq, d_n, dir, modo[1], s_out, $realtime);
end
endmodule | 0 |
2,622 | data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v | 100,331,186 | testenabler.v | v | 73 | 91 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:2: Cannot find include file: modulos/enabler.v\n `include "modulos/enabler.v" \n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/enabler.v.sv\n modulos/enabler.v\n modulos/enabler.v.v\n modulos/enabler.v.sv\n obj_dir/modulos/enabler.v\n obj_dir/modulos/enabler.v.v\n obj_dir/modulos/enabler.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:5: Cannot find include file: ../tarea3/modulos/nandGate.v\n `include "../tarea3/modulos/nandGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:8: Cannot find include file: ../tarea3/modulos/notGate.v\n `include "../tarea3/modulos/notGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:28: Unsupported: Ignoring delay on this delayed statement.\n always #30 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:34: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:37: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:40: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:42: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:45: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:47: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:50: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:57: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testEnabler.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:58: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:63: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b ",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testenabler.v:65: Unsupported: Ignoring delay on this delayed statement.\n #450\n ^\n%Error: Exiting due to 6 error(s), 9 warning(s)\n' | 57 | module | module testenabler();
reg clk;
reg enb;
wire out;
enabler tester(
.clk(clk),
.enb(enb),
.eclk(out)
);
parameter retardos = 30;
always #30 clk = !clk;
initial begin
clk = 0;
enb = 1;
#retardos
enb = 0;
#retardos
enb = 1;
#retardos
enb = 0;
#retardos
enb = 0;
#retardos
enb = 0;
#retardos
enb = 1;
#retardos
enb = 1;
end
initial
begin
$dumpfile("./tests/testEnabler.vcd");
$dumpvars();
$display("------------------------------------");
$display("-- Test para modulo Enabler --");
$display("------------------------------------");
$display ("\t tiempo | clk | enb | out ");
$monitor ("%t| %b | %b | %b ",
$time, clk, enb, out);
#450
$display("------------------------------------");
$display("####### FIN TEST DE: ENABLER ######");
$display("------------------------------------");
$finish;
end
endmodule | module testenabler(); |
reg clk;
reg enb;
wire out;
enabler tester(
.clk(clk),
.enb(enb),
.eclk(out)
);
parameter retardos = 30;
always #30 clk = !clk;
initial begin
clk = 0;
enb = 1;
#retardos
enb = 0;
#retardos
enb = 1;
#retardos
enb = 0;
#retardos
enb = 0;
#retardos
enb = 0;
#retardos
enb = 1;
#retardos
enb = 1;
end
initial
begin
$dumpfile("./tests/testEnabler.vcd");
$dumpvars();
$display("------------------------------------");
$display("-- Test para modulo Enabler --");
$display("------------------------------------");
$display ("\t tiempo | clk | enb | out ");
$monitor ("%t| %b | %b | %b ",
$time, clk, enb, out);
#450
$display("------------------------------------");
$display("####### FIN TEST DE: ENABLER ######");
$display("------------------------------------");
$finish;
end
endmodule | 0 |
2,623 | data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v | 100,331,186 | testregistro4bits.v | v | 289 | 114 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:2: Cannot find include file: ./modulos/salidaSerial.v\n `include "./modulos/salidaSerial.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/./modulos/salidaSerial.v.sv\n ./modulos/salidaSerial.v\n ./modulos/salidaSerial.v.v\n ./modulos/salidaSerial.v.sv\n obj_dir/./modulos/salidaSerial.v\n obj_dir/./modulos/salidaSerial.v.v\n obj_dir/./modulos/salidaSerial.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:5: Cannot find include file: ./modulos/registro4bits.v\n `include "./modulos/registro4bits.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:8: Cannot find include file: ./modulos/bitHolder.v\n `include "./modulos/bitHolder.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:11: Cannot find include file: ./modulos/ternarioDoble.v\n `include "./modulos/ternarioDoble.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:14: Cannot find include file: ./modulos/serialOcontiguo.v\n `include "./modulos/serialOcontiguo.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:17: Cannot find include file: ./modulos/enabler.v\n `include "./modulos/enabler.v" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:21: Cannot find include file: ../tarea3/modulos/norGate.v\n `include "../tarea3/modulos/norGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:24: Cannot find include file: ../tarea3/modulos/notGate.v\n `include "../tarea3/modulos/notGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:27: Cannot find include file: ../tarea3/modulos/nandGate.v\n `include "../tarea3/modulos/nandGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:30: Cannot find include file: ../tarea3/modulos/mux.v\n `include "../tarea3/modulos/mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:33: Cannot find include file: ../tarea3/modulos/ffD.v\n `include "../tarea3/modulos/ffD.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:37: Cannot find include file: ./modulos/sreg.v\n `include "./modulos/sreg.v" \n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:95: Unsupported: Ignoring delay on this delayed statement.\n initial # 50 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:97: Unsupported: Ignoring delay on this delayed statement.\n always # 17.4 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:111: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:112: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:123: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:125: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:131: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:133: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:138: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:140: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:145: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:147: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:152: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:154: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:159: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:161: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:167: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:169: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:174: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:176: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:181: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:183: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:188: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:190: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:197: Unsupported: Ignoring delay on this delayed statement.\n # 200\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:201: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:207: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:209: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:212: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:215: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:219: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:221: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:224: Unsupported: Ignoring delay on this delayed statement.\n # 90\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:226: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:229: Unsupported: Ignoring delay on this delayed statement.\n # 60\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:231: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:234: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:236: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:239: Unsupported: Ignoring delay on this delayed statement.\n # 550;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:240: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:244: Unsupported: Ignoring delay on this delayed statement.\n # 60;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:246: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:254: Unsupported: Ignoring delay on this delayed statement.\n # 200\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:257: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:262: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:264: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:267: Unsupported: Ignoring delay on this delayed statement.\n # 550;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:268: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:279: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testregistro4bits.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:280: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testregistro4bits.v:285: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Error: Exiting due to 38 error(s), 25 warning(s)\n' | 58 | module | module testregistro4bits ();
wire [3:0] qe;
wire s_oute;
reg clk;
reg enb;
reg dir;
reg s_in;
reg [1:0] modo;
reg [3:0] d;
wire [3:0] qc;
wire s_outc;
registro4bits estructural(
.clk(clk),
.enb(enb),
.dir(dir),
.s_in(s_in),
.modo(modo),
.d(d),
.q(qe),
.s_out(s_oute)
);
rdesplazante conductual(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qc),
.S_OUT(s_outc)
);
initial # 50 clk = 0;
always # 17.4 clk = ~clk;
always @(qe,qc ) begin
if(qe != qc)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas q >>>>>>>>>>>>>>>>>>>");
end
always @(s_outc,s_oute ) begin
if(s_outc != s_oute)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas s_out >>>>>>>>>>>>>>>>>>>");
end
initial begin
# 50;
@(posedge clk);
modo <= 2'b00;
# 10;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0010");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0010;
dir <= 1'bx;
# 50;
$display("se carga 0100");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0100;
dir <= 1'bx;
# 50;
$display("se carga 1000");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1000;
dir <= 1'bx;
# 50;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0011");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0011;
dir <= 1'bx;
# 50;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 50;
$display("se carga 1111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1111;
dir <= 1'bx;
# 200
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_in = 0");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b00;
dir <= 1'b0;
s_in <= 2'b0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1;
# 400
$display("Hacia la derecha");
$display("con s_in = 0");
@(posedge clk);
dir <= 1'b1;
s_in <= 0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 90
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 60
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 40
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 550;
@(posedge clk);
$display("Hacemos otra carga paralela antes de la rotacion circular");
# 60;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 200
$display("---\nModo de rotacion circular\n---");
$display("Hacia la izquierda");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b01;
dir <= 1'b0;
# 400
$display("Hacia la derecha");
@(posedge clk);
dir <= 1'b1;
# 550;
@(posedge clk);
$display("------------------------------------");
$display("##### FIN TEST DE REGISTRO #####-");
$display("------------------------------------");
$finish;
end
initial
begin
$dumpfile("./tests/testregistro4bits.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo registro4bits --");
$display("------------------------------------");
$display ("\t tiempo | enb | dir | s_in | modo | d | q | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",
$time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
end
endmodule | module testregistro4bits (); |
wire [3:0] qe;
wire s_oute;
reg clk;
reg enb;
reg dir;
reg s_in;
reg [1:0] modo;
reg [3:0] d;
wire [3:0] qc;
wire s_outc;
registro4bits estructural(
.clk(clk),
.enb(enb),
.dir(dir),
.s_in(s_in),
.modo(modo),
.d(d),
.q(qe),
.s_out(s_oute)
);
rdesplazante conductual(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qc),
.S_OUT(s_outc)
);
initial # 50 clk = 0;
always # 17.4 clk = ~clk;
always @(qe,qc ) begin
if(qe != qc)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas q >>>>>>>>>>>>>>>>>>>");
end
always @(s_outc,s_oute ) begin
if(s_outc != s_oute)$display("<<<<<<<<<<<<<<<<HAY ADiferencias entre las salidas s_out >>>>>>>>>>>>>>>>>>>");
end
initial begin
# 50;
@(posedge clk);
modo <= 2'b00;
# 10;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0010");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0010;
dir <= 1'bx;
# 50;
$display("se carga 0100");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0100;
dir <= 1'bx;
# 50;
$display("se carga 1000");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1000;
dir <= 1'bx;
# 50;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0011");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0011;
dir <= 1'bx;
# 50;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 50;
$display("se carga 1111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1111;
dir <= 1'bx;
# 200
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_in = 0");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b00;
dir <= 1'b0;
s_in <= 2'b0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1;
# 400
$display("Hacia la derecha");
$display("con s_in = 0");
@(posedge clk);
dir <= 1'b1;
s_in <= 0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 90
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 60
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 40
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 550;
@(posedge clk);
$display("Hacemos otra carga paralela antes de la rotacion circular");
# 60;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 200
$display("---\nModo de rotacion circular\n---");
$display("Hacia la izquierda");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b01;
dir <= 1'b0;
# 400
$display("Hacia la derecha");
@(posedge clk);
dir <= 1'b1;
# 550;
@(posedge clk);
$display("------------------------------------");
$display("##### FIN TEST DE REGISTRO #####-");
$display("------------------------------------");
$finish;
end
initial
begin
$dumpfile("./tests/testregistro4bits.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo registro4bits --");
$display("------------------------------------");
$display ("\t tiempo | enb | dir | s_in | modo | d | q | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",
$time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
end
endmodule | 0 |
2,624 | data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v | 100,331,186 | testsalidaSerial.v | v | 188 | 84 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:2: Cannot find include file: modulos/ternarioDoble.v\n `include "modulos/ternarioDoble.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.sv\n modulos/ternarioDoble.v\n modulos/ternarioDoble.v.v\n modulos/ternarioDoble.v.sv\n obj_dir/modulos/ternarioDoble.v\n obj_dir/modulos/ternarioDoble.v.v\n obj_dir/modulos/ternarioDoble.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:5: Cannot find include file: ../tarea3/modulos/mux.v\n `include "../tarea3/modulos/mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:8: Cannot find include file: ../tarea3/modulos/norGate.v\n `include "../tarea3/modulos/norGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:11: Cannot find include file: modulos/salidaSerial.v\n `include "modulos/salidaSerial.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:14: Cannot find include file: modulos/serialOcontiguo.v\n `include "modulos/serialOcontiguo.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:43: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:49: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:55: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:61: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:67: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:73: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:79: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:85: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:91: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:97: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:103: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:109: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:115: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:121: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:127: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:133: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:139: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:145: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:151: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:157: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:163: Unsupported: Ignoring delay on this delayed statement.\n #retardos\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:175: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testsalidaSerial.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:176: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testsalidaSerial.v:181: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 21 warning(s)\n' | 59 | module | module testsalidaSerial ();
reg s_der, s_izq, dir;
reg [1:0] modo;
wire outAnd;
wire s_out;
salidaSerial tester(
.modo(modo),
.s_der(s_der),
.s_izq(s_izq),
.dir(dir),
.s_out(s_out)
);
parameter retardos = 25;
initial begin
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b01;
s_der = 1;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b01;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b10;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
$finish;
end
initial begin
$dumpfile("./tests/testsalidaSerial.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test -para modulo salidaSerial --");
$display("------------------------------------");
$display ("\t tiempo | s_der | s_izq | dir | dir | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %f ns",
$time, s_der, s_izq, dir, s_out, $realtime);
end
endmodule | module testsalidaSerial (); |
reg s_der, s_izq, dir;
reg [1:0] modo;
wire outAnd;
wire s_out;
salidaSerial tester(
.modo(modo),
.s_der(s_der),
.s_izq(s_izq),
.dir(dir),
.s_out(s_out)
);
parameter retardos = 25;
initial begin
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b01;
s_der = 1;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b01;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b10;
s_der = 0;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b10;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 1;
dir = 0;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 1;
#retardos
modo = 2'b00;
s_der = 0;
s_izq = 1;
dir = 1;
#retardos
modo = 2'b00;
s_der = 1;
s_izq = 0;
dir = 0;
$finish;
end
initial begin
$dumpfile("./tests/testsalidaSerial.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test -para modulo salidaSerial --");
$display("------------------------------------");
$display ("\t tiempo | s_der | s_izq | dir | dir | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %f ns",
$time, s_der, s_izq, dir, s_out, $realtime);
end
endmodule | 0 |
2,625 | data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v | 100,331,186 | testserialOcontiguo.v | v | 139 | 61 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:2: Cannot find include file: ../tarea3/modulos/norGate.v\n `include "../tarea3/modulos/norGate.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/../tarea3/modulos/norGate.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/../tarea3/modulos/norGate.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/../tarea3/modulos/norGate.v.sv\n ../tarea3/modulos/norGate.v\n ../tarea3/modulos/norGate.v.v\n ../tarea3/modulos/norGate.v.sv\n obj_dir/../tarea3/modulos/norGate.v\n obj_dir/../tarea3/modulos/norGate.v.v\n obj_dir/../tarea3/modulos/norGate.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:5: Cannot find include file: ../tarea3/modulos/mux.v\n `include "../tarea3/modulos/mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:8: Cannot find include file: ./modulos/serialOcontiguo.v\n `include "./modulos/serialOcontiguo.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:34: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:38: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:42: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:46: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:50: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:54: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:58: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:62: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:66: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:70: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:74: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:78: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:82: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:86: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:90: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:94: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:98: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:102: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:106: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:110: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:114: Unsupported: Ignoring delay on this delayed statement.\n#retardos\n^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:122: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testserialOcontiguo.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:123: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:129: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b",\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testserialOcontiguo.v:131: Unsupported: Ignoring delay on this delayed statement.\n #2650\n ^\n%Error: Exiting due to 6 error(s), 22 warning(s)\n' | 60 | module | module testserialOcontiguo ();
reg usual, s_in;
reg [1:0] modo;
wire out;
parameter retardos = 40;
serialOcontiguo tester(
.usual(usual),
.s_in(s_in),
.modo(modo),
.out(out)
);
initial begin
usual <= 0;
modo <= 2'b0;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b0;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b01;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b01;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b11;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b11;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
end
initial
begin
$dumpfile("./tests/testserialOcontiguo.vcd");
$dumpvars();
$display("---------------------------------------");
$display("-- Test para modulo serialOcontiguo --");
$display("---------------------------------------");
$display ("\t tiempo | usual | s_in | modo | out ");
$monitor ("%t| %b | %b | %b | %b",
$time, usual, s_in, modo, out);
#2650
$display("---------------------------------------");
$display("##### FIN TEST DE: SERIALOCONTIGUO ####");
$display("---------------------------------------");
$finish;
end
endmodule | module testserialOcontiguo (); |
reg usual, s_in;
reg [1:0] modo;
wire out;
parameter retardos = 40;
serialOcontiguo tester(
.usual(usual),
.s_in(s_in),
.modo(modo),
.out(out)
);
initial begin
usual <= 0;
modo <= 2'b0;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b0;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b01;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b01;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b11;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b11;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b10;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 1;
#retardos
usual <= 0;
modo <= 2'b00;
s_in <= 0;
#retardos
usual <= 1;
modo <= 2'b00;
s_in <= 1;
end
initial
begin
$dumpfile("./tests/testserialOcontiguo.vcd");
$dumpvars();
$display("---------------------------------------");
$display("-- Test para modulo serialOcontiguo --");
$display("---------------------------------------");
$display ("\t tiempo | usual | s_in | modo | out ");
$monitor ("%t| %b | %b | %b | %b",
$time, usual, s_in, modo, out);
#2650
$display("---------------------------------------");
$display("##### FIN TEST DE: SERIALOCONTIGUO ####");
$display("---------------------------------------");
$finish;
end
endmodule | 0 |
2,626 | data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v | 100,331,186 | testternarioDoble.v | v | 186 | 75 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:2: Cannot find include file: modulos/ternarioDoble.v\n `include "modulos/ternarioDoble.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.v\n data/full_repos/permissive/100331186/tarea4/pruebas,data/full_repos/permissive/100331186/modulos/ternarioDoble.v.sv\n modulos/ternarioDoble.v\n modulos/ternarioDoble.v.v\n modulos/ternarioDoble.v.sv\n obj_dir/modulos/ternarioDoble.v\n obj_dir/modulos/ternarioDoble.v.v\n obj_dir/modulos/ternarioDoble.v.sv\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:5: Cannot find include file: ../tarea3/modulos/mux.v\n `include "../tarea3/modulos/mux.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:34: Unsupported: Ignoring delay on this delayed statement.\n initial # 50 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:41: Unsupported: Ignoring delay on this delayed statement.\n always # 45 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:46: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:47: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:56: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:57: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:59: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:60: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:62: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:63: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:67: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:68: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:76: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:77: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:79: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:80: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:82: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:83: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:88: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:89: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:98: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:99: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:101: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:102: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:104: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:105: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:109: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:110: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:118: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:119: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:121: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:122: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:124: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:125: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:130: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:131: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:140: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:141: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:143: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:144: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:146: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:147: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:151: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:152: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:160: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:161: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:163: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:164: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:166: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:167: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:169: Unsupported: Ignoring delay on this delayed statement.\n # 150;\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:170: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:176: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("./tests/testternarioDoble.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:177: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea4/pruebas/testternarioDoble.v:182: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Error: Exiting due to 30 error(s), 27 warning(s)\n' | 61 | module | module testternarioDoble ();
reg a, b, c, s1, s2, clk;
wire y;
ternarioDoble tester(
.a(a),
.b(b),
.c(c),
.s1(s1),
.s2(s2),
.y(y)
);
initial # 50 clk = 0;
always # 45 clk = ~clk;
initial begin
# 150;
@(posedge clk);
$display("Eleccion de señal a=0, entonces s1=0 y s2=0");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b0;
s2 <= 1'b0;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal a=1, entonces s1=0 y s2=0");
a <= 1'b1;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b0;
s2 <= 1'b0;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal b=0, entonces s1=0 y s2=0");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b1;
s2 <= 1'b0;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal b=1, entonces s1=1 y s2=0");
a <= 1'b0;
b <= 1'b1;
c <= 1'b0;
s1 <= 1'b1;
s2 <= 1'b0;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal c=0, entonces s1=x y s2=1");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'bx;
s2 <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal c=1, entonces s0=x y s1=1");
a <= 1'b0;
b <= 1'b0;
c <= 1'b1;
s1 <= 1'bx;
s2 <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$finish;
end
initial
begin
$dumpfile("./tests/testternarioDoble.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo ternarioDoble --");
$display("------------------------------------");
$display ("\t tiempo | a | b | c | s1 | s2 | y | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",
$time, a, b, c, s1, s2, y, $realtime);
end
endmodule | module testternarioDoble (); |
reg a, b, c, s1, s2, clk;
wire y;
ternarioDoble tester(
.a(a),
.b(b),
.c(c),
.s1(s1),
.s2(s2),
.y(y)
);
initial # 50 clk = 0;
always # 45 clk = ~clk;
initial begin
# 150;
@(posedge clk);
$display("Eleccion de señal a=0, entonces s1=0 y s2=0");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b0;
s2 <= 1'b0;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal a=1, entonces s1=0 y s2=0");
a <= 1'b1;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b0;
s2 <= 1'b0;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal b=0, entonces s1=0 y s2=0");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'b1;
s2 <= 1'b0;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal b=1, entonces s1=1 y s2=0");
a <= 1'b0;
b <= 1'b1;
c <= 1'b0;
s1 <= 1'b1;
s2 <= 1'b0;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
c <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal c=0, entonces s1=x y s2=1");
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
s1 <= 1'bx;
s2 <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$display("Eleccion de señal c=1, entonces s0=x y s1=1");
a <= 1'b0;
b <= 1'b0;
c <= 1'b1;
s1 <= 1'bx;
s2 <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b1;
# 150;
@(posedge clk);
b <= 1'b1;
# 150;
@(posedge clk);
a <= 1'b0;
# 150;
@(posedge clk);
$finish;
end
initial
begin
$dumpfile("./tests/testternarioDoble.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo ternarioDoble --");
$display("------------------------------------");
$display ("\t tiempo | a | b | c | s1 | s2 | y | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %f ns",
$time, a, b, c, s1, s2, y, $realtime);
end
endmodule | 0 |
2,627 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module BUF(A, Y);
input A;
output Y;
assign #(3.5:4.8:6) Y = A;
endmodule | module BUF(A, Y); |
input A;
output Y;
assign #(3.5:4.8:6) Y = A;
endmodule | 0 |
2,628 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module NOT(A, Y);
input A;
output Y;
assign #(1:3.8:7.5) Y = ~A;
endmodule | module NOT(A, Y); |
input A;
output Y;
assign #(1:3.8:7.5) Y = ~A;
endmodule | 0 |
2,629 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module NAND(A, B, Y);
input A, B;
output Y;
assign #(1.5:5:6.5) Y = ~(A & B);
endmodule | module NAND(A, B, Y); |
input A, B;
output Y;
assign #(1.5:5:6.5) Y = ~(A & B);
endmodule | 0 |
2,630 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module NOR(A, B, Y);
input A, B;
output Y;
assign #(1:5.1:7.5) Y = ~(A | B);
endmodule | module NOR(A, B, Y); |
input A, B;
output Y;
assign #(1:5.1:7.5) Y = ~(A | B);
endmodule | 0 |
2,631 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
#(1.5:5.4:7.5) Q <= D;
endmodule | module DFF(C, D, Q); |
input C, D;
output reg Q;
always @(posedge C)
#(1.5:5.4:7.5) Q <= D;
endmodule | 0 |
2,632 | data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v | 100,331,186 | cmos_cells.v | v | 46 | 104 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:31: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:39: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b1; \n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:41: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:43: Unsupported: Ignoring delay on this delayed statement.\n#(1.5:5.4:7.5) Q <= D;\n^\n%Warning-MULTITOP: data/full_repos/permissive/100331186/tarea5/con-retrasos/lib/cmos_cells.v:9: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'BUF\'\nmodule BUF(A, Y);\n ^~~\n : ... Top module \'NOT\'\nmodule NOT(A, Y);\n ^~~\n : ... Top module \'NAND\'\nmodule NAND(A, B, Y);\n ^~~~\n : ... Top module \'NOR\'\nmodule NOR(A, B, Y);\n ^~~\n : ... Top module \'DFF\'\nmodule DFF(C, D, Q);\n ^~~\n : ... Top module \'DFFSR\'\nmodule DFFSR(C, D, Q, S, R); \n ^~~~~\n%Error: Exiting due to 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 62 | module | module DFFSR(C, D, Q, S, R);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
#(1.5:5.4:7.5) Q <= 1'b1;
else if (R)
#(1.5:5.4:7.5) Q <= 1'b0;
else
#(1.5:5.4:7.5) Q <= D;
endmodule | module DFFSR(C, D, Q, S, R); |
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S)
#(1.5:5.4:7.5) Q <= 1'b1;
else if (R)
#(1.5:5.4:7.5) Q <= 1'b0;
else
#(1.5:5.4:7.5) Q <= D;
endmodule | 0 |
2,633 | data/full_repos/permissive/100331186/tarea5/con-retrasos/src/sreg1.v | 100,331,186 | sreg1.v | v | 38 | 56 | [] | [] | [] | [(1, 37)] | null | data/verilator_xmls/9402ee39-4820-466c-b16c-7f170a1edf2f.xml | null | 64 | module | module rdesplazante1(CLK, ENB,DIR,S_IN,MODE,D,Q,S_OUT);
input [3 : 0] D;
input [1:0] MODE;
input ENB,S_IN,CLK,DIR;
output reg [3:0] Q;
output reg S_OUT;
always@(posedge CLK)
if(ENB) begin
if(MODE === 2'b00) begin
S_OUT = 1;
if(!DIR) begin
Q[3:0] <= {Q[2:0],S_IN};
S_OUT <= Q[3];
end
else begin
Q[3:0] <= {S_IN,Q[3:1]};
S_OUT <= Q[0];
end
end
if(MODE === 2'b01) begin
if(!DIR) begin
Q[3:1] <= Q[2:0];
Q[0] <= Q[3];
end
else begin
Q[3] <= Q[0];
Q[2:0] <= Q[3:1];
end
end
if(MODE === 2'b10) begin
Q <= D;
end
end
endmodule | module rdesplazante1(CLK, ENB,DIR,S_IN,MODE,D,Q,S_OUT); |
input [3 : 0] D;
input [1:0] MODE;
input ENB,S_IN,CLK,DIR;
output reg [3:0] Q;
output reg S_OUT;
always@(posedge CLK)
if(ENB) begin
if(MODE === 2'b00) begin
S_OUT = 1;
if(!DIR) begin
Q[3:0] <= {Q[2:0],S_IN};
S_OUT <= Q[3];
end
else begin
Q[3:0] <= {S_IN,Q[3:1]};
S_OUT <= Q[0];
end
end
if(MODE === 2'b01) begin
if(!DIR) begin
Q[3:1] <= Q[2:0];
Q[0] <= Q[3];
end
else begin
Q[3] <= Q[0];
Q[2:0] <= Q[3:1];
end
end
if(MODE === 2'b10) begin
Q <= D;
end
end
endmodule | 0 |
2,634 | data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v | 100,331,186 | enabler.v | v | 34 | 41 | [] | [] | [] | [(7, 33)] | null | null | 1: b"%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'clk'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire clk,enb,eclk;\n ^~~\n data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:8: ... Location of original declaration\n input clk,\n ^~~\n%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'enb'\n wire clk,enb,eclk;\n ^~~\n data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:9: ... Location of original declaration\n input enb,\n ^~~\n%Error: data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:13: Duplicate declaration of signal: 'eclk'\n wire clk,enb,eclk;\n ^~~~\n data/full_repos/permissive/100331186/tarea5/con-retrasos/src/modulosT4/enabler.v:10: ... Location of original declaration\n output eclk\n ^~~~\n%Error: Exiting due to 3 error(s)\n" | 72 | module | module enabler(
input clk,
input enb,
output eclk
);
wire clk,enb,eclk;
wire outNot;
wire outNand;
parameter notoe = 1'b0;
nandGate modeNor(
.a(clk),
.b(enb),
.y(outNand)
);
notGate inverter(
.a(outNand),
.y(outNot)
);
assign eclk = outNot;
endmodule | module enabler(
input clk,
input enb,
output eclk
); |
wire clk,enb,eclk;
wire outNot;
wire outNand;
parameter notoe = 1'b0;
nandGate modeNor(
.a(clk),
.b(enb),
.y(outNand)
);
notGate inverter(
.a(outNand),
.y(outNot)
);
assign eclk = outNot;
endmodule | 0 |
2,635 | data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v | 100,331,186 | test.v | v | 255 | 116 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:2: Cannot find include file: ./build/sintetizado.v\n `include "./build/sintetizado.v" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v\n data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v.v\n data/full_repos/permissive/100331186/tarea5/sin-retrasos/src,data/full_repos/permissive/100331186/./build/sintetizado.v.sv\n ./build/sintetizado.v\n ./build/sintetizado.v.v\n ./build/sintetizado.v.sv\n obj_dir/./build/sintetizado.v\n obj_dir/./build/sintetizado.v.v\n obj_dir/./build/sintetizado.v.sv\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:5: Cannot find include file: ./modulos/sreg.v\n `include "./modulos/sreg.v" \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:7: Cannot find include file: ./lib/cmos_cells.v\n`include "./lib/cmos_cells.v" \n ^~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n initial # 50 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n always # 17.4 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:77: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:78: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:89: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:91: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:97: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:99: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:104: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:106: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:111: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:113: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:118: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:120: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:125: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:127: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:133: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:135: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:140: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:142: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:147: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:149: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:154: Unsupported: Ignoring delay on this delayed statement.\n # 50;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:156: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:163: Unsupported: Ignoring delay on this delayed statement.\n # 200\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:167: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:173: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:175: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:178: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:181: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:185: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:187: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:190: Unsupported: Ignoring delay on this delayed statement.\n # 90\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:192: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:195: Unsupported: Ignoring delay on this delayed statement.\n # 60\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:197: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:200: Unsupported: Ignoring delay on this delayed statement.\n # 40\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:202: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:205: Unsupported: Ignoring delay on this delayed statement.\n # 550;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:206: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:210: Unsupported: Ignoring delay on this delayed statement.\n # 60;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:212: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:220: Unsupported: Ignoring delay on this delayed statement.\n # 200\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:223: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:228: Unsupported: Ignoring delay on this delayed statement.\n # 400\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:230: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:233: Unsupported: Ignoring delay on this delayed statement.\n # 550;\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:234: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:245: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tests/rdesplazante.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:246: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100331186/tarea5/sin-retrasos/src/test.v:251: Unsupported or unknown PLI call: $monitor\n $monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",\n ^~~~~~~~\n%Error: Exiting due to 29 error(s), 25 warning(s)\n' | 83 | module | module testregistro4bits ();
wire [3:0] qe;
wire s_oute;
reg clk;
reg enb;
reg dir;
reg s_in;
reg [1:0] modo;
reg [3:0] d;
wire [3:0] qc;
wire s_outc;
real cambioqc;
real cambioqe;
real cambiosoc;
real cambiosoe;
real tp = 43;
integer contador = 0;
rdesplazante estructural(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qe),
.S_OUT(s_oute)
);
rdesplazanteconduct conductual(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qc),
.S_OUT(s_outc)
);
initial # 50 clk = 0;
always # 17.4 clk = ~clk;
always @(qe) cambioqe = $time;
always @(qc) cambioqc = $time;
always @(s_outc) cambiosoc = $time;
always @(s_oute) cambiosoe = $time;
always @(qe, qc) begin
if (qe != qc) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas q >>>>>>>>>>>>>>>>>>>");
end
always @(s_outc, s_oute) begin
if (s_outc != s_oute) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas s_out >>>>>>>>>>>>>>>>>>>");
end
initial begin
# 50;
@(posedge clk);
modo <= 2'b00;
# 10;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0010");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0010;
dir <= 1'bx;
# 50;
$display("se carga 0100");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0100;
dir <= 1'bx;
# 50;
$display("se carga 1000");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1000;
dir <= 1'bx;
# 50;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0011");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0011;
dir <= 1'bx;
# 50;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 50;
$display("se carga 1111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1111;
dir <= 1'bx;
# 200
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_in = 0");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b00;
dir <= 1'b0;
s_in <= 2'b0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1;
# 400
$display("Hacia la derecha");
$display("con s_in = 0");
@(posedge clk);
dir <= 1'b1;
s_in <= 0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 90
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 60
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 40
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 550;
@(posedge clk);
$display("Hacemos otra carga paralela antes de la rotacion circular");
# 60;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 200
$display("---\nModo de rotacion circular\n---");
$display("Hacia la izquierda");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b01;
dir <= 1'b0;
# 400
$display("Hacia la derecha");
@(posedge clk);
dir <= 1'b1;
# 550;
@(posedge clk);
$display("------------------------------------------------------------------------------------------");
$display("## FIN COMPARACION DE SINTESIS SIN TIEMPOS DE RETRASO DE YOSYS Y DESCRIPCION CONDUCTUAL ##");
$display("------------------------------------------------------------------------------------------");
$display("Cantidad de diferencias totales: %d", contador);
$finish;
end
initial
begin
$dumpfile("tests/rdesplazante.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo rdesplazante --");
$display("------------------------------------");
$display ("\t tiempo | enb | dir | s_in | modo | d | q | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",
$time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
end
endmodule | module testregistro4bits (); |
wire [3:0] qe;
wire s_oute;
reg clk;
reg enb;
reg dir;
reg s_in;
reg [1:0] modo;
reg [3:0] d;
wire [3:0] qc;
wire s_outc;
real cambioqc;
real cambioqe;
real cambiosoc;
real cambiosoe;
real tp = 43;
integer contador = 0;
rdesplazante estructural(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qe),
.S_OUT(s_oute)
);
rdesplazanteconduct conductual(
.CLK(clk),
.ENB(enb),
.DIR(dir),
.S_IN(s_in),
.MODE(modo),
.D(d),
.Q(qc),
.S_OUT(s_outc)
);
initial # 50 clk = 0;
always # 17.4 clk = ~clk;
always @(qe) cambioqe = $time;
always @(qc) cambioqc = $time;
always @(s_outc) cambiosoc = $time;
always @(s_oute) cambiosoe = $time;
always @(qe, qc) begin
if (qe != qc) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas q >>>>>>>>>>>>>>>>>>>");
end
always @(s_outc, s_oute) begin
if (s_outc != s_oute) $display("<<<<<<<<<<<<<<<<Hay diferencias entre las salidas s_out >>>>>>>>>>>>>>>>>>>");
end
initial begin
# 50;
@(posedge clk);
modo <= 2'b00;
# 10;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0010");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0010;
dir <= 1'bx;
# 50;
$display("se carga 0100");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0100;
dir <= 1'bx;
# 50;
$display("se carga 1000");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1000;
dir <= 1'bx;
# 50;
$display("se carga 0000");
@(posedge clk);
enb <= 1;
modo <= 2'b10;
d <= 4'b0000;
dir <= 1'bx;
# 50;
$display("se carga 0001");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0001;
dir <= 1'bx;
# 50;
$display("se carga 0011");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0011;
dir <= 1'bx;
# 50;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 50;
$display("se carga 1111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b1111;
dir <= 1'bx;
# 200
$display("---\nModo de Carga en Serie\n---");
$display("Hacia la izquierda");
$display("con s_in = 0");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b00;
dir <= 1'b0;
s_in <= 2'b0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1;
# 400
$display("Hacia la derecha");
$display("con s_in = 0");
@(posedge clk);
dir <= 1'b1;
s_in <= 0;
# 400
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 90
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 60
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b1;
# 40
$display("con s_in = 1");
@(posedge clk);
s_in <= 1'b0;
# 550;
@(posedge clk);
$display("Hacemos otra carga paralela antes de la rotacion circular");
# 60;
$display("se carga 0111");
@(posedge clk);
modo <= 2'b10;
d <= 4'b0111;
dir <= 1'bx;
# 200
$display("---\nModo de rotacion circular\n---");
$display("Hacia la izquierda");
@(posedge clk);
d <= 4'bzzzz;
modo <= 2'b01;
dir <= 1'b0;
# 400
$display("Hacia la derecha");
@(posedge clk);
dir <= 1'b1;
# 550;
@(posedge clk);
$display("------------------------------------------------------------------------------------------");
$display("## FIN COMPARACION DE SINTESIS SIN TIEMPOS DE RETRASO DE YOSYS Y DESCRIPCION CONDUCTUAL ##");
$display("------------------------------------------------------------------------------------------");
$display("Cantidad de diferencias totales: %d", contador);
$finish;
end
initial
begin
$dumpfile("tests/rdesplazante.vcd");
$dumpvars;
$display("------------------------------------");
$display("-- Test para modulo rdesplazante --");
$display("------------------------------------");
$display ("\t tiempo | enb | dir | s_in | modo | d | q | s_out | tiempo");
$monitor ("%t| %b | %b | %b | %b | %b | %b | %b | %f ns",
$time, enb, dir, s_in, modo, d, qc, s_outc , $realtime);
end
endmodule | 0 |
2,636 | data/full_repos/permissive/100554922/Clock/clockswitch_00/clock_switch_module.v | 100,554,922 | clock_switch_module.v | v | 95 | 82 | [] | [] | [] | null | line:16: before: "," | null | 1: b'%Error: data/full_repos/permissive/100554922/Clock/clockswitch_00/clock_switch_module.v:60: syntax error, unexpected always\nalways @ (negedge clkb or negedge rst_n) begin\n^~~~~~\n%Error: Exiting due to 1 error(s)\n' | 84 | module | module clock_switc_module(
input wire rst_n ,
input wire clka ,
input wire clkb ,
input wire sel_clkb ,
input wire clk_o
);
`ifdef USE_GATE_CELL
`define CLK_EDGE posedge
`else
`define CLK_EDGE negedge
`endif
reg sel_clka_d0 ;
reg sel_clka_d1 ;
reg sel_clka_dly1 ;
reg sel_clka_dly2 ;
reg sel_clka_dly3 ;
reg sel_clkb_d0 ;
reg sel_clkb_d1 ;
reg sel_clkb_dly1 ;
reg sel_clkb_dly2 ;
reg sel_clkb_dly3 ;
wire clka_g ;
wire clkb_g ;
always @ (`CLK_EDGE clka or negedge rst_n) begin
if (!rst_n) begin
sel_clka_d0 <= 1'b0;
sel_clka_d1 <= 1'b0;
end
else begin
sel_clka_d0 <= (~sel_clkb) & (~sel_clkb_dly3) ;
sel_clka_d1 <= sel_clka_d0 ;
end
end
always @ (`CLK_EDGE clka or negedge rst_n) begin
if (!rst_n) begin
sel_clka_dly1 <= 1'b0;
sel_clka_dly2 <= 1'b0;
sel_clka_dly3 <= 1'b0;
end
else begin
sel_clka_dly1 <= sel_clka_d1;
sel_clka_dly2 <= sel_clka_dly1 ;
sel_clka_dly3 <= sel_clka_dly2 ;
end
end
always @ (posedge clkb_n or negedge rst_n)
always @ (`CLK_EDGE clkb or negedge rst_n) begin
if (!rst_n) begin
sel_clkb_d0 <= 1'b0;
sel_clkb_d1 <= 1'b0;
end
else begin
sel_clkb_d0 <= sel_clkb & (~sel_clka_dly3) ;
sel_clkb_d1 <= sel_clkb_d0 ;
end
end
always @ (`CLK_EDGE clkb or negedge rst_n) begin
if (!rst_n) begin
sel_clkb_dly1 <= 1'b0;
sel_clkb_dly2 <= 1'b0;
sel_clkb_dly3 <= 1'b0;
end
else begin
sel_clkb_dly1 <= sel_clkb_d1 ;
sel_clkb_dly2 <= sel_clkb_dly1 ;
sel_clkb_dly3 <= sel_clkb_dly2 ;
end
end
`ifdef USE_GATE_CELL
clk_gate_xxx clk_gate_a ( .CP(clka), .EN(sel_clka_dly1), .Q(clka_g) .TE(1'b0) );
clk_gate_xxx clk_gate_b ( .CP(clkb), .EN(sel_clkb_dly1), .Q(clkb_g) .TE(1'b0) );
`else
assign clka_g = clka & sel_clka_dly1 ;
assign clkb_g = clkb & sel_clkb_dly1 ;
`endif
assign clk_o = clka_g | clkb_g ;
endmodule | module clock_switc_module(
input wire rst_n ,
input wire clka ,
input wire clkb ,
input wire sel_clkb ,
input wire clk_o
); |
`ifdef USE_GATE_CELL
`define CLK_EDGE posedge
`else
`define CLK_EDGE negedge
`endif
reg sel_clka_d0 ;
reg sel_clka_d1 ;
reg sel_clka_dly1 ;
reg sel_clka_dly2 ;
reg sel_clka_dly3 ;
reg sel_clkb_d0 ;
reg sel_clkb_d1 ;
reg sel_clkb_dly1 ;
reg sel_clkb_dly2 ;
reg sel_clkb_dly3 ;
wire clka_g ;
wire clkb_g ;
always @ (`CLK_EDGE clka or negedge rst_n) begin
if (!rst_n) begin
sel_clka_d0 <= 1'b0;
sel_clka_d1 <= 1'b0;
end
else begin
sel_clka_d0 <= (~sel_clkb) & (~sel_clkb_dly3) ;
sel_clka_d1 <= sel_clka_d0 ;
end
end
always @ (`CLK_EDGE clka or negedge rst_n) begin
if (!rst_n) begin
sel_clka_dly1 <= 1'b0;
sel_clka_dly2 <= 1'b0;
sel_clka_dly3 <= 1'b0;
end
else begin
sel_clka_dly1 <= sel_clka_d1;
sel_clka_dly2 <= sel_clka_dly1 ;
sel_clka_dly3 <= sel_clka_dly2 ;
end
end
always @ (posedge clkb_n or negedge rst_n)
always @ (`CLK_EDGE clkb or negedge rst_n) begin
if (!rst_n) begin
sel_clkb_d0 <= 1'b0;
sel_clkb_d1 <= 1'b0;
end
else begin
sel_clkb_d0 <= sel_clkb & (~sel_clka_dly3) ;
sel_clkb_d1 <= sel_clkb_d0 ;
end
end
always @ (`CLK_EDGE clkb or negedge rst_n) begin
if (!rst_n) begin
sel_clkb_dly1 <= 1'b0;
sel_clkb_dly2 <= 1'b0;
sel_clkb_dly3 <= 1'b0;
end
else begin
sel_clkb_dly1 <= sel_clkb_d1 ;
sel_clkb_dly2 <= sel_clkb_dly1 ;
sel_clkb_dly3 <= sel_clkb_dly2 ;
end
end
`ifdef USE_GATE_CELL
clk_gate_xxx clk_gate_a ( .CP(clka), .EN(sel_clka_dly1), .Q(clka_g) .TE(1'b0) );
clk_gate_xxx clk_gate_b ( .CP(clkb), .EN(sel_clkb_dly1), .Q(clkb_g) .TE(1'b0) );
`else
assign clka_g = clka & sel_clka_dly1 ;
assign clkb_g = clkb & sel_clkb_dly1 ;
`endif
assign clk_o = clka_g | clkb_g ;
endmodule | 1 |
2,640 | data/full_repos/permissive/100597706/rtl/regfile.v | 100,597,706 | regfile.v | v | 41 | 59 | [] | [] | [] | [(2, 40)] | null | data/verilator_xmls/877ac150-2ee6-4dfe-a9c9-0199ee3372b0.xml | null | 87 | module | module regFile(
input clk, rst,
input rfwr,
input [4:0] rfrd, rfrs1, rfrs2,
input [31:0] rfD,
output [31:0] rfRS1, rfRS2
,input simdone
);
reg[31:0] RF[31:0];
assign rfRS1 = RF[rfrs1];
assign rfRS2 = RF[rfrs2];
integer i;
initial begin
for(i=0; i<32; i=i+1)
RF[i] = 0;
end
always @(posedge clk)
if(!rst) begin
if(rfwr) begin
RF[rfrd] <= rfD;
`ifdef _DBUG_
$display("x%0d = \t0x%h -> %h",rfrd,RF[rfrd], rfD);
`endif
end
end
`ifdef _RDUMP_
always @ (posedge simdone)
for(i=0; i<32; i=i+1)
$display("x%0d: \t0x%h\t%0d",i,RF[i], $signed(RF[i]));
`endif
endmodule | module regFile(
input clk, rst,
input rfwr,
input [4:0] rfrd, rfrs1, rfrs2,
input [31:0] rfD,
output [31:0] rfRS1, rfRS2
,input simdone
); |
reg[31:0] RF[31:0];
assign rfRS1 = RF[rfrs1];
assign rfRS2 = RF[rfrs2];
integer i;
initial begin
for(i=0; i<32; i=i+1)
RF[i] = 0;
end
always @(posedge clk)
if(!rst) begin
if(rfwr) begin
RF[rfrd] <= rfD;
`ifdef _DBUG_
$display("x%0d = \t0x%h -> %h",rfrd,RF[rfrd], rfD);
`endif
end
end
`ifdef _RDUMP_
always @ (posedge simdone)
for(i=0; i<32; i=i+1)
$display("x%0d: \t0x%h\t%0d",i,RF[i], $signed(RF[i]));
`endif
endmodule | 5 |
2,663 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module cpu_tb_generic;
reg clk, rst;
wire[31:0] baddr, bdi, bdo;
wire bwr;
wire[1:0] bsz;
wire[4:0] rfrd, rfrs1, rfrs2;
wire rfwr;
wire[31:0] rfD;
wire[31:0] rfRS1, rfRS2;
wire simdone;
wire[31:0] extA, extB;
wire[31:0] extR;
wire extStart;
wire extDone;
wire[2:0] extFunc3;
wire brdy;
wire CS, CSM, CSQM;
wire IRQ;
wire [3:0] IRQnum;
wire [15:0] IRQen;
reg [15:0] INT;
assign CS = ~(CSM | CSQM);
assign brdy = (CS)? 1'b1 : 1'bz;
IntCtrl INTCU(
.clk(clk), .rst(rst),
.INT(INT), .IRQen(IRQen),
.IRQ(IRQ), .IRQnum(IRQnum)
);
rv32_CPU_v2 CPU(
.clk(clk),
.rst(rst),
.bdi(bdi), .bdo(bdo), .baddr(baddr), .bsz(bsz), .bwr(bwr),
.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
.brdy(brdy),
.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
.simdone(simdone)
);
m_wrapper #(12) M (
.clk(clk),
.baddr(baddr),
.bdi(bdi),
.bsz(bsz),
.bwr(bwr),
.bdo(bdo),
.brdy(brdy),
.CS(CSM)
);
qm_wrapper QM (
.clk(clk),
.rst(rst),
.baddr(baddr),
.bdi(bdi),
.bsz(bsz),
.bwr(bwr),
.bdo(bdo),
.brdy(brdy),
.CS(CSQM)
);
mul MULEXT (
.clk(clk),
.rst(rst),
.done(extDone),
.start(extStart),
.a(extA), .b(extB),
.p(extR)
);
regFile RF (.clk(clk), .rst(rst),
.rfwr(rfwr),
.rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
.rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)
,.simdone(simdone)
);
integer i;
initial begin clk = 0; end
always # 5 clk = ~ clk;
initial begin
rst = 0;
#50;
@(negedge clk);
rst = 1;
#50;
@(negedge clk);
rst = 0;
end
initial begin
INT = 16'd0;
#300 INT[4] = 1'b1;
#20 INT[4] = 1'b0;
#300 INT[14] = 1'b1;
#20 INT[14] = 1'b0;
end
`ifdef _DBUG_
always @ (posedge clk) begin
$display("baddr_tb = %h, brdy_tb: %b, CS_tb : %b, bdo_tb = %h", baddr, brdy, CS, bdo);
end
`endif
endmodule | module cpu_tb_generic; |
reg clk, rst;
wire[31:0] baddr, bdi, bdo;
wire bwr;
wire[1:0] bsz;
wire[4:0] rfrd, rfrs1, rfrs2;
wire rfwr;
wire[31:0] rfD;
wire[31:0] rfRS1, rfRS2;
wire simdone;
wire[31:0] extA, extB;
wire[31:0] extR;
wire extStart;
wire extDone;
wire[2:0] extFunc3;
wire brdy;
wire CS, CSM, CSQM;
wire IRQ;
wire [3:0] IRQnum;
wire [15:0] IRQen;
reg [15:0] INT;
assign CS = ~(CSM | CSQM);
assign brdy = (CS)? 1'b1 : 1'bz;
IntCtrl INTCU(
.clk(clk), .rst(rst),
.INT(INT), .IRQen(IRQen),
.IRQ(IRQ), .IRQnum(IRQnum)
);
rv32_CPU_v2 CPU(
.clk(clk),
.rst(rst),
.bdi(bdi), .bdo(bdo), .baddr(baddr), .bsz(bsz), .bwr(bwr),
.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
.brdy(brdy),
.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
.simdone(simdone)
);
m_wrapper #(12) M (
.clk(clk),
.baddr(baddr),
.bdi(bdi),
.bsz(bsz),
.bwr(bwr),
.bdo(bdo),
.brdy(brdy),
.CS(CSM)
);
qm_wrapper QM (
.clk(clk),
.rst(rst),
.baddr(baddr),
.bdi(bdi),
.bsz(bsz),
.bwr(bwr),
.bdo(bdo),
.brdy(brdy),
.CS(CSQM)
);
mul MULEXT (
.clk(clk),
.rst(rst),
.done(extDone),
.start(extStart),
.a(extA), .b(extB),
.p(extR)
);
regFile RF (.clk(clk), .rst(rst),
.rfwr(rfwr),
.rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
.rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)
,.simdone(simdone)
);
integer i;
initial begin clk = 0; end
always # 5 clk = ~ clk;
initial begin
rst = 0;
#50;
@(negedge clk);
rst = 1;
#50;
@(negedge clk);
rst = 0;
end
initial begin
INT = 16'd0;
#300 INT[4] = 1'b1;
#20 INT[4] = 1'b0;
#300 INT[14] = 1'b1;
#20 INT[14] = 1'b0;
end
`ifdef _DBUG_
always @ (posedge clk) begin
$display("baddr_tb = %h, brdy_tb: %b, CS_tb : %b, bdo_tb = %h", baddr, brdy, CS, bdo);
end
`endif
endmodule | 5 |
2,664 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module m_wrapper #(parameter logHBank = 10) (
input clk,
input [31:0] baddr,
input [31:0] bdi,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
output brdy,
output CS
);
wire [31:0] bdo_m;
wire brdy_m;
`ifdef _DBUG_
always @ (posedge clk)begin
$display("baddr_m: %h, CSM = %b, bdo_m = %h, brdy_m = %b", baddr, CS, bdo_m, brdy_m);
end
`endif
assign CS = (baddr[31:logHBank+2] == 0);
wire mwr = CS & bwr;
memory #(logHBank) M (.clk(clk), .bdi(bdi), .baddr(baddr), .bdo(bdo_m), .mwr(mwr), .bsz(bsz), .brdy(brdy_m));
assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
assign brdy = CS? brdy_m : 1'bz;
endmodule | module m_wrapper #(parameter logHBank = 10) (
input clk,
input [31:0] baddr,
input [31:0] bdi,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
output brdy,
output CS
); |
wire [31:0] bdo_m;
wire brdy_m;
`ifdef _DBUG_
always @ (posedge clk)begin
$display("baddr_m: %h, CSM = %b, bdo_m = %h, brdy_m = %b", baddr, CS, bdo_m, brdy_m);
end
`endif
assign CS = (baddr[31:logHBank+2] == 0);
wire mwr = CS & bwr;
memory #(logHBank) M (.clk(clk), .bdi(bdi), .baddr(baddr), .bdo(bdo_m), .mwr(mwr), .bsz(bsz), .brdy(brdy_m));
assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
assign brdy = CS? brdy_m : 1'bz;
endmodule | 5 |
2,665 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module qm_wrapper (
input clk,
input rst,
input [31:0] baddr,
input [31:0] bdi,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
output brdy,
output CS
);
wire [31:0] bdo_m;
wire brdy_m;
assign CS = (baddr[31:28] == 4'hf);
wire mwr = CS & bwr;
rom_qspi rq (
.clk(clk), .rst(rst),
.baddr(baddr[23:0]),
.bsz(2'b0),
.trigger_rd(CS),
.bdo(bdo_m),
.brdy(brdy_m)
);
assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
assign brdy = CS? brdy_m : 1'bz;
`ifdef _DBUG_
always @ (posedge clk) begin
$display("baddr_qm: %h, CSQM = %b, bdo_qm = %h, brdy_qm = %b", baddr, CS, bdo_m, brdy_m);
end
`endif
endmodule | module qm_wrapper (
input clk,
input rst,
input [31:0] baddr,
input [31:0] bdi,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
output brdy,
output CS
); |
wire [31:0] bdo_m;
wire brdy_m;
assign CS = (baddr[31:28] == 4'hf);
wire mwr = CS & bwr;
rom_qspi rq (
.clk(clk), .rst(rst),
.baddr(baddr[23:0]),
.bsz(2'b0),
.trigger_rd(CS),
.bdo(bdo_m),
.brdy(brdy_m)
);
assign bdo = CS? bdo_m : 32'hZZZZZZZZ;
assign brdy = CS? brdy_m : 1'bz;
`ifdef _DBUG_
always @ (posedge clk) begin
$display("baddr_qm: %h, CSQM = %b, bdo_qm = %h, brdy_qm = %b", baddr, CS, bdo_m, brdy_m);
end
`endif
endmodule | 5 |
2,666 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module io_wrapper #(parameter targ_addr = 32'h80000000) (
input clk, rst,
input [31:0] baddr,
input [31:0] bdi,
input [31:0] bdi_m,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
input brdy_m,
output brdy,
output CS
);
reg [31:0] ioreg;
assign CS = (targ_addr == baddr);
wire mwr = CS & bwr;
always @ (posedge clk) begin
if (rst)
ioreg <= 32'b0;
else if (mwr)
ioreg <= bdi;
else if (brdy_m)
ioreg <= bdi_m;
end
assign bdo = CS? (brdy_m ? bdi_m : ioreg) : 32'hZZZZZZZZ;
assign brdy = CS? 1'b1 : 1'bz;
endmodule | module io_wrapper #(parameter targ_addr = 32'h80000000) (
input clk, rst,
input [31:0] baddr,
input [31:0] bdi,
input [31:0] bdi_m,
input [1:0] bsz,
input bwr,
output [31:0] bdo,
input brdy_m,
output brdy,
output CS
); |
reg [31:0] ioreg;
assign CS = (targ_addr == baddr);
wire mwr = CS & bwr;
always @ (posedge clk) begin
if (rst)
ioreg <= 32'b0;
else if (mwr)
ioreg <= bdi;
else if (brdy_m)
ioreg <= bdi_m;
end
assign bdo = CS? (brdy_m ? bdi_m : ioreg) : 32'hZZZZZZZZ;
assign brdy = CS? 1'b1 : 1'bz;
endmodule | 5 |
2,667 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module cpu_tb_ahbl;
localparam ioN = 1;
localparam selBitLn = 5;
reg HCLK, HRST;
initial begin HCLK = 0; end
always # 5 HCLK = ~ HCLK;
initial begin
HRST = 0;
#50;
@(negedge HCLK);
HRST = 1;
#50;
@(negedge HCLK);
HRST = 0;
$display("initialized");
end
wire [31:0] HADDR, HWDATA, HRDATA;
wire [1:0] HSIZE;
wire HREADY, HTRANS, HWRITE;
reg [15:0] INT;
AHBLMASTER AHBM (
.HCLK(HCLK), .HRST(HRST),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HADDR(HADDR),
.HSIZE(HSIZE),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HWRITE(HWRITE),
.INT(INT)
);
wire [0:2+ioN] HSEL;
AHBLDEC #(12, ioN) AHBLD (
.HADDR(HADDR),
.HSEL(HSEL)
);
wire [0:2+ioN] HREADYout;
wire [31:0] HRDATAout [0:2+ioN];
assign HREADYout[0] = 1'b1;
assign HRDATAout[0] = 32'h40404040;
AHBSLAVE_M #(12) M (
.HSEL(HSEL[1]),
.HCLK(HCLK),
.HRST(HRST),
.HREADY(HREADY),
.HADDR(HADDR),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HWDATA(HWDATA),
.HREADYout(HREADYout[1]),
.HRDATA(HRDATAout[1])
);
assign HREADYout[2] = 1'b1;
assign HRDATAout[2] = `INST_NOP;
AHBSLAVE_IO io1 (
.HSEL(HSEL[3]),
.HCLK(HCLK),
.HRST(HRST),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HSIZE(HSIZE),
.HWRITE(HWRITE),
.HREADY(HREADY),
.HREADYout(HREADYout[3]),
.HRDATA(HRDATAout[3])
);
reg [selBitLn-1:0] HREADY_sel, HRDATA_sel;
integer i;
always@ (posedge HCLK, posedge HRST) begin
if(HRST) begin
HREADY_sel <= 0;
HRDATA_sel <= 0;
end
else if(HREADY) begin
for (i = 0; i < 3+ioN; i = i + 1)
if (HSEL[i] & HTRANS) begin
HREADY_sel <= i[selBitLn-1:0];
HRDATA_sel <= i[selBitLn-1:0];
end
end
end
assign HREADY = HREADYout[HREADY_sel];
assign HRDATA = HRDATAout[HRDATA_sel];
`ifdef _DBUG_
always @ *
$display ("HRDATA_tb = %h", HRDATA);
always @ *
$display ("HRDATA_sel = %h", HRDATA_sel);
`endif
endmodule | module cpu_tb_ahbl; |
localparam ioN = 1;
localparam selBitLn = 5;
reg HCLK, HRST;
initial begin HCLK = 0; end
always # 5 HCLK = ~ HCLK;
initial begin
HRST = 0;
#50;
@(negedge HCLK);
HRST = 1;
#50;
@(negedge HCLK);
HRST = 0;
$display("initialized");
end
wire [31:0] HADDR, HWDATA, HRDATA;
wire [1:0] HSIZE;
wire HREADY, HTRANS, HWRITE;
reg [15:0] INT;
AHBLMASTER AHBM (
.HCLK(HCLK), .HRST(HRST),
.HRDATA(HRDATA),
.HREADY(HREADY),
.HADDR(HADDR),
.HSIZE(HSIZE),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HWRITE(HWRITE),
.INT(INT)
);
wire [0:2+ioN] HSEL;
AHBLDEC #(12, ioN) AHBLD (
.HADDR(HADDR),
.HSEL(HSEL)
);
wire [0:2+ioN] HREADYout;
wire [31:0] HRDATAout [0:2+ioN];
assign HREADYout[0] = 1'b1;
assign HRDATAout[0] = 32'h40404040;
AHBSLAVE_M #(12) M (
.HSEL(HSEL[1]),
.HCLK(HCLK),
.HRST(HRST),
.HREADY(HREADY),
.HADDR(HADDR),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HWDATA(HWDATA),
.HREADYout(HREADYout[1]),
.HRDATA(HRDATAout[1])
);
assign HREADYout[2] = 1'b1;
assign HRDATAout[2] = `INST_NOP;
AHBSLAVE_IO io1 (
.HSEL(HSEL[3]),
.HCLK(HCLK),
.HRST(HRST),
.HTRANS(HTRANS),
.HWDATA(HWDATA),
.HSIZE(HSIZE),
.HWRITE(HWRITE),
.HREADY(HREADY),
.HREADYout(HREADYout[3]),
.HRDATA(HRDATAout[3])
);
reg [selBitLn-1:0] HREADY_sel, HRDATA_sel;
integer i;
always@ (posedge HCLK, posedge HRST) begin
if(HRST) begin
HREADY_sel <= 0;
HRDATA_sel <= 0;
end
else if(HREADY) begin
for (i = 0; i < 3+ioN; i = i + 1)
if (HSEL[i] & HTRANS) begin
HREADY_sel <= i[selBitLn-1:0];
HRDATA_sel <= i[selBitLn-1:0];
end
end
end
assign HREADY = HREADYout[HREADY_sel];
assign HRDATA = HRDATAout[HRDATA_sel];
`ifdef _DBUG_
always @ *
$display ("HRDATA_tb = %h", HRDATA);
always @ *
$display ("HRDATA_sel = %h", HRDATA_sel);
`endif
endmodule | 5 |
2,668 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module AHBLMASTER (
input HCLK, HRST,
input [31:0] HRDATA,
input HREADY,
output [31:0] HADDR,
output [1:0] HSIZE,
output HTRANS,
output [31:0] HWDATA,
output HWRITE,
input [15:0] INT
);
localparam IDLE = 1'b0;
localparam NONSEQ = 1'b1;
localparam SZ_BYTE = 2'b00;
localparam SZ_HW = 2'b01;
localparam SZ_W = 2'b10;
wire[4:0] rfrd, rfrs1, rfrs2;
wire rfwr;
wire[31:0] rfD;
wire[31:0] rfRS1, rfRS2;
wire simdone;
wire[31:0] extA, extB;
wire[31:0] extR;
wire extStart;
wire extDone;
wire[2:0] extFunc3;
wire IRQ;
wire [3:0] IRQnum;
wire [15:0] IRQen;
rv32_CPU_v2 CPU(
.clk(HCLK),
.rst(HRST),
.bdi(HWDATA), .bdo(HRDATA), .baddr(HADDR), .bsz(HSIZE), .bwr(HWRITE),
.brdy(HREADY),
.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
.simdone(simdone)
);
assign HTRANS = NONSEQ;
IntCtrl INTCU(
.clk(HCLK), .rst(HRST),
.INT(INT), .IRQen(IRQen),
.IRQ(IRQ), .IRQnum(IRQnum)
);
mul MULEXT (
.clk(HCLK),
.rst(HRST),
.done(extDone),
.start(extStart),
.a(extA), .b(extB),
.p(extR)
);
regFile RF (.clk(HCLK), .rst(HRST),
.rfwr(rfwr),
.rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
.rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)
,.simdone(simdone)
);
endmodule | module AHBLMASTER (
input HCLK, HRST,
input [31:0] HRDATA,
input HREADY,
output [31:0] HADDR,
output [1:0] HSIZE,
output HTRANS,
output [31:0] HWDATA,
output HWRITE,
input [15:0] INT
); |
localparam IDLE = 1'b0;
localparam NONSEQ = 1'b1;
localparam SZ_BYTE = 2'b00;
localparam SZ_HW = 2'b01;
localparam SZ_W = 2'b10;
wire[4:0] rfrd, rfrs1, rfrs2;
wire rfwr;
wire[31:0] rfD;
wire[31:0] rfRS1, rfRS2;
wire simdone;
wire[31:0] extA, extB;
wire[31:0] extR;
wire extStart;
wire extDone;
wire[2:0] extFunc3;
wire IRQ;
wire [3:0] IRQnum;
wire [15:0] IRQen;
rv32_CPU_v2 CPU(
.clk(HCLK),
.rst(HRST),
.bdi(HWDATA), .bdo(HRDATA), .baddr(HADDR), .bsz(HSIZE), .bwr(HWRITE),
.brdy(HREADY),
.rfwr(rfwr), .rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2), .rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2),
.extA(extA), .extB(extB), .extR(extR), .extStart(extStart), .extDone(extDone), .extFunc3(extFunc3),
.IRQ(IRQ), .IRQnum(IRQnum), .IRQen(IRQen),
.simdone(simdone)
);
assign HTRANS = NONSEQ;
IntCtrl INTCU(
.clk(HCLK), .rst(HRST),
.INT(INT), .IRQen(IRQen),
.IRQ(IRQ), .IRQnum(IRQnum)
);
mul MULEXT (
.clk(HCLK),
.rst(HRST),
.done(extDone),
.start(extStart),
.a(extA), .b(extB),
.p(extR)
);
regFile RF (.clk(HCLK), .rst(HRST),
.rfwr(rfwr),
.rfrd(rfrd), .rfrs1(rfrs1), .rfrs2(rfrs2),
.rfD(rfD), .rfRS1(rfRS1), .rfRS2(rfRS2)
,.simdone(simdone)
);
endmodule | 5 |
2,669 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module AHBSLAVE_M #(parameter logHBank = 10)
(
input HSEL,
input HCLK,
input HRST,
input HREADY,
input [31:0] HADDR,
input HTRANS,
input HWRITE,
input [1:0] HSIZE,
input [31:0] HWDATA,
output HREADYout,
output [31:0] HRDATA
);
reg last_HSEL, last_HWRITE, last_HTRANS;
reg [31:0] last_HADDR;
reg [1:0] last_HSIZE;
always @(posedge HCLK, posedge HRST)
begin
if(HRST)
begin
last_HSEL <= 1'b0;
last_HWRITE <= 1'b0;
last_HTRANS <= 1'b1;
last_HADDR <= 32'd0;
last_HSIZE <= 2'b0;
end
else if(HREADY)
begin
last_HSEL <= HSEL;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
last_HADDR <= HADDR;
last_HSIZE <= HSIZE;
end
end
reg [31:0] baddr_buffer;
always @ (*)
if (last_HSEL)
baddr_buffer = last_HADDR;
memory #(logHBank) M (.clk(HCLK), .bdi(HWDATA), .baddr(baddr_buffer), .bdo(HRDATA), .mwr(last_HWRITE & last_HTRANS), .bsz(last_HSIZE), .brdy(HREADYout));
`ifdef _DBUG_
always @ *
$display("HRDATA_memory = %h", HRDATA);
always @ *
$display("baddr_buffer = %h", baddr_buffer);
always @ *
$display("last_HSEL = %h", last_HSEL);
`endif
endmodule | module AHBSLAVE_M #(parameter logHBank = 10)
(
input HSEL,
input HCLK,
input HRST,
input HREADY,
input [31:0] HADDR,
input HTRANS,
input HWRITE,
input [1:0] HSIZE,
input [31:0] HWDATA,
output HREADYout,
output [31:0] HRDATA
); |
reg last_HSEL, last_HWRITE, last_HTRANS;
reg [31:0] last_HADDR;
reg [1:0] last_HSIZE;
always @(posedge HCLK, posedge HRST)
begin
if(HRST)
begin
last_HSEL <= 1'b0;
last_HWRITE <= 1'b0;
last_HTRANS <= 1'b1;
last_HADDR <= 32'd0;
last_HSIZE <= 2'b0;
end
else if(HREADY)
begin
last_HSEL <= HSEL;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
last_HADDR <= HADDR;
last_HSIZE <= HSIZE;
end
end
reg [31:0] baddr_buffer;
always @ (*)
if (last_HSEL)
baddr_buffer = last_HADDR;
memory #(logHBank) M (.clk(HCLK), .bdi(HWDATA), .baddr(baddr_buffer), .bdo(HRDATA), .mwr(last_HWRITE & last_HTRANS), .bsz(last_HSIZE), .brdy(HREADYout));
`ifdef _DBUG_
always @ *
$display("HRDATA_memory = %h", HRDATA);
always @ *
$display("baddr_buffer = %h", baddr_buffer);
always @ *
$display("last_HSEL = %h", last_HSEL);
`endif
endmodule | 5 |
2,670 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module AHBSLAVE_IO (
input HSEL,
input HCLK,
input HRST,
input HTRANS,
input [31:0] HWDATA,
input [1:0] HSIZE,
input HWRITE,
input HREADY,
output HREADYout,
output [31:0] HRDATA,
output reg [4:0] strg
);
reg last_HSEL;
reg last_HWRITE;
reg last_HTRANS;
always@ (posedge HCLK)
begin
if(HREADY)
begin
last_HSEL <= HSEL;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
always@ (posedge HCLK, posedge HRST)
begin
if(HRST)
strg <= 4'd0;
else if(last_HSEL & last_HWRITE & last_HTRANS)
strg <= HWDATA[4:0];
end
assign HREADYout = 1'b1;
assign HRDATA = strg;
endmodule | module AHBSLAVE_IO (
input HSEL,
input HCLK,
input HRST,
input HTRANS,
input [31:0] HWDATA,
input [1:0] HSIZE,
input HWRITE,
input HREADY,
output HREADYout,
output [31:0] HRDATA,
output reg [4:0] strg
); |
reg last_HSEL;
reg last_HWRITE;
reg last_HTRANS;
always@ (posedge HCLK)
begin
if(HREADY)
begin
last_HSEL <= HSEL;
last_HWRITE <= HWRITE;
last_HTRANS <= HTRANS;
end
end
always@ (posedge HCLK, posedge HRST)
begin
if(HRST)
strg <= 4'd0;
else if(last_HSEL & last_HWRITE & last_HTRANS)
strg <= HWDATA[4:0];
end
assign HREADYout = 1'b1;
assign HRDATA = strg;
endmodule | 5 |
2,671 | data/full_repos/permissive/100597706/testing/testbench.v | 100,597,706 | testbench.v | v | 644 | 156 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:128: Unsupported: Ignoring delay on this delayed statement.\n always # 5 clk = ~ clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:132: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:133: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/100597706/testing/testbench.v:136: syntax error, unexpected \'@\'\n @(negedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:143: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[4] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:144: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[4] = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n #300 INT[14] = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100597706/testing/testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #20 INT[14] = 1\'b0;\n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 96 | module | module AHBLDEC #(parameter logHBank = 10, parameter ioN = 1) (
input [31:0] HADDR,
output reg [0:2+ioN] HSEL
);
reg [0:1+ioN] HSEL_wo_def;
integer i;
always @ * begin
HSEL_wo_def[0] = (HADDR[31:logHBank+2] == 0);
HSEL_wo_def[1] = (HADDR[31:28] == 4'hf);
for (i = 0; i < ioN; i = i + 1)
HSEL_wo_def[i+2] = (HADDR == {28'h8000000, i[3:0]});
if (HSEL_wo_def == 0)
HSEL = {1'b1, HSEL_wo_def};
else
HSEL = {1'b0, HSEL_wo_def};
end
endmodule | module AHBLDEC #(parameter logHBank = 10, parameter ioN = 1) (
input [31:0] HADDR,
output reg [0:2+ioN] HSEL
); |
reg [0:1+ioN] HSEL_wo_def;
integer i;
always @ * begin
HSEL_wo_def[0] = (HADDR[31:logHBank+2] == 0);
HSEL_wo_def[1] = (HADDR[31:28] == 4'hf);
for (i = 0; i < ioN; i = i + 1)
HSEL_wo_def[i+2] = (HADDR == {28'h8000000, i[3:0]});
if (HSEL_wo_def == 0)
HSEL = {1'b1, HSEL_wo_def};
else
HSEL = {1'b0, HSEL_wo_def};
end
endmodule | 5 |
2,673 | data/full_repos/permissive/100638358/leds.v | 100,638,358 | leds.v | v | 36 | 88 | [] | [] | [] | [(1, 36)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:10: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'soma\' generates 4 bits.\n : ... In instance top\n counter<= counter+soma;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:23: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh14\' generates 32 or 5 bits.\n : ... In instance top\n soma=20;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100638358/leds.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh1e\' generates 32 or 5 bits.\n : ... In instance top\n soma=30;\n ^\n%Error: Exiting due to 3 warning(s)\n' | 98 | module | module top(input CLOCK_50, input [3:0]SW, output reg [7:0]LEDR, output reg [0:0]LEDG);
reg[31:0] counter;
reg[3:0] soma=1;
always @(posedge CLOCK_50)
begin
if(counter<=50000000)
begin
counter<= counter+soma;
end
else
begin
counter<=0;
LEDR[0]<=~LEDR[0];
end
if(SW[0]==1)
begin
soma=10;
end
if(SW[1]==1)
begin
soma=20;
end
if(SW[2]==1)
begin
soma=30;
end
if(counter == 25000000)
begin
LEDG <=~LEDG;
end
end
endmodule | module top(input CLOCK_50, input [3:0]SW, output reg [7:0]LEDR, output reg [0:0]LEDG); |
reg[31:0] counter;
reg[3:0] soma=1;
always @(posedge CLOCK_50)
begin
if(counter<=50000000)
begin
counter<= counter+soma;
end
else
begin
counter<=0;
LEDR[0]<=~LEDR[0];
end
if(SW[0]==1)
begin
soma=10;
end
if(SW[1]==1)
begin
soma=20;
end
if(SW[2]==1)
begin
soma=30;
end
if(counter == 25000000)
begin
LEDG <=~LEDG;
end
end
endmodule | 0 |
2,674 | data/full_repos/permissive/100638358/trab04emilio.v | 100,638,358 | trab04emilio.v | v | 55 | 85 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/112e11da-e544-430f-88cc-84fe7552ec29.xml | null | 99 | module | module triangulo(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS);
reg signed [25:0] cx = 0;
reg signed [25:0] cy = 0;
reg signed [25:0] p1_x = 300;
reg signed [25:0] p1_y = 100;
reg signed [25:0] p2_x = 400;
reg signed [25:0] p2_y = 300;
reg signed [25:0] p3_x = 600;
reg signed [25:0] p3_y = 200;
assign VGA_R = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_G = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_B = v ? (tr ? 4'hc : 4'h0) : 4'b0;
wire v = (cx >= 285) & (cx < 1555) & (cy >= 35) & (cy < 515);
wire tr = ((p2_x - p1_x) * (cy - p1_y) -(cx - p1_x) * (p2_y - p1_y)) <= 0 &&
((p3_x - p2_x) * (cy - p2_y) -(cx - p2_x) * (p3_y - p2_y)) <= 0 &&
((p1_x - p3_x) * (cy - p3_y) -(cx - p3_x) * (p1_y - p3_y)) <= 0;
reg [10:0] c = 10;
assign VGA_HS = cx >= 190;
assign VGA_VS = cy >= 2;
always @(posedge CLOCK_50) begin
if (cx == 1585)
begin
if (cy == 525) begin
cy <= 0;
end
else
cy <= cy + 1;
cx <= 0;
end
else
begin
cx <= cx + 1;
end
end
endmodule | module triangulo(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS); |
reg signed [25:0] cx = 0;
reg signed [25:0] cy = 0;
reg signed [25:0] p1_x = 300;
reg signed [25:0] p1_y = 100;
reg signed [25:0] p2_x = 400;
reg signed [25:0] p2_y = 300;
reg signed [25:0] p3_x = 600;
reg signed [25:0] p3_y = 200;
assign VGA_R = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_G = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_B = v ? (tr ? 4'hc : 4'h0) : 4'b0;
wire v = (cx >= 285) & (cx < 1555) & (cy >= 35) & (cy < 515);
wire tr = ((p2_x - p1_x) * (cy - p1_y) -(cx - p1_x) * (p2_y - p1_y)) <= 0 &&
((p3_x - p2_x) * (cy - p2_y) -(cx - p2_x) * (p3_y - p2_y)) <= 0 &&
((p1_x - p3_x) * (cy - p3_y) -(cx - p3_x) * (p1_y - p3_y)) <= 0;
reg [10:0] c = 10;
assign VGA_HS = cx >= 190;
assign VGA_VS = cy >= 2;
always @(posedge CLOCK_50) begin
if (cx == 1585)
begin
if (cy == 525) begin
cy <= 0;
end
else
cy <= cy + 1;
cx <= 0;
end
else
begin
cx <= cx + 1;
end
end
endmodule | 0 |
2,675 | data/full_repos/permissive/100638358/trab05emilio.v | 100,638,358 | trab05emilio.v | v | 93 | 90 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/9da377f6-f20a-414e-b5e3-e19afd8c7743.xml | null | 100 | module | module triangulov2(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS);
reg signed [23:0] cx = 0;
reg signed [23:0] cy = 0;
reg signed [23:0] p1_x = 300;
reg signed [23:0] p1_y = 100;
reg signed [23:0] p2_x = 400;
reg signed [23:0] p2_y = 300;
reg signed [23:0] p3_x = 600;
reg signed [23:0] p3_y = 200;
reg [28:0] cont = 0;
reg [1:0] cc = 0;
assign VGA_R = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_G = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_B = v ? (tr ? 4'hc : 4'h0) : 4'b0;
wire v = (cx >= 285) & (cx < 1555) & (cy >= 35) & (cy < 515);
wire tr = ((p2_x - p1_x) * (cy - p1_y) -(cx - p1_x) * (p2_y - p1_y)) <= 0 &&
((p3_x - p2_x) * (cy - p2_y) -(cx - p2_x) * (p3_y - p2_y)) <= 0 &&
((p1_x - p3_x) * (cy - p3_y) -(cx - p3_x) * (p1_y - p3_y)) <= 0;
reg [10:0] c = 10;
assign VGA_HS = cx >= 190;
assign VGA_VS = cy >= 2;
always @(posedge CLOCK_50) begin
cont = cont + 1;
if(cont == 35000000) begin
cc = cc + 1;
cont = 0;
end
if(cc == 0) begin
p1_x = 300;
p1_y = 100;
p2_x = 400;
p2_y = 300;
p3_x = 600;
p3_y = 200;
end
else if(cc == 1) begin
p1_x = 300;
p1_y = 100;
p2_x = 600;
p2_y = 400;
p3_x = 800;
p3_y = 350;
end
else if(cc == 2) begin
p1_x = 300;
p1_y = 100;
p2_x = 1000;
p2_y = 500;
p3_x = 1400;
p3_y = 300;
end
else if(cc == 3) begin
p1_x = 300;
p1_y = 100;
p2_x = 1000;
p2_y = 500;
p3_x = 1400;
p3_y = 100;
end
if (cx == 1585)
begin
if (cy == 525) begin
cy <= 0;
end
else
cy <= cy + 1;
cx <= 0;
end
else
begin
cx <= cx + 1;
end
end
endmodule | module triangulov2(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS); |
reg signed [23:0] cx = 0;
reg signed [23:0] cy = 0;
reg signed [23:0] p1_x = 300;
reg signed [23:0] p1_y = 100;
reg signed [23:0] p2_x = 400;
reg signed [23:0] p2_y = 300;
reg signed [23:0] p3_x = 600;
reg signed [23:0] p3_y = 200;
reg [28:0] cont = 0;
reg [1:0] cc = 0;
assign VGA_R = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_G = v ? (tr ? 4'hc : 4'h0) : 4'b0;
assign VGA_B = v ? (tr ? 4'hc : 4'h0) : 4'b0;
wire v = (cx >= 285) & (cx < 1555) & (cy >= 35) & (cy < 515);
wire tr = ((p2_x - p1_x) * (cy - p1_y) -(cx - p1_x) * (p2_y - p1_y)) <= 0 &&
((p3_x - p2_x) * (cy - p2_y) -(cx - p2_x) * (p3_y - p2_y)) <= 0 &&
((p1_x - p3_x) * (cy - p3_y) -(cx - p3_x) * (p1_y - p3_y)) <= 0;
reg [10:0] c = 10;
assign VGA_HS = cx >= 190;
assign VGA_VS = cy >= 2;
always @(posedge CLOCK_50) begin
cont = cont + 1;
if(cont == 35000000) begin
cc = cc + 1;
cont = 0;
end
if(cc == 0) begin
p1_x = 300;
p1_y = 100;
p2_x = 400;
p2_y = 300;
p3_x = 600;
p3_y = 200;
end
else if(cc == 1) begin
p1_x = 300;
p1_y = 100;
p2_x = 600;
p2_y = 400;
p3_x = 800;
p3_y = 350;
end
else if(cc == 2) begin
p1_x = 300;
p1_y = 100;
p2_x = 1000;
p2_y = 500;
p3_x = 1400;
p3_y = 300;
end
else if(cc == 3) begin
p1_x = 300;
p1_y = 100;
p2_x = 1000;
p2_y = 500;
p3_x = 1400;
p3_y = 100;
end
if (cx == 1585)
begin
if (cy == 525) begin
cy <= 0;
end
else
cy <= cy + 1;
cx <= 0;
end
else
begin
cx <= cx + 1;
end
end
endmodule | 0 |
2,676 | data/full_repos/permissive/100638358/TRAB3_triangulo02.v | 100,638,358 | TRAB3_triangulo02.v | v | 71 | 68 | [] | [] | [] | null | line:69: before: "$" | null | 1: b'%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:22: syntax error, unexpected inside, expecting \'[\'\n output inside\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:27: syntax error, unexpected assign\n assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:38: syntax error, unexpected inside, expecting IDENTIFIER or do or final\n wire inside;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:40: syntax error, unexpected inside, expecting \')\'\n TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:62: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:68: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n' | 101 | module | module sign (
input [11:0] X1, Y1, X2, Y2, X4, Y,
output sign
);
wire signed [11:0] Sub1, Sub2, Sub3, Sub4;
wire signed [22:0] Mult1, Mult2, Sub5;
assign Sub1 = X4 - Y2;
assign Sub2 = Y1 - Y2;
assign Sub3 = Y1 - X2;
assign Sub4 = Y - Y2;
assign Mult1 = Sub1 * Sub2;
assign Mult2 = Sub3 * Sub4;
assign Sub5 = Mult1 - Mult2;
assign sign = (Sub5 >= 0) ? 1 : 0;
endmodule | module sign (
input [11:0] X1, Y1, X2, Y2, X4, Y,
output sign
); |
wire signed [11:0] Sub1, Sub2, Sub3, Sub4;
wire signed [22:0] Mult1, Mult2, Sub5;
assign Sub1 = X4 - Y2;
assign Sub2 = Y1 - Y2;
assign Sub3 = Y1 - X2;
assign Sub4 = Y - Y2;
assign Mult1 = Sub1 * Sub2;
assign Mult2 = Sub3 * Sub4;
assign Sub5 = Mult1 - Mult2;
assign sign = (Sub5 >= 0) ? 1 : 0;
endmodule | 0 |
2,677 | data/full_repos/permissive/100638358/TRAB3_triangulo02.v | 100,638,358 | TRAB3_triangulo02.v | v | 71 | 68 | [] | [] | [] | null | line:69: before: "$" | null | 1: b'%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:22: syntax error, unexpected inside, expecting \'[\'\n output inside\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:27: syntax error, unexpected assign\n assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:38: syntax error, unexpected inside, expecting IDENTIFIER or do or final\n wire inside;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:40: syntax error, unexpected inside, expecting \')\'\n TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:62: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:68: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n' | 101 | module | module TestTriangle (
input [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y,
output inside
);
wire sign1, sign2, sign3;
assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;
sign out1(X1, Y1, X2, Y2, X4, Y, sign1);
sign out2(X2, Y2, X3, Y3, X4, Y, sign2);
sign out3(X3, Y3, X1, Y1, X4, Y, sign3);
endmodule | module TestTriangle (
input [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y,
output inside
); |
wire sign1, sign2, sign3;
assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;
sign out1(X1, Y1, X2, Y2, X4, Y, sign1);
sign out2(X2, Y2, X3, Y3, X4, Y, sign2);
sign out3(X3, Y3, X1, Y1, X4, Y, sign3);
endmodule | 0 |
2,678 | data/full_repos/permissive/100638358/TRAB3_triangulo02.v | 100,638,358 | TRAB3_triangulo02.v | v | 71 | 68 | [] | [] | [] | null | line:69: before: "$" | null | 1: b'%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:22: syntax error, unexpected inside, expecting \'[\'\n output inside\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:27: syntax error, unexpected assign\n assign inside = (sign1 == 1 && sign2 == 1 && sign3 == 1) ? 1:0;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:38: syntax error, unexpected inside, expecting IDENTIFIER or do or final\n wire inside;\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:40: syntax error, unexpected inside, expecting \')\'\n TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);\n ^~~~~~\n%Error: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,A);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:45: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:56: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:62: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100638358/TRAB3_triangulo02.v:68: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n' | 101 | module | module Test;
reg [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y;
wire inside;
TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);
initial
begin
$dumpvars(0,A);
#1
X1 <= 10;
Y1 <= 10;
X2 <= 30;
Y2 <= 10;
X3 <= 20;
Y3 <= 30;
X4 <= 15;
Y <= 15;
#1
X4 <= 15;
Y <= 15;
#1
X4 <= 9;
Y <= 15;
#1
X4 <= 10;
Y <= 11;
#1
X4 <= 30;
Y <= 11;
#40
$finish;
end
endmodule | module Test; |
reg [11:0] X1, Y1, X2, Y2, X3, Y3, X4, Y;
wire inside;
TestTriangle A(X1, Y1, X2, Y2, X3, Y3, X4, Y, inside);
initial
begin
$dumpvars(0,A);
#1
X1 <= 10;
Y1 <= 10;
X2 <= 30;
Y2 <= 10;
X3 <= 20;
Y3 <= 30;
X4 <= 15;
Y <= 15;
#1
X4 <= 15;
Y <= 15;
#1
X4 <= 9;
Y <= 15;
#1
X4 <= 10;
Y <= 11;
#1
X4 <= 30;
Y <= 11;
#40
$finish;
end
endmodule | 0 |
2,684 | data/full_repos/permissive/100752663/src/mod_hex_display.v | 100,752,663 | mod_hex_display.v | v | 224 | 74 | [] | [] | [] | [(4, 223)] | null | data/verilator_xmls/827abf76-275e-4ac6-9434-27f0ee654729.xml | null | 107 | module | module mod_hex_display(
input in_pix_clk,
input [9:0] in_pix_x,
input [9:0] in_pix_y,
input in_latch,
input [7:0] in_data0,
input [7:0] in_data1,
input [7:0] in_data2,
input [7:0] in_data3,
input [7:0] in_data4,
input [7:0] in_data5,
input [7:0] in_data6,
input [7:0] in_data7,
input [7:0] in_pixel_r,
input [7:0] in_pixel_g,
input [7:0] in_pixel_b,
output [7:0] out_pixel_r,
output [7:0] out_pixel_g,
output [7:0] out_pixel_b
);
reg [7:0] font_data[127:0];
initial begin
font_data[ 0] <= { 8'b00000000 };
font_data[ 1] <= { 8'b00111100 };
font_data[ 2] <= { 8'b01000010 };
font_data[ 3] <= { 8'b01000010 };
font_data[ 4] <= { 8'b01000010 };
font_data[ 5] <= { 8'b01000010 };
font_data[ 6] <= { 8'b00111100 };
font_data[ 7] <= { 8'b00000000 };
font_data[ 8] <= { 8'b00000000 };
font_data[ 9] <= { 8'b00001000 };
font_data[ 10] <= { 8'b00011000 };
font_data[ 11] <= { 8'b00001000 };
font_data[ 12] <= { 8'b00001000 };
font_data[ 13] <= { 8'b00001000 };
font_data[ 14] <= { 8'b00011100 };
font_data[ 15] <= { 8'b00000000 };
font_data[ 16] <= { 8'b00000000 };
font_data[ 17] <= { 8'b00111100 };
font_data[ 18] <= { 8'b01000010 };
font_data[ 19] <= { 8'b00000100 };
font_data[ 20] <= { 8'b00011000 };
font_data[ 21] <= { 8'b00100000 };
font_data[ 22] <= { 8'b01111110 };
font_data[ 23] <= { 8'b00000000 };
font_data[ 24] <= { 8'b00000000 };
font_data[ 25] <= { 8'b00111100 };
font_data[ 26] <= { 8'b01000010 };
font_data[ 27] <= { 8'b00001100 };
font_data[ 28] <= { 8'b00000010 };
font_data[ 29] <= { 8'b01000010 };
font_data[ 30] <= { 8'b00111100 };
font_data[ 31] <= { 8'b00000000 };
font_data[ 32] <= { 8'b00000000 };
font_data[ 33] <= { 8'b00000100 };
font_data[ 34] <= { 8'b00001100 };
font_data[ 35] <= { 8'b00010100 };
font_data[ 36] <= { 8'b00100100 };
font_data[ 37] <= { 8'b00111110 };
font_data[ 38] <= { 8'b00000100 };
font_data[ 39] <= { 8'b00000000 };
font_data[ 40] <= { 8'b00000000 };
font_data[ 41] <= { 8'b01111110 };
font_data[ 42] <= { 8'b01000000 };
font_data[ 43] <= { 8'b01111100 };
font_data[ 44] <= { 8'b00000010 };
font_data[ 45] <= { 8'b01000010 };
font_data[ 46] <= { 8'b00111100 };
font_data[ 47] <= { 8'b00000000 };
font_data[ 48] <= { 8'b00000000 };
font_data[ 49] <= { 8'b00111100 };
font_data[ 50] <= { 8'b01000000 };
font_data[ 51] <= { 8'b01111100 };
font_data[ 52] <= { 8'b01000010 };
font_data[ 53] <= { 8'b01000010 };
font_data[ 54] <= { 8'b00111100 };
font_data[ 55] <= { 8'b00000000 };
font_data[ 56] <= { 8'b00000000 };
font_data[ 57] <= { 8'b01111110 };
font_data[ 58] <= { 8'b00000100 };
font_data[ 59] <= { 8'b00001000 };
font_data[ 60] <= { 8'b00010000 };
font_data[ 61] <= { 8'b00100000 };
font_data[ 62] <= { 8'b01000000 };
font_data[ 63] <= { 8'b00000000 };
font_data[ 64] <= { 8'b00000000 };
font_data[ 65] <= { 8'b00111100 };
font_data[ 66] <= { 8'b01000010 };
font_data[ 67] <= { 8'b00111100 };
font_data[ 68] <= { 8'b01000010 };
font_data[ 69] <= { 8'b01000010 };
font_data[ 70] <= { 8'b00111100 };
font_data[ 71] <= { 8'b00000000 };
font_data[ 72] <= { 8'b00000000 };
font_data[ 73] <= { 8'b00111100 };
font_data[ 74] <= { 8'b01000010 };
font_data[ 75] <= { 8'b01000010 };
font_data[ 76] <= { 8'b00111110 };
font_data[ 77] <= { 8'b00000010 };
font_data[ 78] <= { 8'b00111100 };
font_data[ 79] <= { 8'b00000000 };
font_data[ 80] <= { 8'b00000000 };
font_data[ 81] <= { 8'b00111100 };
font_data[ 82] <= { 8'b01000010 };
font_data[ 83] <= { 8'b01111110 };
font_data[ 84] <= { 8'b01000010 };
font_data[ 85] <= { 8'b01000010 };
font_data[ 86] <= { 8'b01000010 };
font_data[ 87] <= { 8'b00000000 };
font_data[ 88] <= { 8'b00000000 };
font_data[ 89] <= { 8'b01111100 };
font_data[ 90] <= { 8'b01000010 };
font_data[ 91] <= { 8'b01111100 };
font_data[ 92] <= { 8'b01000010 };
font_data[ 93] <= { 8'b01000010 };
font_data[ 94] <= { 8'b01111100 };
font_data[ 95] <= { 8'b00000000 };
font_data[ 96] <= { 8'b00000000 };
font_data[ 97] <= { 8'b00011100 };
font_data[ 98] <= { 8'b00100010 };
font_data[ 99] <= { 8'b01000000 };
font_data[100] <= { 8'b01000000 };
font_data[101] <= { 8'b00100010 };
font_data[102] <= { 8'b00011100 };
font_data[103] <= { 8'b00000000 };
font_data[104] <= { 8'b00000000 };
font_data[105] <= { 8'b01111100 };
font_data[106] <= { 8'b01000010 };
font_data[107] <= { 8'b01000010 };
font_data[108] <= { 8'b01000010 };
font_data[109] <= { 8'b01000010 };
font_data[110] <= { 8'b01111100 };
font_data[111] <= { 8'b00000000 };
font_data[112] <= { 8'b00000000 };
font_data[113] <= { 8'b01111110 };
font_data[114] <= { 8'b01000000 };
font_data[115] <= { 8'b01111100 };
font_data[116] <= { 8'b01000000 };
font_data[117] <= { 8'b01000000 };
font_data[118] <= { 8'b01111110 };
font_data[119] <= { 8'b00000000 };
font_data[120] <= { 8'b00000000 };
font_data[121] <= { 8'b01111110 };
font_data[122] <= { 8'b01000000 };
font_data[123] <= { 8'b01111100 };
font_data[124] <= { 8'b01000000 };
font_data[125] <= { 8'b01000000 };
font_data[126] <= { 8'b01000000 };
font_data[127] <= { 8'b00000000 };
end
parameter N_NIBBLES = 16;
reg[3:0] data[N_NIBBLES-1:0];
always @(posedge in_latch) begin
data[0] <= in_data0[7:4];
data[1] <= in_data0[3:0];
data[2] <= in_data1[7:4];
data[3] <= in_data1[3:0];
data[4] <= in_data2[7:4];
data[5] <= in_data2[3:0];
data[6] <= in_data3[7:4];
data[7] <= in_data3[3:0];
data[8] <= in_data4[7:4];
data[9] <= in_data4[3:0];
data[10] <= in_data5[7:4];
data[11] <= in_data5[3:0];
data[12] <= in_data6[7:4];
data[13] <= in_data6[3:0];
data[14] <= in_data7[7:4];
data[15] <= in_data7[3:0];
end
reg is_overlay;
wire is_pixel_active;
reg [7:0] scanline;
reg [2:0] scanline_x;
always @(posedge in_pix_clk) begin
scanline <= font_data[ { data[in_pix_x[6:3]], in_pix_y[2:0] } ];
scanline_x <= ~in_pix_x[2:0];
if (in_pix_y[9:4] == 0 && in_pix_y[3] == 1 && in_pix_x[9:7] == 0) begin
is_overlay <= 1;
end else begin
is_overlay <= 0;
end
end
assign is_pixel_active = scanline[scanline_x];
assign out_pixel_r = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_r;
assign out_pixel_g = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_g;
assign out_pixel_b = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_b;
endmodule | module mod_hex_display(
input in_pix_clk,
input [9:0] in_pix_x,
input [9:0] in_pix_y,
input in_latch,
input [7:0] in_data0,
input [7:0] in_data1,
input [7:0] in_data2,
input [7:0] in_data3,
input [7:0] in_data4,
input [7:0] in_data5,
input [7:0] in_data6,
input [7:0] in_data7,
input [7:0] in_pixel_r,
input [7:0] in_pixel_g,
input [7:0] in_pixel_b,
output [7:0] out_pixel_r,
output [7:0] out_pixel_g,
output [7:0] out_pixel_b
); |
reg [7:0] font_data[127:0];
initial begin
font_data[ 0] <= { 8'b00000000 };
font_data[ 1] <= { 8'b00111100 };
font_data[ 2] <= { 8'b01000010 };
font_data[ 3] <= { 8'b01000010 };
font_data[ 4] <= { 8'b01000010 };
font_data[ 5] <= { 8'b01000010 };
font_data[ 6] <= { 8'b00111100 };
font_data[ 7] <= { 8'b00000000 };
font_data[ 8] <= { 8'b00000000 };
font_data[ 9] <= { 8'b00001000 };
font_data[ 10] <= { 8'b00011000 };
font_data[ 11] <= { 8'b00001000 };
font_data[ 12] <= { 8'b00001000 };
font_data[ 13] <= { 8'b00001000 };
font_data[ 14] <= { 8'b00011100 };
font_data[ 15] <= { 8'b00000000 };
font_data[ 16] <= { 8'b00000000 };
font_data[ 17] <= { 8'b00111100 };
font_data[ 18] <= { 8'b01000010 };
font_data[ 19] <= { 8'b00000100 };
font_data[ 20] <= { 8'b00011000 };
font_data[ 21] <= { 8'b00100000 };
font_data[ 22] <= { 8'b01111110 };
font_data[ 23] <= { 8'b00000000 };
font_data[ 24] <= { 8'b00000000 };
font_data[ 25] <= { 8'b00111100 };
font_data[ 26] <= { 8'b01000010 };
font_data[ 27] <= { 8'b00001100 };
font_data[ 28] <= { 8'b00000010 };
font_data[ 29] <= { 8'b01000010 };
font_data[ 30] <= { 8'b00111100 };
font_data[ 31] <= { 8'b00000000 };
font_data[ 32] <= { 8'b00000000 };
font_data[ 33] <= { 8'b00000100 };
font_data[ 34] <= { 8'b00001100 };
font_data[ 35] <= { 8'b00010100 };
font_data[ 36] <= { 8'b00100100 };
font_data[ 37] <= { 8'b00111110 };
font_data[ 38] <= { 8'b00000100 };
font_data[ 39] <= { 8'b00000000 };
font_data[ 40] <= { 8'b00000000 };
font_data[ 41] <= { 8'b01111110 };
font_data[ 42] <= { 8'b01000000 };
font_data[ 43] <= { 8'b01111100 };
font_data[ 44] <= { 8'b00000010 };
font_data[ 45] <= { 8'b01000010 };
font_data[ 46] <= { 8'b00111100 };
font_data[ 47] <= { 8'b00000000 };
font_data[ 48] <= { 8'b00000000 };
font_data[ 49] <= { 8'b00111100 };
font_data[ 50] <= { 8'b01000000 };
font_data[ 51] <= { 8'b01111100 };
font_data[ 52] <= { 8'b01000010 };
font_data[ 53] <= { 8'b01000010 };
font_data[ 54] <= { 8'b00111100 };
font_data[ 55] <= { 8'b00000000 };
font_data[ 56] <= { 8'b00000000 };
font_data[ 57] <= { 8'b01111110 };
font_data[ 58] <= { 8'b00000100 };
font_data[ 59] <= { 8'b00001000 };
font_data[ 60] <= { 8'b00010000 };
font_data[ 61] <= { 8'b00100000 };
font_data[ 62] <= { 8'b01000000 };
font_data[ 63] <= { 8'b00000000 };
font_data[ 64] <= { 8'b00000000 };
font_data[ 65] <= { 8'b00111100 };
font_data[ 66] <= { 8'b01000010 };
font_data[ 67] <= { 8'b00111100 };
font_data[ 68] <= { 8'b01000010 };
font_data[ 69] <= { 8'b01000010 };
font_data[ 70] <= { 8'b00111100 };
font_data[ 71] <= { 8'b00000000 };
font_data[ 72] <= { 8'b00000000 };
font_data[ 73] <= { 8'b00111100 };
font_data[ 74] <= { 8'b01000010 };
font_data[ 75] <= { 8'b01000010 };
font_data[ 76] <= { 8'b00111110 };
font_data[ 77] <= { 8'b00000010 };
font_data[ 78] <= { 8'b00111100 };
font_data[ 79] <= { 8'b00000000 };
font_data[ 80] <= { 8'b00000000 };
font_data[ 81] <= { 8'b00111100 };
font_data[ 82] <= { 8'b01000010 };
font_data[ 83] <= { 8'b01111110 };
font_data[ 84] <= { 8'b01000010 };
font_data[ 85] <= { 8'b01000010 };
font_data[ 86] <= { 8'b01000010 };
font_data[ 87] <= { 8'b00000000 };
font_data[ 88] <= { 8'b00000000 };
font_data[ 89] <= { 8'b01111100 };
font_data[ 90] <= { 8'b01000010 };
font_data[ 91] <= { 8'b01111100 };
font_data[ 92] <= { 8'b01000010 };
font_data[ 93] <= { 8'b01000010 };
font_data[ 94] <= { 8'b01111100 };
font_data[ 95] <= { 8'b00000000 };
font_data[ 96] <= { 8'b00000000 };
font_data[ 97] <= { 8'b00011100 };
font_data[ 98] <= { 8'b00100010 };
font_data[ 99] <= { 8'b01000000 };
font_data[100] <= { 8'b01000000 };
font_data[101] <= { 8'b00100010 };
font_data[102] <= { 8'b00011100 };
font_data[103] <= { 8'b00000000 };
font_data[104] <= { 8'b00000000 };
font_data[105] <= { 8'b01111100 };
font_data[106] <= { 8'b01000010 };
font_data[107] <= { 8'b01000010 };
font_data[108] <= { 8'b01000010 };
font_data[109] <= { 8'b01000010 };
font_data[110] <= { 8'b01111100 };
font_data[111] <= { 8'b00000000 };
font_data[112] <= { 8'b00000000 };
font_data[113] <= { 8'b01111110 };
font_data[114] <= { 8'b01000000 };
font_data[115] <= { 8'b01111100 };
font_data[116] <= { 8'b01000000 };
font_data[117] <= { 8'b01000000 };
font_data[118] <= { 8'b01111110 };
font_data[119] <= { 8'b00000000 };
font_data[120] <= { 8'b00000000 };
font_data[121] <= { 8'b01111110 };
font_data[122] <= { 8'b01000000 };
font_data[123] <= { 8'b01111100 };
font_data[124] <= { 8'b01000000 };
font_data[125] <= { 8'b01000000 };
font_data[126] <= { 8'b01000000 };
font_data[127] <= { 8'b00000000 };
end
parameter N_NIBBLES = 16;
reg[3:0] data[N_NIBBLES-1:0];
always @(posedge in_latch) begin
data[0] <= in_data0[7:4];
data[1] <= in_data0[3:0];
data[2] <= in_data1[7:4];
data[3] <= in_data1[3:0];
data[4] <= in_data2[7:4];
data[5] <= in_data2[3:0];
data[6] <= in_data3[7:4];
data[7] <= in_data3[3:0];
data[8] <= in_data4[7:4];
data[9] <= in_data4[3:0];
data[10] <= in_data5[7:4];
data[11] <= in_data5[3:0];
data[12] <= in_data6[7:4];
data[13] <= in_data6[3:0];
data[14] <= in_data7[7:4];
data[15] <= in_data7[3:0];
end
reg is_overlay;
wire is_pixel_active;
reg [7:0] scanline;
reg [2:0] scanline_x;
always @(posedge in_pix_clk) begin
scanline <= font_data[ { data[in_pix_x[6:3]], in_pix_y[2:0] } ];
scanline_x <= ~in_pix_x[2:0];
if (in_pix_y[9:4] == 0 && in_pix_y[3] == 1 && in_pix_x[9:7] == 0) begin
is_overlay <= 1;
end else begin
is_overlay <= 0;
end
end
assign is_pixel_active = scanline[scanline_x];
assign out_pixel_r = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_r;
assign out_pixel_g = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_g;
assign out_pixel_b = is_overlay ? (is_pixel_active ? 8'b1 : 8'b0)
: in_pixel_b;
endmodule | 7 |
2,686 | data/full_repos/permissive/100752663/src/mod_sdram_controller.v | 100,752,663 | mod_sdram_controller.v | v | 415 | 89 | [] | [] | [] | null | line:106 column:19: Illegal character "'" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:99: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_q\' generates 13 bits.\n : ... In instance mod_sdram_controller\n assign out_sdram_a = a_q;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:103: Cannot find file containing module: \'SB_IO\'\n SB_IO #(\n ^~~~~\n ... Looked in:\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO.v\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/SB_IO.sv\n SB_IO\n SB_IO.v\n SB_IO.sv\n obj_dir/SB_IO\n obj_dir/SB_IO.v\n obj_dir/SB_IO.sv\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:154: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n : ... In instance mod_sdram_controller\n a_d = 11\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:203: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n : ... In instance mod_sdram_controller\n a_d = 11\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:213: Operator EQ expects 16 bits on the RHS, but RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance mod_sdram_controller\n if (delay_ctr_q == 13\'d0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:227: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:232: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:238: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:251: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h2\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:298: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h6\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d6; \n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:307: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:325: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h2\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d2; \n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:362: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance mod_sdram_controller\n delay_ctr_d = 13\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100752663/src/mod_sdram_controller.v:396: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'a_d\' generates 12 bits.\n : ... In instance mod_sdram_controller\n a_q <= a_d;\n ^~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n' | 109 | module | module mod_sdram_controller (
input in_sdram_clk,
input in_rst,
output out_sdram_cle,
output out_sdram_cs,
output out_sdram_cas,
output out_sdram_ras,
output out_sdram_we,
output out_sdram_dqm,
output [1:0] out_sdram_ba,
output [11:0] out_sdram_a,
inout [7:0] inout_sdram_dq,
input [21:0] in_addr,
input in_rw,
input [31:0] in_data,
output [31:0] out_data,
output out_busy,
input in_valid,
output out_valid
);
localparam CMD_UNSELECTED = 4'b1000;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE_REG = 4'b0000;
localparam STATE_SIZE = 4;
localparam INIT = 0,
WAIT = 1,
PRECHARGE_INIT = 2,
REFRESH_INIT_1 = 3,
REFRESH_INIT_2 = 4,
LOAD_MODE_REG = 5,
IDLE = 6,
REFRESH = 7,
ACTIVATE = 8,
READ = 9,
READ_RES = 10,
WRITE = 11,
PRECHARGE = 12;
reg cle_d, dqm_d;
reg [3:0] cmd_d;
reg [1:0] ba_d;
reg [11:0] a_d;
reg [7:0] dq_d;
reg [7:0] dqi_d;
(* IOB = "TRUE" *)
reg cle_q, dqm_q;
(* IOB = "TRUE" *)
reg [3:0] cmd_q;
(* IOB = "TRUE" *)
reg [1:0] ba_q;
(* IOB = "TRUE" *)
reg [12:0] a_q;
(* IOB = "TRUE" *)
reg [7:0] dq_q;
(* IOB = "TRUE" *)
wire [7:0] dqi_q;
reg dq_en_d, dq_en_q;
assign out_sdram_cle = cle_q;
assign out_sdram_cs = cmd_q[3];
assign out_sdram_ras = cmd_q[2];
assign out_sdram_cas = cmd_q[1];
assign out_sdram_we = cmd_q[0];
assign out_sdram_dqm = dqm_q;
assign out_sdram_ba = ba_q;
assign out_sdram_a = a_q;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) data_io [7:0] (
.PACKAGE_PIN(inout_sdram_dq),
.OUTPUT_ENABLE(dq_en_d),
.D_OUT_0(dq_q),
.D_IN_0(dqi_q)
);
reg [STATE_SIZE-1:0] state_d, state_q = INIT;
reg [STATE_SIZE-1:0] next_state_d, next_state_q;
reg [21:0] addr_d, addr_q;
reg [31:0] data_d, data_q;
reg out_valid_d, out_valid_q;
assign out_data = data_q;
assign out_busy = !ready_q;
assign out_valid = out_valid_q;
reg [15:0] delay_ctr_d, delay_ctr_q;
reg [1:0] byte_ctr_d, byte_ctr_q;
reg [9:0] refresh_ctr_d, refresh_ctr_q;
reg refresh_flag_d, refresh_flag_q;
reg ready_d, ready_q;
reg saved_rw_d, saved_rw_q;
reg [21:0] saved_addr_d, saved_addr_q;
reg [31:0] saved_data_d, saved_data_q;
reg rw_op_d, rw_op_q;
reg [3:0] row_open_d, row_open_q;
reg [11:0] row_addr_d[3:0], row_addr_q[3:0];
reg [2:0] precharge_bank_d, precharge_bank_q;
integer i;
always @* begin
dq_d = dq_q;
dqi_d = dqi_q;
dq_en_d = 1'b0;
cle_d = cle_q;
cmd_d = CMD_NOP;
dqm_d = 1'b0;
ba_d = 2'd0;
a_d = 11'd0;
state_d = state_q;
next_state_d = next_state_q;
delay_ctr_d = delay_ctr_q;
addr_d = addr_q;
data_d = data_q;
out_valid_d = 1'b0;
precharge_bank_d = precharge_bank_q;
rw_op_d = rw_op_q;
byte_ctr_d = 2'd0;
row_open_d = row_open_q;
for (i = 0; i < 4; i = i + 1)
row_addr_d[i] = row_addr_q[i];
refresh_flag_d = refresh_flag_q;
refresh_ctr_d = refresh_ctr_q + 1'b1;
if (refresh_ctr_q > 10'd750) begin
refresh_ctr_d = 10'd0;
refresh_flag_d = 1'b1;
end
saved_rw_d = saved_rw_q;
saved_data_d = saved_data_q;
saved_addr_d = saved_addr_q;
ready_d = ready_q;
if (ready_q && in_valid) begin
saved_rw_d = in_rw;
saved_data_d = in_data;
saved_addr_d = in_addr;
ready_d = 1'b0;
end
case (state_q)
INIT: begin
ready_d = 1'b0;
row_open_d = 4'b0;
out_valid_d = 1'b0;
a_d = 11'b0;
ba_d = 2'b0;
cle_d = 1'b1;
state_d = WAIT;
delay_ctr_d = 16'd19000;
next_state_d = PRECHARGE_INIT;
dq_en_d = 1'b0;
end
WAIT: begin
delay_ctr_d = delay_ctr_q - 1'b1;
if (delay_ctr_q == 13'd0) begin
state_d = next_state_q;
if (next_state_q == WRITE) begin
dq_en_d = 1'b1;
dq_d = data_q[7:0];
end
end
end
PRECHARGE_INIT: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = 1'b1;
ba_d = 2'd0;
state_d = WAIT;
next_state_d = REFRESH_INIT_1;
delay_ctr_d = 13'd0;
end
REFRESH_INIT_1: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = REFRESH_INIT_2;
end
REFRESH_INIT_2: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = LOAD_MODE_REG;
end
LOAD_MODE_REG: begin
cmd_d = CMD_LOAD_MODE_REG;
ba_d = 2'b0;
a_d = { 2'b00,
1'b0,
2'b00,
3'b010,
1'b0,
3'b010 };
state_d = WAIT;
delay_ctr_d = 13'd2;
next_state_d = IDLE;
refresh_flag_d = 1'b0;
refresh_ctr_d = 10'b1;
ready_d = 1'b1;
end
IDLE: begin
if (refresh_flag_q) begin
state_d = PRECHARGE;
next_state_d = REFRESH;
precharge_bank_d = 3'b100;
refresh_flag_d = 1'b0;
end else if (!ready_q) begin
ready_d = 1'b1;
rw_op_d = saved_rw_q;
addr_d = saved_addr_q;
if (saved_rw_q)
data_d = saved_data_q;
if (row_open_q[saved_addr_q[21:20]]) begin
if (row_addr_q[saved_addr_q[21:20]] == saved_addr_q[19:8]) begin
if (saved_rw_q)
state_d = WRITE;
else
state_d = READ;
end else begin
state_d = PRECHARGE;
precharge_bank_d = {1'b0, saved_addr_q[21:20]};
next_state_d = ACTIVATE;
end
end else begin
state_d = ACTIVATE;
end
end
end
REFRESH: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd6;
next_state_d = IDLE;
end
ACTIVATE: begin
cmd_d = CMD_ACTIVE;
a_d = addr_q[19:8];
ba_d = addr_q[21:20];
delay_ctr_d = 13'd0;
state_d = WAIT;
if (rw_op_q)
next_state_d = WRITE;
else
next_state_d = READ;
row_open_d[addr_q[21:20]] = 1'b1;
row_addr_d[addr_q[21:20]] = addr_q[19:8];
end
READ: begin
cmd_d = CMD_READ;
a_d = {2'b0, addr_q[7:0], 2'b0};
ba_d = addr_q[21:20];
state_d = WAIT;
delay_ctr_d = 13'd2;
next_state_d = READ_RES;
end
READ_RES: begin
byte_ctr_d = byte_ctr_q + 1'b1;
data_d = {dqi_q, data_q[31:8]};
if (byte_ctr_q == 2'd3) begin
out_valid_d = 1'b1;
state_d = IDLE;
end
end
WRITE: begin
byte_ctr_d = byte_ctr_q + 1'b1;
if (byte_ctr_q == 2'd0)
cmd_d = CMD_WRITE;
dq_d = data_q[7:0];
data_d = {8'h00, data_q[31:8]};
dq_en_d = 1'b1;
a_d = {2'b0, addr_q[7:0], 2'b00};
ba_d = addr_q[21:20];
if (byte_ctr_q == 2'd3) begin
state_d = IDLE;
end
end
PRECHARGE: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = precharge_bank_q[2];
ba_d = precharge_bank_q[1:0];
state_d = WAIT;
delay_ctr_d = 13'd0;
if (precharge_bank_q[2]) begin
row_open_d = 4'b0000;
end else begin
row_open_d[precharge_bank_q[1:0]] = 1'b0;
end
end
default: state_d = INIT;
endcase
end
always @(posedge in_sdram_clk) begin
if(in_rst) begin
cle_q <= 1'b0;
dq_en_q <= 1'b0;
state_q <= INIT;
ready_q <= 1'b0;
end else begin
cle_q <= cle_d;
dq_en_q <= dq_en_d;
state_q <= state_d;
ready_q <= ready_d;
end
saved_rw_q <= saved_rw_d;
saved_data_q <= saved_data_d;
saved_addr_q <= saved_addr_d;
cmd_q <= cmd_d;
dqm_q <= dqm_d;
ba_q <= ba_d;
a_q <= a_d;
dq_q <= dq_d;
next_state_q <= next_state_d;
refresh_flag_q <= refresh_flag_d;
refresh_ctr_q <= refresh_ctr_d;
data_q <= data_d;
addr_q <= addr_d;
out_valid_q <= out_valid_d;
row_open_q <= row_open_d;
for (i = 0; i < 4; i = i + 1)
row_addr_q[i] <= row_addr_d[i];
precharge_bank_q <= precharge_bank_d;
rw_op_q <= rw_op_d;
byte_ctr_q <= byte_ctr_d;
delay_ctr_q <= delay_ctr_d;
end
endmodule | module mod_sdram_controller (
input in_sdram_clk,
input in_rst,
output out_sdram_cle,
output out_sdram_cs,
output out_sdram_cas,
output out_sdram_ras,
output out_sdram_we,
output out_sdram_dqm,
output [1:0] out_sdram_ba,
output [11:0] out_sdram_a,
inout [7:0] inout_sdram_dq,
input [21:0] in_addr,
input in_rw,
input [31:0] in_data,
output [31:0] out_data,
output out_busy,
input in_valid,
output out_valid
); |
localparam CMD_UNSELECTED = 4'b1000;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE_REG = 4'b0000;
localparam STATE_SIZE = 4;
localparam INIT = 0,
WAIT = 1,
PRECHARGE_INIT = 2,
REFRESH_INIT_1 = 3,
REFRESH_INIT_2 = 4,
LOAD_MODE_REG = 5,
IDLE = 6,
REFRESH = 7,
ACTIVATE = 8,
READ = 9,
READ_RES = 10,
WRITE = 11,
PRECHARGE = 12;
reg cle_d, dqm_d;
reg [3:0] cmd_d;
reg [1:0] ba_d;
reg [11:0] a_d;
reg [7:0] dq_d;
reg [7:0] dqi_d;
(* IOB = "TRUE" *)
reg cle_q, dqm_q;
(* IOB = "TRUE" *)
reg [3:0] cmd_q;
(* IOB = "TRUE" *)
reg [1:0] ba_q;
(* IOB = "TRUE" *)
reg [12:0] a_q;
(* IOB = "TRUE" *)
reg [7:0] dq_q;
(* IOB = "TRUE" *)
wire [7:0] dqi_q;
reg dq_en_d, dq_en_q;
assign out_sdram_cle = cle_q;
assign out_sdram_cs = cmd_q[3];
assign out_sdram_ras = cmd_q[2];
assign out_sdram_cas = cmd_q[1];
assign out_sdram_we = cmd_q[0];
assign out_sdram_dqm = dqm_q;
assign out_sdram_ba = ba_q;
assign out_sdram_a = a_q;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) data_io [7:0] (
.PACKAGE_PIN(inout_sdram_dq),
.OUTPUT_ENABLE(dq_en_d),
.D_OUT_0(dq_q),
.D_IN_0(dqi_q)
);
reg [STATE_SIZE-1:0] state_d, state_q = INIT;
reg [STATE_SIZE-1:0] next_state_d, next_state_q;
reg [21:0] addr_d, addr_q;
reg [31:0] data_d, data_q;
reg out_valid_d, out_valid_q;
assign out_data = data_q;
assign out_busy = !ready_q;
assign out_valid = out_valid_q;
reg [15:0] delay_ctr_d, delay_ctr_q;
reg [1:0] byte_ctr_d, byte_ctr_q;
reg [9:0] refresh_ctr_d, refresh_ctr_q;
reg refresh_flag_d, refresh_flag_q;
reg ready_d, ready_q;
reg saved_rw_d, saved_rw_q;
reg [21:0] saved_addr_d, saved_addr_q;
reg [31:0] saved_data_d, saved_data_q;
reg rw_op_d, rw_op_q;
reg [3:0] row_open_d, row_open_q;
reg [11:0] row_addr_d[3:0], row_addr_q[3:0];
reg [2:0] precharge_bank_d, precharge_bank_q;
integer i;
always @* begin
dq_d = dq_q;
dqi_d = dqi_q;
dq_en_d = 1'b0;
cle_d = cle_q;
cmd_d = CMD_NOP;
dqm_d = 1'b0;
ba_d = 2'd0;
a_d = 11'd0;
state_d = state_q;
next_state_d = next_state_q;
delay_ctr_d = delay_ctr_q;
addr_d = addr_q;
data_d = data_q;
out_valid_d = 1'b0;
precharge_bank_d = precharge_bank_q;
rw_op_d = rw_op_q;
byte_ctr_d = 2'd0;
row_open_d = row_open_q;
for (i = 0; i < 4; i = i + 1)
row_addr_d[i] = row_addr_q[i];
refresh_flag_d = refresh_flag_q;
refresh_ctr_d = refresh_ctr_q + 1'b1;
if (refresh_ctr_q > 10'd750) begin
refresh_ctr_d = 10'd0;
refresh_flag_d = 1'b1;
end
saved_rw_d = saved_rw_q;
saved_data_d = saved_data_q;
saved_addr_d = saved_addr_q;
ready_d = ready_q;
if (ready_q && in_valid) begin
saved_rw_d = in_rw;
saved_data_d = in_data;
saved_addr_d = in_addr;
ready_d = 1'b0;
end
case (state_q)
INIT: begin
ready_d = 1'b0;
row_open_d = 4'b0;
out_valid_d = 1'b0;
a_d = 11'b0;
ba_d = 2'b0;
cle_d = 1'b1;
state_d = WAIT;
delay_ctr_d = 16'd19000;
next_state_d = PRECHARGE_INIT;
dq_en_d = 1'b0;
end
WAIT: begin
delay_ctr_d = delay_ctr_q - 1'b1;
if (delay_ctr_q == 13'd0) begin
state_d = next_state_q;
if (next_state_q == WRITE) begin
dq_en_d = 1'b1;
dq_d = data_q[7:0];
end
end
end
PRECHARGE_INIT: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = 1'b1;
ba_d = 2'd0;
state_d = WAIT;
next_state_d = REFRESH_INIT_1;
delay_ctr_d = 13'd0;
end
REFRESH_INIT_1: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = REFRESH_INIT_2;
end
REFRESH_INIT_2: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd7;
next_state_d = LOAD_MODE_REG;
end
LOAD_MODE_REG: begin
cmd_d = CMD_LOAD_MODE_REG;
ba_d = 2'b0;
a_d = { 2'b00,
1'b0,
2'b00,
3'b010,
1'b0,
3'b010 };
state_d = WAIT;
delay_ctr_d = 13'd2;
next_state_d = IDLE;
refresh_flag_d = 1'b0;
refresh_ctr_d = 10'b1;
ready_d = 1'b1;
end
IDLE: begin
if (refresh_flag_q) begin
state_d = PRECHARGE;
next_state_d = REFRESH;
precharge_bank_d = 3'b100;
refresh_flag_d = 1'b0;
end else if (!ready_q) begin
ready_d = 1'b1;
rw_op_d = saved_rw_q;
addr_d = saved_addr_q;
if (saved_rw_q)
data_d = saved_data_q;
if (row_open_q[saved_addr_q[21:20]]) begin
if (row_addr_q[saved_addr_q[21:20]] == saved_addr_q[19:8]) begin
if (saved_rw_q)
state_d = WRITE;
else
state_d = READ;
end else begin
state_d = PRECHARGE;
precharge_bank_d = {1'b0, saved_addr_q[21:20]};
next_state_d = ACTIVATE;
end
end else begin
state_d = ACTIVATE;
end
end
end
REFRESH: begin
cmd_d = CMD_REFRESH;
state_d = WAIT;
delay_ctr_d = 13'd6;
next_state_d = IDLE;
end
ACTIVATE: begin
cmd_d = CMD_ACTIVE;
a_d = addr_q[19:8];
ba_d = addr_q[21:20];
delay_ctr_d = 13'd0;
state_d = WAIT;
if (rw_op_q)
next_state_d = WRITE;
else
next_state_d = READ;
row_open_d[addr_q[21:20]] = 1'b1;
row_addr_d[addr_q[21:20]] = addr_q[19:8];
end
READ: begin
cmd_d = CMD_READ;
a_d = {2'b0, addr_q[7:0], 2'b0};
ba_d = addr_q[21:20];
state_d = WAIT;
delay_ctr_d = 13'd2;
next_state_d = READ_RES;
end
READ_RES: begin
byte_ctr_d = byte_ctr_q + 1'b1;
data_d = {dqi_q, data_q[31:8]};
if (byte_ctr_q == 2'd3) begin
out_valid_d = 1'b1;
state_d = IDLE;
end
end
WRITE: begin
byte_ctr_d = byte_ctr_q + 1'b1;
if (byte_ctr_q == 2'd0)
cmd_d = CMD_WRITE;
dq_d = data_q[7:0];
data_d = {8'h00, data_q[31:8]};
dq_en_d = 1'b1;
a_d = {2'b0, addr_q[7:0], 2'b00};
ba_d = addr_q[21:20];
if (byte_ctr_q == 2'd3) begin
state_d = IDLE;
end
end
PRECHARGE: begin
cmd_d = CMD_PRECHARGE;
a_d[10] = precharge_bank_q[2];
ba_d = precharge_bank_q[1:0];
state_d = WAIT;
delay_ctr_d = 13'd0;
if (precharge_bank_q[2]) begin
row_open_d = 4'b0000;
end else begin
row_open_d[precharge_bank_q[1:0]] = 1'b0;
end
end
default: state_d = INIT;
endcase
end
always @(posedge in_sdram_clk) begin
if(in_rst) begin
cle_q <= 1'b0;
dq_en_q <= 1'b0;
state_q <= INIT;
ready_q <= 1'b0;
end else begin
cle_q <= cle_d;
dq_en_q <= dq_en_d;
state_q <= state_d;
ready_q <= ready_d;
end
saved_rw_q <= saved_rw_d;
saved_data_q <= saved_data_d;
saved_addr_q <= saved_addr_d;
cmd_q <= cmd_d;
dqm_q <= dqm_d;
ba_q <= ba_d;
a_q <= a_d;
dq_q <= dq_d;
next_state_q <= next_state_d;
refresh_flag_q <= refresh_flag_d;
refresh_ctr_q <= refresh_ctr_d;
data_q <= data_d;
addr_q <= addr_d;
out_valid_q <= out_valid_d;
row_open_q <= row_open_d;
for (i = 0; i < 4; i = i + 1)
row_addr_q[i] <= row_addr_d[i];
precharge_bank_q <= precharge_bank_d;
rw_op_q <= rw_op_d;
byte_ctr_q <= byte_ctr_d;
delay_ctr_q <= delay_ctr_d;
end
endmodule | 7 |
2,687 | data/full_repos/permissive/100752663/src/mod_vga_encoder.v | 100,752,663 | mod_vga_encoder.v | v | 210 | 69 | [] | [] | [] | [(4, 209)] | null | null | 1: b"%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:190: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_r'\n : ... In instance mod_vga_encoder\n out_vga_r <= in_vga_r;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:191: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_g'\n : ... In instance mod_vga_encoder\n out_vga_g <= in_vga_g;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:192: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_b'\n : ... In instance mod_vga_encoder\n out_vga_b <= in_vga_b;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:194: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_r'\n : ... In instance mod_vga_encoder\n out_vga_r <= 0;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:195: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_g'\n : ... In instance mod_vga_encoder\n out_vga_g <= 0;\n ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/100752663/src/mod_vga_encoder.v:196: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out_vga_b'\n : ... In instance mod_vga_encoder\n out_vga_b <= 0;\n ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 110 | module | module mod_vga_encoder(
input in_clk_25_175_mhz,
input [7:0] in_vga_r,
input [7:0] in_vga_g,
input [7:0] in_vga_b,
output [7:0] out_vga_r,
output [7:0] out_vga_g,
output [7:0] out_vga_b,
output out_vga_hsync,
output out_vga_vsync,
output [9:0] out_vga_next_x,
output [9:0] out_vga_next_y,
output out_vga_active
);
reg hsync, hsync_delay1, hsync_delay2;
reg vsync, vsync_delay1, vsync_delay2;
reg new_line = 0;
reg [9:0] pix_x = 0;
reg [9:0] pix_y = 0;
reg active_x = 0;
reg active_y = 0;
reg active_x_delay = 0;
reg active_y_delay = 0;
parameter res_x = 640;
parameter res_y = 480;
parameter hpulse = 96;
parameter hbp = 48;
parameter hfp = 16;
parameter vpulse = 2;
parameter vbp = 33;
parameter vfp = 10;
parameter hpixels = res_x + hfp + hpulse + hbp;
parameter vlines = res_y + vfp + vpulse + vbp;
reg [3:0] horiz_state = 4'b1000;
reg [3:0] vert_state = 4'b1000;
always @(posedge in_clk_25_175_mhz) begin
casex (horiz_state)
4'b1xxx: begin
hsync <= 1'b0;
active_x <= 1'b0;
new_line <= 1'b0;
if (pix_x == (hpulse - 1)) begin
horiz_state <= 4'b0100;
pix_x <= 0;
end else begin
horiz_state <= 4'b1000;
pix_x <= pix_x + 1;
end
end
4'bx1xx: begin
hsync <= 1'b1;
active_x <= 1'b0;
new_line <= 1'b0;
if (pix_x == (hbp - 1)) begin
horiz_state <= 4'b0010;
pix_x <= 0;
end else begin
horiz_state <= 4'b0100;
pix_x <= pix_x + 1;
end
end
4'bxx1x: begin
hsync <= 1'b1;
active_x <= 1'b1;
new_line <= 1'b0;
if (pix_x == (res_x - 1)) begin
horiz_state <= 4'b0001;
pix_x <= 0;
end else begin
horiz_state <= 4'b0010;
pix_x <= pix_x + 1;
end
end
4'bxxx1: begin
hsync <= 1'b1;
active_x <= 1'b0;
if (pix_x == (hfp - 2)) begin
new_line <= 1;
end else begin
new_line <= 0;
end
if (pix_x == (hfp - 1)) begin
horiz_state <= 4'b1000;
pix_x <= 0;
end else begin
horiz_state <= 4'b0001;
pix_x <= pix_x + 1;
end
end
endcase
if (new_line) begin
casex (vert_state)
4'b1xxx: begin
vsync <= 1'b0;
active_y <= 1'b0;
if (pix_y == (vpulse - 1)) begin
vert_state <= 4'b0100;
pix_y <= 0;
end else begin
vert_state <= 4'b1000;
pix_y <= pix_y + 1;
end
end
4'bx1xx: begin
vsync <= 1'b1;
active_y <= 1'b0;
if (pix_y == (vbp - 1)) begin
vert_state <= 4'b0010;
pix_y <= 0;
end else begin
vert_state <= 4'b0100;
pix_y <= pix_y + 1;
end
end
4'bxx1x: begin
vsync <= 1'b1;
active_y <= 1'b1;
if (pix_y == (res_y - 1)) begin
vert_state <= 4'b0001;
pix_y <= 0;
end else begin
vert_state <= 4'b0010;
pix_y <= pix_y + 1;
end
end
4'bxxx1: begin
vsync <= 1'b1;
active_y <= 1'b0;
if (pix_y == (vfp - 1)) begin
vert_state <= 4'b1000;
pix_y <= 0;
end else begin
vert_state <= 4'b0001;
pix_y <= pix_y + 1;
end
end
endcase
end
hsync_delay1 <= hsync;
hsync_delay2 <= hsync_delay1;
vsync_delay1 <= vsync;
vsync_delay2 <= vsync_delay1;
active_x_delay <= active_x;
active_y_delay <= active_y;
if (active_x & active_y) begin
out_vga_r <= in_vga_r;
out_vga_g <= in_vga_g;
out_vga_b <= in_vga_b;
end else begin
out_vga_r <= 0;
out_vga_g <= 0;
out_vga_b <= 0;
end
end
assign out_vga_hsync = hsync_delay2;
assign out_vga_vsync = vsync_delay2;
assign out_vga_next_x = pix_x;
assign out_vga_next_y = pix_y;
assign out_vga_active = active_x;
endmodule | module mod_vga_encoder(
input in_clk_25_175_mhz,
input [7:0] in_vga_r,
input [7:0] in_vga_g,
input [7:0] in_vga_b,
output [7:0] out_vga_r,
output [7:0] out_vga_g,
output [7:0] out_vga_b,
output out_vga_hsync,
output out_vga_vsync,
output [9:0] out_vga_next_x,
output [9:0] out_vga_next_y,
output out_vga_active
); |
reg hsync, hsync_delay1, hsync_delay2;
reg vsync, vsync_delay1, vsync_delay2;
reg new_line = 0;
reg [9:0] pix_x = 0;
reg [9:0] pix_y = 0;
reg active_x = 0;
reg active_y = 0;
reg active_x_delay = 0;
reg active_y_delay = 0;
parameter res_x = 640;
parameter res_y = 480;
parameter hpulse = 96;
parameter hbp = 48;
parameter hfp = 16;
parameter vpulse = 2;
parameter vbp = 33;
parameter vfp = 10;
parameter hpixels = res_x + hfp + hpulse + hbp;
parameter vlines = res_y + vfp + vpulse + vbp;
reg [3:0] horiz_state = 4'b1000;
reg [3:0] vert_state = 4'b1000;
always @(posedge in_clk_25_175_mhz) begin
casex (horiz_state)
4'b1xxx: begin
hsync <= 1'b0;
active_x <= 1'b0;
new_line <= 1'b0;
if (pix_x == (hpulse - 1)) begin
horiz_state <= 4'b0100;
pix_x <= 0;
end else begin
horiz_state <= 4'b1000;
pix_x <= pix_x + 1;
end
end
4'bx1xx: begin
hsync <= 1'b1;
active_x <= 1'b0;
new_line <= 1'b0;
if (pix_x == (hbp - 1)) begin
horiz_state <= 4'b0010;
pix_x <= 0;
end else begin
horiz_state <= 4'b0100;
pix_x <= pix_x + 1;
end
end
4'bxx1x: begin
hsync <= 1'b1;
active_x <= 1'b1;
new_line <= 1'b0;
if (pix_x == (res_x - 1)) begin
horiz_state <= 4'b0001;
pix_x <= 0;
end else begin
horiz_state <= 4'b0010;
pix_x <= pix_x + 1;
end
end
4'bxxx1: begin
hsync <= 1'b1;
active_x <= 1'b0;
if (pix_x == (hfp - 2)) begin
new_line <= 1;
end else begin
new_line <= 0;
end
if (pix_x == (hfp - 1)) begin
horiz_state <= 4'b1000;
pix_x <= 0;
end else begin
horiz_state <= 4'b0001;
pix_x <= pix_x + 1;
end
end
endcase
if (new_line) begin
casex (vert_state)
4'b1xxx: begin
vsync <= 1'b0;
active_y <= 1'b0;
if (pix_y == (vpulse - 1)) begin
vert_state <= 4'b0100;
pix_y <= 0;
end else begin
vert_state <= 4'b1000;
pix_y <= pix_y + 1;
end
end
4'bx1xx: begin
vsync <= 1'b1;
active_y <= 1'b0;
if (pix_y == (vbp - 1)) begin
vert_state <= 4'b0010;
pix_y <= 0;
end else begin
vert_state <= 4'b0100;
pix_y <= pix_y + 1;
end
end
4'bxx1x: begin
vsync <= 1'b1;
active_y <= 1'b1;
if (pix_y == (res_y - 1)) begin
vert_state <= 4'b0001;
pix_y <= 0;
end else begin
vert_state <= 4'b0010;
pix_y <= pix_y + 1;
end
end
4'bxxx1: begin
vsync <= 1'b1;
active_y <= 1'b0;
if (pix_y == (vfp - 1)) begin
vert_state <= 4'b1000;
pix_y <= 0;
end else begin
vert_state <= 4'b0001;
pix_y <= pix_y + 1;
end
end
endcase
end
hsync_delay1 <= hsync;
hsync_delay2 <= hsync_delay1;
vsync_delay1 <= vsync;
vsync_delay2 <= vsync_delay1;
active_x_delay <= active_x;
active_y_delay <= active_y;
if (active_x & active_y) begin
out_vga_r <= in_vga_r;
out_vga_g <= in_vga_g;
out_vga_b <= in_vga_b;
end else begin
out_vga_r <= 0;
out_vga_g <= 0;
out_vga_b <= 0;
end
end
assign out_vga_hsync = hsync_delay2;
assign out_vga_vsync = vsync_delay2;
assign out_vga_next_x = pix_x;
assign out_vga_next_y = pix_y;
assign out_vga_active = active_x;
endmodule | 7 |
2,688 | data/full_repos/permissive/100752663/src/top.v | 100,752,663 | top.v | v | 153 | 79 | [] | [] | [] | null | line:36: before: ")" | null | 1: b"%Error: data/full_repos/permissive/100752663/src/top.v:32: Cannot find file containing module: 'mod_clock_master'\nmod_clock_master clock_master(\n^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/mod_clock_master\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/mod_clock_master.v\n data/full_repos/permissive/100752663/src,data/full_repos/permissive/100752663/mod_clock_master.sv\n mod_clock_master\n mod_clock_master.v\n mod_clock_master.sv\n obj_dir/mod_clock_master\n obj_dir/mod_clock_master.v\n obj_dir/mod_clock_master.sv\n%Error: data/full_repos/permissive/100752663/src/top.v:48: Cannot find file containing module: 'mod_grid_display'\nmod_grid_display grid_display(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100752663/src/top.v:67: Cannot find file containing module: 'mod_hex_display'\nmod_hex_display hex_display(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100752663/src/top.v:92: Cannot find file containing module: 'mod_vga_encoder'\nmod_vga_encoder vga_encoder(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100752663/src/top.v:107: Cannot find file containing module: 'mod_controller'\nmod_controller controller0(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100752663/src/top.v:116: Cannot find file containing module: 'mod_sdram_controller'\nmod_sdram_controller sdram_controller(\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 111 | module | module top(
input in_clk_12_mhz,
output [7:0] out_leds,
output out_vga_r,
output out_vga_g,
output out_vga_b,
output out_vga_hsync,
output out_vga_vsync,
output out_controller0_pulse,
output out_controller0_latch,
input in_controller0_data,
output out_sdram_cle,
output out_sdram_cs,
output out_sdram_cas,
output out_sdram_ras,
output out_sdram_we,
output out_sdram_dqm,
output [1:0] out_sdram_ba,
output [11:0] out_sdram_a,
inout [7:0] inout_sdram_dq
);
wire w_vga_clock;
wire w_sdram_clock;
mod_clock_master clock_master(
.in_clk_12_mhz( in_clk_12_mhz ),
.out_clk_25_175_mhz( w_vga_clock ),
.out_clk_166_mhz( w_sdram_clock ),
);
wire [9:0] w_vga_pix_x;
wire [9:0] w_vga_pix_y;
wire [7:0] w_grid_r;
wire [7:0] w_grid_g;
wire [7:0] w_grid_b;
mod_grid_display grid_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_pixel_r( 8'b11111111 ),
.in_pixel_g( 8'b00000000 ),
.in_pixel_b( 8'b00000000 ),
.out_pixel_r( w_grid_r ),
.out_pixel_g( w_grid_g ),
.out_pixel_b( w_grid_b )
);
wire [7:0] w_hex_r;
wire [7:0] w_hex_g;
wire [7:0] w_hex_b;
wire w_hex_display_pixel_on;
mod_hex_display hex_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_latch( out_vga_vsync ),
.in_data0( counter[63:56] ),
.in_data1( counter[55:48] ),
.in_data2( counter[47:40] ),
.in_data3( counter[39:32] ),
.in_data4( counter[31:24] ),
.in_data5( counter[23:16] ),
.in_data6( counter[15:8] ),
.in_data7( controller0_buttons[7:0] ),
.in_pixel_r( w_grid_r ),
.in_pixel_g( w_grid_g ),
.in_pixel_b( w_grid_b ),
.out_pixel_r( w_hex_r ),
.out_pixel_g( w_hex_g ),
.out_pixel_b( w_hex_b )
);
mod_vga_encoder vga_encoder(
.in_clk_25_175_mhz( w_vga_clock ),
.in_vga_r( w_hex_r ),
.in_vga_g( w_hex_g ),
.in_vga_b( w_hex_b ),
.out_vga_r( { out_vga_r } ),
.out_vga_g( { out_vga_g } ),
.out_vga_b( { out_vga_b } ),
.out_vga_hsync( out_vga_hsync ),
.out_vga_vsync( out_vga_vsync ),
.out_vga_next_x( w_vga_pix_x ),
.out_vga_next_y( w_vga_pix_y )
);
wire [7:0] controller0_buttons;
mod_controller controller0(
.in_clk_controller( counter[8] ),
.in_vsync( out_vga_vsync ),
.in_controller_data( in_controller0_data ),
.out_controller_latch( out_controller0_latch ),
.out_controller_pulse( out_controller0_pulse ),
.out_controller_buttons( controller0_buttons )
);
mod_sdram_controller sdram_controller(
.in_sdram_clk(w_sdram_clock),
.in_rst(1'b0),
.out_sdram_cle(out_sdram_cle),
.out_sdram_cs(out_sdram_cs),
.out_sdram_cas(out_sdram_cas),
.out_sdram_ras(out_sdram_ras),
.out_sdram_we(out_sdram_we),
.out_sdram_dqm(out_sdram_dqm),
.out_sdram_ba(out_sdram_ba),
.out_sdram_a(out_sdram_a),
.inout_sdram_dq(inout_sdram_dq),
.in_addr(22'b0000000000001000100100),
.in_rw(readOrWrite),
.in_data(counter),
.out_data(mem_read),
.out_busy(busy),
.in_valid(start),
.out_valid(done)
);
reg [31:0] mem_read;
reg readOrWrite = 0;
wire busy;
reg start = 0;
wire done;
reg [63:0] counter;
always @(posedge in_clk_12_mhz) begin
counter <= counter + 1;
end
assign out_leds[7:0] = controller0_buttons[7:0];
endmodule | module top(
input in_clk_12_mhz,
output [7:0] out_leds,
output out_vga_r,
output out_vga_g,
output out_vga_b,
output out_vga_hsync,
output out_vga_vsync,
output out_controller0_pulse,
output out_controller0_latch,
input in_controller0_data,
output out_sdram_cle,
output out_sdram_cs,
output out_sdram_cas,
output out_sdram_ras,
output out_sdram_we,
output out_sdram_dqm,
output [1:0] out_sdram_ba,
output [11:0] out_sdram_a,
inout [7:0] inout_sdram_dq
); |
wire w_vga_clock;
wire w_sdram_clock;
mod_clock_master clock_master(
.in_clk_12_mhz( in_clk_12_mhz ),
.out_clk_25_175_mhz( w_vga_clock ),
.out_clk_166_mhz( w_sdram_clock ),
);
wire [9:0] w_vga_pix_x;
wire [9:0] w_vga_pix_y;
wire [7:0] w_grid_r;
wire [7:0] w_grid_g;
wire [7:0] w_grid_b;
mod_grid_display grid_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_pixel_r( 8'b11111111 ),
.in_pixel_g( 8'b00000000 ),
.in_pixel_b( 8'b00000000 ),
.out_pixel_r( w_grid_r ),
.out_pixel_g( w_grid_g ),
.out_pixel_b( w_grid_b )
);
wire [7:0] w_hex_r;
wire [7:0] w_hex_g;
wire [7:0] w_hex_b;
wire w_hex_display_pixel_on;
mod_hex_display hex_display(
.in_pix_clk( w_vga_clock ),
.in_pix_x( w_vga_pix_x ),
.in_pix_y( w_vga_pix_y ),
.in_latch( out_vga_vsync ),
.in_data0( counter[63:56] ),
.in_data1( counter[55:48] ),
.in_data2( counter[47:40] ),
.in_data3( counter[39:32] ),
.in_data4( counter[31:24] ),
.in_data5( counter[23:16] ),
.in_data6( counter[15:8] ),
.in_data7( controller0_buttons[7:0] ),
.in_pixel_r( w_grid_r ),
.in_pixel_g( w_grid_g ),
.in_pixel_b( w_grid_b ),
.out_pixel_r( w_hex_r ),
.out_pixel_g( w_hex_g ),
.out_pixel_b( w_hex_b )
);
mod_vga_encoder vga_encoder(
.in_clk_25_175_mhz( w_vga_clock ),
.in_vga_r( w_hex_r ),
.in_vga_g( w_hex_g ),
.in_vga_b( w_hex_b ),
.out_vga_r( { out_vga_r } ),
.out_vga_g( { out_vga_g } ),
.out_vga_b( { out_vga_b } ),
.out_vga_hsync( out_vga_hsync ),
.out_vga_vsync( out_vga_vsync ),
.out_vga_next_x( w_vga_pix_x ),
.out_vga_next_y( w_vga_pix_y )
);
wire [7:0] controller0_buttons;
mod_controller controller0(
.in_clk_controller( counter[8] ),
.in_vsync( out_vga_vsync ),
.in_controller_data( in_controller0_data ),
.out_controller_latch( out_controller0_latch ),
.out_controller_pulse( out_controller0_pulse ),
.out_controller_buttons( controller0_buttons )
);
mod_sdram_controller sdram_controller(
.in_sdram_clk(w_sdram_clock),
.in_rst(1'b0),
.out_sdram_cle(out_sdram_cle),
.out_sdram_cs(out_sdram_cs),
.out_sdram_cas(out_sdram_cas),
.out_sdram_ras(out_sdram_ras),
.out_sdram_we(out_sdram_we),
.out_sdram_dqm(out_sdram_dqm),
.out_sdram_ba(out_sdram_ba),
.out_sdram_a(out_sdram_a),
.inout_sdram_dq(inout_sdram_dq),
.in_addr(22'b0000000000001000100100),
.in_rw(readOrWrite),
.in_data(counter),
.out_data(mem_read),
.out_busy(busy),
.in_valid(start),
.out_valid(done)
);
reg [31:0] mem_read;
reg readOrWrite = 0;
wire busy;
reg start = 0;
wire done;
reg [63:0] counter;
always @(posedge in_clk_12_mhz) begin
counter <= counter + 1;
end
assign out_leds[7:0] = controller0_buttons[7:0];
endmodule | 7 |
2,689 | data/full_repos/permissive/100796583/MBSsoc_top.v | 100,796,583 | MBSsoc_top.v | v | 135 | 66 | [] | [] | [] | [(113, 245)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:2: Cannot find include file: cpu/MBScore_const.v\n`include "cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583,data/full_repos/permissive/100796583/cpu/MBScore_const.v\n data/full_repos/permissive/100796583,data/full_repos/permissive/100796583/cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583,data/full_repos/permissive/100796583/cpu/MBScore_const.v.sv\n cpu/MBScore_const.v\n cpu/MBScore_const.v.v\n cpu/MBScore_const.v.sv\n obj_dir/cpu/MBScore_const.v\n obj_dir/cpu/MBScore_const.v.v\n obj_dir/cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] data_bus_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:7: Define or directive not defined: \'`ADDR_WIDTH\'\n output [`ADDR_WIDTH-1:0] addr_bus_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:8: Define or directive not defined: \'`CTRL_BUS_WIDTH\'\n output [`CTRL_BUS_WIDTH-1:0] ctrl_bus_out,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:12: Define or directive not defined: \'`CORE_NUM\'\n output [`CORE_NUM-1:0] cpu_pause_out,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] data_bus;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:20: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,ram_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:21: Define or directive not defined: \'`CTRL_BUS_WIDTH\'\n wire [`CTRL_BUS_WIDTH-1:0] ctrl_bus;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:23: Define or directive not defined: \'`INT_SEL_WIDTH\'\n wire [`INT_SEL_WIDTH-1:0] int_num0,int_num1;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:24: Define or directive not defined: \'`CORE_NUM\'\n wire [`CORE_NUM-1:0] int_able;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:25: Define or directive not defined: \'`CORE_NUM\'\n wire [`CORE_NUM-1:0] cpu_pause;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:29: Define or directive not defined: \'`SYSCODE_WIDTH\'\n wire [`SYSCODE_WIDTH-1:0] syscall_code0,syscall_code1;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/MBSsoc_top.v:31: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH-1:0] init_pc_cpu1,init_pc_cpu0;\n ^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n' | 112 | module | module MBSsoc_top(
input clk,rst_n,
output [`DATA_WIDTH-1:0] data_bus_out,
output [`ADDR_WIDTH-1:0] addr_bus_out,
output [`CTRL_BUS_WIDTH-1:0] ctrl_bus_out,
output cpu1_en_out,
output syscall0_out,
output [2:0] state0,state1,
output [`CORE_NUM-1:0] cpu_pause_out,
output cpu_sel_out,
output cpu0_lock_flag_out,
output [31:0] lock_addr_out
);
wire [`DATA_WIDTH-1:0] data_bus;
wire [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,ram_addr;
wire [`CTRL_BUS_WIDTH-1:0] ctrl_bus;
wire [`INT_SEL_WIDTH-1:0] int_num0,int_num1;
wire [`CORE_NUM-1:0] int_able;
wire [`CORE_NUM-1:0] cpu_pause;
wire ram_re,ram_we;
wire syscall0,syscall1;
wire [`SYSCODE_WIDTH-1:0] syscall_code0,syscall_code1;
wire cpu1_en;
wire [`ADDR_WIDTH-1:0] init_pc_cpu1,init_pc_cpu0;
wire [3:0] cpu_ctrl_bus;
wire cpu_sel;
wire cpu0_access_lock,cpu1_access_lock;
wire cpu0_lock_flag,cpu1_lock_flag;
assign cpu1_en_out = cpu1_en;
assign syscall0_out = syscall0;
assign cpu_pause_out = cpu_pause;
assign cpu_sel_out = cpu_sel;
assign cpu0_lock_flag_out = cpu0_lock_flag;
reg bus_clk;
always @(clk)
bus_clk = clk;
assign data_bus_out = data_bus;
assign addr_bus_out = ram_addr;
assign ctrl_bus_out = ctrl_bus;
MBScore_cpu_top CPU0(
.state(state0),
.clk(clk),
.rst_n(rst_n),
.pause(cpu_pause[0]),
.data_bus(data_bus),
.addr_bus(addr_bus0),
.ram_re(cpu_ctrl_bus[0]),
.ram_we(cpu_ctrl_bus[1]),
.int_vec(int_num0),
.int_able(int_able[0]),
.syscall(syscall0),
.syscall_code(syscall_code0),
.init_addr(init_pc_cpu0),
.cpu_sel(~cpu_sel),
.lock_flag(cpu0_lock_flag),
.lock(cpu0_access_lock)
);
MBScore_cpu_top CPU1(
.state(state1),
.clk(clk),
.rst_n(~cpu1_en),
.pause(cpu_pause[1]),
.data_bus(data_bus),
.addr_bus(addr_bus1),
.ram_re(cpu_ctrl_bus[2]),
.ram_we(cpu_ctrl_bus[3]),
.int_vec(int_num1),
.int_able(int_able[1]),
.syscall(syscall1),
.syscall_code(syscall_code1),
.init_addr(init_pc_cpu1),
.cpu_sel(cpu_sel),
.lock_flag(cpu1_lock_flag),
.lock(cpu1_access_lock)
);
MBSsoc_ram RAM(
.clk(clk),
.ram_we(ctrl_bus[1]),
.ram_re(ctrl_bus[0]),
.addr(ram_addr),
.data(data_bus),
.wr_invalid(ctrl_bus[5])
);
MBSsoc_apic APIC(
.clk(clk),
.rst_n(rst_n),
.int_vec({8'd0,syscall1,syscall0,1'b0,5'd0}),
.int_able(int_able),
.int_num_out0(int_num0),
.int_num_out1(int_num1),
.syscall_code1(syscall_code1),
.syscall_code0(syscall_code0),
.cpu0_pc(init_pc_cpu0),
.cpu1_pc(init_pc_cpu1),
.cpu1_en(cpu1_en),
.ctrl_in(ctrl_bus[4:2]),
.data_in(data_bus)
);
MBSsoc_bus_ctrl BUS_CTRL(
.clk(bus_clk),
.rst_n(rst_n),
.cpu_ctrl_bus(cpu_ctrl_bus),
.addr_bus0(addr_bus0),
.addr_bus1(addr_bus1),
.cpu_pause(cpu_pause),
.ram_addr(ram_addr),
.cpu_sel_out(cpu_sel),
.ctrl_bus(ctrl_bus),
.lock({cpu1_access_lock,cpu0_access_lock}),
.lock_flag({cpu1_lock_flag,cpu0_lock_flag}),
.lock_addr_out(lock_addr_out)
);
endmodule | module MBSsoc_top(
input clk,rst_n,
output [`DATA_WIDTH-1:0] data_bus_out,
output [`ADDR_WIDTH-1:0] addr_bus_out,
output [`CTRL_BUS_WIDTH-1:0] ctrl_bus_out,
output cpu1_en_out,
output syscall0_out,
output [2:0] state0,state1,
output [`CORE_NUM-1:0] cpu_pause_out,
output cpu_sel_out,
output cpu0_lock_flag_out,
output [31:0] lock_addr_out
); |
wire [`DATA_WIDTH-1:0] data_bus;
wire [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,ram_addr;
wire [`CTRL_BUS_WIDTH-1:0] ctrl_bus;
wire [`INT_SEL_WIDTH-1:0] int_num0,int_num1;
wire [`CORE_NUM-1:0] int_able;
wire [`CORE_NUM-1:0] cpu_pause;
wire ram_re,ram_we;
wire syscall0,syscall1;
wire [`SYSCODE_WIDTH-1:0] syscall_code0,syscall_code1;
wire cpu1_en;
wire [`ADDR_WIDTH-1:0] init_pc_cpu1,init_pc_cpu0;
wire [3:0] cpu_ctrl_bus;
wire cpu_sel;
wire cpu0_access_lock,cpu1_access_lock;
wire cpu0_lock_flag,cpu1_lock_flag;
assign cpu1_en_out = cpu1_en;
assign syscall0_out = syscall0;
assign cpu_pause_out = cpu_pause;
assign cpu_sel_out = cpu_sel;
assign cpu0_lock_flag_out = cpu0_lock_flag;
reg bus_clk;
always @(clk)
bus_clk = clk;
assign data_bus_out = data_bus;
assign addr_bus_out = ram_addr;
assign ctrl_bus_out = ctrl_bus;
MBScore_cpu_top CPU0(
.state(state0),
.clk(clk),
.rst_n(rst_n),
.pause(cpu_pause[0]),
.data_bus(data_bus),
.addr_bus(addr_bus0),
.ram_re(cpu_ctrl_bus[0]),
.ram_we(cpu_ctrl_bus[1]),
.int_vec(int_num0),
.int_able(int_able[0]),
.syscall(syscall0),
.syscall_code(syscall_code0),
.init_addr(init_pc_cpu0),
.cpu_sel(~cpu_sel),
.lock_flag(cpu0_lock_flag),
.lock(cpu0_access_lock)
);
MBScore_cpu_top CPU1(
.state(state1),
.clk(clk),
.rst_n(~cpu1_en),
.pause(cpu_pause[1]),
.data_bus(data_bus),
.addr_bus(addr_bus1),
.ram_re(cpu_ctrl_bus[2]),
.ram_we(cpu_ctrl_bus[3]),
.int_vec(int_num1),
.int_able(int_able[1]),
.syscall(syscall1),
.syscall_code(syscall_code1),
.init_addr(init_pc_cpu1),
.cpu_sel(cpu_sel),
.lock_flag(cpu1_lock_flag),
.lock(cpu1_access_lock)
);
MBSsoc_ram RAM(
.clk(clk),
.ram_we(ctrl_bus[1]),
.ram_re(ctrl_bus[0]),
.addr(ram_addr),
.data(data_bus),
.wr_invalid(ctrl_bus[5])
);
MBSsoc_apic APIC(
.clk(clk),
.rst_n(rst_n),
.int_vec({8'd0,syscall1,syscall0,1'b0,5'd0}),
.int_able(int_able),
.int_num_out0(int_num0),
.int_num_out1(int_num1),
.syscall_code1(syscall_code1),
.syscall_code0(syscall_code0),
.cpu0_pc(init_pc_cpu0),
.cpu1_pc(init_pc_cpu1),
.cpu1_en(cpu1_en),
.ctrl_in(ctrl_bus[4:2]),
.data_in(data_bus)
);
MBSsoc_bus_ctrl BUS_CTRL(
.clk(bus_clk),
.rst_n(rst_n),
.cpu_ctrl_bus(cpu_ctrl_bus),
.addr_bus0(addr_bus0),
.addr_bus1(addr_bus1),
.cpu_pause(cpu_pause),
.ram_addr(ram_addr),
.cpu_sel_out(cpu_sel),
.ctrl_bus(ctrl_bus),
.lock({cpu1_access_lock,cpu0_access_lock}),
.lock_flag({cpu1_lock_flag,cpu0_lock_flag}),
.lock_addr_out(lock_addr_out)
);
endmodule | 0 |
2,690 | data/full_repos/permissive/100796583/cpu/MBScore_alu.v | 100,796,583 | MBScore_alu.v | v | 40 | 111 | [] | [] | [] | [(112, 150)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_in_a,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_in_b,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:7: Define or directive not defined: \'`ALU_OP_WIDTH\'\n input [`ALU_OP_WIDTH-1:0] alu_op_type,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:8: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] alu_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] alu_out_r;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:18: Define or directive not defined: \'`ALU_OP_ADD\'\n `ALU_OP_ADD: {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:18: syntax error, unexpected \':\', expecting endcase\n `ALU_OP_ADD: {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} + {1\'b0 + alu_in_b};\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:19: Define or directive not defined: \'`ALU_OP_ADDU\'\n `ALU_OP_ADDU: {cf_r,alu_out_r} <= {1\'b0,alu_in_a + alu_in_b};\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:20: Define or directive not defined: \'`ALU_OP_SUB\'\n `ALU_OP_SUB: {cf_r,alu_out_r} <= {1\'b0 + alu_in_a} - {1\'b0 + alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:21: Define or directive not defined: \'`ALU_OP_SUBU\'\n `ALU_OP_SUBU: {cf_r,alu_out_r} <= {1\'b0,alu_in_a - alu_in_b};\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:22: Define or directive not defined: \'`ALU_OP_AND\'\n `ALU_OP_AND: {cf_r,alu_out_r} <= {1\'b0,alu_in_a & alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:23: Define or directive not defined: \'`ALU_OP_OR\'\n `ALU_OP_OR: {cf_r,alu_out_r} <= {1\'b0,alu_in_a | alu_in_b};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:24: Define or directive not defined: \'`ALU_OP_XOR\'\n `ALU_OP_XOR: {cf_r,alu_out_r} <= {1\'b0,alu_in_a ^ alu_in_b};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:25: Define or directive not defined: \'`ALU_OP_NOR\'\n `ALU_OP_NOR: {cf_r,alu_out_r} <= {1\'b0,~(alu_in_a | alu_in_b)};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:26: Define or directive not defined: \'`ALU_OP_SLL\'\n `ALU_OP_SLL: {cf_r,alu_out_r} <= {1\'b0,alu_in_b << alu_in_a};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:27: Define or directive not defined: \'`ALU_OP_SRL\'\n `ALU_OP_SRL: {cf_r,alu_out_r} <= {1\'b0,alu_in_b >> alu_in_a};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:28: Define or directive not defined: \'`ALU_OP_SRA\'\n `ALU_OP_SRA: {cf_r,alu_out_r} <= {1\'b0,$signed(alu_in_b) >>> alu_in_a};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:29: Define or directive not defined: \'`ALU_OP_EQ\'\n `ALU_OP_EQ: {cf_r,alu_out_r} <= {1\'b0,(alu_in_a == alu_in_b) ? 32\'d1 : 32\'d0};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:30: Define or directive not defined: \'`ALU_OP_NE\'\n `ALU_OP_NE: {cf_r,alu_out_r} <= {1\'b0,(alu_in_a != alu_in_b) ? 32\'d1 : 32\'d0};\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:31: Define or directive not defined: \'`ALU_OP_LT\'\n `ALU_OP_LT: {cf_r,alu_out_r} <= {1\'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32\'d1 : 32\'d0}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:32: Define or directive not defined: \'`ALU_OP_LTU\'\n `ALU_OP_LTU: {cf_r,alu_out_r} <= {1\'b0,( alu_in_a < alu_in_b ) ? 32\'d1 : 32\'d0}; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu.v:40: syntax error, unexpected endmodule\nendmodule \n^~~~~~~~~\n%Error: Cannot continue\n' | 113 | module | module MBScore_alu(
input clk,
input rst_n,
input [`DATA_WIDTH-1:0] alu_in_a,
input [`DATA_WIDTH-1:0] alu_in_b,
input [`ALU_OP_WIDTH-1:0] alu_op_type,
output [`DATA_WIDTH-1:0] alu_out,
output cf
);
reg cf_r;
reg [`DATA_WIDTH-1:0] alu_out_r;
always @(negedge clk)
begin
case(alu_op_type)
`ALU_OP_ADD: {cf_r,alu_out_r} <= {1'b0 + alu_in_a} + {1'b0 + alu_in_b};
`ALU_OP_ADDU: {cf_r,alu_out_r} <= {1'b0,alu_in_a + alu_in_b};
`ALU_OP_SUB: {cf_r,alu_out_r} <= {1'b0 + alu_in_a} - {1'b0 + alu_in_b};
`ALU_OP_SUBU: {cf_r,alu_out_r} <= {1'b0,alu_in_a - alu_in_b};
`ALU_OP_AND: {cf_r,alu_out_r} <= {1'b0,alu_in_a & alu_in_b};
`ALU_OP_OR: {cf_r,alu_out_r} <= {1'b0,alu_in_a | alu_in_b};
`ALU_OP_XOR: {cf_r,alu_out_r} <= {1'b0,alu_in_a ^ alu_in_b};
`ALU_OP_NOR: {cf_r,alu_out_r} <= {1'b0,~(alu_in_a | alu_in_b)};
`ALU_OP_SLL: {cf_r,alu_out_r} <= {1'b0,alu_in_b << alu_in_a};
`ALU_OP_SRL: {cf_r,alu_out_r} <= {1'b0,alu_in_b >> alu_in_a};
`ALU_OP_SRA: {cf_r,alu_out_r} <= {1'b0,$signed(alu_in_b) >>> alu_in_a};
`ALU_OP_EQ: {cf_r,alu_out_r} <= {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0};
`ALU_OP_NE: {cf_r,alu_out_r} <= {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0};
`ALU_OP_LT: {cf_r,alu_out_r} <= {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0};
`ALU_OP_LTU: {cf_r,alu_out_r} <= {1'b0,( alu_in_a < alu_in_b ) ? 32'd1 : 32'd0};
default: {cf_r,alu_out_r} <= {1'b0,alu_out_r};
endcase
end
assign cf = cf_r;
assign alu_out = alu_out_r;
endmodule | module MBScore_alu(
input clk,
input rst_n,
input [`DATA_WIDTH-1:0] alu_in_a,
input [`DATA_WIDTH-1:0] alu_in_b,
input [`ALU_OP_WIDTH-1:0] alu_op_type,
output [`DATA_WIDTH-1:0] alu_out,
output cf
); |
reg cf_r;
reg [`DATA_WIDTH-1:0] alu_out_r;
always @(negedge clk)
begin
case(alu_op_type)
`ALU_OP_ADD: {cf_r,alu_out_r} <= {1'b0 + alu_in_a} + {1'b0 + alu_in_b};
`ALU_OP_ADDU: {cf_r,alu_out_r} <= {1'b0,alu_in_a + alu_in_b};
`ALU_OP_SUB: {cf_r,alu_out_r} <= {1'b0 + alu_in_a} - {1'b0 + alu_in_b};
`ALU_OP_SUBU: {cf_r,alu_out_r} <= {1'b0,alu_in_a - alu_in_b};
`ALU_OP_AND: {cf_r,alu_out_r} <= {1'b0,alu_in_a & alu_in_b};
`ALU_OP_OR: {cf_r,alu_out_r} <= {1'b0,alu_in_a | alu_in_b};
`ALU_OP_XOR: {cf_r,alu_out_r} <= {1'b0,alu_in_a ^ alu_in_b};
`ALU_OP_NOR: {cf_r,alu_out_r} <= {1'b0,~(alu_in_a | alu_in_b)};
`ALU_OP_SLL: {cf_r,alu_out_r} <= {1'b0,alu_in_b << alu_in_a};
`ALU_OP_SRL: {cf_r,alu_out_r} <= {1'b0,alu_in_b >> alu_in_a};
`ALU_OP_SRA: {cf_r,alu_out_r} <= {1'b0,$signed(alu_in_b) >>> alu_in_a};
`ALU_OP_EQ: {cf_r,alu_out_r} <= {1'b0,(alu_in_a == alu_in_b) ? 32'd1 : 32'd0};
`ALU_OP_NE: {cf_r,alu_out_r} <= {1'b0,(alu_in_a != alu_in_b) ? 32'd1 : 32'd0};
`ALU_OP_LT: {cf_r,alu_out_r} <= {1'b0,( $signed(alu_in_a) < $signed(alu_in_b) ) ? 32'd1 : 32'd0};
`ALU_OP_LTU: {cf_r,alu_out_r} <= {1'b0,( alu_in_a < alu_in_b ) ? 32'd1 : 32'd0};
default: {cf_r,alu_out_r} <= {1'b0,alu_out_r};
endcase
end
assign cf = cf_r;
assign alu_out = alu_out_r;
endmodule | 0 |
2,691 | data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v | 100,796,583 | MBScore_alu_operator_mux.v | v | 32 | 70 | [] | [] | [] | [(113, 139)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:6: Define or directive not defined: \'`IMM_WIDTH\'\n input [`IMM_WIDTH-1:0] imm,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:7: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n input [`ALU_SEL_WIDTH-1:0] alu_sel_a,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:8: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n input [`ALU_SEL_WIDTH-1:0] alu_sel_b,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] rs,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] rt,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] alu_a,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] alu_b\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] alu_a_r,alu_b_r;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:21: Define or directive not defined: \'`ALU_SEL_IMM\'\n alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16\'b0,imm} : rs;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:21: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16\'b0,imm} : rs;\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:22: Define or directive not defined: \'`ALU_SEL_IMM\'\n alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16\'b0,imm} : rt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_alu_operator_mux.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16\'b0,imm} : rt;\n ^\n%Error: Exiting due to 13 error(s)\n' | 114 | module | module MBScore_alu_operator_mux(
input clk,
input alu_mux_ack,
input [`IMM_WIDTH-1:0] imm,
input [`ALU_SEL_WIDTH-1:0] alu_sel_a,
input [`ALU_SEL_WIDTH-1:0] alu_sel_b,
input [`DATA_WIDTH-1:0] rs,
input [`DATA_WIDTH-1:0] rt,
output [`DATA_WIDTH-1:0] alu_a,
output [`DATA_WIDTH-1:0] alu_b
);
reg [`DATA_WIDTH-1:0] alu_a_r,alu_b_r;
always @(negedge clk)
begin
if(alu_mux_ack)
begin
alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16'b0,imm} : rs;
alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16'b0,imm} : rt;
end
end
assign alu_a = alu_a_r;
assign alu_b = alu_b_r;
endmodule | module MBScore_alu_operator_mux(
input clk,
input alu_mux_ack,
input [`IMM_WIDTH-1:0] imm,
input [`ALU_SEL_WIDTH-1:0] alu_sel_a,
input [`ALU_SEL_WIDTH-1:0] alu_sel_b,
input [`DATA_WIDTH-1:0] rs,
input [`DATA_WIDTH-1:0] rt,
output [`DATA_WIDTH-1:0] alu_a,
output [`DATA_WIDTH-1:0] alu_b
); |
reg [`DATA_WIDTH-1:0] alu_a_r,alu_b_r;
always @(negedge clk)
begin
if(alu_mux_ack)
begin
alu_a_r <= (alu_sel_a == `ALU_SEL_IMM)? {16'b0,imm} : rs;
alu_b_r <= (alu_sel_b == `ALU_SEL_IMM)? {16'b0,imm} : rt;
end
end
assign alu_a = alu_a_r;
assign alu_b = alu_b_r;
endmodule | 0 |
2,692 | data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v | 100,796,583 | MBScore_bus_ctrl.v | v | 28 | 67 | [] | [] | [] | [(112, 138)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:4: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] data_wr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:5: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH-1:0] inst_addr,data_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:9: Define or directive not defined: \'`ADDR_WIDTH\'\n output [`ADDR_WIDTH-1:0] addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] data_rd,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n inout [`DATA_WIDTH-1:0] data\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] data_r;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_bus_ctrl.v:20: Define or directive not defined: \'`DATA_WIDTH\'\n assign data = (ram_we == 1\'b1) ? data_wr : `DATA_WIDTH\'bz;\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 115 | module | module MBScore_bus_ctrl(
input clk,
input [`DATA_WIDTH-1:0] data_wr,
input [`ADDR_WIDTH-1:0] inst_addr,data_addr,
input data_sel,
input inst_re,data_re,data_we,
input cpu_sel,
output [`ADDR_WIDTH-1:0] addr,
output ram_re,ram_we,
output [`DATA_WIDTH-1:0] data_rd,
inout [`DATA_WIDTH-1:0] data
);
assign addr = (data_sel == 1'b1)? data_addr : inst_addr;
assign ram_we = data_we;
assign ram_re = inst_re | data_re;
reg [`DATA_WIDTH-1:0] data_r;
assign data = (ram_we == 1'b1) ? data_wr : `DATA_WIDTH'bz;
always @(data)
if(ram_re && cpu_sel)
data_r = data;
assign data_rd = data_r;
endmodule | module MBScore_bus_ctrl(
input clk,
input [`DATA_WIDTH-1:0] data_wr,
input [`ADDR_WIDTH-1:0] inst_addr,data_addr,
input data_sel,
input inst_re,data_re,data_we,
input cpu_sel,
output [`ADDR_WIDTH-1:0] addr,
output ram_re,ram_we,
output [`DATA_WIDTH-1:0] data_rd,
inout [`DATA_WIDTH-1:0] data
); |
assign addr = (data_sel == 1'b1)? data_addr : inst_addr;
assign ram_we = data_we;
assign ram_re = inst_re | data_re;
reg [`DATA_WIDTH-1:0] data_r;
assign data = (ram_we == 1'b1) ? data_wr : `DATA_WIDTH'bz;
always @(data)
if(ram_re && cpu_sel)
data_r = data;
assign data_rd = data_r;
endmodule | 0 |
2,693 | data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v | 100,796,583 | MBScore_cpu_top.v | v | 180 | 126 | [] | [] | [] | [(113, 289)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n inout [`DATA_WIDTH-1:0] data_bus,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n input [`INT_SEL_WIDTH-1:0] int_vec,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:8: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH-1:0] init_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n output [`ADDR_WIDTH-1:0] addr_bus,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:16: Define or directive not defined: \'`SYSCODE_WIDTH\'\n output [`SYSCODE_WIDTH-1:0] syscall_code,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:20: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n wire [`ALU_SEL_WIDTH-1:0] alu_sel_a,alu_sel_b;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:21: Define or directive not defined: \'`ALU_OP_WIDTH\'\n wire [`ALU_OP_WIDTH-1:0] alu_op_type;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:23: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n wire [`REG_ADDR_WIDTH-1:0] rs_addr,rt_addr,rd_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:25: Define or directive not defined: \'`IMM_WIDTH\'\n wire [`IMM_WIDTH-1:0] imm;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:26: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] rs_data,rt_data,alu_a,alu_b,alu_out;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:27: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH-1:0] inst_mem_addr,data_mem_addr,int_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:28: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] inst;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:32: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] rf_data_in;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:40: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] spr_temp;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:45: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] data_from_bus;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:46: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH-1:0] inst_addr,data_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: Define or directive not defined: \'`OPCODE_LW\'\n assign data_addr = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign data_addr = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:47: Define or directive not defined: \'`OPCODE_SW\'\n assign data_addr = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: Define or directive not defined: \'`OPCODE_STREX\'\n assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:52: Define or directive not defined: \'`OPCODE_LDREX\'\n assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1\'b1 : 1\'b0;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:133: Define or directive not defined: \'`OPCODE_STREX\'\n .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31\'b0,lock_flag} : alu_out ),\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_cpu_top.v:133: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n .alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31\'b0,lock_flag} : alu_out ),\n ^\n%Error: Exiting due to 25 error(s)\n' | 117 | module | module MBScore_cpu_top(
input clk,rst_n,
inout [`DATA_WIDTH-1:0] data_bus,
input [`INT_SEL_WIDTH-1:0] int_vec,
input pause,
input [`ADDR_WIDTH-1:0] init_addr,
input cpu_sel,
input lock_flag,
output lock,
output [`ADDR_WIDTH-1:0] addr_bus,
output ram_re,ram_we,
output int_able,
output syscall,
output [`SYSCODE_WIDTH-1:0] syscall_code,
output [2:0] state
);
wire [`ALU_SEL_WIDTH-1:0] alu_sel_a,alu_sel_b;
wire [`ALU_OP_WIDTH-1:0] alu_op_type;
wire alu_mux_ack;
wire [`REG_ADDR_WIDTH-1:0] rs_addr,rt_addr,rd_addr;
wire reg_we,spr_sel,next,JAL_or_J,BEQ_or_BNE,JR,hlt;
wire [`IMM_WIDTH-1:0] imm;
wire [`DATA_WIDTH-1:0] rs_data,rt_data,alu_a,alu_b,alu_out;
wire [`ADDR_WIDTH-1:0] inst_mem_addr,data_mem_addr,int_addr;
wire [`DATA_WIDTH-1:0] inst;
wire IR_ack;
wire pc_we;
wire data_mem_we;
wire [`DATA_WIDTH-1:0] rf_data_in;
wire mem_to_reg_we;
wire LUI;
wire stop;
wire setINTR;
wire int_jump;
wire cf;
wire int_en_n;
wire [`DATA_WIDTH-1:0] spr_temp;
wire data_mem_re;
wire rf_clk,bus_clk;
wire inst_re;
wire [`DATA_WIDTH-1:0] data_from_bus;
wire [`ADDR_WIDTH-1:0] inst_addr,data_addr;
assign data_addr = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;
assign inst_out = inst;
assign int_able = ~int_en_n;
assign syscall_code = inst[25:6];
assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1'b1 : 1'b0;
MBScore_bus_ctrl bus_ctrl(
.clk(bus_clk),
.inst_addr(inst_addr),
.data_addr(data_addr),
.data_sel(data_mem_re | data_mem_we),
.inst_re(inst_re),
.data_re(data_mem_re),
.data_we(data_mem_we),
.addr(addr_bus),
.data_rd(data_from_bus),
.data_wr(rt_data),
.ram_re(ram_re),
.ram_we(ram_we),
.data(data_bus),
.cpu_sel(cpu_sel)
);
MBScore_ctrl ctrl(
.state(state),
.clk(clk),
.rst_n(rst_n),
.inst(inst),
.IR_ack(IR_ack),
.alu_sel_a(alu_sel_a),
.alu_sel_b(alu_sel_b),
.alu_op_type(alu_op_type),
.alu_mux_ack(alu_mux_ack),
.rs_addr(rs_addr),
.rd_addr(rd_addr),
.rt_addr(rt_addr),
.reg_we(reg_we),
.spr_sel(spr_sel),
.imm(imm),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.next(next),
.pc_we(pc_we),
.mem_we(data_mem_we),
.mem_re(data_mem_re),
.inst_re(inst_re),
.mem_to_reg_we(mem_to_reg_we),
.LUI(LUI),
.stop(stop),
.pause(pause),
.syscall(syscall),
.rf_clk(rf_clk),
.bus_clk(bus_clk)
);
MBScore_IR IR(
.clk(clk),
.rst_n(rst_n),
.IR_ack(IR_ack),
.next(next),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.jump(alu_out[0]),
.next_addr(rs_data),
.int_addr(int_addr),
.inst_in(data_from_bus),
.inst_out(inst),
.pc_out(inst_addr),
.int_jump(int_jump),
.init_addr(init_addr)
);
MBScore_rf rf(
.clk(rf_clk),
.rst_n(rst_n),
.rs_addr(rs_addr),
.rd_addr(rd_addr),
.rt_addr(rt_addr),
.reg_we(reg_we),
.mem_to_reg_we(mem_to_reg_we),
.spr_sel(spr_sel),
.alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31'b0,lock_flag} : alu_out ),
.mem_data_in(data_from_bus),
.rs_out(rs_data),
.rt_out(rt_data),
.pc_we(pc_we),
.pc_in(inst_addr),
.LUI(LUI),
.setINTR(setINTR),
.int_en_n(int_en_n),
.spr_out(spr_temp),
.spr_in(spr_temp)
);
MBScore_alu_operator_mux alu_op_mux(
.clk(clk),
.alu_mux_ack(alu_mux_ack),
.imm(imm),
.alu_sel_a(alu_sel_a),
.alu_sel_b(alu_sel_b),
.rs(rs_data),
.rt(rt_data),
.alu_a(alu_a),
.alu_b(alu_b)
);
MBScore_alu alu(
.clk(clk),
.rst_n(rst_n),
.alu_in_a(alu_a),
.alu_in_b(alu_b),
.alu_op_type(alu_op_type),
.alu_out(alu_out),
.cf(cf)
);
MBScore_interrupt_ctrl int_ctrl(
.clk(clk),
.rst_n(rst_n),
.int_vec(int_vec),
.int_en_n(int_en_n),
.stop(stop),
.setINTR(setINTR),
.int_addr(int_addr),
.int_jump(int_jump)
);
endmodule | module MBScore_cpu_top(
input clk,rst_n,
inout [`DATA_WIDTH-1:0] data_bus,
input [`INT_SEL_WIDTH-1:0] int_vec,
input pause,
input [`ADDR_WIDTH-1:0] init_addr,
input cpu_sel,
input lock_flag,
output lock,
output [`ADDR_WIDTH-1:0] addr_bus,
output ram_re,ram_we,
output int_able,
output syscall,
output [`SYSCODE_WIDTH-1:0] syscall_code,
output [2:0] state
); |
wire [`ALU_SEL_WIDTH-1:0] alu_sel_a,alu_sel_b;
wire [`ALU_OP_WIDTH-1:0] alu_op_type;
wire alu_mux_ack;
wire [`REG_ADDR_WIDTH-1:0] rs_addr,rt_addr,rd_addr;
wire reg_we,spr_sel,next,JAL_or_J,BEQ_or_BNE,JR,hlt;
wire [`IMM_WIDTH-1:0] imm;
wire [`DATA_WIDTH-1:0] rs_data,rt_data,alu_a,alu_b,alu_out;
wire [`ADDR_WIDTH-1:0] inst_mem_addr,data_mem_addr,int_addr;
wire [`DATA_WIDTH-1:0] inst;
wire IR_ack;
wire pc_we;
wire data_mem_we;
wire [`DATA_WIDTH-1:0] rf_data_in;
wire mem_to_reg_we;
wire LUI;
wire stop;
wire setINTR;
wire int_jump;
wire cf;
wire int_en_n;
wire [`DATA_WIDTH-1:0] spr_temp;
wire data_mem_re;
wire rf_clk,bus_clk;
wire inst_re;
wire [`DATA_WIDTH-1:0] data_from_bus;
wire [`ADDR_WIDTH-1:0] inst_addr,data_addr;
assign data_addr = (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_SW) ? rs_data + $signed(inst[15:0]) : rs_data;
assign inst_out = inst;
assign int_able = ~int_en_n;
assign syscall_code = inst[25:6];
assign lock = ((inst[31:26] == `OPCODE_STREX || inst[31:26] == `OPCODE_LDREX) && (~inst_re) )? 1'b1 : 1'b0;
MBScore_bus_ctrl bus_ctrl(
.clk(bus_clk),
.inst_addr(inst_addr),
.data_addr(data_addr),
.data_sel(data_mem_re | data_mem_we),
.inst_re(inst_re),
.data_re(data_mem_re),
.data_we(data_mem_we),
.addr(addr_bus),
.data_rd(data_from_bus),
.data_wr(rt_data),
.ram_re(ram_re),
.ram_we(ram_we),
.data(data_bus),
.cpu_sel(cpu_sel)
);
MBScore_ctrl ctrl(
.state(state),
.clk(clk),
.rst_n(rst_n),
.inst(inst),
.IR_ack(IR_ack),
.alu_sel_a(alu_sel_a),
.alu_sel_b(alu_sel_b),
.alu_op_type(alu_op_type),
.alu_mux_ack(alu_mux_ack),
.rs_addr(rs_addr),
.rd_addr(rd_addr),
.rt_addr(rt_addr),
.reg_we(reg_we),
.spr_sel(spr_sel),
.imm(imm),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.next(next),
.pc_we(pc_we),
.mem_we(data_mem_we),
.mem_re(data_mem_re),
.inst_re(inst_re),
.mem_to_reg_we(mem_to_reg_we),
.LUI(LUI),
.stop(stop),
.pause(pause),
.syscall(syscall),
.rf_clk(rf_clk),
.bus_clk(bus_clk)
);
MBScore_IR IR(
.clk(clk),
.rst_n(rst_n),
.IR_ack(IR_ack),
.next(next),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.jump(alu_out[0]),
.next_addr(rs_data),
.int_addr(int_addr),
.inst_in(data_from_bus),
.inst_out(inst),
.pc_out(inst_addr),
.int_jump(int_jump),
.init_addr(init_addr)
);
MBScore_rf rf(
.clk(rf_clk),
.rst_n(rst_n),
.rs_addr(rs_addr),
.rd_addr(rd_addr),
.rt_addr(rt_addr),
.reg_we(reg_we),
.mem_to_reg_we(mem_to_reg_we),
.spr_sel(spr_sel),
.alu_data_in( (inst[31:26] == `OPCODE_STREX ) ? {31'b0,lock_flag} : alu_out ),
.mem_data_in(data_from_bus),
.rs_out(rs_data),
.rt_out(rt_data),
.pc_we(pc_we),
.pc_in(inst_addr),
.LUI(LUI),
.setINTR(setINTR),
.int_en_n(int_en_n),
.spr_out(spr_temp),
.spr_in(spr_temp)
);
MBScore_alu_operator_mux alu_op_mux(
.clk(clk),
.alu_mux_ack(alu_mux_ack),
.imm(imm),
.alu_sel_a(alu_sel_a),
.alu_sel_b(alu_sel_b),
.rs(rs_data),
.rt(rt_data),
.alu_a(alu_a),
.alu_b(alu_b)
);
MBScore_alu alu(
.clk(clk),
.rst_n(rst_n),
.alu_in_a(alu_a),
.alu_in_b(alu_b),
.alu_op_type(alu_op_type),
.alu_out(alu_out),
.cf(cf)
);
MBScore_interrupt_ctrl int_ctrl(
.clk(clk),
.rst_n(rst_n),
.int_vec(int_vec),
.int_en_n(int_en_n),
.stop(stop),
.setINTR(setINTR),
.int_addr(int_addr),
.int_jump(int_jump)
);
endmodule | 0 |
2,694 | data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v | 100,796,583 | MBScore_ctrl.v | v | 335 | 123 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:2: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:8: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] inst,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:10: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:11: Define or directive not defined: \'`ALU_SEL_WIDTH\'\n output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:12: Define or directive not defined: \'`ALU_OP_WIDTH\'\n output reg [`ALU_OP_WIDTH-1:0] alu_op_type,\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:14: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rs_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:15: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rd_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:16: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n output [`REG_ADDR_WIDTH-1:0] rt_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:18: Define or directive not defined: \'`IMM_WIDTH\'\n output [`IMM_WIDTH-1:0] imm,\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:32: Define or directive not defined: \'`OPCODE_ADDI\'\n assign rd_addr = ( inst[31:26] == `OPCODE_ADDI || inst[31:26] == `OPCODE_ADDIU ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:32: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n assign rd_addr = ( inst[31:26] == `OPCODE_ADDI || inst[31:26] == `OPCODE_ADDIU ||\n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:32: Define or directive not defined: \'`OPCODE_ADDIU\'\n assign rd_addr = ( inst[31:26] == `OPCODE_ADDI || inst[31:26] == `OPCODE_ADDIU ||\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:33: Define or directive not defined: \'`OPCODE_ANDI\'\n inst[31:26] == `OPCODE_ANDI || inst[31:26] == `OPCODE_SLTI ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:33: Define or directive not defined: \'`OPCODE_SLTI\'\n inst[31:26] == `OPCODE_ANDI || inst[31:26] == `OPCODE_SLTI ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:34: Define or directive not defined: \'`OPCODE_SLTIU\'\n inst[31:26] == `OPCODE_SLTIU || inst[31:26] == `OPCODE_ORI ||\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:34: Define or directive not defined: \'`OPCODE_ORI\'\n inst[31:26] == `OPCODE_SLTIU || inst[31:26] == `OPCODE_ORI ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:35: Define or directive not defined: \'`OPCODE_XORI\'\n inst[31:26] == `OPCODE_XORI || inst[31:26] == `OPCODE_LUI ||\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:35: Define or directive not defined: \'`OPCODE_LUI\'\n inst[31:26] == `OPCODE_XORI || inst[31:26] == `OPCODE_LUI ||\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:36: Define or directive not defined: \'`OPCODE_LW\'\n inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX)? inst[20:16] : inst[15:11];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:36: Define or directive not defined: \'`OPCODE_LDREX\'\n inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX)? inst[20:16] : inst[15:11];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:37: Define or directive not defined: \'`OPCODE_CALC\'\n assign imm = ( inst[31:26] == `OPCODE_CALC && \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:37: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n assign imm = ( inst[31:26] == `OPCODE_CALC && \n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:38: Define or directive not defined: \'`FUNCT_SLL\'\n (inst[5:0] == `FUNCT_SLL || inst[5:0] == `FUNCT_SRA || inst[5:0] == `FUNCT_SRL) ) ? {11\'d0,inst[10:6]} : inst[15:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:38: Define or directive not defined: \'`FUNCT_SRA\'\n (inst[5:0] == `FUNCT_SLL || inst[5:0] == `FUNCT_SRA || inst[5:0] == `FUNCT_SRL) ) ? {11\'d0,inst[10:6]} : inst[15:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:38: Define or directive not defined: \'`FUNCT_SRL\'\n (inst[5:0] == `FUNCT_SLL || inst[5:0] == `FUNCT_SRA || inst[5:0] == `FUNCT_SRL) ) ? {11\'d0,inst[10:6]} : inst[15:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:50: Define or directive not defined: \'`ID\'\n if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:50: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )\n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:50: Define or directive not defined: \'`OPCODE_LW\'\n if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:50: Define or directive not defined: \'`OPCODE_LDREX\'\n if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:55: Define or directive not defined: \'`ID\'\n if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:55: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )\n ^~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:55: Define or directive not defined: \'`OPCODE_SW\'\n if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:55: Define or directive not defined: \'`OPCODE_STREX\'\n if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:60: Define or directive not defined: \'`IF\'\n if( nextState == `IF)\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:60: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if( nextState == `IF)\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:71: Define or directive not defined: \'`WAIT\'\n curState <= `WAIT;\n ^~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n curState <= `WAIT;\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:75: Define or directive not defined: \'`IDLE\'\n curState <= `IDLE;\n ^~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n curState <= `IDLE;\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:85: Define or directive not defined: \'`WAIT\'\n `WAIT: nextState <= `IDLE;\n ^~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:85: syntax error, unexpected \':\', expecting endcase\n `WAIT: nextState <= `IDLE;\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:85: Define or directive not defined: \'`IDLE\'\n `WAIT: nextState <= `IDLE;\n ^~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:86: Define or directive not defined: \'`IDLE\'\n `IDLE: nextState <= `IF;\n ^~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:86: Define or directive not defined: \'`IF\'\n `IDLE: nextState <= `IF;\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:87: Define or directive not defined: \'`IF\'\n `IF: nextState <= `ID;\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:87: Define or directive not defined: \'`ID\'\n `IF: nextState <= `ID;\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:88: Define or directive not defined: \'`ID\'\n `ID:\n ^~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:90: Define or directive not defined: \'`OPCODE_J\'\n if(inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_HLT\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:90: Define or directive not defined: \'`OPCODE_HLT\'\n if(inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_HLT\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_ctrl.v:91: Define or directive not defined: \'`OPCODE_SPECIAL\'\n || (inst[31:26] == `OPCODE_SPECIAL && inst[5:0] == `FUNCT_SYSCALL) )\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 118 | module | module MBScore_ctrl(
input clk,
input rst_n,
input stop,pause,
input [`DATA_WIDTH-1:0] inst,
output reg IR_ack,
output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a,
output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b,
output reg [`ALU_OP_WIDTH-1:0] alu_op_type,
output reg alu_mux_ack,
output [`REG_ADDR_WIDTH-1:0] rs_addr,
output [`REG_ADDR_WIDTH-1:0] rd_addr,
output [`REG_ADDR_WIDTH-1:0] rt_addr,
output reg reg_we,spr_sel,pc_we,
output [`IMM_WIDTH-1:0] imm,
output reg JAL_or_J,BEQ_or_BNE,JR,hlt,next,LUI,
output reg mem_we,mem_re,mem_to_reg_we,inst_re,
output reg syscall,
output reg rf_clk,bus_clk,
output reg set_lock_flag,
output [3:0] state
);
reg [3:0] curState,nextState;
reg [3:0] lastState;
assign state = curState;
assign rs_addr = inst[25:21];
assign rt_addr = inst[20:16];
assign rd_addr = ( inst[31:26] == `OPCODE_ADDI || inst[31:26] == `OPCODE_ADDIU ||
inst[31:26] == `OPCODE_ANDI || inst[31:26] == `OPCODE_SLTI ||
inst[31:26] == `OPCODE_SLTIU || inst[31:26] == `OPCODE_ORI ||
inst[31:26] == `OPCODE_XORI || inst[31:26] == `OPCODE_LUI ||
inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX)? inst[20:16] : inst[15:11];
assign imm = ( inst[31:26] == `OPCODE_CALC &&
(inst[5:0] == `FUNCT_SLL || inst[5:0] == `FUNCT_SRA || inst[5:0] == `FUNCT_SRL) ) ? {11'd0,inst[10:6]} : inst[15:0];
always @(clk)
begin
rf_clk <= clk;
bus_clk <= clk;
end
always @(clk or nextState)
if(!clk)
begin
if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )
mem_re = 1'b1;
else
mem_re = 1'b0;
if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )
mem_we = 1'b1;
else
mem_we = 1'b0;
if( nextState == `IF)
inst_re = 1'b1;
else
inst_re = 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
curState <= `WAIT;
end
else
if(stop)
curState <= `IDLE;
else
curState <= nextState;
end
always @(curState or inst or pause)
begin
if(pause) nextState <= curState;
else
case(curState)
`WAIT: nextState <= `IDLE;
`IDLE: nextState <= `IF;
`IF: nextState <= `ID;
`ID:
begin
if(inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_HLT
|| (inst[31:26] == `OPCODE_SPECIAL && inst[5:0] == `FUNCT_SYSCALL) )
nextState <= `IF;
else
nextState <= `EXE;
end
`EXE:
begin
if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR)
|| inst[31:26] == `OPCODE_JAL
|| (inst[31:26] == `OPCODE_SPECIAL && inst[5:0] == `FUNCT_SPRWR) )
nextState <= `IF;
else
nextState <= `WB;
end
`WB: nextState <= `IF;
default: nextState <= nextState;
endcase
end
always @(curState)
begin
if(!rst_n)
begin
IR_ack <= 0;
alu_sel_a <= 0;
alu_sel_b <= 0;
alu_op_type <= 0;
JAL_or_J <= 0;
BEQ_or_BNE <= 0;
JR <= 0;
hlt <= 0;
next <= 0;
reg_we <= 0;
spr_sel <= 0;
alu_mux_ack <= 0;
pc_we <= 0;
mem_to_reg_we <= 0;
LUI <= 0;
syscall <= 0;
set_lock_flag <= 0;
end
begin
IR_ack <= 0;
alu_sel_a <= 0;
alu_sel_b <= 0;
alu_op_type <= 0;
JAL_or_J <= 0;
BEQ_or_BNE <= 0;
JR <= 0;
hlt <= 0;
next <= 0;
reg_we <= 0;
spr_sel <= 0;
alu_mux_ack <= 0;
pc_we <= 0;
mem_to_reg_we <= 0;
LUI <= 0;
syscall <= 0;
set_lock_flag <= 0;
if(curState == `IF)
IR_ack <= 1'b1;
if(curState == `ID)
begin
case(inst[31:26])
`OPCODE_CALC:
begin
case(inst[5:0])
`FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,
`FUNCT_OR,`FUNCT_XOR,`FUNCT_NOR,`FUNCT_SLT,`FUNCT_SLTU,
`FUNCT_SLLV,`FUNCT_SRLV,`FUNCT_SRAV:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
`FUNCT_SLL,`FUNCT_SRL,`FUNCT_SRA:
begin
alu_sel_a <= `ALU_SEL_IMM;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
default: ;
endcase
end
`OPCODE_ADDI,`OPCODE_ADDIU,`OPCODE_ANDI,`OPCODE_ORI,
`OPCODE_XORI,`OPCODE_SLTI,`OPCODE_SLTIU:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_IMM;
alu_mux_ack <= 1'b1;
end
`OPCODE_BEQ,`OPCODE_BNE:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
`OPCODE_LUI:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_IMM;
alu_mux_ack <= 1'b1;
end
`OPCODE_HLT:
begin
hlt <= 1'b1;
next <= 1'b1;
end
`OPCODE_J:
begin
JAL_or_J <= 1'b1;
next <= 1'b1;
end
`OPCODE_JAL:
begin
reg_we <= 1'b1;
pc_we <= 1'b1;
end
`OPCODE_SPECIAL:
begin
if(inst[5:0] == `FUNCT_SYSCALL)
begin
syscall <= 1'b1;
next <= 1'b1;
end
if(inst[5:0] == `FUNCT_SPRRD)
begin
spr_sel <= 1'b1;
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
if(inst[5:0] == `FUNCT_SPRWR)
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
end
default: ;
endcase
end
if(curState == `EXE)
begin
case(inst[31:26])
`OPCODE_JAL:
begin
JAL_or_J <= 1'b1;
next <= 1'b1;
end
`OPCODE_LW,`OPCODE_LDREX: mem_to_reg_we <= 1'b1;
`OPCODE_STREX:
begin
reg_we <= 1'b1;
set_lock_flag <= 1'b1;
end
`OPCODE_CALC:
begin
case(inst[5:0])
`FUNCT_ADD : alu_op_type <= `ALU_OP_ADD;
`FUNCT_ADDU : alu_op_type <= `ALU_OP_ADDU;
`FUNCT_SUB : alu_op_type <= `ALU_OP_SUB;
`FUNCT_SUBU : alu_op_type <= `ALU_OP_SUBU;
`FUNCT_AND : alu_op_type <= `ALU_OP_AND;
`FUNCT_OR : alu_op_type <= `ALU_OP_OR;
`FUNCT_XOR : alu_op_type <= `ALU_OP_XOR;
`FUNCT_NOR : alu_op_type <= `ALU_OP_NOR;
`FUNCT_SLT : alu_op_type <= `ALU_OP_LT;
`FUNCT_SLTU : alu_op_type <= `ALU_OP_LTU;
`FUNCT_SLLV,`FUNCT_SLL : alu_op_type <= `ALU_OP_SLL;
`FUNCT_SRLV,`FUNCT_SRL : alu_op_type <= `ALU_OP_SRL;
`FUNCT_SRAV,`FUNCT_SRA : alu_op_type <= `ALU_OP_SRA;
`FUNCT_JR:
begin
JR <= 1'b1;
next <= 1'b1;
end
default:;
endcase
end
`OPCODE_ADDI : alu_op_type <= `ALU_OP_ADD;
`OPCODE_ADDIU : alu_op_type <= `ALU_OP_ADDU;
`OPCODE_ANDI : alu_op_type <= `ALU_OP_AND;
`OPCODE_ORI : alu_op_type <= `ALU_OP_OR;
`OPCODE_XORI : alu_op_type <= `ALU_OP_XOR;
`OPCODE_BEQ : alu_op_type <= `ALU_OP_EQ;
`OPCODE_BNE : alu_op_type <= `ALU_OP_NE;
`OPCODE_SLTI : alu_op_type <= `ALU_OP_LT;
`OPCODE_SLTIU : alu_op_type <= `ALU_OP_LTU;
`OPCODE_LUI : alu_op_type <= `ALU_OP_ADDU;
`OPCODE_SPECIAL : if(inst[5:0] == `FUNCT_SPRRD)
alu_op_type <= `ALU_OP_ADDU;
else
if(inst[5:0] == `FUNCT_SPRWR)
begin
spr_sel <= 1'b1;
reg_we <= 1'b1;
next <= 1'b1;
end
default:;
endcase
end
if(curState == `WB)
begin
if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE)
begin
BEQ_or_BNE <= 1'b1;
end
else
begin
if(inst[31:26] == `OPCODE_LUI)
LUI <= 1'b1;
if(inst[31:26] != `OPCODE_SW && inst[31:26] != `OPCODE_LW &&
inst[31:26] != `OPCODE_LDREX && inst[31:26] != `OPCODE_STREX)
begin
spr_sel <= 1'b0;
reg_we <= 1'b1;
end
end
next <= 1'b1;
end
end
end
endmodule | module MBScore_ctrl(
input clk,
input rst_n,
input stop,pause,
input [`DATA_WIDTH-1:0] inst,
output reg IR_ack,
output reg [`ALU_SEL_WIDTH-1:0] alu_sel_a,
output reg [`ALU_SEL_WIDTH-1:0] alu_sel_b,
output reg [`ALU_OP_WIDTH-1:0] alu_op_type,
output reg alu_mux_ack,
output [`REG_ADDR_WIDTH-1:0] rs_addr,
output [`REG_ADDR_WIDTH-1:0] rd_addr,
output [`REG_ADDR_WIDTH-1:0] rt_addr,
output reg reg_we,spr_sel,pc_we,
output [`IMM_WIDTH-1:0] imm,
output reg JAL_or_J,BEQ_or_BNE,JR,hlt,next,LUI,
output reg mem_we,mem_re,mem_to_reg_we,inst_re,
output reg syscall,
output reg rf_clk,bus_clk,
output reg set_lock_flag,
output [3:0] state
); |
reg [3:0] curState,nextState;
reg [3:0] lastState;
assign state = curState;
assign rs_addr = inst[25:21];
assign rt_addr = inst[20:16];
assign rd_addr = ( inst[31:26] == `OPCODE_ADDI || inst[31:26] == `OPCODE_ADDIU ||
inst[31:26] == `OPCODE_ANDI || inst[31:26] == `OPCODE_SLTI ||
inst[31:26] == `OPCODE_SLTIU || inst[31:26] == `OPCODE_ORI ||
inst[31:26] == `OPCODE_XORI || inst[31:26] == `OPCODE_LUI ||
inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX)? inst[20:16] : inst[15:11];
assign imm = ( inst[31:26] == `OPCODE_CALC &&
(inst[5:0] == `FUNCT_SLL || inst[5:0] == `FUNCT_SRA || inst[5:0] == `FUNCT_SRL) ) ? {11'd0,inst[10:6]} : inst[15:0];
always @(clk)
begin
rf_clk <= clk;
bus_clk <= clk;
end
always @(clk or nextState)
if(!clk)
begin
if( curState == `ID && (inst[31:26] == `OPCODE_LW || inst[31:26] == `OPCODE_LDREX) )
mem_re = 1'b1;
else
mem_re = 1'b0;
if(curState == `ID && (inst[31:26] == `OPCODE_SW || inst[31:26] == `OPCODE_STREX) )
mem_we = 1'b1;
else
mem_we = 1'b0;
if( nextState == `IF)
inst_re = 1'b1;
else
inst_re = 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
curState <= `WAIT;
end
else
if(stop)
curState <= `IDLE;
else
curState <= nextState;
end
always @(curState or inst or pause)
begin
if(pause) nextState <= curState;
else
case(curState)
`WAIT: nextState <= `IDLE;
`IDLE: nextState <= `IF;
`IF: nextState <= `ID;
`ID:
begin
if(inst[31:26] == `OPCODE_J || inst[31:26] == `OPCODE_HLT
|| (inst[31:26] == `OPCODE_SPECIAL && inst[5:0] == `FUNCT_SYSCALL) )
nextState <= `IF;
else
nextState <= `EXE;
end
`EXE:
begin
if( (inst[31:26] == `OPCODE_CALC && inst[5:0] == `FUNCT_JR)
|| inst[31:26] == `OPCODE_JAL
|| (inst[31:26] == `OPCODE_SPECIAL && inst[5:0] == `FUNCT_SPRWR) )
nextState <= `IF;
else
nextState <= `WB;
end
`WB: nextState <= `IF;
default: nextState <= nextState;
endcase
end
always @(curState)
begin
if(!rst_n)
begin
IR_ack <= 0;
alu_sel_a <= 0;
alu_sel_b <= 0;
alu_op_type <= 0;
JAL_or_J <= 0;
BEQ_or_BNE <= 0;
JR <= 0;
hlt <= 0;
next <= 0;
reg_we <= 0;
spr_sel <= 0;
alu_mux_ack <= 0;
pc_we <= 0;
mem_to_reg_we <= 0;
LUI <= 0;
syscall <= 0;
set_lock_flag <= 0;
end
begin
IR_ack <= 0;
alu_sel_a <= 0;
alu_sel_b <= 0;
alu_op_type <= 0;
JAL_or_J <= 0;
BEQ_or_BNE <= 0;
JR <= 0;
hlt <= 0;
next <= 0;
reg_we <= 0;
spr_sel <= 0;
alu_mux_ack <= 0;
pc_we <= 0;
mem_to_reg_we <= 0;
LUI <= 0;
syscall <= 0;
set_lock_flag <= 0;
if(curState == `IF)
IR_ack <= 1'b1;
if(curState == `ID)
begin
case(inst[31:26])
`OPCODE_CALC:
begin
case(inst[5:0])
`FUNCT_ADD,`FUNCT_ADDU,`FUNCT_SUB,`FUNCT_SUBU,`FUNCT_AND,
`FUNCT_OR,`FUNCT_XOR,`FUNCT_NOR,`FUNCT_SLT,`FUNCT_SLTU,
`FUNCT_SLLV,`FUNCT_SRLV,`FUNCT_SRAV:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
`FUNCT_SLL,`FUNCT_SRL,`FUNCT_SRA:
begin
alu_sel_a <= `ALU_SEL_IMM;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
default: ;
endcase
end
`OPCODE_ADDI,`OPCODE_ADDIU,`OPCODE_ANDI,`OPCODE_ORI,
`OPCODE_XORI,`OPCODE_SLTI,`OPCODE_SLTIU:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_IMM;
alu_mux_ack <= 1'b1;
end
`OPCODE_BEQ,`OPCODE_BNE:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
`OPCODE_LUI:
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_IMM;
alu_mux_ack <= 1'b1;
end
`OPCODE_HLT:
begin
hlt <= 1'b1;
next <= 1'b1;
end
`OPCODE_J:
begin
JAL_or_J <= 1'b1;
next <= 1'b1;
end
`OPCODE_JAL:
begin
reg_we <= 1'b1;
pc_we <= 1'b1;
end
`OPCODE_SPECIAL:
begin
if(inst[5:0] == `FUNCT_SYSCALL)
begin
syscall <= 1'b1;
next <= 1'b1;
end
if(inst[5:0] == `FUNCT_SPRRD)
begin
spr_sel <= 1'b1;
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
if(inst[5:0] == `FUNCT_SPRWR)
begin
alu_sel_a <= `ALU_SEL_RS;
alu_sel_b <= `ALU_SEL_RT;
alu_mux_ack <= 1'b1;
end
end
default: ;
endcase
end
if(curState == `EXE)
begin
case(inst[31:26])
`OPCODE_JAL:
begin
JAL_or_J <= 1'b1;
next <= 1'b1;
end
`OPCODE_LW,`OPCODE_LDREX: mem_to_reg_we <= 1'b1;
`OPCODE_STREX:
begin
reg_we <= 1'b1;
set_lock_flag <= 1'b1;
end
`OPCODE_CALC:
begin
case(inst[5:0])
`FUNCT_ADD : alu_op_type <= `ALU_OP_ADD;
`FUNCT_ADDU : alu_op_type <= `ALU_OP_ADDU;
`FUNCT_SUB : alu_op_type <= `ALU_OP_SUB;
`FUNCT_SUBU : alu_op_type <= `ALU_OP_SUBU;
`FUNCT_AND : alu_op_type <= `ALU_OP_AND;
`FUNCT_OR : alu_op_type <= `ALU_OP_OR;
`FUNCT_XOR : alu_op_type <= `ALU_OP_XOR;
`FUNCT_NOR : alu_op_type <= `ALU_OP_NOR;
`FUNCT_SLT : alu_op_type <= `ALU_OP_LT;
`FUNCT_SLTU : alu_op_type <= `ALU_OP_LTU;
`FUNCT_SLLV,`FUNCT_SLL : alu_op_type <= `ALU_OP_SLL;
`FUNCT_SRLV,`FUNCT_SRL : alu_op_type <= `ALU_OP_SRL;
`FUNCT_SRAV,`FUNCT_SRA : alu_op_type <= `ALU_OP_SRA;
`FUNCT_JR:
begin
JR <= 1'b1;
next <= 1'b1;
end
default:;
endcase
end
`OPCODE_ADDI : alu_op_type <= `ALU_OP_ADD;
`OPCODE_ADDIU : alu_op_type <= `ALU_OP_ADDU;
`OPCODE_ANDI : alu_op_type <= `ALU_OP_AND;
`OPCODE_ORI : alu_op_type <= `ALU_OP_OR;
`OPCODE_XORI : alu_op_type <= `ALU_OP_XOR;
`OPCODE_BEQ : alu_op_type <= `ALU_OP_EQ;
`OPCODE_BNE : alu_op_type <= `ALU_OP_NE;
`OPCODE_SLTI : alu_op_type <= `ALU_OP_LT;
`OPCODE_SLTIU : alu_op_type <= `ALU_OP_LTU;
`OPCODE_LUI : alu_op_type <= `ALU_OP_ADDU;
`OPCODE_SPECIAL : if(inst[5:0] == `FUNCT_SPRRD)
alu_op_type <= `ALU_OP_ADDU;
else
if(inst[5:0] == `FUNCT_SPRWR)
begin
spr_sel <= 1'b1;
reg_we <= 1'b1;
next <= 1'b1;
end
default:;
endcase
end
if(curState == `WB)
begin
if(inst[31:26] == `OPCODE_BEQ || inst[31:26] == `OPCODE_BNE)
begin
BEQ_or_BNE <= 1'b1;
end
else
begin
if(inst[31:26] == `OPCODE_LUI)
LUI <= 1'b1;
if(inst[31:26] != `OPCODE_SW && inst[31:26] != `OPCODE_LW &&
inst[31:26] != `OPCODE_LDREX && inst[31:26] != `OPCODE_STREX)
begin
spr_sel <= 1'b0;
reg_we <= 1'b1;
end
end
next <= 1'b1;
end
end
end
endmodule | 0 |
2,695 | data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v | 100,796,583 | MBScore_interrupt_ctrl.v | v | 54 | 47 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n input [`INT_SEL_WIDTH-1:0] int_vec,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:10: Define or directive not defined: \'`ADDR_WIDTH\'\n output reg [`ADDR_WIDTH-1:0] int_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:30: Define or directive not defined: \'`INT_KEYBOARD\'\n if(int_vec_r == `INT_KEYBOARD)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:30: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if(int_vec_r == `INT_KEYBOARD)\n ^\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:31: Define or directive not defined: \'`INT_KEYBOARD_ADDR\'\n int_addr = `INT_KEYBOARD_ADDR;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:33: Define or directive not defined: \'`INT_MOUSE\'\n if(int_vec_r == `INT_MOUSE)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:34: Define or directive not defined: \'`INT_MOUSE_ADDR\'\n int_addr = `INT_MOUSE_ADDR;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:36: Define or directive not defined: \'`INT_UART\'\n if(int_vec_r == `INT_UART)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:37: Define or directive not defined: \'`INT_UART_ADDR\'\n int_addr = `INT_UART_ADDR;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:39: Define or directive not defined: \'`INT_STORAGE\'\n if(int_vec_r == `INT_STORAGE)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:40: Define or directive not defined: \'`INT_STORAGE_ADDR\'\n int_addr = `INT_STORAGE_ADDR;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:42: Define or directive not defined: \'`INT_ETHERNET\'\n if(int_vec_r == `INT_ETHERNET)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:43: Define or directive not defined: \'`INT_ETHERNET_ADDR\'\n int_addr = `INT_ETHERNET_ADDR;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_interrupt_ctrl.v:51: Define or directive not defined: \'`ADDR_WIDTH\'\n int_addr = `ADDR_WIDTH\'d0;\n ^~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n' | 119 | module | module MBScore_interrupt_ctrl(
input clk,
input rst_n,
input [`INT_SEL_WIDTH-1:0] int_vec,
input int_en_n,
output reg stop,
output reg setINTR,
output reg [`ADDR_WIDTH-1:0] int_addr,
output reg int_jump
);
reg int_vec_r;
always @(int_vec)
if(int_vec && !int_en_n)
begin
int_vec_r = int_vec;
stop = 1'b1;
end
else
stop = 1'b0;
always @(posedge clk)
if(stop)
begin
setINTR = 1'b1;
if(int_vec_r == `INT_KEYBOARD)
int_addr = `INT_KEYBOARD_ADDR;
else
if(int_vec_r == `INT_MOUSE)
int_addr = `INT_MOUSE_ADDR;
else
if(int_vec_r == `INT_UART)
int_addr = `INT_UART_ADDR;
else
if(int_vec_r == `INT_STORAGE)
int_addr = `INT_STORAGE_ADDR;
else
if(int_vec_r == `INT_ETHERNET)
int_addr = `INT_ETHERNET_ADDR;
int_jump = 1'b1;
end
else
begin
setINTR = 1'b0;
int_jump = 1'b0;
int_addr = `ADDR_WIDTH'd0;
end
endmodule | module MBScore_interrupt_ctrl(
input clk,
input rst_n,
input [`INT_SEL_WIDTH-1:0] int_vec,
input int_en_n,
output reg stop,
output reg setINTR,
output reg [`ADDR_WIDTH-1:0] int_addr,
output reg int_jump
); |
reg int_vec_r;
always @(int_vec)
if(int_vec && !int_en_n)
begin
int_vec_r = int_vec;
stop = 1'b1;
end
else
stop = 1'b0;
always @(posedge clk)
if(stop)
begin
setINTR = 1'b1;
if(int_vec_r == `INT_KEYBOARD)
int_addr = `INT_KEYBOARD_ADDR;
else
if(int_vec_r == `INT_MOUSE)
int_addr = `INT_MOUSE_ADDR;
else
if(int_vec_r == `INT_UART)
int_addr = `INT_UART_ADDR;
else
if(int_vec_r == `INT_STORAGE)
int_addr = `INT_STORAGE_ADDR;
else
if(int_vec_r == `INT_ETHERNET)
int_addr = `INT_ETHERNET_ADDR;
int_jump = 1'b1;
end
else
begin
setINTR = 1'b0;
int_jump = 1'b0;
int_addr = `ADDR_WIDTH'd0;
end
endmodule | 0 |
2,696 | data/full_repos/permissive/100796583/cpu/MBScore_IR.v | 100,796,583 | MBScore_IR.v | v | 54 | 56 | [] | [] | [] | [(112, 163)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH-1:0] next_addr,int_addr,init_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] inst_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] inst_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] pc_out\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:18: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] pc = 32\'d0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_IR.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] inst;\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 120 | module | module MBScore_IR(
input clk,
input rst_n,
input IR_ack,
input next,
input JAL_or_J,
input BEQ_or_BNE,
input JR,
input hlt,
input jump,int_jump,
input [`ADDR_WIDTH-1:0] next_addr,int_addr,init_addr,
input [`DATA_WIDTH-1:0] inst_in,
output [`DATA_WIDTH-1:0] inst_out,
output [`DATA_WIDTH-1:0] pc_out
);
reg [`DATA_WIDTH-1:0] pc = 32'd0;
reg [`DATA_WIDTH-1:0] inst;
assign pc_out = pc;
assign inst_out = inst;
always @(negedge clk)
if(IR_ack)
inst = inst_in;
always @(negedge clk or negedge rst_n)
if(next || int_jump)
begin
if(hlt == 1'b1)
pc = pc;
else
if(JAL_or_J)
pc = (inst[25:0] << 2);
else
if(BEQ_or_BNE && jump)
pc = pc + 4 + ($signed(inst[15:0]) << 2);
else
if(JR)
pc = next_addr;
else
if(int_jump)
pc = int_addr;
else
pc = pc + 4;
end
else
if(!rst_n)
pc = init_addr;
endmodule | module MBScore_IR(
input clk,
input rst_n,
input IR_ack,
input next,
input JAL_or_J,
input BEQ_or_BNE,
input JR,
input hlt,
input jump,int_jump,
input [`ADDR_WIDTH-1:0] next_addr,int_addr,init_addr,
input [`DATA_WIDTH-1:0] inst_in,
output [`DATA_WIDTH-1:0] inst_out,
output [`DATA_WIDTH-1:0] pc_out
); |
reg [`DATA_WIDTH-1:0] pc = 32'd0;
reg [`DATA_WIDTH-1:0] inst;
assign pc_out = pc;
assign inst_out = inst;
always @(negedge clk)
if(IR_ack)
inst = inst_in;
always @(negedge clk or negedge rst_n)
if(next || int_jump)
begin
if(hlt == 1'b1)
pc = pc;
else
if(JAL_or_J)
pc = (inst[25:0] << 2);
else
if(BEQ_or_BNE && jump)
pc = pc + 4 + ($signed(inst[15:0]) << 2);
else
if(JR)
pc = next_addr;
else
if(int_jump)
pc = int_addr;
else
pc = pc + 4;
end
else
if(!rst_n)
pc = init_addr;
endmodule | 0 |
2,697 | data/full_repos/permissive/100796583/cpu/MBScore_rf.v | 100,796,583 | MBScore_rf.v | v | 122 | 82 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:1: Cannot find include file: MBScore_const.v\n`include "MBScore_const.v" \n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.v\n data/full_repos/permissive/100796583/cpu,data/full_repos/permissive/100796583/MBScore_const.v.sv\n MBScore_const.v\n MBScore_const.v.v\n MBScore_const.v.sv\n obj_dir/MBScore_const.v\n obj_dir/MBScore_const.v.v\n obj_dir/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:5: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n input [`REG_ADDR_WIDTH-1:0] rs_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:6: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n input [`REG_ADDR_WIDTH-1:0] rd_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:7: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n input [`REG_ADDR_WIDTH-1:0] rt_addr,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:11: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] alu_data_in,mem_data_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:12: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] pc_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] rs_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:16: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] rt_out,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:17: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] spr_out,spr_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/cpu/MBScore_rf.v:21: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n reg [`REG_ADDR_WIDTH-1:0] rs_addr_r,rt_addr_r,rd_addr_r;\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n' | 121 | module | module MBScore_rf(
input clk,
input rst_n,
input [`REG_ADDR_WIDTH-1:0] rs_addr,
input [`REG_ADDR_WIDTH-1:0] rd_addr,
input [`REG_ADDR_WIDTH-1:0] rt_addr,
input reg_we,mem_to_reg_we,
input pc_we,
input spr_sel,
input [`DATA_WIDTH-1:0] alu_data_in,mem_data_in,
input [`DATA_WIDTH-1:0] pc_in,
input LUI,
input setINTR,
output [`DATA_WIDTH-1:0] rs_out,
output [`DATA_WIDTH-1:0] rt_out,
output [`DATA_WIDTH-1:0] spr_out,spr_in,
output int_en_n
);
reg [`REG_ADDR_WIDTH-1:0] rs_addr_r,rt_addr_r,rd_addr_r;
reg [31:0] gr [0:31];
reg [31:0] spr [0:7];
assign rs_out = (spr_sel == 1'b1 && !reg_we)? spr[rs_addr_r] : gr[rs_addr_r];
assign rt_out = gr[rt_addr_r];
assign spr_out = spr[rd_addr_r];
assign int_en_n = spr[1][0];
reg [31:0] spr_temp_r;
initial
begin
gr[0] = 32'd0;
gr[1] = 32'b0;
gr[2] = 32'b0;
gr[3] = 32'd0;
gr[4] = 32'd0;
gr[5] = 32'd0;
gr[6] = 32'd0;
gr[7] = 32'd0;
gr[8] = 32'd0;
gr[9] = 32'd0;
gr[10] = 32'd0;
gr[11] = 32'd0;
gr[12] = 32'd0;
gr[13] = 32'd0;
gr[14] = 32'd0;
gr[15] = 32'd0;
gr[16] = 32'd0;
gr[17] = 32'd0;
gr[18] = 32'd0;
gr[19] = 32'd0;
gr[20] = 32'd0;
gr[21] = 32'd0;
gr[22] = 32'd0;
gr[23] = 32'd0;
gr[24] = 32'd0;
gr[25] = 32'd0;
gr[26] = 32'd0;
gr[27] = 32'd0;
gr[28] = 32'd0;
gr[29] = 32'd0;
gr[30] = 32'd0;
gr[31] = 32'd0;
spr[0] = 32'd0;
spr[1] = 32'd0;
spr[2] = 32'd0;
spr[3] = 32'd0;
spr[4] = 32'd0;
spr[5] = 32'd0;
spr[6] = 32'd0;
spr[7] = 32'd0;
end
always @(negedge clk)
if(reg_we && !spr_sel && !mem_to_reg_we)
begin
if(pc_we)
gr[31] = pc_in + 4;
else
if(rd_addr != 0)
begin
if(LUI)
gr[rd_addr] = {alu_data_in[15:0],16'd0};
else
gr[rd_addr] = alu_data_in;
end
end
else
if(mem_to_reg_we)
begin
if(rd_addr != 0)
gr[rd_addr] = mem_data_in;
end
always @(posedge clk)
begin
rs_addr_r <= rs_addr;
rt_addr_r <= rt_addr;
end
always @(negedge clk)
if(reg_we && spr_sel)
spr[rd_addr] = ( spr_in & rt_out ) | ( rs_out & (~rt_out) );
else
if(setINTR)
begin
spr[0] = pc_in;
spr[1][0] = 1'b1;
end
always @(posedge clk)
rd_addr_r <= rd_addr;
endmodule | module MBScore_rf(
input clk,
input rst_n,
input [`REG_ADDR_WIDTH-1:0] rs_addr,
input [`REG_ADDR_WIDTH-1:0] rd_addr,
input [`REG_ADDR_WIDTH-1:0] rt_addr,
input reg_we,mem_to_reg_we,
input pc_we,
input spr_sel,
input [`DATA_WIDTH-1:0] alu_data_in,mem_data_in,
input [`DATA_WIDTH-1:0] pc_in,
input LUI,
input setINTR,
output [`DATA_WIDTH-1:0] rs_out,
output [`DATA_WIDTH-1:0] rt_out,
output [`DATA_WIDTH-1:0] spr_out,spr_in,
output int_en_n
); |
reg [`REG_ADDR_WIDTH-1:0] rs_addr_r,rt_addr_r,rd_addr_r;
reg [31:0] gr [0:31];
reg [31:0] spr [0:7];
assign rs_out = (spr_sel == 1'b1 && !reg_we)? spr[rs_addr_r] : gr[rs_addr_r];
assign rt_out = gr[rt_addr_r];
assign spr_out = spr[rd_addr_r];
assign int_en_n = spr[1][0];
reg [31:0] spr_temp_r;
initial
begin
gr[0] = 32'd0;
gr[1] = 32'b0;
gr[2] = 32'b0;
gr[3] = 32'd0;
gr[4] = 32'd0;
gr[5] = 32'd0;
gr[6] = 32'd0;
gr[7] = 32'd0;
gr[8] = 32'd0;
gr[9] = 32'd0;
gr[10] = 32'd0;
gr[11] = 32'd0;
gr[12] = 32'd0;
gr[13] = 32'd0;
gr[14] = 32'd0;
gr[15] = 32'd0;
gr[16] = 32'd0;
gr[17] = 32'd0;
gr[18] = 32'd0;
gr[19] = 32'd0;
gr[20] = 32'd0;
gr[21] = 32'd0;
gr[22] = 32'd0;
gr[23] = 32'd0;
gr[24] = 32'd0;
gr[25] = 32'd0;
gr[26] = 32'd0;
gr[27] = 32'd0;
gr[28] = 32'd0;
gr[29] = 32'd0;
gr[30] = 32'd0;
gr[31] = 32'd0;
spr[0] = 32'd0;
spr[1] = 32'd0;
spr[2] = 32'd0;
spr[3] = 32'd0;
spr[4] = 32'd0;
spr[5] = 32'd0;
spr[6] = 32'd0;
spr[7] = 32'd0;
end
always @(negedge clk)
if(reg_we && !spr_sel && !mem_to_reg_we)
begin
if(pc_we)
gr[31] = pc_in + 4;
else
if(rd_addr != 0)
begin
if(LUI)
gr[rd_addr] = {alu_data_in[15:0],16'd0};
else
gr[rd_addr] = alu_data_in;
end
end
else
if(mem_to_reg_we)
begin
if(rd_addr != 0)
gr[rd_addr] = mem_data_in;
end
always @(posedge clk)
begin
rs_addr_r <= rs_addr;
rt_addr_r <= rt_addr;
end
always @(negedge clk)
if(reg_we && spr_sel)
spr[rd_addr] = ( spr_in & rt_out ) | ( rs_out & (~rt_out) );
else
if(setINTR)
begin
spr[0] = pc_in;
spr[1][0] = 1'b1;
end
always @(posedge clk)
rd_addr_r <= rd_addr;
endmodule | 0 |
2,698 | data/full_repos/permissive/100796583/module/MBSsoc_apic.v | 100,796,583 | MBSsoc_apic.v | v | 144 | 79 | [] | [] | [] | [(113, 254)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:2: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:6: Define or directive not defined: \'`INT_SEL_WIDTH\'\n input [`INT_SEL_WIDTH-1:0] int_vec,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:7: Define or directive not defined: \'`CORE_NUM\'\n input [`CORE_NUM-1:0] int_able,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:8: Define or directive not defined: \'`SYSCODE_WIDTH\'\n input [`SYSCODE_WIDTH-1:0] syscall_code1,syscall_code0,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:10: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] data_in,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:11: Define or directive not defined: \'`INT_SEL_WIDTH\'\n output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:12: Define or directive not defined: \'`INT_SEL_WIDTH\'\n output reg [`INT_SEL_WIDTH-1:0] int_ack,\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:13: Define or directive not defined: \'`ADDR_WIDTH\'\n output [`ADDR_WIDTH-1:0] cpu0_pc,cpu1_pc,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:17: Define or directive not defined: \'`INT_SEL_WIDTH\'\n reg [`INT_SEL_WIDTH-1:0] int_vec_r;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] conf_r;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:20: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] cpu0_pc_r = 32\'d0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:21: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] cpu1_pc_r = 32\'d0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:26: Define or directive not defined: \'`SYSCODE_WIDTH\'\n reg [`SYSCODE_WIDTH-1:0] syscall_code1_r,syscall_code0_r;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:41: Define or directive not defined: \'`INT_SYSCALL0\'\n if(int_vec_r[`INT_SYSCALL0] == 1\'b1)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if(int_vec_r[`INT_SYSCALL0] == 1\'b1)\n ^\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:47: Define or directive not defined: \'`INT_SYSCALL1\'\n if(int_vec_r[`INT_SYSCALL1] == 1\'b1)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n if(int_vec_r[`INT_SYSCALL1] == 1\'b1)\n ^\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:61: Define or directive not defined: \'`CHANGE_CPU1_PC\'\n `CHANGE_CPU1_PC: \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:72: Define or directive not defined: \'`INT_KEYBOARD\'\n if(int_vec_r[`INT_KEYBOARD])\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:74: Define or directive not defined: \'`INT_KEYBOARD\'\n int_num_out1 <= `INT_KEYBOARD;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:75: Define or directive not defined: \'`INT_KEYBOARD\'\n int_ack[`INT_KEYBOARD] <= 1\'b1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:78: Define or directive not defined: \'`INT_MOUSE\'\n if(int_vec_r[`INT_MOUSE])\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:80: Define or directive not defined: \'`INT_MOUSE\'\n int_num_out1 <= `INT_MOUSE;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:81: Define or directive not defined: \'`INT_MOUSE\'\n int_ack[`INT_MOUSE] <= 1\'b1;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:84: Define or directive not defined: \'`INT_UART\'\n if(int_vec_r[`INT_UART])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:86: Define or directive not defined: \'`INT_UART\'\n int_num_out1 <= `INT_UART;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:87: Define or directive not defined: \'`INT_UART\'\n int_ack[`INT_UART] <= 1\'b1;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:90: Define or directive not defined: \'`INT_STORAGE\'\n if(int_vec_r[`INT_STORAGE])\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:92: Define or directive not defined: \'`INT_STORAGE\'\n int_num_out1 <= `INT_STORAGE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:93: Define or directive not defined: \'`INT_STORAGE\'\n int_ack[`INT_STORAGE] <= 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:96: Define or directive not defined: \'`INT_ETHERNET\'\n if(int_vec_r[`INT_ETHERNET])\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:98: Define or directive not defined: \'`INT_ETHERNET\'\n int_num_out1 <= `INT_ETHERNET;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:99: Define or directive not defined: \'`INT_ETHERNET\'\n int_ack[`INT_ETHERNET] <= 1\'b1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:105: Define or directive not defined: \'`INT_KEYBOARD\'\n if(int_vec_r[`INT_KEYBOARD])\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:107: Define or directive not defined: \'`INT_KEYBOARD\'\n int_num_out0 <= `INT_KEYBOARD;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:108: Define or directive not defined: \'`INT_KEYBOARD\'\n int_ack[`INT_KEYBOARD] <= 1\'b1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:111: Define or directive not defined: \'`INT_MOUSE\'\n if(int_vec_r[`INT_MOUSE])\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:113: Define or directive not defined: \'`INT_MOUSE\'\n int_num_out0 <= `INT_MOUSE;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:114: Define or directive not defined: \'`INT_MOUSE\'\n int_ack[`INT_MOUSE] <= 1\'b1;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:117: Define or directive not defined: \'`INT_UART\'\n if(int_vec_r[`INT_UART])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:119: Define or directive not defined: \'`INT_UART\'\n int_num_out0 <= `INT_UART;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:120: Define or directive not defined: \'`INT_UART\'\n int_ack[`INT_UART] <= 1\'b1;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:123: Define or directive not defined: \'`INT_STORAGE\'\n if(int_vec_r[`INT_STORAGE])\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:125: Define or directive not defined: \'`INT_STORAGE\'\n int_num_out0 <= `INT_STORAGE;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:126: Define or directive not defined: \'`INT_STORAGE\'\n int_ack[`INT_STORAGE] <= 1\'b1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:129: Define or directive not defined: \'`INT_ETHERNET\'\n if(int_vec_r[`INT_ETHERNET])\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:131: Define or directive not defined: \'`INT_ETHERNET\'\n int_num_out0 <= `INT_ETHERNET;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:132: Define or directive not defined: \'`INT_ETHERNET\'\n int_ack[`INT_ETHERNET] <= 1\'b1;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:138: Define or directive not defined: \'`INT_SEL_WIDTH\'\n int_num_out0 <= `INT_SEL_WIDTH\'d0;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_apic.v:139: Define or directive not defined: \'`INT_SEL_WIDTH\'\n int_num_out1 <= `INT_SEL_WIDTH\'d0;\n ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 122 | module | module MBSsoc_apic(
input clk,
input rst_n,
input [`INT_SEL_WIDTH-1:0] int_vec,
input [`CORE_NUM-1:0] int_able,
input [`SYSCODE_WIDTH-1:0] syscall_code1,syscall_code0,
input [2:0] ctrl_in,
input [`DATA_WIDTH-1:0] data_in,
output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,
output reg [`INT_SEL_WIDTH-1:0] int_ack,
output [`ADDR_WIDTH-1:0] cpu0_pc,cpu1_pc,
output reg cpu1_en
);
reg [`INT_SEL_WIDTH-1:0] int_vec_r;
reg [`DATA_WIDTH-1:0] conf_r;
reg [`ADDR_WIDTH-1:0] cpu0_pc_r = 32'd0;
reg [`ADDR_WIDTH-1:0] cpu1_pc_r = 32'd0;
assign cpu0_pc = cpu0_pc_r;
assign cpu1_pc = cpu1_pc_r;
reg syscall0,syscall1;
reg [`SYSCODE_WIDTH-1:0] syscall_code1_r,syscall_code0_r;
always @(posedge clk)
case (ctrl_in)
3'b001: conf_r <= data_in;
3'b010: cpu0_pc_r <= data_in;
3'b100: cpu1_pc_r <= data_in;
default: {conf_r,cpu0_pc_r,cpu1_pc_r} <= {conf_r,cpu0_pc_r,cpu1_pc_r};
endcase
always @(int_vec)
begin
int_vec_r <= int_vec;
if(int_vec_r[`INT_SYSCALL0] == 1'b1)
begin
syscall0 <= 1'b1;
syscall_code0_r <= syscall0;
end
if(int_vec_r[`INT_SYSCALL1] == 1'b1)
begin
syscall1 <= 1'b1;
syscall_code1_r <= syscall1;
end
end
always @(negedge clk)
if(int_vec_r || syscall0 || syscall1)
begin
if(syscall0)
begin
case (syscall_code0)
`CHANGE_CPU1_PC:
begin
cpu1_en <= 1'b1;
end
endcase
syscall0 <= 1'b0;
end
if(int_able[1] && !conf_r[1])
begin
if(int_vec_r[`INT_KEYBOARD])
begin
int_num_out1 <= `INT_KEYBOARD;
int_ack[`INT_KEYBOARD] <= 1'b1;
end
else
if(int_vec_r[`INT_MOUSE])
begin
int_num_out1 <= `INT_MOUSE;
int_ack[`INT_MOUSE] <= 1'b1;
end
else
if(int_vec_r[`INT_UART])
begin
int_num_out1 <= `INT_UART;
int_ack[`INT_UART] <= 1'b1;
end
else
if(int_vec_r[`INT_STORAGE])
begin
int_num_out1 <= `INT_STORAGE;
int_ack[`INT_STORAGE] <= 1'b1;
end
else
if(int_vec_r[`INT_ETHERNET])
begin
int_num_out1 <= `INT_ETHERNET;
int_ack[`INT_ETHERNET] <= 1'b1;
end
end
else
if(int_able[0] && !conf_r[0])
begin
if(int_vec_r[`INT_KEYBOARD])
begin
int_num_out0 <= `INT_KEYBOARD;
int_ack[`INT_KEYBOARD] <= 1'b1;
end
else
if(int_vec_r[`INT_MOUSE])
begin
int_num_out0 <= `INT_MOUSE;
int_ack[`INT_MOUSE] <= 1'b1;
end
else
if(int_vec_r[`INT_UART])
begin
int_num_out0 <= `INT_UART;
int_ack[`INT_UART] <= 1'b1;
end
else
if(int_vec_r[`INT_STORAGE])
begin
int_num_out0 <= `INT_STORAGE;
int_ack[`INT_STORAGE] <= 1'b1;
end
else
if(int_vec_r[`INT_ETHERNET])
begin
int_num_out0 <= `INT_ETHERNET;
int_ack[`INT_ETHERNET] <= 1'b1;
end
end
end
else
begin
int_num_out0 <= `INT_SEL_WIDTH'd0;
int_num_out1 <= `INT_SEL_WIDTH'd0;
int_ack <= `INT_SEL_WIDTH'd0;
cpu1_en <= 1'b0;
end
endmodule | module MBSsoc_apic(
input clk,
input rst_n,
input [`INT_SEL_WIDTH-1:0] int_vec,
input [`CORE_NUM-1:0] int_able,
input [`SYSCODE_WIDTH-1:0] syscall_code1,syscall_code0,
input [2:0] ctrl_in,
input [`DATA_WIDTH-1:0] data_in,
output reg [`INT_SEL_WIDTH-1:0] int_num_out0,int_num_out1,
output reg [`INT_SEL_WIDTH-1:0] int_ack,
output [`ADDR_WIDTH-1:0] cpu0_pc,cpu1_pc,
output reg cpu1_en
); |
reg [`INT_SEL_WIDTH-1:0] int_vec_r;
reg [`DATA_WIDTH-1:0] conf_r;
reg [`ADDR_WIDTH-1:0] cpu0_pc_r = 32'd0;
reg [`ADDR_WIDTH-1:0] cpu1_pc_r = 32'd0;
assign cpu0_pc = cpu0_pc_r;
assign cpu1_pc = cpu1_pc_r;
reg syscall0,syscall1;
reg [`SYSCODE_WIDTH-1:0] syscall_code1_r,syscall_code0_r;
always @(posedge clk)
case (ctrl_in)
3'b001: conf_r <= data_in;
3'b010: cpu0_pc_r <= data_in;
3'b100: cpu1_pc_r <= data_in;
default: {conf_r,cpu0_pc_r,cpu1_pc_r} <= {conf_r,cpu0_pc_r,cpu1_pc_r};
endcase
always @(int_vec)
begin
int_vec_r <= int_vec;
if(int_vec_r[`INT_SYSCALL0] == 1'b1)
begin
syscall0 <= 1'b1;
syscall_code0_r <= syscall0;
end
if(int_vec_r[`INT_SYSCALL1] == 1'b1)
begin
syscall1 <= 1'b1;
syscall_code1_r <= syscall1;
end
end
always @(negedge clk)
if(int_vec_r || syscall0 || syscall1)
begin
if(syscall0)
begin
case (syscall_code0)
`CHANGE_CPU1_PC:
begin
cpu1_en <= 1'b1;
end
endcase
syscall0 <= 1'b0;
end
if(int_able[1] && !conf_r[1])
begin
if(int_vec_r[`INT_KEYBOARD])
begin
int_num_out1 <= `INT_KEYBOARD;
int_ack[`INT_KEYBOARD] <= 1'b1;
end
else
if(int_vec_r[`INT_MOUSE])
begin
int_num_out1 <= `INT_MOUSE;
int_ack[`INT_MOUSE] <= 1'b1;
end
else
if(int_vec_r[`INT_UART])
begin
int_num_out1 <= `INT_UART;
int_ack[`INT_UART] <= 1'b1;
end
else
if(int_vec_r[`INT_STORAGE])
begin
int_num_out1 <= `INT_STORAGE;
int_ack[`INT_STORAGE] <= 1'b1;
end
else
if(int_vec_r[`INT_ETHERNET])
begin
int_num_out1 <= `INT_ETHERNET;
int_ack[`INT_ETHERNET] <= 1'b1;
end
end
else
if(int_able[0] && !conf_r[0])
begin
if(int_vec_r[`INT_KEYBOARD])
begin
int_num_out0 <= `INT_KEYBOARD;
int_ack[`INT_KEYBOARD] <= 1'b1;
end
else
if(int_vec_r[`INT_MOUSE])
begin
int_num_out0 <= `INT_MOUSE;
int_ack[`INT_MOUSE] <= 1'b1;
end
else
if(int_vec_r[`INT_UART])
begin
int_num_out0 <= `INT_UART;
int_ack[`INT_UART] <= 1'b1;
end
else
if(int_vec_r[`INT_STORAGE])
begin
int_num_out0 <= `INT_STORAGE;
int_ack[`INT_STORAGE] <= 1'b1;
end
else
if(int_vec_r[`INT_ETHERNET])
begin
int_num_out0 <= `INT_ETHERNET;
int_ack[`INT_ETHERNET] <= 1'b1;
end
end
end
else
begin
int_num_out0 <= `INT_SEL_WIDTH'd0;
int_num_out1 <= `INT_SEL_WIDTH'd0;
int_ack <= `INT_SEL_WIDTH'd0;
cpu1_en <= 1'b0;
end
endmodule | 0 |
2,699 | data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v | 100,796,583 | MBSsoc_bus_ctrl.v | v | 115 | 93 | [] | [] | [] | [(112, 224)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:6: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:7: Define or directive not defined: \'`CORE_NUM\'\n input [`CORE_NUM-1:0] lock,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:9: Define or directive not defined: \'`CORE_NUM\'\n output reg [`CORE_NUM-1:0] cpu_pause,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:11: Define or directive not defined: \'`CTRL_BUS_WIDTH\'\n output [`CTRL_BUS_WIDTH-1:0] ctrl_bus,\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:14: Define or directive not defined: \'`ADDR_WIDTH\'\n output reg [`ADDR_WIDTH-1:0] ram_addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:16: Define or directive not defined: \'`CORE_NUM\'\n output reg [`CORE_NUM-1:0] lock_flag,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:25: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] lock_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:29: Define or directive not defined: \'`ADDR_WIDTH\'\n wire [`ADDR_WIDTH-1:0] addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:47: Define or directive not defined: \'`ADDR_WIDTH\'\n ram_addr <= `ADDR_WIDTH\'d0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:75: Define or directive not defined: \'`APIC_CONF_ADDR\'\n `APIC_CONF_ADDR: apic_conf <= we;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:75: syntax error, unexpected \':\', expecting endcase\n `APIC_CONF_ADDR: apic_conf <= we;\n ^\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:76: Define or directive not defined: \'`APIC_CPU0_PC_ADDR\'\n `APIC_CPU0_PC_ADDR: apic_cpu0_pc <= we;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:77: Define or directive not defined: \'`APIC_CPU1_PC_ADDR\'\n `APIC_CPU1_PC_ADDR: apic_cpu1_pc <= we;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_bus_ctrl.v:92: syntax error, unexpected else\n else\n ^~~~\n%Error: Exiting due to 15 error(s)\n' | 123 | module | module MBSsoc_bus_ctrl(
input clk,
input rst_n,
input [3:0] cpu_ctrl_bus,
input [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,
input [`CORE_NUM-1:0] lock,
output reg [`CORE_NUM-1:0] cpu_pause,
output cpu_sel_out,
output [`CTRL_BUS_WIDTH-1:0] ctrl_bus,
output reg [`ADDR_WIDTH-1:0] ram_addr,
output reg [`CORE_NUM-1:0] lock_flag,
output [31:0] lock_addr_out
);
reg cpu_sel;
wire we,re;
reg change;
reg apic_conf,apic_cpu0_pc,apic_cpu1_pc,ram_re,ram_we;
reg [`ADDR_WIDTH-1:0] lock_addr;
assign lock_addr_out = lock_addr;
reg ram_wr_invalid;
wire [`ADDR_WIDTH-1:0] addr;
assign cpu_sel_out = cpu_sel;
assign addr = (cpu_sel == 1'b1) ? addr_bus1 : addr_bus0;
assign re = (cpu_sel == 1'b1) ? cpu_ctrl_bus[2] : cpu_ctrl_bus[0];
assign we = (cpu_sel == 1'b1) ? cpu_ctrl_bus[3] : cpu_ctrl_bus[1];
assign ctrl_bus[0] = ram_re;
assign ctrl_bus[1] = ram_we;
assign ctrl_bus[2] = apic_conf;
assign ctrl_bus[3] = apic_cpu0_pc;
assign ctrl_bus[4] = apic_cpu1_pc;
assign ctrl_bus[5] = ram_wr_invalid;
always @(posedge change or negedge rst_n)
if(!rst_n) lock_addr <= 32'hFFFFFFFF;
else
begin
ram_re <= 1'b0;
ram_we <= 1'b0;
ram_addr <= `ADDR_WIDTH'd0;
ram_wr_invalid <= 1'b0;
apic_conf <= 1'b0;
apic_cpu0_pc <= 1'b0;
apic_cpu1_pc <= 1'b0;
lock_flag <= 2'b00;
lock_addr <= lock_addr;
if(lock[cpu_sel] && re) lock_addr <= addr;
if(lock[cpu_sel] && we)
begin
if(addr == lock_addr) lock_addr <= 32'hFFFFFFFF;
else
begin
lock_flag[cpu_sel] <= 1'b1;
ram_wr_invalid <= 1'b1;
end
end
if(addr < 33554432)
begin
ram_re <= re;
ram_we <= we;
ram_addr <= addr;
end
else
case (addr)
`APIC_CONF_ADDR: apic_conf <= we;
`APIC_CPU0_PC_ADDR: apic_cpu0_pc <= we;
`APIC_CPU1_PC_ADDR: apic_cpu1_pc <= we;
default:;
endcase
end
always @(clk or rst_n)
if(~clk)
begin
if( (cpu_ctrl_bus[0] && cpu_ctrl_bus[2]) || (cpu_ctrl_bus[1] && cpu_ctrl_bus[3]) ||
(cpu_ctrl_bus[0] && cpu_ctrl_bus[3]) || (cpu_ctrl_bus[1] && cpu_ctrl_bus[2]) )
begin
cpu_pause[0] <= 1'b1;
cpu_sel <= 1'b1;
end
else
if(cpu_ctrl_bus[0] || cpu_ctrl_bus[1])
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b0;
end
else
if(cpu_ctrl_bus[2] || cpu_ctrl_bus[3])
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b1;
end
else
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b0;
end
change <= 1'b1;
end
else
change <= 1'b0;
endmodule | module MBSsoc_bus_ctrl(
input clk,
input rst_n,
input [3:0] cpu_ctrl_bus,
input [`ADDR_WIDTH-1:0] addr_bus0,addr_bus1,
input [`CORE_NUM-1:0] lock,
output reg [`CORE_NUM-1:0] cpu_pause,
output cpu_sel_out,
output [`CTRL_BUS_WIDTH-1:0] ctrl_bus,
output reg [`ADDR_WIDTH-1:0] ram_addr,
output reg [`CORE_NUM-1:0] lock_flag,
output [31:0] lock_addr_out
); |
reg cpu_sel;
wire we,re;
reg change;
reg apic_conf,apic_cpu0_pc,apic_cpu1_pc,ram_re,ram_we;
reg [`ADDR_WIDTH-1:0] lock_addr;
assign lock_addr_out = lock_addr;
reg ram_wr_invalid;
wire [`ADDR_WIDTH-1:0] addr;
assign cpu_sel_out = cpu_sel;
assign addr = (cpu_sel == 1'b1) ? addr_bus1 : addr_bus0;
assign re = (cpu_sel == 1'b1) ? cpu_ctrl_bus[2] : cpu_ctrl_bus[0];
assign we = (cpu_sel == 1'b1) ? cpu_ctrl_bus[3] : cpu_ctrl_bus[1];
assign ctrl_bus[0] = ram_re;
assign ctrl_bus[1] = ram_we;
assign ctrl_bus[2] = apic_conf;
assign ctrl_bus[3] = apic_cpu0_pc;
assign ctrl_bus[4] = apic_cpu1_pc;
assign ctrl_bus[5] = ram_wr_invalid;
always @(posedge change or negedge rst_n)
if(!rst_n) lock_addr <= 32'hFFFFFFFF;
else
begin
ram_re <= 1'b0;
ram_we <= 1'b0;
ram_addr <= `ADDR_WIDTH'd0;
ram_wr_invalid <= 1'b0;
apic_conf <= 1'b0;
apic_cpu0_pc <= 1'b0;
apic_cpu1_pc <= 1'b0;
lock_flag <= 2'b00;
lock_addr <= lock_addr;
if(lock[cpu_sel] && re) lock_addr <= addr;
if(lock[cpu_sel] && we)
begin
if(addr == lock_addr) lock_addr <= 32'hFFFFFFFF;
else
begin
lock_flag[cpu_sel] <= 1'b1;
ram_wr_invalid <= 1'b1;
end
end
if(addr < 33554432)
begin
ram_re <= re;
ram_we <= we;
ram_addr <= addr;
end
else
case (addr)
`APIC_CONF_ADDR: apic_conf <= we;
`APIC_CPU0_PC_ADDR: apic_cpu0_pc <= we;
`APIC_CPU1_PC_ADDR: apic_cpu1_pc <= we;
default:;
endcase
end
always @(clk or rst_n)
if(~clk)
begin
if( (cpu_ctrl_bus[0] && cpu_ctrl_bus[2]) || (cpu_ctrl_bus[1] && cpu_ctrl_bus[3]) ||
(cpu_ctrl_bus[0] && cpu_ctrl_bus[3]) || (cpu_ctrl_bus[1] && cpu_ctrl_bus[2]) )
begin
cpu_pause[0] <= 1'b1;
cpu_sel <= 1'b1;
end
else
if(cpu_ctrl_bus[0] || cpu_ctrl_bus[1])
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b0;
end
else
if(cpu_ctrl_bus[2] || cpu_ctrl_bus[3])
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b1;
end
else
begin
cpu_pause <= 2'b00;
cpu_sel <= 1'b0;
end
change <= 1'b1;
end
else
change <= 1'b0;
endmodule | 0 |
2,700 | data/full_repos/permissive/100796583/module/MBSsoc_ram.v | 100,796,583 | MBSsoc_ram.v | v | 23 | 67 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 38: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/module,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:5: Define or directive not defined: \'`ADDR_WIDTH\'\n input [`ADDR_WIDTH-1:0] addr,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:6: Define or directive not defined: \'`DATA_WIDTH\'\n inout [`DATA_WIDTH-1:0] data\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:9: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:9: Define or directive not defined: \'`MEM_LEN\'\n reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:12: Define or directive not defined: \'`ADDR_WIDTH\'\n reg [`ADDR_WIDTH-1:0] addr_r;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/module/MBSsoc_ram.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n assign data = (ram_re == 1\'b1) ? ram[addr_r] : `DATA_WIDTH\'bz;\n ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n' | 124 | module | module MBSsoc_ram(
input clk,
input ram_we,ram_re,wr_invalid,
input [`ADDR_WIDTH-1:0] addr,
inout [`DATA_WIDTH-1:0] data
);
reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];
initial $readmemb("D:/lijunyan/MBSsoc/module/mem.txt",ram);
reg [`ADDR_WIDTH-1:0] addr_r;
assign data = (ram_re == 1'b1) ? ram[addr_r] : `DATA_WIDTH'bz;
always @(posedge clk)
addr_r = addr >> 2;
always @(posedge clk)
if(ram_we && ~wr_invalid)
ram[addr >> 2] = data;
endmodule | module MBSsoc_ram(
input clk,
input ram_we,ram_re,wr_invalid,
input [`ADDR_WIDTH-1:0] addr,
inout [`DATA_WIDTH-1:0] data
); |
reg [`DATA_WIDTH-1:0] ram [0:`MEM_LEN-1];
initial $readmemb("D:/lijunyan/MBSsoc/module/mem.txt",ram);
reg [`ADDR_WIDTH-1:0] addr_r;
assign data = (ram_re == 1'b1) ? ram[addr_r] : `DATA_WIDTH'bz;
always @(posedge clk)
addr_r = addr >> 2;
always @(posedge clk)
if(ram_we && ~wr_invalid)
ram[addr >> 2] = data;
endmodule | 0 |
2,701 | data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v | 100,796,583 | MBScore_cpu_top_tb(old).v | v | 39 | 119 | [] | [] | [] | [(113, 147)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:5: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] inst;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:6: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] alu_result;\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:19: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:21: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:28: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb(old).v:34: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk; \n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n' | 127 | module | module MBScore_cpu_top_vlg_tst();
reg clk,rst_n;
reg [`DATA_WIDTH-1:0] inst;
wire [`DATA_WIDTH-1:0] alu_result;
MBScore_cpu_top i1(
.clk(clk),
.rst_n(rst_n),
.inst(inst),
.alu_result(alu_result)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
#10
inst = 32'b00000000001000010000100000100000;
end
always
begin
forever #10 clk = ~clk;
end
endmodule | module MBScore_cpu_top_vlg_tst(); |
reg clk,rst_n;
reg [`DATA_WIDTH-1:0] inst;
wire [`DATA_WIDTH-1:0] alu_result;
MBScore_cpu_top i1(
.clk(clk),
.rst_n(rst_n),
.inst(inst),
.alu_result(alu_result)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
#10
inst = 32'b00000000001000010000100000100000;
end
always
begin
forever #10 clk = ~clk;
end
endmodule | 0 |
2,702 | data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v | 100,796,583 | MBScore_cpu_top_tb.v | v | 39 | 119 | [] | [] | [] | [(113, 147)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:5: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] alu_result,pc_out,inst;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:8: Define or directive not defined: \'`INT_SEL_WIDTH\'\n wire [`INT_SEL_WIDTH-1:0] int_vec;\n ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_cpu_top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk; \n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 128 | module | module MBScore_cpu_top_vlg_tst();
reg clk,rst_n;
wire [`DATA_WIDTH-1:0] alu_result,pc_out,inst;
wire [3:0] state;
wire [`INT_SEL_WIDTH-1:0] int_vec;
MBScore_cpu_top i1(
.clk(clk),
.rst_n(rst_n),
.alu_result(alu_result),
.pc_out(pc_out),
.inst_out(inst),
.state(state),
.int_vec_out(int_vec)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
endmodule | module MBScore_cpu_top_vlg_tst(); |
reg clk,rst_n;
wire [`DATA_WIDTH-1:0] alu_result,pc_out,inst;
wire [3:0] state;
wire [`INT_SEL_WIDTH-1:0] int_vec;
MBScore_cpu_top i1(
.clk(clk),
.rst_n(rst_n),
.alu_result(alu_result),
.pc_out(pc_out),
.inst_out(inst),
.state(state),
.int_vec_out(int_vec)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
endmodule | 0 |
2,703 | data/full_repos/permissive/100796583/test/MBScore_IR_tb.v | 100,796,583 | MBScore_IR_tb.v | v | 84 | 117 | [] | [] | [] | [(113, 194)] | null | null | 1: b'%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:1: Cannot find include file: ../cpu/MBScore_const.v\n`include "../cpu/MBScore_const.v" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/../cpu/MBScore_const.v.sv\n ../cpu/MBScore_const.v\n ../cpu/MBScore_const.v.v\n ../cpu/MBScore_const.v.sv\n obj_dir/../cpu/MBScore_const.v\n obj_dir/../cpu/MBScore_const.v.v\n obj_dir/../cpu/MBScore_const.v.sv\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] next_addr;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n reg [`DATA_WIDTH-1:0] inst_in;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] inst_out;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:16: Define or directive not defined: \'`DATA_WIDTH\'\n wire [`DATA_WIDTH-1:0] pc_out;\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBScore_IR_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: Exiting due to 5 error(s), 8 warning(s)\n' | 130 | module | module MBScore_IR_vlg_tst();
reg clk;
reg rst_n;
reg IR_ack;
reg next;
reg JAL_or_J;
reg BEQ_or_BNE;
reg JR;
reg hlt;
reg jump;
reg [`DATA_WIDTH-1:0] next_addr;
reg [`DATA_WIDTH-1:0] inst_in;
wire [`DATA_WIDTH-1:0] inst_out;
wire [`DATA_WIDTH-1:0] pc_out;
wire mem_re;
MBScore_IR i1(
.clk(clk),
.rst_n(rst_n),
.IR_ack(IR_ack),
.next(next),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.jump(jump),
.next_addr(next_addr),
.inst_in(inst_in),
.inst_out(inst_out),
.pc_out(pc_out),
.mem_re(mem_re)
);
initial
begin
JAL_or_J = 1'b0;
BEQ_or_BNE = 1'b0;
JR = 1'b0;
hlt = 1'b0;
next = 1'b0;
IR_ack = 1'b0;
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
always @(posedge mem_re)
if(pc_out == 32'd0)
inst_in = 32'b00010000001000100000000000000001;
else
if(pc_out == 32'd8)
inst_in = 32'b00010000001000100000000000000010;
else
inst_in = 32'b00010000001000100000000000000011;
initial
begin
#10
IR_ack = 1'b1;
#20
IR_ack = 1'b0;
#40
next = 1'b1;
BEQ_or_BNE = 1'b1;
jump = 1'b0;
#20
IR_ack = 1'b1;
#20
IR_ack = 1'b0;
end
endmodule | module MBScore_IR_vlg_tst(); |
reg clk;
reg rst_n;
reg IR_ack;
reg next;
reg JAL_or_J;
reg BEQ_or_BNE;
reg JR;
reg hlt;
reg jump;
reg [`DATA_WIDTH-1:0] next_addr;
reg [`DATA_WIDTH-1:0] inst_in;
wire [`DATA_WIDTH-1:0] inst_out;
wire [`DATA_WIDTH-1:0] pc_out;
wire mem_re;
MBScore_IR i1(
.clk(clk),
.rst_n(rst_n),
.IR_ack(IR_ack),
.next(next),
.JAL_or_J(JAL_or_J),
.BEQ_or_BNE(BEQ_or_BNE),
.JR(JR),
.hlt(hlt),
.jump(jump),
.next_addr(next_addr),
.inst_in(inst_in),
.inst_out(inst_out),
.pc_out(pc_out),
.mem_re(mem_re)
);
initial
begin
JAL_or_J = 1'b0;
BEQ_or_BNE = 1'b0;
JR = 1'b0;
hlt = 1'b0;
next = 1'b0;
IR_ack = 1'b0;
rst_n = 1'b1;
clk = 1'b0;
#1
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
always @(posedge mem_re)
if(pc_out == 32'd0)
inst_in = 32'b00010000001000100000000000000001;
else
if(pc_out == 32'd8)
inst_in = 32'b00010000001000100000000000000010;
else
inst_in = 32'b00010000001000100000000000000011;
initial
begin
#10
IR_ack = 1'b1;
#20
IR_ack = 1'b0;
#40
next = 1'b1;
BEQ_or_BNE = 1'b1;
jump = 1'b0;
#20
IR_ack = 1'b1;
#20
IR_ack = 1'b0;
end
endmodule | 0 |
2,704 | data/full_repos/permissive/100796583/test/MBSsoc_top_tb.v | 100,796,583 | MBSsoc_top_tb.v | v | 49 | 119 | [] | [] | [] | [(2, 49)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBSsoc_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBSsoc_top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100796583/test/MBSsoc_top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/100796583/test/MBSsoc_top_tb.v:17: Cannot find file containing module: \'MBSsoc_top\'\n MBSsoc_top i1(\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/MBSsoc_top\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/MBSsoc_top.v\n data/full_repos/permissive/100796583/test,data/full_repos/permissive/100796583/MBSsoc_top.sv\n MBSsoc_top\n MBSsoc_top.v\n MBSsoc_top.sv\n obj_dir/MBSsoc_top\n obj_dir/MBSsoc_top.v\n obj_dir/MBSsoc_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 133 | module | module MBSsoc_top_tb();
reg clk,rst_n;
wire [31:0] data_bus;
wire [31:0] addr_bus;
wire [31:0] ctrl_bus;
wire [31:0] inst;
wire cpu1_en;
wire syscall0;
wire [2:0] state0,state1;
wire [1:0] cpu_pause;
wire cpu_sel;
wire cpu0_lock_flag;
wire [31:0] lock_addr;
MBSsoc_top i1(
.clk(clk),
.rst_n(rst_n),
.data_bus_out(data_bus),
.addr_bus_out(addr_bus),
.ctrl_bus_out(ctrl_bus),
.cpu1_en_out(cpu1_en),
.syscall0_out(syscall0),
.state0(state0),
.state1(state1),
.cpu_pause_out(cpu_pause),
.cpu_sel_out(cpu_sel),
.cpu0_lock_flag_out(cpu0_lock_flag),
.lock_addr_out(lock_addr)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#5
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
endmodule | module MBSsoc_top_tb(); |
reg clk,rst_n;
wire [31:0] data_bus;
wire [31:0] addr_bus;
wire [31:0] ctrl_bus;
wire [31:0] inst;
wire cpu1_en;
wire syscall0;
wire [2:0] state0,state1;
wire [1:0] cpu_pause;
wire cpu_sel;
wire cpu0_lock_flag;
wire [31:0] lock_addr;
MBSsoc_top i1(
.clk(clk),
.rst_n(rst_n),
.data_bus_out(data_bus),
.addr_bus_out(addr_bus),
.ctrl_bus_out(ctrl_bus),
.cpu1_en_out(cpu1_en),
.syscall0_out(syscall0),
.state0(state0),
.state1(state1),
.cpu_pause_out(cpu_pause),
.cpu_sel_out(cpu_sel),
.cpu0_lock_flag_out(cpu0_lock_flag),
.lock_addr_out(lock_addr)
);
initial
begin
rst_n = 1'b1;
clk = 1'b0;
#5
rst_n = 1'b0;
#5
rst_n = 1'b1;
$display("Running testbench");
end
always
begin
forever #10 clk = ~clk;
end
endmodule | 0 |
2,705 | data/full_repos/permissive/100822769/alu.v | 100,822,769 | alu.v | v | 161 | 106 | [] | [] | [] | [(23, 159)] | null | null | 1: b'%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n ^~\n ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:116: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0)) \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n ^\n%Warning-UNSIGNED: data/full_repos/permissive/100822769/alu.v:134: Comparison is constant due to unsigned arithmetic\n : ... In instance alu\n if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0)) \n ^\n%Error: Exiting due to 7 warning(s)\n' | 134 | module | module alu
(
control,
operand0,
operand1,
result,
overflow,
zero
);
input [3:0] control;
input [31:0] operand0;
input [31:0] operand1;
output [31:0] result;
output overflow;
output zero;
reg [31:0] result;
reg overflow;
reg zero;
always @(control)
begin
case (control)
4'b0000 :
begin
result = operand0 & operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0001:
begin
result = operand0 | operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0010:
begin
result = operand0 + operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0011:
begin
result = operand0 ^ operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0100:
begin
result = ~(operand0 | operand1);
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0110:
begin
result = operand0 - operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0111:
begin
result = (operand0 < operand1) ? -1 : 0;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1000:
begin
result = operand0 << operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1001:
begin
result = operand0 >> operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1011:
begin
result = operand0 + operand1;
if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0))
begin
overflow = 1;
end
else
begin
overflow = 0;
end
zero = (result == 0) ? 1 : 0;
end
4'b1100:
begin
result = operand0 - operand1;
if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0))
begin
overflow = 1;
end
else
begin
overflow = 0;
end
zero = (result == 0) ? 1 : 0;
end
default:
begin
zero = 0;
overflow = 0;
end
endcase
end
endmodule | module alu
(
control,
operand0,
operand1,
result,
overflow,
zero
); |
input [3:0] control;
input [31:0] operand0;
input [31:0] operand1;
output [31:0] result;
output overflow;
output zero;
reg [31:0] result;
reg overflow;
reg zero;
always @(control)
begin
case (control)
4'b0000 :
begin
result = operand0 & operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0001:
begin
result = operand0 | operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0010:
begin
result = operand0 + operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0011:
begin
result = operand0 ^ operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0100:
begin
result = ~(operand0 | operand1);
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0110:
begin
result = operand0 - operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b0111:
begin
result = (operand0 < operand1) ? -1 : 0;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1000:
begin
result = operand0 << operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1001:
begin
result = operand0 >> operand1;
overflow = 0;
zero = (result == 0) ? 1 : 0;
end
4'b1011:
begin
result = operand0 + operand1;
if ((operand0 >= 0 && operand1 >= 0 && result < 0) ||(operand0 < 0 && operand1 < 0 && result >= 0))
begin
overflow = 1;
end
else
begin
overflow = 0;
end
zero = (result == 0) ? 1 : 0;
end
4'b1100:
begin
result = operand0 - operand1;
if ((operand0 >= 0 && operand1 < 0 && result < 0)||(operand0 < 0 && operand1 >= 0 && result >= 0))
begin
overflow = 1;
end
else
begin
overflow = 0;
end
zero = (result == 0) ? 1 : 0;
end
default:
begin
zero = 0;
overflow = 0;
end
endcase
end
endmodule | 6 |
2,706 | data/full_repos/permissive/100822769/data_memory.v | 100,822,769 | data_memory.v | v | 82 | 131 | [] | [] | [] | [(23, 79)] | null | data/verilator_xmls/c3206005-371a-4f21-a401-2f96d45c9e32.xml | null | 136 | module | module data_memory(
clk,
addr,
rdata,
wdata,
wren
);
input clk;
input [31:0] addr;
input [31:0] wdata;
input [3:0] wren;
output [31:0] rdata;
reg [7:0] memory_lane0 [65535:0];
reg [7:0] memory_lane1 [65535:0];
reg [7:0] memory_lane2 [65535:0];
reg [7:0] memory_lane3 [65535:0];
assign rdata = {
memory_lane3[addr[17:2]],
memory_lane2[addr[17:2]],
memory_lane1[addr[17:2]],
memory_lane0[addr[17:2]]
};
always @(posedge clk)
begin
if (wren[0])
memory_lane0[addr[17:2]] <= wdata[7:0];
if (wren[1])
memory_lane1[addr[17:2]] <= wdata[15:8];
if (wren[2])
memory_lane2[addr[17:2]] <= wdata[23:16];
if (wren[3])
memory_lane3[addr[17:2]] <= wdata[31:24];
end
endmodule | module data_memory(
clk,
addr,
rdata,
wdata,
wren
); |
input clk;
input [31:0] addr;
input [31:0] wdata;
input [3:0] wren;
output [31:0] rdata;
reg [7:0] memory_lane0 [65535:0];
reg [7:0] memory_lane1 [65535:0];
reg [7:0] memory_lane2 [65535:0];
reg [7:0] memory_lane3 [65535:0];
assign rdata = {
memory_lane3[addr[17:2]],
memory_lane2[addr[17:2]],
memory_lane1[addr[17:2]],
memory_lane0[addr[17:2]]
};
always @(posedge clk)
begin
if (wren[0])
memory_lane0[addr[17:2]] <= wdata[7:0];
if (wren[1])
memory_lane1[addr[17:2]] <= wdata[15:8];
if (wren[2])
memory_lane2[addr[17:2]] <= wdata[23:16];
if (wren[3])
memory_lane3[addr[17:2]] <= wdata[31:24];
end
endmodule | 6 |
2,707 | data/full_repos/permissive/100822769/instruction_memory.v | 100,822,769 | instruction_memory.v | v | 52 | 155 | [] | [] | [] | [(23, 50)] | null | data/verilator_xmls/0cee160b-3dd3-4fbe-9459-affb1dcdb422.xml | null | 137 | module | module instruction_memory(
address,
instruction
);
input [31:0] address;
output [31:0] instruction;
reg [31:0] instruction_memory [255:0];
initial
begin
$readmemh("program.mips",instruction_memory);
end
assign instruction = instruction_memory[address[9:2]];
endmodule | module instruction_memory(
address,
instruction
); |
input [31:0] address;
output [31:0] instruction;
reg [31:0] instruction_memory [255:0];
initial
begin
$readmemh("program.mips",instruction_memory);
end
assign instruction = instruction_memory[address[9:2]];
endmodule | 6 |
2,712 | data/full_repos/permissive/100918256/bit_timing.v | 100,918,256 | bit_timing.v | v | 36 | 83 | [] | [] | [] | null | line:29: before: "if" | null | 1: b'%Error: data/full_repos/permissive/100918256/bit_timing.v:29: syntax error, unexpected posedge, expecting TYPE-IDENTIFIER\n if(posedge reset\n ^~~~~~~\n%Error: Cannot continue\n' | 144 | module | module bit_timing(
input rx,
input rst,
input clk,
output sampled_rx,
output baud_clk
);
if(posedge reset
endmodule | module bit_timing(
input rx,
input rst,
input clk,
output sampled_rx,
output baud_clk
); |
if(posedge reset
endmodule | 1 |
2,713 | data/full_repos/permissive/100918256/CANIPCORETEST.v | 100,918,256 | CANIPCORETEST.v | v | 93 | 112 | [] | [] | [] | [(25, 91)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:73: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:75: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:81: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:89: Unsupported: Ignoring delay on this delayed statement.\n always #5 sys_clk=~sys_clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/CANIPCORETEST.v:90: Unsupported: Ignoring delay on this delayed statement.\n always #25 can_clk=~can_clk;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:34: Little bit endian vector: MSB < LSB of bit range: 0:5\n reg [0:5] bus2ip_addr;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:35: Little bit endian vector: MSB < LSB of bit range: 0:31\n reg [0:31] bus2ip_data;\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/100918256/CANIPCORETEST.v:42: Little bit endian vector: MSB < LSB of bit range: 0:31\n wire [0:31] ip2bus_data;\n ^\n%Error: data/full_repos/permissive/100918256/CANIPCORETEST.v:45: Cannot find file containing module: \'CAN_BUS_Model\'\n CAN_BUS_Model uut (\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model.v\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/CAN_BUS_Model.sv\n CAN_BUS_Model\n CAN_BUS_Model.v\n CAN_BUS_Model.sv\n obj_dir/CAN_BUS_Model\n obj_dir/CAN_BUS_Model.v\n obj_dir/CAN_BUS_Model.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 145 | module | module CANIPCORETEST;
reg can_clk;
reg can_phy_rx;
reg bus2ip_reset;
reg bus2ip_rnw;
reg bus2ip_cs;
reg sys_clk;
reg [0:5] bus2ip_addr;
reg [0:31] bus2ip_data;
wire ip2bus_intrevent;
wire ip2bus_error;
wire ip2bus_ack;
wire can_phy_tx;
wire [0:31] ip2bus_data;
CAN_BUS_Model uut (
.can_phy_rx(can_phy_rx),
.can_clk(can_clk),
.bus2ip_reset(bus2ip_reset),
.ip2bus_intrevent(ip2bus_intrevent),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_cs(bus2ip_cs),
.ip2bus_error(ip2bus_error),
.sys_clk(sys_clk),
.ip2bus_ack(ip2bus_ack),
.can_phy_tx(can_phy_tx),
.ip2bus_data(ip2bus_data),
.bus2ip_addr(bus2ip_addr),
.bus2ip_data(bus2ip_data)
);
initial begin
can_clk = 0;
bus2ip_reset = 1;
bus2ip_rnw = 1;
bus2ip_cs = 0;
sys_clk = 0;
bus2ip_addr = 6'd3;
bus2ip_data = 32'd42;
can_phy_rx = 1;
#100;
bus2ip_reset = 0;
#10;
bus2ip_data = 32'd42;
bus2ip_addr = 6'd3;
#10;
bus2ip_cs = 1;
bus2ip_rnw = 0;
#50
bus2ip_cs = 0;
bus2ip_rnw = 1;
end
always #5 sys_clk=~sys_clk;
always #25 can_clk=~can_clk;
endmodule | module CANIPCORETEST; |
reg can_clk;
reg can_phy_rx;
reg bus2ip_reset;
reg bus2ip_rnw;
reg bus2ip_cs;
reg sys_clk;
reg [0:5] bus2ip_addr;
reg [0:31] bus2ip_data;
wire ip2bus_intrevent;
wire ip2bus_error;
wire ip2bus_ack;
wire can_phy_tx;
wire [0:31] ip2bus_data;
CAN_BUS_Model uut (
.can_phy_rx(can_phy_rx),
.can_clk(can_clk),
.bus2ip_reset(bus2ip_reset),
.ip2bus_intrevent(ip2bus_intrevent),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_cs(bus2ip_cs),
.ip2bus_error(ip2bus_error),
.sys_clk(sys_clk),
.ip2bus_ack(ip2bus_ack),
.can_phy_tx(can_phy_tx),
.ip2bus_data(ip2bus_data),
.bus2ip_addr(bus2ip_addr),
.bus2ip_data(bus2ip_data)
);
initial begin
can_clk = 0;
bus2ip_reset = 1;
bus2ip_rnw = 1;
bus2ip_cs = 0;
sys_clk = 0;
bus2ip_addr = 6'd3;
bus2ip_data = 32'd42;
can_phy_rx = 1;
#100;
bus2ip_reset = 0;
#10;
bus2ip_data = 32'd42;
bus2ip_addr = 6'd3;
#10;
bus2ip_cs = 1;
bus2ip_rnw = 0;
#50
bus2ip_cs = 0;
bus2ip_rnw = 1;
end
always #5 sys_clk=~sys_clk;
always #25 can_clk=~can_clk;
endmodule | 1 |
2,715 | data/full_repos/permissive/100918256/CRC.v | 100,918,256 | CRC.v | v | 52 | 666 | [] | [] | [] | null | line:52: before: "/" | data/verilator_xmls/fdf9839c-8945-4561-bc0f-7ab392014e3d.xml | null | 147 | module | module CRC(
input [63:0] data_in,
input crc_en,
output [14:0] crc_out,
input rst,
input clk);
reg [14:0] lfsr_q ,lfsr_c ;
assign crc_out[14:0] = lfsr_q[14:0];
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[17] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[27] ^ data_in[29] ^ data_in[33] ^ data_in[37] ^ data_in[38] ^ data_in[43] ^ data_in[45] ^ data_in[48] ^ data_in[49] ^ data_in[51] ^ data_in[52] ^ data_in[57] ^ data_in[58] ^ data_in[61] ^ data_in[62] ^ data_in[63];
lfsr_c[1] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[28] ^ data_in[30] ^ data_in[34] ^ data_in[38] ^ data_in[39] ^ data_in[44] ^ data_in[46] ^ data_in[49] ^ data_in[50] ^ data_in[52] ^ data_in[53] ^ data_in[58] ^ data_in[59] ^ data_in[62] ^ data_in[63];
lfsr_c[2] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[29] ^ data_in[31] ^ data_in[35] ^ data_in[39] ^ data_in[40] ^ data_in[45] ^ data_in[47] ^ data_in[50] ^ data_in[51] ^ data_in[53] ^ data_in[54] ^ data_in[59] ^ data_in[60] ^ data_in[63];
lfsr_c[3] = lfsr_q[0] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[5] ^ data_in[11] ^ data_in[13] ^ data_in[15] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[27] ^ data_in[29] ^ data_in[30] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[46] ^ data_in[49] ^ data_in[54] ^ data_in[55] ^ data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[62] ^ data_in[63];
lfsr_c[4] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ data_in[0] ^ data_in[4] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[27] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[39] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[59] ^ data_in[62];
lfsr_c[5] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[1] ^ data_in[5] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[40] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[53] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[63];
lfsr_c[6] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ data_in[2] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[18] ^ data_in[19] ^ data_in[21] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[41] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[53] ^ data_in[54] ^ data_in[57] ^ data_in[58] ^ data_in[59] ^ data_in[61];
lfsr_c[7] = lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[13] ^ data_in[17] ^ data_in[21] ^ data_in[22] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[34] ^ data_in[38] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[47] ^ data_in[50] ^ data_in[53] ^ data_in[54] ^ data_in[55] ^ data_in[57] ^ data_in[59] ^ data_in[60] ^ data_in[61] ^ data_in[63];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[0] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[17] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[25] ^ data_in[26] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[44] ^ data_in[47] ^ data_in[49] ^ data_in[52] ^ data_in[54] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[60] ^ data_in[63];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12] ^ data_in[1] ^ data_in[5] ^ data_in[6] ^ data_in[7] ^ data_in[10] ^ data_in[12] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[26] ^ data_in[27] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[45] ^ data_in[48] ^ data_in[50] ^ data_in[53] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[61];
lfsr_c[10] = lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[17] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[28] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[46] ^ data_in[48] ^ data_in[52] ^ data_in[54] ^ data_in[56] ^ data_in[59] ^ data_in[61] ^ data_in[63];
lfsr_c[11] = lfsr_q[0] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[13] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[14] ^ data_in[15] ^ data_in[18] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[29] ^ data_in[30] ^ data_in[33] ^ data_in[35] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[44] ^ data_in[46] ^ data_in[47] ^ data_in[49] ^ data_in[53] ^ data_in[55] ^ data_in[57] ^ data_in[60] ^ data_in[62];
lfsr_c[12] = lfsr_q[1] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ data_in[16] ^ data_in[19] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[36] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[45] ^ data_in[47] ^ data_in[48] ^ data_in[50] ^ data_in[54] ^ data_in[56] ^ data_in[58] ^ data_in[61] ^ data_in[63];
lfsr_c[13] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[17] ^ data_in[20] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[28] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[48] ^ data_in[49] ^ data_in[51] ^ data_in[55] ^ data_in[57] ^ data_in[59] ^ data_in[62];
lfsr_c[14] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[26] ^ data_in[28] ^ data_in[32] ^ data_in[36] ^ data_in[37] ^ data_in[42] ^ data_in[44] ^ data_in[47] ^ data_in[48] ^ data_in[50] ^ data_in[51] ^ data_in[56] ^ data_in[57] ^ data_in[60] ^ data_in[61] ^ data_in[62];
end
always @(posedge clk or posedge rst) begin
if(rst) begin
lfsr_q <= {15{1'b1}};
end
else begin
lfsr_q[14:0] <= crc_en ? lfsr_c[14:0] : lfsr_q[14:0];
end
end
endmodule | module CRC(
input [63:0] data_in,
input crc_en,
output [14:0] crc_out,
input rst,
input clk); |
reg [14:0] lfsr_q ,lfsr_c ;
assign crc_out[14:0] = lfsr_q[14:0];
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[17] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[27] ^ data_in[29] ^ data_in[33] ^ data_in[37] ^ data_in[38] ^ data_in[43] ^ data_in[45] ^ data_in[48] ^ data_in[49] ^ data_in[51] ^ data_in[52] ^ data_in[57] ^ data_in[58] ^ data_in[61] ^ data_in[62] ^ data_in[63];
lfsr_c[1] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[18] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[28] ^ data_in[30] ^ data_in[34] ^ data_in[38] ^ data_in[39] ^ data_in[44] ^ data_in[46] ^ data_in[49] ^ data_in[50] ^ data_in[52] ^ data_in[53] ^ data_in[58] ^ data_in[59] ^ data_in[62] ^ data_in[63];
lfsr_c[2] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[16] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[29] ^ data_in[31] ^ data_in[35] ^ data_in[39] ^ data_in[40] ^ data_in[45] ^ data_in[47] ^ data_in[50] ^ data_in[51] ^ data_in[53] ^ data_in[54] ^ data_in[59] ^ data_in[60] ^ data_in[63];
lfsr_c[3] = lfsr_q[0] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[13] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[5] ^ data_in[11] ^ data_in[13] ^ data_in[15] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[27] ^ data_in[29] ^ data_in[30] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[37] ^ data_in[38] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[46] ^ data_in[49] ^ data_in[54] ^ data_in[55] ^ data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[62] ^ data_in[63];
lfsr_c[4] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ data_in[0] ^ data_in[4] ^ data_in[7] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[16] ^ data_in[17] ^ data_in[19] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[27] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[39] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[59] ^ data_in[62];
lfsr_c[5] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[1] ^ data_in[5] ^ data_in[8] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[17] ^ data_in[18] ^ data_in[20] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[40] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[53] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[60] ^ data_in[63];
lfsr_c[6] = lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ data_in[2] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[18] ^ data_in[19] ^ data_in[21] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[41] ^ data_in[43] ^ data_in[44] ^ data_in[45] ^ data_in[46] ^ data_in[47] ^ data_in[48] ^ data_in[49] ^ data_in[50] ^ data_in[51] ^ data_in[52] ^ data_in[53] ^ data_in[54] ^ data_in[57] ^ data_in[58] ^ data_in[59] ^ data_in[61];
lfsr_c[7] = lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[13] ^ data_in[17] ^ data_in[21] ^ data_in[22] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[28] ^ data_in[29] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[34] ^ data_in[38] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[47] ^ data_in[50] ^ data_in[53] ^ data_in[54] ^ data_in[55] ^ data_in[57] ^ data_in[59] ^ data_in[60] ^ data_in[61] ^ data_in[63];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[14] ^ data_in[0] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[9] ^ data_in[11] ^ data_in[17] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[25] ^ data_in[26] ^ data_in[30] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[38] ^ data_in[39] ^ data_in[44] ^ data_in[47] ^ data_in[49] ^ data_in[52] ^ data_in[54] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[60] ^ data_in[63];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12] ^ data_in[1] ^ data_in[5] ^ data_in[6] ^ data_in[7] ^ data_in[10] ^ data_in[12] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[21] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[26] ^ data_in[27] ^ data_in[31] ^ data_in[32] ^ data_in[33] ^ data_in[36] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[45] ^ data_in[48] ^ data_in[50] ^ data_in[53] ^ data_in[55] ^ data_in[56] ^ data_in[57] ^ data_in[58] ^ data_in[61];
lfsr_c[10] = lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[12] ^ data_in[13] ^ data_in[14] ^ data_in[17] ^ data_in[22] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[28] ^ data_in[29] ^ data_in[32] ^ data_in[34] ^ data_in[38] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[43] ^ data_in[45] ^ data_in[46] ^ data_in[48] ^ data_in[52] ^ data_in[54] ^ data_in[56] ^ data_in[59] ^ data_in[61] ^ data_in[63];
lfsr_c[11] = lfsr_q[0] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[13] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[14] ^ data_in[15] ^ data_in[18] ^ data_in[23] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[29] ^ data_in[30] ^ data_in[33] ^ data_in[35] ^ data_in[39] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[44] ^ data_in[46] ^ data_in[47] ^ data_in[49] ^ data_in[53] ^ data_in[55] ^ data_in[57] ^ data_in[60] ^ data_in[62];
lfsr_c[12] = lfsr_q[1] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[14] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[10] ^ data_in[11] ^ data_in[12] ^ data_in[14] ^ data_in[15] ^ data_in[16] ^ data_in[19] ^ data_in[24] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[30] ^ data_in[31] ^ data_in[34] ^ data_in[36] ^ data_in[40] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[45] ^ data_in[47] ^ data_in[48] ^ data_in[50] ^ data_in[54] ^ data_in[56] ^ data_in[58] ^ data_in[61] ^ data_in[63];
lfsr_c[13] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7] ^ data_in[11] ^ data_in[12] ^ data_in[13] ^ data_in[15] ^ data_in[16] ^ data_in[17] ^ data_in[20] ^ data_in[25] ^ data_in[26] ^ data_in[27] ^ data_in[28] ^ data_in[31] ^ data_in[32] ^ data_in[35] ^ data_in[37] ^ data_in[41] ^ data_in[42] ^ data_in[43] ^ data_in[44] ^ data_in[46] ^ data_in[48] ^ data_in[49] ^ data_in[51] ^ data_in[55] ^ data_in[57] ^ data_in[59] ^ data_in[62];
lfsr_c[14] = lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[8] ^ data_in[9] ^ data_in[10] ^ data_in[11] ^ data_in[13] ^ data_in[16] ^ data_in[18] ^ data_in[19] ^ data_in[20] ^ data_in[26] ^ data_in[28] ^ data_in[32] ^ data_in[36] ^ data_in[37] ^ data_in[42] ^ data_in[44] ^ data_in[47] ^ data_in[48] ^ data_in[50] ^ data_in[51] ^ data_in[56] ^ data_in[57] ^ data_in[60] ^ data_in[61] ^ data_in[62];
end
always @(posedge clk or posedge rst) begin
if(rst) begin
lfsr_q <= {15{1'b1}};
end
else begin
lfsr_q[14:0] <= crc_en ? lfsr_c[14:0] : lfsr_q[14:0];
end
end
endmodule | 1 |
2,718 | data/full_repos/permissive/100918256/One-ShotTest.v | 100,918,256 | One-ShotTest.v | v | 62 | 111 | [] | [] | [] | [(25, 60)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:54: Unsupported: Ignoring delay on this delayed statement.\n #100; $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/One-ShotTest.v:58: Unsupported: Ignoring delay on this delayed statement.\n always #1.25 clk=~clk;\n ^\n%Error: data/full_repos/permissive/100918256/One-ShotTest.v:36: Cannot find file containing module: \'OneShot\'\n OneShot uut (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot.v\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/OneShot.sv\n OneShot\n OneShot.v\n OneShot.sv\n obj_dir/OneShot\n obj_dir/OneShot.v\n obj_dir/OneShot.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 150 | module | module OneShotTest;
reg pulse;
reg clk;
reg rst;
wire out;
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
pulse = 0;
clk = 0;
rst = 1;
#100;
rst = 0;
#10;
pulse = 1;
#100; $stop;
end
always #1.25 clk=~clk;
endmodule | module OneShotTest; |
reg pulse;
reg clk;
reg rst;
wire out;
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
pulse = 0;
clk = 0;
rst = 1;
#100;
rst = 0;
#10;
pulse = 1;
#100; $stop;
end
always #1.25 clk=~clk;
endmodule | 1 |
2,720 | data/full_repos/permissive/100918256/rx_can.v | 100,918,256 | rx_can.v | v | 43 | 83 | [] | [] | [] | null | line:37: before: "rst" | null | 1: b'%Error: data/full_repos/permissive/100918256/rx_can.v:42: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n' | 152 | module | module rx_container(
output reg [63:0] rx_data,
output reg rxing,
input txing,
input rx,
input clk,
input baud_clk,
input rst
);
initial rxing = 1'b0;
initial rx_data = 64'd0;
reg[63:0] shift_buffer = 64'd0;
always @ (posedge clk or rst) begin
endmodule | module rx_container(
output reg [63:0] rx_data,
output reg rxing,
input txing,
input rx,
input clk,
input baud_clk,
input rst
); |
initial rxing = 1'b0;
initial rx_data = 64'd0;
reg[63:0] shift_buffer = 64'd0;
always @ (posedge clk or rst) begin
endmodule | 1 |
2,724 | data/full_repos/permissive/100918256/Tx_test_internal.v | 100,918,256 | Tx_test_internal.v | v | 84 | 115 | [] | [] | [] | null | line:75: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:70: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:72: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:75: Unsupported: Ignoring delay on this delayed statement.\n #300000 $stop;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:79: Unsupported: Ignoring delay on this delayed statement.\n always #1.25 clk=~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100918256/Tx_test_internal.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1000 baud_clk=~baud_clk;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/100918256/Tx_test_internal.v:35: Signal definition not found, creating implicitly: \'rx\'\n : ... Suggested alternative: \'tx\'\n assign rx = tx;\n ^~\n%Warning-IMPLICIT: data/full_repos/permissive/100918256/Tx_test_internal.v:36: Signal definition not found, creating implicitly: \'bitstuffed_output\'\n assign bitstuffed_output = tx;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100918256/Tx_test_internal.v:44: Cannot find file containing module: \'can_tx\'\n can_tx uut (\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx.v\n data/full_repos/permissive/100918256,data/full_repos/permissive/100918256/can_tx.sv\n can_tx\n can_tx.v\n can_tx.sv\n obj_dir/can_tx\n obj_dir/can_tx.v\n obj_dir/can_tx.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 156 | module | module Tx_test_internal;
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
wire tx;
wire can_bitstuff;
wire txing;
can_tx uut (
.tx(tx),
.can_bitstuff(can_bitstuff),
.txing(txing),
.rx(rx),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data),
.bitstuffed_output(bitstuffed_output),
.clear_to_tx(clear_to_tx)
);
initial begin
address = 11'h28;
clk = 0;
baud_clk = 0;
rst = 1;
data = 43;
send_data = 0;
clear_to_tx = 0;
#100;
rst = 0;
#10;
send_data = 1;
clear_to_tx = 1;
#300000 $stop;
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule | module Tx_test_internal; |
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;
reg clear_to_tx;
assign rx = tx;
assign bitstuffed_output = tx;
wire tx;
wire can_bitstuff;
wire txing;
can_tx uut (
.tx(tx),
.can_bitstuff(can_bitstuff),
.txing(txing),
.rx(rx),
.address(address),
.clk(clk),
.baud_clk(baud_clk),
.rst(rst),
.data(data),
.send_data(send_data),
.bitstuffed_output(bitstuffed_output),
.clear_to_tx(clear_to_tx)
);
initial begin
address = 11'h28;
clk = 0;
baud_clk = 0;
rst = 1;
data = 43;
send_data = 0;
clear_to_tx = 0;
#100;
rst = 0;
#10;
send_data = 1;
clear_to_tx = 1;
#300000 $stop;
end
always #1.25 clk=~clk;
always #1000 baud_clk=~baud_clk;
endmodule | 1 |
2,725 | data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v | 100,975,158 | ManBearPig.v | v | 180 | 69 | [] | [] | [] | [(3, 179)] | null | null | 1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v:72: Cannot find file containing module: 'Processor'\n Processor MIPS_Processor (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full,data/full_repos/permissive/100975158/Processor\n data/full_repos/permissive/100975158/MIPS32_Full,data/full_repos/permissive/100975158/Processor.v\n data/full_repos/permissive/100975158/MIPS32_Full,data/full_repos/permissive/100975158/Processor.sv\n Processor\n Processor.v\n Processor.sv\n obj_dir/Processor\n obj_dir/Processor.v\n obj_dir/Processor.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v:87: Cannot find file containing module: 'MemoryMappedUART'\n MemoryMappedUART UART0 (\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v:103: Cannot find file containing module: 'MemoryMappedUART'\n MemoryMappedUART UART1 (\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v:119: Cannot find file containing module: 'DataMemoryInterface'\n DataMemoryInterface DataMemory (\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/ManBearPig.v:167: Cannot find file containing module: 'Multiplex4'\n Multiplex4 #(.WIDTH (32)) MemoryReadSelection (\n ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 158 | module | module ManBearPig (
input clock,
input reset,
input rx_source_0,
output tx_source_0,
input rx_source_1,
output tx_source_1,
output d_test_valid,
output d_uart0_read,
output d_uart1_read,
output d_uart0_write,
output d_uart1_write,
output d_mem_read,
output d_mem_write,
output [1:0] d_mem_map,
output [31:0] d_datamemory_address
);
wire datamemory_write;
wire datamemory_read;
wire [31:0] datamemory_read_data;
wire [31:0] datamemory_write_data;
wire [31:0] datamemory_address;
reg memory_read;
reg memory_write;
wire [31:0] memory_data;
reg uart0_read;
reg uart0_write;
wire [31:0] uart0_data;
wire uart0_tx;
reg uart1_read;
reg uart1_write;
wire [31:0] uart1_data;
wire uart1_tx;
reg [1:0] memory_map;
assign d_uart0_read = (uart0_read);
assign d_uart1_read = (uart1_read);
assign d_uart0_write = (uart0_write);
assign d_uart1_write = (uart1_write);
assign d_mem_read = (datamemory_read);
assign d_mem_write = (datamemory_write);
assign d_mem_map = (memory_map);
assign d_datamemory_address = datamemory_address;
Processor MIPS_Processor (
.clock (clock),
.reset (reset),
.me_memory_address_out (datamemory_address),
.me_memory_read_out (datamemory_read),
.me_memory_data_read_in (datamemory_read_data),
.me_memory_write_out (datamemory_write),
.me_memory_data_write_out (datamemory_write_data),
.d_test_valid (d_test_valid)
);
MemoryMappedUART UART0 (
.clock (clock),
.reset (reset),
.selected (1'b1),
.rx_signal (rx_source_0),
.tx_signal (uart0_tx),
.address (datamemory_address[7:0]),
.in_data (datamemory_write_data[7:0]),
.out_data (uart0_data),
.write (uart0_write),
.read (uart0_read)
);
MemoryMappedUART UART1 (
.clock (clock),
.reset (reset),
.selected (1'b1),
.rx_signal (rx_source_1),
.tx_signal (uart1_tx),
.address (datamemory_address[7:0]),
.in_data (datamemory_write_data[7:0]),
.out_data (uart1_data),
.write (uart1_write),
.read (uart1_read)
);
DataMemoryInterface DataMemory (
.clock (clock),
.reset (reset),
.address (datamemory_address),
.mem_write (memory_write),
.data_write (datamemory_write_data),
.mem_read (memory_read),
.read_data (memory_data)
);
always @ ( * ) begin
case (datamemory_address[8])
0 : begin
memory_map <= 2'd0;
memory_read <= datamemory_read;
memory_write <= datamemory_write;
uart0_read <= 1'b0;
uart0_write <= 1'b0;
uart1_read <= 1'b0;
uart1_write <= 1'b0;
end
1 : begin
case (datamemory_address[9])
0 : begin
memory_map <= 2'd1;
memory_read <= 1'b0;
memory_write <= 1'b0;
uart0_read <= datamemory_read;
uart0_write <= datamemory_write;
uart1_read <= 1'b0;
uart1_write <= 1'b0;
end
1 : begin
memory_map <= 2'd2;
memory_read <= 1'b0;
memory_write <= 1'b0;
uart0_read <= 1'b0;
uart0_write <= 1'b0;
uart1_read <= datamemory_read;
uart1_write <= datamemory_write;
end
endcase
end
endcase
end
Multiplex4 #(.WIDTH (32)) MemoryReadSelection (
.sel (memory_map),
.in0 (memory_data),
.in1 (uart0_data),
.in2 (uart1_data),
.in3 (32'hxxxxxxxx),
.out (datamemory_read_data)
);
assign tx_source_0 = uart0_tx;
assign tx_source_1 = uart1_tx;
endmodule | module ManBearPig (
input clock,
input reset,
input rx_source_0,
output tx_source_0,
input rx_source_1,
output tx_source_1,
output d_test_valid,
output d_uart0_read,
output d_uart1_read,
output d_uart0_write,
output d_uart1_write,
output d_mem_read,
output d_mem_write,
output [1:0] d_mem_map,
output [31:0] d_datamemory_address
); |
wire datamemory_write;
wire datamemory_read;
wire [31:0] datamemory_read_data;
wire [31:0] datamemory_write_data;
wire [31:0] datamemory_address;
reg memory_read;
reg memory_write;
wire [31:0] memory_data;
reg uart0_read;
reg uart0_write;
wire [31:0] uart0_data;
wire uart0_tx;
reg uart1_read;
reg uart1_write;
wire [31:0] uart1_data;
wire uart1_tx;
reg [1:0] memory_map;
assign d_uart0_read = (uart0_read);
assign d_uart1_read = (uart1_read);
assign d_uart0_write = (uart0_write);
assign d_uart1_write = (uart1_write);
assign d_mem_read = (datamemory_read);
assign d_mem_write = (datamemory_write);
assign d_mem_map = (memory_map);
assign d_datamemory_address = datamemory_address;
Processor MIPS_Processor (
.clock (clock),
.reset (reset),
.me_memory_address_out (datamemory_address),
.me_memory_read_out (datamemory_read),
.me_memory_data_read_in (datamemory_read_data),
.me_memory_write_out (datamemory_write),
.me_memory_data_write_out (datamemory_write_data),
.d_test_valid (d_test_valid)
);
MemoryMappedUART UART0 (
.clock (clock),
.reset (reset),
.selected (1'b1),
.rx_signal (rx_source_0),
.tx_signal (uart0_tx),
.address (datamemory_address[7:0]),
.in_data (datamemory_write_data[7:0]),
.out_data (uart0_data),
.write (uart0_write),
.read (uart0_read)
);
MemoryMappedUART UART1 (
.clock (clock),
.reset (reset),
.selected (1'b1),
.rx_signal (rx_source_1),
.tx_signal (uart1_tx),
.address (datamemory_address[7:0]),
.in_data (datamemory_write_data[7:0]),
.out_data (uart1_data),
.write (uart1_write),
.read (uart1_read)
);
DataMemoryInterface DataMemory (
.clock (clock),
.reset (reset),
.address (datamemory_address),
.mem_write (memory_write),
.data_write (datamemory_write_data),
.mem_read (memory_read),
.read_data (memory_data)
);
always @ ( * ) begin
case (datamemory_address[8])
0 : begin
memory_map <= 2'd0;
memory_read <= datamemory_read;
memory_write <= datamemory_write;
uart0_read <= 1'b0;
uart0_write <= 1'b0;
uart1_read <= 1'b0;
uart1_write <= 1'b0;
end
1 : begin
case (datamemory_address[9])
0 : begin
memory_map <= 2'd1;
memory_read <= 1'b0;
memory_write <= 1'b0;
uart0_read <= datamemory_read;
uart0_write <= datamemory_write;
uart1_read <= 1'b0;
uart1_write <= 1'b0;
end
1 : begin
memory_map <= 2'd2;
memory_read <= 1'b0;
memory_write <= 1'b0;
uart0_read <= 1'b0;
uart0_write <= 1'b0;
uart1_read <= datamemory_read;
uart1_write <= datamemory_write;
end
endcase
end
endcase
end
Multiplex4 #(.WIDTH (32)) MemoryReadSelection (
.sel (memory_map),
.in0 (memory_data),
.in1 (uart0_data),
.in2 (uart1_data),
.in3 (32'hxxxxxxxx),
.out (datamemory_read_data)
);
assign tx_source_0 = uart0_tx;
assign tx_source_1 = uart1_tx;
endmodule | 0 |
2,726 | data/full_repos/permissive/100975158/MIPS32_Full/Memory/MemoryMappedUART.v | 100,975,158 | MemoryMappedUART.v | v | 60 | 118 | [] | [] | [] | [(3, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/Memory/MemoryMappedUART.v:35: Cannot find file containing module: 'UART'\n UART UART_Instance (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Memory,data/full_repos/permissive/100975158/UART\n data/full_repos/permissive/100975158/MIPS32_Full/Memory,data/full_repos/permissive/100975158/UART.v\n data/full_repos/permissive/100975158/MIPS32_Full/Memory,data/full_repos/permissive/100975158/UART.sv\n UART\n UART.v\n UART.sv\n obj_dir/UART\n obj_dir/UART.v\n obj_dir/UART.sv\n%Error: Exiting due to 1 error(s)\n" | 159 | module | module MemoryMappedUART (
input clock,
input reset,
input selected,
input rx_signal,
output tx_signal,
input [7:0] address,
input write,
input [7:0] in_data,
input read,
output [31:0] out_data,
output uart_clock,
output uart_clock_16,
output [7:0] debug_data
);
wire read_uart = ((address == 8'd0) & read);
wire read_aval = ((address == 8'd4) & read);
wire write_uart = ((address == 8'd8) & write);
wire [7:0] uart_read_data;
wire uart_data_avaliable;
wire clock_def;
assign clock_def = (selected) ? clock : 1'b0;
UART UART_Instance (
.clock (clock_def),
.reset (reset),
.rx (rx_signal),
.tx (tx_signal),
.write (write_uart),
.read (read_uart),
.data_write (in_data),
.data_read (uart_read_data),
.data_ready (uart_data_avaliable),
.uart_clock (uart_clock),
.uart_clock_16 (uart_clock_16),
.debug_data (debug_data)
);
assign out_data = (read_uart) ? {24'd0, uart_read_data} : ( (read_aval) ? {31'd0, uart_data_avaliable} : 32'd0 );
endmodule | module MemoryMappedUART (
input clock,
input reset,
input selected,
input rx_signal,
output tx_signal,
input [7:0] address,
input write,
input [7:0] in_data,
input read,
output [31:0] out_data,
output uart_clock,
output uart_clock_16,
output [7:0] debug_data
); |
wire read_uart = ((address == 8'd0) & read);
wire read_aval = ((address == 8'd4) & read);
wire write_uart = ((address == 8'd8) & write);
wire [7:0] uart_read_data;
wire uart_data_avaliable;
wire clock_def;
assign clock_def = (selected) ? clock : 1'b0;
UART UART_Instance (
.clock (clock_def),
.reset (reset),
.rx (rx_signal),
.tx (tx_signal),
.write (write_uart),
.read (read_uart),
.data_write (in_data),
.data_read (uart_read_data),
.data_ready (uart_data_avaliable),
.uart_clock (uart_clock),
.uart_clock_16 (uart_clock_16),
.debug_data (debug_data)
);
assign out_data = (read_uart) ? {24'd0, uart_read_data} : ( (read_aval) ? {31'd0, uart_data_avaliable} : 32'd0 );
endmodule | 0 |
2,727 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v | 100,975,158 | ArithmeticLogicUnit.v | v | 62 | 89 | [] | [] | [] | [(154, 211)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: Define or directive not defined: \'`ALUOP_ADD\'\n assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:24: Define or directive not defined: \'`ALUOP_ADDU\'\n assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:34: Define or directive not defined: \'`ALUOP_ADD\'\n `ALUOP_ADD : result <= AddSub_Result;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:34: syntax error, unexpected \':\', expecting endcase\n `ALUOP_ADD : result <= AddSub_Result;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:35: Define or directive not defined: \'`ALUOP_ADDU\'\n `ALUOP_ADDU : result <= AddSub_Result;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:36: Define or directive not defined: \'`ALUOP_AND\'\n `ALUOP_AND : result <= (A & B);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:37: Define or directive not defined: \'`ALUOP_MUL\'\n `ALUOP_MUL : result <= Mult_Result[31:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:38: Define or directive not defined: \'`ALUOP_NOR\'\n `ALUOP_NOR : result <= ~(A | B);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:39: Define or directive not defined: \'`ALUOP_OR\'\n `ALUOP_OR : result <= (A | B);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:40: Define or directive not defined: \'`ALUOP_SLL\'\n `ALUOP_SLL : result <= B << shamt;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:41: Define or directive not defined: \'`ALUOP_SLT\'\n `ALUOP_SLT : result <= (A_signed < B_signed) ? 32\'h00000001 : 32\'h00000000;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:42: Define or directive not defined: \'`ALUOP_SLTU\'\n `ALUOP_SLTU : result <= (A < B) ? 32\'h00000001 : 32\'h00000000;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:43: Define or directive not defined: \'`ALUOP_SRL\'\n `ALUOP_SRL : result <= B >> shamt;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:44: Define or directive not defined: \'`ALUOP_SUB\'\n `ALUOP_SUB : result <= AddSub_Result;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:45: Define or directive not defined: \'`ALUOP_SUBU\'\n `ALUOP_SUBU : result <= AddSub_Result;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:46: Define or directive not defined: \'`ALUOP_XOR\'\n `ALUOP_XOR : result <= A ^ B;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:54: Define or directive not defined: \'`ALUOP_ADD\'\n `ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ArithmeticLogicUnit.v:55: Define or directive not defined: \'`ALUOP_SUB\'\n `ALUOP_SUB : overflow <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));\n ^~~~~~~~~~\n%Error: Cannot continue\n' | 160 | module | module ArithmeticLogicUnit (
input [31:0] A,
input [31:0] B,
input [4:0] operation,
input signed [4:0] shamt,
output reg signed [31:0] result,
output reg overflow
);
wire AddSub;
wire signed [31:0] A_signed;
wire signed [31:0] B_signed;
wire signed [31:0] AddSub_Result;
wire signed [31:0] Mult_Result;
assign A_signed = A;
assign B_signed = B;
assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));
assign AddSub_Result = (AddSub) ? (A + B) : (A - B);
assign Mult_Result = A_signed * B_signed;
always @ ( * ) begin
case (operation)
`ALUOP_ADD : result <= AddSub_Result;
`ALUOP_ADDU : result <= AddSub_Result;
`ALUOP_AND : result <= (A & B);
`ALUOP_MUL : result <= Mult_Result[31:0];
`ALUOP_NOR : result <= ~(A | B);
`ALUOP_OR : result <= (A | B);
`ALUOP_SLL : result <= B << shamt;
`ALUOP_SLT : result <= (A_signed < B_signed) ? 32'h00000001 : 32'h00000000;
`ALUOP_SLTU : result <= (A < B) ? 32'h00000001 : 32'h00000000;
`ALUOP_SRL : result <= B >> shamt;
`ALUOP_SUB : result <= AddSub_Result;
`ALUOP_SUBU : result <= AddSub_Result;
`ALUOP_XOR : result <= A ^ B;
default : result <= 32'hxxxxxxxx;
endcase
end
always @ ( * ) begin
case (operation)
`ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
`ALUOP_SUB : overflow <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
default : overflow <= 0;
endcase
end
endmodule | module ArithmeticLogicUnit (
input [31:0] A,
input [31:0] B,
input [4:0] operation,
input signed [4:0] shamt,
output reg signed [31:0] result,
output reg overflow
); |
wire AddSub;
wire signed [31:0] A_signed;
wire signed [31:0] B_signed;
wire signed [31:0] AddSub_Result;
wire signed [31:0] Mult_Result;
assign A_signed = A;
assign B_signed = B;
assign AddSub = ( (operation == `ALUOP_ADD) | (operation == `ALUOP_ADDU));
assign AddSub_Result = (AddSub) ? (A + B) : (A - B);
assign Mult_Result = A_signed * B_signed;
always @ ( * ) begin
case (operation)
`ALUOP_ADD : result <= AddSub_Result;
`ALUOP_ADDU : result <= AddSub_Result;
`ALUOP_AND : result <= (A & B);
`ALUOP_MUL : result <= Mult_Result[31:0];
`ALUOP_NOR : result <= ~(A | B);
`ALUOP_OR : result <= (A | B);
`ALUOP_SLL : result <= B << shamt;
`ALUOP_SLT : result <= (A_signed < B_signed) ? 32'h00000001 : 32'h00000000;
`ALUOP_SLTU : result <= (A < B) ? 32'h00000001 : 32'h00000000;
`ALUOP_SRL : result <= B >> shamt;
`ALUOP_SUB : result <= AddSub_Result;
`ALUOP_SUBU : result <= AddSub_Result;
`ALUOP_XOR : result <= A ^ B;
default : result <= 32'hxxxxxxxx;
endcase
end
always @ ( * ) begin
case (operation)
`ALUOP_ADD : overflow <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
`ALUOP_SUB : overflow <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
default : overflow <= 0;
endcase
end
endmodule | 0 |
2,728 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Comparator.v | 100,975,158 | Comparator.v | v | 14 | 85 | [] | [] | [] | [(3, 13)] | null | data/verilator_xmls/1a344103-fbfa-4cb9-a32f-63005c2d96b2.xml | null | 161 | module | module Comparator (
input [31:0] A,
input [31:0] B,
output Equals
);
assign Equals = (A == B);
endmodule | module Comparator (
input [31:0] A,
input [31:0] B,
output Equals
); |
assign Equals = (A == B);
endmodule | 0 |
2,729 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v | 100,975,158 | ControlUnity.v | v | 236 | 88 | [] | [] | [] | [(154, 385)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:39: Define or directive not defined: \'`SIG_NOP\'\n signals <= `SIG_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n signals <= `SIG_NOP;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:44: Define or directive not defined: \'`OPCODE_TYPE_R\'\n `OPCODE_TYPE_R: begin\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:44: syntax error, unexpected \':\', expecting endcase\n `OPCODE_TYPE_R: begin\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:46: Define or directive not defined: \'`FUNCT_ADD\'\n `FUNCT_ADD : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:47: Define or directive not defined: \'`SIG_ADD\'\n signals <= `SIG_ADD;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:49: Define or directive not defined: \'`FUNCT_ADDU\'\n `FUNCT_ADDU : begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:49: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_ADDU : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:50: Define or directive not defined: \'`SIG_ADDU\'\n signals <= `SIG_ADDU;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:52: Define or directive not defined: \'`FUNCT_AND\'\n `FUNCT_AND : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:52: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_AND : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:53: Define or directive not defined: \'`SIG_AND\'\n signals <= `SIG_AND;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:55: Define or directive not defined: \'`FUNCT_JR\'\n `FUNCT_JR : begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:55: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_JR : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:56: Define or directive not defined: \'`SIG_JR\'\n signals <= `SIG_JR;\n ^~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:58: Define or directive not defined: \'`FUNCT_NOR\'\n `FUNCT_NOR : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:58: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_NOR : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:59: Define or directive not defined: \'`SIG_NOR\'\n signals <= `SIG_NOR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:61: Define or directive not defined: \'`FUNCT_OR\'\n `FUNCT_OR : begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:61: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_OR : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:62: Define or directive not defined: \'`SIG_OR\'\n signals <= `SIG_OR;\n ^~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:64: Define or directive not defined: \'`FUNCT_SLL\'\n `FUNCT_SLL : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:64: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_SLL : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:65: Define or directive not defined: \'`SIG_SLL\'\n signals <= `SIG_SLL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:67: Define or directive not defined: \'`FUNCT_SLT\'\n `FUNCT_SLT : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:67: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_SLT : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:68: Define or directive not defined: \'`SIG_SLT\'\n signals <= `SIG_SLT;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:70: Define or directive not defined: \'`FUNCT_SRL\'\n `FUNCT_SRL : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:70: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_SRL : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:71: Define or directive not defined: \'`SIG_SRL\'\n signals <= `SIG_SRL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:73: Define or directive not defined: \'`FUNCT_SUB\'\n `FUNCT_SUB : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:73: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_SUB : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:74: Define or directive not defined: \'`SIG_SUB\'\n signals <= `SIG_SUB;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:76: Define or directive not defined: \'`FUNCT_SUBU\'\n `FUNCT_SUBU : begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:76: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_SUBU : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:77: Define or directive not defined: \'`SIG_SUBU\'\n signals <= `SIG_SUBU;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:79: Define or directive not defined: \'`FUNCT_XOR\'\n `FUNCT_XOR : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:79: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FUNCT_XOR : begin\n ^~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:80: Define or directive not defined: \'`SIG_XOR\'\n signals <= `SIG_XOR;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:83: Define or directive not defined: \'`SIG_NOP\'\n signals <= `SIG_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:88: Define or directive not defined: \'`OPCODE_TYPE_R_EX\'\n `OPCODE_TYPE_R_EX: begin\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:90: Define or directive not defined: \'`FUNCT_MUL\'\n `FUNCT_MUL : begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:91: Define or directive not defined: \'`SIG_MUL\'\n signals <= `SIG_MUL;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:94: Define or directive not defined: \'`SIG_NOP\'\n signals <= `SIG_NOP;\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:99: Define or directive not defined: \'`OPCODE_ADDI\'\n `OPCODE_ADDI : begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:100: Define or directive not defined: \'`SIG_ADDI\'\n signals <= `SIG_ADDI;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:103: Define or directive not defined: \'`OPCODE_ADDIU\'\n `OPCODE_ADDIU : begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:104: Define or directive not defined: \'`SIG_ADDIU\'\n signals <= `SIG_ADDIU;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/ControlUnity.v:107: Define or directive not defined: \'`OPCODE_SLTI\'\n `OPCODE_SLTI : begin\n ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 163 | module | module ControlUnity (
input id_stall,
input [5:0] id_opcode,
input [5:0] id_funct,
input id_cmp_eq,
output if_flush,
output reg [7:0] id_signal_forwarding,
output [1:0] id_pc_source_sel,
output id_sign_extend,
output id_jump_link,
output id_reg_dst,
output id_alu_src,
output id_branch_delay_slot,
output reg [4:0] id_alu_op,
output id_mem_write,
output id_mem_read,
output id_mem_to_reg,
output id_reg_write
);
wire branch, branch_eq, branch_ne;
reg [8:0] signals;
assign id_pc_source_sel[0] = signals[7];
assign id_jump_link = signals[6];
assign id_alu_src = signals[5];
assign id_reg_dst = signals[4];
assign id_mem_read = signals[3];
assign id_mem_write = signals[2];
assign id_mem_to_reg = signals[1];
assign id_reg_write = signals[0];
always @ ( * ) begin
if (id_stall) begin
signals <= `SIG_NOP;
end
else begin
case (id_opcode)
`OPCODE_TYPE_R: begin
case (id_funct)
`FUNCT_ADD : begin
signals <= `SIG_ADD;
end
`FUNCT_ADDU : begin
signals <= `SIG_ADDU;
end
`FUNCT_AND : begin
signals <= `SIG_AND;
end
`FUNCT_JR : begin
signals <= `SIG_JR;
end
`FUNCT_NOR : begin
signals <= `SIG_NOR;
end
`FUNCT_OR : begin
signals <= `SIG_OR;
end
`FUNCT_SLL : begin
signals <= `SIG_SLL;
end
`FUNCT_SLT : begin
signals <= `SIG_SLT;
end
`FUNCT_SRL : begin
signals <= `SIG_SRL;
end
`FUNCT_SUB : begin
signals <= `SIG_SUB;
end
`FUNCT_SUBU : begin
signals <= `SIG_SUBU;
end
`FUNCT_XOR : begin
signals <= `SIG_XOR;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
`OPCODE_TYPE_R_EX: begin
case (id_funct)
`FUNCT_MUL : begin
signals <= `SIG_MUL;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
`OPCODE_ADDI : begin
signals <= `SIG_ADDI;
end
`OPCODE_ADDIU : begin
signals <= `SIG_ADDIU;
end
`OPCODE_SLTI : begin
signals <= `SIG_SLTI;
end
`OPCODE_J : begin
signals <= `SIG_J;
end
`OPCODE_JAL : begin
signals <= `SIG_JAL;
end
`OPCODE_BEQ : begin
signals <= `SIG_BEQ;
end
`OPCODE_BNE : begin
signals <= `SIG_BNE;
end
`OPCODE_LW : begin
signals <= `SIG_LW;
end
`OPCODE_SW : begin
signals <= `SIG_SW;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
end
always @ ( * ) begin
case (id_opcode)
`OPCODE_TYPE_R : begin
case (id_funct)
`FUNCT_ADD : id_signal_forwarding <= `HAZ_ADD;
`FUNCT_ADDU : id_signal_forwarding <= `HAZ_ADDU;
`FUNCT_AND : id_signal_forwarding <= `HAZ_AND;
`FUNCT_JR : id_signal_forwarding <= `HAZ_JR;
`FUNCT_NOR : id_signal_forwarding <= `HAZ_NOR;
`FUNCT_OR : id_signal_forwarding <= `HAZ_OR;
`FUNCT_SLL : id_signal_forwarding <= `HAZ_SLL;
`FUNCT_SLT : id_signal_forwarding <= `HAZ_SLT;
`FUNCT_SLTU : id_signal_forwarding <= `HAZ_SLTU;
`FUNCT_SRL : id_signal_forwarding <= `HAZ_SRL;
`FUNCT_SUB : id_signal_forwarding <= `HAZ_SUB;
`FUNCT_SUBU : id_signal_forwarding <= `HAZ_SUBU;
`FUNCT_XOR : id_signal_forwarding <= `HAZ_XOR;
default : id_signal_forwarding <= 8'hxx;
endcase
end
`OPCODE_TYPE_R_EX : begin
case (id_funct)
`FUNCT_MUL : id_signal_forwarding <= `HAZ_MUL;
default : id_signal_forwarding <= 8'hxx;
endcase
end
`OPCODE_ADDI : id_signal_forwarding <= `HAZ_ADDI;
`OPCODE_ADDIU : id_signal_forwarding <= `HAZ_ADDIU;
`OPCODE_SLTI : id_signal_forwarding <= `HAZ_SLTI;
`OPCODE_SLTIU : id_signal_forwarding <= `HAZ_SLTIU;
`OPCODE_J : id_signal_forwarding <= `HAZ_J;
`OPCODE_JAL : id_signal_forwarding <= `HAZ_JAL;
`OPCODE_BEQ : id_signal_forwarding <= `HAZ_BEQ;
`OPCODE_BNE : id_signal_forwarding <= `HAZ_BNE;
`OPCODE_LW : id_signal_forwarding <= `HAZ_LW;
`OPCODE_SW : id_signal_forwarding <= `HAZ_SW;
default : id_signal_forwarding <= 8'hxx;
endcase
end
always @ ( * ) begin
if (id_stall) begin
id_alu_op <= `ALUOP_ADDU;
end
else begin
case (id_opcode)
`OPCODE_TYPE_R : begin
case (id_funct)
`FUNCT_ADD : id_alu_op <= `ALUOP_ADD;
`FUNCT_ADDU : id_alu_op <= `ALUOP_ADDU;
`FUNCT_AND : id_alu_op <= `ALUOP_AND;
`FUNCT_NOR : id_alu_op <= `ALUOP_NOR;
`FUNCT_OR : id_alu_op <= `ALUOP_OR;
`FUNCT_SLL : id_alu_op <= `ALUOP_SLL;
`FUNCT_SLT : id_alu_op <= `ALUOP_SLT;
`FUNCT_SLTU : id_alu_op <= `ALUOP_SLTU;
`FUNCT_SRL : id_alu_op <= `ALUOP_SRL;
`FUNCT_SUB : id_alu_op <= `ALUOP_SUB;
`FUNCT_SUBU : id_alu_op <= `ALUOP_SUBU;
`FUNCT_XOR : id_alu_op <= `ALUOP_XOR;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
`OPCODE_TYPE_R_EX : begin
case (id_funct)
`FUNCT_MUL : id_alu_op <= `ALUOP_MUL;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
`OPCODE_ADDI : id_alu_op <= `ALUOP_ADD;
`OPCODE_ADDIU : id_alu_op <= `ALUOP_ADDU;
`OPCODE_JAL : id_alu_op <= `ALUOP_ADDU;
`OPCODE_LW : id_alu_op <= `ALUOP_ADDU;
`OPCODE_SLTI : id_alu_op <= `ALUOP_SLT;
`OPCODE_SLTIU : id_alu_op <= `ALUOP_SLTU;
`OPCODE_SW : id_alu_op <= `ALUOP_ADDU;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
end
assign branch_eq = id_opcode[2] & ~id_opcode[1] & ~id_opcode[0] & id_cmp_eq;
assign branch_ne = id_opcode[2] & ~id_opcode[1] & id_opcode[0] & ~id_cmp_eq;
assign branch = (branch_eq | branch_ne);
assign id_pc_source_sel[1] = (signals[8] & ~signals[7]) ? branch : signals[8];
assign if_flush = 0;
assign id_branch_delay_slot = (branch & signals[8]) | (signals[7]);
assign id_sign_extend = (id_opcode[5:2] != 4'b0011);
endmodule | module ControlUnity (
input id_stall,
input [5:0] id_opcode,
input [5:0] id_funct,
input id_cmp_eq,
output if_flush,
output reg [7:0] id_signal_forwarding,
output [1:0] id_pc_source_sel,
output id_sign_extend,
output id_jump_link,
output id_reg_dst,
output id_alu_src,
output id_branch_delay_slot,
output reg [4:0] id_alu_op,
output id_mem_write,
output id_mem_read,
output id_mem_to_reg,
output id_reg_write
); |
wire branch, branch_eq, branch_ne;
reg [8:0] signals;
assign id_pc_source_sel[0] = signals[7];
assign id_jump_link = signals[6];
assign id_alu_src = signals[5];
assign id_reg_dst = signals[4];
assign id_mem_read = signals[3];
assign id_mem_write = signals[2];
assign id_mem_to_reg = signals[1];
assign id_reg_write = signals[0];
always @ ( * ) begin
if (id_stall) begin
signals <= `SIG_NOP;
end
else begin
case (id_opcode)
`OPCODE_TYPE_R: begin
case (id_funct)
`FUNCT_ADD : begin
signals <= `SIG_ADD;
end
`FUNCT_ADDU : begin
signals <= `SIG_ADDU;
end
`FUNCT_AND : begin
signals <= `SIG_AND;
end
`FUNCT_JR : begin
signals <= `SIG_JR;
end
`FUNCT_NOR : begin
signals <= `SIG_NOR;
end
`FUNCT_OR : begin
signals <= `SIG_OR;
end
`FUNCT_SLL : begin
signals <= `SIG_SLL;
end
`FUNCT_SLT : begin
signals <= `SIG_SLT;
end
`FUNCT_SRL : begin
signals <= `SIG_SRL;
end
`FUNCT_SUB : begin
signals <= `SIG_SUB;
end
`FUNCT_SUBU : begin
signals <= `SIG_SUBU;
end
`FUNCT_XOR : begin
signals <= `SIG_XOR;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
`OPCODE_TYPE_R_EX: begin
case (id_funct)
`FUNCT_MUL : begin
signals <= `SIG_MUL;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
`OPCODE_ADDI : begin
signals <= `SIG_ADDI;
end
`OPCODE_ADDIU : begin
signals <= `SIG_ADDIU;
end
`OPCODE_SLTI : begin
signals <= `SIG_SLTI;
end
`OPCODE_J : begin
signals <= `SIG_J;
end
`OPCODE_JAL : begin
signals <= `SIG_JAL;
end
`OPCODE_BEQ : begin
signals <= `SIG_BEQ;
end
`OPCODE_BNE : begin
signals <= `SIG_BNE;
end
`OPCODE_LW : begin
signals <= `SIG_LW;
end
`OPCODE_SW : begin
signals <= `SIG_SW;
end
default : begin
signals <= `SIG_NOP;
end
endcase
end
end
always @ ( * ) begin
case (id_opcode)
`OPCODE_TYPE_R : begin
case (id_funct)
`FUNCT_ADD : id_signal_forwarding <= `HAZ_ADD;
`FUNCT_ADDU : id_signal_forwarding <= `HAZ_ADDU;
`FUNCT_AND : id_signal_forwarding <= `HAZ_AND;
`FUNCT_JR : id_signal_forwarding <= `HAZ_JR;
`FUNCT_NOR : id_signal_forwarding <= `HAZ_NOR;
`FUNCT_OR : id_signal_forwarding <= `HAZ_OR;
`FUNCT_SLL : id_signal_forwarding <= `HAZ_SLL;
`FUNCT_SLT : id_signal_forwarding <= `HAZ_SLT;
`FUNCT_SLTU : id_signal_forwarding <= `HAZ_SLTU;
`FUNCT_SRL : id_signal_forwarding <= `HAZ_SRL;
`FUNCT_SUB : id_signal_forwarding <= `HAZ_SUB;
`FUNCT_SUBU : id_signal_forwarding <= `HAZ_SUBU;
`FUNCT_XOR : id_signal_forwarding <= `HAZ_XOR;
default : id_signal_forwarding <= 8'hxx;
endcase
end
`OPCODE_TYPE_R_EX : begin
case (id_funct)
`FUNCT_MUL : id_signal_forwarding <= `HAZ_MUL;
default : id_signal_forwarding <= 8'hxx;
endcase
end
`OPCODE_ADDI : id_signal_forwarding <= `HAZ_ADDI;
`OPCODE_ADDIU : id_signal_forwarding <= `HAZ_ADDIU;
`OPCODE_SLTI : id_signal_forwarding <= `HAZ_SLTI;
`OPCODE_SLTIU : id_signal_forwarding <= `HAZ_SLTIU;
`OPCODE_J : id_signal_forwarding <= `HAZ_J;
`OPCODE_JAL : id_signal_forwarding <= `HAZ_JAL;
`OPCODE_BEQ : id_signal_forwarding <= `HAZ_BEQ;
`OPCODE_BNE : id_signal_forwarding <= `HAZ_BNE;
`OPCODE_LW : id_signal_forwarding <= `HAZ_LW;
`OPCODE_SW : id_signal_forwarding <= `HAZ_SW;
default : id_signal_forwarding <= 8'hxx;
endcase
end
always @ ( * ) begin
if (id_stall) begin
id_alu_op <= `ALUOP_ADDU;
end
else begin
case (id_opcode)
`OPCODE_TYPE_R : begin
case (id_funct)
`FUNCT_ADD : id_alu_op <= `ALUOP_ADD;
`FUNCT_ADDU : id_alu_op <= `ALUOP_ADDU;
`FUNCT_AND : id_alu_op <= `ALUOP_AND;
`FUNCT_NOR : id_alu_op <= `ALUOP_NOR;
`FUNCT_OR : id_alu_op <= `ALUOP_OR;
`FUNCT_SLL : id_alu_op <= `ALUOP_SLL;
`FUNCT_SLT : id_alu_op <= `ALUOP_SLT;
`FUNCT_SLTU : id_alu_op <= `ALUOP_SLTU;
`FUNCT_SRL : id_alu_op <= `ALUOP_SRL;
`FUNCT_SUB : id_alu_op <= `ALUOP_SUB;
`FUNCT_SUBU : id_alu_op <= `ALUOP_SUBU;
`FUNCT_XOR : id_alu_op <= `ALUOP_XOR;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
`OPCODE_TYPE_R_EX : begin
case (id_funct)
`FUNCT_MUL : id_alu_op <= `ALUOP_MUL;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
`OPCODE_ADDI : id_alu_op <= `ALUOP_ADD;
`OPCODE_ADDIU : id_alu_op <= `ALUOP_ADDU;
`OPCODE_JAL : id_alu_op <= `ALUOP_ADDU;
`OPCODE_LW : id_alu_op <= `ALUOP_ADDU;
`OPCODE_SLTI : id_alu_op <= `ALUOP_SLT;
`OPCODE_SLTIU : id_alu_op <= `ALUOP_SLTU;
`OPCODE_SW : id_alu_op <= `ALUOP_ADDU;
default : id_alu_op <= `ALUOP_ADDU;
endcase
end
end
assign branch_eq = id_opcode[2] & ~id_opcode[1] & ~id_opcode[0] & id_cmp_eq;
assign branch_ne = id_opcode[2] & ~id_opcode[1] & id_opcode[0] & ~id_cmp_eq;
assign branch = (branch_eq | branch_ne);
assign id_pc_source_sel[1] = (signals[8] & ~signals[7]) ? branch : signals[8];
assign if_flush = 0;
assign id_branch_delay_slot = (branch & signals[8]) | (signals[7]);
assign id_sign_extend = (id_opcode[5:2] != 4'b0011);
endmodule | 0 |
2,730 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v | 100,975,158 | DataMemoryInterface.v | v | 39 | 80 | [] | [] | [] | [(3, 38)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v:30: Bit extraction of array[255:0] requires 8 bit index, not 7 bits.\n : ... In instance DataMemoryInterface\n memory[address[8:2]] <= data_write; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/Processor/DataMemoryInterface.v:36: Bit extraction of array[255:0] requires 8 bit index, not 7 bits.\n : ... In instance DataMemoryInterface\n assign read_data = (mem_read) ? memory[address[8:2]] : 32\'hxxxxxxxx;\n ^\n%Error: Exiting due to 2 warning(s)\n' | 164 | module | module DataMemoryInterface (
input clock,
input reset,
input [31:0] address,
input mem_write,
input [31:0] data_write,
input mem_read,
output [31:0] read_data
);
reg [31:0] memory [0:255];
integer i;
initial begin
for (i = 0; i < 256; i = i + 1) begin
memory[i] = 0;
end
end
always @ (posedge clock) begin
if (reset) begin
for (i = 0; i < 256; i = i + 1) begin
memory[i] = 0;
end
end
else begin
if (mem_write) begin
memory[address[8:2]] <= data_write;
end
end
end
assign read_data = (mem_read) ? memory[address[8:2]] : 32'hxxxxxxxx;
endmodule | module DataMemoryInterface (
input clock,
input reset,
input [31:0] address,
input mem_write,
input [31:0] data_write,
input mem_read,
output [31:0] read_data
); |
reg [31:0] memory [0:255];
integer i;
initial begin
for (i = 0; i < 256; i = i + 1) begin
memory[i] = 0;
end
end
always @ (posedge clock) begin
if (reset) begin
for (i = 0; i < 256; i = i + 1) begin
memory[i] = 0;
end
end
else begin
if (mem_write) begin
memory[address[8:2]] <= data_write;
end
end
end
assign read_data = (mem_read) ? memory[address[8:2]] : 32'hxxxxxxxx;
endmodule | 0 |
2,731 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Execute_Memory_Pipeline.v | 100,975,158 | Execute_Memory_Pipeline.v | v | 38 | 114 | [] | [] | [] | [(3, 37)] | null | data/verilator_xmls/7186903d-f6d9-4d21-8abd-99313aa9a007.xml | null | 165 | module | module Execute_Memory_Pipeline (
input clock,
input reset,
input ex_stall,
input ex_mem_read,
input ex_mem_write,
input ex_mem_to_reg,
input ex_reg_write,
input [31:0] ex_alu_result,
input [31:0] ex_reg2_fwd,
input [4:0] ex_rt_rd,
output reg me_mem_read,
output reg me_mem_write,
output reg me_mem_to_reg,
output reg me_reg_write,
output reg [31:0] me_alu_result,
output reg [31:0] me_data2_reg,
output reg [4:0] me_rt_rd
);
wire me_stall = 0;
always @ (posedge clock) begin
me_mem_read <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_read : ( (ex_stall) ? 1'b0 : ex_mem_read));
me_mem_write <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_write : ( (ex_stall) ? 1'b0 : ex_mem_write));
me_mem_to_reg <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_to_reg : ex_mem_to_reg);
me_reg_write <= (reset) ? 1'b0 : ( (me_stall) ? me_reg_write : ( (ex_stall) ? 1'b0 : ex_reg_write));
me_alu_result <= (reset) ? 32'b0 : ( (me_stall) ? me_alu_result : ex_alu_result);
me_data2_reg <= (reset) ? 32'b0 : ( (me_stall) ? me_data2_reg : ex_reg2_fwd);
me_rt_rd <= (reset) ? 5'b0 : ( (me_stall) ? me_rt_rd : ex_rt_rd);
end
endmodule | module Execute_Memory_Pipeline (
input clock,
input reset,
input ex_stall,
input ex_mem_read,
input ex_mem_write,
input ex_mem_to_reg,
input ex_reg_write,
input [31:0] ex_alu_result,
input [31:0] ex_reg2_fwd,
input [4:0] ex_rt_rd,
output reg me_mem_read,
output reg me_mem_write,
output reg me_mem_to_reg,
output reg me_reg_write,
output reg [31:0] me_alu_result,
output reg [31:0] me_data2_reg,
output reg [4:0] me_rt_rd
); |
wire me_stall = 0;
always @ (posedge clock) begin
me_mem_read <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_read : ( (ex_stall) ? 1'b0 : ex_mem_read));
me_mem_write <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_write : ( (ex_stall) ? 1'b0 : ex_mem_write));
me_mem_to_reg <= (reset) ? 1'b0 : ( (me_stall) ? me_mem_to_reg : ex_mem_to_reg);
me_reg_write <= (reset) ? 1'b0 : ( (me_stall) ? me_reg_write : ( (ex_stall) ? 1'b0 : ex_reg_write));
me_alu_result <= (reset) ? 32'b0 : ( (me_stall) ? me_alu_result : ex_alu_result);
me_data2_reg <= (reset) ? 32'b0 : ( (me_stall) ? me_data2_reg : ex_reg2_fwd);
me_rt_rd <= (reset) ? 5'b0 : ( (me_stall) ? me_rt_rd : ex_rt_rd);
end
endmodule | 0 |
2,732 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/InstructionMemoryInterface.v | 100,975,158 | InstructionMemoryInterface.v | v | 20 | 128 | [] | [] | [] | [(3, 19)] | null | data/verilator_xmls/c24fb998-fe95-41ec-a676-8549cd19a511.xml | null | 167 | module | module InstructionMemoryInterface #(parameter INSTRUCTION_FILE = "file.txt") (
input if_stall,
input [31:0] if_pc_usable,
output [31:0] if_instruction
);
reg [31:0] memory [0:63];
initial begin
$readmemb(INSTRUCTION_FILE, memory);
end
assign if_instruction = (if_stall) ? 32'b0 : memory[if_pc_usable[7:2]][31:0];
endmodule | module InstructionMemoryInterface #(parameter INSTRUCTION_FILE = "file.txt") (
input if_stall,
input [31:0] if_pc_usable,
output [31:0] if_instruction
); |
reg [31:0] memory [0:63];
initial begin
$readmemb(INSTRUCTION_FILE, memory);
end
assign if_instruction = (if_stall) ? 32'b0 : memory[if_pc_usable[7:2]][31:0];
endmodule | 0 |
2,733 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Instruction_Decode_Execute_Pipeline.v | 100,975,158 | Instruction_Decode_Execute_Pipeline.v | v | 87 | 156 | [] | [] | [] | [(3, 86)] | null | data/verilator_xmls/41952631-cbef-40c1-ac34-46ea65665226.xml | null | 168 | module | module Instruction_Decode_Execute_Pipeline (
input clock,
input reset,
input id_stall,
input ex_stall,
input id_jump_link,
input id_reg_dst,
input id_alu_src,
input [4:0] id_alu_op,
input id_mem_read,
input id_mem_write,
input id_mem_to_reg,
input id_reg_write,
input [4:0] id_rs,
input [4:0] id_rt,
input id_w_rs_ex,
input id_n_rs_ex,
input id_w_rt_ex,
input id_n_rt_ex,
input [31:0] id_reg1_end,
input [31:0] id_reg2_end,
input [31:0] id_pc,
input [16:0] id_sign_extended_immediate,
output reg ex_jump_link,
output [1:0] ex_jump_link_reg_dst,
output reg ex_alu_src,
output reg [4:0] ex_alu_op,
output reg ex_mem_read,
output reg ex_mem_write,
output reg ex_mem_to_reg,
output reg ex_reg_write,
output reg [4:0] ex_rs,
output reg [4:0] ex_rt,
output reg ex_w_rs_ex,
output reg ex_n_rs_ex,
output reg ex_w_rt_ex,
output reg ex_n_rt_ex,
output reg [31:0] ex_reg1_data,
output reg [31:0] ex_reg2_data,
output reg [31:0] ex_pc,
output [31:0] ex_sign_extended_immediate,
output [4:0] ex_rd,
output [4:0] ex_shamt
);
reg [16:0] ex_sign_ex_imm_creator;
reg ex_reg_dst;
assign ex_jump_link_reg_dst = (ex_jump_link) ? 2'b10 : ( (ex_reg_dst) ? 2'b01 : 2'b00 );
assign ex_rd = ex_sign_extended_immediate[15:11];
assign ex_shamt = ex_sign_extended_immediate[10:6];
assign ex_sign_extended_immediate = (ex_sign_ex_imm_creator[16]) ? {15'h7fff, ex_sign_ex_imm_creator[16:0]} : {15'h0000, ex_sign_ex_imm_creator[16:0]};
always @ (posedge clock) begin
ex_jump_link <= (reset) ? 1'b0 : ( (ex_stall) ? ex_jump_link : id_jump_link );
ex_reg_dst <= (reset) ? 1'b0 : ( (ex_stall) ? ex_reg_dst : id_reg_dst);
ex_alu_src <= (reset) ? 1'b0 : ( (ex_stall) ? ex_alu_src : id_alu_src);
ex_alu_op <= (reset) ? 5'b0 : ( (ex_stall) ? ex_alu_op : ( (id_stall) ? 5'b0 : id_alu_op));
ex_mem_read <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_read : ( (id_stall) ? 1'b0 : id_mem_read));
ex_mem_write <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_write : ( (id_stall) ? 1'b0 : id_mem_write));
ex_mem_to_reg <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_to_reg : id_mem_to_reg);
ex_reg_write <= (reset) ? 1'b0 : ( (ex_stall) ? ex_reg_write : ( (id_stall) ? 1'b0 : id_reg_write));
ex_reg1_data <= (reset) ? 32'b0 : ( (ex_stall) ? ex_reg1_data : id_reg1_end);
ex_reg2_data <= (reset) ? 32'b0 : ( (ex_stall) ? ex_reg2_data : id_reg2_end);
ex_pc <= (reset) ? 32'b0 : ( (ex_stall) ? ex_pc : id_pc);
ex_sign_ex_imm_creator <= (reset) ? 17'b0 : ( (ex_stall) ? ex_sign_ex_imm_creator : id_sign_extended_immediate);
ex_rs <= (reset) ? 5'b0 : ( (ex_stall) ? ex_rs : id_rs);
ex_rt <= (reset) ? 5'b0 : ( (ex_stall) ? ex_rt : id_rt);
ex_w_rs_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_w_rs_ex : ( (id_stall) ? 1'b0 : id_w_rs_ex));
ex_n_rs_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_n_rs_ex : ( (id_stall) ? 1'b0 : id_n_rs_ex));
ex_w_rt_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_w_rt_ex : ( (id_stall) ? 1'b0 : id_w_rt_ex));
ex_n_rt_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_n_rt_ex : ( (id_stall) ? 1'b0 : id_n_rt_ex));
end
endmodule | module Instruction_Decode_Execute_Pipeline (
input clock,
input reset,
input id_stall,
input ex_stall,
input id_jump_link,
input id_reg_dst,
input id_alu_src,
input [4:0] id_alu_op,
input id_mem_read,
input id_mem_write,
input id_mem_to_reg,
input id_reg_write,
input [4:0] id_rs,
input [4:0] id_rt,
input id_w_rs_ex,
input id_n_rs_ex,
input id_w_rt_ex,
input id_n_rt_ex,
input [31:0] id_reg1_end,
input [31:0] id_reg2_end,
input [31:0] id_pc,
input [16:0] id_sign_extended_immediate,
output reg ex_jump_link,
output [1:0] ex_jump_link_reg_dst,
output reg ex_alu_src,
output reg [4:0] ex_alu_op,
output reg ex_mem_read,
output reg ex_mem_write,
output reg ex_mem_to_reg,
output reg ex_reg_write,
output reg [4:0] ex_rs,
output reg [4:0] ex_rt,
output reg ex_w_rs_ex,
output reg ex_n_rs_ex,
output reg ex_w_rt_ex,
output reg ex_n_rt_ex,
output reg [31:0] ex_reg1_data,
output reg [31:0] ex_reg2_data,
output reg [31:0] ex_pc,
output [31:0] ex_sign_extended_immediate,
output [4:0] ex_rd,
output [4:0] ex_shamt
); |
reg [16:0] ex_sign_ex_imm_creator;
reg ex_reg_dst;
assign ex_jump_link_reg_dst = (ex_jump_link) ? 2'b10 : ( (ex_reg_dst) ? 2'b01 : 2'b00 );
assign ex_rd = ex_sign_extended_immediate[15:11];
assign ex_shamt = ex_sign_extended_immediate[10:6];
assign ex_sign_extended_immediate = (ex_sign_ex_imm_creator[16]) ? {15'h7fff, ex_sign_ex_imm_creator[16:0]} : {15'h0000, ex_sign_ex_imm_creator[16:0]};
always @ (posedge clock) begin
ex_jump_link <= (reset) ? 1'b0 : ( (ex_stall) ? ex_jump_link : id_jump_link );
ex_reg_dst <= (reset) ? 1'b0 : ( (ex_stall) ? ex_reg_dst : id_reg_dst);
ex_alu_src <= (reset) ? 1'b0 : ( (ex_stall) ? ex_alu_src : id_alu_src);
ex_alu_op <= (reset) ? 5'b0 : ( (ex_stall) ? ex_alu_op : ( (id_stall) ? 5'b0 : id_alu_op));
ex_mem_read <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_read : ( (id_stall) ? 1'b0 : id_mem_read));
ex_mem_write <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_write : ( (id_stall) ? 1'b0 : id_mem_write));
ex_mem_to_reg <= (reset) ? 1'b0 : ( (ex_stall) ? ex_mem_to_reg : id_mem_to_reg);
ex_reg_write <= (reset) ? 1'b0 : ( (ex_stall) ? ex_reg_write : ( (id_stall) ? 1'b0 : id_reg_write));
ex_reg1_data <= (reset) ? 32'b0 : ( (ex_stall) ? ex_reg1_data : id_reg1_end);
ex_reg2_data <= (reset) ? 32'b0 : ( (ex_stall) ? ex_reg2_data : id_reg2_end);
ex_pc <= (reset) ? 32'b0 : ( (ex_stall) ? ex_pc : id_pc);
ex_sign_ex_imm_creator <= (reset) ? 17'b0 : ( (ex_stall) ? ex_sign_ex_imm_creator : id_sign_extended_immediate);
ex_rs <= (reset) ? 5'b0 : ( (ex_stall) ? ex_rs : id_rs);
ex_rt <= (reset) ? 5'b0 : ( (ex_stall) ? ex_rt : id_rt);
ex_w_rs_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_w_rs_ex : ( (id_stall) ? 1'b0 : id_w_rs_ex));
ex_n_rs_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_n_rs_ex : ( (id_stall) ? 1'b0 : id_n_rs_ex));
ex_w_rt_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_w_rt_ex : ( (id_stall) ? 1'b0 : id_w_rt_ex));
ex_n_rt_ex <= (reset) ? 1'b0 : ( (ex_stall) ? ex_n_rt_ex : ( (id_stall) ? 1'b0 : id_n_rt_ex));
end
endmodule | 0 |
2,734 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Instruction_Fetch_Decode_Pipeline.v | 100,975,158 | Instruction_Fetch_Decode_Pipeline.v | v | 31 | 145 | [] | [] | [] | [(3, 30)] | null | data/verilator_xmls/b88874b2-98d9-425a-b474-15245d215f9a.xml | null | 169 | module | module Instruction_Fetch_Decode_Pipeline (
input clock,
input reset,
input if_flush,
input if_stall,
input id_stall,
input if_bra_delay,
input [31:0] if_instruction,
input [31:0] if_pc_add_4,
input [31:0] if_pc_usable,
output reg [31:0] id_instruction,
output reg [31:0] id_pc_add_4,
output reg [31:0] id_pc
);
always @ (posedge clock) begin
id_instruction <= (reset) ? 32'b0 : ( (id_stall) ? id_instruction : ( (if_stall | if_flush | if_bra_delay) ? 32'b0 : if_instruction ) );
id_pc_add_4 <= (reset) ? 32'b0 : ( (id_stall) ? id_pc_add_4 : if_pc_add_4);
id_pc <= (reset) ? 32'b0 : ( (id_stall | if_bra_delay) ? id_pc : if_pc_usable);
end
endmodule | module Instruction_Fetch_Decode_Pipeline (
input clock,
input reset,
input if_flush,
input if_stall,
input id_stall,
input if_bra_delay,
input [31:0] if_instruction,
input [31:0] if_pc_add_4,
input [31:0] if_pc_usable,
output reg [31:0] id_instruction,
output reg [31:0] id_pc_add_4,
output reg [31:0] id_pc
); |
always @ (posedge clock) begin
id_instruction <= (reset) ? 32'b0 : ( (id_stall) ? id_instruction : ( (if_stall | if_flush | if_bra_delay) ? 32'b0 : if_instruction ) );
id_pc_add_4 <= (reset) ? 32'b0 : ( (id_stall) ? id_pc_add_4 : if_pc_add_4);
id_pc <= (reset) ? 32'b0 : ( (id_stall | if_bra_delay) ? id_pc : if_pc_usable);
end
endmodule | 0 |
2,735 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Memory_WriteBack_Pipeline.v | 100,975,158 | Memory_WriteBack_Pipeline.v | v | 32 | 113 | [] | [] | [] | [(3, 31)] | null | data/verilator_xmls/98d36336-d034-4d7f-905a-3e71e4165281.xml | null | 171 | module | module Memory_WriteBack_Pipeline (
input clock,
input reset,
input me_reg_write,
input me_mem_to_reg,
input [31:0] me_mem_read_data,
input [31:0] me_alu_result,
input [4:0] me_rt_rd,
output reg wb_reg_write,
output reg wb_mem_to_reg,
output reg [31:0] wb_data_memory,
output reg [31:0] wb_alu_result,
output reg [4:0] wb_rt_rd
);
wire me_stall = 0;
wire wb_stall = 0;
always @ (posedge clock) begin
wb_reg_write <= (reset) ? 1'b0 : ( (wb_stall) ? wb_reg_write : ((me_stall) ? 1'b0 : me_reg_write));
wb_mem_to_reg <= (reset) ? 1'b0 : ( (wb_stall) ? wb_mem_to_reg : me_mem_to_reg);
wb_data_memory <= (reset) ? 32'b0 : ( (wb_stall) ? wb_data_memory : me_mem_read_data);
wb_alu_result <= (reset) ? 32'b0 : ( (wb_stall) ? wb_alu_result : me_alu_result);
wb_rt_rd <= (reset) ? 5'b0 : ( (wb_stall) ? wb_rt_rd : me_rt_rd);
end
endmodule | module Memory_WriteBack_Pipeline (
input clock,
input reset,
input me_reg_write,
input me_mem_to_reg,
input [31:0] me_mem_read_data,
input [31:0] me_alu_result,
input [4:0] me_rt_rd,
output reg wb_reg_write,
output reg wb_mem_to_reg,
output reg [31:0] wb_data_memory,
output reg [31:0] wb_alu_result,
output reg [4:0] wb_rt_rd
); |
wire me_stall = 0;
wire wb_stall = 0;
always @ (posedge clock) begin
wb_reg_write <= (reset) ? 1'b0 : ( (wb_stall) ? wb_reg_write : ((me_stall) ? 1'b0 : me_reg_write));
wb_mem_to_reg <= (reset) ? 1'b0 : ( (wb_stall) ? wb_mem_to_reg : me_mem_to_reg);
wb_data_memory <= (reset) ? 32'b0 : ( (wb_stall) ? wb_data_memory : me_mem_read_data);
wb_alu_result <= (reset) ? 32'b0 : ( (wb_stall) ? wb_alu_result : me_alu_result);
wb_rt_rd <= (reset) ? 5'b0 : ( (wb_stall) ? wb_rt_rd : me_rt_rd);
end
endmodule | 0 |
2,736 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/PC_Latch.v | 100,975,158 | PC_Latch.v | v | 22 | 81 | [] | [] | [] | [(4, 21)] | null | data/verilator_xmls/349bdb90-bc3d-4f7f-a488-a544768b0f5f.xml | null | 173 | module | module PC_Latch (
input clock,
input reset,
input enable,
input [31:0] data,
output reg [31:0] value
);
initial begin
value = 32'd0;
end
always @ (posedge clock) begin
value <= (reset) ? 32'd0 : ((enable) ? data : value);
end
endmodule | module PC_Latch (
input clock,
input reset,
input enable,
input [31:0] data,
output reg [31:0] value
); |
initial begin
value = 32'd0;
end
always @ (posedge clock) begin
value <= (reset) ? 32'd0 : ((enable) ? data : value);
end
endmodule | 0 |
2,737 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/Processor.v | 100,975,158 | Processor.v | v | 540 | 199 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/Processor.v:3: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: Exiting due to 1 error(s)\n' | 174 | module | module Processor (
input clock,
input reset,
output d_test_valid,
output reg me_memory_write_out,
output reg me_memory_read_out,
output reg [31:0] me_memory_data_write_out,
output reg [31:0] me_memory_address_out,
input [31:0] me_memory_data_read_in
);
parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";
wire if_stall;
wire if_flush;
wire [31:0] if_pc;
wire [31:0] if_pc_out;
wire [31:0] if_pc_usable;
wire [31:0] if_pc_add_4;
wire [31:0] if_instruction;
wire if_bra_delay;
wire id_stall;
wire id_reg_dst;
wire id_alu_src;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
wire id_cmp_eq;
wire id_sign_extend;
wire id_jump_link;
wire [4:0] id_alu_op;
wire id_branch_delay_slot;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire id_w_rs_ex;
wire id_n_rs_ex;
wire id_w_rt_ex;
wire id_n_rt_ex;
wire [1:0] id_pc_source_sel;
wire [31:0] id_instruction;
wire [4:0] id_rs = id_instruction[25:21];
wire [4:0] id_rt = id_instruction[20:16];
wire [5:0] id_opcode = id_instruction[31:26];
wire [5:0] id_funct = id_instruction[5:0];
wire [31:0] id_reg1_data;
wire [31:0] id_reg1_end;
wire [31:0] id_reg2_data;
wire [31:0] id_reg2_end;
wire [31:0] id_immediate = id_instruction[15:0];
wire [31:0] id_pc_add_4;
wire [31:0] id_pc;
wire [31:0] id_jump_address = id_instruction[25:0];
wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
wire [31:0] id_branch_address;
wire ex_stall;
wire ex_mem_read;
wire ex_mem_write;
wire ex_mem_to_reg;
wire ex_reg_write;
wire ex_alu_src;
wire ex_jump_link;
wire [1:0] ex_jump_link_reg_dst;
wire [4:0] ex_alu_op;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire ex_w_rs_ex;
wire ex_n_rs_ex;
wire ex_w_rt_ex;
wire ex_n_rt_ex;
wire [4:0] ex_rs;
wire [4:0] ex_rt;
wire [4:0] ex_rd;
wire [4:0] ex_rt_rd;
wire [4:0] ex_shamt;
wire [31:0] ex_reg1_data;
wire [31:0] ex_reg1_fwd;
wire [31:0] ex_reg2_data;
wire [31:0] ex_reg2_fwd;
wire [31:0] ex_data2_imm;
wire [31:0] ex_sign_extended_immediate;
wire [31:0] ex_alu_result;
wire [31:0] ex_pc;
wire ex_alu_overflow;
wire me_mem_read;
wire me_mem_write;
wire me_mem_to_reg;
wire me_reg_write;
wire me_write_data_fwd_sel;
wire [4:0] me_rt_rd;
wire [31:0] me_alu_result;
wire [31:0] me_data2_reg;
wire [31:0] me_pc;
wire [31:0] me_mem_read_data;
wire [31:0] me_mem_write_data;
wire wb_mem_to_reg;
wire wb_reg_write;
wire [4:0] wb_rt_rd;
wire [31:0] wb_data_memory;
wire [31:0] wb_alu_result;
wire [31:0] wb_write_data;
wire [7:0] id_signal_forwarding;
wire [7:0] final_signal_forwarding;
assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};
assign if_bra_delay = id_branch_delay_slot;
always @ ( * ) begin
me_memory_address_out <= me_alu_result;
me_memory_write_out <= me_mem_write;
me_memory_read_out <= me_mem_read;
me_memory_data_write_out <= me_mem_write_data;
end
assign me_mem_read_data = me_memory_data_read_in;
Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
.sel (id_pc_source_sel),
.in0 (if_pc_add_4),
.in1 (id_jump_address_usable),
.in2 (id_branch_address),
.in3 (id_reg1_end),
.out (if_pc_out)
);
PC_Latch PC (
.clock (clock),
.reset (reset),
.enable (~(if_stall | id_stall)),
.data (if_pc_out),
.value (if_pc_usable)
);
InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
.if_stall (if_stall),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction)
);
SimpleAdder PC_Increment (
.A (if_pc_usable),
.B (32'h00000004),
.C (if_pc_add_4)
);
Instruction_Fetch_Decode_Pipeline IF_ID (
.clock (clock),
.reset (reset),
.if_flush (if_flush),
.if_stall (if_stall),
.id_stall (id_stall),
.if_bra_delay (if_bra_delay),
.if_pc_add_4 (if_pc_add_4),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction),
.id_pc_add_4 (id_pc_add_4),
.id_instruction (id_instruction),
.id_pc (id_pc)
);
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (id_rs),
.read_reg2 (id_rt),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.wb_reg_write (wb_reg_write),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
.sel (id_fwd_rs_sel),
.in0 (id_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg1_end)
);
Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
.sel (id_fwd_rt_sel),
.in0 (id_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg2_end)
);
Comparator Branch_Antecipation (
.A (id_reg1_end),
.B (id_reg2_end),
.Equals (id_cmp_eq)
);
SimpleAdder Branch_Address_Calculation (
.A (id_pc_add_4),
.B (id_immediate_left_shifted2),
.C (id_branch_address)
);
ControlUnity Control (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (final_signal_forwarding),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
Instruction_Decode_Execute_Pipeline ID_EX (
.clock (clock),
.reset (reset),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_rs (id_rs),
.id_rt (id_rt),
.id_w_rs_ex (id_signal_forwarding[3]),
.id_n_rs_ex (id_signal_forwarding[2]),
.id_w_rt_ex (id_signal_forwarding[1]),
.id_n_rt_ex (id_signal_forwarding[0]),
.id_reg1_end (id_reg1_end),
.id_reg2_end (id_reg2_end),
.id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
.id_pc (id_pc),
.ex_jump_link (ex_jump_link),
.ex_jump_link_reg_dst (ex_jump_link_reg_dst),
.ex_alu_src (ex_alu_src),
.ex_alu_op (ex_alu_op),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_w_rs_ex (ex_w_rs_ex),
.ex_n_rs_ex (ex_n_rs_ex),
.ex_w_rt_ex (ex_w_rt_ex),
.ex_n_rt_ex (ex_n_rt_ex),
.ex_reg1_data (ex_reg1_data),
.ex_reg2_data (ex_reg2_data),
.ex_sign_extended_immediate (ex_sign_extended_immediate),
.ex_rd (ex_rd),
.ex_shamt (ex_shamt),
.ex_pc (ex_pc)
);
Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
.sel (ex_fwd_rs_sel),
.in0 (ex_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (ex_pc),
.out (ex_reg1_fwd)
);
Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
.sel (ex_fwd_rt_sel),
.in0 (ex_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'h00000004),
.out (ex_reg2_fwd)
);
assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;
Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
.sel (ex_jump_link_reg_dst),
.in0 (ex_rt),
.in1 (ex_rd),
.in2 (5'b11111),
.in3 (5'bxxxxx),
.out (ex_rt_rd)
);
ArithmeticLogicUnit ALU (
.A (ex_reg1_fwd),
.B (ex_data2_imm),
.operation (ex_alu_op),
.shamt (ex_shamt),
.result (ex_alu_result),
.overflow (ex_alu_overflow)
);
Execute_Memory_Pipeline EX_MEM (
.clock (clock),
.reset (reset),
.ex_stall (ex_stall),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_alu_result (ex_alu_result),
.ex_reg2_fwd (ex_reg2_fwd),
.ex_rt_rd (ex_rt_rd),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.me_reg_write (me_reg_write),
.me_alu_result (me_alu_result),
.me_data2_reg (me_data2_reg),
.me_rt_rd (me_rt_rd)
);
assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;
assign d_test_valid = (me_alu_result >= 32'd256) ? 1'b1 : 1'b0;
Memory_WriteBack_Pipeline MEM_WB (
.clock (clock),
.reset (reset),
.me_reg_write (me_reg_write),
.me_mem_to_reg (me_mem_to_reg),
.me_mem_read_data (me_mem_read_data),
.me_alu_result (me_alu_result),
.me_rt_rd (me_rt_rd),
.wb_reg_write (wb_reg_write),
.wb_mem_to_reg (wb_mem_to_reg),
.wb_data_memory (wb_data_memory),
.wb_alu_result (wb_alu_result),
.wb_rt_rd (wb_rt_rd)
);
assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule | module Processor (
input clock,
input reset,
output d_test_valid,
output reg me_memory_write_out,
output reg me_memory_read_out,
output reg [31:0] me_memory_data_write_out,
output reg [31:0] me_memory_address_out,
input [31:0] me_memory_data_read_in
); |
parameter INSTRUCTIONS = "C:/Outros/Full Processor/MIPS32_Processor/Final Project/MIPS32_Full/Testing Codes/Exponential.txt";
wire if_stall;
wire if_flush;
wire [31:0] if_pc;
wire [31:0] if_pc_out;
wire [31:0] if_pc_usable;
wire [31:0] if_pc_add_4;
wire [31:0] if_instruction;
wire if_bra_delay;
wire id_stall;
wire id_reg_dst;
wire id_alu_src;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
wire id_cmp_eq;
wire id_sign_extend;
wire id_jump_link;
wire [4:0] id_alu_op;
wire id_branch_delay_slot;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire id_w_rs_ex;
wire id_n_rs_ex;
wire id_w_rt_ex;
wire id_n_rt_ex;
wire [1:0] id_pc_source_sel;
wire [31:0] id_instruction;
wire [4:0] id_rs = id_instruction[25:21];
wire [4:0] id_rt = id_instruction[20:16];
wire [5:0] id_opcode = id_instruction[31:26];
wire [5:0] id_funct = id_instruction[5:0];
wire [31:0] id_reg1_data;
wire [31:0] id_reg1_end;
wire [31:0] id_reg2_data;
wire [31:0] id_reg2_end;
wire [31:0] id_immediate = id_instruction[15:0];
wire [31:0] id_pc_add_4;
wire [31:0] id_pc;
wire [31:0] id_jump_address = id_instruction[25:0];
wire [31:0] id_jump_address_usable = {id_pc_add_4[31:28], id_jump_address[25:0], 2'b00};
wire [31:0] id_sign_extended_immediate = (id_sign_extend & id_immediate[15]) ? {14'h3fff, id_immediate[15:0]} : {14'h0000, id_immediate[15:0]};
wire [31:0] id_immediate_left_shifted2 = {id_sign_extended_immediate[29:0], 2'b00};
wire [31:0] id_branch_address;
wire ex_stall;
wire ex_mem_read;
wire ex_mem_write;
wire ex_mem_to_reg;
wire ex_reg_write;
wire ex_alu_src;
wire ex_jump_link;
wire [1:0] ex_jump_link_reg_dst;
wire [4:0] ex_alu_op;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire ex_w_rs_ex;
wire ex_n_rs_ex;
wire ex_w_rt_ex;
wire ex_n_rt_ex;
wire [4:0] ex_rs;
wire [4:0] ex_rt;
wire [4:0] ex_rd;
wire [4:0] ex_rt_rd;
wire [4:0] ex_shamt;
wire [31:0] ex_reg1_data;
wire [31:0] ex_reg1_fwd;
wire [31:0] ex_reg2_data;
wire [31:0] ex_reg2_fwd;
wire [31:0] ex_data2_imm;
wire [31:0] ex_sign_extended_immediate;
wire [31:0] ex_alu_result;
wire [31:0] ex_pc;
wire ex_alu_overflow;
wire me_mem_read;
wire me_mem_write;
wire me_mem_to_reg;
wire me_reg_write;
wire me_write_data_fwd_sel;
wire [4:0] me_rt_rd;
wire [31:0] me_alu_result;
wire [31:0] me_data2_reg;
wire [31:0] me_pc;
wire [31:0] me_mem_read_data;
wire [31:0] me_mem_write_data;
wire wb_mem_to_reg;
wire wb_reg_write;
wire [4:0] wb_rt_rd;
wire [31:0] wb_data_memory;
wire [31:0] wb_alu_result;
wire [31:0] wb_write_data;
wire [7:0] id_signal_forwarding;
wire [7:0] final_signal_forwarding;
assign final_signal_forwarding = {id_signal_forwarding[7:4], ex_w_rs_ex, ex_n_rs_ex, ex_w_rt_ex, ex_n_rt_ex};
assign if_bra_delay = id_branch_delay_slot;
always @ ( * ) begin
me_memory_address_out <= me_alu_result;
me_memory_write_out <= me_mem_write;
me_memory_read_out <= me_mem_read;
me_memory_data_write_out <= me_mem_write_data;
end
assign me_mem_read_data = me_memory_data_read_in;
Multiplex4 #(.WIDTH(32)) PC_Source_Selection_Mux (
.sel (id_pc_source_sel),
.in0 (if_pc_add_4),
.in1 (id_jump_address_usable),
.in2 (id_branch_address),
.in3 (id_reg1_end),
.out (if_pc_out)
);
PC_Latch PC (
.clock (clock),
.reset (reset),
.enable (~(if_stall | id_stall)),
.data (if_pc_out),
.value (if_pc_usable)
);
InstructionMemoryInterface #(.INSTRUCTION_FILE(INSTRUCTIONS)) instruction_memory (
.if_stall (if_stall),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction)
);
SimpleAdder PC_Increment (
.A (if_pc_usable),
.B (32'h00000004),
.C (if_pc_add_4)
);
Instruction_Fetch_Decode_Pipeline IF_ID (
.clock (clock),
.reset (reset),
.if_flush (if_flush),
.if_stall (if_stall),
.id_stall (id_stall),
.if_bra_delay (if_bra_delay),
.if_pc_add_4 (if_pc_add_4),
.if_pc_usable (if_pc_usable),
.if_instruction (if_instruction),
.id_pc_add_4 (id_pc_add_4),
.id_instruction (id_instruction),
.id_pc (id_pc)
);
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (id_rs),
.read_reg2 (id_rt),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.wb_reg_write (wb_reg_write),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
Multiplex4 #(.WIDTH(32)) ID_RS_Forwarding_Mux (
.sel (id_fwd_rs_sel),
.in0 (id_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg1_end)
);
Multiplex4 #(.WIDTH(32)) ID_RT_Forwarding_Mux (
.sel (id_fwd_rt_sel),
.in0 (id_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'hxxxxxxxx),
.out (id_reg2_end)
);
Comparator Branch_Antecipation (
.A (id_reg1_end),
.B (id_reg2_end),
.Equals (id_cmp_eq)
);
SimpleAdder Branch_Address_Calculation (
.A (id_pc_add_4),
.B (id_immediate_left_shifted2),
.C (id_branch_address)
);
ControlUnity Control (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (final_signal_forwarding),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
Instruction_Decode_Execute_Pipeline ID_EX (
.clock (clock),
.reset (reset),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_rs (id_rs),
.id_rt (id_rt),
.id_w_rs_ex (id_signal_forwarding[3]),
.id_n_rs_ex (id_signal_forwarding[2]),
.id_w_rt_ex (id_signal_forwarding[1]),
.id_n_rt_ex (id_signal_forwarding[0]),
.id_reg1_end (id_reg1_end),
.id_reg2_end (id_reg2_end),
.id_sign_extended_immediate (id_sign_extended_immediate[16:0]),
.id_pc (id_pc),
.ex_jump_link (ex_jump_link),
.ex_jump_link_reg_dst (ex_jump_link_reg_dst),
.ex_alu_src (ex_alu_src),
.ex_alu_op (ex_alu_op),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_w_rs_ex (ex_w_rs_ex),
.ex_n_rs_ex (ex_n_rs_ex),
.ex_w_rt_ex (ex_w_rt_ex),
.ex_n_rt_ex (ex_n_rt_ex),
.ex_reg1_data (ex_reg1_data),
.ex_reg2_data (ex_reg2_data),
.ex_sign_extended_immediate (ex_sign_extended_immediate),
.ex_rd (ex_rd),
.ex_shamt (ex_shamt),
.ex_pc (ex_pc)
);
Multiplex4 #(.WIDTH(32)) EX_RS_Forwarding_Mux (
.sel (ex_fwd_rs_sel),
.in0 (ex_reg1_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (ex_pc),
.out (ex_reg1_fwd)
);
Multiplex4 #(.WIDTH(32)) EX_RT_Forwarding_Mux (
.sel (ex_fwd_rt_sel),
.in0 (ex_reg2_data),
.in1 (me_alu_result),
.in2 (wb_write_data),
.in3 (32'h00000004),
.out (ex_reg2_fwd)
);
assign ex_data2_imm = (ex_alu_src) ? ex_sign_extended_immediate : ex_reg2_fwd;
Multiplex4 #(.WIDTH(5)) EX_Reg_Destination_Mux (
.sel (ex_jump_link_reg_dst),
.in0 (ex_rt),
.in1 (ex_rd),
.in2 (5'b11111),
.in3 (5'bxxxxx),
.out (ex_rt_rd)
);
ArithmeticLogicUnit ALU (
.A (ex_reg1_fwd),
.B (ex_data2_imm),
.operation (ex_alu_op),
.shamt (ex_shamt),
.result (ex_alu_result),
.overflow (ex_alu_overflow)
);
Execute_Memory_Pipeline EX_MEM (
.clock (clock),
.reset (reset),
.ex_stall (ex_stall),
.ex_mem_read (ex_mem_read),
.ex_mem_write (ex_mem_write),
.ex_mem_to_reg (ex_mem_to_reg),
.ex_reg_write (ex_reg_write),
.ex_alu_result (ex_alu_result),
.ex_reg2_fwd (ex_reg2_fwd),
.ex_rt_rd (ex_rt_rd),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.me_reg_write (me_reg_write),
.me_alu_result (me_alu_result),
.me_data2_reg (me_data2_reg),
.me_rt_rd (me_rt_rd)
);
assign me_mem_write_data = (me_write_data_fwd_sel) ? wb_write_data : me_data2_reg;
assign d_test_valid = (me_alu_result >= 32'd256) ? 1'b1 : 1'b0;
Memory_WriteBack_Pipeline MEM_WB (
.clock (clock),
.reset (reset),
.me_reg_write (me_reg_write),
.me_mem_to_reg (me_mem_to_reg),
.me_mem_read_data (me_mem_read_data),
.me_alu_result (me_alu_result),
.me_rt_rd (me_rt_rd),
.wb_reg_write (wb_reg_write),
.wb_mem_to_reg (wb_mem_to_reg),
.wb_data_memory (wb_data_memory),
.wb_alu_result (wb_alu_result),
.wb_rt_rd (wb_rt_rd)
);
assign wb_write_data = (wb_mem_to_reg) ? wb_data_memory : wb_alu_result;
endmodule | 0 |
2,738 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/RegisterFile.v | 100,975,158 | RegisterFile.v | v | 47 | 75 | [] | [] | [] | [(3, 46)] | null | data/verilator_xmls/a95112ee-286f-4d80-b584-76e1a2f22605.xml | null | 175 | module | module RegisterFile (
input clock,
input reset,
input [4:0] read_reg1,
input [4:0] read_reg2,
output [31:0] id_reg1_data,
output [31:0] id_reg2_data,
input wb_reg_write,
input [4:0] wb_rt_rd,
input [31:0] wb_write_data
);
reg [31:0] registers [1:31];
integer i;
initial begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 0;
end
end
always @ (posedge clock) begin
if (reset) begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 0;
end
end
else begin
if (wb_rt_rd != 0 & wb_reg_write) begin
registers[wb_rt_rd] <= wb_write_data;
end
end
end
assign id_reg1_data = (read_reg1 == 0) ? 32'b0 : registers[read_reg1];
assign id_reg2_data = (read_reg2 == 0) ? 32'b0 : registers[read_reg2];
endmodule | module RegisterFile (
input clock,
input reset,
input [4:0] read_reg1,
input [4:0] read_reg2,
output [31:0] id_reg1_data,
output [31:0] id_reg2_data,
input wb_reg_write,
input [4:0] wb_rt_rd,
input [31:0] wb_write_data
); |
reg [31:0] registers [1:31];
integer i;
initial begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 0;
end
end
always @ (posedge clock) begin
if (reset) begin
for (i = 1; i < 32; i = i + 1) begin
registers[i] <= 0;
end
end
else begin
if (wb_rt_rd != 0 & wb_reg_write) begin
registers[wb_rt_rd] <= wb_write_data;
end
end
end
assign id_reg1_data = (read_reg1 == 0) ? 32'b0 : registers[read_reg1];
assign id_reg2_data = (read_reg2 == 0) ? 32'b0 : registers[read_reg2];
endmodule | 0 |
2,739 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/SimpleAdder.v | 100,975,158 | SimpleAdder.v | v | 11 | 24 | [] | [] | [] | [(3, 10)] | null | data/verilator_xmls/262503ec-726d-4acc-a547-4a42eb461ea2.xml | null | 176 | module | module SimpleAdder (
input [31:0] A,
input [31:0] B,
output [31:0] C
);
assign C = (A + B);
endmodule | module SimpleAdder (
input [31:0] A,
input [31:0] B,
output [31:0] C
); |
assign C = (A + B);
endmodule | 0 |
2,740 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v | 100,975,158 | TB_ArithmeticLogicUnit.v | v | 117 | 60 | [] | [] | [] | [(154, 266)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:28: Define or directive not defined: \'`ALUOP_ADD\'\n operation = `ALUOP_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_ADD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:29: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:34: Define or directive not defined: \'`ALUOP_SUB\'\n operation = `ALUOP_SUB;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_SUB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:40: Define or directive not defined: \'`ALUOP_MUL\'\n operation = `ALUOP_MUL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_MUL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:46: Define or directive not defined: \'`ALUOP_SLT\'\n operation = `ALUOP_SLT;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_SLT;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:56: Define or directive not defined: \'`ALUOP_OR\'\n operation = `ALUOP_OR;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_OR;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:55: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:62: Define or directive not defined: \'`ALUOP_AND\'\n operation = `ALUOP_AND;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_AND;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:68: Define or directive not defined: \'`ALUOP_NOR\'\n operation = `ALUOP_NOR;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_NOR;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:73: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:78: Define or directive not defined: \'`ALUOP_ADD\'\n operation = `ALUOP_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_ADD;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:79: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:84: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:90: Define or directive not defined: \'`ALUOP_SUB\'\n operation = `ALUOP_SUB;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_SUB;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:96: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:102: Define or directive not defined: \'`ALUOP_SLL\'\n operation = `ALUOP_SLL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:102: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_SLL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:101: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:108: Define or directive not defined: \'`ALUOP_SRL\'\n operation = `ALUOP_SRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n operation = `ALUOP_SRL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:107: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ArithmeticLogicUnit.v:109: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 23 error(s), 26 warning(s)\n' | 177 | module | module TB_ArithmeticLogicUnit ();
reg [31:0] A;
reg [31:0] B;
reg [4:0] operation;
reg [4:0] shamt;
wire [31:0] result;
wire overflow;
ArithmeticLogicUnit ALU (
.A (A),
.B (B),
.operation (operation),
.shamt (shamt),
.result (result),
.overflow (overflow)
);
initial begin
shamt = 0;
A = 20;
B = 10;
#10
operation = `ALUOP_ADD;
#10
if (result == 32'd30)
$display("Add Passed");
#10
operation = `ALUOP_SUB;
#10
if (result == 32'd10)
$display("Sub Passed");
#10
operation = `ALUOP_MUL;
#10
if (result == 32'd200)
$display("Mul Passed");
#10
operation = `ALUOP_SLT;
#10
if (result == 32'd0)
$display("Slower Than Passed");
#10
A = 5'b01010;
B = 5'b10010;
#10
operation = `ALUOP_OR;
#10
if (result == 5'b11010)
$display("Or Passed");
#10
operation = `ALUOP_AND;
#10
if (result == 5'b00010)
$display("And Passed");
#10
operation = `ALUOP_NOR;
#10
if (result == 32'b11111111111111111111111111100101)
$display("Nor Passed");
#10
A = 32'b10000000000000000000000000000001;
B = 32'b10000000000000000000000000000001;
#10
operation = `ALUOP_ADD;
#10
if (overflow == 1'b1)
$display("Overflow Add Passed");
#10
A = 32'b01111111111111111111111111111111;
B = 32'b10000000000000000000000000000001;
shamt = 2;
#10
operation = `ALUOP_SUB;
#10
if (overflow == 1'b1)
$display("Overflow Sub Passed");
#10
A = 32'b11111111111111111111111111111111;
B = 32'b01111111111111111111111111111111;
shamt = 2;
#10
operation = `ALUOP_SLL;
#10
if (result == 32'b11111111111111111111111111111100)
$display("Sll Passed");
#10
operation = `ALUOP_SRL;
#10
if (result == 32'b00011111111111111111111111111111)
$display("Srl Passed");
end
endmodule | module TB_ArithmeticLogicUnit (); |
reg [31:0] A;
reg [31:0] B;
reg [4:0] operation;
reg [4:0] shamt;
wire [31:0] result;
wire overflow;
ArithmeticLogicUnit ALU (
.A (A),
.B (B),
.operation (operation),
.shamt (shamt),
.result (result),
.overflow (overflow)
);
initial begin
shamt = 0;
A = 20;
B = 10;
#10
operation = `ALUOP_ADD;
#10
if (result == 32'd30)
$display("Add Passed");
#10
operation = `ALUOP_SUB;
#10
if (result == 32'd10)
$display("Sub Passed");
#10
operation = `ALUOP_MUL;
#10
if (result == 32'd200)
$display("Mul Passed");
#10
operation = `ALUOP_SLT;
#10
if (result == 32'd0)
$display("Slower Than Passed");
#10
A = 5'b01010;
B = 5'b10010;
#10
operation = `ALUOP_OR;
#10
if (result == 5'b11010)
$display("Or Passed");
#10
operation = `ALUOP_AND;
#10
if (result == 5'b00010)
$display("And Passed");
#10
operation = `ALUOP_NOR;
#10
if (result == 32'b11111111111111111111111111100101)
$display("Nor Passed");
#10
A = 32'b10000000000000000000000000000001;
B = 32'b10000000000000000000000000000001;
#10
operation = `ALUOP_ADD;
#10
if (overflow == 1'b1)
$display("Overflow Add Passed");
#10
A = 32'b01111111111111111111111111111111;
B = 32'b10000000000000000000000000000001;
shamt = 2;
#10
operation = `ALUOP_SUB;
#10
if (overflow == 1'b1)
$display("Overflow Sub Passed");
#10
A = 32'b11111111111111111111111111111111;
B = 32'b01111111111111111111111111111111;
shamt = 2;
#10
operation = `ALUOP_SLL;
#10
if (result == 32'b11111111111111111111111111111100)
$display("Sll Passed");
#10
operation = `ALUOP_SRL;
#10
if (result == 32'b00011111111111111111111111111111)
$display("Srl Passed");
end
endmodule | 0 |
2,741 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v | 100,975,158 | TB_ControlUnity.v | v | 238 | 87 | [] | [] | [] | [(154, 387)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:60: Define or directive not defined: \'`SIG_NOP\'\n if (signals == `SIG_NOP)\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:60: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_NOP)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:59: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:65: Define or directive not defined: \'`OPCODE_TYPE_R\'\n id_opcode = `OPCODE_TYPE_R;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_TYPE_R;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:66: Define or directive not defined: \'`FUNCT_ADD\'\n id_funct = `FUNCT_ADD;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_funct = `FUNCT_ADD;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:70: Define or directive not defined: \'`SIG_R_TYPE\'\n if (signals == `SIG_R_TYPE)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:70: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_R_TYPE)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:75: Define or directive not defined: \'`ALUOP_ADD\'\n if (id_alu_op == `ALUOP_ADD)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:75: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_alu_op == `ALUOP_ADD)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:80: Define or directive not defined: \'`HAZ_EX_RS__EX_RT\'\n if (id_signal_forwarding == `HAZ_EX_RS__EX_RT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:80: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_signal_forwarding == `HAZ_EX_RS__EX_RT)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:91: Define or directive not defined: \'`OPCODE_SLTI\'\n id_opcode = `OPCODE_SLTI;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_SLTI;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:90: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:93: Define or directive not defined: \'`SIG_I_TYPE\'\n if (signals == `SIG_I_TYPE)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_I_TYPE)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:98: Define or directive not defined: \'`ALUOP_SLT\'\n if (id_alu_op == `ALUOP_SLT)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:98: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_alu_op == `ALUOP_SLT)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:103: Define or directive not defined: \'`HAZ_EX_RS\'\n if (id_signal_forwarding == `HAZ_EX_RS)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:103: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_signal_forwarding == `HAZ_EX_RS)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:114: Define or directive not defined: \'`OPCODE_BEQ\'\n id_opcode = `OPCODE_BEQ;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:114: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_BEQ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:118: Define or directive not defined: \'`SIG_BRANCH\'\n if (signals == `SIG_BRANCH)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:118: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_BRANCH)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:117: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:123: Define or directive not defined: \'`HAZ_ID_RS__ID_RT\'\n if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:123: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:134: Define or directive not defined: \'`OPCODE_BNE\'\n id_opcode = `OPCODE_BNE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:134: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_BNE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:133: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:138: Define or directive not defined: \'`SIG_BNE\'\n if (signals == `SIG_BNE)\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:138: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_BNE)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:137: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:143: Define or directive not defined: \'`HAZ_ID_RS__ID_RT\'\n if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:143: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:154: Define or directive not defined: \'`OPCODE_BNE\'\n id_opcode = `OPCODE_BNE;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:154: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_BNE;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:153: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:158: Define or directive not defined: \'`SIG_NOP\'\n if (signals == `SIG_NOP)\n ^~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:158: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_NOP)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:157: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:169: Define or directive not defined: \'`OPCODE_JAL\'\n id_opcode = `OPCODE_JAL;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:169: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_JAL;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:168: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:172: Define or directive not defined: \'`SIG_JUMP_LINK\'\n if (signals == `SIG_JUMP_LINK)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:172: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_JUMP_LINK)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:171: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:183: Define or directive not defined: \'`OPCODE_TYPE_R\'\n id_opcode = `OPCODE_TYPE_R;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:183: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_TYPE_R;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:182: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:184: Define or directive not defined: \'`FUNCT_JR\'\n id_funct = `FUNCT_JR;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:184: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_funct = `FUNCT_JR;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:187: Define or directive not defined: \'`SIG_JUMP_REG\'\n if (signals == `SIG_JUMP_REG)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:187: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (signals == `SIG_JUMP_REG)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:198: Define or directive not defined: \'`OPCODE_LW\'\n id_opcode = `OPCODE_LW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:198: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n id_opcode = `OPCODE_LW;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:197: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_ControlUnity.v:200: Define or directive not defined: \'`SIG_LOAD_WORD\'\n if (signals == `SIG_LOAD_WORD)\n ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 178 | module | module TB_ControlUnity ();
reg id_stall;
reg [5:0] id_opcode;
reg [5:0] id_funct;
reg id_cmp_eq;
wire if_flush;
wire [7:0] id_signal_forwarding;
wire [1:0] id_pc_source_sel;
wire id_sign_extend;
wire id_jump_link;
wire id_reg_dst;
wire id_alu_src;
wire id_branch_delay_slot;
wire [4:0] id_alu_op;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
ControlUnity Unity (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
wire [8:0] signals;
assign signals[8] = id_pc_source_sel[1];
assign signals[7] = id_pc_source_sel[0];
assign signals[6] = id_jump_link;
assign signals[5] = id_alu_src;
assign signals[4] = id_reg_dst;
assign signals[3] = id_mem_read;
assign signals[2] = id_mem_write;
assign signals[1] = id_mem_to_reg;
assign signals[0] = id_reg_write;
initial begin
id_stall = 1;
id_cmp_eq = 0;
#10
if (signals == `SIG_NOP)
$display("Stall Signals Passed");
#10
id_stall = 0;
id_opcode = `OPCODE_TYPE_R;
id_funct = `FUNCT_ADD;
id_cmp_eq = 0;
#10
if (signals == `SIG_R_TYPE)
$display("R-Type Signals are OK");
else
$display("R-Type Signals Fail");
if (id_alu_op == `ALUOP_ADD)
$display("R-Type Alu Operation is OK");
else
$display("R-Type Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS__EX_RT)
$display("R-Type Hazard Detection Signals OK");
else
$display("R-Type Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("It detected that this instruction will change PC Register");
else
$display("It detected that this instruction will not change PC Register");
#10
id_opcode = `OPCODE_SLTI;
#10
if (signals == `SIG_I_TYPE)
$display("I-Type Signals are OK");
else
$display("I-Type Signals Fail");
if (id_alu_op == `ALUOP_SLT)
$display("I-Type Alu Operation is OK");
else
$display("I-Type Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS)
$display("I-Type Hazard Detection Signals OK");
else
$display("I-Type Hazard Detection Signals Fail");
if (id_sign_extend)
$display("Instruction requires Sign Extension - SUCCESS");
else
$display("Instruction doesn't require Sign Extension - FAIL");
#10
id_opcode = `OPCODE_BEQ;
id_cmp_eq = 1;
#10
if (signals == `SIG_BRANCH)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)
$display("Branch Hazard Detection Signals OK");
else
$display("Branch Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - SUCCESS");
else
$display("Instruction won't branch to a defined Address - FAIL");
#10
id_opcode = `OPCODE_BNE;
id_cmp_eq = 0;
#10
if (signals == `SIG_BNE)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)
$display("Branch Hazard Detection Signals OK");
else
$display("Branch Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - SUCCESS");
else
$display("Instruction won't branch to a defined Address - FAIL");
#10
id_opcode = `OPCODE_BNE;
id_cmp_eq = 1;
#10
if (signals == `SIG_NOP)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - FAIL");
else
$display("Instruction won't branch to a defined Address - SUCCESS");
#10
id_opcode = `OPCODE_JAL;
#10
if (signals == `SIG_JUMP_LINK)
$display("Jump Link Signals are OK");
else
$display("Jump Link Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will jump to a defined Address - SUCCESS");
else
$display("Instruction won't jump to a defined Address - FAIL");
#10
id_opcode = `OPCODE_TYPE_R;
id_funct = `FUNCT_JR;
#10
if (signals == `SIG_JUMP_REG)
$display("Jump Register Signals are OK");
else
$display("Jump Register Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will jump to a defined Address - SUCCESS");
else
$display("Instruction won't jump to a defined Address - FAIL");
#10
id_opcode = `OPCODE_LW;
#10
if (signals == `SIG_LOAD_WORD)
$display("Load Signals are OK");
else
$display("Load Signals Fail");
if (id_alu_op == `ALUOP_ADDU)
$display("Load Alu Operation is OK");
else
$display("Load Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS)
$display("Load Hazard Detection Signals OK");
else
$display("Load Hazard Detection Signals Fail");
#10
id_opcode = `OPCODE_SW;
#10
if (signals == `SIG_STORE_WORD)
$display("Store Signals are OK");
else
$display("Store Signals - Fail");
if (id_alu_op == `ALUOP_ADDU)
$display("Store Alu Operation is OK");
else
$display("Store Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS__WB_RT)
$display("Store Hazard Detection Signals OK");
else
$display("Store Hazard Detection Signals Fail");
end
endmodule | module TB_ControlUnity (); |
reg id_stall;
reg [5:0] id_opcode;
reg [5:0] id_funct;
reg id_cmp_eq;
wire if_flush;
wire [7:0] id_signal_forwarding;
wire [1:0] id_pc_source_sel;
wire id_sign_extend;
wire id_jump_link;
wire id_reg_dst;
wire id_alu_src;
wire id_branch_delay_slot;
wire [4:0] id_alu_op;
wire id_mem_write;
wire id_mem_read;
wire id_mem_to_reg;
wire id_reg_write;
ControlUnity Unity (
.id_stall (id_stall),
.id_opcode (id_opcode),
.id_funct (id_funct),
.id_cmp_eq (id_cmp_eq),
.if_flush (if_flush),
.id_signal_forwarding (id_signal_forwarding),
.id_pc_source_sel (id_pc_source_sel),
.id_sign_extend (id_sign_extend),
.id_jump_link (id_jump_link),
.id_reg_dst (id_reg_dst),
.id_alu_src (id_alu_src),
.id_alu_op (id_alu_op),
.id_mem_read (id_mem_read),
.id_mem_write (id_mem_write),
.id_mem_to_reg (id_mem_to_reg),
.id_reg_write (id_reg_write),
.id_branch_delay_slot (id_branch_delay_slot)
);
wire [8:0] signals;
assign signals[8] = id_pc_source_sel[1];
assign signals[7] = id_pc_source_sel[0];
assign signals[6] = id_jump_link;
assign signals[5] = id_alu_src;
assign signals[4] = id_reg_dst;
assign signals[3] = id_mem_read;
assign signals[2] = id_mem_write;
assign signals[1] = id_mem_to_reg;
assign signals[0] = id_reg_write;
initial begin
id_stall = 1;
id_cmp_eq = 0;
#10
if (signals == `SIG_NOP)
$display("Stall Signals Passed");
#10
id_stall = 0;
id_opcode = `OPCODE_TYPE_R;
id_funct = `FUNCT_ADD;
id_cmp_eq = 0;
#10
if (signals == `SIG_R_TYPE)
$display("R-Type Signals are OK");
else
$display("R-Type Signals Fail");
if (id_alu_op == `ALUOP_ADD)
$display("R-Type Alu Operation is OK");
else
$display("R-Type Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS__EX_RT)
$display("R-Type Hazard Detection Signals OK");
else
$display("R-Type Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("It detected that this instruction will change PC Register");
else
$display("It detected that this instruction will not change PC Register");
#10
id_opcode = `OPCODE_SLTI;
#10
if (signals == `SIG_I_TYPE)
$display("I-Type Signals are OK");
else
$display("I-Type Signals Fail");
if (id_alu_op == `ALUOP_SLT)
$display("I-Type Alu Operation is OK");
else
$display("I-Type Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS)
$display("I-Type Hazard Detection Signals OK");
else
$display("I-Type Hazard Detection Signals Fail");
if (id_sign_extend)
$display("Instruction requires Sign Extension - SUCCESS");
else
$display("Instruction doesn't require Sign Extension - FAIL");
#10
id_opcode = `OPCODE_BEQ;
id_cmp_eq = 1;
#10
if (signals == `SIG_BRANCH)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)
$display("Branch Hazard Detection Signals OK");
else
$display("Branch Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - SUCCESS");
else
$display("Instruction won't branch to a defined Address - FAIL");
#10
id_opcode = `OPCODE_BNE;
id_cmp_eq = 0;
#10
if (signals == `SIG_BNE)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_signal_forwarding == `HAZ_ID_RS__ID_RT)
$display("Branch Hazard Detection Signals OK");
else
$display("Branch Hazard Detection Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - SUCCESS");
else
$display("Instruction won't branch to a defined Address - FAIL");
#10
id_opcode = `OPCODE_BNE;
id_cmp_eq = 1;
#10
if (signals == `SIG_NOP)
$display("Branch Signals are OK");
else
$display("Branch Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will branch to a defined Address - FAIL");
else
$display("Instruction won't branch to a defined Address - SUCCESS");
#10
id_opcode = `OPCODE_JAL;
#10
if (signals == `SIG_JUMP_LINK)
$display("Jump Link Signals are OK");
else
$display("Jump Link Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will jump to a defined Address - SUCCESS");
else
$display("Instruction won't jump to a defined Address - FAIL");
#10
id_opcode = `OPCODE_TYPE_R;
id_funct = `FUNCT_JR;
#10
if (signals == `SIG_JUMP_REG)
$display("Jump Register Signals are OK");
else
$display("Jump Register Signals Fail");
if (id_branch_delay_slot)
$display("Instruction will jump to a defined Address - SUCCESS");
else
$display("Instruction won't jump to a defined Address - FAIL");
#10
id_opcode = `OPCODE_LW;
#10
if (signals == `SIG_LOAD_WORD)
$display("Load Signals are OK");
else
$display("Load Signals Fail");
if (id_alu_op == `ALUOP_ADDU)
$display("Load Alu Operation is OK");
else
$display("Load Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS)
$display("Load Hazard Detection Signals OK");
else
$display("Load Hazard Detection Signals Fail");
#10
id_opcode = `OPCODE_SW;
#10
if (signals == `SIG_STORE_WORD)
$display("Store Signals are OK");
else
$display("Store Signals - Fail");
if (id_alu_op == `ALUOP_ADDU)
$display("Store Alu Operation is OK");
else
$display("Store Alu Operation Fail");
if (id_signal_forwarding == `HAZ_EX_RS__WB_RT)
$display("Store Hazard Detection Signals OK");
else
$display("Store Hazard Detection Signals Fail");
end
endmodule | 0 |
2,742 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v | 100,975,158 | TB_DataMemoryInterface.v | v | 62 | 57 | [] | [] | [] | [(3, 61)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:27: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:32: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:36: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:47: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:59: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_DataMemoryInterface.v:12: Cannot find file containing module: \'DataMemoryInterface\'\n DataMemoryInterface DataMemory(\n ^~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/DataMemoryInterface.sv\n DataMemoryInterface\n DataMemoryInterface.v\n DataMemoryInterface.sv\n obj_dir/DataMemoryInterface\n obj_dir/DataMemoryInterface.v\n obj_dir/DataMemoryInterface.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 179 | module | module TB_DataMemoryInterface ();
reg clock;
reg reset;
reg [31:0] address;
reg mem_write;
reg [31:0] data_write;
reg mem_read;
wire [31:0] read_data;
DataMemoryInterface DataMemory(
.clock (clock),
.reset (reset),
.address (address),
.mem_write (mem_write),
.data_write (data_write),
.mem_read (mem_read),
.read_data (read_data)
);
initial begin
reset = 0;
clock = 1;
#10
address = 32'd0;
mem_write = 1;
data_write = 32'd500;
#20
mem_write = 0;
mem_read = 1;
#10
if (read_data == 32'd500)
$display ("Read and Write 1 - OK");
else
$display ("Read and Write 1 - FAIL");
#20
address = 32'd0;
mem_write = 1;
data_write = 32'd400;
#20
mem_write = 0;
mem_read = 1;
#10
if (read_data == 32'd400)
$display ("Read and Write Override - OK");
else
$display ("Read and Write Override - FAIL");
end
always #10 clock = ~clock;
endmodule | module TB_DataMemoryInterface (); |
reg clock;
reg reset;
reg [31:0] address;
reg mem_write;
reg [31:0] data_write;
reg mem_read;
wire [31:0] read_data;
DataMemoryInterface DataMemory(
.clock (clock),
.reset (reset),
.address (address),
.mem_write (mem_write),
.data_write (data_write),
.mem_read (mem_read),
.read_data (read_data)
);
initial begin
reset = 0;
clock = 1;
#10
address = 32'd0;
mem_write = 1;
data_write = 32'd500;
#20
mem_write = 0;
mem_read = 1;
#10
if (read_data == 32'd500)
$display ("Read and Write 1 - OK");
else
$display ("Read and Write 1 - FAIL");
#20
address = 32'd0;
mem_write = 1;
data_write = 32'd400;
#20
mem_write = 0;
mem_read = 1;
#10
if (read_data == 32'd400)
$display ("Read and Write Override - OK");
else
$display ("Read and Write Override - FAIL");
end
always #10 clock = ~clock;
endmodule | 0 |
2,743 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v | 100,975,158 | TB_Forwarding_Hazard_Unity.v | v | 213 | 153 | [] | [] | [] | [(154, 362)] | null | null | 1: b'%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:2: Cannot find include file: Constants.v\n`include "Constants.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Constants.v.sv\n Constants.v\n Constants.v.v\n Constants.v.sv\n obj_dir/Constants.v\n obj_dir/Constants.v.v\n obj_dir/Constants.v.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:59: Define or directive not defined: \'`HAZ_ID_RS__ID_RT\'\n sig_hazards <= `HAZ_ID_RS__ID_RT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n sig_hazards <= `HAZ_ID_RS__ID_RT;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:58: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:81: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:92: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:102: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:106: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:117: Define or directive not defined: \'`HAZ_EX_RS__EX_RT\'\n sig_hazards <= `HAZ_EX_RS__EX_RT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n sig_hazards <= `HAZ_EX_RS__EX_RT;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:116: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:133: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:143: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:147: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:158: Define or directive not defined: \'`HAZ_EX_RS__WB_RT\'\n sig_hazards <= `HAZ_EX_RS__WB_RT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:158: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n sig_hazards <= `HAZ_EX_RS__WB_RT;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:157: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:170: Define or directive not defined: \'`HAZ_EX_RS__EX_RT\'\n sig_hazards <= `HAZ_EX_RS__EX_RT;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:170: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n sig_hazards <= `HAZ_EX_RS__EX_RT;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:169: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:180: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:186: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:191: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:197: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Forwarding_Hazard_Unity.v:200: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: Exiting due to 9 error(s), 18 warning(s)\n' | 180 | module | module TB_Forwarding_Hazard_Unity ();
reg [7:0] sig_hazards;
reg [4:0] id_rs;
reg [4:0] id_rt;
reg [4:0] ex_rs;
reg [4:0] ex_rt;
reg [4:0] ex_rt_rd;
reg [4:0] me_rt_rd;
reg [4:0] wb_rt_rd;
reg ex_jump_link;
reg ex_reg_write;
reg me_reg_write;
reg wb_reg_write;
reg me_mem_read;
reg me_mem_write;
reg me_mem_to_reg;
wire id_stall;
wire ex_stall;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire me_write_data_fwd_sel;
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (sig_hazards),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
initial begin
#10
sig_hazards <= `HAZ_ID_RS__ID_RT;
id_rs = 5'd1;
id_rt = 5'd2;
ex_rs = 5'd3;
ex_rt = 5'd4;
ex_rt_rd = 5'd1;
me_rt_rd = 5'd2;
wb_rt_rd = 5'd3;
ex_reg_write = 1;
me_reg_write = 1;
wb_reg_write = 1;
me_mem_read = 0;
me_mem_write = 0;
#10
if (id_stall == 1)
$display ("Stall when need value Branch - OK");
#10
id_rs = 5'd1;
id_rt = 5'd2;
ex_rs = 5'd3;
ex_rt = 5'd4;
ex_rt_rd = 5'd3;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd2;
#10
if (id_fwd_rs_sel == 2'b01)
$display ("Forwarding ME/ID RS - OK");
else
$display ("Forwarding ME/ID RS - FAIL");
if (id_fwd_rt_sel == 2'b10)
$display ("Forwarding WB/ID RT - OK");
else
$display ("Forwarding WB/ID RS - FAIL");
#10
me_rt_rd = 5'd2;
wb_rt_rd = 5'd1;
#10
if (id_fwd_rs_sel == 2'b10)
$display ("Forwarding WB/ID RS - OK");
else
$display ("Forwarding WB/ID RS - FAIL");
if (id_fwd_rt_sel == 2'b01)
$display ("Forwarding ME/ID RT - OK");
else
$display ("Forwarding ME/ID RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__EX_RT;
ex_rs = 5'd1;
ex_rt = 5'd2;
ex_rt_rd = 5'd6;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd2;
ex_reg_write = 1;
me_reg_write = 1;
wb_reg_write = 1;
me_mem_read = 0;
me_mem_write = 0;
ex_jump_link = 0;
#10
if (ex_fwd_rs_sel == 2'b01)
$display ("Forwarding ME/EX RS - OK");
else
$display ("Forwarding ME/EX RS - FAIL");
if (ex_fwd_rt_sel == 2'b10)
$display ("Forwarding WB/EX RT - OK");
else
$display ("Forwarding WB/EX RT - FAIL");
#10
me_rt_rd = 5'd2;
wb_rt_rd = 5'd1;
#10
if (ex_fwd_rs_sel == 2'b10)
$display ("Forwarding WB/EX RS - OK");
else
$display ("Forwarding WB/EX RS - FAIL");
if (ex_fwd_rt_sel == 2'b01)
$display ("Forwarding ME/EX RT - OK");
else
$display ("Forwarding ME/EX RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__WB_RT;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd1;
me_reg_write = 0;
#10
if (me_write_data_fwd_sel == 1)
$display ("Forwarding WB/ME RT - OK");
else
$display ("Forwarding WB/ME RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__EX_RT;
ex_rs = 5'd1;
ex_rt = 5'd2;
me_rt_rd = 5'd1;
me_mem_read = 1;
me_reg_write = 1;
ex_jump_link = 0;
#10
if (ex_stall == 1)
$display ("Stall EX when need value Load Value - OK");
else
$display ("Stall EX when need value Load Value - FAIL");
#10
me_mem_read = 0;
me_mem_write = 1;
me_reg_write = 0;
#10
if (ex_stall == 0)
$display ("Stall EX when need value Only on Load Value - OK");
else
$display ("Stall EX when need value Only on Load Value - FAIL");
#10
ex_jump_link = 1;
#10
if (ex_fwd_rs_sel == 2'b11)
$display ("Jump Link RS - OK");
else
$display ("Jump Link RS - FAIL");
if (ex_fwd_rt_sel == 2'b11)
$display ("Jump Link RT - OK");
else
$display ("Jump Link RT - FAIL");
end
endmodule | module TB_Forwarding_Hazard_Unity (); |
reg [7:0] sig_hazards;
reg [4:0] id_rs;
reg [4:0] id_rt;
reg [4:0] ex_rs;
reg [4:0] ex_rt;
reg [4:0] ex_rt_rd;
reg [4:0] me_rt_rd;
reg [4:0] wb_rt_rd;
reg ex_jump_link;
reg ex_reg_write;
reg me_reg_write;
reg wb_reg_write;
reg me_mem_read;
reg me_mem_write;
reg me_mem_to_reg;
wire id_stall;
wire ex_stall;
wire [1:0] id_fwd_rs_sel;
wire [1:0] id_fwd_rt_sel;
wire [1:0] ex_fwd_rs_sel;
wire [1:0] ex_fwd_rt_sel;
wire me_write_data_fwd_sel;
Forwarding_Hazard_Unity ForwardingHazardControl (
.sig_hazards (sig_hazards),
.id_rs (id_rs),
.id_rt (id_rt),
.ex_rs (ex_rs),
.ex_rt (ex_rt),
.ex_rt_rd (ex_rt_rd),
.me_rt_rd (me_rt_rd),
.wb_rt_rd (wb_rt_rd),
.ex_jump_link (ex_jump_link),
.ex_reg_write (ex_reg_write),
.me_reg_write (me_reg_write),
.wb_reg_write (wb_reg_write),
.me_mem_read (me_mem_read),
.me_mem_write (me_mem_write),
.me_mem_to_reg (me_mem_to_reg),
.id_stall (id_stall),
.ex_stall (ex_stall),
.id_fwd_rs_sel (id_fwd_rs_sel),
.id_fwd_rt_sel (id_fwd_rt_sel),
.ex_fwd_rs_sel (ex_fwd_rs_sel),
.ex_fwd_rt_sel (ex_fwd_rt_sel),
.me_write_data_fwd_sel (me_write_data_fwd_sel)
);
initial begin
#10
sig_hazards <= `HAZ_ID_RS__ID_RT;
id_rs = 5'd1;
id_rt = 5'd2;
ex_rs = 5'd3;
ex_rt = 5'd4;
ex_rt_rd = 5'd1;
me_rt_rd = 5'd2;
wb_rt_rd = 5'd3;
ex_reg_write = 1;
me_reg_write = 1;
wb_reg_write = 1;
me_mem_read = 0;
me_mem_write = 0;
#10
if (id_stall == 1)
$display ("Stall when need value Branch - OK");
#10
id_rs = 5'd1;
id_rt = 5'd2;
ex_rs = 5'd3;
ex_rt = 5'd4;
ex_rt_rd = 5'd3;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd2;
#10
if (id_fwd_rs_sel == 2'b01)
$display ("Forwarding ME/ID RS - OK");
else
$display ("Forwarding ME/ID RS - FAIL");
if (id_fwd_rt_sel == 2'b10)
$display ("Forwarding WB/ID RT - OK");
else
$display ("Forwarding WB/ID RS - FAIL");
#10
me_rt_rd = 5'd2;
wb_rt_rd = 5'd1;
#10
if (id_fwd_rs_sel == 2'b10)
$display ("Forwarding WB/ID RS - OK");
else
$display ("Forwarding WB/ID RS - FAIL");
if (id_fwd_rt_sel == 2'b01)
$display ("Forwarding ME/ID RT - OK");
else
$display ("Forwarding ME/ID RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__EX_RT;
ex_rs = 5'd1;
ex_rt = 5'd2;
ex_rt_rd = 5'd6;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd2;
ex_reg_write = 1;
me_reg_write = 1;
wb_reg_write = 1;
me_mem_read = 0;
me_mem_write = 0;
ex_jump_link = 0;
#10
if (ex_fwd_rs_sel == 2'b01)
$display ("Forwarding ME/EX RS - OK");
else
$display ("Forwarding ME/EX RS - FAIL");
if (ex_fwd_rt_sel == 2'b10)
$display ("Forwarding WB/EX RT - OK");
else
$display ("Forwarding WB/EX RT - FAIL");
#10
me_rt_rd = 5'd2;
wb_rt_rd = 5'd1;
#10
if (ex_fwd_rs_sel == 2'b10)
$display ("Forwarding WB/EX RS - OK");
else
$display ("Forwarding WB/EX RS - FAIL");
if (ex_fwd_rt_sel == 2'b01)
$display ("Forwarding ME/EX RT - OK");
else
$display ("Forwarding ME/EX RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__WB_RT;
me_rt_rd = 5'd1;
wb_rt_rd = 5'd1;
me_reg_write = 0;
#10
if (me_write_data_fwd_sel == 1)
$display ("Forwarding WB/ME RT - OK");
else
$display ("Forwarding WB/ME RT - FAIL");
#10
sig_hazards <= `HAZ_EX_RS__EX_RT;
ex_rs = 5'd1;
ex_rt = 5'd2;
me_rt_rd = 5'd1;
me_mem_read = 1;
me_reg_write = 1;
ex_jump_link = 0;
#10
if (ex_stall == 1)
$display ("Stall EX when need value Load Value - OK");
else
$display ("Stall EX when need value Load Value - FAIL");
#10
me_mem_read = 0;
me_mem_write = 1;
me_reg_write = 0;
#10
if (ex_stall == 0)
$display ("Stall EX when need value Only on Load Value - OK");
else
$display ("Stall EX when need value Only on Load Value - FAIL");
#10
ex_jump_link = 1;
#10
if (ex_fwd_rs_sel == 2'b11)
$display ("Jump Link RS - OK");
else
$display ("Jump Link RS - FAIL");
if (ex_fwd_rt_sel == 2'b11)
$display ("Jump Link RT - OK");
else
$display ("Jump Link RT - FAIL");
end
endmodule | 0 |
2,744 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Processor.v | 100,975,158 | TB_Processor.v | v | 83 | 105 | [] | [] | [] | [(3, 82)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Processor.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Processor.v:75: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_Processor.v:37: Cannot find file containing module: \'Processor\'\n Processor #(.INSTRUCTIONS("C:/Outros/MI-SD/TEC499-Sistemas-Digitais/inst_exponential.txt")) MIPS32 (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Processor\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Processor.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/Processor.sv\n Processor\n Processor.v\n Processor.sv\n obj_dir/Processor\n obj_dir/Processor.v\n obj_dir/Processor.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 181 | module | module TB_Processor ();
reg clock;
reg reset;
wire [31:0] dif_instruction;
wire [31:0] dif_pc_usable;
wire [31:0] did_instruction;
wire [31:0] did_pc_usable;
wire [31:0] did_rt_data;
wire [31:0] did_rs_data;
wire [31:0] did_se_immediate;
wire [4:0] did_rt;
wire [4:0] did_rs;
wire [31:0] dwb_write_data;
wire [31:0] dex_alu_result;
wire [31:0] dex_alu_a;
wire [31:0] dex_alu_b;
wire [4:0] dex_alu_op;
wire [4:0] dme_rt_rd;
wire [31:0] dme_data_mem;
wire [31:0] dme_data_write_mem;
wire [4:0] dwb_rt_rd;
wire dif_flush;
wire did_flush;
wire dex_alu_src;
wire [1:0] dex_fwd_rt_sel;
wire [1:0] dex_fwd_rs_sel;
wire dif_stall;
wire did_stall;
wire dwb_write_reg;
wire dme_write_mem;
wire dme_read_mem;
wire did_branch_delay_slot;
Processor #(.INSTRUCTIONS("C:/Outros/MI-SD/TEC499-Sistemas-Digitais/inst_exponential.txt")) MIPS32 (
.clock (clock),
.reset (reset),
.dif_instruction (dif_instruction),
.dif_pc_usable (dif_pc_usable),
.did_rt_data (did_rt_data),
.did_rs_data (did_rs_data),
.did_se_immediate (did_se_immediate),
.did_rt (did_rt),
.did_rs (did_rs),
.dex_alu_a (dex_alu_a),
.dex_alu_b (dex_alu_b),
.dex_alu_result (dex_alu_result),
.dme_data_write_mem (dme_data_write_mem),
.dme_data_mem (dme_data_mem),
.dwb_write_reg (dwb_write_reg),
.dwb_write_data (dwb_write_data),
.dwb_rt_rd (dwb_rt_rd)
);
integer i = 0;
initial begin
clock = 0;
end
always begin
#10
clock = ~clock;
$display ("Cycle...........: %d", i);
$display ("PC..............: %b", dif_pc_usable);
$display ("Instruction.....: %b", dif_instruction);
$display ("---------------------");
end
always begin
#20
i = i + 1;
end
initial begin
reset = 0;
end
endmodule | module TB_Processor (); |
reg clock;
reg reset;
wire [31:0] dif_instruction;
wire [31:0] dif_pc_usable;
wire [31:0] did_instruction;
wire [31:0] did_pc_usable;
wire [31:0] did_rt_data;
wire [31:0] did_rs_data;
wire [31:0] did_se_immediate;
wire [4:0] did_rt;
wire [4:0] did_rs;
wire [31:0] dwb_write_data;
wire [31:0] dex_alu_result;
wire [31:0] dex_alu_a;
wire [31:0] dex_alu_b;
wire [4:0] dex_alu_op;
wire [4:0] dme_rt_rd;
wire [31:0] dme_data_mem;
wire [31:0] dme_data_write_mem;
wire [4:0] dwb_rt_rd;
wire dif_flush;
wire did_flush;
wire dex_alu_src;
wire [1:0] dex_fwd_rt_sel;
wire [1:0] dex_fwd_rs_sel;
wire dif_stall;
wire did_stall;
wire dwb_write_reg;
wire dme_write_mem;
wire dme_read_mem;
wire did_branch_delay_slot;
Processor #(.INSTRUCTIONS("C:/Outros/MI-SD/TEC499-Sistemas-Digitais/inst_exponential.txt")) MIPS32 (
.clock (clock),
.reset (reset),
.dif_instruction (dif_instruction),
.dif_pc_usable (dif_pc_usable),
.did_rt_data (did_rt_data),
.did_rs_data (did_rs_data),
.did_se_immediate (did_se_immediate),
.did_rt (did_rt),
.did_rs (did_rs),
.dex_alu_a (dex_alu_a),
.dex_alu_b (dex_alu_b),
.dex_alu_result (dex_alu_result),
.dme_data_write_mem (dme_data_write_mem),
.dme_data_mem (dme_data_mem),
.dwb_write_reg (dwb_write_reg),
.dwb_write_data (dwb_write_data),
.dwb_rt_rd (dwb_rt_rd)
);
integer i = 0;
initial begin
clock = 0;
end
always begin
#10
clock = ~clock;
$display ("Cycle...........: %d", i);
$display ("PC..............: %b", dif_pc_usable);
$display ("Instruction.....: %b", dif_instruction);
$display ("---------------------");
end
always begin
#20
i = i + 1;
end
initial begin
reset = 0;
end
endmodule | 0 |
2,745 | data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v | 100,975,158 | TB_RegisterFile.v | v | 101 | 65 | [] | [] | [] | [(3, 100)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:52: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:61: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:87: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:91: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/Processor/TB_RegisterFile.v:19: Cannot find file containing module: \'RegisterFile\'\n RegisterFile RegisterAccess (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile.v\n data/full_repos/permissive/100975158/MIPS32_Full/Processor,data/full_repos/permissive/100975158/RegisterFile.sv\n RegisterFile\n RegisterFile.v\n RegisterFile.sv\n obj_dir/RegisterFile\n obj_dir/RegisterFile.v\n obj_dir/RegisterFile.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 182 | module | module TB_RegisterFile ();
reg clock;
reg [2:0] result;
reg reset;
reg [4:0] read_reg1;
reg [4:0] read_reg2;
reg [4:0] wb_rt_rd;
reg wb_reg_write;
reg [31:0] wb_write_data;
wire [31:0] id_reg1_data;
wire [31:0] id_reg2_data;
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (read_reg1),
.read_reg2 (read_reg2),
.wb_reg_write (wb_reg_write),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
initial begin
clock = 1;
end
always #10 clock = ~clock;
initial begin
reset <= 0;
result <= 3'd0;
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd1;
wb_rt_rd <= 5'd3;
wb_write_data <= 32'd500;
#20
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd0;
wb_rt_rd <= 5'd4;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd500)
result[0] <= 1;
#10
read_reg1 <= 5'd4;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd1;
wb_rt_rd <= 5'd0;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd0)
result[1] <= 1;
#10
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd0;
wb_rt_rd <= 5'd3;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd500 & id_reg2_data == 32'd0)
result[2] <= 1;
#20
if (result == 3'd7)
$display("All Tests Passed");
else
$display("Some tests didn't pass");
end
endmodule | module TB_RegisterFile (); |
reg clock;
reg [2:0] result;
reg reset;
reg [4:0] read_reg1;
reg [4:0] read_reg2;
reg [4:0] wb_rt_rd;
reg wb_reg_write;
reg [31:0] wb_write_data;
wire [31:0] id_reg1_data;
wire [31:0] id_reg2_data;
RegisterFile RegisterAccess (
.clock (clock),
.reset (reset),
.read_reg1 (read_reg1),
.read_reg2 (read_reg2),
.wb_reg_write (wb_reg_write),
.wb_rt_rd (wb_rt_rd),
.wb_write_data (wb_write_data),
.id_reg1_data (id_reg1_data),
.id_reg2_data (id_reg2_data)
);
initial begin
clock = 1;
end
always #10 clock = ~clock;
initial begin
reset <= 0;
result <= 3'd0;
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd1;
wb_rt_rd <= 5'd3;
wb_write_data <= 32'd500;
#20
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd0;
wb_rt_rd <= 5'd4;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd500)
result[0] <= 1;
#10
read_reg1 <= 5'd4;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd1;
wb_rt_rd <= 5'd0;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd0)
result[1] <= 1;
#10
read_reg1 <= 5'd3;
read_reg2 <= 5'd0;
wb_reg_write <= 1'd0;
wb_rt_rd <= 5'd3;
wb_write_data <= 32'd500;
#10
if (id_reg1_data == 32'd500 & id_reg2_data == 32'd0)
result[2] <= 1;
#20
if (result == 3'd7)
$display("All Tests Passed");
else
$display("Some tests didn't pass");
end
endmodule | 0 |
2,746 | data/full_repos/permissive/100975158/MIPS32_Full/UART/RX.v | 100,975,158 | RX.v | v | 102 | 92 | [] | [] | [] | null | line:10: before: "=" | data/verilator_xmls/0da7691d-3dc4-48b0-8e0c-47b75b99be84.xml | null | 183 | module | module RX (
input clock,
input reset,
input uart_tick_16,
input rx_signal,
output ready,
output reg [7:0] rx_data = 0
);
localparam [3:0] IDLE = 0;
localparam [3:0] BIT0 = 1;
localparam [3:0] BIT1 = 2;
localparam [3:0] BIT2 = 3;
localparam [3:0] BIT3 = 4;
localparam [3:0] BIT4 = 5;
localparam [3:0] BIT5 = 6;
localparam [3:0] BIT6 = 7;
localparam [3:0] BIT7 = 8;
localparam [3:0] STOP = 9;
reg [1:0] rx_sync = 3;
reg [1:0] rx_count = 0;
reg rx_bit = 1;
reg [3:0] state = IDLE;
reg clock_lock = 0;
reg [3:0] rx_bit_spacing = 4'b1110;
always @ (posedge clock) begin
if (uart_tick_16)
rx_sync <= {rx_sync[0], rx_signal};
else
rx_sync <= rx_sync;
end
always @ (posedge clock) begin
if (uart_tick_16) begin
case (rx_sync[1])
0: rx_count <= (rx_count == 2'b11) ? rx_count : rx_count + 1'b1;
1: rx_count <= (rx_count == 2'b00) ? rx_count : rx_count - 1'b1;
endcase
rx_bit <= (rx_count == 2'b11) ? 1'b0 : ( (rx_count == 2'b00) ? 1'b1 : rx_bit );
end
else begin
rx_count <= rx_count;
rx_bit <= rx_bit;
end
end
always @ (posedge clock) begin
if (uart_tick_16) begin
if (~clock_lock)
clock_lock <= ~rx_bit;
else
clock_lock <= ((state == IDLE) && rx_bit) ? 1'b0 : clock_lock;
rx_bit_spacing <= (clock_lock) ? rx_bit_spacing + 1'b1 : 4'b1110;
end
else begin
clock_lock <= clock_lock;
rx_bit_spacing <= rx_bit_spacing;
end
end
wire rx_rc_bit = (rx_bit_spacing == 4'b1111);
always @ (posedge clock) begin
if (reset) state <= IDLE;
else if (uart_tick_16) begin
case (state)
IDLE: state <= (rx_rc_bit & (rx_bit == 0)) ? BIT0 : IDLE;
BIT0: state <= (rx_rc_bit) ? BIT1 : BIT0;
BIT1: state <= (rx_rc_bit) ? BIT2 : BIT1;
BIT2: state <= (rx_rc_bit) ? BIT3 : BIT2;
BIT3: state <= (rx_rc_bit) ? BIT4 : BIT3;
BIT4: state <= (rx_rc_bit) ? BIT5 : BIT4;
BIT5: state <= (rx_rc_bit) ? BIT6 : BIT5;
BIT6: state <= (rx_rc_bit) ? BIT7 : BIT6;
BIT7: state <= (rx_rc_bit) ? STOP : BIT7;
STOP: state <= (rx_rc_bit) ? IDLE : STOP;
default: state <= 4'bxxxx;
endcase
end
else state <= state;
end
wire read_value = (uart_tick_16 & rx_rc_bit & (state != IDLE) & (state != STOP));
always @ (posedge clock) begin
rx_data <= (read_value) ? {rx_bit, rx_data[7:1]} : rx_data[7:0];
end
assign ready = (uart_tick_16 & rx_rc_bit & (state == STOP));
endmodule | module RX (
input clock,
input reset,
input uart_tick_16,
input rx_signal,
output ready,
output reg [7:0] rx_data = 0
); |
localparam [3:0] IDLE = 0;
localparam [3:0] BIT0 = 1;
localparam [3:0] BIT1 = 2;
localparam [3:0] BIT2 = 3;
localparam [3:0] BIT3 = 4;
localparam [3:0] BIT4 = 5;
localparam [3:0] BIT5 = 6;
localparam [3:0] BIT6 = 7;
localparam [3:0] BIT7 = 8;
localparam [3:0] STOP = 9;
reg [1:0] rx_sync = 3;
reg [1:0] rx_count = 0;
reg rx_bit = 1;
reg [3:0] state = IDLE;
reg clock_lock = 0;
reg [3:0] rx_bit_spacing = 4'b1110;
always @ (posedge clock) begin
if (uart_tick_16)
rx_sync <= {rx_sync[0], rx_signal};
else
rx_sync <= rx_sync;
end
always @ (posedge clock) begin
if (uart_tick_16) begin
case (rx_sync[1])
0: rx_count <= (rx_count == 2'b11) ? rx_count : rx_count + 1'b1;
1: rx_count <= (rx_count == 2'b00) ? rx_count : rx_count - 1'b1;
endcase
rx_bit <= (rx_count == 2'b11) ? 1'b0 : ( (rx_count == 2'b00) ? 1'b1 : rx_bit );
end
else begin
rx_count <= rx_count;
rx_bit <= rx_bit;
end
end
always @ (posedge clock) begin
if (uart_tick_16) begin
if (~clock_lock)
clock_lock <= ~rx_bit;
else
clock_lock <= ((state == IDLE) && rx_bit) ? 1'b0 : clock_lock;
rx_bit_spacing <= (clock_lock) ? rx_bit_spacing + 1'b1 : 4'b1110;
end
else begin
clock_lock <= clock_lock;
rx_bit_spacing <= rx_bit_spacing;
end
end
wire rx_rc_bit = (rx_bit_spacing == 4'b1111);
always @ (posedge clock) begin
if (reset) state <= IDLE;
else if (uart_tick_16) begin
case (state)
IDLE: state <= (rx_rc_bit & (rx_bit == 0)) ? BIT0 : IDLE;
BIT0: state <= (rx_rc_bit) ? BIT1 : BIT0;
BIT1: state <= (rx_rc_bit) ? BIT2 : BIT1;
BIT2: state <= (rx_rc_bit) ? BIT3 : BIT2;
BIT3: state <= (rx_rc_bit) ? BIT4 : BIT3;
BIT4: state <= (rx_rc_bit) ? BIT5 : BIT4;
BIT5: state <= (rx_rc_bit) ? BIT6 : BIT5;
BIT6: state <= (rx_rc_bit) ? BIT7 : BIT6;
BIT7: state <= (rx_rc_bit) ? STOP : BIT7;
STOP: state <= (rx_rc_bit) ? IDLE : STOP;
default: state <= 4'bxxxx;
endcase
end
else state <= state;
end
wire read_value = (uart_tick_16 & rx_rc_bit & (state != IDLE) & (state != STOP));
always @ (posedge clock) begin
rx_data <= (read_value) ? {rx_bit, rx_data[7:1]} : rx_data[7:0];
end
assign ready = (uart_tick_16 & rx_rc_bit & (state == STOP));
endmodule | 0 |
2,747 | data/full_repos/permissive/100975158/MIPS32_Full/UART/TX.v | 100,975,158 | TX.v | v | 89 | 76 | [] | [] | [] | [(3, 88)] | null | data/verilator_xmls/d2c859a6-59a4-4083-93dc-95805fcea3d8.xml | null | 184 | module | module TX (
input clock,
input reset,
input uart_tick,
input tx_start,
input [7:0] tx_data,
output ready,
output reg tx_signal,
output [7:0] debug_data
);
localparam [3:0] IDLE = 0;
localparam [3:0] STRT = 1;
localparam [3:0] BIT0 = 2;
localparam [3:0] BIT1 = 3;
localparam [3:0] BIT2 = 4;
localparam [3:0] BIT3 = 5;
localparam [3:0] BIT4 = 6;
localparam [3:0] BIT5 = 7;
localparam [3:0] BIT6 = 8;
localparam [3:0] BIT7 = 9;
localparam [3:0] STOP = 10;
reg [7:0] write_data = 8'd2;
reg [3:0] state = IDLE;
assign ready = (state == IDLE) || (state == STOP);
always @ (posedge clock) begin
if (ready & tx_start)
write_data <= tx_data;
end
assign debug_data = tx_data;
always @ (posedge clock) begin
if (reset)
state <= IDLE;
else begin
case (state)
IDLE : state <= (tx_start) ? STRT : IDLE;
STRT : state <= (uart_tick) ? BIT0 : STRT;
BIT0 : state <= (uart_tick) ? BIT1 : BIT0;
BIT1 : state <= (uart_tick) ? BIT2 : BIT1;
BIT2 : state <= (uart_tick) ? BIT3 : BIT2;
BIT3 : state <= (uart_tick) ? BIT4 : BIT3;
BIT4 : state <= (uart_tick) ? BIT5 : BIT4;
BIT5 : state <= (uart_tick) ? BIT6 : BIT5;
BIT6 : state <= (uart_tick) ? BIT7 : BIT6;
BIT7 : state <= (uart_tick) ? STOP : BIT7;
STOP : if (uart_tick) state <= (tx_start) ? STRT : IDLE;
default: state <= 4'bxxxx;
endcase
end
end
always @ (state, write_data) begin
case (state)
IDLE: tx_signal <= 1;
STRT: tx_signal <= 0;
BIT0: tx_signal <= write_data[0];
BIT1: tx_signal <= write_data[1];
BIT2: tx_signal <= write_data[2];
BIT3: tx_signal <= write_data[3];
BIT4: tx_signal <= write_data[4];
BIT5: tx_signal <= write_data[5];
BIT6: tx_signal <= write_data[6];
BIT7: tx_signal <= write_data[7];
STOP: tx_signal <= 1;
default: tx_signal <= 1'bx;
endcase
end
endmodule | module TX (
input clock,
input reset,
input uart_tick,
input tx_start,
input [7:0] tx_data,
output ready,
output reg tx_signal,
output [7:0] debug_data
); |
localparam [3:0] IDLE = 0;
localparam [3:0] STRT = 1;
localparam [3:0] BIT0 = 2;
localparam [3:0] BIT1 = 3;
localparam [3:0] BIT2 = 4;
localparam [3:0] BIT3 = 5;
localparam [3:0] BIT4 = 6;
localparam [3:0] BIT5 = 7;
localparam [3:0] BIT6 = 8;
localparam [3:0] BIT7 = 9;
localparam [3:0] STOP = 10;
reg [7:0] write_data = 8'd2;
reg [3:0] state = IDLE;
assign ready = (state == IDLE) || (state == STOP);
always @ (posedge clock) begin
if (ready & tx_start)
write_data <= tx_data;
end
assign debug_data = tx_data;
always @ (posedge clock) begin
if (reset)
state <= IDLE;
else begin
case (state)
IDLE : state <= (tx_start) ? STRT : IDLE;
STRT : state <= (uart_tick) ? BIT0 : STRT;
BIT0 : state <= (uart_tick) ? BIT1 : BIT0;
BIT1 : state <= (uart_tick) ? BIT2 : BIT1;
BIT2 : state <= (uart_tick) ? BIT3 : BIT2;
BIT3 : state <= (uart_tick) ? BIT4 : BIT3;
BIT4 : state <= (uart_tick) ? BIT5 : BIT4;
BIT5 : state <= (uart_tick) ? BIT6 : BIT5;
BIT6 : state <= (uart_tick) ? BIT7 : BIT6;
BIT7 : state <= (uart_tick) ? STOP : BIT7;
STOP : if (uart_tick) state <= (tx_start) ? STRT : IDLE;
default: state <= 4'bxxxx;
endcase
end
end
always @ (state, write_data) begin
case (state)
IDLE: tx_signal <= 1;
STRT: tx_signal <= 0;
BIT0: tx_signal <= write_data[0];
BIT1: tx_signal <= write_data[1];
BIT2: tx_signal <= write_data[2];
BIT3: tx_signal <= write_data[3];
BIT4: tx_signal <= write_data[4];
BIT5: tx_signal <= write_data[5];
BIT6: tx_signal <= write_data[6];
BIT7: tx_signal <= write_data[7];
STOP: tx_signal <= 1;
default: tx_signal <= 1'bx;
endcase
end
endmodule | 0 |
2,748 | data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v | 100,975,158 | UART.v | v | 109 | 61 | [] | [] | [] | [(4, 108)] | null | null | 1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:39: Cannot find file containing module: 'UART_Clock_Generator'\n UART_Clock_Generator UART_Clock (\n ^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator\n data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator.v\n data/full_repos/permissive/100975158/MIPS32_Full/UART,data/full_repos/permissive/100975158/UART_Clock_Generator.sv\n UART_Clock_Generator\n UART_Clock_Generator.v\n UART_Clock_Generator.sv\n obj_dir/UART_Clock_Generator\n obj_dir/UART_Clock_Generator.v\n obj_dir/UART_Clock_Generator.sv\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:66: Cannot find file containing module: 'RX'\n RX RX_O_Rato (\n ^~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:75: Cannot find file containing module: 'FIFO_Structure'\n FIFO_Structure RX_Buffer (\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:86: Cannot find file containing module: 'FIFO_Structure_Ahead'\n FIFO_Structure_Ahead TX_Buffer (\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART.v:97: Cannot find file containing module: 'TX'\n TX TX_O_Rato (\n ^~\n%Error: Exiting due to 5 error(s)\n" | 185 | module | module UART (
input clock,
input reset,
input rx,
output tx,
input write,
input [7:0] data_write,
input read,
output [7:0] data_read,
output data_ready,
output uart_clock,
output uart_clock_16,
output [7:0] debug_data
);
wire uart_tick;
wire uart_tick_16;
wire tx_ready;
wire rx_ready;
reg tx_start = 0;
reg tx_fifo_read = 0;
wire tx_fifo_full;
wire tx_fifo_empty;
wire [7:0] tx_fifo_data;
wire [7:0] rx_data;
wire rx_fifo_full;
wire rx_fifo_empty;
UART_Clock_Generator UART_Clock (
.clock (clock),
.uart_tick (uart_tick),
.uart_tick_16 (uart_tick_16)
);
assign uart_clock = (uart_tick);
assign uart_clock_16 = (uart_tick_16);
assign data_ready = ~rx_fifo_empty;
always @ (posedge clock) begin
if (reset) begin
tx_start <= 0;
tx_fifo_read <= 0;
end
else begin
if (tx_ready & uart_tick & ~tx_fifo_empty) begin
tx_start <= 1;
tx_fifo_read <= 1;
end
else begin
tx_start <= 0;
tx_fifo_read <= 0;
end
end
end
RX RX_O_Rato (
.clock (clock),
.reset (reset),
.uart_tick_16 (uart_tick_16),
.rx_signal (rx),
.ready (rx_ready),
.rx_data (rx_data)
);
FIFO_Structure RX_Buffer (
.clock (clock),
.reset (reset),
.read (read),
.write (rx_ready),
.in_data (rx_data),
.full (rx_fifo_full),
.empty (rx_fifo_empty),
.out_data (data_read)
);
FIFO_Structure_Ahead TX_Buffer (
.clock (clock),
.reset (reset),
.read (tx_fifo_read),
.write (write),
.in_data (data_write),
.full (tx_fifo_full),
.empty (tx_fifo_empty),
.out_data (tx_fifo_data)
);
TX TX_O_Rato (
.clock (clock),
.reset (reset),
.uart_tick (uart_tick),
.tx_signal (tx),
.tx_start (tx_start),
.tx_data (tx_fifo_data),
.ready (tx_ready)
);
endmodule | module UART (
input clock,
input reset,
input rx,
output tx,
input write,
input [7:0] data_write,
input read,
output [7:0] data_read,
output data_ready,
output uart_clock,
output uart_clock_16,
output [7:0] debug_data
); |
wire uart_tick;
wire uart_tick_16;
wire tx_ready;
wire rx_ready;
reg tx_start = 0;
reg tx_fifo_read = 0;
wire tx_fifo_full;
wire tx_fifo_empty;
wire [7:0] tx_fifo_data;
wire [7:0] rx_data;
wire rx_fifo_full;
wire rx_fifo_empty;
UART_Clock_Generator UART_Clock (
.clock (clock),
.uart_tick (uart_tick),
.uart_tick_16 (uart_tick_16)
);
assign uart_clock = (uart_tick);
assign uart_clock_16 = (uart_tick_16);
assign data_ready = ~rx_fifo_empty;
always @ (posedge clock) begin
if (reset) begin
tx_start <= 0;
tx_fifo_read <= 0;
end
else begin
if (tx_ready & uart_tick & ~tx_fifo_empty) begin
tx_start <= 1;
tx_fifo_read <= 1;
end
else begin
tx_start <= 0;
tx_fifo_read <= 0;
end
end
end
RX RX_O_Rato (
.clock (clock),
.reset (reset),
.uart_tick_16 (uart_tick_16),
.rx_signal (rx),
.ready (rx_ready),
.rx_data (rx_data)
);
FIFO_Structure RX_Buffer (
.clock (clock),
.reset (reset),
.read (read),
.write (rx_ready),
.in_data (rx_data),
.full (rx_fifo_full),
.empty (rx_fifo_empty),
.out_data (data_read)
);
FIFO_Structure_Ahead TX_Buffer (
.clock (clock),
.reset (reset),
.read (tx_fifo_read),
.write (write),
.in_data (data_write),
.full (tx_fifo_full),
.empty (tx_fifo_empty),
.out_data (tx_fifo_data)
);
TX TX_O_Rato (
.clock (clock),
.reset (reset),
.uart_tick (uart_tick),
.tx_signal (tx),
.tx_start (tx_start),
.tx_data (tx_fifo_data),
.ready (tx_ready)
);
endmodule | 0 |
2,749 | data/full_repos/permissive/100975158/MIPS32_Full/UART/UART_Clock_Generator.v | 100,975,158 | UART_Clock_Generator.v | v | 26 | 67 | [] | [] | [] | [(3, 25)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/MIPS32_Full/UART/UART_Clock_Generator.v:22: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'uart_tick_16\' generates 1 bits.\n : ... In instance UART_Clock_Generator\n assign uart_tick = (uart_tick_16 == 4\'d1 && counter == 4\'d15);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 186 | module | module UART_Clock_Generator (
input clock,
output uart_tick,
output uart_tick_16
);
reg [12:0] accumulator = 13'd0;
always @ (posedge clock) begin
accumulator <= accumulator[11:0] + 12'd151;
end
assign uart_tick_16 = (accumulator[12]);
reg [3:0] counter = 4'd0;
always @ (posedge clock) begin
counter <= (uart_tick_16) ? counter + 1'b1 : counter;
end
assign uart_tick = (uart_tick_16 == 4'd1 && counter == 4'd15);
endmodule | module UART_Clock_Generator (
input clock,
output uart_tick,
output uart_tick_16
); |
reg [12:0] accumulator = 13'd0;
always @ (posedge clock) begin
accumulator <= accumulator[11:0] + 12'd151;
end
assign uart_tick_16 = (accumulator[12]);
reg [3:0] counter = 4'd0;
always @ (posedge clock) begin
counter <= (uart_tick_16) ? counter + 1'b1 : counter;
end
assign uart_tick = (uart_tick_16 == 4'd1 && counter == 4'd15);
endmodule | 0 |
2,750 | data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure.v | 100,975,158 | FIFO_Structure.v | v | 36 | 48 | [] | [] | [] | [(3, 35)] | null | null | 1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure.v:16: Cannot find file containing module: 'scfifo'\n scfifo #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/scfifo\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/scfifo.v\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/scfifo.sv\n scfifo\n scfifo.v\n scfifo.sv\n obj_dir/scfifo\n obj_dir/scfifo.v\n obj_dir/scfifo.sv\n%Error: Exiting due to 1 error(s)\n" | 187 | module | module FIFO_Structure (
input clock,
input write,
input read,
input [7:0] in_data,
input reset,
output full,
output empty,
output [7:0] out_data
);
scfifo #(
.intended_device_family ("Cyclone IV"),
.lpm_type ("scfifo"),
.lpm_width (8),
.lpm_numwords (16),
.lpm_showahead ("OFF"),
.overflow_checking ("ON"),
.underflow_checking ("ON")
) FIFO (
.clock (clock),
.data (in_data),
.wrreq (write),
.rdreq (read),
.q (out_data),
.empty (empty),
.full (full),
.aclr (reset)
);
endmodule | module FIFO_Structure (
input clock,
input write,
input read,
input [7:0] in_data,
input reset,
output full,
output empty,
output [7:0] out_data
); |
scfifo #(
.intended_device_family ("Cyclone IV"),
.lpm_type ("scfifo"),
.lpm_width (8),
.lpm_numwords (16),
.lpm_showahead ("OFF"),
.overflow_checking ("ON"),
.underflow_checking ("ON")
) FIFO (
.clock (clock),
.data (in_data),
.wrreq (write),
.rdreq (read),
.q (out_data),
.empty (empty),
.full (full),
.aclr (reset)
);
endmodule | 0 |
2,751 | data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure_Ahead.v | 100,975,158 | FIFO_Structure_Ahead.v | v | 38 | 48 | [] | [] | [] | [(3, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/100975158/MIPS32_Full/Util/FIFO_Structure_Ahead.v:16: Cannot find file containing module: 'dcfifo'\n dcfifo #(\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo.v\n data/full_repos/permissive/100975158/MIPS32_Full/Util,data/full_repos/permissive/100975158/dcfifo.sv\n dcfifo\n dcfifo.v\n dcfifo.sv\n obj_dir/dcfifo\n obj_dir/dcfifo.v\n obj_dir/dcfifo.sv\n%Error: Exiting due to 1 error(s)\n" | 188 | module | module FIFO_Structure_Ahead (
input clock,
input write,
input read,
input [7:0] in_data,
input reset,
output full,
output empty,
output [7:0] out_data
);
dcfifo #(
.intended_device_family ("Cyclone IV"),
.lpm_type ("dcfifo"),
.lpm_width (8),
.lpm_numwords (16),
.lpm_showahead ("ON"),
.overflow_checking ("ON"),
.underflow_checking ("ON"),
.clocks_are_synchronized("TRUE")
) FIFO (
.rdclk (clock),
.wrclk (clock),
.data (in_data),
.wrreq (write),
.rdreq (read),
.q (out_data),
.rdempty (empty),
.wrfull (full),
.aclr (reset)
);
endmodule | module FIFO_Structure_Ahead (
input clock,
input write,
input read,
input [7:0] in_data,
input reset,
output full,
output empty,
output [7:0] out_data
); |
dcfifo #(
.intended_device_family ("Cyclone IV"),
.lpm_type ("dcfifo"),
.lpm_width (8),
.lpm_numwords (16),
.lpm_showahead ("ON"),
.overflow_checking ("ON"),
.underflow_checking ("ON"),
.clocks_are_synchronized("TRUE")
) FIFO (
.rdclk (clock),
.wrclk (clock),
.data (in_data),
.wrreq (write),
.rdreq (read),
.q (out_data),
.rdempty (empty),
.wrfull (full),
.aclr (reset)
);
endmodule | 0 |
2,752 | data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v | 100,975,158 | ALU.v | v | 55 | 111 | [] | [] | [] | [(1, 54)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:21: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n : ... In instance ALU\n saida = rs & rt;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:21: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n : ... In instance ALU\n saida = rs & rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:23: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n : ... In instance ALU\n saida = rs | rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:23: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n : ... In instance ALU\n saida = rs | rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:25: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n : ... In instance ALU\n saida = rs + rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:25: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n : ... In instance ALU\n saida = rs + rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:29: Operator DIV expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n : ... In instance ALU\n saida = rs / rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:29: Operator DIV expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n : ... In instance ALU\n saida = rs / rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:31: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'rs\' generates 32 bits.\n : ... In instance ALU\n saida = rs - rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:31: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'rt\' generates 32 bits.\n : ... In instance ALU\n saida = rs - rt;\n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:33: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n : ... In instance ALU\n saida = (rs < rt); \n ^\n%Warning-WIDTH: data/full_repos/permissive/100975158/ProcessadorQuartus/ALU.v:43: Operator EQ expects 64 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance ALU\n if(saida == 1\'b0)\n ^~\n%Error: Exiting due to 12 warning(s)\n' | 189 | module | module ALU(input[31:0] rs, rt, input[2:0] sinalOperacao,output[31:0] resultado, output zero, overflow);
reg [63:0] saida;
reg over, tzero;
always @ *
case (sinalOperacao)
3'b000:
saida = rs & rt;
3'b001:
saida = rs | rt;
3'b010:
saida = rs + rt;
3'b011:
saida = rs * rt;
3'b100:
saida = rs / rt;
3'b110:
saida = rs - rt;
3'b111:
saida = (rs < rt);
endcase
always @ ( * ) begin
if(saida[63:32] > 32'b0)
over = 1'b1;
else
over = 1'b0;
if(saida == 1'b0)
tzero = 1'b1;
else
tzero = 1'b0;
end
assign resultado = saida[31:0];
assign overflow = over;
assign zero = tzero;
endmodule | module ALU(input[31:0] rs, rt, input[2:0] sinalOperacao,output[31:0] resultado, output zero, overflow); |
reg [63:0] saida;
reg over, tzero;
always @ *
case (sinalOperacao)
3'b000:
saida = rs & rt;
3'b001:
saida = rs | rt;
3'b010:
saida = rs + rt;
3'b011:
saida = rs * rt;
3'b100:
saida = rs / rt;
3'b110:
saida = rs - rt;
3'b111:
saida = (rs < rt);
endcase
always @ ( * ) begin
if(saida[63:32] > 32'b0)
over = 1'b1;
else
over = 1'b0;
if(saida == 1'b0)
tzero = 1'b1;
else
tzero = 1'b0;
end
assign resultado = saida[31:0];
assign overflow = over;
assign zero = tzero;
endmodule | 0 |
2,753 | data/full_repos/permissive/100975158/ProcessadorQuartus/BancoDeRegistradores.v | 100,975,158 | BancoDeRegistradores.v | v | 34 | 56 | [] | [] | [] | [(1, 33)] | null | data/verilator_xmls/e93e45c8-b509-48b2-94fd-70c1fb5fd5fa.xml | null | 190 | module | module BancoDeRegistradores(input sinal_escrita, clock,
input[4:0] rs, rt, reg_escrita,
input[31:0] dado_escrita,
output[31:0] out_rs, out_rt);
reg [31:0] registradores [0:31];
reg [31:0] dado1, dado2;
always @(*) begin
if (rs == 5'b00000)
dado1 <= 32'd0;
else if ((rs == reg_escrita) && sinal_escrita)
dado1 <= dado_escrita;
else
dado1 <= registradores[rs][31:0];
if (rt == 5'b00000)
dado2 <= 32'd0;
else if ((rt == reg_escrita) && sinal_escrita)
dado2 <= dado_escrita;
else
dado2 <= registradores[rt][31:0];
end
assign out_rs = dado1;
assign out_rt = dado2;
always @ (posedge clock) begin
if (sinal_escrita && reg_escrita != 5'd0)
registradores[reg_escrita] <= dado_escrita;
end
endmodule | module BancoDeRegistradores(input sinal_escrita, clock,
input[4:0] rs, rt, reg_escrita,
input[31:0] dado_escrita,
output[31:0] out_rs, out_rt); |
reg [31:0] registradores [0:31];
reg [31:0] dado1, dado2;
always @(*) begin
if (rs == 5'b00000)
dado1 <= 32'd0;
else if ((rs == reg_escrita) && sinal_escrita)
dado1 <= dado_escrita;
else
dado1 <= registradores[rs][31:0];
if (rt == 5'b00000)
dado2 <= 32'd0;
else if ((rt == reg_escrita) && sinal_escrita)
dado2 <= dado_escrita;
else
dado2 <= registradores[rt][31:0];
end
assign out_rs = dado1;
assign out_rt = dado2;
always @ (posedge clock) begin
if (sinal_escrita && reg_escrita != 5'd0)
registradores[reg_escrita] <= dado_escrita;
end
endmodule | 0 |
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