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2,242 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_135
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_135
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,243 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_139
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_139
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,244 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_143
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_143
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,245 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_147
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_147
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,246 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_151
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_151
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,247 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_155
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_155
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,248 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_159
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_159
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,249 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_35
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_35
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,250 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_39
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_39
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,251 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_43
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_43
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,252 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,253 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_51
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_51
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,254 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_55
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_55
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,255 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_59
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_59
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,256 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_63
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_63
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,257 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,258 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,259 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_75
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_75
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,260 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_79
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_79
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,261 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_83
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_83
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,262 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_87
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_87
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,263 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,264 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_95
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_95
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,265 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_99
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_99
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,266 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,267 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized10
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized10
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,268 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11
(u_wcnt_hcmp_q,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output u_wcnt_hcmp_q;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(u_wcnt_hcmp_q),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11
(u_wcnt_hcmp_q,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output u_wcnt_hcmp_q;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(u_wcnt_hcmp_q),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,269 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_188
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_188
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,270 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_196
(\iwcnt_reg[0] ,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output \iwcnt_reg[0] ;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire \iwcnt_reg[0] ;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(\iwcnt_reg[0] ),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_196
(\iwcnt_reg[0] ,
DOUT_O,
SRL_Q_O,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output \iwcnt_reg[0] ;
output DOUT_O;
input SRL_Q_O;
input [0:0]E;
input S_DCLK_O;
input [15:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [15:0]PROBES_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire \iwcnt_reg[0] ;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(\iwcnt_reg[0] ),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_Q_O),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(PROBES_I[14]),
.I3(PROBES_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,271 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12
(SRL_Q_O,
u_wcnt_lcmp_q,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output SRL_Q_O;
output u_wcnt_lcmp_q;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
(* async_reg = "true" *) wire u_wcnt_lcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({u_wcnt_lcmp_q,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12
(SRL_Q_O,
u_wcnt_lcmp_q,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output SRL_Q_O;
output u_wcnt_lcmp_q;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
(* async_reg = "true" *) wire u_wcnt_lcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({u_wcnt_lcmp_q,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,272 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_189
(SRL_Q_O,
u_wcnt_hcmp_q,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output SRL_Q_O;
output u_wcnt_hcmp_q;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
(* async_reg = "true" *) wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({u_wcnt_hcmp_q,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_189
(SRL_Q_O,
u_wcnt_hcmp_q,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output SRL_Q_O;
output u_wcnt_hcmp_q;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
(* async_reg = "true" *) wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({u_wcnt_hcmp_q,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,273 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_197
(SRL_Q_O,
DOUT_O,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_197
(SRL_Q_O,
DOUT_O,
SRL_D_I,
E,
S_DCLK_O,
PROBES_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]E;
input S_DCLK_O;
input [13:0]PROBES_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [0:0]E;
wire [13:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire [3:0]sel;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[0]),
.I1(PROBES_I[1]),
.I2(PROBES_I[2]),
.I3(PROBES_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[4]),
.I1(PROBES_I[5]),
.I2(PROBES_I[6]),
.I3(PROBES_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[8]),
.I1(PROBES_I[9]),
.I2(PROBES_I[10]),
.I3(PROBES_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(E),
.CLK(S_DCLK_O),
.I0(PROBES_I[12]),
.I1(PROBES_I[13]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,274 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,275 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized3
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized3
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,276 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized4
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized4
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,277 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized5
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized5
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,278 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized6
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized6
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,279 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized7
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized7
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,280 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized8
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized8
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,281 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized9
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk);
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized9
(srl_q_0,
out,
mu_config_cs_serial_output,
mu_config_cs_shift_en,
s_dclk_o,
all_dly1,
all_dly2,
CO,
Q,
clk); |
output srl_q_0;
output out;
input [0:0]mu_config_cs_serial_output;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]CO;
input [0:0]Q;
input clk;
wire [0:0]CO;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire s_dclk_o;
wire [3:0]sel;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CO),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(srl_q_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(all_dly1),
.I1(all_dly2),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(mu_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,282 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA
(\parallel_dout_reg[15] ,
Q,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
\reset_out_reg[3] ,
clk);
output [0:0]\parallel_dout_reg[15] ;
output [9:0]Q;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(clk),
.CE(1'b1),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(clk),
.CE(1'b1),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(clk),
.CE(1'b1),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(clk),
.CE(1'b1),
.D(D[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(clk),
.CE(1'b1),
.D(D[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(clk),
.CE(1'b1),
.D(D[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(clk),
.CE(1'b1),
.D(D[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(clk),
.CE(1'b1),
.D(D[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(clk),
.CE(1'b1),
.D(D[9]),
.Q(Q[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA
(\parallel_dout_reg[15] ,
Q,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
\reset_out_reg[3] ,
clk); |
output [0:0]\parallel_dout_reg[15] ;
output [9:0]Q;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(clk),
.CE(1'b1),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(clk),
.CE(1'b1),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(clk),
.CE(1'b1),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(clk),
.CE(1'b1),
.D(D[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(clk),
.CE(1'b1),
.D(D[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(clk),
.CE(1'b1),
.D(D[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(clk),
.CE(1'b1),
.D(D[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(clk),
.CE(1'b1),
.D(D[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(clk),
.CE(1'b1),
.D(D[9]),
.Q(Q[9]),
.R(1'b0));
endmodule | 8 |
2,283 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_100
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_101 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_100
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_101 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,284 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_104
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_105 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_104
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_105 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,285 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_108
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_109 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_108
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_109 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,286 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_112
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_113 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_112
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_113 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,287 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_116
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_117 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_116
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_117 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,288 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_120
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_121 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_120
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_121 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,289 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_124
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_125 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_124
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_125 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,290 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_128
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_129 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_128
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_129 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,291 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_132
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_133 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_132
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_133 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,292 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_136
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_137 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_136
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_137 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,293 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_140
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_141 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_140
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_141 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,294 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_144
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_145 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_144
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_145 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,295 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_148
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_149 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_148
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_149 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,296 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_152
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_153 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_152
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_153 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,297 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_156
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_157 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_156
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_157 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,298 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_32
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_33 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_32
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_33 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,299 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_36
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_37 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_36
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_37 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,300 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_40
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_41 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_40
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_41 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,301 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_44
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_45 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_44
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_45 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,302 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_48
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_49 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_48
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_49 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,303 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_52
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_53 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_52
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_53 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,304 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_56
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_57 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_56
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_57 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,305 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_60
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_61 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_60
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_61 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,306 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_64
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_65 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_64
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_65 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,307 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_68
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_69 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_68
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_69 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,308 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_72
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_73 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_72
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_73 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,309 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_76
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_77 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_76
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_77 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,310 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_80
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_81 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_80
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_81 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,311 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_84
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_85 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_84
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_85 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,312 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_88
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_89 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_88
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_89 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,313 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_92
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_93 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_92
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_93 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,314 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_96
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_97 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_96
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_97 DUT
(.D(D),
.Q(Q),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule | 8 |
2,315 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | 8 |
2,316 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,317 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized2
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized2 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized2
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized2 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | 8 |
2,318 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized3
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized3 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized3
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized3 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,319 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized4
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized4 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized4
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized4 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | 8 |
2,320 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized5
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized5 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized5
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized5 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,321 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized6
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized6 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized6
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized6 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | 8 |
2,322 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized7
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized7 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized7
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized7 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,323 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized8
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized8 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized8
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
clk,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input clk;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized8 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0]
(.C(clk),
.CE(1'b1),
.D(all_dly1),
.Q(all_dly2),
.R(1'b0));
FDRE \probeDelay1_reg[0]
(.C(clk),
.CE(1'b1),
.D(probe_data),
.Q(all_dly1),
.R(1'b0));
endmodule | 8 |
2,324 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized9
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized9 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized9
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized9 DUT
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,325 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay
(Q,
SRL_Q_O,
u_wcnt_lcmp_q,
PROBES_I,
out,
E,
S_DCLK_O,
SRL_D_I);
output [14:0]Q;
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [14:0]PROBES_I;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [0:0]E;
wire [14:0]PROBES_I;
wire [14:0]Q;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
wire u_wcnt_lcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10 DUT
(.E(E),
.PROBES_I({Q[14],PROBES_I[14],Q[13],PROBES_I[13],Q[12],PROBES_I[12],Q[11],PROBES_I[11],Q[10],PROBES_I[10],Q[9],PROBES_I[9],Q[8],PROBES_I[8],Q[7],PROBES_I[7],Q[6],PROBES_I[6],Q[5],PROBES_I[5],Q[4],PROBES_I[4],Q[3],PROBES_I[3],Q[2],PROBES_I[2],Q[1],PROBES_I[1],Q[0],PROBES_I[0]}),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
FDRE \probeDelay1_reg[0]
(.C(out),
.CE(1'b1),
.D(PROBES_I[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \probeDelay1_reg[10]
(.C(out),
.CE(1'b1),
.D(PROBES_I[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \probeDelay1_reg[11]
(.C(out),
.CE(1'b1),
.D(PROBES_I[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \probeDelay1_reg[12]
(.C(out),
.CE(1'b1),
.D(PROBES_I[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \probeDelay1_reg[13]
(.C(out),
.CE(1'b1),
.D(PROBES_I[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \probeDelay1_reg[14]
(.C(out),
.CE(1'b1),
.D(PROBES_I[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(out),
.CE(1'b1),
.D(PROBES_I[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(out),
.CE(1'b1),
.D(PROBES_I[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(out),
.CE(1'b1),
.D(PROBES_I[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(out),
.CE(1'b1),
.D(PROBES_I[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(out),
.CE(1'b1),
.D(PROBES_I[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(out),
.CE(1'b1),
.D(PROBES_I[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(out),
.CE(1'b1),
.D(PROBES_I[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(out),
.CE(1'b1),
.D(PROBES_I[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(out),
.CE(1'b1),
.D(PROBES_I[9]),
.Q(Q[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay
(Q,
SRL_Q_O,
u_wcnt_lcmp_q,
PROBES_I,
out,
E,
S_DCLK_O,
SRL_D_I); |
output [14:0]Q;
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [14:0]PROBES_I;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [0:0]E;
wire [14:0]PROBES_I;
wire [14:0]Q;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
wire u_wcnt_lcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10 DUT
(.E(E),
.PROBES_I({Q[14],PROBES_I[14],Q[13],PROBES_I[13],Q[12],PROBES_I[12],Q[11],PROBES_I[11],Q[10],PROBES_I[10],Q[9],PROBES_I[9],Q[8],PROBES_I[8],Q[7],PROBES_I[7],Q[6],PROBES_I[6],Q[5],PROBES_I[5],Q[4],PROBES_I[4],Q[3],PROBES_I[3],Q[2],PROBES_I[2],Q[1],PROBES_I[1],Q[0],PROBES_I[0]}),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
FDRE \probeDelay1_reg[0]
(.C(out),
.CE(1'b1),
.D(PROBES_I[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \probeDelay1_reg[10]
(.C(out),
.CE(1'b1),
.D(PROBES_I[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \probeDelay1_reg[11]
(.C(out),
.CE(1'b1),
.D(PROBES_I[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \probeDelay1_reg[12]
(.C(out),
.CE(1'b1),
.D(PROBES_I[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \probeDelay1_reg[13]
(.C(out),
.CE(1'b1),
.D(PROBES_I[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \probeDelay1_reg[14]
(.C(out),
.CE(1'b1),
.D(PROBES_I[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(out),
.CE(1'b1),
.D(PROBES_I[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(out),
.CE(1'b1),
.D(PROBES_I[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(out),
.CE(1'b1),
.D(PROBES_I[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(out),
.CE(1'b1),
.D(PROBES_I[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(out),
.CE(1'b1),
.D(PROBES_I[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(out),
.CE(1'b1),
.D(PROBES_I[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(out),
.CE(1'b1),
.D(PROBES_I[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(out),
.CE(1'b1),
.D(PROBES_I[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(out),
.CE(1'b1),
.D(PROBES_I[9]),
.Q(Q[9]),
.R(1'b0));
endmodule | 8 |
2,326 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_186
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I);
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire u_wcnt_hcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_187 DUT
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I(PROBES_I),
.SRL_D_I(SRL_D_I),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_186
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I); |
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire u_wcnt_hcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_187 DUT
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I(PROBES_I),
.SRL_D_I(SRL_D_I),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
endmodule | 8 |
2,327 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_194
(SRL_Q_O,
DOUT_O,
D,
out,
E,
S_DCLK_O,
SRL_D_I);
output SRL_Q_O;
output DOUT_O;
input [14:0]D;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire [29:1]all_in;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_195 DUT
(.DOUT_O(DOUT_O),
.E(E),
.PROBES_I({all_in[29],D[14],all_in[27],D[13],all_in[25],D[12],all_in[23],D[11],all_in[21],D[10],all_in[19],D[9],all_in[17],D[8],all_in[15],D[7],all_in[13],D[6],all_in[11],D[5],all_in[9],D[4],all_in[7],D[3],all_in[5],D[2],all_in[3],D[1],all_in[1],D[0]}),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O));
FDRE \probeDelay1_reg[0]
(.C(out),
.CE(1'b1),
.D(D[0]),
.Q(all_in[1]),
.R(1'b0));
FDRE \probeDelay1_reg[10]
(.C(out),
.CE(1'b1),
.D(D[10]),
.Q(all_in[21]),
.R(1'b0));
FDRE \probeDelay1_reg[11]
(.C(out),
.CE(1'b1),
.D(D[11]),
.Q(all_in[23]),
.R(1'b0));
FDRE \probeDelay1_reg[12]
(.C(out),
.CE(1'b1),
.D(D[12]),
.Q(all_in[25]),
.R(1'b0));
FDRE \probeDelay1_reg[13]
(.C(out),
.CE(1'b1),
.D(D[13]),
.Q(all_in[27]),
.R(1'b0));
FDRE \probeDelay1_reg[14]
(.C(out),
.CE(1'b1),
.D(D[14]),
.Q(all_in[29]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(out),
.CE(1'b1),
.D(D[1]),
.Q(all_in[3]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(out),
.CE(1'b1),
.D(D[2]),
.Q(all_in[5]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(out),
.CE(1'b1),
.D(D[3]),
.Q(all_in[7]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(out),
.CE(1'b1),
.D(D[4]),
.Q(all_in[9]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(out),
.CE(1'b1),
.D(D[5]),
.Q(all_in[11]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(out),
.CE(1'b1),
.D(D[6]),
.Q(all_in[13]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(out),
.CE(1'b1),
.D(D[7]),
.Q(all_in[15]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(out),
.CE(1'b1),
.D(D[8]),
.Q(all_in[17]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(out),
.CE(1'b1),
.D(D[9]),
.Q(all_in[19]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_194
(SRL_Q_O,
DOUT_O,
D,
out,
E,
S_DCLK_O,
SRL_D_I); |
output SRL_Q_O;
output DOUT_O;
input [14:0]D;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire [29:1]all_in;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_195 DUT
(.DOUT_O(DOUT_O),
.E(E),
.PROBES_I({all_in[29],D[14],all_in[27],D[13],all_in[25],D[12],all_in[23],D[11],all_in[21],D[10],all_in[19],D[9],all_in[17],D[8],all_in[15],D[7],all_in[13],D[6],all_in[11],D[5],all_in[9],D[4],all_in[7],D[3],all_in[5],D[2],all_in[3],D[1],all_in[1],D[0]}),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O));
FDRE \probeDelay1_reg[0]
(.C(out),
.CE(1'b1),
.D(D[0]),
.Q(all_in[1]),
.R(1'b0));
FDRE \probeDelay1_reg[10]
(.C(out),
.CE(1'b1),
.D(D[10]),
.Q(all_in[21]),
.R(1'b0));
FDRE \probeDelay1_reg[11]
(.C(out),
.CE(1'b1),
.D(D[11]),
.Q(all_in[23]),
.R(1'b0));
FDRE \probeDelay1_reg[12]
(.C(out),
.CE(1'b1),
.D(D[12]),
.Q(all_in[25]),
.R(1'b0));
FDRE \probeDelay1_reg[13]
(.C(out),
.CE(1'b1),
.D(D[13]),
.Q(all_in[27]),
.R(1'b0));
FDRE \probeDelay1_reg[14]
(.C(out),
.CE(1'b1),
.D(D[14]),
.Q(all_in[29]),
.R(1'b0));
FDRE \probeDelay1_reg[1]
(.C(out),
.CE(1'b1),
.D(D[1]),
.Q(all_in[3]),
.R(1'b0));
FDRE \probeDelay1_reg[2]
(.C(out),
.CE(1'b1),
.D(D[2]),
.Q(all_in[5]),
.R(1'b0));
FDRE \probeDelay1_reg[3]
(.C(out),
.CE(1'b1),
.D(D[3]),
.Q(all_in[7]),
.R(1'b0));
FDRE \probeDelay1_reg[4]
(.C(out),
.CE(1'b1),
.D(D[4]),
.Q(all_in[9]),
.R(1'b0));
FDRE \probeDelay1_reg[5]
(.C(out),
.CE(1'b1),
.D(D[5]),
.Q(all_in[11]),
.R(1'b0));
FDRE \probeDelay1_reg[6]
(.C(out),
.CE(1'b1),
.D(D[6]),
.Q(all_in[13]),
.R(1'b0));
FDRE \probeDelay1_reg[7]
(.C(out),
.CE(1'b1),
.D(D[7]),
.Q(all_in[15]),
.R(1'b0));
FDRE \probeDelay1_reg[8]
(.C(out),
.CE(1'b1),
.D(D[8]),
.Q(all_in[17]),
.R(1'b0));
FDRE \probeDelay1_reg[9]
(.C(out),
.CE(1'b1),
.D(D[9]),
.Q(all_in[19]),
.R(1'b0));
endmodule | 8 |
2,328 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer
(out,
\dout_pulse_reg[0] ,
clk,
s_dclk_o,
last_din,
arm_ctrl);
output out;
output [0:0]\dout_pulse_reg[0] ;
input clk;
input s_dclk_o;
input last_din;
input arm_ctrl;
wire arm_ctrl;
wire clk;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__0_n_0;
wire [0:0]\dout_pulse_reg[0] ;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire last_din;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign out = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1__0
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(arm_ctrl),
.O(din_reg_i_1__0_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg_i_1__0_n_0),
.Q(din_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\dout_pulse[0]_i_1__0
(.I0(dout_reg1),
.I1(last_din),
.O(\dout_pulse_reg[0] ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(clk),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(clk),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer
(out,
\dout_pulse_reg[0] ,
clk,
s_dclk_o,
last_din,
arm_ctrl); |
output out;
output [0:0]\dout_pulse_reg[0] ;
input clk;
input s_dclk_o;
input last_din;
input arm_ctrl;
wire arm_ctrl;
wire clk;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__0_n_0;
wire [0:0]\dout_pulse_reg[0] ;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire last_din;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign out = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1__0
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(arm_ctrl),
.O(din_reg_i_1__0_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg_i_1__0_n_0),
.Q(din_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\dout_pulse[0]_i_1__0
(.I0(dout_reg1),
.I1(last_din),
.O(\dout_pulse_reg[0] ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(clk),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(clk),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | 8 |
2,329 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_160
(temp_reg0_reg_0,
\SEQUENCER_STATE_O_reg[8] ,
s_dclk_o,
out,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\current_state_reg[3] ,
Q);
output [0:0]temp_reg0_reg_0;
output \SEQUENCER_STATE_O_reg[8] ;
input s_dclk_o;
input out;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \current_state_reg[3] ;
input [0:0]Q;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire \SEQUENCER_STATE_O_reg[8] ;
wire \current_state_reg[3] ;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__1_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire out;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign temp_reg0_reg_0[0] = dout_reg1;
LUT3 #(
.INIT(8'h02))
\SEQUENCER_STATE_O[15]_i_1
(.I0(dout_reg1),
.I1(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.I2(\current_state_reg[3] ),
.O(\SEQUENCER_STATE_O_reg[8] ));
LUT4 #(
.INIT(16'h28EB))
din_reg_i_1__1
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(Q),
.O(din_reg_i_1__1_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(out),
.CE(1'b1),
.D(din_reg_i_1__1_n_0),
.Q(din_reg),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(out),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(out),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_160
(temp_reg0_reg_0,
\SEQUENCER_STATE_O_reg[8] ,
s_dclk_o,
out,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\current_state_reg[3] ,
Q); |
output [0:0]temp_reg0_reg_0;
output \SEQUENCER_STATE_O_reg[8] ;
input s_dclk_o;
input out;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \current_state_reg[3] ;
input [0:0]Q;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire \SEQUENCER_STATE_O_reg[8] ;
wire \current_state_reg[3] ;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__1_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire out;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign temp_reg0_reg_0[0] = dout_reg1;
LUT3 #(
.INIT(8'h02))
\SEQUENCER_STATE_O[15]_i_1
(.I0(dout_reg1),
.I1(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.I2(\current_state_reg[3] ),
.O(\SEQUENCER_STATE_O_reg[8] ));
LUT4 #(
.INIT(16'h28EB))
din_reg_i_1__1
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(Q),
.O(din_reg_i_1__1_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(out),
.CE(1'b1),
.D(din_reg_i_1__1_n_0),
.Q(din_reg),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(out),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(out),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | 8 |
2,330 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_161
(out,
D,
clk,
s_dclk_o,
last_din,
halt_ctrl);
output out;
output [0:0]D;
input clk;
input s_dclk_o;
input last_din;
input halt_ctrl;
wire [0:0]D;
wire clk;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire halt_ctrl;
wire last_din;
wire s_dclk_o;
wire temp_reg0;
wire temp_reg1;
assign out = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(halt_ctrl),
.O(din_reg_i_1_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg_i_1_n_0),
.Q(din_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\dout_pulse[0]_i_1
(.I0(dout_reg1),
.I1(last_din),
.O(D));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(clk),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(clk),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(temp_reg0),
.Q(temp_reg1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_161
(out,
D,
clk,
s_dclk_o,
last_din,
halt_ctrl); |
output out;
output [0:0]D;
input clk;
input s_dclk_o;
input last_din;
input halt_ctrl;
wire [0:0]D;
wire clk;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire halt_ctrl;
wire last_din;
wire s_dclk_o;
wire temp_reg0;
wire temp_reg1;
assign out = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(halt_ctrl),
.O(din_reg_i_1_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg_i_1_n_0),
.Q(din_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\dout_pulse[0]_i_1
(.I0(dout_reg1),
.I1(last_din),
.O(D));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(clk),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(clk),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(temp_reg0),
.Q(temp_reg1),
.R(1'b0));
endmodule | 8 |
2,331 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_162
(temp_reg0_reg_0,
s_dclk_o,
out,
halt_out);
output [0:0]temp_reg0_reg_0;
input s_dclk_o;
input out;
input halt_out;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__2_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire halt_out;
wire out;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign temp_reg0_reg_0[0] = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1__2
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(halt_out),
.O(din_reg_i_1__2_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(out),
.CE(1'b1),
.D(din_reg_i_1__2_n_0),
.Q(din_reg),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(out),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(out),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_162
(temp_reg0_reg_0,
s_dclk_o,
out,
halt_out); |
output [0:0]temp_reg0_reg_0;
input s_dclk_o;
input out;
input halt_out;
(* shreg_extract = "no" *) wire din_reg;
wire din_reg_i_1__2_n_0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg0;
(* async_reg = "true" *) (* shreg_extract = "no" *) wire dout_reg1;
wire halt_out;
wire out;
wire s_dclk_o;
wire temp_reg0_reg_n_0;
wire temp_reg1;
assign temp_reg0_reg_0[0] = dout_reg1;
LUT4 #(
.INIT(16'hEB28))
din_reg_i_1__2
(.I0(din_reg),
.I1(din_reg),
.I2(temp_reg1),
.I3(halt_out),
.O(din_reg_i_1__2_n_0));
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
din_reg_reg
(.C(out),
.CE(1'b1),
.D(din_reg_i_1__2_n_0),
.Q(din_reg),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg0_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(din_reg),
.Q(dout_reg0),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* SHREG_EXTRACT = "no" *)
FDRE #(
.INIT(1'b0))
dout_reg1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dout_reg0),
.Q(dout_reg1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg0_reg
(.C(out),
.CE(1'b1),
.D(dout_reg1),
.Q(temp_reg0_reg_n_0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
temp_reg1_reg
(.C(out),
.CE(1'b1),
.D(temp_reg0_reg_n_0),
.Q(temp_reg1),
.R(1'b0));
endmodule | 8 |
2,332 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4
(wcnt_ce,
cfg_data_0,
E,
SRL_Q_O,
A,
S_DCLK_O);
output wcnt_ce;
output cfg_data_0;
input [0:0]E;
input SRL_Q_O;
input [3:0]A;
input S_DCLK_O;
wire [3:0]A;
wire [0:0]E;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire wcnt_ce;
(* BOX_TYPE = "PRIMITIVE" *)
SRLC16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRLC16E
(.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(wcnt_ce),
.Q15(cfg_data_0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4
(wcnt_ce,
cfg_data_0,
E,
SRL_Q_O,
A,
S_DCLK_O); |
output wcnt_ce;
output cfg_data_0;
input [0:0]E;
input SRL_Q_O;
input [3:0]A;
input S_DCLK_O;
wire [3:0]A;
wire [0:0]E;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire wcnt_ce;
(* BOX_TYPE = "PRIMITIVE" *)
SRLC16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRLC16E
(.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(wcnt_ce),
.Q15(cfg_data_0));
endmodule | 8 |
2,333 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_190
(\iscnt_reg[14] ,
cfg_data_0,
E,
cfg_data_1,
A,
S_DCLK_O);
output \iscnt_reg[14] ;
output cfg_data_0;
input [0:0]E;
input cfg_data_1;
input [3:0]A;
input S_DCLK_O;
wire [3:0]A;
wire [0:0]E;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire \iscnt_reg[14] ;
(* BOX_TYPE = "PRIMITIVE" *)
SRLC16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRLC16E
(.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_1),
.Q(\iscnt_reg[14] ),
.Q15(cfg_data_0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_190
(\iscnt_reg[14] ,
cfg_data_0,
E,
cfg_data_1,
A,
S_DCLK_O); |
output \iscnt_reg[14] ;
output cfg_data_0;
input [0:0]E;
input cfg_data_1;
input [3:0]A;
input S_DCLK_O;
wire [3:0]A;
wire [0:0]E;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire \iscnt_reg[14] ;
(* BOX_TYPE = "PRIMITIVE" *)
SRLC16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRLC16E
(.A0(A[0]),
.A1(A[1]),
.A2(A[2]),
.A3(A[3]),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_1),
.Q(\iscnt_reg[14] ),
.Q15(cfg_data_0));
endmodule | 8 |
2,334 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5
(wcnt_hcmp_ce,
SRL_D_I,
E,
SRL_Q_O,
A,
S_DCLK_O);
output wcnt_hcmp_ce;
output SRL_D_I;
input [0:0]E;
input SRL_Q_O;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire wcnt_hcmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(wcnt_hcmp_ce),
.Q31(SRL_D_I));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5
(wcnt_hcmp_ce,
SRL_D_I,
E,
SRL_Q_O,
A,
S_DCLK_O); |
output wcnt_hcmp_ce;
output SRL_D_I;
input [0:0]E;
input SRL_Q_O;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire wcnt_hcmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(wcnt_hcmp_ce),
.Q31(SRL_D_I));
endmodule | 8 |
2,335 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_184
(wcnt_lcmp_ce,
SRL_D_I,
E,
cfg_data_0,
A,
S_DCLK_O);
output wcnt_lcmp_ce;
output SRL_D_I;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire S_DCLK_O;
wire cfg_data_0;
wire wcnt_lcmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(wcnt_lcmp_ce),
.Q31(SRL_D_I));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_184
(wcnt_lcmp_ce,
SRL_D_I,
E,
cfg_data_0,
A,
S_DCLK_O); |
output wcnt_lcmp_ce;
output SRL_D_I;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire S_DCLK_O;
wire cfg_data_0;
wire wcnt_lcmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(wcnt_lcmp_ce),
.Q31(SRL_D_I));
endmodule | 8 |
2,336 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_191
(scnt_cmp_ce,
cfg_data_1_0,
E,
cfg_data_0,
A,
S_DCLK_O);
output scnt_cmp_ce;
output cfg_data_1_0;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1_0;
wire scnt_cmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(scnt_cmp_ce),
.Q31(cfg_data_1_0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_191
(scnt_cmp_ce,
cfg_data_1_0,
E,
cfg_data_0,
A,
S_DCLK_O); |
output scnt_cmp_ce;
output cfg_data_1_0;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
wire [4:0]A;
wire [0:0]E;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1_0;
wire scnt_cmp_ce;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(scnt_cmp_ce),
.Q31(cfg_data_1_0));
endmodule | 8 |
2,337 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6
(cfg_data_1,
cmp_reset,
E,
cfg_data_0,
A,
S_DCLK_O,
u_scnt_cmp_q);
output cfg_data_1;
output cmp_reset;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
input [0:0]u_scnt_cmp_q;
wire [4:0]A;
wire [0:0]E;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cmp_reset;
wire [0:0]u_scnt_cmp_q;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(cfg_data_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
LUT3 #(
.INIT(8'hB8))
u_scnt_cmp_q_i_1
(.I0(SRL_Q_1),
.I1(u_scnt_cmp_q),
.I2(SRL_Q_0),
.O(cmp_reset));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6
(cfg_data_1,
cmp_reset,
E,
cfg_data_0,
A,
S_DCLK_O,
u_scnt_cmp_q); |
output cfg_data_1;
output cmp_reset;
input [0:0]E;
input cfg_data_0;
input [4:0]A;
input S_DCLK_O;
input [0:0]u_scnt_cmp_q;
wire [4:0]A;
wire [0:0]E;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cmp_reset;
wire [0:0]u_scnt_cmp_q;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(cfg_data_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
LUT3 #(
.INIT(8'hB8))
u_scnt_cmp_q_i_1
(.I0(SRL_Q_1),
.I1(u_scnt_cmp_q),
.I2(SRL_Q_0),
.O(cmp_reset));
endmodule | 8 |
2,338 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_192
(SRL_D_I,
\iscnt_reg[0] ,
E,
cfg_data_1_0,
A,
S_DCLK_O,
u_scnt_cmp_q);
output SRL_D_I;
output \iscnt_reg[0] ;
input [0:0]E;
input cfg_data_1_0;
input [4:0]A;
input S_DCLK_O;
input [0:0]u_scnt_cmp_q;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire S_DCLK_O;
wire cfg_data_1_0;
wire \iscnt_reg[0] ;
wire [0:0]u_scnt_cmp_q;
LUT3 #(
.INIT(8'hB8))
\G_COUNTER[0].U_COUNTER_i_1
(.I0(SRL_Q_1),
.I1(u_scnt_cmp_q),
.I2(SRL_Q_0),
.O(\iscnt_reg[0] ));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(SRL_D_I));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_1_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_192
(SRL_D_I,
\iscnt_reg[0] ,
E,
cfg_data_1_0,
A,
S_DCLK_O,
u_scnt_cmp_q); |
output SRL_D_I;
output \iscnt_reg[0] ;
input [0:0]E;
input cfg_data_1_0;
input [4:0]A;
input S_DCLK_O;
input [0:0]u_scnt_cmp_q;
wire [4:0]A;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire S_DCLK_O;
wire cfg_data_1_0;
wire \iscnt_reg[0] ;
wire [0:0]u_scnt_cmp_q;
LUT3 #(
.INIT(8'hB8))
\G_COUNTER[0].U_COUNTER_i_1
(.I0(SRL_Q_1),
.I1(u_scnt_cmp_q),
.I2(SRL_Q_0),
.O(\iscnt_reg[0] ));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(SRL_D_I));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_1_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
endmodule | 8 |
2,339 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0
(D,
CAP_DONE_O_reg,
E,
SRL_Q_O,
A,
S_DCLK_O,
out,
cap_done,
Q,
wcnt_hcmp);
output [0:0]D;
output CAP_DONE_O_reg;
input [0:0]E;
input SRL_Q_O;
input [4:0]A;
input S_DCLK_O;
input out;
input cap_done;
input [1:0]Q;
input wcnt_hcmp;
wire [4:0]A;
wire CAP_DONE_O_reg;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire SRL_MUX;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_O;
wire S_DCLK_O;
wire cap_done;
wire cap_done_i;
wire out;
wire wcnt_hcmp;
LUT4 #(
.INIT(16'hA0AE))
CAP_DONE_O_i_1
(.I0(cap_done),
.I1(cap_done_i),
.I2(Q[0]),
.I3(Q[1]),
.O(CAP_DONE_O_reg));
LUT3 #(
.INIT(8'hB8))
\I_YESLUT6.I_YES_OREG.O_reg_i_1
(.I0(SRL_Q_1),
.I1(wcnt_hcmp),
.I2(SRL_Q_0),
.O(SRL_MUX));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX),
.Q(cap_done_i),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(D));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0
(D,
CAP_DONE_O_reg,
E,
SRL_Q_O,
A,
S_DCLK_O,
out,
cap_done,
Q,
wcnt_hcmp); |
output [0:0]D;
output CAP_DONE_O_reg;
input [0:0]E;
input SRL_Q_O;
input [4:0]A;
input S_DCLK_O;
input out;
input cap_done;
input [1:0]Q;
input wcnt_hcmp;
wire [4:0]A;
wire CAP_DONE_O_reg;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire SRL_MUX;
wire SRL_Q31;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_O;
wire S_DCLK_O;
wire cap_done;
wire cap_done_i;
wire out;
wire wcnt_hcmp;
LUT4 #(
.INIT(16'hA0AE))
CAP_DONE_O_i_1
(.I0(cap_done),
.I1(cap_done_i),
.I2(Q[0]),
.I3(Q[1]),
.O(CAP_DONE_O_reg));
LUT3 #(
.INIT(8'hB8))
\I_YESLUT6.I_YES_OREG.O_reg_i_1
(.I0(SRL_Q_1),
.I1(wcnt_hcmp),
.I2(SRL_Q_0),
.O(SRL_MUX));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX),
.Q(cap_done_i),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31),
.Q(SRL_Q_1),
.Q31(D));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A(A),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q_O),
.Q(SRL_Q_0),
.Q31(SRL_Q31));
endmodule | 8 |
2,340 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7
(\xsdb_reg_reg[0] ,
D,
p_2_out,
trigger_reg,
E,
cfg_data_0,
A,
S_DCLK_O,
Q,
out,
u_wcnt_lcmp_q,
wcnt_hcmp,
dout_reg1_reg,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
trig_out_fsm);
output [0:0]\xsdb_reg_reg[0] ;
output [0:0]D;
output [0:0]p_2_out;
output trigger_reg;
input [0:0]E;
input cfg_data_0;
input [3:0]A;
input S_DCLK_O;
input [0:0]Q;
input out;
input [0:0]u_wcnt_lcmp_q;
input wcnt_hcmp;
input dout_reg1_reg;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
input trig_out_fsm;
wire [3:0]A;
wire [0:0]D;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
wire [0:0]Q;
wire SRL_MUX8_n_0;
wire SRL_Q31_0;
wire SRL_Q31_1;
wire SRL_Q31_2;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_2;
wire SRL_Q_3;
wire S_DCLK_O;
wire cap_done;
wire cfg_data_0;
wire dout_reg1_reg;
wire out;
wire [0:0]p_2_out;
wire trig_out_fsm;
wire trigger_reg;
wire [0:0]u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire [0:0]\xsdb_reg_reg[0] ;
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX8_n_0),
.Q(\xsdb_reg_reg[0] ),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_2),
.Q(SRL_Q_3),
.Q31(D));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_1),
.Q(SRL_Q_2),
.Q31(SRL_Q31_2));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_C
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_0),
.Q(SRL_Q_1),
.Q31(SRL_Q31_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_D
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31_0));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
SRL_MUX8
(.I0(SRL_Q_3),
.I1(SRL_Q_2),
.I2(SRL_Q_1),
.I3(u_wcnt_lcmp_q),
.I4(SRL_Q_0),
.I5(wcnt_hcmp),
.O(SRL_MUX8_n_0));
LUT2 #(
.INIT(4'h4))
\cntcmpsel[1]_i_2
(.I0(\xsdb_reg_reg[0] ),
.I1(dout_reg1_reg),
.O(p_2_out));
LUT6 #(
.INIT(64'hF000F00000100000))
trigger_i_1
(.I0(cap_done),
.I1(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I2(dout_reg1_reg),
.I3(\xsdb_reg_reg[0] ),
.I4(A[0]),
.I5(trig_out_fsm),
.O(trigger_reg));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7
(\xsdb_reg_reg[0] ,
D,
p_2_out,
trigger_reg,
E,
cfg_data_0,
A,
S_DCLK_O,
Q,
out,
u_wcnt_lcmp_q,
wcnt_hcmp,
dout_reg1_reg,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
trig_out_fsm); |
output [0:0]\xsdb_reg_reg[0] ;
output [0:0]D;
output [0:0]p_2_out;
output trigger_reg;
input [0:0]E;
input cfg_data_0;
input [3:0]A;
input S_DCLK_O;
input [0:0]Q;
input out;
input [0:0]u_wcnt_lcmp_q;
input wcnt_hcmp;
input dout_reg1_reg;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
input trig_out_fsm;
wire [3:0]A;
wire [0:0]D;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
wire [0:0]Q;
wire SRL_MUX8_n_0;
wire SRL_Q31_0;
wire SRL_Q31_1;
wire SRL_Q31_2;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_2;
wire SRL_Q_3;
wire S_DCLK_O;
wire cap_done;
wire cfg_data_0;
wire dout_reg1_reg;
wire out;
wire [0:0]p_2_out;
wire trig_out_fsm;
wire trigger_reg;
wire [0:0]u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire [0:0]\xsdb_reg_reg[0] ;
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX8_n_0),
.Q(\xsdb_reg_reg[0] ),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_2),
.Q(SRL_Q_3),
.Q31(D));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_1),
.Q(SRL_Q_2),
.Q31(SRL_Q31_2));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_C
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_0),
.Q(SRL_Q_1),
.Q31(SRL_Q31_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_D
(.A({A,\xsdb_reg_reg[0] }),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_0),
.Q(SRL_Q_0),
.Q31(SRL_Q31_0));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
SRL_MUX8
(.I0(SRL_Q_3),
.I1(SRL_Q_2),
.I2(SRL_Q_1),
.I3(u_wcnt_lcmp_q),
.I4(SRL_Q_0),
.I5(wcnt_hcmp),
.O(SRL_MUX8_n_0));
LUT2 #(
.INIT(4'h4))
\cntcmpsel[1]_i_2
(.I0(\xsdb_reg_reg[0] ),
.I1(dout_reg1_reg),
.O(p_2_out));
LUT6 #(
.INIT(64'hF000F00000100000))
trigger_i_1
(.I0(cap_done),
.I1(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I2(dout_reg1_reg),
.I3(\xsdb_reg_reg[0] ),
.I4(A[0]),
.I5(trig_out_fsm),
.O(trigger_reg));
endmodule | 8 |
2,341 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_183
(\xsdb_reg_reg[1] ,
cfg_data_0,
\current_state_reg[0] ,
\current_state_reg[0]_0 ,
itrigger_in,
E,
capture_ctrl_config_serial_output,
A,
u_wcnt_lcmp_q,
S_DCLK_O,
Q,
out,
wcnt_hcmp,
dout_reg1_reg,
trig_out_fsm,
en_adv_trigger,
basic_trigger);
output [0:0]\xsdb_reg_reg[1] ;
output cfg_data_0;
output \current_state_reg[0] ;
output \current_state_reg[0]_0 ;
output itrigger_in;
input [0:0]E;
input capture_ctrl_config_serial_output;
input [2:0]A;
input [1:0]u_wcnt_lcmp_q;
input S_DCLK_O;
input [0:0]Q;
input out;
input wcnt_hcmp;
input dout_reg1_reg;
input trig_out_fsm;
input en_adv_trigger;
input basic_trigger;
wire [2:0]A;
wire [0:0]E;
wire [0:0]Q;
wire SRL_MUX8__0;
wire SRL_Q31_0;
wire SRL_Q31_1;
wire SRL_Q31_2;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_2;
wire SRL_Q_3;
wire S_DCLK_O;
wire basic_trigger;
wire capture_ctrl_config_serial_output;
wire cfg_data_0;
wire \current_state_reg[0] ;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire en_adv_trigger;
wire itrigger_in;
wire out;
wire trig_out_fsm;
wire [1:0]u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire [0:0]\xsdb_reg_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h2))
\G_COUNTER[0].U_COUNTER_i_5
(.I0(\xsdb_reg_reg[1] ),
.I1(u_wcnt_lcmp_q[0]),
.O(\current_state_reg[0]_0 ));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX8__0),
.Q(\xsdb_reg_reg[1] ),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_2),
.Q(SRL_Q_3),
.Q31(cfg_data_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_1),
.Q(SRL_Q_2),
.Q31(SRL_Q31_2));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_C
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_0),
.Q(SRL_Q_1),
.Q31(SRL_Q31_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_D
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(capture_ctrl_config_serial_output),
.Q(SRL_Q_0),
.Q31(SRL_Q31_0));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
SRL_MUX8
(.I0(SRL_Q_3),
.I1(SRL_Q_2),
.I2(SRL_Q_1),
.I3(u_wcnt_lcmp_q[1]),
.I4(SRL_Q_0),
.I5(wcnt_hcmp),
.O(SRL_MUX8__0));
LUT3 #(
.INIT(8'h10))
\cntcmpsel[1]_i_1
(.I0(\xsdb_reg_reg[1] ),
.I1(u_wcnt_lcmp_q[0]),
.I2(dout_reg1_reg),
.O(\current_state_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h00008A80))
itrigger_out_i_1
(.I0(\xsdb_reg_reg[1] ),
.I1(trig_out_fsm),
.I2(en_adv_trigger),
.I3(basic_trigger),
.I4(u_wcnt_lcmp_q[0]),
.O(itrigger_in));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_183
(\xsdb_reg_reg[1] ,
cfg_data_0,
\current_state_reg[0] ,
\current_state_reg[0]_0 ,
itrigger_in,
E,
capture_ctrl_config_serial_output,
A,
u_wcnt_lcmp_q,
S_DCLK_O,
Q,
out,
wcnt_hcmp,
dout_reg1_reg,
trig_out_fsm,
en_adv_trigger,
basic_trigger); |
output [0:0]\xsdb_reg_reg[1] ;
output cfg_data_0;
output \current_state_reg[0] ;
output \current_state_reg[0]_0 ;
output itrigger_in;
input [0:0]E;
input capture_ctrl_config_serial_output;
input [2:0]A;
input [1:0]u_wcnt_lcmp_q;
input S_DCLK_O;
input [0:0]Q;
input out;
input wcnt_hcmp;
input dout_reg1_reg;
input trig_out_fsm;
input en_adv_trigger;
input basic_trigger;
wire [2:0]A;
wire [0:0]E;
wire [0:0]Q;
wire SRL_MUX8__0;
wire SRL_Q31_0;
wire SRL_Q31_1;
wire SRL_Q31_2;
wire SRL_Q_0;
wire SRL_Q_1;
wire SRL_Q_2;
wire SRL_Q_3;
wire S_DCLK_O;
wire basic_trigger;
wire capture_ctrl_config_serial_output;
wire cfg_data_0;
wire \current_state_reg[0] ;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire en_adv_trigger;
wire itrigger_in;
wire out;
wire trig_out_fsm;
wire [1:0]u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire [0:0]\xsdb_reg_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h2))
\G_COUNTER[0].U_COUNTER_i_5
(.I0(\xsdb_reg_reg[1] ),
.I1(u_wcnt_lcmp_q[0]),
.O(\current_state_reg[0]_0 ));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg
(.C(out),
.CE(1'b1),
.D(SRL_MUX8__0),
.Q(\xsdb_reg_reg[1] ),
.R(Q));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_A
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_2),
.Q(SRL_Q_3),
.Q31(cfg_data_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_B
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_1),
.Q(SRL_Q_2),
.Q31(SRL_Q31_2));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_C
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(SRL_Q31_0),
.Q(SRL_Q_1),
.Q31(SRL_Q31_1));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\I_YESLUT6.U_SRL32_D
(.A({A,\xsdb_reg_reg[1] ,u_wcnt_lcmp_q[0]}),
.CE(E),
.CLK(S_DCLK_O),
.D(capture_ctrl_config_serial_output),
.Q(SRL_Q_0),
.Q31(SRL_Q31_0));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
SRL_MUX8
(.I0(SRL_Q_3),
.I1(SRL_Q_2),
.I2(SRL_Q_1),
.I3(u_wcnt_lcmp_q[1]),
.I4(SRL_Q_0),
.I5(wcnt_hcmp),
.O(SRL_MUX8__0));
LUT3 #(
.INIT(8'h10))
\cntcmpsel[1]_i_1
(.I0(\xsdb_reg_reg[1] ),
.I1(u_wcnt_lcmp_q[0]),
.I2(dout_reg1_reg),
.O(\current_state_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h00008A80))
itrigger_out_i_1
(.I0(\xsdb_reg_reg[1] ),
.I1(trig_out_fsm),
.I2(en_adv_trigger),
.I3(basic_trigger),
.I4(u_wcnt_lcmp_q[0]),
.O(itrigger_in));
endmodule | 8 |
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