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%!PS-Adobe-3.0
%%BoundingBox: (atend)
%%Pages: (atend)
%%PageOrder: (atend)
%%DocumentFonts: (atend)
%%Creator: Frame 5.0
%%DocumentData: Clean7Bit
%%EndComments
%%BeginProlog
%
% Frame ps_prolog 5.0, for use with Frame 5.0 products
% This ps_prolog file is Copyright (c) 1986-1995 Frame Technology
% Corporation. All rights reserved. This ps_prolog file may be
% freely copied and distributed in conjunction with documents created
% using FrameMaker, FrameMaker/SGML and FrameViewer as long as this
% copyright notice is preserved.
%
% FrameMaker users specify the proper paper size for each print job in the
% "Print" dialog's "Printer Paper Size" "Width" and "Height~ fields. If the
% printer that the PS file is sent to does not support the requested paper
% size, or if there is no paper tray of the proper size currently installed,
% then the job will not be printed. The following flag, if set to true, will
% cause the job to print on the default paper in such cases.
/FMAllowPaperSizeMismatch false def
%
% Frame products normally print colors as their true color on a color printer
% or as shades of gray, based on luminance, on a black-and white printer. The
% following flag, if set to true, forces all non-white colors to print as pure
% black. This has no effect on bitmap images.
/FMPrintAllColorsAsBlack false def
%
% Frame products can either set their own line screens or use a printer's
% default settings. Three flags below control this separately for no
% separations, spot separations and process separations. If a flag
% is true, then the default printer settings will not be changed. If it is
% false, Frame products will use their own settings from a table based on
% the printer's resolution.
/FMUseDefaultNoSeparationScreen true def
/FMUseDefaultSpotSeparationScreen true def
/FMUseDefaultProcessSeparationScreen false def
%
% For any given PostScript printer resolution, Frame products have two sets of
% screen angles and frequencies for printing process separations, which are
% recomended by Adobe. The following variable chooses the higher frequencies
% when set to true or the lower frequencies when set to false. This is only
% effective if the appropriate FMUseDefault...SeparationScreen flag is false.
/FMUseHighFrequencyScreens true def
%
% The following is a set of predefined optimal frequencies and angles for various
% common dpi settings. This is taken from "Advances in Color Separation Using
% PostScript Software Technology," from Adobe Systems (3/13/89 P.N. LPS 0043)
% and corrolated with information which is in various PPD (4.0) files.
%
% The "dpiranges" figure is the minimum dots per inch device resolution which
% can support this setting. The "low" and "high" values are controlled by the
% setting of the FMUseHighFrequencyScreens flag above. The "TDot" flags control
% the use of the "Yellow Triple Dot" feature whereby the frequency id divided by
% three, but the dot function is "trippled" giving a block of 3x3 dots per cell.
%
% PatFreq is a compromise pattern frequency for ps Level 2 printers which is close
% to the ideal WYSIWYG pattern frequency of 9 repetitions/inch but does not beat
% (too badly) against the screen frequencies of any separations for that DPI.
/dpiranges [ 2540 2400 1693 1270 1200 635 600 0 ] def
/CMLowFreqs [ 100.402 94.8683 89.2289 100.402 94.8683 66.9349 63.2456 47.4342 ] def
/YLowFreqs [ 95.25 90.0 84.65 95.25 90.0 70.5556 66.6667 50.0 ] def
/KLowFreqs [ 89.8026 84.8528 79.8088 89.8026 84.8528 74.8355 70.7107 53.033 ] def
/CLowAngles [ 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 71.5651 ] def
/MLowAngles [ 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 18.4349 ] def
/YLowTDot [ true true false true true false false false ] def
/CMHighFreqs [ 133.87 126.491 133.843 108.503 102.523 100.402 94.8683 63.2456 ] def
/YHighFreqs [ 127.0 120.0 126.975 115.455 109.091 95.25 90.0 60.0 ] def
/KHighFreqs [ 119.737 113.137 119.713 128.289 121.218 89.8026 84.8528 63.6395 ] def
/CHighAngles [ 71.5651 71.5651 71.5651 70.0169 70.0169 71.5651 71.5651 71.5651 ] def
/MHighAngles [ 18.4349 18.4349 18.4349 19.9831 19.9831 18.4349 18.4349 18.4349 ] def
/YHighTDot [ false false true false false true true false ] def
/PatFreq [ 10.5833 10.0 9.4055 10.5833 10.0 10.5833 10.0 9.375 ] def
%
% PostScript Level 2 printers contain an "Accurate Screens" feature which can
% improve process separation rendering at the expense of compute time. This
% flag is ignored by PostScript Level 1 printers.
/FMUseAcccurateScreens true def
%
% The following PostScript procedure defines the spot function that Frame
% products will use for process separations. You may un-comment-out one of
% the alternative functions below, or use your own.
%
% Dot function
/FMSpotFunction {abs exch abs 2 copy add 1 gt
{1 sub dup mul exch 1 sub dup mul add 1 sub }
{dup mul exch dup mul add 1 exch sub }ifelse } def
%
% Line function
% /FMSpotFunction { pop } def
%
% Elipse function
% /FMSpotFunction { dup 5 mul 8 div mul exch dup mul exch add
% sqrt 1 exch sub } def
%
%
/FMversion (5.0) def
/fMLevel1 /languagelevel where {pop languagelevel} {1} ifelse 2 lt def
/FMPColor
fMLevel1 {
false
/colorimage where {pop pop true} if
} {
true
} ifelse
def
/FrameDict 400 dict def
systemdict /errordict known not {/errordict 10 dict def
errordict /rangecheck {stop} put} if
% The readline in PS 23.0 doesn't recognize cr's as nl's on AppleTalk
FrameDict /tmprangecheck errordict /rangecheck get put
errordict /rangecheck {FrameDict /bug true put} put
FrameDict /bug false put
mark
% Some PS machines read past the CR, so keep the following 3 lines together!
currentfile 5 string readline
00
0000000000
cleartomark
errordict /rangecheck FrameDict /tmprangecheck get put
FrameDict /bug get {
/readline {
/gstring exch def
/gfile exch def
/gindex 0 def
{
gfile read pop
dup 10 eq {exit} if
dup 13 eq {exit} if
gstring exch gindex exch put
/gindex gindex 1 add def
} loop
pop
gstring 0 gindex getinterval true
} bind def
} if
/FMshowpage /showpage load def
/FMquit /quit load def
/FMFAILURE {
dup = flush
FMshowpage
/Helvetica findfont 12 scalefont setfont
72 200 moveto show
72 220 moveto show
FMshowpage
FMquit
} def
/FMVERSION {
FMversion ne {
(Frame product version does not match ps_prolog! Check installation;)
(also check ~/fminit and ./fminit for old versions) FMFAILURE
} if
} def
/FMBADEPSF {
(Adobe's PostScript Language Reference Manual, 2nd Edition, section H.2.4)
(says your EPS file is not valid, as it calls X )
dup dup (X) search pop exch pop exch pop length
5 -1 roll
putinterval
FMFAILURE
} def
/fmConcatProcs
{
/proc2 exch cvlit def/proc1 exch cvlit def/newproc proc1 length proc2 length add array def
newproc 0 proc1 putinterval newproc proc1 length proc2 putinterval newproc cvx
}def
FrameDict begin [
/ALDsave
/FMdicttop
/FMoptop
/FMpointsize
/FMsaveobject
/b
/bitmapsave
/blut
/bpside
/bs
/bstring
/bwidth
/c
/cf
/cs
/cynu
/depth
/edown
/fh
/fillvals
/fw
/fx
/fy
/g
/gfile
/gindex
/grnt
/gryt
/gstring
/height
/hh
/i
/im
/indx
/is
/k
/kk
/landscape
/lb
/len
/llx
/lly
/m
/magu
/manualfeed
/n
/offbits
/onbits
/organgle
/orgbangle
/orgbfreq
/orgbproc
/orgbxfer
/orgfreq
/orggangle
/orggfreq
/orggproc
/orggxfer
/orgmatrix
/orgproc
/orgrangle
/orgrfreq
/orgrproc
/orgrxfer
/orgxfer
/pagesave
/paperheight
/papersizedict
/paperwidth
/pos
/pwid
/r
/rad
/redt
/sl
/str
/tran
/u
/urx
/ury
/val
/width
/width
/ws
/ww
/x
/x1
/x2
/xindex
/xpoint
/xscale
/xx
/y
/y1
/y2
/yelu
/yindex
/ypoint
/yscale
/yy
] { 0 def } forall
/FmBD {bind def} bind def
systemdict /pdfmark known {
/fMAcrobat true def
/FmPD /pdfmark load def
/FmPT /show load def
currentdistillerparams /CoreDistVersion get 2000 ge {
/FmPD2 /pdfmark load def
/FmPA { mark exch /Dest exch 5 3 roll
/View [ /XYZ null 6 -2 roll FmDC exch pop null] /DEST FmPD
}FmBD
} {
/FmPD2 /cleartomark load def
/FmPA {pop pop pop}FmBD
} ifelse
} {
/fMAcrobat false def
/FmPD /cleartomark load def
/FmPD2 /cleartomark load def
/FmPT /pop load def
/FmPA {pop pop pop}FmBD
} ifelse
/FmDC {
transform fMDefaultMatrix itransform cvi exch cvi exch
}FmBD
/FmBx {
dup 3 index lt {3 1 roll exch} if
1 index 4 index lt {4 -1 roll 3 1 roll exch 4 1 roll} if
}FmBD
/FMnone 0 def
/FMcyan 1 def
/FMmagenta 2 def
/FMyellow 3 def
/FMblack 4 def
/FMcustom 5 def
/fMNegative false def
/FrameSepIs FMnone def
/FrameSepBlack 0 def
/FrameSepYellow 0 def
/FrameSepMagenta 0 def
/FrameSepCyan 0 def
/FrameSepRed 1 def
/FrameSepGreen 1 def
/FrameSepBlue 1 def
/FrameCurGray 1 def
/FrameCurPat null def
/FrameCurColors [ 0 0 0 1 0 0 0 ] def
/FrameColorEpsilon .001 def
/eqepsilon {
sub dup 0 lt {neg} if
FrameColorEpsilon le
} bind def
/FrameCmpColorsCMYK {
2 copy 0 get exch 0 get eqepsilon {
2 copy 1 get exch 1 get eqepsilon {
2 copy 2 get exch 2 get eqepsilon {
3 get exch 3 get eqepsilon
} {pop pop false} ifelse
}{pop pop false} ifelse
} {pop pop false} ifelse
} bind def
/FrameCmpColorsRGB {
2 copy 4 get exch 0 get eqepsilon {
2 copy 5 get exch 1 get eqepsilon {
6 get exch 2 get eqepsilon
}{pop pop false} ifelse
} {pop pop false} ifelse
} bind def
/RGBtoCMYK {
1 exch sub
3 1 roll
1 exch sub
3 1 roll
1 exch sub
3 1 roll
3 copy
2 copy
le { pop } { exch pop } ifelse
2 copy
le { pop } { exch pop } ifelse
dup dup dup
6 1 roll
4 1 roll
7 1 roll
sub
6 1 roll
sub
5 1 roll
sub
4 1 roll
} bind def
/CMYKtoRGB {
dup dup 4 -1 roll add
5 1 roll 3 -1 roll add
4 1 roll add
1 exch sub dup 0 lt {pop 0} if 3 1 roll
1 exch sub dup 0 lt {pop 0} if exch
1 exch sub dup 0 lt {pop 0} if exch
} bind def
/FrameSepInit {
1.0 RealSetgray
} bind def
/FrameSetSepColor {
/FrameSepBlue exch def
/FrameSepGreen exch def
/FrameSepRed exch def
/FrameSepBlack exch def
/FrameSepYellow exch def
/FrameSepMagenta exch def
/FrameSepCyan exch def
/FrameSepIs FMcustom def
setCurrentScreen
} bind def
/FrameSetCyan {
/FrameSepBlue 1.0 def
/FrameSepGreen 1.0 def
/FrameSepRed 0.0 def
/FrameSepBlack 0.0 def
/FrameSepYellow 0.0 def
/FrameSepMagenta 0.0 def
/FrameSepCyan 1.0 def
/FrameSepIs FMcyan def
setCurrentScreen
} bind def
/FrameSetMagenta {
/FrameSepBlue 1.0 def
/FrameSepGreen 0.0 def
/FrameSepRed 1.0 def
/FrameSepBlack 0.0 def
/FrameSepYellow 0.0 def
/FrameSepMagenta 1.0 def
/FrameSepCyan 0.0 def
/FrameSepIs FMmagenta def
setCurrentScreen
} bind def
/FrameSetYellow {
/FrameSepBlue 0.0 def
/FrameSepGreen 1.0 def
/FrameSepRed 1.0 def
/FrameSepBlack 0.0 def
/FrameSepYellow 1.0 def
/FrameSepMagenta 0.0 def
/FrameSepCyan 0.0 def
/FrameSepIs FMyellow def
setCurrentScreen
} bind def
/FrameSetBlack {
/FrameSepBlue 0.0 def
/FrameSepGreen 0.0 def
/FrameSepRed 0.0 def
/FrameSepBlack 1.0 def
/FrameSepYellow 0.0 def
/FrameSepMagenta 0.0 def
/FrameSepCyan 0.0 def
/FrameSepIs FMblack def
setCurrentScreen
} bind def
/FrameNoSep {
/FrameSepIs FMnone def
setCurrentScreen
} bind def
/FrameSetSepColors {
FrameDict begin
[ exch 1 add 1 roll ]
/FrameSepColors
exch def end
} bind def
/FrameColorInSepListCMYK {
FrameSepColors {
exch dup 3 -1 roll
FrameCmpColorsCMYK
{ pop true exit } if
} forall
dup true ne {pop false} if
} bind def
/FrameColorInSepListRGB {
FrameSepColors {
exch dup 3 -1 roll
FrameCmpColorsRGB
{ pop true exit } if
} forall
dup true ne {pop false} if
} bind def
/RealSetgray /setgray load def
/RealSetrgbcolor /setrgbcolor load def
/RealSethsbcolor /sethsbcolor load def
end
/setgray {
FrameDict begin
FrameSepIs FMnone eq
{ RealSetgray }
{
FrameSepIs FMblack eq
{ RealSetgray }
{ FrameSepIs FMcustom eq
FrameSepRed 0 eq and
FrameSepGreen 0 eq and
FrameSepBlue 0 eq and {
RealSetgray
} {
1 RealSetgray pop
} ifelse
} ifelse
} ifelse
end
} bind def
/setrgbcolor {
FrameDict begin
FrameSepIs FMnone eq
{ RealSetrgbcolor }
{
3 copy [ 4 1 roll ]
FrameColorInSepListRGB
{
FrameSepBlue eq exch
FrameSepGreen eq and exch
FrameSepRed eq and
{ 0 } { 1 } ifelse
}
{
FMPColor {
RealSetrgbcolor
currentcmykcolor
} {
RGBtoCMYK
} ifelse
FrameSepIs FMblack eq
{1.0 exch sub 4 1 roll pop pop pop} {
FrameSepIs FMyellow eq
{pop 1.0 exch sub 3 1 roll pop pop} {
FrameSepIs FMmagenta eq
{pop pop 1.0 exch sub exch pop } {
FrameSepIs FMcyan eq
{pop pop pop 1.0 exch sub }
{pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse
} ifelse
RealSetgray
}
ifelse
end
} bind def
/sethsbcolor {
FrameDict begin
FrameSepIs FMnone eq
{ RealSethsbcolor }
{
RealSethsbcolor
currentrgbcolor
setrgbcolor
}
ifelse
end
} bind def
FrameDict begin
/setcmykcolor where {
pop /RealSetcmykcolor /setcmykcolor load def
} {
/RealSetcmykcolor {
4 1 roll
3 { 3 index add 0 max 1 min 1 exch sub 3 1 roll} repeat
RealSetrgbcolor pop
} bind def
} ifelse
userdict /setcmykcolor {
FrameDict begin
FrameSepIs FMnone eq
{ RealSetcmykcolor }
{
4 copy [ 5 1 roll ]
FrameColorInSepListCMYK
{
FrameSepBlack eq exch
FrameSepYellow eq and exch
FrameSepMagenta eq and exch
FrameSepCyan eq and
{ 0 } { 1 } ifelse
}
{
FrameSepIs FMblack eq
{1.0 exch sub 4 1 roll pop pop pop} {
FrameSepIs FMyellow eq
{pop 1.0 exch sub 3 1 roll pop pop} {
FrameSepIs FMmagenta eq
{pop pop 1.0 exch sub exch pop } {
FrameSepIs FMcyan eq
{pop pop pop 1.0 exch sub }
{pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse
} ifelse
RealSetgray
}
ifelse
end
} bind put
fMLevel1 {
/patScreenDict 7 dict dup begin
<0f1e3c78f0e1c387> [ 45 { pop } {exch pop} .5 2 sqrt] FmBD
<0f87c3e1f0783c1e> [ 135 { pop } {exch pop} .5 2 sqrt] FmBD
<cccccccccccccccc> [ 0 { pop } dup .5 2 ] FmBD
<ffff0000ffff0000> [ 90 { pop } dup .5 2 ] FmBD
<8142241818244281> [ 45 { 2 copy lt {exch} if pop} dup .75 2 sqrt] FmBD
<03060c183060c081> [ 45 { pop } {exch pop} .875 2 sqrt] FmBD
<8040201008040201> [ 135 { pop } {exch pop} .875 2 sqrt] FmBD
end def
} {
/patProcDict 5 dict dup begin
<0f1e3c78f0e1c387> { 3 setlinewidth -1 -1 moveto 9 9 lineto stroke
4 -4 moveto 12 4 lineto stroke
-4 4 moveto 4 12 lineto stroke} bind def
<0f87c3e1f0783c1e> { 3 setlinewidth -1 9 moveto 9 -1 lineto stroke
-4 4 moveto 4 -4 lineto stroke
4 12 moveto 12 4 lineto stroke} bind def
<8142241818244281> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke
-1 -1 moveto 9 9 lineto stroke } bind def
<03060c183060c081> { 1 setlinewidth -1 -1 moveto 9 9 lineto stroke
4 -4 moveto 12 4 lineto stroke
-4 4 moveto 4 12 lineto stroke} bind def
<8040201008040201> { 1 setlinewidth -1 9 moveto 9 -1 lineto stroke
-4 4 moveto 4 -4 lineto stroke
4 12 moveto 12 4 lineto stroke} bind def
end def
/patDict 15 dict dup begin
/PatternType 1 def
/PaintType 2 def
/TilingType 3 def
/BBox [ 0 0 8 8 ] def
/XStep 8 def
/YStep 8 def
/PaintProc {
begin
patProcDict bstring known {
patProcDict bstring get exec
} {
8 8 true [1 0 0 -1 0 8] bstring imagemask
} ifelse
end
} bind def
end def
} ifelse
/combineColor {
FrameSepIs FMnone eq
{
graymode fMLevel1 or not {
[/Pattern [/DeviceCMYK]] setcolorspace
FrameCurColors 0 4 getinterval aload pop FrameCurPat setcolor
} {
FrameCurColors 3 get 1.0 ge {
FrameCurGray RealSetgray
} {
fMAcrobat not FMPColor graymode and and {
0 1 3 {
FrameCurColors exch get
1 FrameCurGray sub mul
} for
RealSetcmykcolor
} {
4 1 6 {
FrameCurColors exch get
graymode {
1 exch sub 1 FrameCurGray sub mul 1 exch sub
} {
1.0 lt {FrameCurGray} {1} ifelse
} ifelse
} for
RealSetrgbcolor
} ifelse
} ifelse
} ifelse
} {
FrameCurColors 0 4 getinterval aload
FrameColorInSepListCMYK {
FrameSepBlack eq exch
FrameSepYellow eq and exch
FrameSepMagenta eq and exch
FrameSepCyan eq and
FrameSepIs FMcustom eq and
{ FrameCurGray } { 1 } ifelse
} {
FrameSepIs FMblack eq
{FrameCurGray 1.0 exch sub mul 1.0 exch sub 4 1 roll pop pop pop} {
FrameSepIs FMyellow eq
{pop FrameCurGray 1.0 exch sub mul 1.0 exch sub 3 1 roll pop pop} {
FrameSepIs FMmagenta eq
{pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub exch pop } {
FrameSepIs FMcyan eq
{pop pop pop FrameCurGray 1.0 exch sub mul 1.0 exch sub }
{pop pop pop pop 1} ifelse } ifelse } ifelse } ifelse
} ifelse
graymode fMLevel1 or not {
[/Pattern [/DeviceGray]] setcolorspace
FrameCurPat setcolor
} {
graymode not fMLevel1 and {
dup 1 lt {pop FrameCurGray} if
} if
RealSetgray
} ifelse
} ifelse
} bind def
/savematrix {
orgmatrix currentmatrix pop
} bind def
/restorematrix {
orgmatrix setmatrix
} bind def
/fMDefaultMatrix matrix defaultmatrix def
/fMatrix2 matrix def
/dpi 72 0 fMDefaultMatrix dtransform
dup mul exch dup mul add sqrt def
/freq dpi dup 72 div round dup 0 eq {pop 1} if 8 mul div def
/sangle 1 0 fMDefaultMatrix dtransform exch atan def
sangle fMatrix2 rotate
fMDefaultMatrix fMatrix2 concatmatrix
dup 0 get /sflipx exch def
3 get /sflipy exch def
/screenIndex {
0 1 dpiranges length 1 sub { dup dpiranges exch get 1 sub dpi le {exit} {pop} ifelse } for
} bind def
/getCyanScreen {
FMUseHighFrequencyScreens { CHighAngles CMHighFreqs} {CLowAngles CMLowFreqs} ifelse
screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load
} bind def
/getMagentaScreen {
FMUseHighFrequencyScreens { MHighAngles CMHighFreqs } {MLowAngles CMLowFreqs} ifelse
screenIndex dup 3 1 roll get 3 1 roll get /FMSpotFunction load
} bind def
/getYellowScreen {
FMUseHighFrequencyScreens { YHighTDot YHighFreqs} { YLowTDot YLowFreqs } ifelse
screenIndex dup 3 1 roll get 3 1 roll get { 3 div
{2 { 1 add 2 div 3 mul dup floor sub 2 mul 1 sub exch} repeat
FMSpotFunction } } {/FMSpotFunction load } ifelse
0.0 exch
} bind def
/getBlackScreen {
FMUseHighFrequencyScreens { KHighFreqs } { KLowFreqs } ifelse
screenIndex get 45.0 /FMSpotFunction load
} bind def
/getSpotScreen {
getBlackScreen
} bind def
/getCompositeScreen {
getBlackScreen
} bind def
/FMSetScreen
fMLevel1 { /setscreen load
}{ {
8 dict begin
/HalftoneType 1 def
/SpotFunction exch def
/Angle exch def
/Frequency exch def
/AccurateScreens FMUseAcccurateScreens def
currentdict end sethalftone
} bind } ifelse
def
/setDefaultScreen {
FMPColor {
orgrxfer cvx orggxfer cvx orgbxfer cvx orgxfer cvx setcolortransfer
}
{
orgxfer cvx settransfer
} ifelse
orgfreq organgle orgproc cvx setscreen
} bind def
/setCurrentScreen {
FrameSepIs FMnone eq {
FMUseDefaultNoSeparationScreen {
setDefaultScreen
} {
getCompositeScreen FMSetScreen
} ifelse
} {
FrameSepIs FMcustom eq {
FMUseDefaultSpotSeparationScreen {
setDefaultScreen
} {
getSpotScreen FMSetScreen
} ifelse
} {
FMUseDefaultProcessSeparationScreen {
setDefaultScreen
} {
FrameSepIs FMcyan eq {
getCyanScreen FMSetScreen
} {
FrameSepIs FMmagenta eq {
getMagentaScreen FMSetScreen
} {
FrameSepIs FMyellow eq {
getYellowScreen FMSetScreen
} {
getBlackScreen FMSetScreen
} ifelse
} ifelse
} ifelse
} ifelse
} ifelse
} ifelse
} bind def
end
/FMDOCUMENT {
array /FMfonts exch def
/#copies exch def
FrameDict begin
0 ne /manualfeed exch def
/paperheight exch def
/paperwidth exch def
0 ne /fMNegative exch def
0 ne /edown exch def
/yscale exch def
/xscale exch def
fMLevel1 {
manualfeed {setmanualfeed} if
/FMdicttop countdictstack 1 add def
/FMoptop count def
setpapername
manualfeed {true} {papersize} ifelse
{manualpapersize} {false} ifelse
{desperatepapersize} {false} ifelse
{papersizefailure} if
count -1 FMoptop {pop pop} for
countdictstack -1 FMdicttop {pop end} for
}
{2 dict
dup /PageSize [paperwidth paperheight] put
manualfeed {dup /ManualFeed manualfeed put} if
{setpagedevice} stopped {papersizefailure} if
}
ifelse
FMPColor {
currentcolorscreen
cvlit /orgproc exch def
/organgle exch def
/orgfreq exch def
cvlit /orgbproc exch def
/orgbangle exch def
/orgbfreq exch def
cvlit /orggproc exch def
/orggangle exch def
/orggfreq exch def
cvlit /orgrproc exch def
/orgrangle exch def
/orgrfreq exch def
currentcolortransfer
fMNegative {
1 1 4 {
pop { 1 exch sub } fmConcatProcs 4 1 roll
} for
4 copy
setcolortransfer
} if
cvlit /orgxfer exch def
cvlit /orgbxfer exch def
cvlit /orggxfer exch def
cvlit /orgrxfer exch def
} {
currentscreen
cvlit /orgproc exch def
/organgle exch def
/orgfreq exch def
currenttransfer
fMNegative {
{ 1 exch sub } fmConcatProcs
dup settransfer
} if
cvlit /orgxfer exch def
} ifelse
end
} def
/FMBEGINPAGE {
FrameDict begin
/pagesave save def
3.86 setmiterlimit
/landscape exch 0 ne def
landscape {
90 rotate 0 exch dup /pwid exch def neg translate pop
}{
pop /pwid exch def
} ifelse
edown { [-1 0 0 1 pwid 0] concat } if
0 0 moveto paperwidth 0 lineto paperwidth paperheight lineto
0 paperheight lineto 0 0 lineto 1 setgray fill
xscale yscale scale
/orgmatrix matrix def
gsave
} def
/FMENDPAGE {
grestore
pagesave restore
end
showpage
} def
/FMFONTDEFINE {
FrameDict begin
findfont
ReEncode
1 index exch
definefont
FMfonts 3 1 roll
put
end
} def
/FMFILLS {
FrameDict begin dup
array /fillvals exch def
dict /patCache exch def
end
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/FMFILL {
FrameDict begin
fillvals 3 1 roll put
end
} def
/FMNORMALIZEGRAPHICS {
newpath
1 setlinewidth
0 setlinecap
0 0 0 sethsbcolor
0 setgray
} bind def
/FMBEGINEPSF {
end
/FMEPSF save def
/showpage {} def
% See Adobe's "PostScript Language Reference Manual, 2nd Edition", page 714.
% "...the following operators MUST NOT be used in an EPS file:" (emphasis ours)
/banddevice {(banddevice) FMBADEPSF} def
/clear {(clear) FMBADEPSF} def
/cleardictstack {(cleardictstack) FMBADEPSF} def
/copypage {(copypage) FMBADEPSF} def
/erasepage {(erasepage) FMBADEPSF} def
/exitserver {(exitserver) FMBADEPSF} def
/framedevice {(framedevice) FMBADEPSF} def
/grestoreall {(grestoreall) FMBADEPSF} def
/initclip {(initclip) FMBADEPSF} def
/initgraphics {(initgraphics) FMBADEPSF} def
/quit {(quit) FMBADEPSF} def
/renderbands {(renderbands) FMBADEPSF} def
/setglobal {(setglobal) FMBADEPSF} def
/setpagedevice {(setpagedevice) FMBADEPSF} def
/setshared {(setshared) FMBADEPSF} def
/startjob {(startjob) FMBADEPSF} def
/lettertray {(lettertray) FMBADEPSF} def
/letter {(letter) FMBADEPSF} def
/lettersmall {(lettersmall) FMBADEPSF} def
/11x17tray {(11x17tray) FMBADEPSF} def
/11x17 {(11x17) FMBADEPSF} def
/ledgertray {(ledgertray) FMBADEPSF} def
/ledger {(ledger) FMBADEPSF} def
/legaltray {(legaltray) FMBADEPSF} def
/legal {(legal) FMBADEPSF} def
/statementtray {(statementtray) FMBADEPSF} def
/statement {(statement) FMBADEPSF} def
/executivetray {(executivetray) FMBADEPSF} def
/executive {(executive) FMBADEPSF} def
/a3tray {(a3tray) FMBADEPSF} def
/a3 {(a3) FMBADEPSF} def
/a4tray {(a4tray) FMBADEPSF} def
/a4 {(a4) FMBADEPSF} def
/a4small {(a4small) FMBADEPSF} def
/b4tray {(b4tray) FMBADEPSF} def
/b4 {(b4) FMBADEPSF} def
/b5tray {(b5tray) FMBADEPSF} def
/b5 {(b5) FMBADEPSF} def
FMNORMALIZEGRAPHICS
[/fy /fx /fh /fw /ury /urx /lly /llx] {exch def} forall
fx fw 2 div add fy fh 2 div add translate
rotate
fw 2 div neg fh 2 div neg translate
fw urx llx sub div fh ury lly sub div scale
llx neg lly neg translate
/FMdicttop countdictstack 1 add def
/FMoptop count def
} bind def
/FMENDEPSF {
count -1 FMoptop {pop pop} for
countdictstack -1 FMdicttop {pop end} for
FMEPSF restore
FrameDict begin
} bind def
FrameDict begin
/setmanualfeed {
%%BeginFeature *ManualFeed True
statusdict /manualfeed true put
%%EndFeature
} bind def
/max {2 copy lt {exch} if pop} bind def
/min {2 copy gt {exch} if pop} bind def
/inch {72 mul} def
/pagedimen {
paperheight sub abs 16 lt exch
paperwidth sub abs 16 lt and
{/papername exch def} {pop} ifelse
} bind def
/setpapername {
/papersizedict 14 dict def
papersizedict begin
/papername /unknown def
/Letter 8.5 inch 11.0 inch pagedimen
/LetterSmall 7.68 inch 10.16 inch pagedimen
/Tabloid 11.0 inch 17.0 inch pagedimen
/Ledger 17.0 inch 11.0 inch pagedimen
/Legal 8.5 inch 14.0 inch pagedimen
/Statement 5.5 inch 8.5 inch pagedimen
/Executive 7.5 inch 10.0 inch pagedimen
/A3 11.69 inch 16.5 inch pagedimen
/A4 8.26 inch 11.69 inch pagedimen
/A4Small 7.47 inch 10.85 inch pagedimen
/B4 10.125 inch 14.33 inch pagedimen
/B5 7.16 inch 10.125 inch pagedimen
end
} bind def
/papersize {
papersizedict begin
/Letter {lettertray letter} def
/LetterSmall {lettertray lettersmall} def
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/Ledger {ledgertray ledger} def
/Legal {legaltray legal} def
/Statement {statementtray statement} def
/Executive {executivetray executive} def
/A3 {a3tray a3} def
/A4 {a4tray a4} def
/A4Small {a4tray a4small} def
/B4 {b4tray b4} def
/B5 {b5tray b5} def
/unknown {unknown} def
papersizedict dup papername known {papername} {/unknown} ifelse get
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statusdict begin stopped end
} bind def
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papersizedict begin
/Letter {letter} def
/LetterSmall {lettersmall} def
/Tabloid {11x17} def
/Ledger {ledger} def
/Legal {legal} def
/Statement {statement} def
/Executive {executive} def
/A3 {a3} def
/A4 {a4} def
/A4Small {a4small} def
/B4 {b4} def
/B5 {b5} def
/unknown {unknown} def
papersizedict dup papername known {papername} {/unknown} ifelse get
end
stopped
} bind def
/desperatepapersize {
statusdict /setpageparams known
{
paperwidth paperheight 0 1
statusdict begin
{setpageparams} stopped
end
} {true} ifelse
} bind def
/papersizefailure {
FMAllowPaperSizeMismatch not
{
(The requested paper size is not available in any currently-installed tray)
(Edit the PS file to "FMAllowPaperSizeMismatch true" to use default tray)
FMFAILURE } if
} def
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/.notdef /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
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/parenright /asterisk /plus /comma /hyphen /period /slash /zero /one
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/Ntilde /Odieresis /Udieresis /aacute /agrave /acircumflex /adieresis
/atilde /aring /ccedilla /eacute /egrave /ecircumflex /edieresis
/iacute /igrave /icircumflex /idieresis /ntilde /oacute /ograve
/ocircumflex /odieresis /otilde /uacute /ugrave /ucircumflex
/udieresis /dagger /.notdef /cent /sterling /section /bullet
/paragraph /germandbls /registered /copyright /trademark /acute
/dieresis /.notdef /AE /Oslash /.notdef /.notdef /.notdef /.notdef
/yen /.notdef /.notdef /.notdef /.notdef /.notdef /.notdef
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/quoteleft /quoteright /.notdef /.notdef /ydieresis /Ydieresis
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/periodcentered /quotesinglbase /quotedblbase /perthousand
/Acircumflex /Ecircumflex /Aacute /Edieresis /Egrave /Iacute
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/breve /dotaccent /ring /cedilla /hungarumlaut /ogonek /caron
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/ReEncode {
dup
length
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{
1 index /FID ne
{def}
{pop pop} ifelse
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0 eq {/Encoding DiacriticEncoding def} if
currentdict
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} bind def
FMPColor
{
/BEGINBITMAPCOLOR {
BITMAPCOLOR} def
/BEGINBITMAPCOLORc {
BITMAPCOLORc} def
/BEGINBITMAPTRUECOLOR {
BITMAPTRUECOLOR } def
/BEGINBITMAPTRUECOLORc {
BITMAPTRUECOLORc } def
/BEGINBITMAPCMYK {
BITMAPCMYK } def
/BEGINBITMAPCMYKc {
BITMAPCMYKc } def
}
{
/BEGINBITMAPCOLOR {
BITMAPGRAY} def
/BEGINBITMAPCOLORc {
BITMAPGRAYc} def
/BEGINBITMAPTRUECOLOR {
BITMAPTRUEGRAY } def
/BEGINBITMAPTRUECOLORc {
BITMAPTRUEGRAYc } def
/BEGINBITMAPCMYK {
BITMAPCMYKGRAY } def
/BEGINBITMAPCMYKc {
BITMAPCMYKGRAYc } def
}
ifelse
/K {
FMPrintAllColorsAsBlack {
dup 1 eq 2 index 1 eq and 3 index 1 eq and not
{7 {pop} repeat 0 0 0 1 0 0 0} if
} if
FrameCurColors astore
pop combineColor
} bind def
/graymode true def
fMLevel1 {
/fmGetFlip {
fMatrix2 exch get mul 0 lt { -1 } { 1 } ifelse
} FmBD
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/setPatternMode {
fMLevel1 {
2 index patScreenDict exch known {
pop pop
patScreenDict exch get aload pop
freq
mul
5 2 roll
fMatrix2 currentmatrix 1 get 0 ne {
3 -1 roll 90 add 3 1 roll
sflipx 1 fmGetFlip sflipy 2 fmGetFlip neg mul
} {
sflipx 0 fmGetFlip sflipy 3 fmGetFlip mul
} ifelse
0 lt {exch pop} {pop} ifelse
fMNegative {
{neg} fmConcatProcs
} if
bind
systemdict /setscreen get exec
/FrameCurGray exch def
} {
/bwidth exch def
/bpside exch def
/bstring exch def
/onbits 0 def /offbits 0 def
freq sangle landscape {90 add} if
{/ypoint exch def
/xpoint exch def
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/yindex ypoint 1 add 2 div bpside mul cvi def
bstring yindex bwidth mul xindex 8 idiv add get
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{/onbits onbits 1 add def 1}
{/offbits offbits 1 add def 0}
ifelse
}
setscreen
offbits offbits onbits add div fMNegative {1.0 exch sub} if
/FrameCurGray exch def
} ifelse
} {
pop pop
dup patCache exch known {
patCache exch get
} {
dup
patDict /bstring 3 -1 roll put
patDict
9 PatFreq screenIndex get div dup matrix scale
makepattern
dup
patCache 4 -1 roll 3 -1 roll put
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/FrameCurGray 0 def
/FrameCurPat exch def
} ifelse
/graymode false def
combineColor
} bind def
/setGrayScaleMode {
graymode not {
/graymode true def
fMLevel1 {
setCurrentScreen
} if
} if
/FrameCurGray exch def
combineColor
} bind def
/normalize {
transform round exch round exch itransform
} bind def
/dnormalize {
dtransform round exch round exch idtransform
} bind def
/lnormalize {
0 dtransform exch cvi 2 idiv 2 mul 1 add exch idtransform pop
} bind def
/H {
lnormalize setlinewidth
} bind def
/Z {
setlinecap
} bind def
/PFill {
graymode fMLevel1 or not {
gsave 1 setgray eofill grestore
} if
} bind def
/PStroke {
graymode fMLevel1 or not {
gsave 1 setgray stroke grestore
} if
stroke
} bind def
/X {
fillvals exch get
dup type /stringtype eq
{8 1 setPatternMode}
{setGrayScaleMode}
ifelse
} bind def
/V {
PFill gsave eofill grestore
} bind def
/Vclip {
clip
} bind def
/Vstrk {
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/N {
PStroke
} bind def
/Nclip {
strokepath clip newpath
} bind def
/Nstrk {
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/M {newpath moveto} bind def
/E {lineto} bind def
/D {curveto} bind def
/O {closepath} bind def
/L {
/n exch def
newpath
normalize
moveto
2 1 n {pop normalize lineto} for
} bind def
/Y {
L
closepath
} bind def
/R {
/y2 exch def
/x2 exch def
/y1 exch def
/x1 exch def
x1 y1
x2 y1
x2 y2
x1 y2
4 Y
} bind def
/rarc
{rad
arcto
} bind def
/RR {
/rad exch def
normalize
/y2 exch def
/x2 exch def
normalize
/y1 exch def
/x1 exch def
mark
newpath
{
x1 y1 rad add moveto
x1 y2 x2 y2 rarc
x2 y2 x2 y1 rarc
x2 y1 x1 y1 rarc
x1 y1 x1 y2 rarc
closepath
} stopped {x1 y1 x2 y2 R} if
cleartomark
} bind def
/RRR {
/rad exch def
normalize /y4 exch def /x4 exch def
normalize /y3 exch def /x3 exch def
normalize /y2 exch def /x2 exch def
normalize /y1 exch def /x1 exch def
newpath
normalize moveto
mark
{
x2 y2 x3 y3 rarc
x3 y3 x4 y4 rarc
x4 y4 x1 y1 rarc
x1 y1 x2 y2 rarc
closepath
} stopped
{x1 y1 x2 y2 x3 y3 x4 y4 newpath moveto lineto lineto lineto closepath} if
cleartomark
} bind def
/C {
grestore
gsave
R
clip
setCurrentScreen
} bind def
/CP {
grestore
gsave
Y
clip
setCurrentScreen
} bind def
/F {
FMfonts exch get
FMpointsize scalefont
setfont
} bind def
/Q {
/FMpointsize exch def
F
} bind def
/T {
moveto show
} bind def
/RF {
rotate
0 ne {-1 1 scale} if
} bind def
/TF {
gsave
moveto
RF
show
grestore
} bind def
/P {
moveto
0 32 3 2 roll widthshow
} bind def
/PF {
gsave
moveto
RF
0 32 3 2 roll widthshow
grestore
} bind def
/S {
moveto
0 exch ashow
} bind def
/SF {
gsave
moveto
RF
0 exch ashow
grestore
} bind def
/B {
moveto
0 32 4 2 roll 0 exch awidthshow
} bind def
/BF {
gsave
moveto
RF
0 32 4 2 roll 0 exch awidthshow
grestore
} bind def
/G {
gsave
newpath
normalize translate 0.0 0.0 moveto
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
PFill fill
grestore
} bind def
/Gstrk {
savematrix
newpath
2 index 2 div add exch 3 index 2 div sub exch
normalize 2 index 2 div sub exch 3 index 2 div add exch
translate
scale
0.0 0.0 1.0 5 3 roll arc
restorematrix
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/Gclip {
newpath
savematrix
normalize translate 0.0 0.0 moveto
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
clip newpath
restorematrix
} bind def
/GG {
gsave
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
PFill
fill
grestore
} bind def
/GGclip {
savematrix
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
clip newpath
restorematrix
} bind def
/GGstrk {
savematrix
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
restorematrix
currentlinewidth exch setlinewidth PStroke setlinewidth
} bind def
/A {
gsave
savematrix
newpath
2 index 2 div add exch 3 index 2 div sub exch
normalize 2 index 2 div sub exch 3 index 2 div add exch
translate
scale
0.0 0.0 1.0 5 3 roll arc
restorematrix
PStroke
grestore
} bind def
/Aclip {
newpath
savematrix
normalize translate 0.0 0.0 moveto
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
strokepath clip newpath
restorematrix
} bind def
/Astrk {
Gstrk
} bind def
/AA {
gsave
savematrix
newpath
3 index 2 div add exch 4 index 2 div sub exch
normalize 3 index 2 div sub exch 4 index 2 div add exch
translate
rotate
scale
0.0 0.0 1.0 5 3 roll arc
restorematrix
PStroke
grestore
} bind def
/AAclip {
savematrix
newpath
normalize translate 0.0 0.0 moveto
rotate
dnormalize scale
0.0 0.0 1.0 5 3 roll arc
closepath
strokepath clip newpath
restorematrix
} bind def
/AAstrk {
GGstrk
} bind def
/BEGINPRINTCODE {
/FMdicttop countdictstack 1 add def
/FMoptop count 7 sub def
/FMsaveobject save def
userdict begin
/showpage {} def
FMNORMALIZEGRAPHICS
3 index neg 3 index neg translate
} bind def
/ENDPRINTCODE {
count -1 FMoptop {pop pop} for
countdictstack -1 FMdicttop {pop end} for
FMsaveobject restore
} bind def
/gn {
0
{ 46 mul
cf read pop
32 sub
dup 46 lt {exit} if
46 sub add
} loop
add
} bind def
/cfs {
/str sl string def
0 1 sl 1 sub {str exch val put} for
str def
} bind def
/ic [
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0223
0
{0 hx} {1 hx} {2 hx} {3 hx} {4 hx} {5 hx} {6 hx} {7 hx} {8 hx} {9 hx}
{10 hx} {11 hx} {12 hx} {13 hx} {14 hx} {15 hx} {16 hx} {17 hx} {18 hx}
{19 hx} {gn hx} {0} {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12}
{13} {14} {15} {16} {17} {18} {19} {gn} {0 wh} {1 wh} {2 wh} {3 wh}
{4 wh} {5 wh} {6 wh} {7 wh} {8 wh} {9 wh} {10 wh} {11 wh} {12 wh}
{13 wh} {14 wh} {gn wh} {0 bl} {1 bl} {2 bl} {3 bl} {4 bl} {5 bl} {6 bl}
{7 bl} {8 bl} {9 bl} {10 bl} {11 bl} {12 bl} {13 bl} {14 bl} {gn bl}
{0 fl} {1 fl} {2 fl} {3 fl} {4 fl} {5 fl} {6 fl} {7 fl} {8 fl} {9 fl}
{10 fl} {11 fl} {12 fl} {13 fl} {14 fl} {gn fl}
] def
/ms {
/sl exch def
/val 255 def
/ws cfs
/im cfs
/val 0 def
/bs cfs
/cs cfs
} bind def
400 ms
/ip {
is
0
cf cs readline pop
{ ic exch get exec
add
} forall
pop
} bind def
/rip {
bis ris copy pop
is
0
cf cs readline pop
{ ic exch get exec
add
} forall
pop pop
ris gis copy pop
dup is exch
cf cs readline pop
{ ic exch get exec
add
} forall
pop pop
gis bis copy pop
dup add is exch
cf cs readline pop
{ ic exch get exec
add
} forall
pop
} bind def
/rip4 {
kis cis copy pop
is
0
cf cs readline pop
{ ic exch get exec
add
} forall
pop pop
cis mis copy pop
dup is exch
cf cs readline pop
{ ic exch get exec
add
} forall
pop pop
mis yis copy pop
dup dup add is exch
cf cs readline pop
{ ic exch get exec
add
} forall
pop pop
yis kis copy pop
3 mul is exch
cf cs readline pop
{ ic exch get exec
add
} forall
pop
} bind def
/wh {
/len exch def
/pos exch def
ws 0 len getinterval im pos len getinterval copy pop
pos len
} bind def
/bl {
/len exch def
/pos exch def
bs 0 len getinterval im pos len getinterval copy pop
pos len
} bind def
/s1 1 string def
/fl {
/len exch def
/pos exch def
/val cf s1 readhexstring pop 0 get def
pos 1 pos len add 1 sub {im exch val put} for
pos len
} bind def
/hx {
3 copy getinterval
cf exch readhexstring pop pop
} bind def
/wbytes {
dup dup
8 gt { pop 8 idiv mul }
{ 8 eq {pop} {1 eq {7 add 8 idiv} {3 add 4 idiv} ifelse} ifelse } ifelse
} bind def
/BEGINBITMAPBWc {
1 {} COMMONBITMAPc
} bind def
/BEGINBITMAPGRAYc {
8 {} COMMONBITMAPc
} bind def
/BEGINBITMAP2BITc {
2 {} COMMONBITMAPc
} bind def
/COMMONBITMAPc {
/cvtProc exch def
/depth exch def
gsave
3 index 2 div add exch
4 index 2 div add exch
translate
rotate
1 index 2 div neg
1 index 2 div neg
translate
scale
/height exch def /width exch def
/lb width depth wbytes def
sl lb lt {lb ms} if
/bitmapsave save def
cvtProc
/is im 0 lb getinterval def
ws 0 lb getinterval is copy pop
/cf currentfile def
width height depth [width 0 0 height neg 0 height]
{ip} image
bitmapsave restore
grestore
} bind def
/BEGINBITMAPBW {
1 {} COMMONBITMAP
} bind def
/BEGINBITMAPGRAY {
8 {} COMMONBITMAP
} bind def
/BEGINBITMAP2BIT {
2 {} COMMONBITMAP
} bind def
/COMMONBITMAP {
/cvtProc exch def
/depth exch def
gsave
3 index 2 div add exch
4 index 2 div add exch
translate
rotate
1 index 2 div neg
1 index 2 div neg
translate
scale
/height exch def /width exch def
/bitmapsave save def
cvtProc
/is width depth wbytes string def
/cf currentfile def
width height depth [width 0 0 height neg 0 height]
{cf is readhexstring pop} image
bitmapsave restore
grestore
} bind def
/ngrayt 256 array def
/nredt 256 array def
/nbluet 256 array def
/ngreent 256 array def
fMLevel1 {
/colorsetup {
currentcolortransfer
/gryt exch def
/blut exch def
/grnt exch def
/redt exch def
0 1 255 {
/indx exch def
/cynu 1 red indx get 255 div sub def
/magu 1 green indx get 255 div sub def
/yelu 1 blue indx get 255 div sub def
/kk cynu magu min yelu min def
/u kk currentundercolorremoval exec def
% /u 0 def
nredt indx 1 0 cynu u sub max sub redt exec put
ngreent indx 1 0 magu u sub max sub grnt exec put
nbluet indx 1 0 yelu u sub max sub blut exec put
ngrayt indx 1 kk currentblackgeneration exec sub gryt exec put
} for
{255 mul cvi nredt exch get}
{255 mul cvi ngreent exch get}
{255 mul cvi nbluet exch get}
{255 mul cvi ngrayt exch get}
setcolortransfer
{pop 0} setundercolorremoval
{} setblackgeneration
} bind def
}
{
/colorSetup2 {
[ /Indexed /DeviceRGB 255
{dup red exch get 255 div
exch dup green exch get 255 div
exch blue exch get 255 div}
] setcolorspace
} bind def
} ifelse
/fakecolorsetup {
/tran 256 string def
0 1 255 {/indx exch def
tran indx
red indx get 77 mul
green indx get 151 mul
blue indx get 28 mul
add add 256 idiv put} for
currenttransfer
{255 mul cvi tran exch get 255.0 div}
exch fmConcatProcs settransfer
} bind def
/BITMAPCOLOR {
/depth 8 def
gsave
3 index 2 div add exch
4 index 2 div add exch
translate
rotate
1 index 2 div neg
1 index 2 div neg
translate
scale
/height exch def /width exch def
/bitmapsave save def
fMLevel1 {
colorsetup
/is width depth wbytes string def
/cf currentfile def
width height depth [width 0 0 height neg 0 height]
{cf is readhexstring pop} {is} {is} true 3 colorimage
} {
colorSetup2
/is width depth wbytes string def
/cf currentfile def
7 dict dup begin
/ImageType 1 def
/Width width def
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(Santa Clara, CA 95054-2913) 108 491 T
(USA) 108 477 T
(Phone:) 108 455 T
(\050+1\051 408-748-9111) 180 455 T
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(ax:) 114.49 441 T
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(A) 509.57 667 T
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(Preface) 126 642.33 T
(........................................................................................................................) 161.24 642.33 T
(1) 525.44 642.33 T
(1) 108 618.33 T
(Scope) 126 618.33 T
(...........................................................................................................................) 152.9 618.33 T
(5) 525.44 618.33 T
(1.1) 126 604.33 T
(SPARC-V8E Attributes) 162 604.33 T
(................................................................................) 272.44 604.33 T
(5) 525.44 604.33 T
(1.1.1) 162 590.33 T
(Design Goals) 207 590.33 T
(.................................................................................) 269.66 590.33 T
(5) 525.44 590.33 T
(1.1.2) 162 576.33 T
(Architectural Enhancements) 207 576.33 T
(.......................................................) 341.94 576.33 T
(5) 525.44 576.33 T
(1.2) 126 562.33 T
(SPARC-V8E Features) 162 562.33 T
(...................................................................................) 264.1 562.33 T
(6) 525.44 562.33 T
(1.3) 126 548.33 T
(SPARC-V8E Definition) 162 548.33 T
(.................................................................................) 269.66 548.33 T
(7) 525.44 548.33 T
(1.4) 126 534.33 T
(SPARC-V8E Compliance) 162 534.33 T
(..............................................................................) 278 534.33 T
(8) 525.44 534.33 T
(2) 108 510.33 T
(Instructions) 126 510.33 T
(................................................................................................................) 183.48 510.33 T
(9) 525.44 510.33 T
(2.1) 126 496.33 T
(Divide Step) 162 496.33 T
(....................................................................................................) 216.84 496.33 T
(10) 519.88 496.33 T
(2.2) 126 482.33 T
(Scan) 162 482.33 T
(...............................................................................................................) 186.26 482.33 T
(12) 519.88 482.33 T
(2.3) 126 468.33 T
(Mac) 162 468.33 T
(................................................................................................................) 183.48 468.33 T
(13) 519.88 468.33 T
(2.4) 126 454.33 T
(Alternate Window Pointer) 162 454.33 T
(...........................................................................) 286.34 454.33 T
(15) 519.88 454.33 T
(2.5) 126 440.33 T
(Partial WRPSR) 162 440.33 T
(.............................................................................................) 236.3 440.33 T
(15) 519.88 440.33 T
(2.6) 126 426.33 T
(Non-Privileged ASI Access) 162 426.33 T
(...........................................................................) 286.34 426.33 T
(15) 519.88 426.33 T
(3) 108 402.33 T
(Memory Management Unit \050MMU\051) 126 402.33 T
(..........................................................................) 289.12 402.33 T
(17) 519.88 402.33 T
(3.1) 126 388.33 T
(Overview) 162 388.33 T
(.......................................................................................................) 208.5 388.33 T
(17) 519.88 388.33 T
(3.2) 126 374.33 T
(Reference MMU architecture) 162 374.33 T
(.......................................................................) 297.46 374.33 T
(17) 519.88 374.33 T
(3.2.1) 162 360.33 T
(Overview) 207 360.33 T
(.......................................................................................) 252.98 360.33 T
(17) 519.88 360.33 T
(3.2.2) 162 346.33 T
(Virtual Address Format) 207 346.33 T
(...............................................................) 319.7 346.33 T
(18) 519.88 346.33 T
(3.2.3) 162 332.33 T
(Physical Address Format) 207 332.33 T
(.............................................................) 325.26 332.33 T
(19) 519.88 332.33 T
(3.2.4) 162 318.33 T
(Address Translation) 207 318.33 T
(.....................................................................) 303.02 318.33 T
(19) 519.88 318.33 T
(3.2.5) 162 304.33 T
(Contexts) 207 304.33 T
(........................................................................................) 250.2 304.33 T
(19) 519.88 304.33 T
(3.2.6) 162 290.33 T
(Tables) 207 290.33 T
(............................................................................................) 239.08 290.33 T
(20) 519.88 290.33 T
(3.2.7) 162 276.33 T
(Page Table Descriptor \050PTD\051) 207 276.33 T
(.......................................................) 341.94 276.33 T
(21) 519.88 276.33 T
(3.2.8) 162 262.33 T
(Page Table Entry \050PTE\051) 207 262.33 T
(...............................................................) 319.7 262.33 T
(21) 519.88 262.33 T
(3.2.9) 162 248.33 T
(Translation Lookaside Buffer \050TLB\051) 207 248.33 T
(...........................................) 375.3 248.33 T
(22) 519.88 248.33 T
(3.3) 126 234.33 T
(Cacheability Control \050Minimal MMU\051) 162 234.33 T
(........................................................) 339.16 234.33 T
(26) 519.88 234.33 T
(4) 108 210.33 T
(Traps) 126 210.33 T
(..........................................................................................................................) 155.68 210.33 T
(27) 519.88 210.33 T
(4.1) 126 196.33 T
(Overview) 162 196.33 T
(.......................................................................................................) 208.5 196.33 T
(27) 519.88 196.33 T
(4.2) 126 182.33 T
(Single-Vector Trapping) 162 182.33 T
(................................................................................) 272.44 182.33 T
(27) 519.88 182.33 T
(5) 108 158.33 T
(Peripheral Extensions) 126 158.33 T
(...............................................................................................) 230.74 158.33 T
(29) 519.88 158.33 T
(5.1) 126 144.33 T
(Overview) 162 144.33 T
(.......................................................................................................) 208.5 144.33 T
(29) 519.88 144.33 T
(5.2) 126 130.33 T
(Input Handler) 162 130.33 T
(...............................................................................................) 230.74 130.33 T
(29) 519.88 130.33 T
(5.2.1) 162 116.33 T
(Input Handler Circuit) 207 116.33 T
(..................................................................) 311.36 116.33 T
(30) 519.88 116.33 T
(5.2.2) 162 102.33 T
(ASI Mapping for Input Handler) 207 102.33 T
(..................................................) 355.84 102.33 T
(31) 519.88 102.33 T
(5.3) 126 88.33 T
(Interrupts) 162 88.33 T
(......................................................................................................) 211.28 88.33 T
(32) 519.88 88.33 T
FMENDPAGE
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(The basic circuitry) 171 708.33 T
(........................................................................) 258.54 708.33 T
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(....................................................) 314.14 680.33 T
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(......................................................) 308.58 666.33 T
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(5.4.2) 126 652.33 T
(IIRC Registers) 171 652.33 T
(..............................................................................) 241.86 652.33 T
(35) 483.88 652.33 T
(5.4.3) 126 638.33 T
(IIRC Operation) 171 638.33 T
(.............................................................................) 244.64 638.33 T
(38) 483.88 638.33 T
(5.4.4) 126 624.33 T
(Extension for Additional Interrupt Sources) 171 624.33 T
(................................) 369.74 624.33 T
(40) 483.88 624.33 T
(5.5) 90 610.33 T
(Timers and Counters) 126 610.33 T
(....................................................................................) 225.18 610.33 T
(42) 483.88 610.33 T
(5.5.1) 126 596.33 T
(Programmable Pulse Generators) 171 596.33 T
(................................................) 325.26 596.33 T
(42) 483.88 596.33 T
(5.5.2) 126 582.33 T
(Simple Counters) 171 582.33 T
(...........................................................................) 250.2 582.33 T
(48) 483.88 582.33 T
(5.5.3) 126 568.33 T
(Simple Timers) 171 568.33 T
(...............................................................................) 239.08 568.33 T
(49) 483.88 568.33 T
(6) 72 544.33 T
(Diagnostic Facilities) 90 544.33 T
(..................................................................................................) 186.26 544.33 T
(59) 483.88 544.33 T
(6.1) 90 530.33 T
(Introduction) 126 530.33 T
(..................................................................................................) 186.26 530.33 T
(59) 483.88 530.33 T
(6.1.1) 126 516.33 T
(The trace enhancing implementation.) 171 516.33 T
(.........................................) 344.72 516.33 T
(59) 483.88 516.33 T
(6.1.2) 126 502.33 T
( The pin effective implementation.) 171 502.33 T
(..............................................) 330.82 502.33 T
(59) 483.88 502.33 T
(6.2) 90 488.33 T
(List of features) 126 488.33 T
(..............................................................................................) 197.38 488.33 T
(60) 483.88 488.33 T
(Annex A) 72 464.33 T
(\050Normative\051 Programming Techniques) 126 464.33 T
(......................................................) 308.58 464.33 T
(63) 483.88 464.33 T
(A.1) 90 450.33 T
(Overview) 126 450.33 T
(.......................................................................................................) 172.36 450.33 T
(63) 483.88 450.33 T
(A.2) 90 436.33 T
(Division Performance Using DIVScc) 126 436.33 T
(...........................................................) 294.68 436.33 T
(63) 483.88 436.33 T
(A.2.1) 126 422.33 T
(divs1 - divide signed, 1 word dividend) 171 422.33 T
(........................................) 347.5 422.33 T
(63) 483.88 422.33 T
(A.2.2) 126 408.33 T
(divs2 - divide signed, 2 word dividend) 171 408.33 T
(........................................) 347.5 408.33 T
(65) 483.88 408.33 T
(A.2.3) 126 394.33 T
(divu1 - divide unsigned, 1 word dividend) 171 394.33 T
(....................................) 358.62 394.33 T
(68) 483.88 394.33 T
(A.2.4) 126 380.33 T
(divu2 - divide unsigned, 2 word dividend) 171 380.33 T
(....................................) 358.62 380.33 T
(70) 483.88 380.33 T
(A.3) 90 366.33 T
(SCAN Instruction Examples) 126 366.33 T
(........................................................................) 258.54 366.33 T
(72) 483.88 366.33 T
(A.3.1) 126 352.33 T
(Software floating point with SCAN) 171 352.33 T
(.............................................) 333.6 352.33 T
(72) 483.88 352.33 T
(A.3.2) 126 338.33 T
(Run length encoding with SCAN) 171 338.33 T
(.................................................) 322.48 338.33 T
(74) 483.88 338.33 T
(Annex B) 72 314.33 T
(\050Normative\051 Alternative Window Usage Models) 126 314.33 T
(.......................................) 350.28 314.33 T
(77) 483.88 314.33 T
(B.1) 90 300.33 T
(Overview) 126 300.33 T
(.......................................................................................................) 172.36 300.33 T
(77) 483.88 300.33 T
(B.2) 90 286.33 T
(Single Register Window Model) 126 286.33 T
(....................................................................) 269.66 286.33 T
(78) 483.88 286.33 T
(B.3) 90 272.33 T
(Conclusion) 126 272.33 T
(.....................................................................................................) 177.92 272.33 T
(79) 483.88 272.33 T
(Annex C) 72 248.33 T
(\050Normative\051 Summary of Operation Codes, ASIs and ASRs) 126 248.33 T
(.....................) 400.32 248.33 T
(81) 483.88 248.33 T
(C.1) 90 234.33 T
(Operation Codes) 126 234.33 T
(...........................................................................................) 205.72 234.33 T
(81) 483.88 234.33 T
(C.2) 90 220.33 T
(ASI Assignments) 126 220.33 T
(..........................................................................................) 208.5 220.33 T
(81) 483.88 220.33 T
(C.3) 90 206.33 T
(ASRs) 126 206.33 T
(..............................................................................................................) 152.9 206.33 T
(81) 483.88 206.33 T
(Annex D) 72 182.33 T
(\050Normative\051 List of options) 126 182.33 T
(.........................................................................) 255.76 182.33 T
(83) 483.88 182.33 T
(D.1) 90 168.33 T
(Introduction) 126 168.33 T
(..................................................................................................) 186.26 168.33 T
(83) 483.88 168.33 T
(D.2) 90 154.33 T
(Instructions) 126 154.33 T
(...................................................................................................) 183.48 154.33 T
(83) 483.88 154.33 T
(D.3) 90 140.33 T
(MMU) 126 140.33 T
(.............................................................................................................) 155.68 140.33 T
(83) 483.88 140.33 T
(D.4) 90 126.33 T
(Traps) 126 126.33 T
(.............................................................................................................) 155.68 126.33 T
(84) 483.88 126.33 T
(D.5) 90 112.33 T
(Peripheral Extensions) 126 112.33 T
(..................................................................................) 230.74 112.33 T
(84) 483.88 112.33 T
(D.6) 90 98.33 T
(Diagnostics) 126 98.33 T
(....................................................................................................) 180.7 98.33 T
(84) 483.88 98.33 T
FMENDPAGE
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(SPARC-V8E) 475.99 748 T
(Preface) 114 17 T
(1) 534 17 T
4 14 Q
(Preface) 296.13 623.67 T
0 12 Q
(Intr) 108 579 T
(oduction) 128.45 579 T
2 F
0.11 (W) 108 557 P
0.11 (elcome to SP) 118.37 557 P
0.11 (ARC-V8E, the real-time / embedded e) 180.82 557 P
0.11 (xtension of SP) 365.82 557 P
0.11 (ARC, the most pre) 434.95 557 P
0.11 (v) 524.98 557 P
0.11 (a-) 530.68 557 P
0.41 (lent RISC architecture for general purpose computing. SP) 108 543 P
0.41 (ARC-V8E adds instructions for) 387.1 543 P
1.52 (increased performance and f) 108 529 P
1.52 (ast interrupt response time, de\336nes critical system features) 248.72 529 P
(and pro) 108 515 T
(vides a reference architecture to support real-time deb) 144.14 515 T
(ugging.) 402.82 515 T
-0.18 (SP) 108 493 P
-0.18 (ARC-V8E is a microprocessor speci\336cation created by the SP) 120.24 493 P
-0.18 (ARC Embedded Commit-) 415.01 493 P
0.05 (tee of EuroSP) 108 479 P
0.05 (ARC and re) 173.66 479 P
0.05 (vie) 230.78 479 P
0.05 (wed by the SP) 245.15 479 P
0.05 (ARC Architecture Committee of SP) 313.2 479 P
0.05 (ARC Inter-) 485.62 479 P
0.25 (national. SP) 108 465 P
0.25 (ARC-V8E is not a speci\336c chip; it is an architectural speci\336cation that can be) 165.15 465 P
2.09 (implemented as a microprocessor by an) 108 451 P
2.09 (yone securing a license from SP) 308.58 451 P
2.09 (ARC Interna-) 472.25 451 P
(tional.) 108 437 T
0.45 (EuroSP) 108 415 P
0.45 (ARC is an open membership SP) 143.57 415 P
0.45 (ARC user group in Europe who counts among its) 299.73 415 P
0.41 (members real-time / embedded computer mak) 108 401 P
0.41 (ers, semiconductor designers and manuf) 330.88 401 P
0.41 (ac-) 525.35 401 P
2.14 (turers, as well as softw) 108 387 P
2.14 (are de) 226.1 387 P
2.14 (v) 256.93 387 P
2.14 (elopment tools and operating systems v) 262.75 387 P
2.14 (endors. SP) 462.95 387 P
2.14 (ARC) 515.33 387 P
0.27 (International is a consortium of computer mak) 108 373 P
0.27 (ers with membership open to an) 332.12 373 P
0.27 (y compan) 486.92 373 P
0.27 (y) 534 373 P
0.05 (in the w) 108 359 P
0.05 (orld. The SP) 146.64 359 P
0.05 (ARC Embedded Committee has been chartered to enable and support) 205.96 359 P
-0.18 (the use of SP) 108 345 P
-0.18 (ARC as the embedded architecture of choice. The SP) 169.35 345 P
-0.18 (ARC Architecture Com-) 422.38 345 P
0.7 (mittee is composed of v) 108 331 P
0.7 (oting members each of whom represents one of SP) 225.21 331 P
0.7 (ARC Interna-) 473.65 331 P
(tional\325) 108 317 T
(s Ex) 138.67 317 T
(ecuti) 159.49 317 T
(v) 182.52 317 T
(e Member companies.) 188.34 317 T
1.15 (General purpose architectures are normally e) 108 295 P
1.15 (v) 329.04 295 P
1.15 (olv) 334.8 295 P
1.15 (ed to anticipate increasing demands of) 349.96 295 P
1.19 (applications as well as to tak) 108 281 P
1.19 (e adv) 251.46 281 P
1.19 (antage of state-of-the-art technology) 278 281 P
1.19 (. SP) 455.73 281 P
1.19 (ARC-V8 and) 475.15 281 P
0.31 (V9 are good e) 108 267 P
0.31 (xamples. The Embedded Committee of EuroSP) 176.38 267 P
0.31 (ARC has identi\336ed an addi-) 404.79 267 P
-0.19 (tional direction, that of creating a chip architecture that can bring RISC research and e) 108 253 P
-0.19 (xpe-) 518.67 253 P
4.97 (rience to real-time / embedded systems at v) 108 239 P
4.97 (olume prices. By using SP) 350.87 239 P
4.97 (ARC-V8) 496.67 239 P
2.95 (architecture as the base for enhancement, the Embedded Committee of EuroSP) 108 225 P
2.95 (ARC) 515.33 225 P
-0.28 (allo) 108 211 P
-0.28 (ws both w) 125.7 211 P
-0.28 (orkstations and embedded systems to share the bene\336ts of v) 174.35 211 P
-0.28 (olume prices and) 458.57 211 P
0.42 (ongoing research. And the simplicity of V8 implementation has already made it a prefer-) 108 197 P
0.45 (ence for custom modular chips such as the ones being designed for the SMILE project, a) 108 183 P
0.62 (major European in) 108 169 P
0.62 (v) 198.09 169 P
0.62 (estment The resulting real-time/embedded e) 203.91 169 P
0.62 (xtension of the V8 archi-) 417.52 169 P
0.65 (tecture creates a processor with high performance suitable for operating systems ranging) 108 155 P
0.08 (from Solaris \050tm\051, do) 108 141 P
0.08 (wn to fully predictable, high speed real-time operation on minimum-) 209.28 141 P
0.09 (sized e) 108 127 P
0.09 (x) 140.9 127 P
0.09 (ecuti) 146.72 127 P
0.09 (v) 169.75 127 P
0.09 (es. It also ensures that this processor) 175.57 127 P
0.09 (, unlik) 350.61 127 P
0.09 (e others that were dedicated only) 381.25 127 P
-0.22 (to real-time / embedded use, will be long li) 108 113 P
-0.22 (v) 312.29 113 P
-0.22 (ed because it will pro\336t from all of the inno) 318.11 113 P
-0.22 (v) 524.98 113 P
-0.22 (a-) 530.68 113 P
(tion and in) 108 99 T
(v) 158.86 99 T
(estment going into the SP) 164.68 99 T
(ARC chips for w) 286.92 99 T
(orkstation use.) 368.46 99 T
FMENDPAGE
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(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(2) 72 17 T
(Preface) 468.02 17 T
1.04 (Learning from e) 72 721 P
1.04 (xperience obtained from Fujitsu\325) 151.87 721 P
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1.04 (ARClite\323 chips, \322DIVIDE STEP\323) 338.24 721 P
-0.05 (instructions ha) 72 707 P
-0.05 (v) 142.04 707 P
-0.05 (e been introduced to minimize interrupt response time. Additional instruc-) 147.86 707 P
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0.54 (C are intended to pro) 213.2 693 P
0.54 (vide hardw) 316.49 693 P
0.54 (are support for high perfor-) 370.56 693 P
2.9 (mance e) 72 679 P
2.9 (x) 114.37 679 P
2.9 (ecution. The MMU has been e) 120.19 679 P
2.9 (xtended, e.g. it supports global conte) 280.47 679 P
2.9 (xt and) 471.44 679 P
1.06 (optional protection of a smaller page size. System features ha) 72 665 P
1.06 (v) 375.95 665 P
1.06 (e been added: input han-) 381.77 665 P
0.04 (dlers, interrupt mechanisms, counters, timers, pulsers. Finally) 72 651 P
0.04 (, a complete real-time deb) 367.11 651 P
0.04 (ug) 492 651 P
(architecture has been de\336ned to support breakpointing, tracing and emulation.) 72 637 T
-0.08 (Architecture compatibility for implementations, is based on the common denominator) 72 615 P
-0.08 (, the) 483.42 615 P
1.04 (V8 Architecture de\336nition and enhancements. Compliance with the speci\336cation can be) 72 601 P
(obtained either via complete H/W implementation or by instruction emulation.) 72 587 T
0 F
(A) 72 543 T
(udience f) 80.06 543 T
(or this Speci\336cation) 126.1 543 T
2 F
-0.04 (The audience for this speci\336cation includes implementors of the architecture and de) 72 521 P
-0.04 (v) 473.52 521 P
-0.04 (elop-) 479.34 521 P
-0.08 (ers of SP) 72 507 P
-0.08 (ARC-V8E system softw) 114.07 507 P
-0.08 (are \050simulators, compilers, deb) 230.45 507 P
-0.08 (uggers, and operating sys-) 378.27 507 P
2.4 (tems, for e) 72 493 P
2.4 (xample\051. Softw) 127.61 493 P
2.4 (are de) 203.88 493 P
2.4 (v) 234.96 493 P
2.4 (elopers who need to write SP) 240.78 493 P
2.4 (ARC-V8E softw) 392 493 P
2.4 (are in) 474.61 493 P
(assembly language will also \336nd this information useful.) 72 479 T
0 F
(Wher) 72 435 T
(e to Start?) 101.11 435 T
2 F
-0.03 (If you are ne) 72 413 P
-0.03 (w to the SP) 132.58 413 P
-0.03 (ARC architecture, read) 186.39 413 P
335.23 411.8 300.26 411.8 2 L
V
0.6 H
0 Z
N
-0.03 (The SP) 300.26 413 P
476 411.8 334.13 411.8 2 L
V
N
-0.03 (ARC Architecture Manual, V) 334.13 413 P
504 411.8 474.67 411.8 2 L
V
N
-0.03 (ersion) 474.67 413 P
78 397.8 72 397.8 2 L
V
N
0.9 (8) 72 399 P
0.9 ( for background. Then look into the subsequent sections and anne) 78 399 P
0.9 (x) 401.81 399 P
0.9 (es of this document) 407.63 399 P
(for more details in areas of interest to you.) 72 385 T
0.71 (If you are already f) 72 363 P
0.71 (amiliar with SP) 166.66 363 P
0.71 (ARC-V8, you will w) 241.65 363 P
0.71 (ant to re) 344.32 363 P
0.71 (vie) 384.76 363 P
0.71 (w the list of ne) 399.12 363 P
0.71 (w fea-) 472.98 363 P
(tures listed belo) 72 349 T
(w and in the ne) 147.7 349 T
(xt section, Scope.) 220.84 349 T
0 F
(Speci\336cation Contents) 72 305 T
2 F
-0.12 (The \336rst section, Scope, describes the o) 72 283 P
-0.12 (v) 261.06 283 P
-0.12 (erall content of the document, and its relationship) 266.88 283 P
0.63 (to SP) 72 269 P
0.63 (ARC-V8E. Section 2, \322Instructions,) 97.2 269 P
0.63 (\323 re) 270.9 269 P
0.63 (vie) 288.88 269 P
0.63 (ws the Instruction Set Architecture \050ISA\051) 303.24 269 P
2.5 (Extensions and enhancements to ASI accessibility) 72 255 P
2.5 (. Section 3, \322Memory Management) 324.69 255 P
2 (Unit,) 72 241 P
2 (\323 is a description of the Memory Management Unit \050MMU\051, Section 4, \322T) 95.5 241 P
2 (raps\323,) 475.68 241 P
1.18 (describes the single-v) 72 227 P
1.18 (ector trapping features, Section 5, \322Peripheral Extensions\323, co) 178.16 227 P
1.18 (v) 484.19 227 P
1.18 (ers) 490.01 227 P
0.41 (T) 72 213 P
0.41 (imers, Counters, and Interrupt F) 78.91 213 P
0.41 (acilities, and Section 6, \322Diagnostic F) 234.38 213 P
0.41 (acilities\323 includes) 417.93 213 P
(instruction tracing, setting and using breakpoints, single stepping and emulation.) 72 199 T
1.28 (Anne) 72 185 P
1.28 (x) 97.81 185 P
1.28 (es follo) 103.63 185 P
1.28 (w the sections and include the follo) 140.27 185 P
1.28 (wing: Anne) 317.61 185 P
1.28 (x A, \322Programming T) 375.04 185 P
1.28 (ech-) 483.35 185 P
1.97 (niques\323, Anne) 72 171 P
1.97 (x B, \322) 142.44 171 P
1.97 (Alternati) 173.75 171 P
1.97 (v) 216.11 171 P
1.97 (e W) 221.93 171 P
1.97 (indo) 243.07 171 P
1.97 (w Usage Models\323, and Anne) 264.11 171 P
1.97 (x C, \322Summary of) 410.1 171 P
(Operation codes, ASI\325) 72 157 T
(s and ASR\325) 178.98 157 T
(s\323.) 233.65 157 T
0 F
(Ackno) 72 113 T
(wledgments) 105.22 113 T
2 F
0.63 (The members of the SP) 72 91 P
0.63 (ARC- V8 Embedded architecture committee, set up in December) 186.06 91 P
FMENDPAGE
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(3) 534 17 T
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0.4 (V8E architecture. Originators of v) 108 707 P
0.4 (arious sections of the initial draft speci\336cation include:) 273.58 707 P
(Frits Zandv) 108 693 T
(eld \050Philips\051 - Secretary) 163.49 693 T
(, MMU, Counters, T) 277.02 693 T
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-0.2 (McK) 108 679 P
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-0.2 (er \050Fujitsu\051- instructions, counters and timers, interrupt control, diagnostics; Anna) 148.54 679 P
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2.88 (es Roumazeilles) 458.79 665 P
1.25 (\050SA) 108 651 P
1.25 (GEM\051- Counters and timers; Cesar Douady \050MHS\051- general comments and instruc-) 126.85 651 P
(tions; Raf) 108 637 T
(ael Guzman \050TGI\051- Chair; Alain F) 154.88 637 T
(anet \050MHS\051- Chair) 319.67 637 T
(.) 409.66 637 T
1.19 (Additional contrib) 108 615 P
1.19 (utors and re) 197.28 615 P
1.19 (vie) 256 615 P
1.19 (wers include: Max Baron \050Sun\051; Edmund K) 270.36 615 P
1.19 (elly \050Sun\051-) 487.15 615 P
1.03 (MMU; Rudolf Usselman \050S-I\051- instructions; Les K) 108 601 P
1.03 (ohn \050Sun\051- e) 357.77 601 P
1.03 (v) 419.53 601 P
1.03 (aluation of bit\336eld pro-) 425.23 601 P
1.03 (posals; Da) 108 587 P
1.03 (vid W) 159.12 587 P
1.03 (ea) 188.85 587 P
1.03 (v) 199.27 587 P
1.03 (er \050Sun\051- interrupts, counters, timers, and o) 205.09 587 P
1.03 (v) 418.05 587 P
1.03 (erall editing and re) 423.87 587 P
1.03 (vie) 516.97 587 P
1.03 (w) 531.34 587 P
(support.) 108 573 T
-0.18 (Others who contrib) 108 551 P
-0.18 (uted either via the \322T) 200.05 551 P
-0.18 (ask F) 300.34 551 P
-0.18 (orce\323 to get the committee started or through) 325.64 551 P
-0.22 (the SP) 108 537 P
-0.22 (ARC-V8E Architecture Subcommittee to \336nalize and produce the \336nal speci\336cation) 137.69 537 P
-0.26 (include: J.J. Whelan \050S-I\051- Chair; Bruce McK) 108 523 P
-0.26 (ee) 325.45 523 P
-0.26 (v) 335.81 523 P
-0.26 (er \050Fujitsu\051; Craig Nelson \050LSI\051; Edmund) 341.63 523 P
(K) 108 509 T
(elly \050Sun\051; Mik) 116.36 509 T
(e Ray\336eld \050TI\051; and Dalibor Vrsalo) 190.25 509 T
(vic \050SunSoft\051.) 359.7 509 T
0.03 (Final consolidation of draft material and technical editing w) 108 487 P
0.03 (as pro) 396.08 487 P
0.03 (vided by Morris En\336eld) 424.92 487 P
(\050Enmor Associates\051 on contract to SP) 108 473 T
(ARC International.) 287.21 473 T
FMENDPAGE
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(SPARC-V8E) 72 748 T
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(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
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(4) 72 17 T
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FMENDPAGE
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(SPARC-V8E) 475.99 748 T
(1) 108 17 T
(Scope) 120 17 T
(5) 534 17 T
4 14 Q
(1 Scope) 292.43 645.67 T
3 12 Q
0.59 (This supplementary speci\336cation de\336nes a 32-bit enhanced SP) 108 601 P
0.59 (ARC-V8 arc) 458.4 601 P
0.59 (hi-) 524.89 601 P
0.26 (tecture called SP) 108 587 P
0.26 (ARC-V8E that is upw) 201.88 587 P
0.26 (ard-compatible with the existing 32-bit) 322.68 587 P
0.94 (SP) 108 573 P
0.94 (ARC-V8 processor arc) 122.9 573 P
0.94 (hitecture) 246.01 573 P
0.94 (. This speci\336cation inc) 296.23 573 P
0.94 (ludes) 422.08 573 P
0.94 (, but is not lim-) 451.33 573 P
0.45 (ited to) 108 559 P
0.45 (, the de\336nition of the enhanced instruction set, ASI access) 143.57 559 P
0.45 (, trap model,) 468.87 559 P
-0.19 (memory management unit, diagnostic facilities) 108 545 P
-0.19 (, and timers and counters) 368.1 545 P
-0.19 (. Spe-) 509.07 545 P
-0.02 (ci\336c implementations ma) 108 531 P
-0.02 (y selectively inc) 247.41 531 P
-0.02 (lude one or more of the speci\336ed sup-) 334.61 531 P
(plementary features and functions) 108 517 T
(.) 299.26 517 T
4 F
(1.1 SP) 108 479 T
(ARC-V8E Attributes) 151.67 479 T
3 F
-0.31 (SP) 108 457 P
-0.31 (ARC-V8E is a CPU) 122.9 457 P
4 F
-0.32 (instruction set architecture) 231.43 457 P
3 F
-0.31 ( \050ISA\051 and a) 403.68 457 P
4 F
-0.32 (set of facil-) 472.43 457 P
0.79 (ities) 108 443 P
3 F
0.77 ( to improve programmer control over processor beha) 134.88 443 P
0.77 (vior and to improve) 429.46 443 P
2.76 (processor responsiveness to the outside world in the context of embedded) 108 429 P
1.79 (applications) 108 415 P
1.79 (. It is derived from SP) 175.04 415 P
1.79 (ARC-V8. Both arc) 305.14 415 P
1.79 (hitectures come from a) 407.96 415 P
1.97 (reduced instruction set computer \050RISC\051 lineage) 108 401 P
1.97 (. As arc) 385.37 401 P
1.97 (hitectures) 430.78 401 P
1.97 (, SP) 486.47 401 P
1.97 (ARC-) 510.01 401 P
0.41 (V8E and SP) 108 387 P
0.41 (ARC-V8 provide a basis for a spectrum of c) 175.29 387 P
0.41 (hip and system imple-) 415.86 387 P
3.25 (mentations at a variety of price/performance points) 108 373 P
3.25 (. SP) 411.67 373 P
3.25 (ARC-V8E ma) 436.5 373 P
3.25 (y be) 514.3 373 P
1.91 (employed in a range of applications) 108 359 P
1.91 (, inc) 313.52 359 P
1.91 (luding most embedded applications) 338.46 359 P
1.63 (suc) 108 345 P
1.63 (h as real-time) 126.13 345 P
1.63 (, process control, medical, imaging) 206.29 345 P
1.63 (, digital telecommunica-) 403.18 345 P
1.36 (tions) 108 331 P
1.36 (, local area networking \050LAN\051, and other time-critical and dedicated or) 135.04 331 P
(embedded scienti\336c and commercial applications) 108 317 T
(.) 377.94 317 T
4 F
(1.1.1 Design Goals) 108 279 T
3 F
0.24 (SP) 108 257 P
0.24 (ARC-V8E, as speci\336ed, is a platform for optimizing and standardizing soft-) 122.9 257 P
0.78 (w) 108 243 P
0.78 (are systems) 117.12 243 P
0.78 (, diagnostic tools) 183.38 243 P
0.78 (, and high-performance hardw) 277.1 243 P
0.78 (are implementa-) 447.43 243 P
(tions) 108 229 T
(.) 135.04 229 T
4 F
(1.1.2 Architectural Enhancements) 108 191 T
3 F
-0.28 (SP) 108 169 P
-0.28 (ARC-V8E is derived from SP) 122.9 169 P
-0.28 (ARC-V8, whic) 280.69 169 P
-0.28 (h in turn is derived from SP) 358.1 169 P
-0.28 (ARC) 511.12 169 P
-0.28 (,) 536.66 169 P
1 (whic) 108 155 P
1 (h w) 133.69 155 P
1 (as formulated at Sun Microsystems in 1985. SP) 154.48 155 P
1 (ARC is based on the) 424.21 155 P
1.66 (RISC I & II designs engineered at the University of California at Berkeley) 108 141 P
1.65 (from 1980 through 1982. Enhancements ha) 108 127 P
1.65 (ve been made based on require-) 356.84 127 P
1.31 (ments for improved performance and lower cost of operation in time-critical) 108 113 P
(and dedicated processing environments) 108 99 T
(.) 326.36 99 T
FMENDPAGE
%%EndPage: "5" 11
%%Page: "6" 12
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(6) 72 17 T
(1) 462.67 17 T
(Scope) 474.67 17 T
3 F
1.32 (The arc) 72 721 P
1.32 (hitecture provides for a spectrum of input/output \050I/O\051 and memory-) 115.24 721 P
0.53 (management unit \050MMU\051 sub-arc) 72 707 P
0.53 (hitectures) 260.39 707 P
0.53 (. SP) 316.08 707 P
0.53 (ARC-V8E assumes that these) 338.18 707 P
0.81 (elements are best de\336ned by the speci\336c requirements of particular systems) 72 693 P
0.81 (.) 500.66 693 P
0.34 (Note that they are invisible to nearly all user programs) 72 679 P
0.34 (, and the interfaces to) 381.73 679 P
(them can be limited to localized modules in an associated operating system.) 72 665 T
4 F
(1.2 SP) 72 627 T
(ARC-V8E F) 115.67 627 T
(eatures) 184.44 627 T
3 F
(SP) 72 605 T
(ARC-V8E inc) 86.9 605 T
(ludes the following enhanced features:) 160.58 605 T
(\321) 90 561 T
(Divide Step Instruction:) 108 561 T
1.17 (The Divide Step instruction,) 126 539 P
4 F
1.21 (DIVScc) 291.14 539 P
3 F
1.17 (, provides for implementation) 336.7 539 P
(of an interruptible divide algorithm.) 126 525 T
(\321) 90 503 T
(Scan Instruction:) 108 503 T
3.03 (The Scan instruction,) 126 481 P
4 F
3.13 (SCAN) 257.77 481 P
3 F
3.03 (, provides the capability for quic) 293.56 481 P
3.03 (kly) 486.66 481 P
-0.22 (locating the \336rst bit set, c) 126 467 P
-0.22 (leared, or differing from the sign in a word.) 266.4 467 P
1.89 (Suc) 126 453 P
1.89 (h operations occur frequently in embedded systems) 146.14 453 P
1.89 (, especially) 441.21 453 P
(for sc) 126 439 T
(heduling and interrupt case detection.) 155.46 439 T
(\321) 90 417 T
(Multiply Accumulate Instruction:) 108 417 T
0.61 (The Multiply Accumulate instruction,) 126 395 P
4 F
0.63 (MAC) 341.35 395 P
3 F
0.61 (, enhances e) 371.12 395 P
0.61 (.g) 439.69 395 P
0.61 (. \050integer\051) 449.17 395 P
(fast F) 126 381 T
(ourier transform operations) 157.57 381 T
(.) 311.48 381 T
(\321) 90 359 T
(Alternate W) 108 359 T
(indow P) 176 359 T
(ointer Register:) 220.24 359 T
1.98 (The Alternate W) 126 337 P
1.98 (indow P) 222.63 337 P
1.98 (ointer Register) 268.83 337 P
1.98 (,) 352.49 337 P
4 F
2.04 (A) 361.14 337 P
2.04 (WP) 369.36 337 P
3 F
1.98 (, helps reducing the) 388.74 337 P
1.73 (amount of time a SP) 126 323 P
1.73 (ARC-V8E is not interruptible during register) 245.6 323 P
(sa) 126 309 T
(ve operations) 138.11 309 T
(.) 211.81 309 T
(\321) 90 287 T
(P) 108 287 T
(artial Write Program Status W) 115.56 287 T
(ord:) 287.3 287 T
1.05 (Write Program Status W) 126 265 P
1.05 (ord,) 266.65 265 P
4 F
1.08 (WRPSR) 292.58 265 P
3 F
1.05 (, with a special value for the) 341.03 265 P
-0.31 (rd \336eld allows atomic setting and resetting of the ET \336eld in the Pro-) 126 251 P
(gram Status W) 126 237 T
(ord.) 209.29 237 T
(\321) 90 215 T
(Non-Privileged ASI Access:) 108 215 T
1.32 (Allows LOAD and ST) 126 193 P
1.32 (ORE from Alternate space instruction access) 248.99 193 P
(to some ASI\325) 126 179 T
(s in user mode) 194.82 179 T
(.) 275.05 179 T
FMENDPAGE
%%EndPage: "6" 12
%%Page: "7" 13
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(1) 108 17 T
(Scope) 120 17 T
(7) 534 17 T
3 F
(\321) 126 721 T
(MMU:) 144 721 T
1.91 (Improvements ha) 162 699 P
1.91 (ve been made to the Reference MMU to provide) 261.57 699 P
6.03 (enhanced functionality while retaining compatibility with the) 162 685 P
(SP) 162 671 T
(ARC-V8 Reference MMU) 176.9 671 T
(.) 314.78 671 T
3.78 (The improvements inc) 162 649 P
3.78 (lude softw) 293.26 649 P
3.78 (are table w) 353.72 649 P
3.78 (alk, page protection) 422.86 649 P
0.26 (down to 1k bytes) 162 635 P
0.26 (, bypass of context number c) 255.84 635 P
0.26 (hec) 413.96 635 P
0.26 (king in the address) 432.54 635 P
(translation phase) 162 621 T
(, and TLB entry loc) 259.36 621 T
(king) 366.4 621 T
(.) 390.77 621 T
(\321) 126 599 T
(Traps:) 144 599 T
(A facility supporting single vector trapping has been provided.) 162 577 T
(\321) 126 555 T
(Interrupt Handlers:) 144 555 T
0.87 (A set of features to shape and prioritize interrupt signals has been) 162 533 P
(added.) 162 519 T
(\321) 126 497 T
(Timers/Counters/Pulsers:) 144 497 T
1.19 (Improved timer/counter/pulser facilities will be provided as part of) 162 475 P
(the P) 162 461 T
(eripheral Extensions expanded functionality) 190.9 461 T
(.) 436.07 461 T
(\321) 126 439 T
(Diagnostic F) 144 439 T
(acilities:) 213.46 439 T
2.6 (Initial diagnostic features ha) 162 417 P
2.6 (ve been provided based on Fujitsu\325) 330.6 417 P
2.6 (s) 534.44 417 P
(SP) 162 403 T
(ARCLite Debug Support Unit speci\336cation.) 176.9 403 T
4 F
(1.3 SP) 108 337 T
(ARC-V8E De\336nition) 151.67 337 T
3 F
0.81 (The SP) 108 319 P
0.81 (ARC V) 148.38 319 P
0.81 (ersion 8 embedded arc) 186.28 319 P
0.81 (hitecture) 312.62 319 P
0.81 (, SP) 362.84 319 P
0.81 (ARC-V8E, is de\336ned by the) 385.22 319 P
-0.25 (sections and normative annexes of this document. A correct implementation of) 108 305 P
0.84 (the arc) 108 291 P
0.84 (hitecture provides for execution of a program strictly according to the) 147.42 291 P
2.09 (rules and algorithms speci\336ed in the sections and normative annexes) 108 277 P
2.09 (. The) 509.9 277 P
2.74 (informative annexes provide supplementary information suc) 108 263 P
2.74 (h as program-) 456.96 263 P
0.35 (ming tips) 108 249 P
0.35 (, expected usage) 160.51 249 P
0.35 (, and assembly language syntax. These annexes are) 251.23 249 P
(not binding on an implementation or user of a SP) 108 235 T
(ARC-V8e system.) 380.94 235 T
1.42 (The Arc) 108 213 P
1.42 (hitecture Committee of SP) 153.33 213 P
1.42 (ARC International has sole responsibility) 304.06 213 P
(for c) 108 199 T
(lari\336cation of the de\336nitions in this document.) 131.9 199 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(8) 72 17 T
(1) 462.67 17 T
(Scope) 474.67 17 T
4 F
(1.4 SP) 72 721 T
(ARC-V8E Compliance) 115.67 721 T
3 F
2.93 (Compliance to this speci\336cation ma) 72 699 P
2.93 (y be c) 280.06 699 P
2.93 (laimed only by implementations) 316.95 699 P
2.34 (whic) 72 685 P
2.34 (h ha) 97.69 685 P
2.34 (ve been submitted to SP) 124.58 685 P
2.34 (ARC International for testing and whic) 267.52 685 P
2.34 (h) 496.67 685 P
3.63 (ha) 72 671 P
3.63 (ve been issued a certi\336cate of compliance) 85.88 671 P
3.63 (. T) 334.57 671 P
3.63 (esting and certi\336cation of) 352.22 671 P
0.71 (SP) 72 657 P
0.71 (ARC-V8E compliance requires that the implementation also be tested and) 86.9 657 P
0.54 (certi\336ed as SP) 72 643 P
0.54 (ARC-V8 compliant with the exception of SP) 152.21 643 P
0.54 (ARC-V8E function-) 396.37 643 P
(ality whic) 72 629 T
(h differs from SP) 126.37 629 T
(ARC-V8.) 220.15 629 T
0.24 (A compliant implementation need not implement all of the features described) 72 607 P
0.59 (in section 1.2 or Annex D of this document. Eac) 72 593 P
0.59 (h of the features identi\336ed in) 339.7 593 P
0.35 (section 1.2 or Annex D can be individually implemented and certi\336ed as com-) 72 579 P
2.19 (pliant. In order for a feature to be so certi\336ed it must be implemented as) 72 565 P
-0.11 (de\336ned in this document. Claims of compliance to this speci\336cation must ha) 72 551 P
-0.11 (ve) 491.56 551 P
-0.23 (the form, \322Compliant to SP) 72 537 P
-0.23 (ARC-V8E, Release 1 <feature list>\323 where <feature) 220.44 537 P
0.25 (list> is the list of features certi\336ed as tested to be compliant by SP) 72 523 P
0.25 (ARC Inter-) 442.21 523 P
0.14 (national. Compliance to SP) 72 509 P
0.14 (ARC-V8E must not be c) 222.67 509 P
0.14 (laimed without the feature) 354.68 509 P
(list.) 72 495 T
0.53 (Annex D of this document formally lists all features and their legal combina-) 72 473 P
(tions) 72 459 T
(.) 99.04 459 T
0.83 (Prior to compliance testing) 72 437 P
0.83 (, a statement must be submitted to SP) 223.53 437 P
0.83 (ARC Inter-) 441.63 437 P
(national for eac) 72 423 T
(h implementation that:) 158.15 423 T
(\321) 90 401 T
3.8 (speci\336es the individual features and functions of this speci\336cation) 108 401 P
(selected for implementation and to be tested for compliance) 108 387 T
(\321) 90 365 T
1.6 (speci\336es the implementation c) 108 365 P
1.6 (hoice for all implementation dependen-) 280.72 365 P
(cies) 108 351 T
(\321) 90 329 T
(speci\336es any subsetting of function as allowed by this document) 108 329 T
1.41 (This information becomes the property of SP) 72 307 P
1.41 (ARC International and ma) 327.36 307 P
1.41 (y be) 480.14 307 P
(released public) 72 293 T
(ly as part of a list of compliant implementations) 155.26 293 T
(.) 421.01 293 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(2) 108 17 T
(Instructions) 120 17 T
(9) 534 17 T
4 14 Q
(2 Instructions) 269.11 623.67 T
3 12 Q
0.39 (The following instructions and Non-Privileged ASI access ha) 108 579 P
0.39 (ve been added to) 446.38 579 P
0.81 (SP) 108 565 P
0.81 (ARC-V8 in order to improve performance and provide additional function-) 122.9 565 P
2.1 (ality especially for embedded, time critical applications) 108 551 P
2.1 (. Divide Step) 425.67 551 P
2.1 (, Scan,) 501 551 P
0.5 (and ASI Non-Privileged access ma) 108 537 P
0.5 (y be inc) 300.56 537 P
0.5 (luded individually or in any combi-) 343.7 537 P
(nation for implementation in a SP) 108 523 T
(ARC-V8E implementation.) 296.71 523 T
FMENDPAGE
%%EndPage: "9" 15
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(10) 72 17 T
(2) 435.34 17 T
(Instructions) 447.34 17 T
4 F
(2.1 Divide Step) 72 721 T
3 F
(F) 72 643 T
(ormat \0503\051:) 79.34 643 T
4 F
(Description:) 72 481.51 T
3 F
0.14 (The DIVScc instruction performs one bit-cyc) 72 459.51 P
0.14 (le of a non-restoring) 318.17 459.51 P
0.14 (, shift-before-) 429.86 459.51 P
0.1 (add, signed or unsigned division. Initially) 72 445.51 P
0.1 (, the more signi\336cant half of the div-) 301.49 445.51 P
0.38 (idend is in the Y register) 72 431.51 P
0.38 (, the less signi\336cant 32 bits are in r[) 210.27 431.51 P
5 F
0.38 (r) 412.91 431.51 P
0.38 (s1) 418.12 431.51 P
3 F
0.38 (]. The divisor) 430.12 431.51 P
0.11 (is in r[) 72 417.51 P
5 F
0.11 (r) 108.67 417.51 P
0.11 (s2) 113.88 417.51 P
3 F
0.11 (]. Subsequently) 125.88 417.51 P
0.11 (, the more signi\336cant half of the partial remainder is) 210.51 417.51 P
0.47 (in the Y register) 72 403.51 P
0.47 (, the less signi\336cant half is in r[) 162.89 403.51 P
5 F
0.47 (r) 341.55 403.51 P
0.47 (s1) 346.76 403.51 P
3 F
0.47 (], along with another quo-) 358.76 403.51 P
(tient bit.) 72 389.51 T
(DIVScc operates as follows:) 72 345.51 T
(\0501\051) 90 323.51 T
0.72 (The) 108 323.51 P
5 F
0.72 (true sign) 133.4 323.51 P
3 F
0.72 ( is formed using the negative \050n\051 and over\337ow \050v\051 integer) 182.77 323.51 P
(condition codes from the Processor Status Register) 108 309.51 T
(.) 387.68 309.51 T
(True sign= PSR.n) 108 287.51 T
4 F
(xor) 209.95 287.51 T
3 F
( PSR.v) 230.84 287.51 T
(.) 266.69 287.51 T
(\0502\051) 90 265.51 T
2.02 (The) 108 265.51 P
5 F
2.02 (remainder) 134.69 265.51 P
3 F
2.02 ( is formed by left shifting the Y register \050initially the) 192.22 265.51 P
0.05 (more signi\336cant word of the dividend\051 one bit, and setting the least sig-) 108 251.51 P
1.04 (ni\336cant bit of the remainder equal to the most signi\336cant bit of r[) 108 237.51 P
5 F
1.04 (r) 482.8 237.51 P
1.04 (s1) 488 237.51 P
3 F
1.04 (]) 500 237.51 P
(\050initially the less signi\336cant word of the dividend\051.) 108 223.51 T
(\0503\051) 90 201.51 T
1.2 (The) 108 201.51 P
5 F
1.2 (divisor) 133.87 201.51 P
3 F
1.2 ( is r[) 172.08 201.51 P
5 F
1.2 (r) 199.8 201.51 P
1.2 (s2) 205.01 201.51 P
3 F
1.2 (] if the) 217.01 201.51 P
5 F
1.2 (i) 260.39 201.51 P
3 F
1.2 ( \336eld is 0, or) 264.38 201.51 P
5 F
1.2 (simm13) 341.72 201.51 P
3 F
1.2 (, sign-extended to 32) 385.72 201.51 P
(bits) 108 187.51 T
(, if the) 128.38 187.51 T
5 F
(i) 167.5 187.51 T
3 F
( \336eld is 1.) 171.49 187.51 T
(\0504\051) 90 165.51 T
1.92 (If) 108 165.51 P
5 F
1.92 (true sign) 122.14 165.51 P
3 F
1.92 ( = 0 \050) 172.71 165.51 P
3 14 Q
2.24 (+) 206.42 165.51 P
3 12 Q
1.92 (\051, the ALU computes) 214.9 165.51 P
5 F
1.92 (\050remainder) 340.15 165.51 P
3 14 Q
2.24 (-) 406.93 165.51 P
5 12 Q
1.92 (divisor\051) 416.85 165.51 P
3 F
1.92 (. If) 459.06 165.51 P
5 F
1.92 (true) 481.79 165.51 P
(sign) 108 151.51 T
3 F
(=) 134.44 151.51 T
(1) 145.04 151.51 T
(\050) 155.05 151.51 T
3 14 Q
(-) 159.05 151.51 T
3 12 Q
(\051, the ALU computes) 163.71 151.51 T
5 F
(\050remainder) 281.27 151.51 T
3 14 Q
(+) 346.13 151.51 T
5 12 Q
(divisor\051) 357.95 151.51 T
3 F
(.) 400.16 151.51 T
(\0505\051) 90 129.51 T
0.33 (Carry-out from the ALU operation is noted as c0. The negative \050n\051 con-) 108 129.51 P
0.04 (dition code is set to bit 31 of the ALU result. The zero \050z\051 condition code) 108 115.51 P
0.25 (is set if the ALU result is 0 and the) 108 101.51 P
5 F
0.25 (true sign) 309.19 101.51 P
3 F
0.25 ( equals Y[31], otherwise it) 358.08 101.51 P
(is c) 108 87.51 T
(leared.) 125.92 87.51 T
0 10 Q
(opcode) 149 684.33 T
(op3) 228.22 684.33 T
(operation) 339.45 684.33 T
2 F
(DIVScc) 134 669.33 T
(011101) 221 669.33 T
(Di) 278 669.33 T
(vide Step \050and modify cc\325) 287.75 669.33 T
(s\051) 391.07 669.33 T
0 F
(Suggested Assembly Language Syntax) 206.46 522.84 T
2 F
(di) 154 507.84 T
(vscc) 161.53 507.84 T
1 F
(r) 226 507.84 T
(e) 229.52 507.84 T
(g) 233.56 507.84 T
1 8 Q
(r) 238.56 505.34 T
(s1) 241.59 505.34 T
1 10 Q
(, r) 248.7 507.84 T
(e) 257.22 507.84 T
(g_or_imm, r) 261.26 507.84 T
(e) 310.89 507.84 T
(g) 314.93 507.84 T
1 8 Q
(r) 319.93 505.34 T
(d) 322.75 505.34 T
128 694.75 128 665.25 2 L
V
0.5 H
0 Z
N
200 695.25 200 664.75 2 L
V
N
272 695.25 272 664.75 2 L
V
N
448 694.75 448 665.25 2 L
V
N
127.75 695 448.25 695 2 L
V
N
128.25 681.25 447.75 681.25 2 L
V
N
128.25 678.75 447.75 678.75 2 L
V
N
127.75 665 448.25 665 2 L
V
N
148 533.26 148 503.76 2 L
V
N
220 517.01 220 503.26 2 L
V
N
428 533.26 428 503.76 2 L
V
N
147.75 533.51 428.25 533.51 2 L
V
N
148.25 519.76 427.75 519.76 2 L
V
N
148.25 517.26 427.75 517.26 2 L
V
N
147.75 503.51 428.25 503.51 2 L
V
N
72 81 504 729 C
72 555.51 504 639 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 76.05 566.47 T
(14) 304.65 566.47 T
(19) 237.02 566.47 T
(24) 170.73 566.47 T
(18) 250.54 566.47 T
(13) 318.17 566.47 T
(12) 331.7 566.47 T
(5) 428.6 566.47 T
(4) 442.12 566.47 T
(0) 495.56 566.47 T
(25) 157.2 566.47 T
(30) 88.24 566.47 T
(29) 101.76 566.47 T
75 605.65 500.33 628.16 R
7 X
V
1 H
0 Z
0 X
N
100.19 627.57 100.19 606.58 2 L
7 X
V
0.5 H
2 Z
0 X
N
168.19 627.57 168.19 606.57 2 L
7 X
V
0 X
N
248.86 627.57 248.86 606.57 2 L
7 X
V
0 X
N
316.19 627.57 316.19 606.57 2 L
7 X
V
0 X
N
330.19 627.57 330.19 606.57 2 L
7 X
V
0 X
N
437.52 627.57 437.52 606.57 2 L
7 X
V
0 X
N
(10) 83.32 615.95 T
(op3) 202.38 615.95 T
7 F
(un) 356.39 615.95 T
(used) 365.21 615.95 T
6 F
( \050) 382.55 615.95 T
7 F
(z) 387.44 615.95 T
(ero) 391.32 615.95 T
6 F
(\051) 402.88 615.95 T
(rd) 131.36 615.95 T
(rs1) 278.64 615.95 T
(i=0) 317.51 615.95 T
(rs2) 465.36 615.95 T
75 574.32 500.33 596.83 R
7 X
V
1 H
0 Z
0 X
N
100.19 596.24 100.19 575.24 2 L
7 X
V
0.5 H
2 Z
0 X
N
168.19 596.24 168.19 575.24 2 L
7 X
V
0 X
N
248.86 596.24 248.86 575.24 2 L
7 X
V
0 X
N
316.19 596.24 316.19 575.24 2 L
7 X
V
0 X
N
330.19 596.24 330.19 575.24 2 L
7 X
V
0 X
N
(10) 83.32 584.62 T
(op3) 202.38 584.62 T
(rd) 131.36 584.62 T
(rs1) 278.64 584.62 T
(i=1) 317.51 584.62 T
(simm13) 399.92 583.47 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "10" 16
%%Page: "11" 17
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(2) 108 17 T
(Instructions) 120 17 T
(11) 528 17 T
3 F
(\0506\051) 126 721 T
1.55 (The) 144 721 P
5 F
1.55 (new true sign) 170.22 721 P
3 F
1.55 ( is formed as \050) 247.3 721 P
5 F
1.55 (true sign) 331.28 721 P
4 F
1.6 (and not) 386.36 721 P
3 F
1.55 (Y[31]\051) 440.51 721 P
4 F
1.6 (or \050not) 479.18 721 P
3 F
1.55 ( c0) 523.11 721 P
4 F
(and) 144 707 T
3 F
( \050) 167.56 707 T
5 F
(true sign) 174.89 707 T
4 F
(or not) 226.87 707 T
3 F
(Y[31]\051\051) 267.98 707 T
(\0507\051) 126 685 T
0.33 (The over\337ow \050v\051 condition code is formed as) 144 685 P
5 F
0.33 (new true sign) 391.33 685 P
4 F
0.34 (xor) 469.64 685 P
3 F
0.33 (bit 31 of) 494.2 685 P
0.16 (the ALU result. The carry \050c\051 condition code is set to) 144 671 P
4 F
0.17 (not) 438.2 671 P
5 F
0.16 (new true sign) 462.36 671 P
3 F
0.16 (.) 536.66 671 P
1.29 (Y is set to the 32-bit ALU result. If r[) 144 657 P
5 F
1.29 (rd) 361.44 657 P
3 F
1.29 (] is not 0, then r[) 374.1 657 P
5 F
1.29 (rd) 473.23 657 P
3 F
1.29 (] is set to) 485.89 657 P
0.33 (r[) 144 643 P
5 F
0.33 (r) 153.32 643 P
0.33 (s1) 158.53 643 P
3 F
0.33 (], left shifted one bit with) 170.53 643 P
4 F
0.34 (not) 316.11 643 P
5 F
0.33 (new true sign) 340.44 643 P
3 F
0.33 ( \050the new quotient bit\051) 415.09 643 P
(in the least signi\336cant bit position.) 144 629 T
3 10 Q
(Note:) 108 604.33 T
0.16 (Usage of DIVScc in other algorithms than in a division algorithm is not advised. This) 144 592.33 P
(same w) 144 580.33 T
(arning applies to MULScc in SP) 178.46 580.33 T
(ARC V) 326.08 580.33 T
(ersion 8 and V) 356.99 580.33 T
(ersion 9.) 423.1 580.33 T
4 12 Q
(Register Manipulation Description:) 108 555 T
3 F
0.64 (Divide step performs one bit cyc) 108 533 P
0.64 (le of a non-restoring) 288.44 533 P
0.64 (, shift-before-add, signed) 401.61 533 P
1.77 (or unsigned division. It operates on a signed or unsigned dividend with an) 108 519 P
3.2 (unsigned divisor) 108 505 P
3.2 (. It uses standard condition code bits to carry true sign,) 201.77 505 P
1.02 (remainder) 108 491 P
1.02 (, and previous quotient bit information from one cyc) 164.8 491 P
1.02 (le to the next.) 460.69 491 P
1.75 (Therefore) 108 477 P
1.75 (, standard SP) 161.77 477 P
1.75 (ARC instructions are suf\336cient for correct initializa-) 240.19 477 P
1.48 (tion for signed or unsigned divide) 108 463 P
1.48 (, eliminating the need for a special divide) 300.73 463 P
0.59 (initialize instruction. Use of shift-before-add and the functional equivalent of) 108 449 P
1.52 (33rd- bit add/subtract maintains remainder and quotient in correct relative) 108 435 P
-0.07 (position with respect to their holding registers) 108 421 P
-0.07 (, eliminating the need for a spe-) 364.18 421 P
0.06 (cial divide terminate instruction to shift the last quotient without shifting the) 108 407 P
(last remainder) 108 393 T
(.) 188.81 393 T
2.66 (F) 108 349 P
2.66 (or non-over\337ow divisions) 115.34 349 P
2.66 (, the non-restoring division lea) 258.58 349 P
2.66 (ves a last partial) 438.88 349 P
-0.32 (remainder bounded by: absolute divisor) 108 335 P
3 14 Q
-0.37 (-) 329.1 335 P
3 12 Q
-0.32 ( 1 \050|divisor|) 333.76 335 P
3 14 Q
-0.37 (-) 405.8 335 P
3 12 Q
-0.32 ( 1\051, and,) 410.46 335 P
3 14 Q
-0.37 (-) 457.74 335 P
3 12 Q
-0.32 ( absolute divi-) 462.4 335 P
2.08 (sor \050) 108 321 P
3 14 Q
2.42 (-) 134.29 321 P
3 12 Q
2.08 (|divisor|\051. W) 138.96 321 P
2.08 (ith true sign last partial remainder carried by standard) 215.57 321 P
0.03 (condition code bits) 108 307 P
0.03 (, standard SP) 210.43 307 P
0.03 (ARC instructions are suf\336cient to produce the) 285.4 307 P
2.48 (correct remainder) 108 293 P
2.48 (, eliminating the need for a special remainder correction) 208.59 293 P
(instruction.) 108 279 T
3 10 Q
(Note:) 108 254.33 T
1.62 (Expected use of divide step will ha) 144 242.33 P
1.62 (ve r[) 313.05 242.33 P
5 F
1.62 (rd) 335.58 242.33 P
3 F
1.62 (] = r[) 346.13 242.33 P
5 F
1.62 (r) 372.08 242.33 P
1.62 (s1) 376.42 242.33 P
3 F
1.62 (]. A useful exception is the \336rst) 386.42 242.33 P
0.11 (divide step of 32 by 32 signed division, whic) 144 230.33 P
0.11 (h preserves the original dividend for later) 346.54 230.33 P
(testing by r[) 144 218.33 T
5 F
(rd) 200.3 218.33 T
3 F
(] = r[) 210.85 218.33 T
5 F
(r) 233.57 218.33 T
(s1) 237.91 218.33 T
3 F
(].) 247.91 218.33 T
4 12 Q
(T) 108 193 T
(raps:) 116.45 193 T
3 F
(none) 144 171 T
FMENDPAGE
%%EndPage: "11" 17
%%Page: "12" 18
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(12) 72 17 T
(2) 435.34 17 T
(Instructions) 447.34 17 T
4 F
(2.2 Scan) 72 721 T
3 F
(F) 72 643 T
(ormat \0503\051:) 79.34 643 T
4 F
(Description:) 72 481.51 T
3 F
1.81 (The SC) 72 459.51 P
1.81 (AN instruction can be used to return the location of the \336rst) 114.49 459.51 P
1.81 ( bit in) 467.48 459.51 P
0.44 (r[) 72 445.51 P
5 F
0.44 (r) 81.32 445.51 P
0.44 (s1) 86.53 445.51 P
3 F
0.44 (] that differs from its most-signi\336cant bit or the location of the \336rst 1 bit) 98.53 445.51 P
(or \336rst 0 bit of source register r[) 72 431.51 T
5 F
(r) 249.32 431.51 T
(s1) 254.53 431.51 T
3 F
(].) 266.53 431.51 T
(SC) 72 409.51 T
(AN works as follows:) 88.01 409.51 T
(\0501\051) 90 387.51 T
3.6 (The value in r[) 108 387.51 P
5 F
3.6 (r) 200.8 387.51 P
3.6 (s1) 206 387.51 P
3 F
3.6 (] is \322) 218 387.51 P
4 F
3.71 (xored) 249.87 387.51 P
3 F
3.6 (\323 on a bit-wise basis with the mask) 285.65 387.51 P
1.63 (obtained by shifting right by one bit and sign-extending the value in) 108 373.51 P
(r[) 108 359.51 T
5 F
(r) 117.32 359.51 T
(s2) 122.53 359.51 T
3 F
(] if the) 134.53 359.51 T
5 F
(i) 174.31 359.51 T
3 F
( \336eld is 0, or with sign_ext\050) 178.31 359.51 T
5 F
(simm13) 328.33 359.51 T
3 F
(\051 if the) 372.34 359.51 T
5 F
( i) 408.78 359.51 T
3 F
( \336eld is 1.) 416.11 359.51 T
(\0502\051) 90 337.51 T
2.01 (The number of the bit position of the \336rst \3221\323 in the result from \0501\051) 108 337.51 P
1.11 (above is returned to the destination register r[) 108 323.51 P
5 F
1.11 (rd) 372.89 323.51 P
3 F
1.11 (]. Bit numbers range) 385.55 323.51 P
0.98 (from 0 for the most signi\336cant bit to 31 for the least signi\336cant bit. A) 108 309.51 P
-0.07 (\3221\323 in the most signi\336cant bit \050MSB\051 position returns a value of 0, while) 108 295.51 P
0.15 (the \336rst \3221\323 in the least signi\336cant bit \050LSB\051 position returns a value of) 108 281.51 P
0.66 (31. If no bit is set \050the two operands are identical\051, an implementation) 108 267.51 P
2.46 (dependent unsigned value greater than or equal to 32 is written to) 108 253.51 P
(r[) 108 239.51 T
5 F
(rd) 117.32 239.51 T
3 F
(].) 129.98 239.51 T
3 10 Q
(Implementation notes:) 72 214.84 T
0.24 (Use of an unsigned value with bit 31 set \050but in any case greater than or equal to 64\051) 108 202.84 P
1.17 (is recommended for use in new implementations) 108 190.84 P
1.17 (.The opcode for Scan is op=2, op3=) 338.33 190.84 P
(2C) 108 178.84 T
(. The Scan instruction con\337icts with SP) 120.41 178.84 T
(ARC V) 302.1 178.84 T
(ersion 9 opcode for MO) 333.01 178.84 T
(Vcc) 438.75 178.84 T
(.) 454.67 178.84 T
(Programming Note:) 72 154.84 T
-0.28 (F) 108 142.84 P
-0.28 (or portability) 114.12 142.84 P
-0.28 (, softw) 173.71 142.84 P
-0.28 (are must perform unsigned comparisons with the result produced) 203.45 142.84 P
(by SC) 108 130.84 T
(AN) 135.05 130.84 T
(, since SC) 149.87 130.84 T
(AN ma) 194.88 130.84 T
(y return a value with bit 31 set to \3241\325.) 227.38 130.84 T
4 12 Q
(T) 72 105.51 T
(raps:) 80.45 105.51 T
3 F
(none) 108 91.51 T
0 10 Q
(opcode) 138.58 684.33 T
(op3) 217.8 684.33 T
(operation) 339.45 684.33 T
2 F
(SCAN) 123.58 669.33 T
(101100) 210.58 669.33 T
(scan for \336rst occurrence of \3241\325 or \3240\325 bit) 280.3 669.33 T
0 F
(Suggested Assembly Language Syntax) 206.46 522.84 T
2 F
(scan) 154 507.84 T
1 F
(r) 226 507.84 T
(e) 229.52 507.84 T
(g) 233.56 507.84 T
1 8 Q
(r) 238.56 505.34 T
(s1) 241.59 505.34 T
1 10 Q
(, r) 248.7 507.84 T
(e) 257.22 507.84 T
(g_or_imm, r) 261.26 507.84 T
(e) 310.89 507.84 T
(g) 314.93 507.84 T
1 8 Q
(r) 319.93 505.34 T
(d) 322.75 505.34 T
117.58 694.75 117.58 665.25 2 L
V
0.5 H
0 Z
N
189.58 695.25 189.58 664.75 2 L
V
N
261.58 695.25 261.58 664.75 2 L
V
N
458.42 694.75 458.42 665.25 2 L
V
N
117.33 695 458.67 695 2 L
V
N
117.83 681.25 458.17 681.25 2 L
V
N
117.83 678.75 458.17 678.75 2 L
V
N
117.33 665 458.67 665 2 L
V
N
148 533.26 148 503.76 2 L
V
N
220 517.01 220 503.26 2 L
V
N
428 533.26 428 503.76 2 L
V
N
147.75 533.51 428.25 533.51 2 L
V
N
148.25 519.76 427.75 519.76 2 L
V
N
148.25 517.26 427.75 517.26 2 L
V
N
147.75 503.51 428.25 503.51 2 L
V
N
72 81 504 729 C
72 555.51 504 639 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 76.05 566.47 T
(14) 304.65 566.47 T
(19) 237.02 566.47 T
(24) 170.73 566.47 T
(18) 250.54 566.47 T
(13) 318.17 566.47 T
(12) 331.7 566.47 T
(5) 428.6 566.47 T
(4) 442.12 566.47 T
(0) 495.56 566.47 T
(25) 157.2 566.47 T
(30) 88.24 566.47 T
(29) 101.76 566.47 T
75 605.65 500.33 628.16 R
7 X
V
1 H
0 Z
0 X
N
100.19 627.57 100.19 606.58 2 L
7 X
V
0.5 H
2 Z
0 X
N
168.19 627.57 168.19 606.57 2 L
7 X
V
0 X
N
248.86 627.57 248.86 606.57 2 L
7 X
V
0 X
N
316.19 627.57 316.19 606.57 2 L
7 X
V
0 X
N
330.19 627.57 330.19 606.57 2 L
7 X
V
0 X
N
437.52 627.57 437.52 606.57 2 L
7 X
V
0 X
N
(10) 83.32 615.95 T
(op3) 202.38 615.95 T
7 F
(un) 356.39 615.95 T
(used) 365.21 615.95 T
6 F
( \050) 382.55 615.95 T
7 F
(z) 387.44 615.95 T
(ero) 391.32 615.95 T
6 F
(\051) 402.88 615.95 T
(rd) 131.36 615.95 T
(rs1) 278.64 615.95 T
(i=0) 317.51 615.95 T
(rs2) 465.36 615.95 T
75 574.32 500.33 596.83 R
7 X
V
1 H
0 Z
0 X
N
100.19 596.24 100.19 575.24 2 L
7 X
V
0.5 H
2 Z
0 X
N
168.19 596.24 168.19 575.24 2 L
7 X
V
0 X
N
248.86 596.24 248.86 575.24 2 L
7 X
V
0 X
N
316.19 596.24 316.19 575.24 2 L
7 X
V
0 X
N
330.19 596.24 330.19 575.24 2 L
7 X
V
0 X
N
(10) 83.32 584.62 T
(op3) 202.38 584.62 T
(rd) 131.36 584.62 T
(rs1) 278.64 584.62 T
(i=1) 317.51 584.62 T
(simm13) 399.92 583.47 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "12" 18
%%Page: "13" 19
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(2) 108 17 T
(Instructions) 120 17 T
(13) 528 17 T
4 F
(2.3 Mac) 108 721 T
3 F
(F) 108 574 T
(ormat \0503\051:) 115.34 574 T
4 F
(Description:) 108 367.51 T
3 F
0.03 (These instructions use ASRxx \050xx tbd\051, Y and ASRyy \050yy tbd\051 as an accumula-) 108 345.51 P
-0.01 (tor) 108 331.51 P
-0.01 (, ASRxx being the most signi\336cant word, Y the middle word and ASRyy the) 122.8 331.51 P
(least signi\336cant word.) 108 317.51 T
2.75 (The product of both operands is computed as for the corresponding MUL) 108 295.51 P
3.62 (instructions) 108 281.51 P
3.62 (, but the result is operand1*operand2+ASRxx|Y|ASRyy) 174.36 281.51 P
3.62 (. This) 505.03 281.51 P
1.26 (result is stored in ASRxx \050most signi\336cant word\051, Y \050middle word\051 and both) 108 267.51 P
(r[rd] and ASRyy \050least signi\336cant word\051.) 108 253.51 T
1.59 (The width of ASRxx is implementation dependant. Its size can be observed) 108 231.51 P
0.7 (from the softw) 108 217.51 P
0.7 (are by writing full 1\325) 189.41 217.51 P
0.7 (s in it and reading bac) 305.07 217.51 P
0.7 (k to see set bits) 432.31 217.51 P
0.7 (. In) 520.41 217.51 P
1.57 (particular) 108 203.51 P
1.57 (, ASRxx ma) 162.58 203.51 P
1.57 (y contains no bits at all, in whic) 230.73 203.51 P
1.57 (h case RDASRxx will) 417.93 203.51 P
(return 0.) 108 189.51 T
0.08 (UMAC and SMAC do not affect the condition code bits) 108 167.51 P
0.08 (. UMACcc and SMACcc) 409.55 167.51 P
(set the condition codes the following w) 108 153.51 T
(a) 320.69 153.51 T
(y) 327.24 153.51 T
(:) 337.02 153.51 T
0.65 (N) 108 131.51 P
0.65 (, Z) 117.12 131.51 P
0.65 (: As speci\336ed in V8, but replacing \322product\323 by \322result\323 \050i.e) 135.11 131.51 P
0.65 (. the accumu-) 464.04 131.51 P
(lated result\051.) 108 117.51 T
(V) 108 95.51 T
(, C) 115.16 95.51 T
(: The condition out of the \336nal addition, i.e) 133.84 95.51 T
(.) 369.66 95.51 T
(the result is computed on 1) 376.33 95.51 T
4 10 Q
(opcode) 181.57 684.33 T
(op3) 262.74 684.33 T
(operation) 370.63 684.33 T
3 F
(UMAC) 170 669.33 T
(tbd) 264.4 669.33 T
(Multiply and accumulate unsigned) 314 669.33 T
(UMACcc) 170 654.33 T
(tbd) 264.4 654.33 T
0.96 (Multiply and accumulate unsigned) 314 654.33 P
(and modify cc) 314 642.33 T
(SMAC) 170 627.33 T
(tbd) 264.4 627.33 T
(Multiply and accumulate signed) 314 627.33 T
(SMACcc) 170 612.33 T
(tbd) 264.4 612.33 T
5.03 (Multiply and accumulate signed) 314 612.33 P
(and modify cc) 314 600.33 T
4 F
(Suggested Assembly Language Syntax) 224.98 453.84 T
3 F
(umac) 190 438.84 T
5 F
(reg) 262 438.84 T
5 8 Q
(r) 276.25 436.34 T
(s1) 279.72 436.34 T
5 10 Q
(, reg_or_imm, reg) 287.72 438.84 T
5 8 Q
(rd) 367.89 436.34 T
3 10 Q
(umaccc) 190 423.84 T
5 F
(reg) 262 423.84 T
5 8 Q
(r) 276.25 421.34 T
(s1) 279.72 421.34 T
5 10 Q
(, reg_or_imm, reg) 287.72 423.84 T
5 8 Q
(rd) 367.89 421.34 T
3 10 Q
(smac) 190 408.84 T
5 F
(reg) 262 408.84 T
5 8 Q
(r) 276.25 406.34 T
(s1) 279.72 406.34 T
5 10 Q
(, reg_or_imm, reg) 287.72 408.84 T
5 8 Q
(rd) 367.89 406.34 T
3 10 Q
(smaccc) 190 393.84 T
5 F
(reg) 262 393.84 T
5 8 Q
(r) 276.25 391.34 T
(s1) 279.72 391.34 T
5 10 Q
(, reg_or_imm, reg) 287.72 393.84 T
5 8 Q
(rd) 367.89 391.34 T
164 694.75 164 596.25 2 L
V
0.5 H
0 Z
N
236 695.25 236 595.75 2 L
V
N
308 695.25 308 595.75 2 L
V
N
484 694.75 484 596.25 2 L
V
N
163.75 695 484.25 695 2 L
V
N
164.25 681.25 483.75 681.25 2 L
V
N
164.25 678.75 483.75 678.75 2 L
V
N
163.75 596 484.25 596 2 L
V
N
184 464.26 184 389.76 2 L
V
N
256 448.01 256 389.26 2 L
V
N
464 464.26 464 389.76 2 L
V
N
183.75 464.51 464.25 464.51 2 L
V
N
184.25 450.76 463.75 450.76 2 L
V
N
184.25 448.26 463.75 448.26 2 L
V
N
183.75 389.51 464.25 389.51 2 L
V
N
108 81 540 729 C
108 486.51 540 570 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 112.05 497.47 T
(14) 340.65 497.47 T
(19) 273.02 497.47 T
(24) 206.73 497.47 T
(18) 286.55 497.47 T
(13) 354.17 497.47 T
(12) 367.7 497.47 T
(5) 464.6 497.47 T
(4) 478.12 497.47 T
(0) 531.56 497.47 T
(25) 193.2 497.47 T
(30) 124.24 497.47 T
(29) 137.76 497.47 T
111 536.65 536.33 559.16 R
7 X
V
1 H
0 Z
0 X
N
136.19 558.57 136.19 537.58 2 L
7 X
V
0.5 H
2 Z
0 X
N
204.19 558.57 204.19 537.57 2 L
7 X
V
0 X
N
284.86 558.57 284.86 537.57 2 L
7 X
V
0 X
N
352.19 558.57 352.19 537.57 2 L
7 X
V
0 X
N
366.19 558.57 366.19 537.57 2 L
7 X
V
0 X
N
473.52 558.57 473.52 537.57 2 L
7 X
V
0 X
N
(tbd) 118.21 546.95 T
(op3) 238.38 546.95 T
7 F
(un) 392.39 546.95 T
(used) 401.21 546.95 T
6 F
( \050) 418.55 546.95 T
7 F
(z) 423.44 546.95 T
(ero) 427.32 546.95 T
6 F
(\051) 438.88 546.95 T
(rd) 167.36 546.95 T
(rs1) 314.64 546.95 T
(i=0) 353.51 546.95 T
(rs2) 501.36 546.95 T
111 505.32 536.33 527.83 R
7 X
V
1 H
0 Z
0 X
N
136.19 527.24 136.19 506.24 2 L
7 X
V
0.5 H
2 Z
0 X
N
204.19 527.24 204.19 506.24 2 L
7 X
V
0 X
N
284.86 527.24 284.86 506.24 2 L
7 X
V
0 X
N
352.19 527.24 352.19 506.24 2 L
7 X
V
0 X
N
366.19 527.24 366.19 506.24 2 L
7 X
V
0 X
N
(tbd) 118.21 515.62 T
(op3) 238.38 515.62 T
(rd) 167.36 515.62 T
(rs1) 314.64 515.62 T
(i=1) 353.51 515.62 T
(simm13) 435.92 514.47 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "13" 19
%%Page: "14" 20
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(14) 72 17 T
(2) 435.34 17 T
(Instructions) 447.34 17 T
3 F
(more bit than the width of the accumulator and) 72 721 T
(:) 339.14 721 T
(C is set if the extra bit is set and the operation is unsigned.) 72 699 T
-0.11 (V is set if the extra bit is different from the most signi\336cant bit of the accumu-) 72 677 P
(lator and the operation is signed.) 72 663 T
(ASRzz \050zz tbd\051 contains 2 bits) 72 641 T
(:) 240.23 641 T
(AccruedOver\337ow) 72 619 T
(: Bit 1, set eac) 169.98 619 T
(h time V=1.) 247.92 619 T
(AccruedCarry) 72 597 T
(: Bit 0, set eac) 152.64 597 T
(h time C=1.) 230.58 597 T
(ASRzz is only reset by writing to it.) 72 575 T
(ASRzz is updated even for instructions whic) 72 553 T
(h do not affect condition codes) 316.57 553 T
(.) 482.71 553 T
0.44 (The MUL instructions also sets ASRyy to the same value as r[rd] and ASRxx) 72 531 P
0.96 (to 0 or full 1\325) 72 517 P
0.96 (s depending on the result sign. Note that MUL is equivalent to) 145.57 517 P
(ASRxx|Y|ASRyy=0 followed by MAC) 72 503 T
(.) 281.6 503 T
4 F
(T) 72 481 T
(raps:) 80.45 481 T
3 F
(none) 108 459 T
FMENDPAGE
%%EndPage: "14" 20
%%Page: "15" 21
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(2) 108 17 T
(Instructions) 120 17 T
(15) 528 17 T
4 F
(2.4 Alternate W) 108 721 T
(indow P) 209.56 721 T
(ointer) 260.11 721 T
3 F
(Description:) 108 699 T
-0.3 (A) 108 677 P
-0.3 (WP \050Alternate W) 116.06 677 P
-0.3 (indow P) 210.57 677 P
-0.3 (ointer\051 is a \336eld of ASRxx \050no relation with previous) 254.5 677 P
(section\051.) 108 663 T
0.42 (PSR contains two additional bits A) 108 641 P
0.42 (W \050Alternate W) 302.89 641 P
0.42 (indow) 390.84 641 P
0.42 (, place tbd\051 and P) 422.67 641 P
0.42 (A) 520.16 641 P
0.42 (W) 528.23 641 P
-0.33 (\050Previous A) 108 627 P
-0.33 (W) 171.51 627 P
-0.33 (, place tbd\051 whic) 181.78 627 P
-0.33 (h are reset on RESET) 270.71 627 P
-0.33 (. The current window is the) 388.99 627 P
1.93 (one pointed to by CWP when A) 108 613 P
1.93 (W=0 and the one pointed to by A) 290.76 613 P
1.93 (WP when) 484.96 613 P
(A) 108 599 T
(W=1.) 116.06 599 T
-0.19 (When a trap is taken, in addition to the normal beha) 108 577 P
-0.19 (vior) 398.69 577 P
-0.19 (, A) 419.04 577 P
-0.19 (W is copied to P) 433.58 577 P
-0.19 (A) 520.16 577 P
-0.19 (W) 528.23 577 P
(and A) 108 563 T
(W is reset. Upon execution of RETT) 140.29 563 T
(, P) 337.02 563 T
(A) 351.04 563 T
(W is copied bac) 359.1 563 T
(k to A) 443.69 563 T
(W) 476.21 563 T
(.) 486.48 563 T
1.62 (This mec) 108 541 P
1.62 (hanism allows routines whic) 159.54 541 P
1.62 (h manipulate windows other than the) 322.55 541 P
1.31 (current window \050suc) 108 527 P
1.31 (h as context switc) 223.41 527 P
1.31 (hing routines\051 to run with ET=1 thus) 325.95 527 P
(reducing the maximum interrupt latency) 108 513 T
(.) 334.06 513 T
4 F
(2.5 P) 108 469 T
(artial WRPSR) 143.89 469 T
3 F
(Description:) 108 447 T
0.06 (When a WRPSR instruction with a non null rd is executed, only some \336elds of) 108 425 P
0.21 (PSR are written rather than all the de\336ned \336elds of PSR.The mapping \322rd =>) 108 411 P
(\336elds\323 is tbd. However:) 108 397 T
(\321) 126 375 T
(rd=0 => all \336elds written \050for compatibility\051) 144 375 T
(\321) 126 353 T
(rd=tbd => only ET is written.) 144 353 T
-0.1 (The second point allows to overcome the explicitly stated weakness of V8 \050pro-) 108 331 P
(gramming note 3 of the WRPSR instruction\051:) 108 317 T
0.07 (If traps are enabled \050ET=1\051, care must be taken if softw) 144 295 P
0.07 (are is to disable) 452.44 295 P
2 (them \050ET=0\051 since the \322RDPSR, WRPSR\323 sequence is interruptible -) 144 281 P
4.6 (allowing PSR to be c) 144 267 P
4.6 (hanged between the two instructions - this) 275.69 267 P
(sequence is not a reliable mec) 144 253 T
(hanism to disable traps) 308.83 253 T
(.) 439.01 253 T
4 F
(2.6 Non-Privileged ASI Access) 108 209 T
3 F
-0.17 (In SP) 108 187 P
-0.17 (ARC-V8E implementations providing for non-privileged ASI access func-) 138.29 187 P
1.78 (tions) 108 173 P
1.78 (, LOAD and ST) 135.04 173 P
1.78 (ORE from Alternate space instructions accessing ASI\325) 225.63 173 P
1.78 (s) 534.44 173 P
2.46 (00) 108 159 P
3 9.6 Q
1.97 (16) 121.34 156 P
3 12 Q
2.46 ( - 7F) 132.02 159 P
3 9.6 Q
1.97 (16) 162.27 156 P
3 12 Q
2.46 ( are privileged instructions) 172.95 159 P
2.46 (. LOAD and ST) 330.02 159 P
2.46 (ORE from Alternate) 422.65 159 P
(space instructions accessing ASI\325) 108 145 T
(s 80) 290.36 145 T
3 9.6 Q
(16) 312.6 142 T
3 12 Q
( - FF) 323.27 145 T
3 9.6 Q
(16) 349.95 142 T
3 12 Q
( are non-privileged instructions) 360.63 145 T
(.) 534.99 145 T
FMENDPAGE
%%EndPage: "15" 21
%%Page: "16" 22
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(16) 72 17 T
(2) 435.34 17 T
(Instructions) 447.34 17 T
FMENDPAGE
%%EndPage: "16" 22
%%Page: "17" 23
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(3) 108 17 T
(Memory Management Unit \050MMU\051) 120 17 T
(17) 528 17 T
4 14 Q
(3 Memory Management Unit \050MMU\051) 193.88 623.67 T
4 12 Q
(3.1 Overview) 108 579 T
3 F
1.53 (This speci\336cation describes a reference MMU for SP) 108 557 P
1.53 (ARC-V8E and a simple) 407.17 557 P
-0.23 (feature to indicate cac) 108 543 P
-0.23 (heability for those cases where no full reference MMU is) 229.66 543 P
0.97 (to be implemented: a minimal MMU) 108 529 P
0.97 (. The SP) 313.49 529 P
0.97 (ARC-V8E reference MMU is an) 361.68 529 P
-0.23 (extension to the existing reference MMU as described in the SP) 108 515 P
-0.23 (ARC-V8 Arc) 457.23 515 P
-0.23 (hi-) 524.89 515 P
0.78 (tecture Speci\336cation. This speci\336cation covers the enhancements and modi\336-) 108 501 P
4.07 (cations to the existing SP) 108 487 P
4.07 (ARC-V8 reference MMU to support embedded) 264.55 487 P
0.73 (applications) 108 473 P
0.73 (. It assumes an understanding of the arc) 175.04 473 P
0.73 (hitecture of the SP) 404.49 473 P
0.73 (ARC-) 510.01 473 P
(V8 reference MMU) 108 459 T
(.) 212.56 459 T
-0 (The enhanced features and functionality offered by an embedded SP) 108 437 P
-0 (ARC-V8E) 486.01 437 P
(reference MMU are covered in Section 3.2 below) 108 423 T
(. They inc) 373.84 423 T
(lude:) 427.98 423 T
(\321) 126 401 T
(Sub-page protection down to 1k byte level) 144 401 T
(\321) 126 379 T
(Support for disabling of context number matc) 144 379 T
(h) 395.93 379 T
(\321) 126 357 T
(Support for softw) 144 357 T
(are table w) 240 357 T
(alk) 301.58 357 T
(\321) 126 335 T
(Support for loc) 144 335 T
(king TLB entries) 225.68 335 T
0.49 (The Minimal MMU cac) 108 313 P
0.49 (heability control can be provided in the case where no) 237.82 313 P
(actual MMU is to be implemented.) 108 299 T
4 F
(3.2 Reference MMU architecture) 108 255 T
(3.2.1 Overview) 108 211 T
3 F
2.79 (The Embedded SP) 108 189 P
2.79 (ARC-V8E MMU arc) 215.15 189 P
2.79 (hitecture has been enhanced and/or) 331.07 189 P
(modi\336ed in four principal areas:) 108 175 T
(\0501\051) 126 153 T
0.39 (Memory protection has been extended down to a level of 1k bytes) 144 153 P
0.39 (. This) 508.26 153 P
-0.02 (is done by splitting 4k byte pages into four subpages and providing pro-) 144 139 P
4.06 (tection for eac) 144 125 P
4.06 (h of the four subpages) 229.8 125 P
4.06 (. However) 368.17 125 P
4.06 (, pages are alw) 426.8 125 P
4.06 (a) 521.45 125 P
4.06 (ys) 528 125 P
2.4 (aligned to 4k byte boundaries) 144 111 P
2.4 (, and, 4k bytes remains the minimum) 317.33 111 P
(page size that ma) 144 97 T
(y be addressed.) 241.68 97 T
FMENDPAGE
%%EndPage: "17" 23
%%Page: "18" 24
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(18) 72 17 T
(3) 319.69 17 T
(Memory Management Unit \050MMU\051) 331.69 17 T
3 F
(\0502\051) 90 699 T
0.56 (Context Number matc) 108 699 P
0.56 (hing in the P) 232.6 699 P
0.56 (age Descriptor Cac) 305.83 699 P
0.56 (he \050a.k.a. Trans-) 411.53 699 P
1.89 (lation Lookaside Buffer) 108 685 P
1.89 (, or TLB\051 has been provided with an optional) 240.82 685 P
0.78 (bypass) 108 671 P
0.78 (. This provides for establishing global pages \050as opposed to only) 145.49 671 P
(local\051 that are accessible across process contexts) 108 657 T
(.) 374.38 657 T
(\0503\051) 90 635 T
0.66 (Support has been provided for a softw) 108 635 P
0.66 (are table w) 321.76 635 P
0.66 (alk in addition to the) 384.66 635 P
(hardw) 108 621 T
(are table w) 143.34 621 T
(alk of the SP) 204.92 621 T
(ARC-V8 MMU) 275.4 621 T
(.) 355.3 621 T
(\0504\051) 90 599 T
(Support has been provided for loc) 108 599 T
(king TLB entries) 293.47 599 T
(.) 387.85 599 T
0.09 (Eac) 72 577 P
0.09 (h of these enhancements are described in the following sections as speci\336c) 92.58 577 P
0.03 (modi\336cations to the existing SP) 72 563 P
0.03 (ARC-V8 reference MMU) 247.03 563 P
0.03 (. No attempt has been) 381.63 563 P
0.71 (made to provide a full description of the existing SP) 72 549 P
0.71 (ARC-V8 reference MMU) 364.69 549 P
0.71 (,) 500.66 549 P
0.82 (however) 72 535 P
0.82 (, some portions of the V8 reference MMU arc) 117.24 535 P
0.82 (hitecture are replicated) 371.92 535 P
(here for bac) 72 521 T
(kground c) 137.24 521 T
(lari\336cation of the Embedded V8e enhancements) 192.26 521 T
(.) 457.54 521 T
3 10 Q
(Note:) 72 496.33 T
1.83 (The SP) 108 484.33 P
1.83 (ARC-V8E MMU Speci\336cation uses the term TLB interc) 142.81 484.33 P
1.83 (hangeably with the) 411.07 484.33 P
(term PDC \050as currently used in the V8 reference MMU Speci\336cation\051.) 108 472.33 T
4 12 Q
(3.2.2 V) 72 429 T
(irtual Address F) 118.56 429 T
(ormat) 219.24 429 T
3 F
-0.06 (As de\336ned in the reference MMU) 72 407 P
-0.06 (, the 32 bit address is subdivided into the fol-) 254.7 407 P
(lowing \336elds:) 72 393 T
(The lower 12 bits are used as an offset within the physical page) 72 300 T
(.) 423.85 300 T
0.78 (Two bits of the page offset ma) 72 278 P
0.78 (y be used during the comparison phase to pro-) 242.17 278 P
1.3 (vide protection for 1k byte pages) 72 264 P
1.3 (. However) 258.46 264 P
1.3 (, addressing itself is not modi\336ed) 314.34 264 P
2.53 (and remains based on a minimum of 4k byte pages \050see physical address) 72 250 P
(below\051.) 72 236 T
0.73 (The three index \336elds correspond to lookup keys into three different transla-) 72 214 P
(tion structures) 72 200 T
(, mapping 4k, 256k, 16M, or 4G of virtual addresses) 153.91 200 T
(.) 441.02 200 T
3 10 Q
(Implementation Note:) 72 175.33 T
0.63 (When only softw) 108 163.33 P
0.63 (are table w) 185.93 163.33 P
0.63 (alk is supported, then the above format does not ha) 238.51 163.33 P
0.63 (ve to) 481.33 163.33 P
1.83 (be followed in full and the detailed structure of the tables and their contents are) 108 151.33 P
1.01 (purely a softw) 108 139.33 P
1.01 (are matter) 175.4 139.33 P
1.01 (. If hardw) 224.86 139.33 P
1.01 (are table w) 272.07 139.33 P
1.01 (alk is supported, table structures and) 325.41 139.33 P
(table elements are as speci\336ed in a section below) 108 127.33 T
(.) 332.35 127.33 T
72 81 504 729 C
72 318 504 389 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 76.71 336 T
(17) 257.81 336 T
(24) 158.06 336 T
(18) 246.21 336 T
(11) 343.3 336 T
(12) 332.36 336 T
(0) 496.22 336 T
(23) 170.37 336 T
75.67 344.65 501 367.17 R
7 X
V
1 H
0 Z
0 X
N
168.86 366.58 168.86 345.58 2 L
7 X
V
0.5 H
2 Z
0 X
N
256.19 366.58 256.19 345.58 2 L
7 X
V
0 X
N
341.69 366.58 341.69 345.58 2 L
7 X
V
11 X
N
0 X
(Inde) 199.11 354.96 T
(x 2) 214.43 354.96 T
(Inde) 110.8 354.96 T
(x 1) 126.12 354.96 T
(Inde) 283.42 354.96 T
(x 3) 298.74 354.96 T
(P) 396.92 353.81 T
(age offset) 401.94 353.81 T
366.36 366.91 366.36 345.91 2 L
7 X
V
11 X
N
0 X
(10) 354.17 336 T
(9) 372 336 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "18" 24
%%Page: "19" 25
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(3) 108 17 T
(Memory Management Unit \050MMU\051) 120 17 T
(19) 528 17 T
4 F
(3.2.3 Physical Address F) 108 721 T
(ormat) 264.12 721 T
3 F
(The physical address is a 36 bit \336eld:) 108 699 T
0.5 (Note that the lower 12 bits of the physical address are the same as the lower) 108 606 P
0.63 (12 bits of the virtual address: they are not translated. This allows the imple-) 108 592 P
-0.12 (mentation of virtually addressed, physically tagged cac) 108 578 P
-0.12 (hes with set sizes up to) 412.13 578 P
(4k bytes) 108 564 T
(.) 154.16 564 T
3 10 Q
(Implementation Note:) 108 539.33 T
(Implementation of all 36 physical address bits is not required.) 144 527.33 T
4 12 Q
(3.2.4 Address T) 108 484 T
(ranslation) 207.79 484 T
3 F
-0.15 (The virtual address along with the context number are compared with the vir-) 108 462 P
1.32 (tual address tags stored in the TLB) 108 448 P
1.32 (. A matc) 312.37 448 P
1.32 (h indicates that the translation) 360.93 448 P
(from virtual to physical address is already in the TLB) 108 434 T
(.) 405.82 434 T
0.83 (When a miss occurs) 108 412 P
0.83 (, system hardw) 219.75 412 P
0.83 (are and/or softw) 305.65 412 P
0.83 (are \050See section on Hard-) 396.89 412 P
1.59 (w) 108 398 P
1.59 (are and Softw) 117.12 398 P
1.59 (are T) 197.21 398 P
1.59 (able W) 227.49 398 P
1.59 (alk\051, will cause a trap that fetc) 266.41 398 P
1.59 (hes the required) 445.93 398 P
0.64 (PTE from the structures in memory) 108 384 P
0.64 (. Due to sparse population and the use of) 308.38 384 P
(large linear mappings) 108 370 T
(, a full set of structures in most cases is not needed.) 229.72 370 T
3.49 (Access permissions are c) 108 348 P
3.49 (hec) 254.6 348 P
3.49 (ked by hardw) 273.18 348 P
3.49 (are for eac) 355.29 348 P
3.49 (h translation. If the) 420.18 348 P
3.11 (requested access violates those permissions) 108 334 P
3.11 (, a fault is generated and the) 361.28 334 P
0.53 (appropriate status information is stored in the F) 108 320 P
0.53 (ault Status Register and the) 380.3 320 P
(F) 108 306 T
(ault Address Register) 115.22 306 T
(.) 234.47 306 T
4 F
(3.2.5 Contexts) 108 262 T
3 F
0.26 (Eac) 108 240 P
0.26 (h virtual address is associated with a \322context\323 number) 128.58 240 P
0.26 (. The management) 435.69 240 P
0.04 (of context numbers is the responsibility of the memory management softw) 108 226 P
0.04 (are) 518.88 226 P
0.04 (.) 536.66 226 P
1.56 (The context number of the current running process is stored in the context) 108 212 P
(register) 108 198 T
(. In this arc) 149.9 198 T
(hitecture) 214.04 198 T
(, the context number has one purpose:) 264.26 198 T
-0.24 (By comparing the context number in the TLB entry \336eld with the) 144 176 P
3.37 (virtual address context, memory protection between different) 144 162 P
(processes is provided during address translation.) 144 148 T
1.84 (The context number can also be used as an index into a list of translation) 108 126 P
(table structures) 108 112 T
(.) 195.92 112 T
108 81 540 729 C
108 624 540 695 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(35) 112.71 642.81 T
(11) 379.3 642.81 T
(12) 368.36 642.81 T
(0) 532.22 642.81 T
111.67 650.65 537 673.17 R
7 X
V
1 H
0 Z
0 X
N
377.69 672.58 377.69 651.58 2 L
7 X
V
0.5 H
2 Z
0 X
N
(Ph) 194.18 660.96 T
(ysical page n) 203.72 660.96 T
(umber \050PPN\051) 250.33 660.96 T
(P) 432.92 659.81 T
(age offset) 437.94 659.81 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "19" 25
%%Page: "20" 26
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(20) 72 17 T
(3) 319.69 17 T
(Memory Management Unit \050MMU\051) 331.69 17 T
3 10 Q
(Implementation Note:) 72 722.33 T
1.02 (The range of context numbers is implementation dependent, but can not be greater) 108 710.33 P
(than 0...127.) 108 698.33 T
3 12 Q
2.36 (The primary difference between SP) 72 673 P
2.36 (ARC-V8E and the SP) 276.79 673 P
2.36 (ARC-V8 reference) 401.67 673 P
1.07 (MMU) 72 659 P
1.07 (, with respect to context number matc) 103.24 659 P
1.07 (hing) 319.59 659 P
1.07 (, is that the context number) 344.18 659 P
0.27 (matc) 72 645 P
0.27 (h can be disabled in SP) 99.25 645 P
0.27 (ARC-V8E. When disabled, the comparison of con-) 228.85 645 P
(text number is not performed during address translation.) 72 631 T
4 F
(3.2.6 T) 72 587 T
(ables) 117.44 587 T
3 F
0.78 (Elements of the V8e MMU table structure and contents ha) 72 565 P
0.78 (ve been enhanced) 404.44 565 P
(to provide for:) 72 551 T
(\321) 108 529 T
(protection down to 1k byte pages) 126 529 T
(\321) 108 507 T
0.79 (support for disabling context number matc) 126 507 P
0.79 (hing on address transla-) 366.52 507 P
(tion; this provides support for both \322local\323 and \322global\323 pages) 126 493 T
0.48 (The following diagram shows the hardw) 72 471 P
0.48 (are table w) 296.46 471 P
0.48 (alk for a matc) 359.01 471 P
0.48 (hing virtual) 437.29 471 P
-0.13 (address) 72 457 P
-0.13 (. I3 \0506 bits\051 ma) 114.59 457 P
-0.13 (y be extended by two bits \050total 8 bits\051 from the V) 194.86 457 P
-0.13 (A page) 466.13 457 P
(offset to provide 256 PTE Level-3 T) 72 443 T
(able entries for 1k byte page protection.) 267.16 443 T
(.) 72 421 T
4 F
(F) 201.55 188.83 T
(igure 1:) 210 188.83 T
(P) 260.22 188.83 T
(age T) 268.67 188.83 T
(able Search) 301.44 188.83 T
3 F
-0.28 (The root pointer is unique to eac) 72 150.83 P
-0.28 (h context. It is found in the Context T) 250.04 150.83 P
-0.28 (able \050see) 456.27 150.83 P
(SP) 72 136.83 T
(ARC-V8 reference MMU description\051.) 86.9 136.83 T
72 81 504 729 C
72 198.83 504 417 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
202.21 221.55 256.21 374.55 R
5 X
0 0 0 1 0 0 0 K
V
1 H
0 Z
0 X
N
95.88 361.55 149.88 379.55 R
7 X
V
0 X
N
6 12 Q
(a PTD) 105.89 366.24 T
202.21 320.55 256.21 338.55 R
7 X
V
0 X
N
(a PTD) 212.22 325.24 T
310.21 221.55 364.21 338.55 R
5 X
V
0 X
N
310.21 275.55 364.21 293.55 R
7 X
V
0 X
N
(a PTD) 320.22 280.24 T
418.21 221.55 472.21 293.55 R
5 X
V
0 X
N
418.21 235.69 472.21 253.69 R
7 X
V
0 X
N
(a PTE) 428.55 240.39 T
(...) 220.21 353.18 T
(...) 328.21 314.17 T
(...) 220.21 272.18 T
(...) 328.21 248.18 T
(...) 436.21 278.17 T
196.69 370.55 196.69 372.09 202.07 370.55 196.69 369.01 4 Y
N
196.69 370.55 196.69 372.09 202.07 370.55 196.69 369.01 4 Y
V
149.88 370.55 196.19 370.55 2 L
7 X
V
2 Z
0 X
N
301.91 331.21 301.91 332.76 307.29 331.21 301.91 329.67 4 Y
0 Z
N
301.91 331.21 301.91 332.76 307.29 331.21 301.91 329.67 4 Y
V
257.33 331.21 301.41 331.21 2 L
7 X
V
2 Z
0 X
N
411.02 284.55 411.02 286.09 416.4 284.55 411.02 283.01 4 Y
0 Z
N
411.02 284.55 411.02 286.09 416.4 284.55 411.02 283.01 4 Y
V
364.21 284.55 410.52 284.55 2 L
7 X
V
2 Z
0 X
N
(Root P) 90.21 383.88 T
(ointer) 126.3 383.88 T
(Le) 193.21 378.88 T
(v) 206.2 378.88 T
(el-1 T) 211.9 378.88 T
(ab) 241.13 378.88 T
(le) 254.24 378.88 T
(Le) 301.21 342.88 T
(v) 314.2 342.88 T
(el-2 T) 319.9 342.88 T
(ab) 349.13 342.88 T
(le) 362.23 342.88 T
(Le) 409.21 297.88 T
(v) 422.2 297.88 T
(el-3 T) 427.9 297.88 T
(ab) 457.13 297.88 T
(le) 470.23 297.88 T
(256 entr) 199.84 207.17 T
(ies) 244.04 207.17 T
(64 entr) 310.73 207.17 T
(ies) 348.26 207.17 T
(64/256 entr) 418.73 208.01 T
(ies) 479.61 208.01 T
366.5 359 503.5 416.17 R
7 X
V
6 10 Q
0 X
(PTD=P) 366.5 409.5 T
(age T) 398.61 409.5 T
(ab) 422.98 409.5 T
(le Descr) 433.9 409.5 T
(iptor) 470.72 409.5 T
(PTE=P) 366.5 393.5 T
(age T) 398.06 393.5 T
(ab) 422.43 393.5 T
(le Entr) 433.35 393.5 T
(y) 462.55 393.5 T
(I= Inde) 366.5 377.5 T
(x Register) 397.06 377.5 T
7 X
90 450 9 9 171.64 353.91 G
0 Z
0 X
90 450 9 9 171.64 353.91 A
8 14 Q
(+) 166.96 351.99 T
7 X
90 450 9 9 279 307.58 G
0 X
90 450 9 9 279 307.58 A
(+) 274.33 305.66 T
7 X
90 450 9 9 390.43 267.08 G
0 X
90 450 9 9 390.43 267.08 A
(+) 385.76 265.16 T
154.42 324.06 190.25 336.56 R
7 X
V
0 X
N
370.26 239.06 406.09 251.56 R
7 X
V
0 X
N
262.75 275.73 298.59 288.23 R
7 X
V
0 X
N
2 10 Q
(I1) 168.18 326.67 T
(I2) 276.51 278.33 T
(I3) 384.01 241.67 T
171.42 370.12 171.42 362.97 2 L
7 X
V
2 Z
0 X
N
171.64 345.12 171.64 336.89 2 L
7 X
V
0 X
N
198.59 330.12 198.59 332.25 202.29 330.12 198.59 327.98 4 Y
0 Z
N
198.59 330.12 198.59 332.25 202.29 330.12 198.59 327.98 4 Y
V
189.71 330.12 198.09 330.12 2 L
7 X
V
2 Z
0 X
N
279 330.5 279.4 317.26 2 L
7 X
V
0 X
N
279 298.69 279 288.69 2 L
7 X
V
0 X
N
305.02 282.97 305.02 285.11 308.72 282.97 305.02 280.84 4 Y
0 Z
N
305.02 282.97 305.02 285.11 308.72 282.97 305.02 280.84 4 Y
V
298.29 282.97 304.52 282.97 2 L
7 X
V
2 Z
0 X
N
390.07 284.4 390.07 275.75 2 L
7 X
V
0 X
N
390.43 257.26 390.43 252.26 2 L
7 X
V
0 X
N
412.16 245.83 412.16 247.97 415.86 245.83 412.16 243.7 4 Y
0 Z
N
412.16 245.83 412.16 247.97 415.86 245.83 412.16 243.7 4 Y
V
406.14 245.83 411.66 245.83 2 L
7 X
V
2 Z
0 X
N
6 12 Q
(8 bits) 164 308.5 T
(6 bits) 273.17 261 T
(6/8bits) 376.5 227.16 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "20" 26
%%Page: "21" 27
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(3) 108 17 T
(Memory Management Unit \050MMU\051) 120 17 T
(21) 528 17 T
4 F
(3.2.7 P) 108 721 T
(age T) 154.12 721 T
(able Descriptor \050PTD\051) 186.89 721 T
3 F
0.59 (The P) 108 699 P
0.59 (age T) 140.83 699 P
0.59 (able Descriptor is shown below) 171.22 699 P
0.59 (. It has been enhanced to inc) 343.45 699 P
0.59 (lude a) 505.4 699 P
(1k byte subpage protection enable \337ag:) 108 685 T
-1.67 (PTP =) 145.38 570 P
(P) 189 570 T
(age T) 196.56 570 T
(able P) 226.36 570 T
(ointer value:) 260.38 570 T
0.89 (The PTP appears on bits 35 through 8 of the physical address) 189 556 P
-0.03 (bus during miss processing) 189 542 P
-0.03 (. The page table pointed to by a PTP) 339.05 542 P
1.86 (must be aligned on a boundary equal to the size of the page) 189 528 P
0.74 (table) 189 514 P
0.74 (. The sizes of the three levels of page tables are the same) 216.58 514 P
(as in the SP) 189 500 T
(ARC-V8 MMU) 255.25 500 T
(R =) 160.73 478 T
5 F
(Reserved) 192.34 478 T
3 F
(KE=) 154.73 456 T
(1k byte protection enable \050only at level 2\051:) 189 456 T
(KE = 0: I3 provides 6 bits- 64 page table entries;) 189 434 T
(page offset provides 12 bits- 4k bytes per page) 234 420 T
(KE= 1: I3 provides 8 bits- 256 page table entries;) 189 384 T
(page offset provides 10 bits- 1k bytes per subpage) 234 370 T
(ET =) 152.72 334 T
(01) 189 334 T
(Other entry types:) 189 320 T
(00: invalid) 189 306 T
(10: valid PTE \050see PTE below\051) 189 292 T
(11: valid PTE \050see PTE below\051) 189 278 T
4 F
(3.2.8 P) 108 234 T
(age T) 154.12 234 T
(able Entry \050PTE\051) 186.89 234 T
3 F
2.51 (The PTE has been enhanced in SP) 108 212 P
2.51 (ARC-V8E to support bypassing context) 313.53 212 P
2.55 (number matc) 108 198 P
2.55 (hing on address translation. This optionally provides for two) 184.47 198 P
(types of pages:) 108 184 T
(\321) 126 162 T
(local pages) 144 162 T
(, local to a particular context) 204.16 162 T
(\321) 126 140 T
(global pages) 144 140 T
(, pages shared between contexts) 211.94 140 T
108 81 540 729 C
108 588 540 659 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 112.71 606.81 T
(1) 501.73 606.81 T
(2) 487.25 606.81 T
(0) 532.22 606.81 T
111.67 614.65 537 637.17 R
7 X
V
1 H
0 Z
0 X
N
498.33 636.5 498.33 615.5 2 L
7 X
V
0.5 H
2 Z
0 X
N
(PTP) 274.73 623.96 T
(ET) 513.42 623.96 T
478 636.83 478 615.83 2 L
7 X
V
0 X
N
(3) 470 606.81 T
(KE) 484.17 623.96 T
0 12 Q
(PTD:) 121.67 645.17 T
458.67 636.83 458.67 615.83 2 L
7 X
V
0 X
N
6 8 Q
(R) 466 624 T
(4) 452 606.81 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "21" 27
%%Page: "22" 28
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(22) 72 17 T
(3) 319.69 17 T
(Memory Management Unit \050MMU\051) 331.69 17 T
3 F
(PPN =) 107.6 649 T
(Physical P) 153 649 T
(age Number value:) 210.79 649 T
0.8 (The high-order 24 bits of the 36-bit physical address of the sub-) 144 627 P
2.19 (page) 144 613 P
2.19 (. The PPN appears on bits 35 through 12 of the physical) 169.79 613 P
(address bus when translation completes) 144 599 T
(CMR =) 104.74 577 T
(C) 153 577 T
(,M and R bits as in V8 reference MMU) 161.22 577 T
(ACC =) 107.4 555 T
(ACC bits as in V8 reference MMU) 153 555 T
(ET =) 116.72 533 T
0.77 (10: valid PTE for \322local\323 subpage: perform the context number) 153 533 P
(c) 172.8 519 T
(hec) 178.04 519 T
(k) 196.62 519 T
0.83 (11: valid PTE for \322global\323 subpage: do not perform the context) 153 505 P
(number c) 172.8 491 T
(hec) 224.71 491 T
(k) 243.29 491 T
(Other entry types:) 153 477 T
(00: invalid PTD) 153 463 T
(01: valid PTD) 153 449 T
4 F
(3.2.9 T) 72 405 T
(ranslation Lookaside Buffer \050TLB\051) 118.12 405 T
3 F
0.1 (Miss processing of the TLB on virtual address translation ma) 72 383 P
0.1 (y be provided by) 413.25 383 P
0.95 (either hardw) 72 369 P
0.95 (are or softw) 144.74 369 P
0.95 (are mec) 211.98 369 P
0.95 (hanisms or a combination of both. As previ-) 256.19 369 P
0.97 (ously noted, the TLB is referred to as a P) 72 355 P
0.97 (age Descriptor Cac) 308.11 355 P
0.97 (he \050PDC\051 in the) 414.64 355 P
1.64 (V8 reference MMU speci\336cation. The terminology has been updated in this) 72 341 P
1.9 (supplement to be consistent with the SP) 72 327 P
1.9 (ARC-V9 speci\336cation and industry) 306.09 327 P
(convention.) 72 313 T
4 F
(3.2.9.1 Hardware and Software T) 72 269 T
(able W) 280.91 269 T
(alk) 321.46 269 T
3 F
(\0501\051) 90 247 T
139.56 245.8 108 245.8 2 L
V
0.6 H
0 Z
N
(Softw) 108 247 T
168.68 245.8 139.34 245.8 2 L
V
N
(are T) 139.34 247 T
206.26 245.8 168.02 245.8 2 L
V
N
(able W) 168.02 247 T
222.92 245.8 205.36 245.8 2 L
V
N
(alk) 205.36 247 T
(:) 222.92 247 T
-0.16 (Softw) 108 225 P
-0.16 (are handling of miss processing uses an openly de\336ned table orga-) 139.34 225 P
0.52 (nization and la) 108 211 P
0.52 (yout for the TLB) 192.28 211 P
0.52 (. Details on loading a TLB element are) 285.85 211 P
(speci\336ed in the sections below on \322Writing TLB Entries\323.) 108 197 T
(\0502\051) 90 175 T
146.22 173.8 108 173.8 2 L
V
N
(Hardw) 108 175 T
175.34 173.8 146 173.8 2 L
V
N
(are T) 146 175 T
212.92 173.8 174.68 173.8 2 L
V
N
(able W) 174.68 175 T
229.58 173.8 212.02 173.8 2 L
V
N
(alk) 212.02 175 T
(:) 229.58 175 T
2.79 (In the case of hardw) 108 153 P
2.79 (are miss processing of the TLB during virtual) 231.6 153 P
0.88 (address translation, the softw) 108 139 P
0.88 (are user is still required to know how to) 276.01 139 P
2.7 (prepare the tables to be used by hardw) 108 125 P
2.7 (are address translation and) 342.31 125 P
0.04 (table w) 108 111 P
0.04 (alk. However) 148.29 111 P
0.04 (, the exact format of the transfer by hardw) 220.48 111 P
0.04 (are from) 456.63 111 P
(these tables to a TLB is transparent to the softw) 108 97 T
(are implementor) 376.73 97 T
(.) 467.98 97 T
72 81 504 729 C
72 667 504 717 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 76.71 670.5 T
(4) 448.39 670.5 T
(1) 475.94 670.5 T
(2) 468.05 670.5 T
(0) 496.22 670.5 T
75.67 679.65 501 702.17 R
7 X
V
1 H
0 Z
0 X
N
446.5 701.67 446.5 680.67 2 L
7 X
V
0.5 H
2 Z
0 X
N
473.5 701.5 473.5 680.5 2 L
7 X
V
0 X
N
(PPN) 238.28 688.96 T
(ET) 481.86 688.96 T
(A) 450.97 688.96 T
(CC) 456.07 688.96 T
(CMR) 422.84 688.96 T
419.06 701.55 419.06 680.56 2 L
7 X
V
0 X
N
(7) 421.28 670.5 T
(8) 411.72 670.5 T
(5) 440.5 670.5 T
0 12 Q
(PTE:) 76.5 706 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "22" 28
%%Page: "23" 29
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(3) 108 17 T
(Memory Management Unit \050MMU\051) 120 17 T
(23) 528 17 T
3 F
(\0503\051) 126 721 T
182.22 719.8 144 719.8 2 L
V
0.6 H
0 Z
N
(Hardw) 144 721 T
259.13 719.8 182 719.8 2 L
V
N
(are and Softw) 182 721 T
288.25 719.8 258.91 719.8 2 L
V
N
(are T) 258.91 721 T
325.82 719.8 287.59 719.8 2 L
V
N
(able W) 287.59 721 T
342.49 719.8 324.92 719.8 2 L
V
N
(alk) 324.92 721 T
(:) 342.49 721 T
2.5 (Even in the case of exc) 144 699 P
2.5 (lusive hardw) 281.99 699 P
2.5 (are miss processing) 356.06 699 P
2.5 (, there exist) 469.21 699 P
2.36 (requirements for softw) 144 685 P
2.36 (are visible interfaces since softw) 274.72 685 P
2.36 (are must ini-) 463.5 685 P
1.57 (tially construct the tables) 144 671 P
1.57 (. F) 290.41 671 P
1.57 (or example) 305.99 671 P
1.57 (, loc) 368.46 671 P
1.57 (king of TLB elements can) 391.72 671 P
0.23 (only be provided by softw) 144 657 P
0.23 (are) 285.17 657 P
0.23 (, even when the table w) 302.96 657 P
0.23 (alk is in hardw) 434.82 657 P
0.23 (are) 518.88 657 P
0.23 (.) 536.66 657 P
1.39 (Consequently suc) 144 643 P
1.39 (h functions as entering a loc) 242.64 643 P
1.39 (k bit into the hardw) 405.74 643 P
1.39 (are) 522 643 P
1.05 (are detailed in the speci\336cation below) 144 629 P
1.05 (. Moreover) 356.67 629 P
1.05 (, even in a fully hard-) 415.62 629 P
0.93 (w) 144 615 P
0.93 (are tablew) 153.12 615 P
0.93 (alk environment, reading and writing of TLB elements by) 212.3 615 P
1.1 (softw) 144 601 P
1.1 (are for diagnostic purposes ma) 173.34 601 P
1.1 (y be useful along with other func-) 347.62 601 P
(tionality) 144 587 T
(.) 189.62 587 T
4 F
(3.2.9.2 TLB Contents) 108 543 T
3 F
2.55 (TLB entries are speci\336ed for softw) 108 521.6 P
2.55 (are miss processing and other softw) 311.22 521.6 P
2.55 (are) 522 521.6 P
0.78 (access to the TLB) 108 508.2 P
0.78 (. The TLB entry consists of two parts) 207.68 508.2 P
0.78 (, an associative and a) 418.18 508.2 P
0.65 (data part. The associative part is used during comparison matc) 108 494.8 P
0.65 (hing with the) 464.03 494.8 P
0.29 (virtual address) 108 481.4 P
0.29 (. If an entry matc) 192.22 481.4 P
0.29 (hes the virtual page address) 289.99 481.4 P
0.29 (, then a physical) 447.99 481.4 P
0.31 (page number \050PPN\051 is directly provided by the data part of the TLB to gener-) 108 468 P
(ate the physical address) 108 454.6 T
(. The TLB is composed of the following \336elds:) 241.72 454.6 T
9 10 Q
(\245) 144 435.2 T
3 12 Q
(PPN:) 153 435.2 T
(Physical P) 189 435.2 T
(age Number \050up to 24 bits) 246.79 435.2 T
(, implementation de\336ned\051) 390.97 435.2 T
9 10 Q
(\245) 144 415.8 T
3 12 Q
(C) 153 415.8 T
(, M, R and ACC bits \050as in V8\051) 161.22 415.8 T
9 10 Q
(\245) 144 396.4 T
3 12 Q
(OL:) 153 396.4 T
(Offset Length Indicator:) 189 396.4 T
(11: use 12 bits offset \0501k subpages or 4k byte pages\051) 189 383 T
(10: use 18 bits offset \050256k byte pages\051) 189 369.6 T
(01: use 24 bits offset \05016M byte pages\051) 189 356.2 T
(00: use 32 bits offset \0504G byte pages) 189 342.8 T
9 10 Q
(\245) 144 323.4 T
3 12 Q
3.47 (VPN: V) 153 323.4 P
3.47 (irtual P) 198.04 323.4 P
3.47 (age Number) 243.97 323.4 P
3.47 (, 20 virtual address bits comprised of) 314.47 323.4 P
(Indexes: I1, I2, and I3) 189 310 T
9 10 Q
(\245) 144 290.6 T
3 12 Q
(K:) 153 290.6 T
1.26 (1k byte subpage identi\336er) 189 290.6 P
1.26 (- equals two most signi\336cant bits of) 336.6 290.6 P
(untranslated 12 bit V) 189 277.2 T
(A page offset) 307.48 277.2 T
9 10 Q
(\245) 144 257.8 T
3 12 Q
(CN:) 153 257.8 T
(Context Number) 189 257.8 T
9 10 Q
(\245) 144 238.4 T
3 12 Q
(KE:) 153 238.4 T
(1k byte subpage protection indicator:) 189 238.4 T
(KE =1:) 189 225 T
(1k byte subpage protection is enabled. Matc) 234 225 T
(h 20 bits of) 477.07 225 T
(VPN plus 2 bits from K \050total 22 bits\051) 234 211.6 T
(KE = 0:) 189 198.2 T
(4k byte page) 234 198.2 T
(. Matc) 304.03 198.2 T
(h only 20 bits of VPN) 338.62 198.2 T
9 10 Q
(\245) 144 178.8 T
3 12 Q
(V) 153 178.8 T
(: V) 160.76 178.8 T
(alid bit,) 175.08 178.8 T
(V=1: valid entry) 189 165.4 T
(.) 277.45 165.4 T
9 10 Q
(\245) 144 146 T
3 12 Q
(G: Global bit, enabling switc) 153 146 T
(h for context \336eld,) 310.31 146 T
(G = 1: do not c) 189 132.6 T
(hec) 268.43 132.6 T
(k Context Number \050global page\051) 287 132.6 T
(G = 0: do compare Context Number \050local page\051) 189 119.2 T
9 10 Q
(\245) 144 99.8 T
3 12 Q
0.94 (TLB- Loc) 150 99.8 P
0.94 (k Bit: Loc) 202.19 99.8 P
0.94 (ks the TLB entry- not to be c) 257.56 99.8 P
0.94 (hanged by tablew) 423.18 99.8 P
0.94 (alk) 522.43 99.8 P
(hardw) 198 86.4 T
(are; can only be handled by softw) 233.34 86.4 T
(are) 417.6 86.4 T
(.) 435.38 86.4 T
FMENDPAGE
%%EndPage: "23" 29
%%Page: "24" 30
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(24) 72 17 T
(3) 319.69 17 T
(Memory Management Unit \050MMU\051) 331.69 17 T
4 F
(3.2.9.3 Address T) 72 721 T
(ranslation) 182.02 721 T
3 F
0.45 (The following diagram illustrates the comparison and matc) 72 699 P
0.45 (hing of TLB \336elds) 403.54 699 P
(during translation of a virtual address into a physical address:) 72 685 T
4 F
(F) 180.33 432.62 T
(igure 2:) 188.78 432.62 T
(TLB Address T) 239 432.62 T
(ranslation) 331.23 432.62 T
(3.2.9.4 Writing TLB Entries-Hardware T) 72 388.62 T
(able W) 325.32 388.62 T
(alk) 365.87 388.62 T
3 F
0.76 (When hardw) 72 366.62 P
0.76 (are miss processing is implemented, the required data elements) 143.87 366.62 P
(can be derived from the following sources:) 72 352.62 T
0 10 Q
(element) 112.69 323.95 T
(Sour) 330.3 323.95 T
(ce) 350.68 323.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
2 F
(PPN) 78.42 303.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(from the PTE being loaded) 192.28 303.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(C,M,R,A) 78.42 283.95 T
(CC) 114.97 283.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(from the PTE being loaded) 192.28 283.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(OL \050of) 78.42 263.95 T
(fset length ind\051) 105.66 263.95 T
(From table w) 192.28 263.95 T
(alk) 245.51 263.95 T
(VPN-virt page number) 78.42 243.95 T
(V) 192.28 243.95 T
(irtual Address) 198.9 243.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(CN-Conte) 78.42 223.95 T
(xt Number) 119.38 223.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(Conte) 192.28 223.95 T
(xt Re) 216.02 223.95 T
(gister) 237.26 223.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(KE- protect enable) 78.42 203.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(PTD- Le) 192.28 203.95 T
(v) 227.3 203.95 T
(el 2 \050last read\051) 232.15 203.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(V) 78.42 183.95 T
(-V) 84.64 183.95 T
(alid Bit) 94.08 183.95 T
(Set to 1 if T) 192.28 183.95 T
(able W) 239.26 183.95 T
(alk ok \050otherwise not entered\051) 267.06 183.95 T
(G-Global Bit) 78.42 163.95 T
(from the PTE being loaded \050least signi\336cant bit of ET\051) 192.28 163.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(LB-Lock Bit) 78.42 143.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
(Only manipulated by Softw) 192.28 143.95 T
(are \050can not be changed by hardw) 303.01 143.95 T
(are\051) 437.86 143.95 T
0 1 1 0 1 0 0 K
0 0 0 1 0 0 0 K
0 12 Q
(T) 170.92 122.62 T
(able 1:) 177.82 122.62 T
(TLB Entry Sour) 215.15 122.62 T
(ces-H/W T) 299.62 122.62 T
(able W) 353.51 122.62 T
(alk) 389.07 122.62 T
72.42 336.37 72.42 136.87 2 L
V
0.5 H
0 Z
N
186.28 336.87 186.28 136.37 2 L
V
N
503.58 336.37 503.58 136.87 2 L
V
N
72.17 336.62 503.83 336.62 2 L
V
N
72.67 317.87 503.33 317.87 2 L
V
N
72.67 315.37 503.33 315.37 2 L
V
N
72.17 136.62 503.83 136.62 2 L
V
N
72 81 504 729 C
72.42 442.62 503.58 659 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
170.25 547.43 253.36 573.14 R
5 X
0 0 0 1 0 0 0 K
V
1 H
0 Z
0 X
N
256.04 547.43 346.19 573.14 R
5 X
V
0 X
N
349.71 547.43 362.39 573.14 R
5 X
V
0 X
N
364.64 547.43 430.85 573.14 R
5 X
V
0 X
N
433.81 547.43 461.98 573.14 R
5 X
V
0 X
N
464.23 547.43 482.55 573.14 R
5 X
V
0 X
N
484.8 547.43 501 573.14 R
5 X
V
0 X
N
77.14 547.43 167.3 573.14 R
5 X
V
0 X
N
10 8 Q
(Inde) 197.66 558.4 T
(x 2) 213.99 558.4 T
(Inde) 109.69 558.4 T
(x 1) 126.02 558.4 T
(Inde) 289.97 558.4 T
(x 3) 306.3 558.4 T
(Conte) 365.7 558.4 T
(xt Number) 388.25 558.4 T
(KE) 444.45 558.4 T
(G) 471.05 558.4 T
(OL) 488.2 558.4 T
6 F
(31) 72.21 636.34 T
(17) 253.31 636.34 T
(24) 153.56 636.34 T
(18) 241.71 636.34 T
(11) 338.8 636.34 T
(12) 327.86 636.34 T
(0) 491.72 636.34 T
(23) 165.87 636.34 T
73.81 609.9 498.31 632.41 R
14 X
V
0 X
N
164.6 630.85 164.6 609.85 2 L
14 X
V
2 Z
0 X
N
251.93 630.85 251.93 609.85 2 L
14 X
V
0 X
N
337.43 630.85 337.43 609.85 2 L
14 X
V
0 X
N
10 F
(Inde) 195.61 619.49 T
(x 2) 211.94 619.49 T
(Inde) 107.3 619.49 T
(x 1) 123.63 619.49 T
(Inde) 279.92 619.49 T
(x 3) 296.25 619.49 T
(P) 392.7 618.34 T
(a) 397.79 618.34 T
(g) 402.16 618.34 T
(e offset) 407.13 618.34 T
362.09 630.85 362.09 609.85 2 L
14 X
V
3 H
8 X
N
6 F
0 X
(9) 368.17 636.34 T
(10) 354.83 636.34 T
336.81 512.86 367.05 512.86 359.59 499.52 343.68 498.69 4 Y
5 X
V
1 H
0 Z
0 X
N
73.71 446.93 500.14 470.5 R
6 X
V
0 X
N
10 F
(TLB HIT) 273.48 456.69 T
0 12 Q
(V) 78.43 598.43 T
(irtual Addr) 86.65 598.43 T
(ess) 145.44 598.43 T
(TLB) 78.43 534.14 T
11 X
90 450 1.5 1.5 269.57 107.21 526.52 GG
107.2 525.02 109.85 525 107.17 520.43 104.55 525.04 4 Y
3 H
N
107.2 525.02 109.85 525 107.17 520.43 104.55 525.04 4 Y
V
107.86 611.71 107.21 526.52 2 L
6 X
V
2 Z
11 X
N
90 450 1.5 1.5 269.57 194.21 522.66 GG
194.2 521.16 196.85 521.14 194.17 516.57 191.55 521.18 4 Y
0 Z
N
194.2 521.16 196.85 521.14 194.17 516.57 191.55 521.18 4 Y
V
194.86 607.86 194.21 522.66 2 L
6 X
V
2 Z
11 X
N
90 450 1.5 1.5 269.57 280.07 521.81 GG
280.06 520.31 282.71 520.29 280.02 515.71 277.41 520.33 4 Y
0 Z
N
280.06 520.31 282.71 520.29 280.02 515.71 277.41 520.33 4 Y
V
280.72 607 280.07 521.81 2 L
6 X
V
2 Z
11 X
N
90 450 1.5 1.5 269.57 350.93 522.38 GG
350.92 520.88 353.57 520.86 350.88 516.29 348.27 520.9 4 Y
0 Z
N
350.92 520.88 353.57 520.86 350.88 516.29 348.27 520.9 4 Y
V
351.57 607.57 350.93 522.38 2 L
6 X
V
2 Z
11 X
N
90 450 1.5 1.5 270 398.29 522.81 GG
398.29 521.31 400.94 521.31 398.29 516.71 395.64 521.31 4 Y
0 Z
N
398.29 521.31 400.94 521.31 398.29 516.71 395.64 521.31 4 Y
V
398.29 546.11 398.29 522.81 2 L
6 X
V
2 Z
11 X
N
1 X
90 450 1.5 1.5 270 127.57 522.81 GG
127.57 521.31 130.22 521.31 127.57 516.71 124.92 521.31 4 Y
0 Z
N
127.57 521.31 130.22 521.31 127.57 516.71 124.92 521.31 4 Y
V
127.57 546.11 127.57 522.81 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 268.51 219.38 521.23 GG
219.34 519.73 221.99 519.66 219.22 515.14 216.69 519.8 4 Y
0 Z
N
219.34 519.73 221.99 519.66 219.22 515.14 216.69 519.8 4 Y
V
220 545 219.38 521.23 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 270 304.29 521.09 GG
304.29 519.59 306.94 519.59 304.29 515 301.64 519.59 4 Y
0 Z
N
304.29 519.59 306.94 519.59 304.29 515 301.64 519.59 4 Y
V
304.29 546.29 304.29 521.09 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 270.53 357.92 522.38 GG
357.93 520.88 360.58 520.9 357.97 516.29 355.28 520.85 4 Y
0 Z
N
357.93 520.88 360.58 520.9 357.97 516.29 355.28 520.85 4 Y
V
357.7 545.55 357.92 522.38 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 270 413.86 522.23 GG
413.86 520.73 416.51 520.73 413.86 516.14 411.21 520.73 4 Y
0 Z
N
413.86 520.73 416.51 520.73 413.86 516.14 411.21 520.73 4 Y
V
413.86 545.95 413.86 522.23 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 269.42 112.31 479.64 GG
112.3 478.14 114.95 478.12 112.25 473.55 109.65 478.17 4 Y
0 Z
N
112.3 478.14 114.95 478.12 112.25 473.55 109.65 478.17 4 Y
V
112.57 505.2 112.31 479.64 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 268.79 206.48 480.41 GG
206.45 478.91 209.1 478.86 206.35 474.32 203.79 478.97 4 Y
0 Z
N
206.45 478.91 209.1 478.86 206.35 474.32 203.79 478.97 4 Y
V
207 505.2 206.48 480.41 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 268.79 291.62 481.01 GG
291.59 479.51 294.24 479.45 291.49 474.91 288.94 479.56 4 Y
0 Z
N
291.59 479.51 294.24 479.45 291.49 474.91 288.94 479.56 4 Y
V
292.14 505.79 291.62 481.01 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 270 351.57 480.41 GG
351.57 478.91 354.23 478.91 351.57 474.32 348.92 478.91 4 Y
0 Z
N
351.57 478.91 354.23 478.91 351.57 474.32 348.92 478.91 4 Y
V
351.57 497.33 351.57 480.41 2 L
6 X
V
2 Z
1 X
N
90 450 1.5 1.5 268.79 410.48 480.41 GG
410.45 478.91 413.1 478.86 410.35 474.32 407.8 478.97 4 Y
0 Z
N
410.45 478.91 413.1 478.86 410.35 474.32 407.8 478.97 4 Y
V
411 505.2 410.48 480.41 2 L
6 X
V
2 Z
1 X
N
0 7 Q
0 X
(com) 344 506.14 T
89 512.86 134.71 512.86 120.43 498.57 104 498.57 4 Y
5 X
V
1 H
0 Z
0 X
N
(compar) 98.29 506.43 T
(e) 121.1 506.43 T
183.43 512.86 229.14 512.86 214.86 498.57 198.43 498.57 4 Y
5 X
V
0 X
N
(compar) 192.71 506.43 T
(e) 215.53 506.43 T
269.29 512.86 315 512.86 300.72 498.57 284.29 498.57 4 Y
5 X
V
0 X
N
(compar) 278.57 506.43 T
(e) 301.39 506.43 T
387.29 512.86 433 512.86 418.72 498.57 402.29 498.57 4 Y
5 X
V
0 X
N
(compar) 396.57 506.43 T
(e) 419.39 506.43 T
370.7 507 370.7 504.87 367 507 370.7 509.13 4 Y
N
370.7 507 370.7 504.87 367 507 370.7 509.13 4 Y
V
452.67 546.86 452.67 534.84 378 534.84 378 507 371.2 507 5 L
2 Z
N
432.03 505.67 432.03 503.53 428.33 505.67 432.03 507.8 4 Y
0 Z
N
432.03 505.67 432.03 503.53 428.33 505.67 432.03 507.8 4 Y
V
473.33 547.62 473.33 505.67 432.53 505.67 3 L
2 Z
N
370.03 500.72 370.03 498.59 366.33 500.72 370.03 502.85 4 Y
0 Z
N
370.03 500.72 370.03 498.59 366.33 500.72 370.03 502.85 4 Y
V
489.29 547.14 489.29 488 375.55 488 375.55 500.72 370.53 500.72 5 L
2 Z
N
314.78 507.38 314.78 505.24 311.08 507.38 314.78 509.51 4 Y
0 Z
N
314.78 507.38 314.78 505.24 311.08 507.38 314.78 509.51 4 Y
V
374.08 488.04 323.01 488.04 323.01 507.38 315.28 507.38 4 L
2 Z
N
135.45 507.38 135.45 505.24 131.75 507.38 135.45 509.51 4 Y
0 Z
N
135.45 507.38 135.45 505.24 131.75 507.38 135.45 509.51 4 Y
V
321.21 488.04 154.41 488.04 154.41 507.38 135.95 507.38 4 L
2 Z
N
228.45 506 228.45 503.86 224.75 506 228.45 508.13 4 Y
0 Z
N
228.45 506 228.45 503.86 224.75 506 228.45 508.13 4 Y
V
243.75 488.5 243.75 506 228.95 506 3 L
2 Z
N
10 8 Q
(K) 353.57 559.14 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "24" 30
%%Page: "25" 31
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(3) 108 17 T
(Memory Management Unit \050MMU\051) 120 17 T
(25) 528 17 T
4 F
(3.2.9.5 Writing TLB Entries- Software T) 108 721 T
(able W) 357.88 721 T
(alk) 398.42 721 T
3 F
1.45 (When softw) 108 699 P
1.45 (are miss processing is implemented, the required TLB elements) 174.57 699 P
-0.11 (are a) 108 685 P
-0.11 (vailable as a set of page descriptors located in a 4k byte area in an imple-) 135.78 685 P
(mentation de\336ned location in ASI space \050see TLB Mapping below\051.) 108 671 T
0.57 (16 bytes are allocated to eac) 108 649 P
0.57 (h page descriptor) 266.59 649 P
0.57 (, hence a maximum of 256 page) 362.31 649 P
0.24 (descriptors can be supported. P) 108 635 P
0.24 (age descriptor) 282.06 635 P
5 F
0.24 (n) 364.09 635 P
3 F
0.24 ( is mapped on the 4 word area) 371.42 635 P
(starting at byte address 16x) 108 621 T
5 F
(n) 266.93 621 T
3 F
( within the 4k byte space) 274.26 621 T
(.) 412.97 621 T
(\0501\051) 126 599 T
2.47 (W) 144 599 P
2.47 (ord 0 of a page descriptor is the physical address page descriptor) 155.05 599 P
(word; it contains \050in ASI address space\051:) 144 585 T
(\0502\051) 126 492 T
1.64 (W) 144 492 P
1.64 (ord 1 of a page descriptor is the TLB page descriptor word; It con-) 155.05 492 P
(tains:) 144 478 T
(\0503\051) 126 385 T
(W) 144 385 T
(ord 2 of a page descriptor contains the Loc) 155.05 385 T
(k Bit;) 388.98 385 T
(\0504\051) 126 292 T
(W) 144 292 T
(ord 3 of a page descriptor is not used.) 155.05 292 T
108 81 540 729 C
108 510 540 581 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 10 Q
0 X
0 0 0 1 0 0 0 K
(P) 147.5 563 T
(age Descriptor W) 153.51 563 T
(ord 0: Ph) 227.74 563 T
(ysical Addr) 267.59 563 T
(ess Data and Contr) 316.58 563 T
(ol Bits) 398.34 563 T
6 8 Q
(31) 112.71 527.83 T
(2) 501.39 527.83 T
(1) 514.05 527.83 T
111.67 536.65 537 559.17 R
7 X
V
1 H
0 Z
0 X
N
482.5 558.67 482.5 537.67 2 L
7 X
V
0.5 H
2 Z
0 X
N
509.5 558.5 509.5 537.5 2 L
7 X
V
0 X
N
(PPN) 274.28 545.96 T
(OL) 517.64 545.96 T
(A) 489.97 545.96 T
(CC) 495.07 545.96 T
(CMR) 460.84 545.96 T
454.06 557.55 454.06 536.56 2 L
7 X
V
0 X
N
(5) 476.28 527.83 T
(8) 445.67 527.83 T
(0) 526.84 527.83 T
(4) 487 527.83 T
(7) 460 527.83 T
108 81 540 729 C
0 0 612 792 C
108 81 540 729 C
108 403 540 474 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 10 Q
0 X
0 0 0 1 0 0 0 K
(P) 150.83 458.17 T
(age Descriptor W) 156.84 458.17 T
(ord 1: V) 231.07 458.17 T
(A T) 265.27 458.17 T
(ag and Contr) 280.74 458.17 T
(ol Bits) 337.23 458.17 T
6 8 Q
(31) 112.71 421 T
(11) 379.3 421 T
(12) 368.36 421 T
(0) 532.22 421 T
111.67 429.65 537 452.17 R
1 H
0 Z
N
377.69 451.58 377.69 430.58 2 L
7 X
V
0.5 H
2 Z
11 X
N
0 X
(Conte) 423.97 437.67 T
(xt Number) 445.08 437.67 T
399.86 451.91 399.86 430.91 2 L
7 X
V
0 X
N
486.19 452.25 486.19 431.25 2 L
7 X
V
0 X
N
504.19 450.91 504.19 429.91 2 L
7 X
V
0 X
N
519.69 452.08 519.69 431.08 2 L
7 X
V
0 X
N
(KE) 491 437.67 T
(V) 509.33 437.67 T
(G) 525.17 437.67 T
(1) 510.17 421 T
(2) 494.33 421 T
(3) 480.17 421 T
(9) 406.83 421 T
(10) 391 421 T
(VPN) 238.5 437.17 T
(\245K) 382.5 438 T
108 81 540 729 C
0 0 612 792 C
108 81 540 729 C
108 310 540 381 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 112.71 330.06 T
(0) 527.72 330.06 T
111.67 336.65 537 359.17 R
7 X
V
1 H
0 Z
0 X
N
0 10 Q
(P) 147.5 363 T
(age Descriptor W) 153.51 363 T
(ord 2: Lock Bit) 227.74 363 T
516.67 358.17 516.67 337.17 2 L
7 X
V
0.5 H
2 Z
0 X
N
6 8 Q
(LB) 524 345 T
108 81 540 729 C
0 0 612 792 C
108 81 540 729 C
108 217 540 288 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 112.71 236.06 T
(0) 519.72 236.06 T
111.67 243.65 537 266.17 R
7 X
V
1 H
0 Z
0 X
N
0 10 Q
(P) 147.5 270 T
(age Descriptor W) 153.51 270 T
(ord 3: N) 227.74 270 T
(A) 263.09 270 T
(Not Used) 278.33 251.83 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "25" 31
%%Page: "26" 32
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(26) 72 17 T
(3) 319.69 17 T
(Memory Management Unit \050MMU\051) 331.69 17 T
4 F
(3.2.9.6 TLB Mapping) 72 721 T
3 F
0.87 (The following is an example of a reference implementation of MMU features) 72 699 P
1 (for page descriptor mapping within the implementation dependent alternate) 72 685 P
(address space) 72 671 T
(.) 148.45 671 T
0.1 (W) 72 649 P
0.1 (ithin this address space) 83.56 649 P
0.1 (, TLB page descriptors ma) 215.2 649 P
0.1 (y be accessed as shown in) 361.49 649 P
(the following table:) 72 635 T
3 10 Q
(Implementation note:) 72 480.33 T
0.29 (F) 108 468.33 P
0.29 (or softw) 114.12 468.33 P
0.29 (are portability across implementations) 151.08 468.33 P
0.29 (, 1k byte subpages are assumed to be) 330.8 468.33 P
-0.14 (referenced by the same Physical P) 108 456.33 P
-0.14 (age Number \050PPN\051. However) 265.1 456.33 P
-0.14 (, this does not prec) 397.95 456.33 P
-0.14 (lude) 484 456.33 P
(individual implementations with 1k byte mapping) 108 444.33 T
(.) 339.84 444.33 T
4 12 Q
(3.3 Cacheability Control \050Minimal MMU\051) 72 401 T
3 F
0.12 (If the reference MMU is not implemented, it ma) 72 379 P
0.12 (y be desirable to control cac) 339.27 379 P
0.12 (h-) 492.67 379 P
0.64 (ing of memory accesses) 72 365 P
0.64 (, e) 202.27 365 P
0.64 (.g) 215.36 365 P
0.64 (. to prevent cac) 224.84 365 P
0.64 (hing data from bloc) 310.67 365 P
0.64 (ks where DMA) 420.06 365 P
(is in progress) 72 351 T
(. In suc) 145.92 351 T
(h cases) 186.28 351 T
(, the following function ma) 225.76 351 T
(y be implemented:) 373.87 351 T
0.81 (When the most signi\336cant bit \050MSB\051 of an instruction address or data) 108 329 P
-0.29 (address equals one) 108 315 P
-0.29 (, the item referenced is not cac) 212.12 315 P
-0.29 (heable) 379.65 315 P
-0.29 (. The remaining) 415.89 315 P
4.19 (31 virtual address bits are used, without translation, as physical) 108 301 P
(address bits) 108 287 T
(.) 174.6 287 T
0 10 Q
(W) 115.71 606.33 T
(ord) 124.96 606.33 T
(No. Bytes) 179.23 606.33 T
(Addr) 342.26 606.33 T
(ess) 364.86 606.33 T
2 F
(0) 125.33 586.33 T
(4) 197 586.33 T
2 12 Q
(16) 246.83 586.33 T
1 F
(n) 258.83 586.33 T
2 F
( to 16) 264.83 586.33 T
1 F
(n) 292.17 586.33 T
8 14 Q
(+) 298.17 586.33 T
2 12 Q
(3) 305.86 586.33 T
2 10 Q
(1) 125.33 566.33 T
(4) 197 566.33 T
2 12 Q
(16) 246.83 566.33 T
1 F
(n) 258.83 566.33 T
8 14 Q
(+) 264.83 566.33 T
2 12 Q
(4 to 16) 272.52 566.33 T
1 F
(n) 305.86 566.33 T
8 14 Q
(+) 311.86 566.33 T
2 12 Q
(7) 319.54 566.33 T
2 10 Q
(2) 125.33 546.33 T
(4) 197 546.33 T
2 12 Q
(16) 246.83 546.33 T
1 F
(n) 258.83 546.33 T
8 14 Q
(+) 264.83 546.33 T
2 12 Q
(8 to 16) 272.52 546.33 T
1 F
(n) 305.86 546.33 T
8 14 Q
(+) 311.86 546.33 T
2 12 Q
(11) 319.54 546.33 T
2 10 Q
(3) 125.33 526.33 T
(4) 197 526.33 T
2 12 Q
(16) 246.83 526.33 T
1 F
(n) 258.83 526.33 T
8 14 Q
(+) 264.83 526.33 T
2 12 Q
(12 to 16) 272.52 526.33 T
1 F
(n) 311.86 526.33 T
8 14 Q
(+) 317.86 526.33 T
2 12 Q
(15- Not Used) 325.54 526.33 T
0 F
(T) 186.44 505 T
(able 2:) 193.34 505 T
(TLB P) 230.68 505 T
(age Descriptor Mapping) 264.9 505 T
97.5 618.75 97.5 519.25 2 L
V
0.5 H
0 Z
N
158.17 619.25 158.17 518.75 2 L
V
N
240.83 619.25 240.83 518.75 2 L
V
N
478.5 618.75 478.5 519.25 2 L
V
N
97.25 619 478.75 619 2 L
V
N
97.75 600.25 478.25 600.25 2 L
V
N
97.75 597.75 478.25 597.75 2 L
V
N
97.25 519 478.75 519 2 L
V
N
FMENDPAGE
%%EndPage: "26" 32
%%Page: "27" 33
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(4) 108 17 T
(Traps) 120 17 T
(27) 528 17 T
4 14 Q
(4 T) 296.97 619.67 T
(raps) 318.88 619.67 T
0 12 Q
(4.1 Ov) 108 575 T
(er) 147.22 575 T
(view) 157.75 575 T
2 F
1.35 (This section contains enhancements to the SP) 108 553 P
1.35 (ARC-V8 trap speci\336cations. V) 333.63 553 P
1.35 (ectoring all) 484.33 553 P
0.39 (traps through a single v) 108 539 P
0.39 (ector) 222.04 539 P
0.39 (, single-v) 245.55 539 P
0.39 (ector trapping, can impro) 290.42 539 P
0.39 (v) 412.72 539 P
0.39 (e performance and mem-) 418.54 539 P
(ory utilization if all trap service routines can \336t into cache memory) 108 525 T
(.) 428.17 525 T
0 F
(4.2 Single-V) 108 481 T
(ector T) 174.8 481 T
(rapping) 210.9 481 T
2 F
0.29 (As an alternati) 108 459 P
0.29 (v) 178.27 459 P
0.29 (e to the standard SP) 184.1 459 P
0.29 (ARC-V8 trap mechanism, a single v) 279.5 459 P
0.29 (ector trap mecha-) 455.45 459 P
(nism is pro) 108 445 T
(vided in SP) 161.16 445 T
(ARC-V8E. When this mechanism is implemented:) 215.4 445 T
9 10 Q
(\245) 144 425 T
3 12 Q
(trap type = 0: reset- vectors to a \336xed physical address) 150 425 T
(, 0) 451.44 425 T
5 F
(x) 464.78 425 T
3 F
(0) 470.78 425 T
9 10 Q
(\245) 144 405 T
3 12 Q
(trap type > 0: all other traps- vector to Trap Base Address) 150 405 T
3 14 Q
(+) 474.64 405 T
3 12 Q
( 0) 483.12 405 T
2 F
1.21 (After a trap has been tak) 108 383 P
1.21 (en, its T) 231.54 383 P
1.21 (rap T) 272.54 383 P
1.21 (ype can be determined by reading the T) 298.45 383 P
1.21 (rap T) 496.77 383 P
1.21 (ype) 522.67 383 P
-0.25 (\336eld, TT) 108 369 P
-0.25 (, of the T) 148.86 369 P
-0.25 (rap Base Re) 191.69 369 P
-0.25 (gister \050TBR\051. This can be used by softw) 248.99 369 P
-0.25 (are to determine sub-) 439.11 369 P
0.85 (sequent processing of the trap. The trap base re) 108 355 P
0.85 (gister has the same layout as in SP) 340.86 355 P
0.85 (ARC-) 511.33 355 P
(V8:) 108 341 T
0.48 (Single v) 108 236.17 P
0.48 (ector trapping can sa) 147.97 236.17 P
0.48 (v) 248.81 236.17 P
0.48 (e code space and impro) 254.63 236.17 P
0.48 (v) 369 236.17 P
0.48 (e the response time of traps, since) 374.82 236.17 P
1.22 (the most frequent trap service routines for a gi) 108 222.17 P
1.22 (v) 339.43 222.17 P
1.22 (en application may \336t and be lock) 345.25 222.17 P
1.22 (ed in) 515.11 222.17 P
(cache as needed.) 108 208.17 T
0.26 (Single v) 108 186.17 P
0.26 (ector trapping is enabled by setting the SVT \337ag, bit 0 of ASR 17, to a 1. A reset) 147.75 186.17 P
1.68 (trap clears the SVT \337ag, making V8e implementations consistent with the SP) 108 172.17 P
1.68 (ARC-V8) 496.67 172.17 P
(speci\336cation.) 108 158.17 T
1.13 (All other trap features are as speci\336ed in the SP) 108 136.17 P
1.13 (ARC-V8 speci\336cation and the reader is) 345.37 136.17 P
(referred to that document for their detailed description.) 108 122.17 T
108 81 540 729 C
110.92 254.17 537.08 337 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
125.5 283.58 522.5 306.1 R
7 X
0 0 0 1 0 0 0 K
V
1 H
0 Z
0 X
N
6 8 Q
(T) 173.72 292.89 T
(r) 177.65 292.89 T
(ap Base Address \050high order 20 bits\051) 180.24 292.89 T
(0 0 0 0) 478.01 292.89 T
348.51 306.32 348.51 285.32 2 L
7 X
V
0.5 H
2 Z
0 X
N
6 10 Q
(T) 274.17 259.5 T
(r) 279.08 259.5 T
(ap Base Register) 282.31 259.5 T
454.84 305.82 454.84 284.82 2 L
7 X
V
0 X
N
6 8 Q
(T) 384.17 292.89 T
(r) 388.1 292.89 T
(ap T) 390.68 292.89 T
(ype \050tt\051) 405.73 292.89 T
(31) 126 271 T
(12) 339.33 271 T
(0) 516.83 271 T
(3) 462.67 271 T
(4) 449.33 271 T
(11) 355.17 271 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "27" 33
%%Page: "28" 34
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(28) 72 17 T
(4) 464.68 17 T
(Traps) 476.68 17 T
FMENDPAGE
%%EndPage: "28" 34
%%Page: "29" 35
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(29) 528 17 T
4 14 Q
(5 P) 236.89 645.67 T
(eripheral Extensions) 258.8 645.67 T
0 12 Q
(5.1 Ov) 108 601 T
(er) 147.22 601 T
(view) 157.75 601 T
2 F
0.32 (This section supplements the SP) 108 579 P
0.32 (ARC-V8 features and functions in areas peripheral to the) 263.51 579 P
3.31 (basic processor such as: input handlers, interrupt mechanisms, timers, counters and) 108 565 P
0.95 (pulsers. The peripheral e) 108 551 P
0.95 (xtensions may be included indi) 229.31 551 P
0.95 (vidually in speci\336c implementa-) 382.15 551 P
(tions.) 108 537 T
0.09 (The input handler described in 5.2 can be used to shape, b) 108 515 P
0.09 (uf) 387.04 515 P
0.09 (fer) 396.73 515 P
0.09 (, mask and reduce noise on) 409.57 515 P
0.69 (an) 108 501 P
0.69 (y inputs. Control of the features \050polarity) 119.15 501 P
0.69 (, noise immunity) 319.51 501 P
0.69 (, b) 401.12 501 P
0.69 (uf) 413.58 501 P
0.69 (fering, masking\051 is con-) 423.27 501 P
(trolled on an input - by - input basis: one re) 108 487 T
(gister controls all such features for one input.) 315.8 487 T
1.41 (The interrupt prioritizer as in 5.3 mak) 108 465 P
1.41 (es use of input handlers as in 5.2; it furthermore) 297.32 465 P
(merely prioritizes interrupts in one or more le) 108 451 T
(v) 326.66 451 T
(els.) 332.48 451 T
1.78 (The inte) 108 429 P
1.78 (grated interrupt request controller as in 5.4 combines functions comparable to) 149.26 429 P
0.96 (those of of input handlers as in 5.2 and prioritizer as in 5.3; furthermore control is on a) 108 415 P
1.4 (function - by - function basis: one re) 108 401 P
1.4 (gister controls polarity and noise reduction for all) 292.58 401 P
0.72 (inputs; one re) 108 387 P
0.72 (gister controls all masks, etc. This dif) 174.58 387 P
0.72 (ference in control philosoph) 358.56 387 P
0.72 (y re\337ects) 495.63 387 P
(tw) 108 373 T
(o sets of user desires.) 119.88 373 T
0.8 (The counter) 108 351 P
0.8 (-timer) 166.21 351 P
0.8 (-pulser as in 5.5 standardizes a rather simple b) 195.3 351 P
0.8 (ut ne) 423.75 351 P
0.8 (v) 447.92 351 P
0.8 (ertheless v) 453.73 351 P
0.8 (ersatile) 505.34 351 P
(counter) 108 337 T
(, prescaler and counter output control construction.) 143.51 337 T
0.67 (The simple counters as in 5.6 support routine capabilities such as DRAM refresh signal-) 108 315 P
0.22 (ing. The simple timers as in 5.6 support more demanding tasks such as periodic interrupt,) 108 301 P
(simple and w) 108 287 T
(atchdog timeout signaling and square w) 171.88 287 T
(a) 362.74 287 T
(v) 367.82 287 T
(e generation.) 373.64 287 T
0 F
(5.2 Input Handler) 108 243 T
2 F
0.03 (A generalized Input Handler for SP) 108 221 P
0.03 (ARC-V8E is speci\336ed. An Input Handler can dri) 277.32 221 P
0.03 (v) 511.16 221 P
0.03 (e the) 516.98 221 P
1.21 (interrupt handling circuitry or dri) 108 207 P
1.21 (v) 271.83 207 P
1.21 (e or control a timer or counter) 277.65 207 P
1.21 (. Input signals are \336rst) 428.19 207 P
0.02 (handled by a standardized edge control, noise immunity control, b) 108 193 P
0.02 (uf) 425.6 193 P
0.02 (fer and enable circuit.) 435.3 193 P
1.17 (Noise immunity is attained by synchronizing the input sample clock with the processor) 108 179 P
0.3 (clock. The input sample clock may ha) 108 165 P
0.3 (v) 291.88 165 P
0.3 (e the same period as the processor clock or it may) 297.7 165 P
0.17 (be di) 108 151 P
0.17 (vided do) 131.53 151 P
0.17 (wn. The ratio of processor clock to input sample clock is an implementation) 173.06 151 P
(parameter) 108 137 T
(. The number of samples tak) 155.32 137 T
(en can be controlled.) 291.84 137 T
1.31 (Control of each separate input line is done via one control re) 108 115 P
1.31 (gister) 412.55 115 P
1.31 (, controlling edge as) 438.74 115 P
(well as number of samples, b) 108 101 T
(uf) 247.74 101 T
(fering and masking.) 257.44 101 T
FMENDPAGE
%%EndPage: "29" 35
%%Page: "30" 36
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(30) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(5.2.1 Input Handler Cir) 72 721 T
(cuit) 199.46 721 T
2 F
(The follo) 72 677 T
(wing diagram sho) 116.03 677 T
(ws the basic Input Handler Circuit:) 201.72 677 T
0 F
(Figur) 200.55 405 T
(e 3:) 229 405 T
(Input Handler Cir) 250.33 405 T
(cuitry) 344.79 405 T
9 10 Q
(\245) 108 367 T
3 12 Q
(IN:) 117 367 T
( the input signal to be handled) 162 367 T
9 10 Q
(\245) 108 347 T
3 12 Q
(INV) 117 347 T
(:) 139.43 347 T
(control signal) 162 347 T
4 F
(:) 237.34 347 T
3 F
(0 = do not invert IN) 162 333 T
(1 = invert IN) 162 319 T
9 10 Q
(\245) 108 299 T
3 12 Q
(INP:) 117 299 T
(IN) 162 299 T
4 F
(xor) 180 299 T
3 F
( INV) 200.89 299 T
9 10 Q
(\245) 108 279 T
3 12 Q
(SHIFT) 117 279 T
(:) 155 279 T
0.58 (a 6 bit shift register with INP as its input and shifted by the) 162 279 P
(system c) 162 265 T
(loc) 209.47 265 T
(k.) 224.5 265 T
9 10 Q
(\245) 108 245 T
3 12 Q
(WIDTH:) 117 245 T
(control signal) 171 245 T
11 F
(:) 246.34 245 T
3 F
(00 => set BUF to 1 when INP = 1) 162 231 T
(01 => set BUF to 1 when INP = 1) 162 217 T
4 F
(and) 349.87 217 T
3 F
( SHIFT[5] = 1) 373.43 217 T
(10 => set BUF to 1 when INP = 1) 162 203 T
4 F
(and) 349.87 203 T
3 F
( SHIFT[5:3] = 111) 373.43 203 T
(11 => set BUF to 1 when INP = 1) 162 189 T
4 F
(and) 349.87 189 T
3 F
( SHIFT[5:0] = 111111) 373.43 189 T
9 10 Q
(\245) 108 169 T
3 12 Q
(EN:) 117 169 T
0.83 (control signal; whic) 162 169 P
0.83 (h enables BUF to the output of the input) 271.35 169 P
(handler) 162 155 T
(.) 204.13 155 T
9 10 Q
(\245) 108 135 T
3 12 Q
(BUF:) 117 135 T
(output signal; the latc) 162 135 T
(hed result) 284.16 135 T
72 81 504 729 C
83.72 415 492.28 651 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
7 X
0 0 0 1 0 0 0 K
90 450 13.5 13.5 421.22 601.5 G
0.5 H
2 Z
0 X
90 450 13.5 13.5 421.22 601.5 A
386.58 529.29 413.58 556.29 13.5 RR
N
377.58 525 422.58 543 R
7 X
V
N
227.72 444 254.72 471 R
0 X
N
263.72 444 290.72 471 R
N
299.72 444 326.72 471 R
N
335.72 444 362.72 471 R
N
371.72 444 398.72 471 R
N
407.72 444 434.72 471 R
N
191.72 457.71 227.72 457.71 2 L
N
254.72 457.71 263.72 457.71 2 L
N
290.72 457.71 299.72 457.71 2 L
N
326.72 457.71 335.72 457.71 2 L
N
362.72 456.71 371.72 456.71 2 L
N
398.72 457.71 407.72 457.71 2 L
N
90 450 13.5 13.5 241.22 493.5 A
218.72 475.71 263.72 493.71 R
7 X
V
N
227.72 493.71 254.72 493.71 2 L
0 X
N
250 493.71 250 484.71 259 484.71 259 457.71 4 L
N
232 493.71 232 484.71 209.72 484.71 209.72 457.71 4 L
N
90 450 13.5 13.5 295.22 520.5 A
263.72 493.71 335.72 520.71 R
7 X
V
N
281 520.71 308 520.71 2 L
0 X
N
295.43 457.71 295.43 520.71 2 L
N
386.58 543 413.58 543 2 L
N
403 543 403 457.71 2 L
N
439.43 457.29 439.43 520.29 407.72 520.29 407.72 542.57 4 L
N
434.72 456.71 443.72 456.71 2 L
N
241 507 241 561 2 L
N
295.43 534 295.43 561 2 L
N
400.86 556.29 400.86 574.29 2 L
N
389.72 534 389.72 543 2 L
N
385 529.29 394 538.29 R
7 X
V
N
295.72 538.71 389.72 538.71 2 L
0 X
N
286.43 520.71 286.43 511.71 268.43 511.71 241.43 511.71 4 L
N
304 520.71 304 511.71 331 511.71 331 457.71 4 L
N
209.72 480 209.72 561 2 L
N
164.72 444.43 191.72 471.43 13.5 RR
N
7 X
90 450 22.5 22.5 159.36 457.64 G
0 X
90 450 22.5 22.5 159.36 457.64 A
123 426 177 489 R
7 X
V
N
90 450 22.5 22.5 155.93 457.5 G
0 X
90 450 22.5 22.5 155.93 457.5 A
118.29 426 172.29 507 R
7 X
V
N
299.72 622 326.72 649 R
V
0 X
N
371.72 622 398.72 649 R
7 X
V
0 X
N
404.15 579 422.15 624 R
7 X
V
N
421.43 615 421.43 588 2 L
0 X
N
385 622 385 604 421 604 3 L
N
358.43 597 421.43 597 2 L
N
313.43 622 313.43 604 340.43 604 3 L
N
313 579 313 597 340 597 3 L
N
335.72 588 362.72 615 R
7 X
V
0 X
N
155.72 622 209.72 649 R
N
169.43 622 169.43 568 214.43 568 3 L
N
200.72 561 416.72 561 405.92 579 211.52 579 4 Y
7 X
V
0 X
N
2 12 Q
(o) 416.43 603.29 T
434.72 601.71 461.72 601.71 2 L
N
110.72 622 137.72 649 R
7 X
V
0 X
N
(INV) 113.72 633 T
(WIDTH) 163.72 633 T
2 10 Q
(PULS) 301.72 636 T
2 11 Q
(MSK) 373.72 634 T
0 12 Q
(OUT) 439.72 608 T
2 F
(M U X) 279.72 567 T
2 14 Q
(Delay shift re) 272.72 428 T
(gister) 348.71 428 T
2 12 Q
(B) 337.72 598 T
(UF) 345.6 598 T
366.72 457.29 366.72 520.29 398.43 520.29 398.43 542.57 4 L
N
123 622 123 460 177 460 3 L
N
85.72 597 112.72 597 112.72 453 175.72 453 4 L
N
0 F
(IN) 92.72 606 T
83.72 415 492.28 651 R
2 H
0 Z
8 X
N
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "30" 36
%%Page: "31" 37
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(31) 528 17 T
0.09 (Control signals INV) 108 721 P
0.09 (, WIDTH, EN and the b) 203.96 721 P
0.09 (uf) 319.12 721 P
0.09 (fered result B) 328.82 721 P
0.09 (UF can all be read and written) 394.19 721 P
2.28 (by softw) 108 707 P
2.28 (are. Reading will usually be done for diagnostic reasons only; B) 151.82 707 P
2.28 (UF may be) 482.11 707 P
0.58 (polled. IN, INP) 108 693 P
0.58 (, and SHIFT can not be read or written by softw) 181.82 693 P
0.58 (are. Each set of 5 signals) 417.79 693 P
(\050INV) 108 679 T
(, WIDTH, EN and B) 131.77 679 T
(UF\051 is mapped to one ASI w) 230.96 679 T
(ord \050see belo) 368.83 679 T
(w\051.) 430.51 679 T
2 10 Q
(Note:) 108 654.33 T
0.26 (An output should be disabled before its INV control or its WIDTH control are changed, otherwise) 144 642.33 P
0.48 (an output signal change not re\337ecting an input signal change may occur) 144 630.33 P
0.48 (. This mechanism may be) 435.6 630.33 P
(used to produce a desired interrupt on a selected line.) 144 618.33 T
0 12 Q
(5.2.2 ASI Mapping f) 108 575 T
(or Input Handler) 217.38 575 T
2 F
(All circuitry for one input is mapped on one ASI as follo) 108 531 T
(ws:) 380 531 T
(\321) 126 509 T
(ASI 1) 144 509 T
2 9.6 Q
(16) 172.33 506 T
2 12 Q
( or C1) 181.93 509 T
2 9.6 Q
(16) 211.93 506 T
2 12 Q
( is used for Input Handlers.) 221.53 509 T
(\321) 126 487 T
2.01 (Input Handlers are mapped in the 4k byte page starting at address 1000) 144 487 P
2 9.6 Q
1.61 (16) 509.39 484 P
2 12 Q
2.01 ( \0504k) 518.99 487 P
(bytes\051.) 144 473 T
(\321) 126 451 T
0.35 (each Input Handler is mapped onto a full w) 144 451 P
0.35 (ord in the alternate address space \050this) 354.62 451 P
0 (permits up to 1024 input handlers\051. The bits are mapped as speci\336ed in the follo) 144 437 P
0 (w-) 527.34 437 P
(ing table:) 144 423 T
0.6 (Input handlers come in groups of 15. The outputs, OUT \05016) 108 215 P
1 F
0.6 (n) 400.64 215 P
8 F
0.6 (+) 410.24 215 P
2 F
0.6 ( 1 through 16) 416.83 215 P
1 F
0.6 (n) 482.96 215 P
8 F
0.6 (+) 492.56 215 P
2 F
0.6 ( 15\051, are) 499.15 215 P
0.45 (mapped on the w) 108 201 P
0.45 (ord at address \05016) 191.55 201 P
1 F
0.45 (n) 278.55 201 P
8 F
0.45 (+) 288 201 P
2 F
0.45 ( 0\051) 294.59 201 P
8 F
0.45 (*) 308.03 201 P
2 F
0.45 (4; this allo) 314.03 201 P
0.45 (ws reading \050polling\051 all outputs of a) 365.31 201 P
(group and \336nding the leftmost \3241\325 using the SCAN instruction.) 108 187 T
0 10 Q
(Bit) 256.22 372.33 T
(Description) 337.39 372.33 T
2 12 Q
(32:5) 230.5 351 T
2 10 Q
(unused) 306.72 352.33 T
2 12 Q
(4) 230.5 329 T
2 10 Q
(INV) 306.72 330.33 T
2 12 Q
(3:2) 230.5 307 T
2 10 Q
(WIDTH) 306.72 308.33 T
2 12 Q
(1) 230.5 285 T
2 10 Q
(EN) 306.72 286.33 T
2 12 Q
(0) 230.5 263 T
2 10 Q
(B) 306.72 264.33 T
(UF) 313.29 264.33 T
0 12 Q
(T) 239.87 241 T
(able 3:) 246.77 241 T
(Input Handler Mapping) 284.1 241 T
224.5 384.75 224.5 255.25 2 L
V
0.5 H
0 Z
N
300.72 385.25 300.72 254.75 2 L
V
N
423.5 384.75 423.5 255.25 2 L
V
N
224.25 385 423.75 385 2 L
V
N
224.25 365 423.75 365 2 L
V
N
224.25 255 423.75 255 2 L
V
N
FMENDPAGE
%%EndPage: "31" 37
%%Page: "32" 38
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(32) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(5.3 Interrupts) 72 721 T
2 F
(This section contains enhancements to the basic SP) 72 699 T
(ARC-V8 interrupt speci\336cation.) 317.21 699 T
0 F
(5.3.1 Ov) 72 655 T
(er) 120.22 655 T
(view:) 130.75 655 T
2 F
1.04 (The interrupt handler) 72 633 P
1.04 (, when combined with a suf) 175.58 633 P
1.04 (\336cient number of input mechanisms as) 313.14 633 P
0.45 (described in 5.2, constructs a 15 channel programmable trigger input controller that arbi-) 72 619 P
0.52 (trates pending unmask) 72 605 P
0.52 (ed interrupt requests, encodes the highest priority interrupt request) 180.9 605 P
0.74 (into a 4 bit code compatible with the SP) 72 591 P
0.74 (ARC-V8 de\336ned Interrupt Request Le) 268.82 591 P
0.74 (v) 455.45 591 P
0.74 (el \050IRL\051,) 461.27 591 P
(and applies this code to IRL[3:0].) 72 577 T
(On top of this, a w) 72 555 T
(ay is described to e) 161.21 555 T
(xtend the number of interrupts handled o) 253.01 555 T
(v) 448.8 555 T
(er 15.) 454.62 555 T
(The follo) 72 533 T
(wing e) 116.03 533 T
(xtensions are made to the SP) 148.18 533 T
(ARC-V8 interrupt speci\336cation:) 285.4 533 T
(\321) 90 511 T
-0.05 (deri) 108 511 P
-0.05 (ving the 4-bit IRL signal, as de\336ned in V8, from \05015\051 separate interrupt signals) 126.36 511 P
(\321) 90 489 T
(b) 108 489 T
(uf) 113.76 489 T
(fering of pulse-shaped interrupt signals) 123.46 489 T
(\321) 90 467 T
(establishing the polarity of interrupt signals) 108 467 T
(\321) 90 445 T
(supporting more than 15 interrupt sources) 108 445 T
(\321) 90 423 T
(masking interrupts) 108 423 T
1.67 (The basic mechanism contains up to 15 Input Handlers \050as pre) 72 401 P
1.67 (viously described\051. The) 387.68 401 P
-0.11 (Input Handlers are in turn connected to a priority circuit, thus generating a 4 bit code to be) 72 387 P
(used as the Interrupt Request Le) 72 373 T
(v) 226.67 373 T
(el \050IRL\051. The basic interrupt circuit is sho) 232.49 373 T
(wn belo) 432.16 373 T
(w) 470.18 373 T
(.) 478.07 373 T
0 F
(5.3.2 The basic cir) 72 329 T
(cuitry) 170.78 329 T
(Figur) 192.45 86 T
(e 4:) 220.9 86 T
(Basic Interrupt Mechanism) 242.23 86 T
72 81 504 729 C
78.39 96 497.61 303 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
301.34 269.41 301.34 125.41 328.34 125.41 382.34 233.41 400.34 233.41 418.34 251.41 400.34 269.41
391.34 269.41 382.34 269.41 355.34 269.41 10 Y
6 X
0 0 0 1 0 0 0 K
V
0.5 H
2 Z
0 X
N
138.77 242.41 255.77 260.41 R
N
147.77 260.41 156.77 251.41 165.77 260.41 3 L
N
174.77 260.41 183.77 251.41 192.77 260.41 3 L
N
201.77 260.41 210.77 251.41 219.77 260.41 3 L
N
228.77 260.41 237.77 251.41 246.77 260.41 3 L
N
138.91 215.12 255.91 233.12 R
N
147.91 233.12 156.91 224.12 165.91 233.12 3 L
N
174.91 233.12 183.91 224.12 192.91 233.12 3 L
N
201.91 233.12 210.91 224.12 219.91 233.12 3 L
N
228.91 233.12 237.91 224.12 246.91 233.12 3 L
N
139.05 161.41 256.05 179.41 R
N
148.05 179.41 157.05 170.41 166.05 179.41 3 L
N
175.05 179.41 184.05 170.41 193.05 179.41 3 L
N
202.05 179.41 211.05 170.41 220.05 179.41 3 L
N
229.05 179.41 238.05 170.41 247.05 179.41 3 L
N
139.2 134.84 256.2 152.84 R
N
148.2 152.84 157.2 143.84 166.2 152.84 3 L
N
175.2 152.84 184.2 143.84 193.2 152.84 3 L
N
202.2 152.84 211.2 143.84 220.2 152.84 3 L
N
229.2 152.84 238.2 143.84 247.2 152.84 3 L
N
265.34 224.7 301.34 224.7 2 L
N
265.34 170.12 301.34 170.12 2 L
N
265.34 143.41 301.34 143.41 2 L
N
2 12 Q
(\245) 184.34 206.41 T
(\245) 184.34 194.41 T
(\245) 184.34 182.41 T
139.34 251.41 121.34 251.41 2 L
N
139.34 224.41 121.34 224.41 2 L
N
139.34 170.41 121.34 170.41 2 L
N
139.34 143.41 121.34 143.41 2 L
N
255.84 255.91 264.84 251.41 255.84 246.91 3 Y
N
255.98 229.34 264.98 224.84 255.98 220.34 3 Y
N
256.12 174.91 265.12 170.41 256.12 165.91 3 Y
N
265.34 251.41 301.34 251.41 2 L
N
418.34 251.41 463.34 251.41 2 L
N
436.34 255.7 445.34 246.7 2 L
N
0 F
(I) 155.34 265.41 T
(W) 178.01 265.41 T
(P) 211.01 265.41 T
(V) 236.34 265.41 T
(OUT) 268.34 256.41 T
(IRL) 444.34 258.41 T
(IN) 117.34 257.41 T
(15) 310.34 251.41 T
(14) 310.34 224.41 T
(2) 310.34 170.41 T
(1) 310.34 143.41 T
256.12 147.91 265.12 143.41 256.12 138.91 3 Y
N
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "32" 38
%%Page: "33" 39
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(33) 528 17 T
0.56 (Each set of \337ip-\337ops, INV) 108 721 P
0.56 (, B) 235.67 721 P
0.56 (UF) 250.12 721 P
0.56 (, WIDTH, and EN can be separately read and written by) 264.49 721 P
0.9 (softw) 108 707 P
0.9 (are. Reading will usually only be done for diagnostic \050or polling\051 purposes. Reset-) 134.54 707 P
(ting the actual input signals is not part of the interrupt mechanism.) 108 693 T
2 10 Q
(Note:) 108 668.33 T
0.18 (An interrupt INT should be disabled before its INV or its WIDTH controls are changed, otherwise) 144 656.33 P
(an output signal change not re\337ecting an input signal change may occur) 144 644.33 T
(.) 430.35 644.33 T
0 12 Q
(5.3.3 Extended Interrupt Mechanism) 108 601 T
2 F
-0.18 (If more than 15 interrupts are to be pro) 108 579 P
-0.18 (vided, then the outputs of the Input Handlers can be) 293 579 P
0.3 (grouped together by means of an) 108 565 P
0 F
0.3 (or) 270.43 565 P
2 F
0.3 ( g) 281.76 565 P
0.3 (ate replacing the priority encoder in order to imple-) 290.99 565 P
1.54 (ment an e) 108 551 P
1.54 (xtended interrupt mechanism. This e) 157.56 551 P
1.54 (xtended interrupt mechanism is depicted) 339.19 551 P
(belo) 108 537 T
(w) 128.36 537 T
(.) 136.25 537 T
0 F
(Figur) 155.12 260 T
(e 5:) 183.57 260 T
(Extended Interrupt Mechanism \050example con\336guration\051) 204.89 260 T
2 F
0.98 (The e) 108 222 P
0.98 (xact interrupt within the inputs to such an) 135.79 222 P
0 F
0.98 (or) 346.28 222 P
2 F
0.98 ( circuit must be detected by softw) 357.61 222 P
0.98 (are) 525.35 222 P
2.53 (scanning all B) 108 208 P
2.53 (UF \337ip-\337ops dri) 181.6 208 P
2.53 (ving those inputs. There is no limit to the number of) 264.37 208 P
(\322branches\323 in the e) 108 194 T
(xtended circuit.) 199.45 194 T
108 81 540 729 C
113.44 270 534.56 511 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
480.84 444.5 525.84 444.5 2 L
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
498.84 448.79 507.84 439.79 2 L
N
0 12 Q
(IRL) 506.84 451.5 T
7 X
90 450 40.5 31.5 297.94 470.5 G
0 X
90 450 40.5 31.5 297.94 470.5 A
7 X
90 450 22.5 40.5 285.94 470.64 G
0 X
90 450 22.5 40.5 285.94 470.64 A
253.44 394 298.44 511 R
7 X
V
N
338.44 471 347.44 471 347.44 444 365.44 444 4 L
0 X
N
217 488.05 275.5 497.05 R
N
221.5 497.05 226 492.55 230.5 497.05 3 L
N
235 497.05 239.5 492.55 244 497.05 3 L
N
248.5 497.05 253 492.55 257.5 497.05 3 L
N
262 497.05 266.5 492.55 271 497.05 3 L
N
216.57 492.55 212.07 492.55 2 L
N
276.05 493.68 278.3 492.55 276.05 491.43 3 Y
N
217.86 442.2 276.36 451.2 R
N
222.36 451.2 226.86 446.7 231.36 451.2 3 L
N
235.86 451.2 240.36 446.7 244.86 451.2 3 L
N
249.36 451.2 253.86 446.7 258.36 451.2 3 L
N
262.86 451.2 267.36 446.7 271.86 451.2 3 L
N
217.43 446.7 212.93 446.7 2 L
N
276.91 447.82 279.16 446.7 276.91 445.57 3 Y
N
218 472.77 276.5 481.77 R
N
222.5 481.77 227 477.27 231.5 481.77 3 L
N
236 481.77 240.5 477.27 245 481.77 3 L
N
249.5 481.77 254 477.27 258.5 481.77 3 L
N
263 481.77 267.5 477.27 272 481.77 3 L
N
217.57 477.27 213.07 477.27 2 L
N
277.05 478.39 279.3 477.27 277.05 476.14 3 Y
N
(\245) 239.44 466 T
(\245) 239.44 454 T
278.3 492.29 305.3 492.29 2 L
N
280.87 477.14 307.87 477.14 2 L
N
279.36 447.29 303.66 447.29 2 L
N
218 418.48 276.5 427.48 R
N
222.5 427.48 227 422.98 231.5 427.48 3 L
N
236 427.48 240.5 422.98 245 427.48 3 L
N
249.5 427.48 254 422.98 258.5 427.48 3 L
N
263 427.48 267.5 422.98 272 427.48 3 L
N
217.57 422.98 213.07 422.98 2 L
N
277.05 424.11 279.3 422.98 277.05 421.86 3 Y
N
279.44 422.43 369.44 422.43 2 L
N
363.84 462.5 363.84 318.5 390.84 318.5 444.84 426.5 462.84 426.5 480.84 444.5 462.84 462.5
453.84 462.5 444.84 462.5 417.84 462.5 10 Y
6 X
V
0 X
N
(15) 372.84 444.5 T
(14) 372.84 417.5 T
(2) 372.84 363.5 T
(1) 372.84 336.5 T
7 X
90 450 40.5 31.5 305.94 348.21 G
0 X
90 450 40.5 31.5 305.94 348.21 A
7 X
90 450 22.5 40.5 293.94 348.36 G
0 X
90 450 22.5 40.5 293.94 348.36 A
261.44 271.71 306.44 388.71 R
7 X
V
N
225 365.77 283.5 374.77 R
0 X
N
229.5 374.77 234 370.27 238.5 374.77 3 L
N
243 374.77 247.5 370.27 252 374.77 3 L
N
256.5 374.77 261 370.27 265.5 374.77 3 L
N
270 374.77 274.5 370.27 279 374.77 3 L
N
224.57 370.27 220.07 370.27 2 L
N
284.05 371.39 286.3 370.27 284.05 369.14 3 Y
N
225.86 319.91 284.36 328.91 R
N
230.36 328.91 234.86 324.41 239.36 328.91 3 L
N
243.86 328.91 248.36 324.41 252.86 328.91 3 L
N
257.36 328.91 261.86 324.41 266.36 328.91 3 L
N
270.86 328.91 275.36 324.41 279.86 328.91 3 L
N
225.43 324.41 220.93 324.41 2 L
N
284.91 325.54 287.16 324.41 284.91 323.29 3 Y
N
226 350.48 284.5 359.48 R
N
230.5 359.48 235 354.98 239.5 359.48 3 L
N
244 359.48 248.5 354.98 253 359.48 3 L
N
257.5 359.48 262 354.98 266.5 359.48 3 L
N
271 359.48 275.5 354.98 280 359.48 3 L
N
225.57 354.98 221.07 354.98 2 L
N
285.05 356.11 287.3 354.98 285.05 353.86 3 Y
N
286.3 370 313.3 370 2 L
N
288.87 354.86 315.87 354.86 2 L
N
287.36 325 311.66 325 2 L
N
226 336.2 284.5 345.2 R
N
230.5 345.2 235 340.7 239.5 345.2 3 L
N
244 345.2 248.5 340.7 253 345.2 3 L
N
257.5 345.2 262 340.7 266.5 345.2 3 L
N
271 345.2 275.5 340.7 280 345.2 3 L
N
225.57 340.7 221.07 340.7 2 L
N
285.05 341.82 287.3 340.7 285.05 339.57 3 Y
N
288.01 340.71 315.01 340.71 2 L
N
275.44 385 302.44 394 R
7 X
V
N
347.44 349 356.44 349 356.44 367 365.44 367 4 L
0 X
N
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "33" 39
%%Page: "34" 40
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(34) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(5.4 Integrated Interrupt Request Contr) 72 721 T
(oller) 279.42 721 T
(5.4.1 Block Diagram and Ov) 72 677 T
(er) 223.22 677 T
(view) 233.76 677 T
2 F
0.53 (The Inte) 72 655 P
0.53 (grated Interrupt Request Controller\050IIRC\051 is a 15 channel, programmable trigger) 112.67 655 P
0.19 (interrupt controller that arbitrates pending unmask) 72 641 P
0.19 (ed interrupt requests, encodes the high-) 314.44 641 P
0.78 (est priority interrupt request into a 4 bit code compatible with SP) 72 627 P
0.78 (ARC-V8 de\336ned Inter-) 391.13 627 P
0.55 (rupt Request Le) 72 613 P
0.55 (v) 149.46 613 P
0.55 (el\050IRL\051, and applies this code to IRL<3:0>. If traps are enabled and the) 155.27 613 P
1.07 (code on IRL<3:0> is greater than the processor interrupt le) 72 599 P
1.07 (v) 363.84 599 P
1.07 (el set in the processor state) 369.66 599 P
-0.09 (re) 72 585 P
-0.09 (gister or the code is 15, then the processor is interrupted. The processor responds by ser-) 81.14 585 P
1 (vicing the interrupt and clearing the latched interrupt request in IIRC. Figure 6 sho) 72 571 P
1 (ws a) 481.34 571 P
(block diagram of the IIRC.) 72 557 T
0.22 (Control of the IIRC is on a feature-by-feature basis: all inputs share the input control re) 72 535 P
0.22 (g-) 494 535 P
(ister) 72 521 T
(, the latch re) 92.18 521 T
(gister and the mask re) 151.32 521 T
(gister) 256.45 521 T
(.) 282.46 521 T
0 F
(Figur) 209.45 251 T
(e 6:) 237.9 251 T
(IIRC Block Diagram) 259.22 251 T
2 F
-0.05 (T) 72 213 P
-0.05 (rigger Mode Control logic selects one of four trigger modes for each channel: high le) 78.91 213 P
-0.05 (v) 486.52 213 P
-0.05 (el,) 492.34 213 P
-0.27 (lo) 72 199 P
-0.27 (w le) 81.04 199 P
-0.27 (v) 100.79 199 P
-0.27 (el, rising edge or f) 106.61 199 P
-0.27 (alling edge. The program sets the selection code by writing to the) 193.05 199 P
(T) 72 185 T
(rigger Mode re) 78.91 185 T
(gisters.) 150.71 185 T
1.16 (Each Interrupt Request that satis\336es the trigger mode conditions is captured in the IRQ) 72 163 P
0.66 (latch. The program may read the latch through the Request Sense re) 72 149 P
0.66 (gister and may clear) 405.04 149 P
(the latch by writing to the Request Clear re) 72 135 T
(gister) 278.46 135 T
(.) 304.46 135 T
0.55 (Indi) 72 113 P
0.55 (vidual Interrupt Requests may be block) 91.03 113 P
0.55 (ed by the IRQ Mask logic. The program con-) 282.64 113 P
(trols the masking by writing to the Mask re) 72 99 T
(gister) 279.14 99 T
(.) 305.15 99 T
72 81 504 729 C
79.5 261 496.5 495 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
151.5 387 178.5 477 R
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
205.5 387 232.5 477 R
N
313.5 387 340.5 477 R
N
367.5 432 394.5 477 R
N
421.5 432 448.5 477 R
N
142.5 315 466.5 315 2 L
N
142.5 306 466.5 306 2 L
N
466.18 315.36 466.18 324.36 488.68 310.86 466.18 297.36 466.18 306.36 5 L
N
142.4 315.21 142.4 324.21 119.9 310.71 142.4 297.21 142.4 306.21 5 L
N
161.68 319.33 161.68 381.44 2 L
N
167.11 319.33 167.11 381.44 2 L
N
162.14 381.67 157.64 381.67 164.39 385.98 171.14 381.67 166.64 381.67 5 L
N
162.29 319.16 157.79 319.16 164.54 315.71 171.29 319.16 166.79 319.16 5 L
N
215.39 319.9 215.39 382.01 2 L
N
220.82 319.9 220.82 382.01 2 L
N
215.86 382.24 211.36 382.24 218.11 386.55 224.86 382.24 220.36 382.24 5 L
N
216 319.73 211.5 319.73 218.25 316.29 225 319.73 220.5 319.73 5 L
N
324.11 319.75 324.11 381.87 2 L
N
329.54 319.75 329.54 381.87 2 L
N
324.57 382.1 320.07 382.1 326.82 386.41 333.57 382.1 329.07 382.1 5 L
N
324.71 319.59 320.21 319.59 326.96 316.14 333.71 319.59 329.21 319.59 5 L
N
377.82 321.01 377.82 424.42 2 L
N
383.25 321.01 383.25 424.42 2 L
N
378.28 424.8 373.78 424.8 380.53 431.98 387.28 424.8 382.78 424.8 5 L
N
378.43 320.74 373.93 320.74 380.68 315 387.43 320.74 382.93 320.74 5 L
N
270.39 320.62 270.39 343.98 2 L
N
275.82 320.62 275.82 343.98 2 L
N
270.86 344.51 266.36 344.51 273.11 351 279.86 344.51 275.36 344.51 5 L
N
271 320.19 266.5 320.19 273.25 315 280 320.19 275.5 320.19 5 L
N
140.21 468 140.21 470.98 150.59 468 140.21 465.02 4 Y
0 Z
N
140.21 468 140.21 470.98 150.59 468 140.21 465.02 4 Y
V
124.5 468 139.96 468 2 L
2 Z
N
140.36 460 140.36 462.98 150.74 460 140.36 457.02 4 Y
0 Z
N
140.36 460 140.36 462.98 150.74 460 140.36 457.02 4 Y
V
124.64 460 140.11 460 2 L
2 Z
N
140.5 452 140.5 454.98 150.88 452 140.5 449.02 4 Y
0 Z
N
140.5 452 140.5 454.98 150.88 452 140.5 449.02 4 Y
V
124.79 452 140.25 452 2 L
2 Z
N
139.93 444 139.93 446.98 150.31 444 139.93 441.02 4 Y
0 Z
N
139.93 444 139.93 446.98 150.31 444 139.93 441.02 4 Y
V
124.21 444 139.68 444 2 L
2 Z
N
140.07 436 140.07 438.98 150.45 436 140.07 433.02 4 Y
0 Z
N
140.07 436 140.07 438.98 150.45 436 140.07 433.02 4 Y
V
124.36 436 139.82 436 2 L
2 Z
N
140.22 428 140.22 430.98 150.59 428 140.22 425.02 4 Y
0 Z
N
140.22 428 140.22 430.98 150.59 428 140.22 425.02 4 Y
V
124.5 428 139.97 428 2 L
2 Z
N
140.36 395 140.36 397.98 150.74 395 140.36 392.02 4 Y
0 Z
N
140.36 395 140.36 397.98 150.74 395 140.36 392.02 4 Y
V
124.64 395 140.11 395 2 L
2 Z
N
193.93 467.86 193.93 470.83 204.31 467.86 193.93 464.88 4 Y
0 Z
N
193.93 467.86 193.93 470.83 204.31 467.86 193.93 464.88 4 Y
V
178.21 467.86 193.68 467.86 2 L
2 Z
N
194.07 459.86 194.07 462.83 204.45 459.86 194.07 456.88 4 Y
0 Z
N
194.07 459.86 194.07 462.83 204.45 459.86 194.07 456.88 4 Y
V
178.36 459.86 193.82 459.86 2 L
2 Z
N
194.21 451.86 194.21 454.83 204.59 451.86 194.21 448.88 4 Y
0 Z
N
194.21 451.86 194.21 454.83 204.59 451.86 194.21 448.88 4 Y
V
178.5 451.86 193.96 451.86 2 L
2 Z
N
193.64 443.86 193.64 446.83 204.02 443.86 193.64 440.88 4 Y
0 Z
N
193.64 443.86 193.64 446.83 204.02 443.86 193.64 440.88 4 Y
V
177.93 443.86 193.39 443.86 2 L
2 Z
N
193.79 435.86 193.79 438.83 204.16 435.86 193.79 432.88 4 Y
0 Z
N
193.79 435.86 193.79 438.83 204.16 435.86 193.79 432.88 4 Y
V
178.07 435.86 193.54 435.86 2 L
2 Z
N
193.93 427.86 193.93 430.83 204.31 427.86 193.93 424.88 4 Y
0 Z
N
193.93 427.86 193.93 430.83 204.31 427.86 193.93 424.88 4 Y
V
178.21 427.86 193.68 427.86 2 L
2 Z
N
194.07 394.86 194.07 397.83 204.45 394.86 194.07 391.88 4 Y
0 Z
N
194.07 394.86 194.07 397.83 204.45 394.86 194.07 391.88 4 Y
V
178.36 394.86 193.82 394.86 2 L
2 Z
N
247.93 468 247.93 470.98 258.31 468 247.93 465.02 4 Y
0 Z
N
247.93 468 247.93 470.98 258.31 468 247.93 465.02 4 Y
V
232.21 468 247.68 468 2 L
2 Z
N
248.07 460 248.07 462.98 258.45 460 248.07 457.02 4 Y
0 Z
N
248.07 460 248.07 462.98 258.45 460 248.07 457.02 4 Y
V
232.36 460 247.82 460 2 L
2 Z
N
248.21 452 248.21 454.98 258.59 452 248.21 449.02 4 Y
0 Z
N
248.21 452 248.21 454.98 258.59 452 248.21 449.02 4 Y
V
232.5 452 247.96 452 2 L
2 Z
N
247.64 444 247.64 446.98 258.02 444 247.64 441.02 4 Y
0 Z
N
247.64 444 247.64 446.98 258.02 444 247.64 441.02 4 Y
V
231.93 444 247.39 444 2 L
2 Z
N
247.79 436 247.79 438.98 258.17 436 247.79 433.02 4 Y
0 Z
N
247.79 436 247.79 438.98 258.17 436 247.79 433.02 4 Y
V
232.07 436 247.54 436 2 L
2 Z
N
247.93 428 247.93 430.98 258.31 428 247.93 425.02 4 Y
0 Z
N
247.93 428 247.93 430.98 258.31 428 247.93 425.02 4 Y
V
232.21 428 247.68 428 2 L
2 Z
N
248.07 395 248.07 397.98 258.45 395 248.07 392.02 4 Y
0 Z
N
248.07 395 248.07 397.98 258.45 395 248.07 392.02 4 Y
V
232.36 395 247.82 395 2 L
2 Z
N
301.93 468 301.93 470.98 312.31 468 301.93 465.02 4 Y
0 Z
N
301.93 468 301.93 470.98 312.31 468 301.93 465.02 4 Y
V
286.21 468 301.68 468 2 L
2 Z
N
302.07 460 302.07 462.98 312.45 460 302.07 457.02 4 Y
0 Z
N
302.07 460 302.07 462.98 312.45 460 302.07 457.02 4 Y
V
286.36 460 301.82 460 2 L
2 Z
N
302.21 452 302.21 454.98 312.59 452 302.21 449.02 4 Y
0 Z
N
302.21 452 302.21 454.98 312.59 452 302.21 449.02 4 Y
V
286.5 452 301.96 452 2 L
2 Z
N
301.64 444 301.64 446.98 312.02 444 301.64 441.02 4 Y
0 Z
N
301.64 444 301.64 446.98 312.02 444 301.64 441.02 4 Y
V
285.93 444 301.39 444 2 L
2 Z
N
301.79 436 301.79 438.98 312.17 436 301.79 433.02 4 Y
0 Z
N
301.79 436 301.79 438.98 312.17 436 301.79 433.02 4 Y
V
286.07 436 301.54 436 2 L
2 Z
N
301.93 428 301.93 430.98 312.31 428 301.93 425.02 4 Y
0 Z
N
301.93 428 301.93 430.98 312.31 428 301.93 425.02 4 Y
V
286.21 428 301.68 428 2 L
2 Z
N
302.07 395 302.07 397.98 312.45 395 302.07 392.02 4 Y
0 Z
N
302.07 395 302.07 397.98 312.45 395 302.07 392.02 4 Y
V
286.36 395 301.82 395 2 L
2 Z
N
355.93 468 355.93 470.98 366.31 468 355.93 465.02 4 Y
0 Z
N
355.93 468 355.93 470.98 366.31 468 355.93 465.02 4 Y
V
340.21 468 355.68 468 2 L
2 Z
N
356.07 460 356.07 462.98 366.45 460 356.07 457.02 4 Y
0 Z
N
356.07 460 356.07 462.98 366.45 460 356.07 457.02 4 Y
V
340.36 460 355.82 460 2 L
2 Z
N
356.21 452 356.21 454.98 366.59 452 356.21 449.02 4 Y
0 Z
N
356.21 452 356.21 454.98 366.59 452 356.21 449.02 4 Y
V
340.5 452 355.96 452 2 L
2 Z
N
355.64 444 355.64 446.98 366.02 444 355.64 441.02 4 Y
0 Z
N
355.64 444 355.64 446.98 366.02 444 355.64 441.02 4 Y
V
339.93 444 355.39 444 2 L
2 Z
N
409.93 467.86 409.93 470.83 420.31 467.86 409.93 464.88 4 Y
0 Z
N
409.93 467.86 409.93 470.83 420.31 467.86 409.93 464.88 4 Y
V
394.21 467.86 409.68 467.86 2 L
2 Z
N
410.07 459.86 410.07 462.83 420.45 459.86 410.07 456.88 4 Y
0 Z
N
410.07 459.86 410.07 462.83 420.45 459.86 410.07 456.88 4 Y
V
394.36 459.86 409.82 459.86 2 L
2 Z
N
410.21 451.86 410.21 454.83 420.59 451.86 410.21 448.88 4 Y
0 Z
N
410.21 451.86 410.21 454.83 420.59 451.86 410.21 448.88 4 Y
V
394.5 451.86 409.96 451.86 2 L
2 Z
N
409.64 443.86 409.64 446.83 420.02 443.86 409.64 440.88 4 Y
0 Z
N
409.64 443.86 409.64 446.83 420.02 443.86 409.64 440.88 4 Y
V
393.93 443.86 409.39 443.86 2 L
2 Z
N
464.64 467.86 464.64 470.83 475.02 467.86 464.64 464.88 4 Y
0 Z
N
464.64 467.86 464.64 470.83 475.02 467.86 464.64 464.88 4 Y
V
448.93 467.86 464.39 467.86 2 L
2 Z
N
464.79 459.86 464.79 462.83 475.17 459.86 464.79 456.88 4 Y
0 Z
N
464.79 459.86 464.79 462.83 475.17 459.86 464.79 456.88 4 Y
V
449.07 459.86 464.54 459.86 2 L
2 Z
N
464.93 451.86 464.93 454.83 475.31 451.86 464.93 448.88 4 Y
0 Z
N
464.93 451.86 464.93 454.83 475.31 451.86 464.93 448.88 4 Y
V
449.21 451.86 464.68 451.86 2 L
2 Z
N
464.36 443.86 464.36 446.83 474.74 443.86 464.36 440.88 4 Y
0 Z
N
464.36 443.86 464.36 446.83 474.74 443.86 464.36 440.88 4 Y
V
448.64 443.86 464.11 443.86 2 L
2 Z
N
2 10 Q
(\245) 133.5 419.71 T
(\245) 133.5 409.71 T
(\245) 133.5 399.71 T
(\245) 185.07 419.57 T
(\245) 185.07 409.57 T
(\245) 185.07 399.57 T
(\245) 241.5 419.04 T
(\245) 241.5 409.04 T
(\245) 241.5 399.04 T
2 8 Q
(IRQ1) 106.5 468 T
(IRQ2) 106.5 460 T
(IRQ3) 106.5 452 T
(IRQ4) 106.5 444 T
(IRQ5) 106.5 436 T
(IRQ6) 106.5 428 T
(IRQ15) 106.5 396 T
435.21 420.71 432.24 420.71 435.21 431.09 438.19 420.71 4 Y
0 Z
N
435.21 420.71 432.24 420.71 435.21 431.09 438.19 420.71 4 Y
V
277.5 360 435.21 360 435.21 420.46 3 L
2 Z
N
259.5 351 286.5 477 R
7 X
V
0 X
N
(IRL) 439.5 414 T
(Mask) 439.5 406 T
(Control) 439.5 398 T
(T) 142.5 486 T
(rigger Mode) 147.11 486 T
(IRQ) 210.88 486 T
(IRQ) 264.65 486 T
(Priority) 312.43 486 T
(IRL) 372.88 486 T
(IRL) 427.76 486 T
(Control) 152.5 478 T
(Latch) 206.95 478 T
(Mask) 263.16 478 T
(Encoder) 312.94 478 T
( Latch) 369.6 478 T
(Match) 425.81 478 T
(D<15:0>) 425.5 321 T
72 81 504 729 C
0 0 612 792 C
2 10 Q
0 X
0 0 0 1 0 0 0 K
(\245) 297.82 455.1 T
(\245) 297.82 445.1 T
(\245) 297.82 435.1 T
FMENDPAGE
%%EndPage: "34" 40
%%Page: "35" 41
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(35) 528 17 T
-0.05 (All unmask) 108 721 P
-0.05 (ed Interrupt Requests are e) 163.49 721 P
-0.05 (xamined by the Priority Encoder) 291.73 721 P
-0.05 (. The highest prior-) 447.51 721 P
(ity is encoded. IRQ15 has the highest priority and IRQ1 the lo) 108 707 T
(west.) 406.34 707 T
(That encoded interrupt le) 108 685 T
(v) 228.67 685 T
(el from the Priority Encoder is captured in the IRL Latch.) 234.49 685 T
-0.25 (The IRL Mask logic can block all interrupt requests by forcing the output of the IRL Latch) 108 663 P
-0.13 (going to the IRL lines to zero. The program controls IRL masking by writing to a reserv) 108 649 P
-0.13 (ed) 528.67 649 P
-0.05 (bit in the Mask re) 108 635 P
-0.05 (gister) 192.29 635 P
-0.05 (. Ev) 218.29 635 P
-0.05 (en if the IRL Latch is mask) 237.39 635 P
-0.05 (ed of) 368.3 635 P
-0.05 (f, programs may poll for pend-) 392.27 635 P
(ing interrupts by reading the Request Sense re) 108 621 T
(gister) 328.79 621 T
(.) 354.79 621 T
0 F
(5.4.2 IIRC Registers) 108 577 T
2 F
-0.12 (The IIRC has six internal re) 108 555 P
-0.12 (gisters that allo) 240.86 555 P
-0.12 (w the program to control IIRC operation and to) 313.66 555 P
1.08 (monitor interrupt requests that may be pending. Re) 108 541 P
1.08 (gisters are mapped, aligned by func-) 360 541 P
(tion, into ASI 1 at successi) 108 527 T
(v) 236.36 527 T
(e w) 242.18 527 T
(ord addresses as sho) 259.06 527 T
(wn in T) 356.4 527 T
(able X.) 392.77 527 T
0 F
(5.4.2.1 T) 108 313 T
(rigger Modes Register Operation) 157.12 313 T
2 F
0.29 (T) 108 291 P
0.29 (rigger Mode re) 114.91 291 P
0.29 (gisters control the trigger mode for each interrupt channel. T) 187.28 291 P
0.29 (rigger Mode) 480.06 291 P
0.22 (Re) 108 277 P
0.22 (gister 0 controls modes for channels 8-15. T) 121.15 277 P
0.22 (rigger Mode Re) 334.23 277 P
0.22 (gister 1 controls modes for) 410.47 277 P
(channels 1-7.) 108 263 T
0 10 Q
(Addr) 198.33 498.33 T
(ess) 220.93 498.33 T
(Register) 304.41 498.33 T
(Requir) 395.12 498.33 T
(ed Access) 424.94 498.33 T
2 F
(IRC-REG + 0) 169.2 478.33 T
(T) 274.28 478.33 T
(rigger Mode 0) 280.04 478.33 T
(Write) 382.07 478.33 T
(IIRC-REG + 4) 169.2 458.33 T
(T) 274.28 458.33 T
(rigger Mode 1) 280.04 458.33 T
(Write) 382.07 458.33 T
(IIRC-REG + 8) 169.2 438.33 T
(Request Sense) 274.28 438.33 T
(Read) 382.07 438.33 T
(IIRC-REG + C) 169.2 418.33 T
(Request Clear) 274.28 418.33 T
(Write) 382.07 418.33 T
(IIRC-REG +10) 169.2 398.33 T
(Mask) 274.28 398.33 T
(Write) 382.07 398.33 T
(IIRC-REG +14) 169.2 378.33 T
(IRL Latch/Clear) 274.28 378.33 T
(Read/Write) 382.07 378.33 T
0 12 Q
(T) 228.74 357 T
(able 4:) 235.64 357 T
(IIRC Register Memory Map) 272.97 357 T
163.2 510.75 163.2 371.25 2 L
V
0.5 H
0 Z
N
268.28 511.25 268.28 370.75 2 L
V
N
376.07 511.25 376.07 370.75 2 L
V
N
484.8 510.75 484.8 371.25 2 L
V
N
162.95 511 485.05 511 2 L
V
N
163.45 492.25 484.55 492.25 2 L
V
N
163.45 489.75 484.55 489.75 2 L
V
N
162.95 371 485.05 371 2 L
V
N
FMENDPAGE
%%EndPage: "35" 41
%%Page: "36" 42
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(36) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
-0.15 (Each tw) 72 493 P
-0.15 (o bit \336eld in the re) 110.71 493 P
-0.15 (gisters selects one of four trigger modes for each channel as fol-) 198.1 493 P
(lo) 72 479 T
(ws:) 81.04 479 T
0.73 (Reset clears the T) 72 315 P
0.73 (rigger Mode re) 159.43 315 P
0.73 (gisters, initializing high le) 232.69 315 P
0.73 (v) 359.93 315 P
0.73 (el triggering for all interrupt) 365.75 315 P
(channels.) 72 301 T
(T) 72 279 T
(rigger modes will be e) 78.91 279 T
(xplained in 5.4.3.3.) 186.05 279 T
2 10 Q
(Note:) 72 254.33 T
( Changing trigger mode of an unmask) 108 242.33 T
(ed channel may result in a f) 259.55 242.33 T
(alse interrupt.) 369.98 242.33 T
0 12 Q
(5.4.2.2 Request Sense Register Operation) 72 199 T
2 F
0.8 (The program reads the state of the IRQ Latch through the Request Sense Re) 72 177 P
0.8 (gister) 447.2 177 P
0.8 (. Each) 473.21 177 P
(one bit indicates a pending interrupt.) 72 163 T
0 10 Q
(MDx) 220.92 450.33 T
(T) 314.77 450.33 T
(rigger Mode) 320.7 450.33 T
2 12 Q
(0) 181.5 429 T
2 10 Q
(high le) 294 430.33 T
(v) 321.25 430.33 T
(el) 326.1 430.33 T
2 12 Q
(1) 181.5 407 T
2 10 Q
(lo) 294 408.33 T
(w le) 301.53 408.33 T
(v) 318.22 408.33 T
(el) 323.07 408.33 T
2 12 Q
(2) 181.5 385 T
2 10 Q
(rising edge) 294 386.33 T
2 12 Q
(3) 181.5 363 T
2 10 Q
(f) 294 364.33 T
(alling edge) 297.23 364.33 T
0 12 Q
(T) 230.5 341 T
(able 5:) 237.4 341 T
(T) 274.73 341 T
(rigger Mode) 281.85 341 T
175.5 462.75 175.5 355.25 2 L
V
0.5 H
0 Z
N
400.5 462.75 400.5 355.25 2 L
V
N
175.25 463 400.75 463 2 L
V
N
175.75 444.25 400.25 444.25 2 L
V
N
175.75 441.75 400.25 441.75 2 L
V
N
175.25 355 400.75 355 2 L
V
N
72 81 504 729 C
72 625 504 717 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 75.88 667.3 T
(16) 300.98 667.29 T
(11) 365.47 667.29 T
(12) 351.53 667.3 T
(0) 495.39 667.3 T
73.4 678.33 498.74 700.84 R
7 X
V
1 H
0 Z
0 X
N
309.5 700.12 309.5 679.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
336.86 700.12 336.86 679.12 2 L
7 X
V
0 X
N
362.52 700.12 362.52 679.12 2 L
7 X
V
0 X
N
(10) 376.33 667.29 T
(9) 394.17 667.29 T
479.5 700.12 479.5 679.12 2 L
7 X
V
0 X
N
(1) 486 667.29 T
(2) 475 667.29 T
(3) 466 667.29 T
457.36 700.12 457.36 679.12 2 L
7 X
V
0 X
N
432.21 700.12 432.21 679.12 2 L
7 X
V
0 X
N
412.21 700.12 412.21 679.12 2 L
7 X
V
0 X
N
387.5 700.12 387.5 679.12 2 L
7 X
V
0 X
N
(4) 452 667.29 T
(5) 440 667.29 T
(6) 430 667.29 T
(7) 418 667.29 T
(8) 409 667.29 T
(13) 341 667.29 T
(14) 330 667.29 T
(15) 317 667.29 T
(md8) 482 687.27 T
(md9) 462 687.27 T
(md10) 435 687.27 T
(md11) 413 687.27 T
(md12) 391.43 687.27 T
(md13) 367 687.27 T
(md14) 342 687.27 T
(md15) 312 687.27 T
7 7 Q
(reser) 166 688 T
(v) 182.16 688 T
(ed) 185.48 688 T
6 12 Q
(T) 221 638 T
(r) 226.89 638 T
(igger Mode Register 0) 231.07 638 T
72 81 504 729 C
0 0 612 792 C
72 81 504 729 C
72 533 504 625 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 75.88 575.3 T
(16) 300.98 575.29 T
(11) 365.47 575.29 T
(12) 351.53 575.3 T
(0) 495.39 575.3 T
73.4 586.33 498.74 608.84 R
7 X
V
1 H
0 Z
0 X
N
309.5 608.12 309.5 587.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
336.86 608.12 336.86 587.12 2 L
7 X
V
0 X
N
362.52 608.12 362.52 587.12 2 L
7 X
V
0 X
N
(10) 376.33 575.29 T
(9) 394.17 575.29 T
479.5 608.12 479.5 587.12 2 L
7 X
V
0 X
N
(1) 486 575.29 T
(2) 475 575.29 T
(3) 462.43 575.29 T
457.36 608.12 457.36 587.12 2 L
7 X
V
0 X
N
432.21 608.12 432.21 587.12 2 L
7 X
V
0 X
N
412.21 608.12 412.21 587.12 2 L
7 X
V
0 X
N
387.5 608.12 387.5 587.12 2 L
7 X
V
0 X
N
(4) 452 575.29 T
(5) 440 575.29 T
(6) 430 575.29 T
(7) 418 575.29 T
(8) 409 575.29 T
(13) 341 575.29 T
(14) 326.43 575.29 T
(15) 313.43 575.29 T
(md 1) 460.33 595.27 T
(md 2) 435 595.27 T
(md 3) 413 595.27 T
(md 4) 391.43 595.27 T
(md 5) 367 595.27 T
(md 6) 342 595.27 T
(md 7) 315.33 595.27 T
7 7 Q
(reser) 166 596 T
(v) 182.16 596 T
(ed) 185.48 596 T
6 12 Q
(T) 221 546 T
(r) 226.89 546 T
(igger Mode Register 1) 231.07 546 T
6 8 Q
(r) 487.57 595.27 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "36" 42
%%Page: "37" 43
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(37) 528 17 T
(.) 108 721 T
(Reset clears the Request Sense Re) 108 607 T
(gister) 272.12 607 T
(.) 298.13 607 T
0 F
(5.4.2.3 Request Clear Register Operation) 108 563 T
2 F
0.06 (Writing one's to selected bits of the Request Clear Re) 108 541 P
0.06 (gister clears corresponding elements) 364.85 541 P
0.19 (of the IRQ Latch. The program typically uses this re) 108 527 P
0.19 (gister to clear the latch element asso-) 360.87 527 P
(ciated with the interrupt channel that it has be) 108 513 T
(gun to service.) 327.12 513 T
(Reset clears the Request Clear Re) 108 399 T
(gister) 270.12 399 T
(.) 296.12 399 T
2 10 Q
(Note:) 108 374.33 T
0.16 (When changing trigger mode for an interrupt channel, its IRQ Latch element may be set and if not) 144 362.33 P
(cleared after the change in trigger mode, may result in a f) 144 350.33 T
(alse interrupt.) 373.28 350.33 T
0 12 Q
(5.4.2.4 Mask Register Operation) 108 307 T
2 F
0.52 (Ones in the Mask Re) 108 285 P
0.52 (gister block corresponding outputs of the IRQ Latch from e) 210.55 285 P
0.52 (xamina-) 500.68 285 P
1.65 (tion by Priority Encoder) 108 271 P
1.65 (, or) 228.81 271 P
1.65 (, alternati) 245.98 271 P
1.65 (v) 292.66 271 P
1.65 (ely with a one in bit zero of the Mask Re) 298.48 271 P
1.65 (gister) 510.82 271 P
1.65 (,) 537 271 P
-0.25 (block the output of the IRL Latch from dri) 108 257 P
-0.25 (ving the IRL<3:0> lines. Using the Mask Re) 309.7 257 P
-0.25 (gis-) 522 257 P
0.39 (ter) 108 243 P
0.39 (, the program may mask unused interrupt channels, temporarily mask indi) 120.18 243 P
0.39 (vidual acti) 478.43 243 P
0.39 (v) 528.85 243 P
0.39 (e) 534.67 243 P
(interrupt channels or mask all interrupt channels.) 108 229 T
(Reset clears the Mask Re) 108 115 T
(gister) 229.13 115 T
(.) 255.13 115 T
108 81 540 729 C
108 625 540 717 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 111.88 667.3 T
(16) 336.98 667.29 T
(0) 531.39 667.3 T
109.4 678.33 534.74 700.84 R
7 X
V
1 H
0 Z
0 X
N
345.5 700.12 345.5 679.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
515.5 700.12 515.5 679.12 2 L
7 X
V
0 X
N
(1) 511 667.29 T
(15) 349.43 667.29 T
7 F
(reser) 202 688 T
(v) 220.46 688 T
(ed) 224.26 688 T
6 12 Q
(Request Sense Register) 257 638 T
6 8 Q
(r) 523.57 687.27 T
(Request Sense) 412 686 T
108 81 540 729 C
0 0 612 792 C
108 81 540 729 C
108 417 540 509 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 111.88 459.3 T
(16) 336.98 459.29 T
(0) 531.39 459.3 T
109.4 470.33 534.74 492.84 R
7 X
V
1 H
0 Z
0 X
N
345.5 492.12 345.5 471.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
515.5 492.12 515.5 471.12 2 L
7 X
V
0 X
N
(1) 511 459.29 T
(15) 349.43 459.29 T
7 F
(reser) 202 480 T
(v) 220.46 480 T
(ed) 224.26 480 T
6 12 Q
(Request Clear Register) 257 430 T
6 8 Q
(r) 523.57 479.27 T
(Request Clear) 412 478 T
108 81 540 729 C
0 0 612 792 C
108 81 540 729 C
108 133 540 225 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 111.88 175.3 T
(16) 336.98 175.29 T
(0) 531.39 175.3 T
109.4 186.33 534.74 208.84 R
7 X
V
1 H
0 Z
0 X
N
345.5 208.12 345.5 187.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
498.5 208.12 498.5 187.12 2 L
7 X
V
0 X
N
(1) 494 175.29 T
(15) 349.43 175.29 T
7 F
(reser) 202 197 T
(v) 220.46 197 T
(ed) 224.26 197 T
6 12 Q
(Mask Register) 304 146 T
6 8 Q
(Mask) 412 197 T
(MKIRL) 507 197 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "37" 43
%%Page: "38" 44
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(38) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(5.4.2.5 IRL Latch/Clear Register Operation) 72 721 T
2 F
-0.29 (The program uses the IRL Latch/Clear re) 72 699 P
-0.29 (gister to read or clear the IRL Latch. Reading this) 268.02 699 P
0.15 (re) 72 685 P
0.15 (gister will return the IRL code on bits 3:0. Writing one to bit 4 of this re) 81.14 685 P
0.15 (gister will clear) 429.04 685 P
0.25 (the IRL Latch. These capabilities permit optionally handling interrupt requests by polling) 72 671 P
(rather than v) 72 657 T
(ectored interrupts.) 132.47 657 T
(Reset clears the IRL Latch/Clear Re) 72 521 T
(gister) 245.45 521 T
0 F
(5.4.3 IIRC Operation) 72 477 T
2 F
1.93 (The IIRC latches interrupt requests into the IRQ Latch according to the trigger mode) 72 455 P
2.25 (option selected for each interrupt channel. The Priority Encoder prioritizes unmask) 72 441 P
2.25 (ed) 492.67 441 P
0.46 (interrupts and generates an encoded interrupt le) 72 427 P
0.46 (v) 302.42 427 P
0.46 (el code for the highest priority interrupt.) 308.24 427 P
1.32 (The IRL Latch holds that code which is transferred through the IRL Mask logic to the) 72 413 P
0.88 (IRL<3:0> lines for processor interrupt. If an interrupt occurs, the response program ser-) 72 399 P
0.66 (vices the interrupt request identi\336ed on IRL<3:0> and clears both the IRL Latch and the) 72 385 P
(latched interrupt request in the IRQ Latch.) 72 371 T
0 F
(5.4.3.1 P) 72 327 T
(olling) 121.09 327 T
2 F
0.72 (The processor can poll interrupts by reading either the IRQ Latch via the Request Sense) 72 305 P
(re) 72 291 T
(gister or the IRL Latch via the IRL Latch/Clear re) 81.14 291 T
(gister) 320.58 291 T
(.) 346.58 291 T
-0.22 (The processor may mask interrupts that it polls via the Request Sense Re) 72 269 P
-0.22 (gister by masking) 419.11 269 P
0.88 (indi) 72 255 P
0.88 (vidual elements of the IRQ Latch or by masking the entire IRL Latch. T) 90.37 255 P
0.88 (ypically the) 446.79 255 P
0.07 (processor periodically reads the IRQ Latch and clears interrupts from the latch as the) 72 241 P
0.07 (y are) 480.28 241 P
-0.25 (serviced. In case of multiple entries in the IRQ Latch, the SCAN instruction can be used to) 72 227 P
0.19 (identify the one entry in the highest bit position. The IRL Latch may remain unmask) 72 213 P
0.19 (ed to) 480.15 213 P
2.93 (allo) 72 199 P
2.93 (w v) 89.7 199 P
2.93 (ectored interrupt servicing of some interrupt requests if polled interrupts are) 110.11 199 P
0.14 (mask) 72 185 P
0.14 (ed in the IRQ Latch \336eld of the Mask Re) 97.21 185 P
0.14 (gister so that the) 294.57 185 P
0.14 (y are block) 373.8 185 P
0.14 (ed from the Pri-) 427.27 185 P
(ority Encoder) 72 171 T
(.) 136.99 171 T
0.59 (The processor may mask all interrupts when it polls via the IRL Latch/Clear Re) 72 149 P
0.59 (gister by) 461.75 149 P
1.68 (masking the IRL Latch, Mask Re) 72 135 P
1.68 (gister bit 0 = 1. T) 240.21 135 P
1.68 (ypically) 331.1 135 P
1.68 (, the processor periodically) 368.98 135 P
0.41 (reads the IRL Latch for the highest le) 72 121 P
0.41 (v) 254.23 121 P
0.41 (el pending interrupt and clears both the IRL Latch) 260.05 121 P
(and the interrupt from the IRQ Latch once the interrupt is serviced.) 72 107 T
72 81 504 729 C
72 539 504 631 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
6 8 Q
0 X
0 0 0 1 0 0 0 K
(31) 75.88 581.3 T
(16) 300.98 581.29 T
(0) 495.39 581.3 T
73.4 592.33 498.74 614.84 R
7 X
V
1 H
0 Z
0 X
N
309.5 614.12 309.5 593.12 2 L
7 X
V
0.5 H
2 Z
0 X
N
462.5 614.12 462.5 593.12 2 L
7 X
V
0 X
N
(4) 458 581.29 T
(15) 313.43 581.29 T
7 F
(reser) 166 602 T
(v) 184.46 602 T
(ed) 188.26 602 T
6 12 Q
(IRL Latch/Clear Register) 237.17 555.33 T
7 8 Q
(reser) 376 602 T
(v) 394.46 602 T
(ed) 398.26 602 T
6 F
(int. le) 469 602 T
(v) 487.88 602 T
(el) 491.68 602 T
(3) 467 581.29 T
449.5 615.12 449.5 594.12 2 L
7 X
V
0 X
N
(5) 440 581.29 T
(Cl) 454 602 T
(Cl= clear) 434.83 561.5 T
(int. le) 434.83 553.5 T
(v) 453.71 553.5 T
(el= interr) 457.52 553.5 T
(upt) 488.98 553.5 T
(le) 470.67 545.67 T
(v) 476.65 545.67 T
(el) 480.45 545.67 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "38" 44
%%Page: "39" 45
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(39) 528 17 T
0 F
(5.4.3.2 Initialization) 108 721 T
2 F
0.24 (All IIRC re) 108 699 P
0.24 (gisters are cleared to 0 by Reset. This results in high le) 162.96 699 P
0.24 (v) 427.91 699 P
0.24 (el trigger mode for all) 433.73 699 P
(interrupts and all masks disabled.) 108 685 T
-0.15 (After reset, the interrupt trigger should be changed after the interrupts are mask) 108 663 P
-0.15 (ed with the) 486.97 663 P
-0.1 (IRQ mask to eliminate f) 108 649 P
-0.1 (alse interrupts. F) 223.46 649 P
-0.1 (ollo) 303.39 649 P
-0.1 (wing this, the IRQ Latches should be cleared,) 321.77 649 P
(then the masks can be disabled.) 108 635 T
0 F
(5.4.3.3 Noise Immunity) 108 591 T
2 F
1.91 (The interrupt sample clock is synchronized with the processor clock and it is used to) 108 569 P
0.18 (e) 108 555 P
0.18 (xamine IRL<3:0> and eng) 113.15 555 P
0.18 (age the trap mechanism. The interrupt sample clock may ha) 240.83 555 P
0.18 (v) 528.85 555 P
0.18 (e) 534.67 555 P
1.11 (the same period as the processor clock or may be di) 108 541 P
1.11 (vided do) 366.77 541 P
1.11 (wn. The ratio of processor) 409.25 541 P
-0.14 (clock to interrupt sample clock is an implementation parameter) 108 527 P
-0.14 (. Sampling of the incoming) 409.54 527 P
1.16 (interrupt request signals tak) 108 513 P
1.16 (es place at the rising or f) 244.36 513 P
1.16 (alling edge of the interrupt sample) 369.2 513 P
(clock. This is also an implementation parameter) 108 499 T
(.) 337.64 499 T
2.03 (F) 108 477 P
2.03 (or le) 114.49 477 P
2.03 (v) 137.88 477 P
2.03 (el mode triggering, a number of successi) 143.7 477 P
2.03 (v) 350.52 477 P
2.03 (e samples at the required le) 356.35 477 P
2.03 (v) 497.15 477 P
2.03 (el must) 502.97 477 P
(occur) 108 463 T
(. That number is also an implementation parameter) 133.99 463 T
(.) 377.96 463 T
0 (F) 108 441 P
0 (or edge mode triggering, the signal must currently satisfy high le) 114.49 441 P
0 (v) 425.18 441 P
0 (el conditions for rising) 431 441 P
1.03 (edge or lo) 108 427 P
1.03 (w le) 157.75 427 P
1.03 (v) 178.8 427 P
1.03 (el conditions for f) 184.62 427 P
1.03 (alling edge. Additionally) 273.25 427 P
1.03 (, prior to the signal satisfying) 394.19 427 P
0.88 (the appropriate current conditions, it must ha) 108 413 P
0.88 (v) 328.7 413 P
0.88 (e satis\336ed the opposite le) 334.52 413 P
0.88 (v) 458.42 413 P
0.88 (el condition for) 464.24 413 P
-0.13 (another number of successi) 108 399 P
-0.13 (v) 238.27 399 P
-0.13 (e samples. That second number is an implementation parame-) 244.1 399 P
0.62 (ter) 108 385 P
0.62 (. Figure 7 sho) 120 385 P
0.62 (ws an e) 187.56 385 P
0.62 (xample of le) 224.62 385 P
0.62 (v) 285.55 385 P
0.62 (el detection for processor to interrupt sample clock) 291.37 385 P
0.07 (ratio = 2, sample on clock rising edge and number of successi) 108 371 P
0.07 (v) 404.56 371 P
0.07 (e clocks at required le) 410.38 371 P
0.07 (v) 515.67 371 P
0.07 (el =) 521.49 371 P
(2.) 108 357 T
0 F
(Figur) 195.32 110 T
(e 7:) 223.77 110 T
(IRC Le) 245.09 110 T
(v) 283.24 110 T
(el Mode T) 289.12 110 T
(rigger Sample T) 340.23 110 T
(iming) 423.34 110 T
108 81 540 729 C
127.22 120 520.78 331 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
181.22 223 217.22 223 217.22 241 244.22 241 244.22 223 316.22 223 6 L
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
361.22 241 388.22 241 388.22 223 415.22 223 415.22 241 496.22 241 6 L
N
181.22 187 199.22 187 199.22 205 280.22 205 280.22 187 316.22 187 6 L
N
181.22 151 217.22 151 217.22 169 307.22 169 307.22 151 316.22 151 6 L
N
370.22 205 388.22 205 388.22 187 451.22 187 451.22 205 496.22 205 6 L
N
370.22 169 388.22 169 388.22 151 487.22 151 487.22 169 496.22 169 6 L
N
190.22 322 190.22 133 2 L
11 X
V
13 X
N
226.22 313 226.22 124 2 L
N
262.22 322 262.22 133 2 L
N
298.22 322 298.22 133 2 L
N
172.22 313 181.22 313 181.22 295 190.22 295 190.22 313 199.22 313 199.22 295
208.22 295 208.22 313 217.22 313 217.22 295 226.22 295 226.22 313 235.22 313 235.22 295
244.22 295 244.22 313 253.22 313 253.22 295 262.22 295 262.22 313 271.22 313 271.22 295
280.22 295 280.22 313 289.22 313 289.22 295 298.22 295 298.22 313 307.22 313 307.22 295
316.22 295 316.22 313 33 L
0 X
N
226.22 265.72 223.24 265.72 226.22 276.09 229.2 265.72 4 Y
0 Z
N
226.22 265.72 223.24 265.72 226.22 276.09 229.2 265.72 4 Y
V
190.22 277 208.22 277 208.22 259 226.22 259 226.22 265.47 5 L
2 Z
N
262.22 265.72 259.24 265.72 262.22 276.09 265.2 265.72 4 Y
0 Z
N
262.22 265.72 259.24 265.72 262.22 276.09 265.2 265.72 4 Y
V
226.22 277 244.22 277 244.22 259 262.22 259 262.22 265.47 5 L
2 Z
N
298.22 265.72 295.24 265.72 298.22 276.09 301.2 265.72 4 Y
0 Z
N
298.22 265.72 295.24 265.72 298.22 276.09 301.2 265.72 4 Y
V
262.22 277 280.22 277 280.22 259 298.22 259 298.22 265.47 5 L
2 Z
N
298.22 277 316.22 277 316.22 259 3 L
N
190.22 265.72 187.24 265.72 190.22 276.09 193.2 265.72 4 Y
0 Z
N
190.22 265.72 187.24 265.72 190.22 276.09 193.2 265.72 4 Y
V
190.22 265.47 190.22 259 172.22 259 3 L
2 Z
N
361.22 322 361.22 133 2 L
13 X
N
397.22 322 397.22 133 2 L
N
433.22 322 433.22 133 2 L
N
469.22 322 469.22 133 2 L
N
361.22 295 361.22 313 370.22 313 370.22 295 379.22 295 379.22 313 388.22 313
388.22 295 397.22 295 397.22 313 406.22 313 406.22 295 415.22 295 415.22 313 424.22 313
424.22 295 433.22 295 433.22 313 442.22 313 442.22 295 451.22 295 451.22 313 460.22 313
460.22 295 469.22 295 469.22 313 478.22 313 478.22 295 487.22 295 487.22 313 30 L
0 X
N
397.22 266.72 394.24 266.72 397.22 277.09 400.2 266.72 4 Y
0 Z
N
397.22 266.72 394.24 266.72 397.22 277.09 400.2 266.72 4 Y
V
361.22 278 379.22 278 379.22 259 397.22 259 397.22 266.47 5 L
2 Z
N
433.22 265.72 430.24 265.72 433.22 276.09 436.2 265.72 4 Y
0 Z
N
433.22 265.72 430.24 265.72 433.22 276.09 436.2 265.72 4 Y
V
397.22 277 415.22 277 415.22 259 433.22 259 433.22 265.47 5 L
2 Z
N
469.22 265.72 466.24 265.72 469.22 276.09 472.2 265.72 4 Y
0 Z
N
469.22 265.72 466.24 265.72 469.22 276.09 472.2 265.72 4 Y
V
433.22 277 451.22 277 451.22 259 469.22 259 469.22 265.47 5 L
2 Z
N
469.22 276 487.22 276 487.22 259 3 L
N
254.17 237.4 258.67 237.4 258.67 228.4 254.17 228.4 4 L
N
254.62 241 249.22 232.9 254.62 224.8 3 L
2 H
N
290.74 202.26 295.24 202.26 295.24 193.26 290.74 193.26 4 L
0.5 H
N
291.19 205.86 285.79 197.76 291.19 189.66 3 L
2 H
N
425.88 234.26 430.38 234.26 430.38 225.26 425.88 225.26 4 L
0.5 H
N
426.33 237.86 420.93 229.76 426.33 221.66 3 L
2 H
N
463.88 198.4 468.38 198.4 468.38 189.4 463.88 189.4 4 L
0.5 H
N
464.33 202 458.93 193.9 464.33 185.8 3 L
2 H
N
2 10 Q
(Not) 263.22 230 T
(Not) 299.08 194.88 T
(Not) 434.08 227.33 T
(Not) 472.23 192.03 T
(Accept) 263.93 155.71 T
(Accept) 443.06 160.03 T
(System) 145.22 304 T
(Internal) 145.22 264 T
(IRQx) 145.22 224 T
(IRQx) 145.22 194 T
(IRQx) 145.22 154 T
479.43 166.26 474.93 166.26 474.93 157.26 479.43 157.26 4 L
0.5 H
N
478.98 169.86 484.38 161.76 478.98 153.66 3 L
2 H
N
299.43 161.26 294.93 161.26 294.93 152.26 299.43 152.26 4 L
0.5 H
N
298.98 164.86 304.38 156.76 298.98 148.66 3 L
2 H
N
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "39" 45
%%Page: "40" 46
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(40) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0.99 (Figure 8 sho) 72 721 P
0.99 (ws an e) 133.68 721 P
0.99 (xample of edge detection with the same implementation parameters) 171.47 721 P
(plus number of prior opposite le) 72 707 T
(v) 226.02 707 T
(el samples = 1.) 231.84 707 T
0 F
(Figur) 172.66 445.75 T
(e 8:) 201.11 445.75 T
(Edge Mode T) 222.44 445.75 T
(rigger Sample T) 290.89 445.75 T
(iming) 374 445.75 T
(5.4.4 Extension f) 72 401.75 T
(or Additional Interrupt Sour) 162.37 401.75 T
(ces) 310.5 401.75 T
2 F
1.42 (SP) 72 379.75 P
1.42 (ARC-V8 pro) 84.24 379.75 P
1.42 (vides for 15 interrupt request le) 147.81 379.75 P
1.42 (v) 305.6 379.75 P
1.42 (els. If there are more than 15 interrupt) 311.42 379.75 P
0 (sources, then a multi-stage interrupt processor must be constructed, with inputs of compa-) 72 365.75 P
0.59 (rable priority being latched and grouped together into a single IRQ line of the Inte) 72 351.75 P
0.59 (grated) 474.01 351.75 P
0.72 (Interrupt Request Controller) 72 337.75 P
0.72 (. After interrupt servicing be) 208.76 337.75 P
0.72 (gins, the program must read the) 348.42 337.75 P
0.73 (re) 72 323.75 P
0.73 (gister of the grouped inputs and determine which one within the group has the highest) 81.14 323.75 P
-0.09 (priority) 72 309.75 P
-0.09 (. W) 107.22 309.75 P
-0.09 (ith appropriate con) 123.98 309.75 P
-0.09 (v) 213.97 309.75 P
-0.09 (entions of bit position mapping, this can be done ef) 219.79 309.75 P
-0.09 (\336ciently) 464.66 309.75 P
(using the SCAN instruction.) 72 295.75 T
0 F
(5.4.4.1 Use of Input Handlers) 72 251.75 T
2 F
-0.02 (Signals at a second or higher stage, that are grouped into a single \336rst stage IRQ line, may) 72 229.75 P
-0.28 (be conditioned through Input Handlers as described in 5.2.1 and the grouping may be done) 72 215.75 P
0.89 (through the) 72 201.75 P
0 F
0.89 (OR) 131.77 201.75 P
2 F
0.89 (ing as described in Section 5.3.3. When resolution of speci\336c indi) 149.77 201.75 P
0.89 (vidual) 474 201.75 P
1.93 (inputs to be serviced is required, the grouped Input Handler Outputs can be read and) 72 187.75 P
(scanned.) 72 173.75 T
72 81 504 729 C
86.53 455.75 489.47 681 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
194.53 681 194.53 663 2 L
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
191.83 654.02 194.53 662.12 197.23 654.02 3 L
N
212.53 681 212.53 663 2 L
N
158.37 644.98 158.37 626.98 2 L
N
155.67 618 158.37 626.1 161.07 618 3 L
N
176.37 681 176.37 663 2 L
N
266.53 680.98 266.53 662.98 2 L
N
263.83 654 266.53 662.1 269.23 654 3 L
N
284.53 680.98 284.53 662.98 2 L
N
230.37 680.98 230.37 662.98 2 L
N
227.67 654 230.37 662.1 233.07 654 3 L
N
248.37 680.98 248.37 662.98 2 L
N
338.53 681 338.53 663 2 L
N
335.83 654.02 338.53 662.12 341.23 654.02 3 L
N
356.53 681 356.53 663 2 L
N
302.37 681 302.37 663 2 L
N
299.67 654.02 302.37 662.12 305.07 654.02 3 L
N
320.37 681 320.37 663 2 L
N
410.53 680.98 410.53 662.98 2 L
N
407.83 654 410.53 662.1 413.23 654 3 L
N
428.53 680.98 428.53 662.98 2 L
N
374.37 680.98 374.37 662.98 2 L
N
371.67 654 374.37 662.1 377.07 654 3 L
N
392.37 680.98 392.37 662.98 2 L
N
158.52 681.26 158.52 663.26 2 L
N
155.82 654.29 158.52 662.39 161.22 654.29 3 L
N
194.53 645 194.53 627 2 L
N
230.37 644.98 230.37 626.98 2 L
N
227.67 618 230.37 626.1 233.07 618 3 L
N
266.53 645 266.53 627 2 L
N
302.37 644.98 302.37 626.98 2 L
N
299.67 618 302.37 626.1 305.07 618 3 L
N
338.53 645 338.53 627 2 L
N
374.37 644.98 374.37 626.98 2 L
N
371.67 618 374.37 626.1 377.07 618 3 L
N
410.53 645 410.53 627 2 L
N
158.53 600 167.53 600 176.53 609 383.53 609 4 L
N
158.53 582 221.53 582 230.53 591 383.53 591 4 L
N
167.53 600 383.53 600 2 L
13 X
N
221.53 582 383.53 582 2 L
N
158.53 564 383.53 564 2 L
N
158.53 564.14 167.53 564.14 176.53 573.14 185.53 573.14 194.53 564.14 212.53 564.14 221.53 573.14
239.53 573.14 248.53 564.14 284.53 564.14 293.53 573.14 311.53 573.14 320.53 564.14 356.53 564.14 365.53 573.14
383.53 573.14 374.53 573.14 374.53 573.14 18 L
0 X
N
158.53 546 383.53 546 2 L
13 X
N
158.53 555.57 167.53 555.57 176.53 546.57 194.53 546.57 203.53 555.57 383.53 555.57 6 L
0 X
N
167.53 528 410.53 528 2 L
13 X
N
158.53 527.43 167.53 527.43 176.53 536.43 356.53 536.43 365.53 527.43 383.53 527.43 392.53 536.43
392.53 536.43 8 L
0 X
N
167.53 510 410.53 510 2 L
13 X
N
158.53 509.57 167.53 509.57 176.53 518.57 284.53 518.57 293.53 509.57 320.53 509.57 329.53 518.57
392.53 518.57 401.53 509.57 428.53 509.57 10 L
0 X
N
158.53 492 419.53 492 2 L
13 X
N
158.53 492.14 167.53 492.14 176.53 501.14 221.53 501.14 230.53 492.14 257.53 492.14 266.53 501.14
329.53 501.14 338.53 492.14 356.53 492.14 365.53 501.14 401.53 501.14 12 L
0 X
N
158.53 473.29 428.53 473.29 2 L
13 X
N
158.53 473.57 167.53 473.57 176.53 482.57 221.53 482.57 230.53 473.57 239.53 482.57 428.53 482.57 7 L
0 X
N
2 10 Q
(System clock) 95.53 663 T
(Sample clock) 95.53 633 T
(V) 95.53 602 T
(alid) 101.64 602 T
(V) 95.53 584 T
(alid) 101.64 584 T
(V) 95.53 566 T
(alid) 101.64 566 T
(Not V) 95.53 549 T
(alid) 119.14 549 T
(Not V) 95.53 530 T
(alid) 119.14 530 T
(Not V) 95.53 512 T
(alid) 119.14 512 T
(Not V) 95.53 494 T
(alid) 119.14 494 T
(Not V) 95.53 476 T
(alid) 119.14 476 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "40" 46
%%Page: "41" 47
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(41) 528 17 T
0 F
(5.4.4.2 Use of Exter) 108 721 T
(nally Latched and Buffer) 213.13 721 T
(ed Signals) 341.93 721 T
2 F
-0.02 (Signals at a second or higher stage, that are grouped into a single \336rst stage IRQ line, may) 108 699 P
0.73 (be conditioned through a reduced IIRC. This consists of the T) 108 685 P
0.73 (rigger Mode Control, IRQ) 411.83 685 P
-0.03 (Latch and IRQ Mask. The 15 outputs are) 108 671 P
0 F
-0.03 (OR) 307.4 671 P
2 F
-0.03 (ed to a single v) 325.4 671 P
-0.03 (alue which is mask) 397.64 671 P
-0.03 (ed by bit 0) 489.09 671 P
0.98 (of the IRQ Mask and then connected to a single group input. This is a single \336rst stage) 108 657 P
0.07 (IRQ line or input to another stage. When resolution of speci\336c indi) 108 643 P
0.07 (vidual inputs to be ser-) 429.74 643 P
(viced is required, the grouped Input Handler Outputs can be read and scanned.) 108 629 T
FMENDPAGE
%%EndPage: "41" 47
%%Page: "42" 48
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(42) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(5.5 T) 72 721 T
(imers and Counters) 103.79 721 T
(5.5.1 Pr) 72 677 T
(ogrammable Pulse Generators) 117.44 677 T
(5.5.1.1 Ov) 72 633 T
(er) 129.22 633 T
(view) 139.75 633 T
2 F
-0.25 (The follo) 72 611 P
-0.25 (wing e) 115.78 611 P
-0.25 (xtended timer and counter features and functions are speci\336ed for SP) 147.68 611 P
-0.25 (ARC-) 475.33 611 P
0.78 (V8E. This speci\336cation pro) 72 597 P
0.78 (vides, in addition to a generalized counter mechanism, a tw) 206.15 597 P
0.78 (o) 498 597 P
1.58 (stage counter mechanism for setting the step size in which actual time counts are per-) 72 583 P
-0.19 (formed. It also pro) 72 569 P
-0.19 (vides increased \337e) 160.56 569 P
-0.19 (xibility in implementing v) 248.64 569 P
-0.19 (arious types of signals gen-) 373.45 569 P
(erated when a counter o) 72 555 T
(v) 186.44 555 T
(er\337o) 192.26 555 T
(ws.) 213.96 555 T
0.67 (SP) 72 533 P
0.67 (ARC-V8E timers and counters are designed to deli) 84.24 533 P
0.67 (v) 332.9 533 P
0.67 (er a pulse of a certain shape to be) 338.72 533 P
-0.12 (used, for e) 72 519 P
-0.12 (xample, as an interrupt. Hence, a timer/counter is actually a pulse generator that) 121.89 519 P
(produces a pulse after a speci\336ed delay) 72 505 T
(.) 259.16 505 T
1.05 (F) 72 483 P
1.05 (or e) 78.49 483 P
1.05 (xample, a pulse generator is required for slo) 97.68 483 P
1.05 (w I/O \050as in actuator signals and slo) 316 483 P
1.05 (w) 495.33 483 P
-0.25 (serial output ports\051 or to reset an interrupt source, re) 72 469 P
-0.25 (g) 319.56 469 P
-0.25 (ardless of whether it originates on- or) 325.5 469 P
-0.14 (of) 72 455 P
-0.14 (f-chip. This speci\336cation describes a bank of general purpose timer/counter pulse gener-) 81.7 455 P
(ators that may be emplo) 72 441 T
(yed in v) 187.2 441 T
(arying implementation conte) 225.56 441 T
(xts.) 363.37 441 T
0.11 (This speci\336cation does not stipulate what is to be counted, as that is left to speci\336c imple-) 72 419 P
0.67 (mentations of the general mechanism\050s\051. Examples of elements that can be implemented) 72 405 P
(include:) 72 391 T
(\321) 90 369 T
(processor clock pulses) 108 369 T
(\321) 90 347 T
(processor clock pulses di) 108 347 T
(vided by) 228.01 347 T
1 F
(n) 272.68 347 T
2 F
( \050where) 278.68 347 T
1 F
(n) 317.99 347 T
2 F
(=16, for e) 323.99 347 T
(xample\051) 370.9 347 T
(\321) 90 325 T
0.46 (input pulses for an on-chip de) 108 325 P
0.46 (vice or an of) 252.97 325 P
0.46 (f-chip de) 314.36 325 P
0.46 (vice \050possibly handled \336rst by) 357.51 325 P
(an input handler as speci\336ed in the section on Input Handlers\051.) 108 311 T
-0.18 (This speci\336cation does not stipulate the destinations for generated counter/timer pulse v) 72 289 P
-0.18 (al-) 491.34 289 P
1.03 (ues as that is left to speci\336c implementations. Examples of generated pulse destinations) 72 275 P
(include:) 72 261 T
(\321) 90 239 T
(interrupt line\050s\051 \050see interrupt speci\336cation\051) 108 239 T
(\321) 90 217 T
(on-chip de) 108 217 T
(vice\050s\051) 158.69 217 T
(\321) 90 195 T
(of) 108 195 T
(f-chip de) 117.7 195 T
(vice\050s\051 \050output via a chip output pin\051) 160.38 195 T
FMENDPAGE
%%EndPage: "42" 48
%%Page: "43" 49
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(43) 528 17 T
0 F
(5.5.1.2 T) 108 721 T
(imer/Counter Mapping) 157.79 721 T
2 F
3.05 (A bank of) 108 699 P
1 F
3.05 (n) 168.13 699 P
2 F
3.05 ( general purpose timer/counter pulse generators is de\336ned. Each timer) 174.13 699 P
3.05 (,) 537 699 P
(counter) 108 685 T
(, and generator consists of three parts:) 143.51 685 T
(\321) 126 641 T
(\050step-\051 pre-SCALER) 144 641 T
(\321) 126 619 T
(\050step-\051 COUNTER) 144 619 T
(\321) 126 597 T
(\050pulse-\051 SHAPER) 144 597 T
0.43 (The timer/counter pulse generators are mapped on an alternate address space \050ASI 1) 108 575 P
2 9.6 Q
0.34 (16) 516.98 572 P
2 12 Q
0.43 ( or) 526.58 575 P
0.97 (81) 108 561 P
2 9.6 Q
0.78 (16) 120 558 P
2 12 Q
0.97 (\051 \050see belo) 129.6 561 P
0.97 (w\051. A bank of 4096 addresses is reserv) 181.23 561 P
0.97 (ed for timer/counters. Each timer/) 373.81 561 P
0.42 (counter occupies 32 bytes within this bank, although not e) 108 547 P
0.42 (v) 390.77 547 P
0.42 (ery byte is used. A maximum) 396.59 547 P
(of 128 timer/counter pulse generators can be mapped.) 108 533 T
0 F
(5.5.1.3 SCALER) 108 489 T
2 F
1 (SCALER is a counter to adjust the v) 108 467 P
1 (alue by which COUNTER is incremented. It is the) 289.7 467 P
0.18 (\336rst stage of a tw) 108 453 P
0.18 (o-stage general counting mechanism. An important e) 191.26 453 P
0.18 (xample of its usage) 446.47 453 P
1.56 (is to compensate for dif) 108 439 P
1.56 (ferences in clock frequenc) 227.27 439 P
1.56 (y among v) 358.05 439 P
1.56 (arious implementations of) 411.55 439 P
-0.14 (SP) 108 425 P
-0.14 (ARC-V8E. The SCALER counts processor clock c) 120.24 425 P
-0.14 (ycles \050or other inputs to the counting) 364.19 425 P
(circuitry) 108 411 T
(, such as clock c) 147.88 411 T
(ycle/16\051.) 226.01 411 T
0.95 (F) 108 389 P
0.95 (or e) 114.49 389 P
0.95 (xample, for COUNTER to count in milliseconds in an application where the clock) 133.59 389 P
0.71 (frequenc) 108 375 P
0.71 (y is 100 MHz, SCALER w) 149.8 375 P
0.71 (ould be set to 100,000 \050or to 100,000/16 when clock) 282.59 375 P
-0.03 (c) 108 361 P
-0.03 (ycle/16 is used as input to the counting circuitry\051. Frequently) 113.15 361 P
-0.03 (, all SCALERs will hold the) 404.78 361 P
1.03 (same v) 108 347 P
1.03 (alue \050e.g. corresponding to 1 msec\051 which can be written at system start-up time) 142.39 347 P
0.81 (and ne) 108 333 P
0.81 (v) 140.17 333 P
0.81 (er changed. Softw) 145.99 333 P
0.81 (are e) 234.47 333 P
0.81 (x) 258.08 333 P
0.81 (ecuting after SCALER is set could then be written to be) 263.9 333 P
(portable across SP) 108 319 T
(ARC-V8E implementations.) 195.55 319 T
0.5 (SCALER can be controlled by tw) 108 297 P
0.5 (o \322e) 272.05 297 P
0.5 (xternal\323 signals, each pro) 292.03 297 P
0.5 (vided by an input handler) 415.33 297 P
(\050see section on Input Handlers\051.) 108 283 T
0.88 (SCALER consists of) 108 261 P
1 F
0.88 (s) 213.66 261 P
2 F
0.88 (-bit re) 218.33 261 P
0.88 (gisters, SCALER.set and SCALER.cnt.) 248.02 261 P
1 F
0.88 (s) 444.23 261 P
2 F
0.88 (is implementation) 452.78 261 P
(dependent b) 108 247 T
(ut within the range of 8 to 32, inclusi) 166.08 247 T
(v) 343.44 247 T
(e.) 349.26 247 T
0.92 (SCALER.cnt decrements at e) 108 225 P
0.92 (v) 251.78 225 P
0.92 (ery count pulse \050in a particular reference implementation,) 257.6 225 P
0.14 (the actual count pulse is an e) 108 211 P
0.14 (xternal pulse handled by an input handler; refer to section on) 246.64 211 P
(Input Handler\051.) 108 197 T
1.07 (SCALER has an Enable input signal whose particular reference implementation is typi-) 108 175 P
0.49 (cally pro) 108 161 P
0.49 (vided by an input handler) 150.63 161 P
0.49 (. Counting is enabled when the Enable signal=1. If the) 274.56 161 P
(Enable signal is dri) 108 147 T
(v) 200.03 147 T
(en by the output of a signal handler:) 205.85 147 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(44) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
(\245) 144 721 T
0.81 (counting can be controlled by an e) 162.36 721 P
0.81 (xternal signal after handling by the) 332.32 721 P
(INV) 162.58 707 T
(, WIDTH, B) 182.35 707 T
(UF and EN construct \050see Input Handler\051) 242.22 707 T
(\245) 144 685 T
(counting can also be controlled by softw) 162.36 685 T
(are:) 356.88 685 T
(-count when B) 144 663 T
(UF=1 and EN=1) 214.54 663 T
(-stop when B) 144 641 T
(UF=0 or EN=0) 207.88 641 T
(When SCALER.cnt reaches zero \050as controlled by SHAPER\051 it either:) 72 619 T
(\245) 144 597 T
(stops counting or) 162.36 597 T
(\245) 144 575 T
(copies SCALER.set and continues decrementing) 162.36 575 T
-0.24 (Which action is tak) 72 553 P
-0.24 (en depends on the associated SHAPER v) 164.15 553 P
-0.24 (alue. When SCALER.cnt con-) 359.07 553 P
0.12 (tinues after reaching zero, it sends one count pulse to COUNT) 72 539 P
0.12 (. The counter mechanism is) 371.22 539 P
0.84 (started by writing a 1 into the SCALER cop) 72 525 P
0.84 (y bit \050see Shaper belo) 289.27 525 P
0.84 (w\051. SCALER.cnt then) 396.32 525 P
(copies SCALER.set and starts counting) 72 511 T
0 F
(5.5.1.4 COUNTER) 72 467 T
2 F
2.64 (COUNTER is a counter to actually count in steps as set by the v) 72 445 P
2.64 (alue in SCALER.) 414.38 445 P
(COUNTER is decremented when SCALER.cnt reaches zero.) 72 431 T
(COUNTER consists of:) 72 409 T
(\321) 90 387 T
(T) 108 387 T
(w) 114.37 387 T
(o) 122.92 387 T
1 F
(c) 131.92 387 T
2 F
(-bit re) 137.24 387 T
(gisters, COUNTER.set and COUNTER.cnt.) 166.06 387 T
1 F
(c) 108 365 T
2 F
(is implementation dependent and may v) 116.33 365 T
(ary from 8 to 32 bits.) 307.68 365 T
(COUNTER operates as follo) 72 343 T
(ws:) 210.01 343 T
(\321) 90 321 T
0.19 (COUNTER.cnt and COUNTER.set are written simultaneously with the same start) 108 321 P
(v) 108 307 T
(alue) 113.7 307 T
(\321) 90 285 T
(COUNTER.cnt can be read; Readability of COUNTER.set is not required) 108 285 T
(\321) 90 263 T
(COUNTER.cnt is decremented by 1 when SCALER.cnt reaches zero) 108 263 T
(\321) 90 241 T
0.94 (When COUNTER.cnt reaches zero \050as controlled by SHAPER, see section 5.4.5) 108 241 P
(belo) 108 227 T
(w\051:) 128.36 227 T
(\245) 144 205 T
(Counting stops, or) 162.36 205 T
(\245) 144 183 T
0.77 (The v) 162.36 183 P
0.77 (alue in COUNTER.set is copied into COUNTER.cnt and count-) 190.49 183 P
(ing continues.) 162.58 169 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(45) 528 17 T
0 F
(5.5.1.5 SHAPER) 108 721 T
2 F
1.07 (When the Counter) 108 699 P
1.07 (.cnt reaches zero, the pulse generated may tak) 197.46 699 P
1.07 (e one of v) 425.06 699 P
1.07 (arious forms,) 475.61 699 P
(including:) 108 685 T
(\321) 126 663 T
(a Positi) 144 663 T
(v) 179.38 663 T
(e Step) 185.2 663 T
(\321) 126 641 T
(a Ne) 144 641 T
(g) 166.14 641 T
(ati) 172.08 641 T
(v) 183.78 641 T
(e Pulse) 189.6 641 T
(\321) 126 619 T
(Pulse after delay) 144 619 T
(\321) 126 597 T
(Pulse of speci\336ed width) 144 597 T
(\321) 126 575 T
(Series of pulses as depicted in the follo) 144 575 T
(wing \336gure) 331.34 575 T
(:) 144 553 T
0 F
(Figur) 229.11 430.33 T
(e 9:) 257.56 430.33 T
(SHAPER Pulse Generation) 278.89 430.33 T
2 F
1.72 (The SHAPER controls a generalized pulse generation f) 108 404.33 P
1.72 (acility) 384.89 404.33 P
1.72 (. The SHAPER is imple-) 414.11 404.33 P
0.33 (mented as an 8-bit re) 108 390.33 P
0.33 (gister) 209.8 390.33 P
0.33 (. The SHAPER re) 235.8 390.33 P
0.33 (gister v) 322.62 390.33 P
0.33 (alues are mapped on 8 bits as follo) 358.32 390.33 P
0.33 (ws) 526.67 390.33 P
(\050bit 0 is the least signi\336cant bit\051) 108 376.33 T
(Note:) 108 354.33 T
(Bits 6:4 of the SHAPER control the v) 144 354.33 T
(alues of the output signal;) 324.71 354.33 T
(Bits 3:0 of the SHAPER control counters stopping, starting and continuing.) 144 340.33 T
(This is e) 108 296.33 T
(xplained in the table belo) 148.49 296.33 T
(w:) 269.51 296.33 T
108 81 540 729 C
112.17 440.33 535.83 549 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
181.92 499.71 210.72 499.71 210.72 514.11 248.32 514.11 247.92 499.71 462.71 499.71 6 L
1 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
181.92 471.11 210.72 471.11 210.72 456.71 246.72 456.71 246.72 471.11 423.11 471.11 423.11 456.71
451.91 456.71 451.91 471.11 462.71 471.11 10 L
N
10 8 Q
(shaper=010xx00) 185.25 491.54 T
(shaper=101xx11) 185.25 448.38 T
(EXAMPLE:) 122.83 538.59 T
(Positive) 138.33 496.17 T
(pulse:) 138.33 488.17 T
(Negative) 138.33 472.17 T
(pulse series:) 138.33 464.17 T
(6) 188.67 530 T
(5) 223.33 530 T
(4) 262.67 530 T
(Shaper Bit:) 136.67 531 T
190.67 509.36 192.8 509.36 190.67 505.67 188.53 509.36 4 Y
0 Z
N
190.67 509.36 192.8 509.36 190.67 505.67 188.53 509.36 4 Y
V
190.67 524.67 190.67 509.86 2 L
2 Z
N
264 506.03 266.13 506.03 264 502.33 261.87 506.03 4 Y
0 Z
N
264 506.03 266.13 506.03 264 502.33 261.87 506.03 4 Y
V
264 524.67 264 506.53 2 L
2 Z
N
226 518.03 228.13 518.03 226 514.33 223.87 518.03 4 Y
0 Z
N
226 518.03 228.13 518.03 226 514.33 223.87 518.03 4 Y
V
226 524.67 226 518.53 2 L
2 Z
N
2 F
(\050see table belo) 274 527.33 T
(w\051) 320.01 527.33 T
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "45" 51
%%Page: "46" 52
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(46) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
(:) 72 721 T
0 F
(5.5.1.6 ASI Mapping f) 72 377 T
(or Counters and T) 190.38 377 T
(imers) 285.17 377 T
2 F
0.26 (When mapping counters and timers on an alternate address space, it is recommended that) 72 355 P
-0.09 (ASI 1) 72 341 P
2 9.6 Q
-0.08 (16) 100.24 338 P
2 12 Q
-0.09 ( or 81) 109.84 341 P
2 9.6 Q
-0.08 (16) 137.65 338 P
2 12 Q
-0.09 ( be used. Addresses aligned on 4k byte blocks are a) 147.24 341 P
-0.09 (v) 393.01 341 P
-0.09 (ailable, pro) 398.71 341 P
-0.09 (viding 128) 452.42 341 P
(counter/timer/pulsers:) 72 327 T
(\321) 90 305 T
(COUNTER.set[) 108 305 T
1 F
(n) 184.99 305 T
2 F
(] is the w) 190.99 305 T
(ord at address:) 235.2 305 T
( 32) 305.18 305 T
1 F
(n) 320.18 305 T
2 F
( to 32) 326.18 305 T
1 F
(n) 353.52 305 T
2 F
(+3) 359.52 305 T
(\321) 90 283 T
(COUNTER.cnt[) 108 283 T
1 F
(n) 186.32 283 T
2 F
(] is the w) 192.32 283 T
(ord at address:) 236.53 283 T
( 32) 306.52 283 T
1 F
(n) 321.52 283 T
2 F
(+4 to 32) 327.52 283 T
1 F
(n) 367.62 283 T
2 F
(+7) 373.62 283 T
(\321) 90 261 T
(SCALER.set[) 108 261 T
1 F
(n) 174.34 261 T
2 F
(] is the w) 180.34 261 T
(ord at address:) 224.54 261 T
( 32) 294.53 261 T
1 F
(n) 309.53 261 T
2 F
(+8 to 32) 315.53 261 T
1 F
(n) 355.63 261 T
2 F
(+11) 361.63 261 T
(\321) 90 239 T
(SCALER.cnt[) 108 239 T
1 F
(n) 175.67 239 T
2 F
(] is the w) 181.67 239 T
(ord at address:) 225.88 239 T
( 32) 295.86 239 T
1 F
(n) 310.86 239 T
2 F
(+12 to 32) 316.86 239 T
1 F
(n) 362.96 239 T
2 F
(+15) 368.96 239 T
(\321) 90 217 T
(SHAPER[) 108 217 T
1 F
(n) 158 217 T
2 F
(] is the w) 164 217 T
(ord at address:) 208.21 217 T
( 32) 278.2 217 T
1 F
(n) 293.2 217 T
2 F
(+16) 299.2 217 T
2 10 Q
(Note:) 72 192.33 T
-0.09 (Elements containing less than 32 bits are mapped on the least signi\336cant bits \050LSB\051 of these w) 108 180.33 P
-0.09 (ords.) 484.28 180.33 P
(The remaining higher order bits in the w) 108 168.33 T
(ord are unused.) 269.82 168.33 T
0 F
(Bit) 101.61 692.33 T
(Description) 299.28 692.33 T
2 12 Q
(31:7) 78 671 T
2 10 Q
(Unde\336ned \050may be used for e) 150 672.33 T
(xtensions\051) 268.43 672.33 T
2 12 Q
(6) 78 649 T
2 10 Q
1.24 (Start v) 150 650.33 P
1.24 (alue of the output signal: The v) 177.38 650.33 P
1.24 (alue of the output signal when COUNTER is) 309.58 650.33 P
(started by writing a 1 to the start bit-2) 150 638.33 T
2 12 Q
(5) 78 617 T
2 10 Q
(V) 150 618.33 T
(alue of the output signal when COUNTER reaches zero for the \336rst time after restart) 156.11 618.33 T
2 12 Q
(4) 78 595 T
2 10 Q
3.08 (V) 150 596.33 P
3.08 (alue of the output signal when SCALER reaches zero for the \336rst time after) 156.11 596.33 P
(COUNTER reached 0) 150 584.33 T
2 12 Q
(3) 78 563 T
2 10 Q
(Reserv) 150 564.33 T
(ed) 177.62 564.33 T
2 12 Q
(2) 78 541 T
2 10 Q
4.12 (When v) 150 542.33 P
4.12 (alue is written to 1, starts the counter by cop) 185.25 542.33 P
4.12 (ying SCALER.set into) 399.46 542.33 P
1.19 (SCALER.cnt and COUNTER.set into COUNTER.cnt and outputting a signal- bit 6.) 150 530.33 P
-0.17 (This is used to start a prepared counter at a precise instant. The de) 150 518.33 P
-0.17 (gree of precision is as) 411.48 518.33 P
(precise as the input \050which e.g. may be clock/16\051) 150 506.33 T
2 12 Q
(1) 78 485 T
2 10 Q
(Bit 1=0: when COUNTER reaches 0, stop COUNTER.) 150 486.33 T
(Bit 1=1: when COUNTER reaches 0, cop) 150 474.33 T
(y COUNTER.set and restart counting.) 316.35 474.33 T
2 12 Q
(0) 78 453 T
2 10 Q
(Bit 0=0: when SCALER and COUNTER reach 0, stop SCALER.) 150 454.33 T
(Bit 0=1: when SCALER and COUNTER reach 0, cop) 150 442.33 T
(y SCALER.set; restart counting.) 365.8 442.33 T
0 12 Q
(T) 199.88 421 T
(able 6:) 206.78 421 T
(Shaper Register Mapping) 244.12 421 T
72 704.75 72 435.25 2 L
V
0.5 H
0 Z
N
144 705.25 144 434.75 2 L
V
N
504 704.75 504 435.25 2 L
V
N
71.75 705 504.25 705 2 L
V
N
72.25 686.25 503.75 686.25 2 L
V
N
72.25 683.75 503.75 683.75 2 L
V
N
71.75 663 504.25 663 2 L
V
N
71.75 577 504.25 577 2 L
V
N
71.75 435 504.25 435 2 L
V
N
FMENDPAGE
%%EndPage: "46" 52
%%Page: "47" 53
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(47) 528 17 T
0 F
(5.5.1.7 Examples) 108 721 T
12 F
(A continuous timer with a large capacity can be mapped.) 108 699 T
2 F
(In this e) 108 677 T
(xample:) 146.48 677 T
(\321) 126 655 T
(set SCALER to FFFF FFFF) 144 655 T
2 9.6 Q
(16) 278.05 652 T
2 12 Q
(\321) 126 633 T
(set COUNTER to FFFF FFFF) 144 633 T
2 9.6 Q
(16) 288.71 630 T
2 12 Q
(\321) 126 611 T
(set SHAPER to) 144 611 T
1 F
(x) 221.68 611 T
2 F
(01) 227 611 T
1 F
(x) 239 611 T
(x) 247.33 611 T
2 F
(1) 252.66 611 T
1 F
(xx) 258.66 611 T
2 F
(2 \050) 269.32 611 T
1 F
(x) 282.31 611 T
2 F
(= don\325) 287.64 611 T
(t care\051) 319.19 611 T
(\321) 126 589 T
(when:) 144 589 T
(\245) 180 567 T
(SCALER is 16 bits \050FFFF\051 and) 198.36 567 T
(\245) 180 545 T
(COUNTER is 24 bits \050FF FFFF\051 and) 198.36 545 T
(\245) 180 523 T
(input is clock/16 then) 198.36 523 T
-0.11 (COUNTER concatenated with SCALER will sho) 108 501 P
-0.11 (w FF FFFF FFFF) 344.13 501 P
2 9.6 Q
-0.09 (16) 428.18 498 P
2 12 Q
-0.11 ( minus the number of) 437.78 501 P
(input pulses since it w) 108 487 T
(as set.) 214.55 487 T
0.79 (COUNTER, concatenated with SCALER, has, at 100 MHz processor clock frequenc) 108 465 P
0.79 (y) 522.66 465 P
0.79 (, a) 527.88 465 P
(\322capacity\323 of 16 x 2) 108 451 T
2 9.6 Q
(16) 204.64 455.8 T
2 12 Q
( x 2) 214.24 451 T
2 9.6 Q
(24) 232.24 455.8 T
2 12 Q
(/ 100M = 176k sec = 49 hr = just o) 241.84 451 T
(v) 408.62 451 T
(er 2 days.) 414.44 451 T
12 F
(An interval or w) 108 407 T
(atc) 188.23 407 T
(hdog timer with an interval of X msec.) 202.78 407 T
2 F
(This can be implemented in man) 108 385 T
(y w) 264.8 385 T
(ays. One e) 282.35 385 T
(xample follo) 332.48 385 T
(ws:) 393.18 385 T
(\321) 126 363 T
0.96 (set SCALER to 100 microsec. \050e) 144 363 P
0.96 (xpressed in input pulses\051 at system start-up. Do) 305.95 363 P
(not change after start-up) 144 349 T
(\321) 126 327 T
(set COUNTER to 10 x) 144 327 T
1 F
(X) 256.33 327 T
2 F
(\321) 126 305 T
1.16 (set SHAPER to) 144 305 P
1 F
1.16 (x) 225.15 305 P
2 F
1.16 (010) 230.48 305 P
1 F
1.16 (x) 252.63 305 P
2 F
1.16 (111 \050repeated \3221\323 pulses, 100 microseconds wide\051 which) 257.96 305 P
(indicates:) 144 291 T
(\245) 180 269 T
(pulse start v) 198.36 269 T
(alue = 0 \050see bit 6\051;) 256.06 269 T
(\245) 180 247 T
0.72 (when COUNTER reaches zero, Output pulse v) 198.36 247 P
0.72 (alue = 1 and remains 1) 427.33 247 P
(until SCALER reaches zero \050as indicated by bit 5\051:) 198.58 233 T
(\245) 180 211 T
2.23 (when SCALER reaches zero, output v) 198.36 211 P
2.23 (alue = 0 and remains 0 until) 392.52 211 P
(changed \050as indicated by bit 4 being 0\051:) 198.58 197 T
(\245) 180 175 T
-0.21 (repeat by restarting COUNTER and SCALER when the) 198.36 175 P
-0.21 (y reach zero \050as) 465.01 175 P
(indicated by bits 1 and 0 being \324112\325) 198.58 161 T
FMENDPAGE
%%EndPage: "47" 53
%%Page: "48" 54
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(48) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
12 F
(T) 72 721 T
(ime can be measured in milliseconds:) 78.89 721 T
2 F
(\321) 90 699 T
0.32 (set SCALER to 1 msec \050e) 108 699 P
0.32 (xpressed in input pulses\051. Do this at system start-up and) 233.1 699 P
(do not change) 108 685 T
(\321) 90 663 T
(set COUNTER to FFFF FFFF FFFF) 108 663 T
2 9.6 Q
(16) 282.4 660 T
2 12 Q
(\321) 90 641 T
(set SHAPER to) 108 641 T
1 F
( xxxx) 182.68 641 T
(x) 209.99 641 T
2 F
(1) 215.32 641 T
1 F
(xx) 221.32 641 T
2 F
( to start it) 231.97 641 T
(\321) 90 619 T
(start the e) 108 619 T
(v) 154.36 619 T
(ent timer via the Enable input mechanism) 160.18 619 T
0.66 (Input handlers may be used to construct counters for counting an) 72 597 P
0.66 (y input. A counter con-) 389.71 597 P
0.65 (structed from a general input handler will count the applied input pulses. Such a counter) 72 583 P
(may also be started and stopped by applying the input handler\325) 72 569 T
(s EN bit.) 372.64 569 T
0 F
(5.5.2 Simple Counters) 72 525 T
2 F
-0.14 (Simple counters ranging from 8 to 32 bits may be implemented to support routine capabil-) 72 503 P
(ities. The number of bits and the number of counters is an implementation parameter) 72 489 T
(.) 477.95 489 T
0.54 (The counters are dri) 72 467 P
0.54 (v) 169.61 467 P
0.54 (en by the processor clock and are mapped into memory at ASI 1 or) 175.43 467 P
0.65 (C1) 72 453 P
2 9.6 Q
0.52 (16) 86 450 P
2 12 Q
0.65 (. Each counter occupies a whole w) 95.6 453 P
0.65 (ord address. Associated with each counter) 265.66 453 P
0.65 (, at the) 470.37 453 P
-0.15 (ne) 72 439 P
-0.15 (xt w) 83.15 439 P
-0.15 (ord address in the same ASI, is its preload re) 103.88 439 P
-0.15 (gister) 316.98 439 P
-0.15 (. The counter and preload re) 342.98 439 P
-0.15 (gister) 477.34 439 P
(must be writable. Readability is an implementation parameter) 72 425 T
(.) 367.31 425 T
(When enabled, the counter does one of the follo) 72 403 T
(wing:) 301.98 403 T
(\321) 90 381 T
(increments and generates an o) 108 381 T
(v) 252.44 381 T
(er\337o) 258.26 381 T
(w signal when it passes maximum v) 279.96 381 T
(alue) 452.99 381 T
(\321) 90 359 T
(decrements and generates an equal_zero signal when it reaches zero) 108 359 T
(\321) 90 337 T
(decrements and generates an under\337o) 108 337 T
(w signal when it passes zero) 288.31 337 T
1.14 (The direction of counting and the form of strobe signal are implementation parameters.) 72 315 P
0.73 (The strobe signal causes the contents of the associated preload re) 72 301 P
0.73 (gister to be loaded into) 391.08 301 P
(the counter and the counter continues counting.) 72 287 T
0.85 (If the strobe signal is deli) 72 265 P
0.85 (v) 197.63 265 P
0.85 (ered to an output pin, then it may be used to control periodic) 203.45 265 P
0.01 (e) 72 251 P
0.01 (v) 77.03 251 P
0.01 (ents in the e) 82.85 251 P
0.01 (xternal system such as DRAM refresh. If the strobe signal is deli) 140.37 251 P
0.01 (v) 450.84 251 P
0.01 (ered to an) 456.66 251 P
0.26 (interrupt request line, then it may be used to periodically acti) 72 237 P
0.26 (v) 366.62 237 P
0.26 (ate service routines such as) 372.32 237 P
0.34 (polling e) 72 223 P
0.34 (xternal requests for service that do not acti) 114.49 223 P
0.34 (v) 320.84 223 P
0.34 (ate v) 326.54 223 P
0.34 (ectored priority interrupts. Each) 349.69 223 P
0.03 (counter is enabled by an associated bit in a system control re) 72 209 P
0.03 (gister \336eld when the bit is set) 363.14 209 P
0.25 (to one. The counter is disabled by the associated bit being set to zero. The system control) 72 195 P
-0.2 (re) 72 181 P
-0.2 (gister is mapped into memory at ASI 1 or 0xC1. The address of the system control re) 81.14 181 P
-0.2 (gis-) 486 181 P
(ter and the mapping of counters to enable bits are implementation parameters.) 72 167 T
FMENDPAGE
%%EndPage: "48" 54
%%Page: "49" 55
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(49) 528 17 T
0 F
(5.5.3 Simple T) 108 721 T
(imers) 187.13 721 T
2 F
0.17 (T) 108 699 P
0.17 (imers ranging from 8 to 32 bits may be implemented to support more demanding timing) 114.91 699 P
(tasks. The number of bits and the number of timers are implementation parameters.) 108 685 T
0.45 (Clocking of the timers and associated prescalers or reload re) 108 663 P
0.45 (gisters is done with either or) 401.44 663 P
-0.03 (both a timer clock or an asynchronous e) 108 649 P
-0.03 (xternal signal. Which one or both is an implemen-) 299.25 649 P
(tation parameter) 108 635 T
(.) 185.65 635 T
-0.21 (The timer clock is synchronized with the processor clock and may ha) 108 613 P
-0.21 (v) 437.71 613 P
-0.21 (e the same period or) 443.53 613 P
1.07 (may be di) 108 599 P
1.07 (vided do) 157.17 599 P
1.07 (wn. The ratio of processor clock to timer clock is an implementation) 199.6 599 P
0.9 (parameter) 108 585 P
0.9 (. If di) 155.32 585 P
0.9 (vided do) 183.14 585 P
0.9 (wn, transitions of the timer clock may be synchronized with the) 225.4 585 P
(rising or f) 108 571 T
(alling edge of the processor clock. This is also an implementation parameter) 155.21 571 T
(.) 520.49 571 T
0.82 (Asynchronous e) 108 549 P
0.82 (xternal signals are g) 186.29 549 P
0.82 (ated by the timer clock for internal synchronization.) 284.99 549 P
-0.05 (Therefore, the minimum duration of the asynchronous signal for its zero condition and for) 108 535 P
0.64 (its one condition is some multiple of the timer clock period, which is an implementation) 108 521 P
(parameter) 108 507 T
(.) 155.32 507 T
2.04 (Each timer can be independently programmed to operate in one of the follo) 108 485 P
2.04 (wing \336v) 493.44 485 P
2.04 (e) 534.97 485 P
(modes:) 108 471 T
(\321) 126 449 T
(Mode 0: Periodic Interrupt Mode) 144 449 T
(\321) 126 427 T
(Mode 1: T) 144 427 T
(imeout Interrupt Mode) 194.24 427 T
(\321) 126 405 T
(Mode 2: Square W) 144 405 T
(a) 234.02 405 T
(v) 239.11 405 T
(e Generator Mode) 244.93 405 T
(\321) 126 383 T
(Mode 3: Softw) 144 383 T
(are T) 215.88 383 T
(rigger W) 240.44 383 T
(atchdog Mode) 282.47 383 T
(\321) 126 361 T
(Mode 4: External T) 144 361 T
(rigger W) 237.9 361 T
(atchdog mode) 279.92 361 T
-0.13 (Figure 10 belo) 108 339 P
-0.13 (w sho) 177.44 339 P
-0.13 (ws a block diagram of timers, prescalers and clock options. Prescalars) 205.35 339 P
0.65 (and timer counters may be dri) 108 325 P
0.65 (v) 254.58 325 P
0.65 (en by the timer clock or an asynchronous e) 260.4 325 P
0.65 (xternal signal.) 471.36 325 P
-0.22 (Those timer units that ha) 108 311 P
-0.22 (v) 226.23 311 P
-0.22 (e prescalers may also dri) 232.05 311 P
-0.22 (v) 349.52 311 P
-0.22 (e their timer counter with the prescaler) 355.34 311 P
(output.) 108 297 T
FMENDPAGE
%%EndPage: "49" 55
%%Page: "50" 56
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(50) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0 F
(Figur) 178.51 464 T
(e 10:) 206.96 464 T
(T) 234.29 464 T
(imer Pr) 242.08 464 T
(escaler Block Diagram) 281.51 464 T
2 F
0.77 (Each timer unit has three or four internal re) 72 426 P
0.77 (gisters that allo) 285.93 426 P
0.77 (w the program to control and) 360.5 426 P
0.51 (monitor its operation. These re) 72 412 P
0.51 (gisters are mapped into ASI 1 or 0xC1 at successi) 221.52 412 P
0.51 (v) 464.8 412 P
0.51 (e w) 470.62 412 P
0.51 (ord) 488 412 P
1.02 (addresses as sho) 72 398 P
1.02 (wn in T) 152.4 398 P
1.02 (able 7. Each starting address, TUC-REGn, is aligned on a quad) 190.81 398 P
(w) 72 384 T
(ord boundary \050address modulo 16=0\051.) 80.54 384 T
2.64 (Determination of timers ha) 72 220 P
2.64 (ving prescalers is an implementation parameter) 209.32 220 P
2.64 (. Lik) 448.79 220 P
2.64 (e) 473.98 220 P
2.64 (wise,) 479 220 P
(which count v) 72 206 T
(alues can be written is an implementation parameter) 139.69 206 T
(.) 389.32 206 T
0 10 Q
(Addr) 110.24 355.33 T
(ess) 132.84 355.33 T
(Register) 230.47 355.33 T
(Requir) 330.06 355.33 T
(ed Access) 359.88 355.33 T
(Reset State) 434.35 355.33 T
2 F
(TUC-REGn + 0) 80.71 335.33 T
(Prescale control/reserv) 186.6 335.33 T
(ed) 277.81 335.33 T
(Read/Write) 321.88 335.33 T
2 12 Q
(1) 420.88 334 T
2 10 Q
(TUC-REGn + 4) 80.71 313.33 T
(T) 186.6 313.33 T
(imer control) 192.36 313.33 T
(Read/Write) 321.88 313.33 T
2 12 Q
(0) 420.88 312 T
2 10 Q
(TUC-REGn + 8) 80.71 291.33 T
(Reload v) 186.6 291.33 T
(alue) 222.18 291.33 T
(Read/Write) 321.88 291.33 T
2 12 Q
(0) 420.88 290 T
2 10 Q
(TUC-REGn + C) 80.71 269.33 T
(Count v) 186.6 269.33 T
(alue) 218.3 269.33 T
(Read) 321.88 269.33 T
2 12 Q
(0) 420.88 268 T
0 F
(T) 155.96 246 T
(able 7:) 162.86 246 T
(T) 200.19 246 T
(imer Unit Contr) 207.98 246 T
(ol Register Memory Map) 291.08 246 T
74.71 367.75 74.71 260.25 2 L
V
0.5 H
0 Z
N
180.6 368.25 180.6 259.75 2 L
V
N
315.88 368.25 315.88 259.75 2 L
V
N
414.88 368.25 414.88 259.75 2 L
V
N
501.29 367.75 501.29 260.25 2 L
V
N
74.46 368 501.54 368 2 L
V
N
74.96 349.25 501.04 349.25 2 L
V
N
74.96 346.75 501.04 346.75 2 L
V
N
74.46 260 501.54 260 2 L
V
N
72 81 504 729 C
72 474 504 717 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
318.38 681 345.38 672 345.38 654 318.38 645 4 Y
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
361.09 663 361.09 665.98 371.47 663 361.09 660.02 4 Y
0 Z
N
361.09 663 361.09 665.98 371.47 663 361.09 660.02 4 Y
V
345.38 663 360.84 663 2 L
2 Z
N
372.38 654 435.38 672 R
N
442.09 663 442.09 665.98 452.47 663 442.09 660.02 4 Y
0 Z
N
442.09 663 442.09 665.98 452.47 663 442.09 660.02 4 Y
V
435.38 663 441.84 663 2 L
2 Z
N
453.38 654 498.38 672 R
N
311.12 672 311.12 673.82 317.47 672 311.12 670.18 4 Y
0 Z
N
311.12 672 311.12 673.82 317.47 672 311.12 670.18 4 Y
V
309.38 699 309.38 672 310.88 672 3 L
2 Z
N
311.12 654 311.12 655.82 317.47 654 311.12 652.18 4 Y
0 Z
N
311.12 654 311.12 655.82 317.47 654 311.12 652.18 4 Y
V
310.88 654 309.38 654 309.38 501 3 L
2 Z
N
2 12 Q
(MUX) 319.38 659 T
(Synchronize) 374.37 659 T
(T) 458.36 659 T
(imer) 465.27 659 T
(0) 490.27 659 T
318.38 636 345.38 627 345.38 609 318.38 600 4 Y
N
361.09 618 361.09 620.98 371.47 618 361.09 615.02 4 Y
0 Z
N
361.09 618 361.09 620.98 371.47 618 361.09 615.02 4 Y
V
345.38 618 360.84 618 2 L
2 Z
N
372.38 609 435.38 627 R
N
442.09 618 442.09 620.98 452.47 618 442.09 615.02 4 Y
0 Z
N
442.09 618 442.09 620.98 452.47 618 442.09 615.02 4 Y
V
435.38 618 441.84 618 2 L
2 Z
N
453.38 609 498.38 627 R
N
(MUX) 319.38 614 T
(Synchronize) 374.37 614 T
(T) 458.36 614 T
(imer) 465.27 614 T
(1) 490.27 614 T
318.38 591 345.38 582 345.38 564 318.38 555 4 Y
N
361.09 573 361.09 575.98 371.47 573 361.09 570.02 4 Y
0 Z
N
361.09 573 361.09 575.98 371.47 573 361.09 570.02 4 Y
V
345.38 573 360.84 573 2 L
2 Z
N
372.38 564 435.38 582 R
N
442.09 573 442.09 575.98 452.47 573 442.09 570.02 4 Y
0 Z
N
442.09 573 442.09 575.98 452.47 573 442.09 570.02 4 Y
V
435.38 573 441.84 573 2 L
2 Z
N
453.38 564 498.38 582 R
N
(MUX) 319.38 569 T
(Synchronize) 374.37 569 T
(T) 458.36 569 T
(imer) 465.27 569 T
(2) 490.27 569 T
318.38 546 345.38 537 345.38 519 318.38 510 4 Y
N
361.09 528 361.09 530.98 371.47 528 361.09 525.02 4 Y
0 Z
N
361.09 528 361.09 530.98 371.47 528 361.09 525.02 4 Y
V
345.38 528 360.84 528 2 L
2 Z
N
372.38 519 435.38 537 R
N
442.09 528 442.09 530.98 452.47 528 442.09 525.02 4 Y
0 Z
N
442.09 528 442.09 530.98 452.47 528 442.09 525.02 4 Y
V
435.38 528 441.84 528 2 L
2 Z
N
453.38 519 498.38 537 R
N
(MUX) 319.38 524 T
(Synchronize) 374.37 524 T
(T) 458.36 524 T
(imer) 465.27 524 T
(3) 490.27 524 T
311.12 609 311.12 610.82 317.47 609 311.12 607.18 4 Y
0 Z
N
311.12 609 311.12 610.82 317.47 609 311.12 607.18 4 Y
V
309.38 609 310.88 609 2 L
2 Z
N
311.12 564 311.12 565.82 317.47 564 311.12 562.18 4 Y
0 Z
N
311.12 564 311.12 565.82 317.47 564 311.12 562.18 4 Y
V
309.38 564 310.88 564 2 L
2 Z
N
311.12 519 311.12 520.82 317.47 519 311.12 517.18 4 Y
0 Z
N
311.12 519 311.12 520.82 317.47 519 311.12 517.18 4 Y
V
309.38 519 310.88 519 2 L
2 Z
N
408.38 642.71 405.4 642.71 408.38 653.09 411.35 642.71 4 Y
0 Z
N
408.38 642.71 405.4 642.71 408.38 653.09 411.35 642.71 4 Y
V
354.38 501 354.38 637 408.38 637 408.38 642.46 4 L
2 Z
N
408.38 597.71 405.4 597.71 408.38 608.09 411.35 597.71 4 Y
0 Z
N
408.38 597.71 405.4 597.71 408.38 608.09 411.35 597.71 4 Y
V
354.38 591 408.38 591 408.38 597.46 3 L
2 Z
N
408.38 507.71 405.4 507.71 408.38 518.09 411.35 507.71 4 Y
0 Z
N
408.38 507.71 405.4 507.71 408.38 518.09 411.35 507.71 4 Y
V
93.38 501 408.38 501 408.38 507.46 3 L
2 Z
N
409.38 552.71 406.4 552.71 409.38 563.09 412.35 552.71 4 Y
0 Z
N
409.38 552.71 406.4 552.71 409.38 563.09 412.35 552.71 4 Y
V
354.38 546 409.38 546 409.38 552.46 3 L
2 Z
N
(\245) 235.66 615.14 T
(\245) 253.66 660 T
(\245) 308.09 498.43 T
(\245) 352.52 587.57 T
(\245) 352.66 543.14 T
(\245) 352.8 498.71 T
307.09 627 307.09 629.98 317.47 627 307.09 624.02 4 Y
0 Z
N
307.09 627 307.09 629.98 317.47 627 307.09 624.02 4 Y
V
300.38 699 300.38 627 306.84 627 3 L
2 Z
N
307.09 582 307.09 584.98 317.47 582 307.09 579.02 4 Y
0 Z
N
307.09 582 307.09 584.98 317.47 582 307.09 579.02 4 Y
V
291.38 699 291.38 582 306.84 582 3 L
2 Z
N
307.09 537 307.09 539.98 317.47 537 307.09 534.02 4 Y
0 Z
N
307.09 537 307.09 539.98 317.47 537 307.09 534.02 4 Y
V
282.38 699 282.38 537 306.84 537 3 L
2 Z
N
307.09 663 307.09 665.98 317.47 663 307.09 660.02 4 Y
0 Z
N
307.09 663 307.09 665.98 317.47 663 307.09 660.02 4 Y
V
306.84 663 210.38 663 2 L
2 Z
N
307.09 618 307.09 620.98 317.47 618 307.09 615.02 4 Y
0 Z
N
307.09 618 307.09 620.98 317.47 618 307.09 615.02 4 Y
V
306.84 618 210.38 618 2 L
2 Z
N
165.38 654 210.38 672 R
N
255.38 687.71 252.4 687.71 255.38 698.09 258.35 687.71 4 Y
0 Z
N
255.38 687.71 252.4 687.71 255.38 698.09 258.35 687.71 4 Y
V
255.38 663 255.38 687.46 2 L
2 Z
N
237.38 687.72 234.4 687.72 237.38 698.09 240.35 687.72 4 Y
0 Z
N
237.38 687.72 234.4 687.72 237.38 698.09 240.35 687.72 4 Y
V
237.38 618 237.38 687.47 2 L
2 Z
N
129.38 681 156.38 672 156.38 654 129.38 645 4 Y
N
118.09 672 118.09 674.98 128.47 672 118.09 669.02 4 Y
0 Z
N
118.09 672 118.09 674.98 128.47 672 118.09 669.02 4 Y
V
111.38 699 111.38 672 117.84 672 3 L
2 Z
N
118.09 627 118.09 629.98 128.47 627 118.09 624.02 4 Y
0 Z
N
118.09 627 118.09 629.98 128.47 627 118.09 624.02 4 Y
V
93.38 699 93.38 627 117.84 627 3 L
2 Z
N
118.09 654 118.09 656.98 128.47 654 118.09 651.02 4 Y
0 Z
N
118.09 654 118.09 656.98 128.47 654 118.09 651.02 4 Y
V
102.38 501 102.38 654 117.84 654 3 L
2 Z
N
118.09 609 118.09 611.98 128.47 609 118.09 606.02 4 Y
0 Z
N
118.09 609 118.09 611.98 128.47 609 118.09 606.02 4 Y
V
102.38 609 117.84 609 2 L
2 Z
N
(\245) 100.52 498.29 T
(MUX) 129.38 659 T
(Prescaler) 166.37 659 T
158.12 663 158.12 664.82 164.47 663 158.12 661.18 4 Y
0 Z
N
158.12 663 158.12 664.82 164.47 663 158.12 661.18 4 Y
V
156.38 663 157.88 663 2 L
2 Z
N
165.38 609 210.38 627 R
N
129.38 636 156.38 627 156.38 609 129.38 600 4 Y
N
(MUX) 129.38 614 T
(Prescaler) 166.37 614 T
158.12 618 158.12 619.82 164.47 618 158.12 616.18 4 Y
0 Z
N
158.12 618 158.12 619.82 164.47 618 158.12 616.18 4 Y
V
156.38 618 157.88 618 2 L
2 Z
N
(PCLK) 73.23 505 T
(Peripheral clock) 154.9 505 T
(A) 74.66 702.29 T
(CK1) 82.85 702.29 T
(A) 110.38 699.71 T
(CK0) 118.56 699.71 T
2 9 Q
(PRSK1 PRSK0) 219.38 700.71 T
(CLK) 282.38 708 T
(3) 282.38 699 T
(2 1) 291.38 699 T
( 0) 304.88 699 T
72 81 504 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "50" 56
%%Page: "51" 57
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(51) 528 17 T
0 F
(5.5.3.1 Pr) 108 721 T
(escaler Contr) 162.44 721 T
(ol Registers) 231.2 721 T
2 F
(Three \336elds are de\336ned for each prescaler control re) 108 699 T
(gister) 358.39 699 T
(.) 384.4 699 T
(\0501\051) 126 677 T
239.15 675.8 144 675.8 2 L
V
0.6 H
0 Z
N
1.59 (Prescalar counter v) 144 677 P
253.52 675.8 238.85 675.8 2 L
V
N
1.59 (alu) 238.85 677 P
1.59 (e- This determines the frequenc) 253.52 677 P
1.59 (y of the prescaler counter) 411.67 677 P
0.05 (output signal. The v) 144 663 P
0.05 (alue of this \336eld is written into the prescaler counter when this) 239.84 663 P
0.01 (\336eld is written and the timer clock is the prescaler counter clock or when prescaler) 144 649 P
2.06 (timeout \050counter reaches zero\051 occurs. This \336eld must be greater than zero. A) 144 635 P
-0.03 (v) 144 621 P
-0.03 (alue of one produces the maximum prescaler counter output frequenc) 149.7 621 P
-0.03 (y) 482.2 621 P
-0.03 (, on half of) 487.42 621 P
-0.02 (its input frequenc) 144 607 P
-0.02 (y) 227.77 607 P
-0.02 (. The number of bits for this \336eld is 8 to 16 and is an implemen-) 232.99 607 P
(tation parameter) 144 593 T
(.) 221.65 593 T
(\0502\051) 126 571 T
251.99 569.8 144 569.8 2 L
V
N
0.01 (Prescaler output select) 144 571 P
0.01 (- This selects the prescaler output clock rate as the prescaler) 251.99 571 P
0.18 (counter output frequenc) 144 557 P
0.18 (y di) 258.81 557 P
0.18 (vided by the po) 277.02 557 P
0.18 (wer of tw) 351.58 557 P
0.18 (o indicated by this \336eld. Zero) 397.79 557 P
1.55 (means the prescaler output clock rate is the prescaler counter output frequenc) 144 543 P
1.55 (y) 531.78 543 P
1.55 (.) 537 543 P
0.32 (One means the output clock rate is the prescaler counter output frequenc) 144 529 P
0.32 (y di) 494.98 529 P
0.32 (vided) 513.34 529 P
0.22 (by tw) 144 515 P
0.22 (o. T) 171.1 515 P
0.22 (w) 189.68 515 P
0.22 (o means the output clock rate is the prescaler counter output frequenc) 198.23 515 P
0.22 (y) 534 515 P
0.2 (di) 144 501 P
0.2 (vided by four) 153.04 501 P
0.2 (, etc. Note that the maximum output clock rate is half the prescaler) 217.62 501 P
0.33 (input frequenc) 144 487 P
0.33 (y) 213.8 487 P
0.33 (. The number of bits for this \336eld is 2 to 14 and is an implementa-) 219.02 487 P
(tion parameter) 144 473 T
(.) 212.99 473 T
(\0503\051) 126 451 T
187.43 449.8 144 449.8 2 L
V
N
1.78 (Enable e) 144 451 P
251.34 449.8 187.25 449.8 2 L
V
N
1.78 (xternal clock) 187.25 451 P
1.78 (- This one bit \336eld enables asynchronous e) 251.34 451 P
1.78 (xternal signals) 468.56 451 P
0.48 (when the prescaler input clock is one. When zero, the timer clock is the prescaler) 144 437 P
(input clock.) 144 423 T
(All unde\336ned bits are reserv) 108 401 T
(ed and one bit is reserv) 243.79 401 T
(ed for de) 354.59 401 T
(vice test purposes.) 396.94 401 T
0 F
(5.5.3.2 T) 108 357 T
(imer Contr) 157.79 357 T
(ol Registers) 215.22 357 T
2 F
-0.29 (Eight \336elds are de\336ned for each timer control re) 108 335 P
-0.29 (gister) 336.08 335 P
-0.29 (. A three bit Mode \336eld selects which) 362.08 335 P
(timer mode is acti) 108 321 T
(v) 194.03 321 T
(e.) 199.85 321 T
0 10 Q
(Mode Field) 229.95 292.33 T
(Operating Mode) 347.08 292.33 T
2 12 Q
(0) 201.75 271 T
2 10 Q
(Periodic Interrupt) 318.75 272.33 T
2 12 Q
(1) 201.75 249 T
2 10 Q
(T) 318.75 250.33 T
(imeout Interrupt) 324.51 250.33 T
2 12 Q
(2) 201.75 227 T
2 10 Q
(Square W) 318.75 228.33 T
(a) 357.66 228.33 T
(v) 361.9 228.33 T
(e Generator) 366.75 228.33 T
2 12 Q
(3) 201.75 205 T
2 10 Q
(Softw) 318.75 206.33 T
(are T) 342.54 206.33 T
(rigger W) 363.01 206.33 T
(atchdog) 398.03 206.33 T
2 12 Q
(4) 201.75 183 T
2 10 Q
(External T) 318.75 184.33 T
(rigger W) 360.89 184.33 T
(atchdog) 395.91 184.33 T
2 12 Q
(5) 201.75 161 T
2 10 Q
(Reserv) 318.75 162.33 T
(ed) 346.37 162.33 T
2 12 Q
(6) 201.75 139 T
2 10 Q
(Reserv) 318.75 140.33 T
(ed) 346.37 140.33 T
2 12 Q
(7) 201.75 117 T
2 10 Q
(Reserv) 318.75 118.33 T
(ed) 346.37 118.33 T
0 12 Q
(T) 221.62 95 T
(able 8:) 228.52 95 T
(T) 265.85 95 T
(imer Contr) 273.64 95 T
(ol Register Entries) 331.07 95 T
195.75 304.75 195.75 109.25 2 L
V
0.5 H
N
312.75 305.25 312.75 108.75 2 L
V
N
452.25 304.75 452.25 109.25 2 L
V
N
195.5 305 452.5 305 2 L
V
N
196 286.25 452 286.25 2 L
V
N
196 283.75 452 283.75 2 L
V
N
195.5 109 452.5 109 2 L
V
N
FMENDPAGE
%%EndPage: "51" 57
%%Page: "52" 58
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(52) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0.09 (A three bit e) 72 721 P
0.09 (v) 131.63 721 P
0.09 (ent \336eld selects the condition for which the timer e) 137.45 721 P
0.09 (v) 381.62 721 P
0.09 (ent input signal is acti) 387.44 721 P
0.09 (v) 492.85 721 P
0.09 (e) 498.67 721 P
(as an e) 72 707 T
(v) 104.35 707 T
(ent g) 110.17 707 T
(ate or trigger depending on the mode.) 133.78 707 T
1.76 (A tw) 72 455 P
1.76 (o bit Output Signal \336eld selects the state of the output signals when the timer is) 97.3 455 P
(stopped.) 72 441 T
-0.14 (A one bit In) 72 285 P
-0.14 (v) 128.77 285 P
-0.14 (ert \336eld modi\336es the output signal. If In) 134.59 285 P
-0.14 (v) 324.49 285 P
-0.14 (ert is one, then the actual output sig-) 330.31 285 P
-0.29 (nal is the normal output signal in) 72 271 P
-0.29 (v) 227.77 271 P
-0.29 (erted. If In) 233.59 271 P
-0.29 (v) 283.5 271 P
-0.29 (ert is zero, then the actual output signal is the) 289.32 271 P
(normal output signal.) 72 257 T
(A tw) 72 235 T
(o bit Clock Select \336eld selects the input clock to the timer counter) 95.54 235 T
(.) 411.53 235 T
0 10 Q
(Ev) 123.96 678.33 T
(ent Field) 135.54 678.33 T
(Acti) 209.37 678.33 T
(v) 227.04 678.33 T
(e Gate/T) 231.93 678.33 T
(rigger Ev) 268.14 678.33 T
(ent) 308.3 678.33 T
(A) 366.65 678.33 T
(pplicable Modes) 373.62 678.33 T
2 12 Q
(0) 118.5 657 T
2 10 Q
(Lo) 190.5 658.33 T
(w Le) 201.36 658.33 T
(v) 221.38 658.33 T
(el Gate) 226.23 658.33 T
(0,1,2) 352.5 658.33 T
2 12 Q
(1) 118.5 635 T
2 10 Q
(High Le) 190.5 636.33 T
(v) 223.3 636.33 T
(el Gate) 228.15 636.33 T
(1.1.2) 352.5 636.33 T
2 12 Q
(2) 118.5 613 T
2 10 Q
(Rising Edge T) 190.5 614.33 T
(rigger) 247.93 614.33 T
(4) 352.5 614.33 T
2 12 Q
(3) 118.5 591 T
2 10 Q
(F) 190.5 592.33 T
(alling Edge T) 195.91 592.33 T
(rigger) 250 592.33 T
(4) 352.5 592.33 T
2 12 Q
(4) 118.5 569 T
2 10 Q
(Rising/F) 190.5 570.33 T
(alling Edge T) 224.81 570.33 T
(riggers) 278.9 570.33 T
(4) 352.5 570.33 T
2 12 Q
(5) 118.5 547 T
2 10 Q
(Reserv) 190.5 548.33 T
(ed) 218.12 548.33 T
2 12 Q
(6) 118.5 525 T
2 10 Q
(Reserv) 190.5 526.33 T
(ed) 218.12 526.33 T
2 12 Q
(7) 118.5 503 T
2 10 Q
(Reserv) 190.5 504.33 T
(ed) 218.12 504.33 T
0 12 Q
(T) 216.72 481 T
(able 9:) 223.62 481 T
(T) 260.95 481 T
(imer Ev) 268.74 481 T
(ent Fields) 309.61 481 T
0 10 Q
(Output Signal Field) 164.76 412.33 T
(T) 288.25 412.33 T
(imer Inacti) 294.74 412.33 T
(v) 342.13 412.33 T
(e Output State) 347.03 412.33 T
2 F
(0) 152.25 392.33 T
(Remains in current state) 273.75 392.33 T
(1) 152.25 372.33 T
(External clock) 273.75 372.33 T
(2) 152.25 352.33 T
(Prescaler output clock) 273.75 352.33 T
(3) 152.25 332.33 T
(Reserv) 273.75 332.33 T
(ed) 301.37 332.33 T
0 12 Q
(T) 194.81 311 T
(able 10:) 201.71 311 T
(T) 245.05 311 T
(imer Output Signal Field) 252.83 311 T
0 10 Q
(Clock Select Field) 184.42 206.33 T
(Counter Clock Sour) 296.85 206.33 T
(ce) 382.77 206.33 T
2 F
(0) 172.5 186.33 T
(T) 285 186.33 T
(imer clock) 290.76 186.33 T
(1) 172.5 166.33 T
(External Clock) 285 166.33 T
(2) 172.5 146.33 T
(Prescaler output clock) 285 146.33 T
(3) 172.5 126.33 T
(Reserv) 285 126.33 T
(ed) 312.62 126.33 T
0 12 Q
(T) 199.5 105 T
(able 11:) 206.4 105 T
(T) 249.73 105 T
(imer Clock Select Field) 257.52 105 T
112.5 690.75 112.5 495.25 2 L
V
0.5 H
0 Z
N
184.5 691.25 184.5 494.75 2 L
V
N
346.5 691.25 346.5 494.75 2 L
V
N
463.5 690.75 463.5 495.25 2 L
V
N
112.25 691 463.75 691 2 L
V
N
112.75 672.25 463.25 672.25 2 L
V
N
112.75 669.75 463.25 669.75 2 L
V
N
112.25 495 463.75 495 2 L
V
N
146.25 424.75 146.25 325.25 2 L
V
N
267.75 425.25 267.75 324.75 2 L
V
N
429.75 424.75 429.75 325.25 2 L
V
N
146 425 430 425 2 L
V
N
146.5 406.25 429.5 406.25 2 L
V
N
146.5 403.75 429.5 403.75 2 L
V
N
146 325 430 325 2 L
V
N
166.5 218.75 166.5 119.25 2 L
V
N
279 219.25 279 118.75 2 L
V
N
409.5 218.75 409.5 119.25 2 L
V
N
166.25 219 409.75 219 2 L
V
N
166.75 200.25 409.25 200.25 2 L
V
N
166.75 197.75 409.25 197.75 2 L
V
N
166.25 119 409.75 119 2 L
V
N
FMENDPAGE
%%EndPage: "52" 58
%%Page: "53" 59
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(53) 528 17 T
1.31 (A one bit Count Enable \336eld, when one, enables the timer counter for counting. When) 108 721 P
-0.19 (Count Enable is zero, the counter stops. While enabled, the counter will not count until its) 108 707 P
-0.24 (speci\336ed input occurs. If a timer does not ha) 108 693 P
-0.24 (v) 318.77 693 P
-0.24 (e a prescaler or if its prescaler output clock is) 324.59 693 P
0.46 (not selected as its counter clock source, then con\336guring the timer counter and starting it) 108 679 P
(can be done with a single ST) 108 665 T
(A instruction.) 245.53 665 T
0.08 (If a timer is to use its prescaler output clock as its counter clock source, then the prescaler) 108 643 P
1.71 (con\336guration, the counter con\336guration, and starting can be done with a single STD) 108 629 P
1.71 (A) 531.34 629 P
-0.19 (instruction since the tw) 108 615 P
-0.19 (o control re) 218.97 615 P
-0.19 (gisters are mapped into adjacent memory addresses that) 273.73 615 P
-0.23 (are double w) 108 601 P
-0.23 (ord aligned. Note that the \336rst c) 169.39 601 P
-0.23 (ycle of the counter action may dif) 322.89 601 P
-0.23 (fer from the) 483.15 601 P
0.84 (later ones because the prescaler becomes acti) 108 587 P
0.84 (v) 329.33 587 P
0.84 (e one store memory time before the timer) 335.15 587 P
-0.13 (counter) 108 573 P
-0.13 (. If the prescaler uses the timer clock to dri) 143.33 573 P
-0.13 (v) 347.15 573 P
-0.13 (e its counter) 352.97 573 P
-0.13 (, then the prescaler counter) 410.89 573 P
1.28 (will be reloaded at the second memory c) 108 559 P
1.28 (ycle when the timer counter is loaded with its) 311.09 559 P
(reload v) 108 545 T
(alue.) 146.69 545 T
0.25 (A one bit Input Signal status \336eld, which must be read only) 108 523 P
0.25 (, allo) 395.27 523 P
0.25 (ws the program to e) 419.21 523 P
0.25 (xam-) 515.34 523 P
0.13 (ine the Input Signal. A one bit Output Signal status \336eld, which must be read only) 108 509 P
0.13 (, allo) 502.84 509 P
0.13 (ws) 526.67 509 P
(the program to e) 108 495 T
(xamine the Output Signal.) 186.8 495 T
(All unde\336ned bits are reserv) 108 473 T
(ed and one bit is reserv) 243.79 473 T
(ed for de) 354.59 473 T
(vice test purposes.) 396.94 473 T
0 F
(5.5.3.3 Pr) 108 429 T
(escaler Operation) 162.44 429 T
2 F
1.34 (Figure 11 sho) 108 407 P
1.34 (ws an e) 176.37 407 P
1.34 (xample prescaler block diagram consisting of an 8 bit counter) 214.85 407 P
1.34 (, 7-) 522.67 407 P
(di) 108 393 T
(vide by 2 \337ip-\337ops and selector logic) 117.04 393 T
0 F
(Figur) 231.9 116 T
(e 11:) 260.35 116 T
(Pr) 287.68 116 T
(escaler Block Diagram) 300.12 116 T
108 81 540 729 C
111.75 126 536.25 353 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
470.75 245 488.75 263 R
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
434.75 245 452.75 263 R
N
398.75 245 416.75 263 R
N
362.75 245 380.75 263 R
N
326.75 245 344.75 263 R
N
290.75 245 308.75 263 R
N
254.75 245 272.75 263 R
N
200.75 245 236.75 263 R
N
459.46 254 459.46 256.98 469.84 254 459.46 251.02 4 Y
0 Z
N
459.46 254 459.46 256.98 469.84 254 459.46 251.02 4 Y
V
452.75 254 459.21 254 2 L
2 Z
N
497.75 238.28 500.73 238.28 497.75 227.91 494.77 238.28 4 Y
0 Z
N
497.75 238.28 500.73 238.28 497.75 227.91 494.77 238.28 4 Y
V
488.75 254 497.75 254 497.75 238.53 3 L
2 Z
N
236.75 182 506.75 227 R
N
461.75 238.28 464.73 238.28 461.75 227.91 458.77 238.28 4 Y
0 Z
N
461.75 238.28 464.73 238.28 461.75 227.91 458.77 238.28 4 Y
V
461.75 254 461.75 238.53 2 L
2 Z
N
423.46 254 423.46 256.98 433.84 254 423.46 251.02 4 Y
0 Z
N
423.46 254 423.46 256.98 433.84 254 423.46 251.02 4 Y
V
416.75 254 423.21 254 2 L
2 Z
N
425.75 238.28 428.73 238.28 425.75 227.91 422.77 238.28 4 Y
0 Z
N
425.75 238.28 428.73 238.28 425.75 227.91 422.77 238.28 4 Y
V
425.75 254 425.75 238.53 2 L
2 Z
N
387.46 253 387.46 255.98 397.84 253 387.46 250.02 4 Y
0 Z
N
387.46 253 387.46 255.98 397.84 253 387.46 250.02 4 Y
V
380.75 253 387.21 253 2 L
2 Z
N
389.75 237.28 392.73 237.28 389.75 226.91 386.77 237.28 4 Y
0 Z
N
389.75 237.28 392.73 237.28 389.75 226.91 386.77 237.28 4 Y
V
389.75 253 389.75 237.53 2 L
2 Z
N
351.46 253 351.46 255.98 361.84 253 351.46 250.02 4 Y
0 Z
N
351.46 253 351.46 255.98 361.84 253 351.46 250.02 4 Y
V
344.75 253 351.21 253 2 L
2 Z
N
353.75 237.28 356.73 237.28 353.75 226.91 350.77 237.28 4 Y
0 Z
N
353.75 237.28 356.73 237.28 353.75 226.91 350.77 237.28 4 Y
V
353.75 253 353.75 237.53 2 L
2 Z
N
245.75 238.28 248.73 238.28 245.75 227.91 242.77 238.28 4 Y
0 Z
N
245.75 238.28 248.73 238.28 245.75 227.91 242.77 238.28 4 Y
V
245.75 254 245.75 238.53 2 L
2 Z
N
243.46 254 243.46 256.98 253.84 254 243.46 251.02 4 Y
0 Z
N
243.46 254 243.46 256.98 253.84 254 243.46 251.02 4 Y
V
236.75 254 243.21 254 2 L
2 Z
N
371.75 157.28 374.73 157.28 371.75 146.91 368.77 157.28 4 Y
0 Z
N
371.75 157.28 374.73 157.28 371.75 146.91 368.77 157.28 4 Y
V
371.75 182 371.75 157.53 2 L
2 Z
N
194.03 173 194.03 170.02 183.65 173 194.03 175.98 4 Y
0 Z
N
194.03 173 194.03 170.02 183.65 173 194.03 175.98 4 Y
V
371.75 173 194.28 173 2 L
2 Z
N
317.75 299 506.75 317 R
N
513.79 191 513.79 188.87 506.37 191 513.79 193.13 4 Y
0 Z
N
513.79 191 513.79 188.87 506.37 191 513.79 193.13 4 Y
V
371.75 299 371.75 272 515.75 272 515.75 191 514.04 191 5 L
2 Z
N
514 209 514 207.18 507.66 209 514 210.82 4 Y
0 Z
N
514 209 514 207.18 507.66 209 514 210.82 4 Y
V
515.75 209 514.25 209 2 L
2 Z
N
514 200 514 198.18 507.66 200 514 201.82 4 Y
0 Z
N
514 200 514 198.18 507.66 200 514 201.82 4 Y
V
515.75 200 514.25 200 2 L
2 Z
N
2 10 Q
(15 14 13 12 11 10) 320.75 326 T
(9) 400.75 326 T
(8) 413.25 326 T
(7) 425.75 326 T
(6) 438.25 326 T
(5) 450.75 326 T
(4) 463.25 326 T
(3) 475.75 326 T
(2) 488.25 326 T
(1) 500.75 326 T
331.75 317 331.75 299 2 L
N
376.75 317 376.75 299 2 L
N
416.75 317 416.75 299 2 L
N
218.75 270.25 220.57 270.25 218.75 263.91 216.93 270.25 4 Y
0 Z
N
218.75 270.25 220.57 270.25 218.75 263.91 216.93 270.25 4 Y
V
425.75 299 425.75 281 218.75 281 218.75 272 218.75 270.5 5 L
2 Z
N
189.46 254 189.46 256.98 199.84 254 189.46 251.02 4 Y
0 Z
N
189.46 254 189.46 256.98 199.84 254 189.46 251.02 4 Y
V
182.75 254 189.21 254 2 L
2 Z
N
316.46 254 316.46 256.98 326.84 254 316.46 251.02 4 Y
0 Z
N
316.46 254 316.46 256.98 326.84 254 316.46 251.02 4 Y
V
309.75 254 316.21 254 2 L
2 Z
N
318.75 238.28 321.73 238.28 318.75 227.91 315.77 238.28 4 Y
0 Z
N
318.75 238.28 321.73 238.28 318.75 227.91 315.77 238.28 4 Y
V
318.75 254 318.75 238.53 2 L
2 Z
N
282.75 238.28 285.73 238.28 282.75 227.91 279.77 238.28 4 Y
0 Z
N
282.75 238.28 285.73 238.28 282.75 227.91 279.77 238.28 4 Y
V
282.75 254 282.75 238.53 2 L
2 Z
N
2 12 Q
(Prescaler re) 356.75 340 T
(gister) 412.87 340 T
(BIT) 297.75 325 T
2 10 Q
(Clock) 151.25 254 T
(8 Bit Cnt) 202.64 254 T
(+2) 256.82 254 T
(+2) 292.46 254 T
(+2) 328.1 254 T
(+2) 363.74 254 T
(+2) 401.88 254 T
(+2) 437.52 254 T
(+2) 473.16 254 T
(PRSCK) 156.75 182 T
(PRSCK for internal use) 381.75 146 T
(+256) 237.75 218 T
(Max) 237.75 208 T
(Count) 237.75 198 T
2 12 Q
(SELECT) 346.75 202 T
(OR) 390.54 202 T
108 81 540 729 C
0 0 612 792 C
280.71 253 280.71 255.98 291.09 253 280.71 250.02 4 Y
0.5 H
0 Z
0 X
0 0 0 1 0 0 0 K
N
280.71 253 280.71 255.98 291.09 253 280.71 250.02 4 Y
V
274 253 280.46 253 2 L
2 Z
N
FMENDPAGE
%%EndPage: "53" 59
%%Page: "54" 60
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(54) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
(\0501\051) 90 721 T
(Prescaler Counter:) 108 721 T
1.04 (The prescaler counter is loaded with the prescaler count v) 108 699 P
1.04 (alue \336eld concurrently) 393.95 699 P
-0.21 (with that \336eld being written into the prescaler control re) 108 685 P
-0.21 (gister when the timer clock) 374.2 685 P
1.2 (dri) 108 671 P
1.2 (v) 121.03 671 P
1.2 (es the counter) 126.85 671 P
1.2 (. The counter then be) 195.24 671 P
1.2 (gins to decrement at its clock frequenc) 305.69 671 P
1.2 (y) 498 671 P
0.82 (and generates an output each time it reaches zero. This output is deli) 108 657 P
0.82 (v) 445.88 657 P
0.82 (ered to the) 451.7 657 P
0.05 (\336rst \337ip-\337op input in the di) 108 643 P
0.05 (vide by 2 \337ip-\337op cascade and the output selector) 238.28 643 P
0.05 (. This) 476.62 643 P
0.7 (output also reloads the counter with the prescaler count v) 108 629 P
0.7 (alue \336eld and continues) 388.26 629 P
(the count.) 108 615 T
-0.28 (If the associated timer counter uses the prescaler output clock as its input clock and) 108 593 P
-0.21 (if the prescaler uses the timer clock as its input, then when the timer reload v) 108 579 P
-0.21 (alue is) 473.21 579 P
0.58 (loaded or reloaded into the timer counter) 108 565 P
0.58 (, the prescaler count v) 306.95 565 P
0.58 (alue is loaded into) 414.6 565 P
(the prescaler counter and a fresh prescaler count c) 108 551 T
(ycle be) 347.72 551 T
(gins.) 381.86 551 T
2.08 (When the prescaler counter is dri) 108 529 P
2.08 (v) 277.05 529 P
2.08 (en by the e) 282.88 529 P
2.08 (xternal clock, the count v) 341.26 529 P
2.08 (alue is) 470.92 529 P
0.48 (loaded into the counter only when it reaches zero.If the count v) 108 515 P
0.48 (alue is changed in) 416.24 515 P
2.67 (the prescaler counter re) 108 501 P
2.67 (gister) 228.12 501 P
2.67 (, it will not be loaded into the counter until the) 254.3 501 P
0.56 (counter reaches zero, \336nishing the pre) 108 487 P
0.56 (vious count sequence. T) 293.1 487 P
0.56 (o reduce this delay) 409.8 487 P
0.56 (,) 501 487 P
0.38 (switch the prescaler counter dri) 108 473 P
0.38 (v) 259.82 473 P
0.38 (e to timer clock, then change the count v) 265.64 473 P
0.38 (alue and) 463.3 473 P
(switch to e) 108 459 T
(xternal clock.) 159.82 459 T
(\0502\051) 90 437 T
(Prescaler Di) 108 437 T
(vide by 2 Cascade:) 166.68 437 T
0.67 (At each \337ip-\337op output in the di) 108 415 P
0.67 (vide by 2 cascade, the frequenc) 266.39 415 P
0.67 (y is halv) 420.18 415 P
0.67 (ed. Each) 462.01 415 P
(output is deli) 108 401 T
(v) 170.38 401 T
(ered to the ne) 176.2 401 T
(xt \337ip-\337op input in the chain and the output selector) 241 401 T
(.) 490 401 T
-0.26 (The \337ip-\337ops in the di) 108 379 P
-0.26 (vide by 2 cascade are cleared whene) 213.98 379 P
-0.26 (v) 386.69 379 P
-0.26 (er the prescaler counter) 392.51 379 P
(is loaded or reloaded.) 108 365 T
(\0503\051) 90 343 T
(Prescaler Output Selector) 108 343 T
0.76 (The selector logic selects the counter output or one of the \337ip-\337op outputs in the) 108 321 P
0.5 (di) 108 307 P
0.5 (vide by 2 cascade as determined by the prescaler output select \336eld of the pres-) 117.04 307 P
1.33 (caler control re) 108 293 P
1.33 (gister) 183.11 293 P
1.33 (. Code 0 selects the counter output. Code 1 selects the \336rst) 209.11 293 P
0.19 (di) 108 279 P
0.19 (vide by 2 \337ip-\337op output. Code 2 selects the second di) 117.04 279 P
0.19 (vide by 2 \337ip-\337op output,) 380.25 279 P
(etc.) 108 265 T
-0.18 (When one of the di) 108 243 P
-0.18 (vide by 2 \337ip-\337op outputs is the selected prescaler output clock) 198.97 243 P
0.2 (then the duty c) 108 229 P
0.2 (ycle will be 50%. Ho) 179.42 229 P
0.2 (we) 281.59 229 P
0.2 (v) 295.28 229 P
0.2 (er) 301.1 229 P
0.2 (, when the counter output is the selected) 309.94 229 P
1.23 (prescaler output clock, then the output will be one more than zero e) 108 215 P
1.23 (xcept at the) 446.21 215 P
(highest frequenc) 108 201 T
(y) 187.46 201 T
(.) 192.68 201 T
1.08 (The counter output is one until the counter decrements to one. Then the counter) 108 179 P
-0.22 (output is zero for one count c) 108 165 P
-0.22 (ycle. Then when the counter reaches zero, the counter) 247.16 165 P
0.51 (output returns to one while the counter is reloaded and be) 108 151 P
0.51 (gins a ne) 388.9 151 P
0.51 (w count do) 432.28 151 P
0.51 (wn.) 486.34 151 P
-0.09 (Therefore the prescaler output clock is zero for one count c) 108 137 P
-0.09 (ycle and one all the rest) 390.82 137 P
(of the count c) 108 123 T
(ycles.) 173.47 123 T
0.03 (Ho) 108 101 P
0.03 (we) 122.36 101 P
0.03 (v) 136.06 101 P
0.03 (er) 141.88 101 P
0.03 (, if the prescaler count v) 150.72 101 P
0.03 (alue is one, which selects the maximum prescaler) 266.52 101 P
0.72 (counter frequenc) 108 87 P
0.72 (y) 189.5 87 P
0.72 (, the counter output is forced to zero at the same time the pres-) 194.72 87 P
FMENDPAGE
%%EndPage: "54" 60
%%Page: "55" 61
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(55) 528 17 T
1.34 (caler count v) 144 721 P
1.34 (alue is loaded into the counter) 208.36 721 P
1.34 (. The ne) 358.7 721 P
1.34 (xt c) 400.18 721 P
1.34 (ycle, with the counter at) 419 721 P
0.33 (zero, the counter output goes to one and the counter is reloaded. F) 144 707 P
0.33 (or this case, the) 464.36 707 P
(prescaler output clock has a 50% duty c) 144 693 T
(ycle.) 334.78 693 T
0 F
(5.5.3.4 T) 108 649 T
(imer Operation and T) 157.79 649 T
(imer Operating Modes) 270.58 649 T
2 F
(Figure 12 sho) 108 627 T
(ws a block diagram of a timer) 173.7 627 T
(.) 316.34 627 T
0 F
(Figur) 239.89 370.88 T
(e 12:) 268.34 370.88 T
(T) 295.67 370.88 T
(imer Block Diagram) 303.46 370.88 T
2 F
-0.09 (The data path to the processor is capable of both input and output. In addition to the timer) 108 332.88 P
1.31 (clock, there are tw) 108 318.88 P
1.31 (o other clock inputs, prescaler output clock and e) 200.45 318.88 P
1.31 (xternal clock. Also) 446.39 318.88 P
2.07 (there is an In Signal that serv) 108 304.88 P
2.07 (es as input to count g) 260.21 304.88 P
2.07 (ating logic or e) 372.16 304.88 P
2.07 (v) 450.39 304.88 P
2.07 (ent trigger logic.) 456.21 304.88 P
0.19 (Finally) 108 290.88 P
0.19 (, there is the timer Out Signal which may be deli) 141.23 290.88 P
0.19 (v) 375.84 290.88 P
0.19 (ered to an output pin and used to) 381.66 290.88 P
-0.1 (control e) 108 276.88 P
-0.1 (xternal system acti) 150.04 276.88 P
-0.1 (vities or deli) 239.53 276.88 P
-0.1 (v) 299.03 276.88 P
-0.1 (ered to interrupt request lines and used to period-) 304.85 276.88 P
0.25 (ically acti) 108 262.88 P
0.25 (v) 154.94 262.88 P
0.25 (ate service routines or used to acti) 160.64 262.88 P
0.25 (v) 328.38 262.88 P
0.25 (ate e) 334.08 262.88 P
0.25 (xception routines if e) 356.47 262.88 P
0.25 (v) 458.57 262.88 P
0.25 (ents f) 464.39 262.88 P
0.25 (ail to hap-) 490.84 262.88 P
(pen within preset time limits.) 108 248.88 T
1.24 (The In Signal can be used as a g) 108 226.88 P
1.24 (ating signal in Modes 0, 1, 2 and 3 to mask the timer) 272.48 226.88 P
0.63 (counter input clock and temporarily stop the timer) 108 212.88 P
0.63 (. It can be used in Mode 4 as a trigger) 352.73 212.88 P
(e) 108 198.88 T
(v) 113.03 198.88 T
(ent to start a ne) 118.85 198.88 T
(w timer count sequence.) 191.87 198.88 T
0.98 (T) 108 176.88 P
0.98 (o use the In Signal as a g) 114.37 176.88 P
0.98 (ating signal in Modes 0, 1, 2 and 2, the Ev) 240.82 176.88 P
0.98 (ent \336eld is set to) 457.41 176.88 P
1.74 (mak) 108 162.88 P
1.74 (e In acti) 128.54 162.88 P
1.74 (v) 170.38 162.88 P
1.74 (e when one or when zero. When acti) 176.2 162.88 P
1.74 (v) 363.35 162.88 P
1.74 (e, clocks to the input of the timer) 369.17 162.88 P
(counter are inhibited and the counter does not count.) 108 148.88 T
-0.25 (T) 108 126.88 P
-0.25 (o use the In Signal as a triggering signal in Mode 4, the Ev) 114.37 126.88 P
-0.25 (ent \336eld is set to mak) 392.89 126.88 P
-0.25 (e the trig-) 493.85 126.88 P
-0.05 (ger e) 108 112.88 P
-0.05 (v) 131.3 112.88 P
-0.05 (ent a rising edge, f) 137.12 112.88 P
-0.05 (alling edge or both a rising and f) 225.78 112.88 P
-0.05 (alling edge. When In Signal gen-) 381.61 112.88 P
0.18 (erates a trigger e) 108 98.88 P
0.18 (v) 187.87 98.88 P
0.18 (ent, timer output is forced to v) 193.68 98.88 P
0.18 (alue of In) 340.11 98.88 P
0.18 (v) 385.97 98.88 P
0.18 (ert bit in timer control re) 391.79 98.88 P
0.18 (gister) 510.82 98.88 P
0.18 (,) 537 98.88 P
108 81 540 729 C
108 380.88 540 601 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
178.59 565 205.59 556 205.59 538 178.59 529 4 Y
0.5 H
2 Z
0 X
0 0 0 1 0 0 0 K
N
223.59 538 295.59 556 R
N
322.59 538 394.59 565 R
N
322.59 574 394.59 592 R
N
430.59 538 466.59 592 R
N
223.59 502 295.59 520 R
N
178.59 475 241.59 493 R
N
160.59 390 484.59 597 R
2 H
8 X
N
160.59 469 484.59 469 2 L
N
160.59 441 484.59 441 2 L
N
160.59 414 484.59 414 2 L
N
167.31 556 167.31 558.98 177.69 556 167.31 553.02 4 Y
0.5 H
0 Z
0 X
N
167.31 556 167.31 558.98 177.69 556 167.31 553.02 4 Y
V
133.59 556 167.06 556 2 L
2 Z
N
167.56 538 167.56 540.64 176.78 538 167.56 535.36 4 Y
1 H
0 Z
N
167.56 538 167.56 540.64 176.78 538 167.56 535.36 4 Y
V
167.06 538 133.59 538 2 L
2 Z
N
167.31 484 167.31 486.98 177.69 484 167.31 481.02 4 Y
0.5 H
0 Z
N
167.31 484 167.31 486.98 177.69 484 167.31 481.02 4 Y
V
167.06 484 133.59 484 2 L
2 Z
N
133.59 583 160.59 583 2 L
1 H
N
133.59 579 160.59 579 2 L
N
159.04 586.4 167.14 581 159.04 575.6 3 L
2 H
N
138.14 586.4 130.04 581 138.14 575.6 3 L
N
128.59 467 155.59 467 2 L
1 H
N
128.59 463 155.59 463 2 L
N
154.04 470.4 162.14 465 154.04 459.6 3 L
2 H
N
133.14 470.4 125.04 465 133.14 459.6 3 L
N
149.31 457 149.31 459.98 159.69 457 149.31 454.02 4 Y
0.5 H
0 Z
N
149.31 457 149.31 459.98 159.69 457 149.31 454.02 4 Y
V
149.06 457 124.59 457 2 L
2 Z
N
149.31 452 149.31 454.98 159.69 452 149.31 449.02 4 Y
0 Z
N
149.31 452 149.31 454.98 159.69 452 149.31 449.02 4 Y
V
149.06 452 124.59 452 2 L
2 Z
N
149.31 448 149.31 450.98 159.69 448 149.31 445.02 4 Y
0 Z
N
149.31 448 149.31 450.98 159.69 448 149.31 445.02 4 Y
V
149.06 448 124.59 448 2 L
2 Z
N
126.59 437 153.59 437 2 L
1 H
N
126.59 433 153.59 433 2 L
N
152.04 440.4 160.14 435 152.04 429.6 3 L
2 H
N
131.14 440.4 123.04 435 131.14 429.6 3 L
N
147.31 427 147.31 429.98 157.69 427 147.31 424.02 4 Y
0.5 H
0 Z
N
147.31 427 147.31 429.98 157.69 427 147.31 424.02 4 Y
V
147.06 427 122.59 427 2 L
2 Z
N
147.31 422 147.31 424.98 157.69 422 147.31 419.02 4 Y
0 Z
N
147.31 422 147.31 424.98 157.69 422 147.31 419.02 4 Y
V
147.06 422 122.59 422 2 L
2 Z
N
147.31 418 147.31 420.98 157.69 418 147.31 415.02 4 Y
0 Z
N
147.31 418 147.31 420.98 157.69 418 147.31 415.02 4 Y
V
147.06 418 122.59 418 2 L
2 Z
N
127.59 412 154.59 412 2 L
1 H
N
127.59 408 154.59 408 2 L
N
153.04 415.4 161.14 410 153.04 404.6 3 L
2 H
N
132.14 415.4 124.04 410 132.14 404.6 3 L
N
148.31 402 148.31 404.98 158.69 402 148.31 399.02 4 Y
0.5 H
0 Z
N
148.31 402 148.31 404.98 158.69 402 148.31 399.02 4 Y
V
148.06 402 123.59 402 2 L
2 Z
N
148.31 397 148.31 399.98 158.69 397 148.31 394.02 4 Y
0 Z
N
148.31 397 148.31 399.98 158.69 397 148.31 394.02 4 Y
V
148.06 397 123.59 397 2 L
2 Z
N
148.31 393 148.31 395.98 158.69 393 148.31 390.02 4 Y
0 Z
N
148.31 393 148.31 395.98 158.69 393 148.31 390.02 4 Y
V
148.06 393 123.59 393 2 L
2 Z
N
2 12 Q
(D0-15) 115.59 587 T
(PRSCK0) 112.59 559 T
(CLK0) 112.59 541 T
(IN0) 115.59 488 T
(TIMER0) 178.59 583 T
(TIMER1) 178.59 457 T
(TIMER2) 178.59 430 T
(TIMER3) 178.59 403 T
(MUX) 178.59 543 T
212.31 547 212.31 549.98 222.69 547 212.31 544.02 4 Y
0 Z
N
212.31 547 212.31 549.98 222.69 547 212.31 544.02 4 Y
V
205.59 547 212.06 547 2 L
2 Z
N
259.59 571.71 256.62 571.71 259.59 582.09 262.57 571.71 4 Y
0 Z
N
259.59 571.71 256.62 571.71 259.59 582.09 262.57 571.71 4 Y
V
259.59 556 259.59 571.46 2 L
2 Z
N
311.31 560 311.31 562.98 321.69 560 311.31 557.02 4 Y
0 Z
N
311.31 560 311.31 562.98 321.69 560 311.31 557.02 4 Y
V
259.59 560 311.06 560 2 L
2 Z
N
311.31 583 311.31 585.98 321.69 583 311.31 580.02 4 Y
0 Z
N
311.31 583 311.31 585.98 321.69 583 311.31 580.02 4 Y
V
277.59 583 311.06 583 2 L
2 Z
N
277.59 560.75 277.59 583.25 2 L
N
259.59 526.71 256.62 526.71 259.59 537.09 262.57 526.71 4 Y
0 Z
N
259.59 526.71 256.62 526.71 259.59 537.09 262.57 526.71 4 Y
V
259.59 520 259.59 526.46 2 L
2 Z
N
311.31 542 311.31 544.98 321.69 542 311.31 539.02 4 Y
0 Z
N
311.31 542 311.31 544.98 321.69 542 311.31 539.02 4 Y
V
259.59 529 306.84 529 306.84 542 311.06 542 4 L
2 Z
N
2 10 Q
(Counter \05016 bit\051) 227.59 544 T
(Reload) 243.59 509 T
(Input Control) 183.59 481 T
(ZER) 331.59 580 T
(O Def) 350.08 580 T
(EQ) 331.59 556 T
(U) 344.82 556 T
(AL) 351.64 556 T
(Defect) 331.59 546 T
419.31 583 419.31 585.98 429.69 583 419.31 580.02 4 Y
0 Z
N
419.31 583 419.31 585.98 429.69 583 419.31 580.02 4 Y
V
394.59 583 419.06 583 2 L
2 Z
N
419.31 556 419.31 558.98 429.69 556 419.31 553.02 4 Y
0 Z
N
419.31 556 419.31 558.98 429.69 556 419.31 553.02 4 Y
V
394.59 556 419.06 556 2 L
2 Z
N
419.31 547 419.31 549.98 429.69 547 419.31 544.02 4 Y
0 Z
N
419.31 547 419.31 549.98 429.69 547 419.31 544.02 4 Y
V
394.59 547 419.06 547 2 L
2 Z
N
(Output) 433.59 569 T
(Control) 433.59 559 T
500.31 565 500.31 567.98 510.69 565 500.31 562.02 4 Y
0 Z
N
500.31 565 500.31 567.98 510.69 565 500.31 562.02 4 Y
V
466.59 565 500.06 565 2 L
2 Z
N
2 12 Q
(OUT0) 493.59 574 T
500.31 457 500.31 459.98 510.69 457 500.31 454.02 4 Y
0 Z
N
500.31 457 500.31 459.98 510.69 457 500.31 454.02 4 Y
V
484.59 457 500.06 457 2 L
2 Z
N
500.31 430 500.31 432.98 510.69 430 500.31 427.02 4 Y
0 Z
N
500.31 430 500.31 432.98 510.69 430 500.31 427.02 4 Y
V
484.59 430 500.06 430 2 L
2 Z
N
500.31 403 500.31 405.98 510.69 403 500.31 400.02 4 Y
0 Z
N
500.31 403 500.31 405.98 510.69 403 500.31 400.02 4 Y
V
484.59 403 500.06 403 2 L
2 Z
N
108 81 540 729 C
0 0 612 792 C
FMENDPAGE
%%EndPage: "55" 61
%%Page: "56" 62
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(56) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
0.19 (reload v) 72 721 P
0.19 (alue is forced into timer counter and a ne) 110.88 721 P
0.19 (w timer count sequence be) 308.73 721 P
0.19 (gins. At time-) 437.28 721 P
(out, timer output changes to not In) 72 707 T
(v) 237.18 707 T
(ert bit v) 243 707 T
(alue.) 280.03 707 T
1.45 (The Out Signal is used to indicate timeout, occurrence of an e) 72 685 P
1.45 (v) 384.27 685 P
1.45 (ent at the In Signal, or) 390.09 685 P
1.95 (counter reaching half reload v) 72 671 P
1.95 (alue during the count sequence. The Out Signal control) 223.45 671 P
1.27 (determines the v) 72 657 P
1.27 (alue of the Out Signal when the timer is stopped. The In) 153.56 657 P
1.27 (v) 436.33 657 P
1.27 (ert bit deter-) 442.15 657 P
(mines the inacti) 72 643 T
(v) 147.7 643 T
(e le) 153.52 643 T
(v) 170.21 643 T
(el of Out Signal when the timer is running.) 176.03 643 T
-0.16 (When the In) 72 621 P
-0.16 (v) 130.52 621 P
-0.16 (ert bit is 0, for each mode, the follo) 136.34 621 P
-0.16 (wing conditions set and reset the Out Sig-) 304.1 621 P
(nal:) 72 607 T
(Set and Reset are sw) 72 431 T
(apped when the In) 171.19 431 T
(v) 259.02 431 T
(ert bit is 1.) 264.84 431 T
0.79 (T) 72 409 P
0.79 (imers are stopped follo) 78.91 409 P
0.79 (wing processor reset. T) 191.31 409 P
0.79 (imer operation is initialized in all modes) 305.24 409 P
0.52 (by \336rst writing the timer mode into the Mode \336eld of the T) 72 395 P
0.52 (imer Control Re) 360.44 395 P
0.52 (gister) 439.3 395 P
0.52 (, setting) 465.48 395 P
0.55 (the Count Enable \336eld to 1 and writing an) 72 381 P
0.55 (y other appropriate \336elds of the T) 277.57 381 P
0.55 (imer Control) 441.78 381 P
-0.19 (Re) 72 367 P
-0.19 (gister) 85.15 367 P
-0.19 (. T) 111.16 367 P
-0.19 (imer operation in modes 0, 1, 2 and 3 be) 123.88 367 P
-0.19 (gins when the reload re) 315.66 367 P
-0.19 (gister is written.) 426.71 367 P
(Then the reload v) 72 353 T
(alue is set in the counter and decrementing be) 156.01 353 T
(gins.) 375.12 353 T
1.85 (T) 72 331 P
1.85 (imer operation in mode 4 be) 78.91 331 P
1.85 (gins when a trigger e) 223.65 331 P
1.85 (v) 331.41 331 P
1.85 (ent occurs at In Signal. Then the) 337.23 331 P
(reload v) 72 317 T
(alue is set in the counter and decrementing be) 110.69 317 T
(gins.) 329.8 317 T
(Once operating, each timer stops in the v) 72 295 T
(arious modes as follo) 268.33 295 T
(ws:) 370.36 295 T
(Note that timers can be stopped in all modes by writing to the T) 72 119 T
(imer Control Re) 377.89 119 T
(gister) 455.71 119 T
(.) 481.72 119 T
0 10 Q
(Mode) 121.65 578.33 T
(Set Out Signal) 195.29 578.33 T
(Reset Out Signal) 344.42 578.33 T
2 F
(0) 101.62 558.33 T
(T) 178.12 558.33 T
(imeout) 183.88 558.33 T
(Writing reload re) 286.12 558.33 T
(gister/reading counter) 354.85 558.33 T
(1) 101.62 538.33 T
(T) 178.12 538.33 T
(imeout) 183.88 538.33 T
(Writing reload re) 286.12 538.33 T
(gister/reading counter) 354.85 538.33 T
(2) 101.62 518.33 T
(T) 178.12 518.33 T
(imeout) 183.88 518.33 T
(Counter = half reload re) 286.12 518.33 T
(gister) 382.14 518.33 T
(3) 101.62 498.33 T
(T) 178.12 498.33 T
(imeout) 183.88 498.33 T
(Writing reload re) 286.12 498.33 T
(gister) 354.85 498.33 T
(4) 101.62 478.33 T
(T) 178.12 478.33 T
(imeout) 183.88 478.33 T
(T) 286.12 478.33 T
(rigger e) 291.89 478.33 T
(v) 322.45 478.33 T
(ent occurs at In Signal) 327.3 478.33 T
0 12 Q
(T) 197.2 457 T
(able 12:) 204.1 457 T
(Output Signal Conditions) 247.43 457 T
0 10 Q
(Mode) 167.78 266.33 T
(Stop T) 299.79 266.33 T
(imer) 328.23 266.33 T
2 F
(0) 150 246.33 T
(Writing TCR, In Signal acti) 222 246.33 T
(v) 333.14 246.33 T
(e) 337.99 246.33 T
(1) 150 226.33 T
(Writing TCR, In Signal acti) 222 226.33 T
(v) 333.14 226.33 T
(e, timeout) 337.99 226.33 T
(2) 150 206.33 T
(Writing TCR, In Signal acti) 222 206.33 T
(v) 333.14 206.33 T
(e) 337.99 206.33 T
(3) 150 186.33 T
(Writing TCR, In Signal acti) 222 186.33 T
(v) 333.14 186.33 T
(e, timeout) 337.99 186.33 T
(4) 150 166.33 T
(Writing TCR, timeout) 222 166.33 T
0 12 Q
(T) 215.33 145 T
(able 13:) 222.23 145 T
(T) 265.56 145 T
(imer Stop Modes) 273.35 145 T
95.62 590.75 95.62 471.25 2 L
V
0.5 H
0 Z
N
172.12 591.25 172.12 470.75 2 L
V
N
280.12 591.25 280.12 470.75 2 L
V
N
480.38 590.75 480.38 471.25 2 L
V
N
95.38 591 480.62 591 2 L
V
N
95.88 572.25 480.12 572.25 2 L
V
N
95.88 569.75 480.12 569.75 2 L
V
N
95.38 471 480.62 471 2 L
V
N
144 278.75 144 159.25 2 L
V
N
216 279.25 216 158.75 2 L
V
N
432 278.75 432 159.25 2 L
V
N
143.75 279 432.25 279 2 L
V
N
144.25 260.25 431.75 260.25 2 L
V
N
144.25 257.75 431.75 257.75 2 L
V
N
143.75 159 432.25 159 2 L
V
N
FMENDPAGE
%%EndPage: "56" 62
%%Page: "57" 63
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(5) 108 17 T
(Peripheral Extensions) 120 17 T
(57) 528 17 T
0.85 (W) 108 721 P
0.85 (ith respect to timer operating modes, each timer can be independently programmed to) 118.85 721 P
(operate in one of the follo) 108 707 T
(wing \336v) 232.01 707 T
(e modes:) 271.5 707 T
-0.19 (The selection of a particular operating mode is controlled by the v) 108 531 P
-0.19 (alue of the Mode \336eld in) 422.61 531 P
(the T) 108 517 T
(imer Control Re) 132.58 517 T
(gister) 210.4 517 T
(.) 236.4 517 T
(\0501\051) 126 495 T
(Periodic Interrupt:) 144 495 T
0.51 (The Out Signal is initially set to the timer stopped state as determined by the Out) 144 473 P
-0.29 (Signal control of TCR, T) 144 459 P
-0.29 (imer is enabled, Count Enable =1 and Mode =0. When the) 262.75 459 P
1.89 (reload re) 144 445 P
1.89 (gister is written with the reload v) 188.02 445 P
1.89 (alue, the reload v) 357.74 445 P
1.89 (alue is set into the) 445.76 445 P
0.35 (counter) 144 431 P
0.35 (, the counter be) 179.51 431 P
0.35 (gins decrementing, and Out Signal is dri) 254.35 431 P
0.35 (v) 449.78 431 P
0.35 (en to the v) 455.6 431 P
0.35 (alue of) 506.67 431 P
(In) 144 417 T
(v) 153.52 417 T
(ert.) 159.34 417 T
-0.29 (When the counter reaches zero, timeout, the Out Signal changes to) 144 395 P
0 F
-0.29 (NO) 463.73 395 P
-0.29 (T) 481.25 395 P
2 F
-0.29 ( In) 489.26 395 P
-0.29 (v) 501.48 395 P
-0.29 (ert and) 507.3 395 P
0.18 (remains at this le) 144 381 P
0.18 (v) 225.9 381 P
0.18 (el until the counter is read or reload re) 231.72 381 P
0.18 (gister is written.Ho) 416.26 381 P
0.18 (we) 508.64 381 P
0.18 (v) 522.34 381 P
0.18 (er) 528.16 381 P
0.18 (,) 537 381 P
0.22 (the counter is automatically set with the reload v) 144 367 P
0.22 (alue and continues decrementing.) 378.72 367 P
0.42 (When the counter is read or reload re) 144 353 P
0.42 (gister is written, Out Signal returns to In) 325.05 353 P
0.42 (v) 521.52 353 P
0.42 (ert) 527.34 353 P
(le) 144 339 T
(v) 152.36 339 T
(el.) 158.18 339 T
(\0502\051) 126 295 T
(T) 144 295 T
(ime Out Interrupt:) 150.91 295 T
0.85 (This mode dif) 144 273 P
0.85 (fers from Mode 0 at timeout. In Mode 1, the timer halts instead of) 212.72 273 P
0.8 (reloading and decrementing the counter) 144 259 P
0.8 (. Then, when the count re) 337.16 259 P
0.8 (gister is read or) 463.28 259 P
0.72 (the reload re) 144 245 P
0.72 (gister is written, the Out Signal returns to In) 205.23 245 P
0.72 (v) 422.15 245 P
0.72 (ert le) 427.97 245 P
0.72 (v) 452.71 245 P
0.72 (el, the counter is) 458.53 245 P
(set with the reload v) 144 231 T
(alue and be) 241.02 231 T
(gins decrementing ag) 295.49 231 T
(ain,) 398.08 231 T
0 10 Q
(Mode) 203.78 678.33 T
(Operation) 338.05 678.33 T
2 F
(0) 186 658.33 T
(Periodic Interrupt Mode) 258 658.33 T
(1) 186 638.33 T
(T) 258 638.33 T
(imeout Interrupt Mode) 263.76 638.33 T
(2) 186 618.33 T
(Square W) 258 618.33 T
(a) 296.91 618.33 T
(v) 301.15 618.33 T
(e Generator Mode) 306 618.33 T
(3) 186 598.33 T
(Softw) 258 598.33 T
(are T) 281.79 598.33 T
(rigger W) 302.26 598.33 T
(atchdog Mode) 337.28 598.33 T
(4) 186 578.33 T
(External T) 258 578.33 T
(rigger W) 300.14 578.33 T
(atchdog Mode) 335.16 578.33 T
0 12 Q
(T) 236.66 557 T
(able 14:) 243.56 557 T
(T) 286.9 557 T
(imer Operating Modes) 294.68 557 T
180 690.75 180 571.25 2 L
V
0.5 H
0 Z
N
252 691.25 252 570.75 2 L
V
N
468 690.75 468 571.25 2 L
V
N
179.75 691 468.25 691 2 L
V
N
180.25 672.25 467.75 672.25 2 L
V
N
180.25 669.75 467.75 669.75 2 L
V
N
179.75 571 468.25 571 2 L
V
N
FMENDPAGE
%%EndPage: "57" 63
%%Page: "58" 64
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(58) 72 17 T
(5) 387.01 17 T
(Peripheral Extensions) 399.01 17 T
(\0503\051) 90 721 T
(Square W) 108 721 T
(a) 154.69 721 T
(v) 159.78 721 T
(e Generator:) 165.6 721 T
(This mode dif) 108 700 T
(fers from Mode 0 in the transition of Out Signal.) 175.03 700 T
0.51 (The Out Signal is initially set to the timer stopped state as determined by the Out) 108 679 P
-0.29 (Signal control of TCR, T) 108 666 P
-0.29 (imer is enabled, Count Enable =1 and Mode =2. When the) 226.75 666 P
1.89 (reload re) 108 653 P
1.89 (gister is written with the reload v) 152.02 653 P
1.89 (alue, the reload v) 321.74 653 P
1.89 (alue is set into the) 409.76 653 P
0.14 (counter) 108 640 P
0.14 (, the counter be) 143.51 640 P
0.14 (gins decrementing, ho) 220.86 640 P
0.14 (we) 327.16 640 P
0.14 (v) 340.85 640 P
0.14 (er) 346.67 640 P
0.14 (, Out Signal remains at the ini-) 355.51 640 P
(tial v) 108 627 T
(alue.) 132.04 627 T
-0.06 (When the counter decrements to half of reload v) 108 606 P
-0.06 (alue, Out Signal is dri) 339.17 606 P
-0.06 (v) 443.64 606 P
-0.06 (en to In) 449.46 606 P
-0.06 (v) 485.52 606 P
-0.06 (ert) 491.34 606 P
0.26 (v) 108 593 P
0.26 (alue. When counter reaches 0, timeout, Out Signal changes to) 113.7 593 P
0 F
0.26 (NO) 415.26 593 P
0.26 (T) 432.78 593 P
2 F
0.26 ( In) 440.79 593 P
0.26 (v) 453.57 593 P
0.26 (ert v) 459.39 593 P
0.26 (alue.) 481.01 593 P
-0.07 (The counter is set with the reload v) 108 580 P
-0.07 (alue and continues decrementing. After the \336rst) 276.15 580 P
(count sequence, Out Signal will be approximately a square w) 108 567 T
(a) 401.83 567 T
(v) 406.92 567 T
(e.) 412.74 567 T
1.44 (F) 108 546 P
1.44 (or reload v) 114.49 546 P
1.44 (alue =1, Out Signal will be at In) 169.05 546 P
1.44 (v) 332.73 546 P
1.44 (ert and not In) 338.55 546 P
1.44 (v) 406.7 546 P
1.44 (ert le) 412.52 546 P
1.44 (v) 437.98 546 P
1.44 (el one timer) 443.8 546 P
(count c) 108 533 T
(ycle each, with a period of tw) 142.81 533 T
(o timer count c) 284.99 533 T
(ycles.) 357.13 533 T
1.58 (F) 108 512 P
1.58 (or reload v) 114.49 512 P
1.58 (alue =N, N>1, Out Signal will be at In) 169.34 512 P
1.58 (v) 365.7 512 P
1.58 (ert le) 371.52 512 P
1.58 (v) 397.12 512 P
1.58 (el for Int\050N/2\051 timer) 402.94 512 P
1.69 (count c) 108 499 P
1.69 (ycles. Out Signal will be at) 144.51 499 P
0 F
1.69 (NO) 287.66 499 P
1.69 (T) 305.18 499 P
2 F
1.69 ( In) 313.18 499 P
1.69 (v) 327.39 499 P
1.69 (ert le) 333.21 499 P
1.69 (v) 358.93 499 P
1.69 (el for Int\050\050N) 364.75 499 P
8 F
1.69 (+) 426.78 499 P
2 F
1.69 (1\051/2\051) 433.37 499 P
8 F
1.69 (+) 461.39 499 P
2 F
1.69 (1 timer) 467.98 499 P
(count c) 108 486 T
(ycles. The period will be N) 142.81 486 T
8 F
(+) 273.46 486 T
2 F
(1 timer count c) 280.04 486 T
(ycles.) 352.19 486 T
(\0504\051) 90 465 T
(Softw) 108 465 T
(are T) 136.55 465 T
(rigger W) 161.11 465 T
(atchdog:) 203.14 465 T
0.51 (The Out Signal is initially set to the timer stopped state as determined by the Out) 108 444 P
0.76 (Signal control of TCR, T) 108 431 P
0.76 (imer is enabled, Count Enable =1 and Mode = 3. When) 230.94 431 P
0.59 (the reload re) 108 418 P
0.59 (gister is written with the reload v) 168.98 418 P
0.59 (alue, the reload v) 330.86 418 P
0.59 (alue is set into the) 414.98 418 P
0.35 (counter) 108 405 P
0.35 (, the counter be) 143.51 405 P
0.35 (gins decrementing, and Out Signal is dri) 218.35 405 P
0.35 (v) 413.78 405 P
0.35 (en to the v) 419.6 405 P
0.35 (alue of) 470.67 405 P
(In) 108 392 T
(v) 117.52 392 T
(ert.) 123.34 392 T
0.3 (When counter = 0, timeout, Out Signal changes to not In) 108 371 P
0.3 (v) 382.63 371 P
0.3 (ert v) 388.45 371 P
0.3 (alue and remains at) 410.11 371 P
0.32 (this v) 108 358 P
0.32 (alue. The timer halts. Ho) 134.36 358 P
0.32 (we) 254.64 358 P
0.32 (v) 268.33 358 P
0.32 (er) 274.15 358 P
0.32 (, writing to the reload re) 283 358 P
0.32 (gister before timeout,) 400.38 358 P
(updates the counter with the reload v) 108 345 T
(alue and delays timeout.) 285 345 T
-0.23 (After the timer halts, it can be restarted by writing to the reload re) 108 324 P
-0.23 (gister) 420.8 324 P
-0.23 (. The reload) 446.81 324 P
(v) 108 311 T
(alue is set into counter and the w) 113.7 311 T
(atchdog count restarts.) 271.22 311 T
(\0505\051) 90 290 T
(Hardw) 108 290 T
(are T) 140.53 290 T
(rigger W) 165.1 290 T
(atchdog:) 207.12 290 T
0.51 (The Out Signal is initially set to the timer stopped state as determined by the Out) 108 269 P
-0.01 (Signal control of TCR, T) 108 256 P
-0.01 (imer is enabled, Count Enable =1 and Mode =4. Then the) 227.89 256 P
(reload re) 108 243 T
(gister is written with the reload v) 150.13 243 T
(alue.) 308.48 243 T
0.82 (When a trigger e) 108 222 P
0.82 (v) 190.47 222 P
0.82 (ent occurs at In Signal, the reload v) 196.29 222 P
0.82 (alue is set into the counter) 371.72 222 P
0.82 (,) 501 222 P
(the counter be) 108 209 T
(gins decrementing, and Out Signal is dri) 175.8 209 T
(v) 369.16 209 T
(en to the v) 374.98 209 T
(alue of In) 425 209 T
(v) 470.51 209 T
(ert.) 476.33 209 T
0.44 (When counter = 0, timeout, Out Signal changes to) 108 188 P
0 F
0.44 (NO) 355.71 188 P
0.44 (T) 373.23 188 P
2 F
0.44 ( In) 381.23 188 P
0.44 (v) 394.19 188 P
0.44 (ert v) 400.01 188 P
0.44 (alue and remains) 421.81 188 P
0.55 (at this v) 108 175 P
0.55 (alue and the timer halts. Ho) 146.8 175 P
0.55 (we) 281.9 175 P
0.55 (v) 295.59 175 P
0.55 (er) 301.41 175 P
0.55 (, occurrences of another trigger e) 310.25 175 P
0.55 (v) 471.3 175 P
0.55 (ent at) 477.12 175 P
-0.08 (In Signal before timeout, updates the counter with the reload v) 108 162 P
-0.08 (alue and delays tim-) 407.24 162 P
(eout.) 108 149 T
0.16 (The timer is restarted after halting at timeout by another trigger e) 108 128 P
0.16 (v) 421.71 128 P
0.16 (ent at In Signal.) 427.53 128 P
0.63 (The In Signal trigger e) 108 115 P
0.63 (v) 218.86 115 P
0.63 (ent is determined by the Ev) 224.68 115 P
0.63 (ent \336eld in TCR and can be a) 359.29 115 P
(rising edge, f) 108 102 T
(alling edge or both.) 170.87 102 T
FMENDPAGE
%%EndPage: "58" 64
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(6) 108 17 T
(Diagnostic Facilities) 120 17 T
(59) 528 17 T
4 14 Q
(6 Diagnostic F) 243.51 623.67 T
(acilities) 346.68 623.67 T
0 12 Q
(6.1 Intr) 108 579 T
(oduction) 152.45 579 T
2 F
-0.21 (As an option, a V8E SP) 108 557 P
-0.21 (ARC can be equipped with a Deb) 219.87 557 P
-0.21 (ug Support Unit \050DSU\051. This unit) 379.69 557 P
(pro) 108 543 T
(vides functions such as) 123.82 543 T
(\245 setting hardw) 144 521 T
(are breakpoints on instruction and data, on address and v) 216.07 521 T
(alue;) 488.39 521 T
(\245 single stepping;) 144 499 T
(\245 instruction trace generation;) 144 477 T
(\245 reading and writing of on chip re) 144 455 T
(gisters;) 308.99 455 T
(\245 emulation.) 144 433 T
(The) 108 411 T
(y are detailed in the subsequent sections of this chapter) 126.48 411 T
(.) 390.11 411 T
1.56 (T) 108 389 P
1.56 (w) 114.37 389 P
1.56 (o implementations with dif) 122.92 389 P
1.56 (ferent emphasis are de\336ned. Both support the abo) 256.96 389 P
1.56 (v) 505.65 389 P
1.56 (e fea-) 511.47 389 P
(tures. The) 108 375 T
(y are:) 155.81 375 T
(\245 a trace enhancing implementation) 144 353 T
(\245 a pin ef) 144 331 T
(fecti) 186.89 331 T
(v) 207.91 331 T
(e implementation.) 213.73 331 T
0 F
(6.1.1 The trace enhancing implementation.) 108 287 T
2 F
0.4 (This implementation mak) 108 265 P
0.4 (es use of a number of e) 232.01 265 P
0.4 (xtra pins to allo) 345.51 265 P
0.4 (w a suf) 421.4 265 P
0.4 (\336cient number of) 456.55 265 P
1.85 (instruction address bits per SP) 108 251 P
1.85 (ARC instruction to reconstruct a full address trace. The) 259.61 251 P
0.94 (same pins are used to control the further diagnostic features introduced abo) 108 237 P
0.94 (v) 479.05 237 P
0.94 (e and to be) 484.87 237 P
1.1 (detailed in the subsequent sections of this chapter) 108 223 P
1.1 (. Implementor de\336ned further features) 352.66 223 P
1.29 (may be added to this implementation; these further features are not subject of the V8E) 108 209 P
(speci\336cation.) 108 195 T
0 F
(6.1.2) 108 151 T
(The pin effecti) 144 151 T
(v) 217.87 151 T
(e implementation.) 223.75 151 T
2 F
1.91 (This implementation relies an a JT) 108 129 P
1.91 (A) 282.74 129 P
1.91 (G interf) 290.92 129 P
1.91 (ace for control as well as for information) 330.37 129 P
0.42 (transport to and from the DSU and for control as well as for information transport to and) 108 115 P
(from an) 108 101 T
(y further features that can be reached via the DSU.) 145.48 101 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(60) 72 17 T
(6) 393 17 T
(Diagnostic Facilities) 405 17 T
1.06 (This implementation also relies hea) 72 721 P
1.06 (vily on DMA; using JT) 246.66 721 P
1.06 (A) 361.81 721 P
1.06 (G and DMA it allo) 369.99 721 P
1.06 (ws soft-) 464.61 721 P
0.16 (w) 72 707 P
0.16 (are independent access to all DSU functions described in the subsequent sections. Since) 80.54 707 P
0.55 (the JT) 72 693 P
0.55 (A) 101.1 693 P
0.55 (G, in this implementation, is a DMA master and the DSU is a DMA sla) 109.28 693 P
0.55 (v) 459.42 693 P
0.55 (e, it can) 465.24 693 P
1.91 (not only reach the DSU functions speci\336ed here and an) 72 679 P
1.91 (y implementor de\336ned further) 353.96 679 P
0.46 (DSU functions b) 72 665 P
0.46 (ut also: - an) 153.35 665 P
0.46 (y \050further\051 DMA mapped sources and destinations, on or of) 210.88 665 P
0.46 (f) 500 665 P
0.58 (chip; - an) 72 651 P
0.58 (y \050further\051 ASI mapped sources and destinations, on or of) 118.31 651 P
0.58 (f chip; - an) 399.88 651 P
0.58 (y \050further\051) 453.77 651 P
-0.06 (memory mapped sources and destinations, on or of) 72 637 P
-0.06 (f chip, e.g. . on chip or of) 315.92 637 P
-0.06 (f chip RAM; .) 436.85 637 P
0.28 (on chip or of) 72 623 P
0.28 (f chip R) 134.21 623 P
0.28 (OM. Ob) 172.96 623 P
0.28 (viously) 213.06 623 P
0.28 (, all of the abo) 247.62 623 P
0.28 (v) 317.57 623 P
0.28 (e, being mapped on space that can be) 323.39 623 P
(reached via softw) 72 609 T
(are, can also be read, written and controlled via softw) 156.52 609 T
(are.) 413.33 609 T
2.04 (Unlik) 72 587 P
2.04 (e con) 99.22 587 P
2.04 (v) 126.43 587 P
2.04 (entional deb) 132.25 587 P
2.04 (uggers, this implementation can be used before system I/O is) 193.04 587 P
-0.14 (a) 72 573 P
-0.14 (v) 77.09 573 P
-0.14 (ailable to e.g. load RAM; to access internal address and data b) 82.79 573 P
-0.14 (uses and to break-point or) 379.92 573 P
(single-step through code sequences.) 72 559 T
0 F
(6.2 List of featur) 72 515 T
(es) 163.1 515 T
2 F
0.09 (The follo) 72 493 P
0.09 (wing features will be detailed in subsequent detailed sections in a ne) 116.11 493 P
0.09 (xt release of) 445.18 493 P
(this spec.) 72 479 T
(\321) 90 457 T
(BREAK:) 108 457 T
9 10 Q
(\245) 108 437 T
3 12 Q
(HARDW) 114 437 T
(ARE BREAK) 161.83 437 T
2 F
(INSTR) 144 415 T
(UCTION ADDRESS MA) 178.19 415 T
(TCH BREAK) 302.18 415 T
(D) 144 393 T
(A) 152.18 393 T
(T) 159.52 393 T
(A ADDRESS AND D) 165.73 393 T
(A) 272.24 393 T
(T) 279.58 393 T
(A MA) 285.79 393 T
(TCH BREAK) 315.46 393 T
(DSU Re) 144 371 T
(gister Write Exception Break) 184.15 371 T
(DSU Re) 144 349 T
(gister Read/Write Exception Break) 184.15 349 T
(External \050-EMU_BRK Pin\051 Break) 144 327 T
(Hardw) 144 305 T
(are Break Request) 176.53 305 T
9 10 Q
(\245) 108 285 T
3 12 Q
(Softw) 114 285 T
(are Break) 145.34 285 T
2 F
(Hardw) 144 263 T
(are/Softw) 176.53 263 T
(are Break Request Disable) 223.07 263 T
(Ret-Break \050Return from Break\051) 144 241 T
(Disable_match_match \337ag) 144 219 T
(T) 144 197 T
(rap_Disabled_Break_Point) 150.91 197 T
(Break on RETT) 144 175 T
(\321) 90 153 T
(Single Step:) 108 153 T
9 10 Q
(\245) 108 133 T
3 12 Q
(Single Step general beha) 114 133 T
(vior) 252.13 133 T
9 10 Q
(\245) 108 113 T
3 12 Q
(Single Step beha) 114 113 T
(vior over trap) 207.24 113 T
9 10 Q
(\245) 108 93 T
3 12 Q
(Single Step beha) 114 93 T
(vior on RETT) 207.24 93 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
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[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(6) 108 17 T
(Diagnostic Facilities) 120 17 T
(61) 528 17 T
(\321) 126 721 T
(ICE Port:) 144 721 T
(\321) 126 699 T
(Deb) 144 699 T
(ug Mode and State:) 163.75 699 T
(\321) 126 677 T
(Instruction T) 144 677 T
(race) 205.91 677 T
(\321) 126 655 T
(DSU re) 144 655 T
(gisters:) 180.14 655 T
(Ob) 144 641 T
(viously) 158.48 641 T
(, the DSU re) 193.04 641 T
(gister sets of the tw) 252.85 641 T
(o implementations are not identical.) 346.06 641 T
FMENDPAGE
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[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(62) 72 17 T
(6) 393 17 T
(Diagnostic Facilities) 405 17 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(63) 528 17 T
0 14 Q
(Annex A Pr) 215.3 623.67 T
(ogramming T) 292.82 623.67 T
(echniques) 373.58 623.67 T
2 12 Q
(\050Informati) 291.92 601 T
(v) 340.94 601 T
(e\051) 346.76 601 T
0 F
(A.1 Ov) 108 557 T
(er) 149.88 557 T
(view) 160.42 557 T
2 F
1.2 (This section pro) 108 535 P
1.2 (vides information to assist in programming the SP) 187.54 535 P
1.2 (ARC-V8E embedded) 435.82 535 P
3.54 (processor) 108 521 P
3.54 (. It co) 153.32 521 P
3.54 (v) 187.87 521 P
3.54 (ers the additional instructions, Di) 193.69 521 P
3.54 (vide Step and Scan, pro) 367.19 521 P
3.54 (vided by) 494.8 521 P
0.22 (SP) 108 507 P
0.22 (ARC-V8E. Code fragments are pro) 120.24 507 P
0.22 (vided to illustrate the use of these instructions. This) 290.58 507 P
3.33 (section presumes f) 108 493 P
3.33 (amiliarity with the SP) 203.86 493 P
3.33 (ARC-V8 Programmer\325) 317.77 493 P
3.33 (s Model and SP) 430.76 493 P
3.33 (ARC) 515.33 493 P
(assembly language as speci\336ed in) 108 479 T
307.98 477.8 272.98 477.8 2 L
V
0.6 H
0 Z
N
(The SP) 272.98 479 T
448.85 477.8 306.88 477.8 2 L
V
N
(ARC Architecture Manual, V) 306.88 479 T
485.84 477.8 447.52 477.8 2 L
V
N
(ersion 8) 447.52 479 T
(.) 485.84 479 T
0 F
(A.2 Di) 108 435 T
(vision P) 146.54 435 T
(erf) 186.65 435 T
(ormance Using DIVScc) 201 435 T
(A.2.1 di) 108 391 T
(vs1 - di) 153.55 391 T
(vide signed, 1 w) 190.1 391 T
(ord di) 270.66 391 T
(vidend) 301.55 391 T
2 F
-0.2 (Signed di) 108 369 P
-0.2 (vision of 32 bit di) 153.17 369 P
-0.2 (vidend by 32 bit di) 237.41 369 P
-0.2 (visor produces a signed 32 bit quotient and a) 326.97 369 P
-0.24 (signed 32 bit remainder \050same sign as di) 108 355 P
-0.24 (vidend or zero if e) 299.68 355 P
-0.24 (xact\051. Since the only o) 386.53 355 P
-0.24 (v) 493.05 355 P
-0.24 (er\337o) 498.87 355 P
-0.24 (w is) 520.57 355 P
0.05 (di) 108 341 P
0.05 (vide by zero, this routine does not check for di) 117.04 341 P
0.05 (vide by zero, lea) 340.48 341 P
0.05 (ving it up to caller to test) 419.7 341 P
1.07 (and abort just after the call. Di) 108 327 P
1.07 (vision without f) 260.45 327 P
1.07 (ault tak) 338.48 327 P
1.07 (es 47 to 58 c) 375.1 327 P
1.07 (ycles assuming each) 439.87 327 P
(instruction tak) 108 313 T
(es one c) 176.88 313 T
(ycle, e) 215.35 313 T
(xcept) 246.49 313 T
13 10 Q
(retl) 275.48 313 T
2 12 Q
(which tak) 305.48 313 T
(es tw) 352.36 313 T
(o.) 377.23 313 T
13 10 Q
(!DIVISION SUBROUTINE - DIVS1) 108 288.33 T
-0.5 (!This subroutine for signed division of 32 bit dividend by 32 bit divisor) 108 276.33 P
(!produces 32 bit signed quotient and 32 bit remainder using divide) 108 264.33 T
(!step instruction. Remainder is zero if division is exact) 108 252.33 T
(!or same sign as original dividend if not. There is no check for divide) 108 240.33 T
(!by zero. It is not possible to overflow with non zero divisor. If the) 108 228.33 T
(!calling routine knows that divide by zero cannot happen, no test is) 108 216.33 T
-0.46 (!needed. If divide by zero is possible, a simple test just after the call) 108 204.33 P
(!can abort the division. Division without fault takes 47 to 58 cycles.) 108 192.33 T
(!Exact division with last partial remainder =0 takes 47 cycles. Exact) 108 180.33 T
(!division with last partial remainder = +/-divisor, as happens with) 108 168.33 T
(!non-restoring division algorithms, takes 51 or 52 cycles.Inexact) 108 156.33 T
(!division, with non-zero final remainder, takes 54 to 58 cycles.) 108 144.33 T
(!call so:) 108 120.33 T
(!) 108 108.33 T
(mov %l1,%o0) 135 108.33 T
(!dvdnd->o0) 201 108.33 T
(!) 108 96.33 T
(orcc %g0,%l2,%o2) 135 96.33 T
(!dvsr->o2 & test) 231 96.33 T
(!) 108 84.33 T
(call divs1) 135 84.33 T
(!DIVISION SUBROUTINE CALL) 195 84.33 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(64) 72 17 T
13 10 Q
(!) 72 722.33 T
(be dvby0) 99 722.33 T
(!abort division if divide by zero) 153 722.33 T
(!) 72 710.33 T
(! Register Map) 72 698.33 T
(!reg#) 72 686.33 T
(!out0) 72 674.33 T
( dividend/remainder) 102 674.33 T
(!out1) 72 662.33 T
( quotient) 102 662.33 T
(!out2) 72 650.33 T
( divisor) 102 650.33 T
(!out4) 72 638.33 T
( scratch for final remainder calculations) 102 638.33 T
(!out5) 72 626.33 T
( absolute value of divisor) 102 626.33 T
(!y) 72 614.33 T
-0.2 (initially sign extension of dividend/successive partial remainders) 105 614.33 S
(!call to divs1 must be made with cc indicating sign of divisor) 72 602.33 T
(!) 72 590.33 T
(.global divs1) 72 578.33 T
(divs1:) 72 566.33 T
(mov %g0,%y) 108 566.33 T
(!0 -> Y) 168 566.33 T
(mov %o2,%o5) 99 554.33 T
(!copy divisor in o5, D) 165 554.33 T
(bl,a 1f) 99 542.33 T
(sub %g0,%o5,%o5) 99 530.33 T
(!if divsr neg, D=-divsr) 189 530.33 T
(1:) 72 518.33 T
(tst %o0) 99 518.33 T
(!initialize cc for first divide step) 153 518.33 T
(!with sign dividend for signed divide) 153 506.33 T
(bl,a 2f) 99 494.33 T
(mov -1,%y) 99 482.33 T
(!-1 -> Y only if dvdnd neg) 153 482.33 T
(2:) 72 470.33 T
(divscc %o0,%o5,%o1) 99 470.33 T
(!divide step 1) 207 470.33 T
(!leave original dividend in o0) 72 458.33 T
(!do partial remainders & quotient in o1) 72 446.33 T
(!don\325t change cc except by divscc until last divide step done) 72 434.33 T
(divscc %o1,%o5,%o1) 99 422.33 T
(!divide step 2) 207 422.33 T
(divscc %o1,%o5,%o1) 99 410.33 T
(divscc %o1,%o5,%o1) 99 398.33 T
(divscc %o1,%o5,%o1) 99 386.33 T
(divscc %o1,%o5,%o1) 99 374.33 T
(divscc %o1,%o5,%o1) 99 362.33 T
(divscc %o1,%o5,%o1) 99 350.33 T
(divscc %o1,%o5,%o1) 99 338.33 T
(divscc %o1,%o5,%o1) 99 326.33 T
(divscc %o1,%o5,%o1) 99 314.33 T
(divscc %o1,%o5,%o1) 99 302.33 T
(divscc %o1,%o5,%o1) 99 290.33 T
(divscc %o1,%o5,%o1) 99 278.33 T
(divscc %o1,%o5,%o1) 99 266.33 T
(divscc %o1,%o5,%o1) 99 254.33 T
(divscc %o1,%o5,%o1) 99 242.33 T
(divscc %o1,%o5,%o1) 99 230.33 T
(divscc %o1,%o5,%o1) 99 218.33 T
(divscc %o1,%o5,%o1) 99 206.33 T
(divscc %o1,%o5,%o1) 99 194.33 T
(divscc %o1,%o5,%o1) 99 182.33 T
(divscc %o1,%o5,%o1) 99 170.33 T
(divscc %o1,%o5,%o1) 99 158.33 T
(divscc %o1,%o5,%o1) 99 146.33 T
(divscc %o1,%o5,%o1) 99 134.33 T
(divscc %o1,%o5,%o1) 99 122.33 T
(divscc %o1,%o5,%o1) 99 110.33 T
(divscc %o1,%o5,%o1) 99 98.33 T
(divscc %o1,%o5,%o1) 99 86.33 T
FMENDPAGE
%%EndPage: "64" 70
%%Page: "65" 71
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(65) 528 17 T
13 10 Q
(divscc %o1,%o5,%o1) 135 722.33 T
(divscc %o1,%o5,%o1) 135 710.33 T
(!divide step 32) 243 710.33 T
(be 6f) 135 698.33 T
(!if final remainder is zero,) 189 698.33 T
(!go fix quotient polarity) 189 686.33 T
(mov %y, %o4) 135 674.33 T
(!final remainder from Y to o4) 207 674.33 T
(bg 4f) 135 662.33 T
(!skip ahead if rmdr+; continue if rmdr-) 189 662.33 T
(addcc %o4,%o5,%g0) 135 650.33 T
(!is neg rmdr + abs divsr =0) 243 650.33 T
(mov %g0,%o4) 135 638.33 T
(!clear rmdr. if not, don\325t clear) 201 638.33 T
(tst %o0) 135 626.33 T
(!test original dvdnd) 189 626.33 T
(bl 5f) 135 614.33 T
(!if neg, go check neg Q) 189 614.33 T
(tst %o1) 135 602.33 T
(!sign Q) 189 602.33 T
(ba 5f) 135 590.33 T
(add %o4,%o5,%o4) 135 578.33 T
(!if orig dvdnd pos and final rmdr neg,) 225 578.33 T
(!correct rmdr; then go check neg Q) 189 566.33 T
(4:) 108 554.33 T
(subcc %o4,%o5,%g0) 135 554.33 T
(!is pos rmdr - abs divsr =0) 243 554.33 T
(be,a 6f) 135 542.33 T
(!if so, go fix quotient polarity and) 189 542.33 T
(mov %g0,%o4) 135 530.33 T
(!clear rmdr. if not, don\325t clear) 201 530.33 T
(tst %o0) 135 518.33 T
(!test original dvdnd) 189 518.33 T
(bge 5f) 135 506.33 T
(!if pos, go check neg Q) 189 506.33 T
(tst %o1) 135 494.33 T
(!sign Q) 189 494.33 T
(sub %o4,%o5,%o4) 135 482.33 T
(!if orig dvdnd neg and final rmdr pos,) 225 482.33 T
(!correct rmdr; then go check neg Q) 189 470.33 T
(5:) 108 458.33 T
(bl,a 6f) 135 458.33 T
(!skip ahead if Q pos) 189 458.33 T
(add %o1,1,%o1) 135 446.33 T
(!if neg Q, 1\325s complement to) 213 446.33 T
(!2\325s complement; annul if pos Q) 189 434.33 T
(6:) 108 422.33 T
(tst %o2) 135 422.33 T
(!check original divisor sign) 189 422.33 T
(bl,a 7f) 135 410.33 T
(sub %g0,%o1,%o1) 135 398.33 T
(!if neg divsr, negate quotient) 225 398.33 T
(7:) 108 386.33 T
(retl) 135 386.33 T
(!exit) 189 386.33 T
(mov %o4,%o0) 135 374.33 T
(!with correct remainder in o0) 201 374.33 T
0 12 Q
(A.2.2 di) 108 331 T
(vs2 - di) 153.55 331 T
(vide signed, 2 w) 190.1 331 T
(ord di) 270.66 331 T
(vidend) 301.55 331 T
2 F
0.5 (Signed di) 108 309 P
0.5 (vision of a 64 bit di) 153.88 309 P
0.5 (vidend by a 32 bit di) 249.77 309 P
0.5 (visor produces a signed 32 bit quotient) 350.99 309 P
1.07 (and a signed 32 bit remainder with the same sign as di) 108 295 P
1.07 (vidend or zero if e) 379.81 295 P
1.07 (xact. Di) 471.89 295 P
1.07 (vision) 510.66 295 P
-0.29 (with di) 108 281 P
-0.29 (vide by zero f) 141.08 281 P
-0.29 (ault tak) 206.39 281 P
-0.29 (es 6 c) 241.64 281 P
-0.29 (ycles. Di) 268.2 281 P
-0.29 (vision with non zero di) 310.27 281 P
-0.29 (visor o) 419.46 281 P
-0.29 (v) 451.99 281 P
-0.29 (er\337o) 457.81 281 P
-0.29 (w f) 479.51 281 P
-0.29 (ault tak) 494.75 281 P
-0.29 (es) 530 281 P
-0.27 (17 to 23 c) 108 267 P
-0.27 (ycles. Di) 154.67 267 P
-0.27 (vision without f) 196.76 267 P
-0.27 (ault tak) 272.11 267 P
-0.27 (es 49 to 60 c) 307.38 267 P
-0.27 (ycles. This assumes each instruction) 366.77 267 P
(tak) 108 253 T
(es one c) 122.54 253 T
(ycle e) 161.02 253 T
(xcept) 189.16 253 T
13 10 Q
(retl) 218.15 253 T
2 12 Q
( which tak) 242.15 253 T
(es tw) 292.02 253 T
(o.) 316.9 253 T
13 10 Q
(!DIVISION SUBROUTINE - DIVS2 REVA) 108 228.33 T
-0.5 (!This subroutine for signed division of 64 bit dividend by 32 bit divisor) 108 216.33 P
(!produces 32 bit signed quotient and 32 bit remainder using divide) 108 204.33 T
(!step instruction. Special treatment is given to borderline overflow) 108 192.33 T
(!with absolute value quotient = 2^31 to support math operator INTEGER) 108 180.33 T
(!PART OF: Q=-2^31 does not overflow; Q=+2^31 overflows as before but) 108 168.33 T
(!with different overflow code. Remainder is zero if division is exact) 108 156.33 T
(!or same sign as original dividend if not. There is a check for divide) 108 144.33 T
-0.5 (!by zero and a check for overflow with non-zero divisor. Check for divide) 108 132.33 P
(!by zero is kept separate to support possible SUN recommended trap for) 108 120.33 T
(!divide by zero. In applications where user knows numerical ranges or) 108 108.33 T
-0.55 (!controls them, these checks can be omitted. Division with divide by zero) 108 96.33 P
(!fault takes 6 cycles; sets overflow flag in condition code; leaves) 108 84.33 T
FMENDPAGE
%%EndPage: "65" 71
%%Page: "66" 72
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(66) 72 17 T
13 10 Q
(!0xfffff800 in register out3. Division with non-zero divisor overflow) 72 722.33 T
(!takes 17 to 23 cycles \05017 or 19 if original dividend plus, 18 or 23 if) 72 710.33 T
(!original dividend minus\051; sets overflow flag in condition code; leaves) 72 698.33 T
(!0x800 in register out3. Division leading to absolute value quotient =) 72 686.33 T
(!2^31 takes 20 cycles if original dividend plus, 23 cycles if original) 72 674.33 T
(!dividend minus. It leaves correct remainder in register out0, -2^31 in) 72 662.33 T
-0.46 (!out1 as quotient and 0 in out3. It clears overflow cc if actual quotient) 72 650.33 P
(!is -2^31 and sets overflow cc if actual quotient is +2^31. Division) 72 638.33 T
(!without fault takes 49 to 60 cycles; clears overflow flag in condition) 72 626.33 T
(!code; leaves 0 in register out3. Exact division with last partial) 72 614.33 T
(!remainder =0 takes 49 cycles. Exact division with last partial) 72 602.33 T
(!remainder=+/-divisor, as happens with non-restoring division) 72 590.33 T
-0.6 (!algorithms, takes 53 or 54 cycles. Inexact division, with non-zero final) 72 578.33 P
(!remainder, takes 56 to 60 cycles.) 72 566.33 T
(!call so:) 72 554.33 T
(!) 72 542.33 T
(mov %l0,%o0) 99 542.33 T
( !msh dvdnd->o0) 165 542.33 T
(!) 72 530.33 T
(mov %l1,%o1) 99 530.33 T
( !lsh dvdnd->o1) 165 530.33 T
(!) 72 518.33 T
(call divs2) 99 518.33 T
( !DIVISION SUBROUTINE CALL) 159 518.33 T
(!) 72 506.33 T
(orcc %g0,%l2,%o2) 99 506.33 T
( !dvsr->o2 & test) 195 506.33 T
(!) 72 494.33 T
(!Register Map) 72 482.33 T
(!reg#) 72 470.33 T
(!out0) 72 458.33 T
(msh dividend/remainder) 126 458.33 T
(!out1) 72 446.33 T
(lsh dividend/quotient) 126 446.33 T
(!out2) 72 434.33 T
(divisor) 126 434.33 T
(!out3) 72 422.33 T
(overflow indication) 126 422.33 T
(!overflow) 72 410.33 T
(divide by zero/0xfffff800 and V=1) 126 410.33 T
(!overflow) 72 398.33 T
(divide by non-zero/0x800 and V=1) 126 398.33 T
(!overflow) 72 386.33 T
(quotient =+2^31/0 and V=1) 126 386.33 T
(!no overflow/0 and V=0) 72 374.33 T
(!out4) 72 362.33 T
(scratch for final remainder calculations) 126 362.33 T
(!out5) 72 350.33 T
(absolute value of divisor) 126 350.33 T
(!y) 72 338.33 T
(msh dividend/successive partial remainders) 126 338.33 T
(!call to divs2 must be made with cc indicating sign of divisor) 72 326.33 T
(!) 72 314.33 T
(.global divs2) 72 302.33 T
(divs2:) 72 290.33 T
(bne 0f) 108 290.33 T
(!go on if divisor not zero) 153 290.33 T
(mov %o2,%o5) 99 278.33 T
(!copy divisor in o5, D) 165 278.33 T
(sethi 0x1fffff,%o3) 99 266.33 T
(!divide by zero indicator) 207 266.33 T
(retl) 99 254.33 T
(!exit with) 153 254.33 T
(addcc %o3,%o3,%o3) 99 242.33 T
( !overflow set) 201 242.33 T
(0:) 72 230.33 T
(bl,a 1f) 99 230.33 T
(sub %g0,%o5,%o5) 99 218.33 T
(!if divsr neg, D=-divsr) 189 218.33 T
(1:) 72 206.33 T
(mov %o0,%y) 99 206.33 T
(!msh dvdnd->Y) 159 206.33 T
(tst %o0) 99 194.33 T
(!initialize cc for first divide step) 153 194.33 T
(!with sign dividend for signed divide) 153 182.33 T
(bl 2f) 99 170.33 T
(!skip ahead for negative dividend) 153 170.33 T
(divscc %o1,%o5,%o1) 99 158.33 T
(!divide step 1) 207 158.33 T
(!don\325t change cc except by divscc until last divide step done) 72 146.33 T
(bl 3f) 99 134.33 T
(!ok if different) 153 134.33 T
(mov %g0,%o3) 99 122.33 T
(!clear overflow indicator) 165 122.33 T
(srl %o1,1,%o4) 99 110.33 T
(!get lsh rmdr) 177 110.33 T
(bg 8f) 99 98.33 T
(!if msh rmdr >0 then overflow) 153 98.33 T
(subcc %o4,%o5,%g0) 99 86.33 T
(!if lsh rmdr <D then Q is +/-2^31) 201 86.33 T
FMENDPAGE
%%EndPage: "66" 72
%%Page: "67" 73
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(67) 528 17 T
13 10 Q
(bge 8f) 135 722.33 T
(!& o4 is correct final rmdr) 189 722.33 T
(!check if overflow on Q = +2^31) 189 710.33 T
(sethi 0x200000,%o1) 135 698.33 T
(!set -2^31 -> Q) 243 698.33 T
(!else overflow) 189 686.33 T
(tst %o2) 135 674.33 T
(!if original divisor >0) 189 674.33 T
(bg,a 9f) 135 662.33 T
(!which implies quotient =+2^31) 189 662.33 T
(addcc %o1,%o1,%g0) 135 650.33 T
(!set ovrlfw cc with o3 = 0) 237 650.33 T
(9:) 108 638.33 T
(retl) 135 638.33 T
(!exit) 189 638.33 T
(mov %o4,%o0) 135 626.33 T
(!with correct remainder in o0) 201 626.33 T
(8:) 108 614.33 T
(sethi 0x200001,%o3) 135 614.33 T
(!overflow divide by non-zero indicator) 243 614.33 T
(retl) 135 602.33 T
(!exit with) 189 602.33 T
(addcc %o3,%o3,%o3) 135 590.33 T
( !overflow set) 237 590.33 T
(2:) 108 578.33 T
(bge 3f) 135 578.33 T
(!ok if different) 189 578.33 T
(mov %g0,%o3) 135 566.33 T
(!clear overflow indicator) 201 566.33 T
(mov %y,%o0) 135 554.33 T
(!get msh rmdr) 195 554.33 T
(addcc %o0,1,%g0) 135 542.33 T
(!is it -1) 225 542.33 T
(bne 8f) 135 530.33 T
(!if <-1 then overflow) 189 530.33 T
(srl %o1,1,%o4) 135 518.33 T
(!get lsh rmdr except for leading 1) 213 518.33 T
(sethi 0x200000,%o1) 135 506.33 T
(!set -2^31 ->Q) 243 506.33 T
(or %o1,%o4,%o4) 135 494.33 T
(!insert leading 1 in lsh rmdr) 219 494.33 T
(addcc %o4,%o5,%g0) 135 482.33 T
(!if lsh rmdr >-D then q is +/-2^31) 237 482.33 T
(ble 8f) 135 470.33 T
(!& o4 is correct final rmdr) 189 470.33 T
(!check if overflow on Q = +2^31) 189 458.33 T
(!else overflow) 189 446.33 T
(tst %o2) 135 434.33 T
(!if original divisor <0) 189 434.33 T
(bl,a 9f) 135 422.33 T
(!which implies quotient =+2^31) 189 422.33 T
(addcc %o1,%o1,%g0) 135 410.33 T
(!set ovrlfw cc with o3 = 0) 237 410.33 T
(9:) 108 398.33 T
(retl) 135 398.33 T
(!exit) 189 398.33 T
(mov %o4,%o0) 135 386.33 T
(!with correct remainder in o0) 201 386.33 T
(8:) 108 374.33 T
(sethi 0x200001,%o3) 135 374.33 T
( !overflow divide by non-zero indicator) 243 374.33 T
(retl) 135 362.33 T
(!exit with) 189 362.33 T
(addcc %o3,%o3,%o3) 135 350.33 T
(!overflow set) 237 350.33 T
(3:) 108 338.33 T
(divscc %o1,%o5,%o1) 135 338.33 T
(!divide step 2) 243 338.33 T
(divscc %o1,%o5,%o1) 135 326.33 T
(divscc %o1,%o5,%o1) 135 314.33 T
(divscc %o1,%o5,%o1) 135 302.33 T
(divscc %o1,%o5,%o1) 135 290.33 T
(divscc %o1,%o5,%o1) 135 278.33 T
(divscc %o1,%o5,%o1) 135 266.33 T
(divscc %o1,%o5,%o1) 135 254.33 T
(divscc %o1,%o5,%o1) 135 242.33 T
(divscc %o1,%o5,%o1) 135 230.33 T
(divscc %o1,%o5,%o1) 135 218.33 T
(divscc %o1,%o5,%o1) 135 206.33 T
(divscc %o1,%o5,%o1) 135 194.33 T
(divscc %o1,%o5,%o1) 135 182.33 T
(divscc %o1,%o5,%o1) 135 170.33 T
(divscc %o1,%o5,%o1) 135 158.33 T
(divscc %o1,%o5,%o1) 135 146.33 T
(divscc %o1,%o5,%o1) 135 134.33 T
(divscc %o1,%o5,%o1) 135 122.33 T
(divscc %o1,%o5,%o1) 135 110.33 T
(divscc %o1,%o5,%o1) 135 98.33 T
(divscc %o1,%o5,%o1) 135 86.33 T
FMENDPAGE
%%EndPage: "67" 73
%%Page: "68" 74
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(68) 72 17 T
13 10 Q
(divscc %o1,%o5,%o1) 99 722.33 T
(divscc %o1,%o5,%o1) 99 710.33 T
(divscc %o1,%o5,%o1) 99 698.33 T
(divscc %o1,%o5,%o1) 99 686.33 T
(divscc %o1,%o5,%o1) 99 674.33 T
(divscc %o1,%o5,%o1) 99 662.33 T
(divscc %o1,%o5,%o1) 99 650.33 T
(divscc %o1,%o5,%o1) 99 638.33 T
(divscc %o1,%o5,%o1) 99 626.33 T
(!divide step 32) 207 626.33 T
(be 6f) 99 614.33 T
(!if final remainder is zero,) 153 614.33 T
(!go fix quotient polarity) 153 602.33 T
(mov %y, %o4) 99 590.33 T
(!final remainder from Y to o4) 171 590.33 T
(bg 4f) 99 578.33 T
(!skip ahead if rmdr+; continue if rmdr-) 153 578.33 T
(addcc %o4,%o5,%g0) 99 566.33 T
(!is neg rmdr + abs divsr =0) 201 566.33 T
(be,a 6f) 99 554.33 T
(!if so, go fix quotient polarity and) 153 554.33 T
(mov %g0,%o4) 99 542.33 T
(!clear rmdr. if not, don\325t clear) 165 542.33 T
(tst %o0) 99 530.33 T
(!test original dvdnd) 153 530.33 T
(bl 5f) 99 518.33 T
(!if neg, go check neg Q) 153 518.33 T
(tst %o1) 99 506.33 T
(!sign Q) 153 506.33 T
(ba 5f) 99 494.33 T
(add %o4,%o5,%o4) 99 482.33 T
(!if orig dvdnd pos and final rmdr neg,) 189 482.33 T
(!correct rmdr; then go check neg Q) 153 470.33 T
(4:) 72 458.33 T
(subcc %o4,%o5,%g0) 99 458.33 T
(!is pos rmdr - abs divsr =0) 201 458.33 T
(be,a 6f) 99 446.33 T
(!if so, go fix quotient polarity and) 153 446.33 T
(mov %g0,%o4) 99 434.33 T
(!clear rmdr. if not, don\325t clear) 165 434.33 T
(tst %o0) 99 422.33 T
(!test original dvdnd) 153 422.33 T
(bge 5f) 99 410.33 T
(!if pos, go check neg Q) 153 410.33 T
(tst %o1) 99 398.33 T
(!sign Q) 153 398.33 T
(sub %o4,%o5,%o4) 99 386.33 T
(!if orig dvdnd neg and final rmdr pos,) 189 386.33 T
(!correct rmdr; then go check neg Q) 153 374.33 T
(5:) 72 362.33 T
(bl,a 6f) 99 362.33 T
(!skip ahead if Q pos) 153 362.33 T
(add %o1,1,%o1) 99 350.33 T
(!if neg Q, 1\325s complement to) 177 350.33 T
(!2\325s complement; annul if pos Q) 153 338.33 T
(6:) 72 326.33 T
(tst %o2) 99 326.33 T
(!check original divisor sign) 153 326.33 T
(bl,a 7f) 99 314.33 T
(sub %g0,%o1,%o1) 99 302.33 T
(!if neg divsr, negate quotient) 189 302.33 T
(7:) 72 290.33 T
(retl) 99 290.33 T
(!exit) 153 290.33 T
(mov %o4,%o0) 99 278.33 T
(!with correct remainder in o0) 165 278.33 T
0 12 Q
(A.2.3 di) 72 235 T
(vu1 - di) 117.55 235 T
(vide unsigned, 1 w) 156.11 235 T
(ord di) 250.01 235 T
(vidend) 280.9 235 T
2 F
-0.28 (Unsigned di) 72 213 P
-0.28 (vision of a 32 bit di) 129.75 213 P
-0.28 (vidend by a 32 bit di) 221.73 213 P
-0.28 (visor produces an unsigned 32 bit quo-) 319.03 213 P
-0.14 (tient and an unsigned 32 bit remainder that is positi) 72 199 P
-0.14 (v) 316.73 199 P
-0.14 (e or zero if e) 322.55 199 P
-0.14 (xact. Since only o) 382.44 199 P
-0.14 (v) 467.82 199 P
-0.14 (er\337o) 473.64 199 P
-0.14 (w) 495.34 199 P
0.53 (is di) 72 185 P
0.53 (vide by zero, this routine does not check for di) 92.57 185 P
0.53 (vide by zero, lea) 320.35 185 P
0.53 (ving it up to caller to) 401.01 185 P
0.47 (test and abort just after the call. Di) 72 171 P
0.47 (vision without f) 240.93 171 P
0.47 (ault tak) 317.75 171 P
0.47 (es 39 c) 353.76 171 P
0.47 (ycles. If remainder is of) 387.84 171 P
7.08 (no interest and only the quotient corresponding to INTEGER\050dvdnd/dvsr\051 or) 72 157 P
-0.27 (FLOOR\050dvdnd/dvsr\051 for unsigned numbers is w) 72 143 P
-0.27 (anted then the last steps of this routine can) 302.18 143 P
1.59 (be modi\336ed as indicated and quotient only unsigned di) 72 129 P
1.59 (vision will tak) 347.04 129 P
1.59 (e 36 c) 418.77 129 P
1.59 (ycles. This) 450.42 129 P
(assumes each instruction tak) 72 115 T
(es one c) 208.86 115 T
(ycle e) 247.33 115 T
(xcept) 275.47 115 T
13 10 Q
(retl) 304.46 115 T
2 12 Q
( which tak) 328.46 115 T
(es tw) 378.34 115 T
(o.) 403.21 115 T
FMENDPAGE
%%EndPage: "68" 74
%%Page: "69" 75
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(69) 528 17 T
13 10 Q
(!DIVISION SUBROUTINE - DIVU1) 108 710.33 T
(!This subroutine for unsigned division of 32 bit dividend by 32 bit) 108 698.33 T
(!divisor produces 32 bit unsigned quotient and 32 bit remainder using) 108 686.33 T
(!divide step instruction. Remainder is zero if division is exact) 108 674.33 T
(!or positive if not. There is no check for divide by zero. It is not) 108 662.33 T
(!possible to overflow with non zero divisor. If the calling routine) 108 650.33 T
(!knows that divide by zero cannot happen, no test is needed. If divide) 108 638.33 T
(!by zero is possible, a simple test just after the call can abort the) 108 626.33 T
(!division. If not aborted, division takes 39 cycles; clears overflow) 108 614.33 T
(!flag; leaves 0 in register out3.) 108 602.33 T
(!If remainder is of no interest and only the quotient corresponding to) 108 590.33 T
(!INTEGER\050dvdnd/dvsr\051 or FLOOR\050dvdnd/dvsr\051 for unsigned numbers is wanted) 108 578.33 T
(!then the last steps of this routine can be modified as indicated and) 108 566.33 T
(!quotient only unsigned division will take 36 cycles.) 108 554.33 T
(!call so:) 108 542.33 T
(!) 108 530.33 T
(mov %l1,%o1) 135 530.33 T
(!dvdnd->o1) 201 530.33 T
(!) 108 518.33 T
(orcc %g0,%l2,%o2) 135 518.33 T
(!dvsr->o2 & test) 231 518.33 T
(!) 108 506.33 T
(call divu1) 135 506.33 T
(!DIVISION SUBROUTINE CALL) 195 506.33 T
(!) 108 494.33 T
(be dvby0) 135 494.33 T
(!abort division if divide by zero) 189 494.33 T
(!) 108 482.33 T
(!Register Map) 108 470.33 T
(!reg#) 108 458.33 T
(!out0) 108 446.33 T
( remainder) 138 446.33 T
(!out1) 108 434.33 T
( dividend/quotient) 138 434.33 T
(!out2) 108 422.33 T
( divisor) 138 422.33 T
(!out3) 108 410.33 T
( 0 if divide by non zero) 138 410.33 T
(!y) 108 398.33 T
( initially zero/successive partial remainders) 135 398.33 T
(!) 108 386.33 T
(.global divu1) 108 374.33 T
(divu1:) 108 362.33 T
(mov %g0,%y) 144 362.33 T
(!0->Y) 204 362.33 T
(orcc %g0,0,%o3) 135 350.33 T
(!initialize cc for first divide step) 219 350.33 T
(!with positive sign for unsigned divide) 189 338.33 T
(!clear divide by zero indicator) 189 326.33 T
(divscc %o1,%o2,%o1) 135 314.33 T
(!divide step 1) 243 314.33 T
(!don\325t change cc except by divscc until last divide step done) 108 302.33 T
(divscc %o1,%o2,%o1) 135 290.33 T
(divscc %o1,%o2,%o1) 135 278.33 T
(divscc %o1,%o2,%o1) 135 266.33 T
(divscc %o1,%o2,%o1) 135 254.33 T
(divscc %o1,%o2,%o1) 135 242.33 T
(divscc %o1,%o2,%o1) 135 230.33 T
(divscc %o1,%o2,%o1) 135 218.33 T
(divscc %o1,%o2,%o1) 135 206.33 T
(divscc %o1,%o2,%o1) 135 194.33 T
(divscc %o1,%o2,%o1) 135 182.33 T
(divscc %o1,%o2,%o1) 135 170.33 T
(divscc %o1,%o2,%o1) 135 158.33 T
(divscc %o1,%o2,%o1) 135 146.33 T
(divscc %o1,%o2,%o1) 135 134.33 T
(divscc %o1,%o2,%o1) 135 122.33 T
(divscc %o1,%o2,%o1) 135 110.33 T
(divscc %o1,%o2,%o1) 135 98.33 T
(divscc %o1,%o2,%o1) 135 86.33 T
FMENDPAGE
%%EndPage: "69" 75
%%Page: "70" 76
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(70) 72 17 T
13 10 Q
(divscc %o1,%o2,%o1) 99 722.33 T
(divscc %o1,%o2,%o1) 99 710.33 T
(divscc %o1,%o2,%o1) 99 698.33 T
(divscc %o1,%o2,%o1) 99 686.33 T
(divscc %o1,%o2,%o1) 99 674.33 T
(divscc %o1,%o2,%o1) 99 662.33 T
(divscc %o1,%o2,%o1) 99 650.33 T
(divscc %o1,%o2,%o1) 99 638.33 T
(divscc %o1,%o2,%o1) 99 626.33 T
(divscc %o1,%o2,%o1) 99 614.33 T
(divscc %o1,%o2,%o1) 99 602.33 T
(divscc %o1,%o2,%o1) 99 590.33 T
(! retl) 99 578.33 T
(!exit for quotient only divide) 153 578.33 T
(divscc %o1,%o2,%o1) 99 566.33 T
(!divide step 32) 207 566.33 T
(!ALL the following steps may be omitted for quotient only divide) 99 554.33 T
(bl 1f) 99 542.33 T
(!skip ahead if rmdr-) 153 542.33 T
(mov %y,%o0) 99 530.33 T
(!final rmdr from Y to o0) 159 530.33 T
(retl) 99 518.33 T
(!exit) 153 518.33 T
(addcc %o0,0,%o0) 99 506.33 T
(!clear ovrflw cc if on) 189 506.33 T
(1:) 72 494.33 T
(retl) 99 494.33 T
(!exit) 153 494.33 T
(addcc %o0,%o2,%o0) 99 482.33 T
(!correct rmdr & clear ovrflw cc if on) 201 482.33 T
0 12 Q
(A.2.4 di) 72 439 T
(vu2 - di) 117.55 439 T
(vide unsigned, 2 w) 156.11 439 T
(ord di) 250.01 439 T
(vidend) 280.9 439 T
2 F
-0.28 (Unsigned di) 72 417 P
-0.28 (vision of a 64 bit di) 129.75 417 P
-0.28 (vidend by a 32 bit di) 221.73 417 P
-0.28 (visor produces an unsigned 32 bit quo-) 319.03 417 P
-0.27 (tient and an unsigned 32 bit remainder that is positi) 72 403 P
-0.27 (v) 315.57 403 P
-0.27 (e or zero if e) 321.39 403 P
-0.27 (xact. Di) 380.75 403 P
-0.27 (vision with di) 418.17 403 P
-0.27 (vide) 483.34 403 P
0.52 (by zero f) 72 389 P
0.52 (ault tak) 115.57 389 P
0.52 (es 6 c) 151.64 389 P
0.52 (ycles. Di) 179.83 389 P
0.52 (vision with non zero di) 222.71 389 P
0.52 (visor o) 335.16 389 P
0.52 (v) 368.51 389 P
0.52 (er\337o) 374.33 389 P
0.52 (w f) 396.02 389 P
0.52 (ault tak) 412.08 389 P
0.52 (es 9 c) 448.15 389 P
0.52 (ycles.) 476.34 389 P
2.12 (Di) 72 375 P
2.12 (vision without f) 83.7 375 P
2.12 (ault tak) 163.82 375 P
2.12 (es 42 c) 201.48 375 P
2.12 (ycles. This assumes each instruction tak) 238.86 375 P
2.12 (es one c) 441.3 375 P
2.12 (ycle) 484.01 375 P
(e) 72 361 T
(xcept) 77.15 361 T
13 10 Q
(retl) 106.14 361 T
2 12 Q
( which tak) 130.14 361 T
(es tw) 180.01 361 T
(o.) 204.89 361 T
13 10 Q
(!DIVISION SUBROUTINE - DIVU2) 72 336.33 T
(!This subroutine for unsigned division of 64 bit dividend by 32 bit) 72 324.33 T
(!divisor produces 32 bit unsigned quotient and 32 bit remainder using) 72 312.33 T
(!divide step instruction. Remainder is zero if division is exact) 72 300.33 T
(!or positive if not. There is a check for divide by zero and a check for) 72 288.33 T
(!overflow with non-zero divisor. Check for divide by zero is kept) 72 276.33 T
-0.55 (!separate to support possible SUN recommended trap for divide by zero. In) 72 264.33 P
(!applications where user knows numerical ranges or controls them, these) 72 252.33 T
(!checks can be omitted. Division with divide by zero fault takes 6) 72 240.33 T
(!cycles; sets overflow flag in condition code; leaves 0xfffff800 in) 72 228.33 T
(!register out3. Division with non-zero divisor overflow takes 9 cycles;) 72 216.33 T
(!sets overflow flag in condition code; leaves 0x800 in register out3.) 72 204.33 T
(!Division without fault takes 42 cycles; clears overflow flag in) 72 192.33 T
(!condition code; leaves 0 in register out3.) 72 180.33 T
(!call so:) 72 168.33 T
(!) 72 156.33 T
(mov %l0,%o0) 99 156.33 T
(!msh dvdnd->o0) 165 156.33 T
(!) 72 144.33 T
(mov %l1,%o1) 99 144.33 T
(!lsh dvdnd->o1) 165 144.33 T
(!) 72 132.33 T
(call divu2) 99 132.33 T
(!DIVISION SUBROUTINE CALL) 159 132.33 T
(!) 72 120.33 T
(orcc %g0,%l2,%o2) 99 120.33 T
(!dvsr->o2 & test) 195 120.33 T
(!) 72 108.33 T
(!Register Map) 72 96.33 T
(!reg#) 72 84.33 T
FMENDPAGE
%%EndPage: "70" 76
%%Page: "71" 77
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(71) 528 17 T
13 10 Q
(!out0) 108 722.33 T
(msh dividend/remainder) 162 722.33 T
(!out1) 108 710.33 T
(lsh dividend/quotient) 162 710.33 T
(!out2) 108 698.33 T
(divisor) 162 698.33 T
(!out3) 108 686.33 T
(overflow indication) 162 686.33 T
(!overflow divide by zero/0xfffff800 and V=1) 108 674.33 T
(!overflow divide by non-zero/0x800 and V=1) 108 662.33 T
(!no overflow/0 and V=0) 108 650.33 T
(!y) 108 638.33 T
(msh dividend/successive partial remainders) 162 638.33 T
(!call to divs2 must be made with cc indicating if divisor zero) 108 626.33 T
(!) 108 614.33 T
(.global divu2) 108 602.33 T
(divu2:) 108 590.33 T
(bne 1f) 144 590.33 T
(!go on if divisor not zero) 189 590.33 T
(mov %o0,%y) 135 578.33 T
(!msh dvdnd->Y) 195 578.33 T
(sethi 0x1fffff,%o3) 135 566.33 T
(!divide by zero indicator) 243 566.33 T
(retl) 135 554.33 T
(!exit with) 189 554.33 T
(addcc %o3,%o3,%o3) 135 542.33 T
( !overflow set) 237 542.33 T
(1:) 108 530.33 T
(subcc %o0,%o2,%g0) 135 530.33 T
(!is msh dvdnd < dvsr) 237 530.33 T
(bcs 2f) 135 518.33 T
(!ok if so) 189 518.33 T
(orcc %g0,0,%o3) 135 506.33 T
(!initialize cc for first divide step) 231 506.33 T
(!with positive sign for unsigned divide) 189 494.33 T
(!clear overflow indicator) 189 482.33 T
(sethi 0x200001,%o3) 135 470.33 T
(!overflow divide by non-zero indicator) 243 470.33 T
(retl) 135 458.33 T
(!exit with) 189 458.33 T
(addcc %o3,%o3,%o3) 135 446.33 T
( !overflow set) 237 446.33 T
(2:) 108 434.33 T
(divscc %o1,%o2,%o1) 135 434.33 T
(!divide step 1) 243 434.33 T
(!don\325t change cc except by divscc until last divide step done) 108 422.33 T
(divscc %o1,%o2,%o1) 135 410.33 T
(divscc %o1,%o2,%o1) 135 398.33 T
(divscc %o1,%o2,%o1) 135 386.33 T
(divscc %o1,%o2,%o1) 135 374.33 T
(divscc %o1,%o2,%o1) 135 362.33 T
(divscc %o1,%o2,%o1) 135 350.33 T
(divscc %o1,%o2,%o1) 135 338.33 T
(divscc %o1,%o2,%o1) 135 326.33 T
(divscc %o1,%o2,%o1) 135 314.33 T
(divscc %o1,%o2,%o1) 135 302.33 T
(divscc %o1,%o2,%o1) 135 290.33 T
(divscc %o1,%o2,%o1) 135 278.33 T
(divscc %o1,%o2,%o1) 135 266.33 T
(divscc %o1,%o2,%o1) 135 254.33 T
(divscc %o1,%o2,%o1) 135 242.33 T
(divscc %o1,%o2,%o1) 135 230.33 T
(divscc %o1,%o2,%o1) 135 218.33 T
(divscc %o1,%o2,%o1) 135 206.33 T
(divscc %o1,%o2,%o1) 135 194.33 T
(divscc %o1,%o2,%o1) 135 182.33 T
(divscc %o1,%o2,%o1) 135 170.33 T
(divscc %o1,%o2,%o1) 135 158.33 T
(divscc %o1,%o2,%o1) 135 146.33 T
(divscc %o1,%o2,%o1) 135 134.33 T
(divscc %o1,%o2,%o1) 135 122.33 T
(divscc %o1,%o2,%o1) 135 110.33 T
(divscc %o1,%o2,%o1) 135 98.33 T
(divscc %o1,%o2,%o1) 135 86.33 T
FMENDPAGE
%%EndPage: "71" 77
%%Page: "72" 78
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(72) 72 17 T
13 10 Q
(divscc %o1,%o2,%o1) 99 722.33 T
(divscc %o1,%o2,%o1) 99 710.33 T
(divscc %o1,%o2,%o1) 99 698.33 T
(!divide step 32) 207 698.33 T
(bl 3f) 99 686.33 T
(!skip ahead if rmdr-) 153 686.33 T
(mov %y,%o0) 99 674.33 T
(!final remdr from Y to o0) 159 674.33 T
(retl) 99 662.33 T
(!exit) 153 662.33 T
(addcc %o0,0,%o0) 99 650.33 T
(!clear ovrflw cc if on) 189 650.33 T
(3:) 72 638.33 T
(retl) 99 638.33 T
(!exit) 153 638.33 T
(addcc %o0,%o2,%o0) 99 626.33 T
(!correct rmdr & clear ovrflw cc if on) 201 626.33 T
0 12 Q
(A.3 SCAN Instruction Examples) 72 583 T
(A.3.1 Softwar) 72 539 T
(e \337oating point with SCAN) 148.1 539 T
2 F
1 (The follo) 72 517 P
1 (wing code fragment sho) 117.03 517 P
1 (ws post normalization of \337oating point add or subtract) 235.36 517 P
0.79 (for the case where the result requires calculating the dif) 72 503 P
0.79 (ference of the magnitudes of the) 345.08 503 P
-0.04 (numbers. The IEEE754 format, which is used in SP) 72 489 P
-0.04 (ARC-V8 architecture is assumed. This) 318.53 489 P
1.79 (uses sign, of) 72 475 P
1.79 (fset e) 134.95 475 P
1.79 (xponent, hidden leading bit when normalized and fraction. Only the) 162.23 475 P
-0.07 (logic of normalize numbers is sho) 72 461 P
-0.07 (wn here. Number v) 234.33 461 P
-0.07 (alues are in sign and magnitude form) 326.45 461 P
(rather than tw) 72 447 T
(o\325) 138.53 447 T
(s complement.) 147.86 447 T
13 10 Q
(bit) 99 412.33 T
(31| 30 23) 126 412.33 T
(| 22 0) 180 412.33 T
(normalized values) 216 412.33 T
(field) 99 400.33 T
(s |) 129 400.33 T
(e) 159 400.33 T
(|) 165 400.33 T
(f) 183 400.33 T
(0<e<255) 195 400.33 T
(x = \050-1\051^s * 2^\050e-127\051 * \0501 + f*2^-23\051) 180 388.33 T
2 12 Q
0.82 (The operation is x) 72 367 P
8 14 Q
0.96 (+) 161.45 367 P
2 12 Q
0.82 (y=z or x) 169.13 367 P
8 14 Q
0.96 (-) 210.87 367 P
2 12 Q
0.82 (y=z. If subtract, then sign y is complemented. The magni-) 218.55 367 P
1.76 (tudes of the numbers ha) 72 353 P
1.76 (v) 193.43 353 P
1.76 (e to be compared and the one with the lesser e) 199.25 353 P
1.76 (xponent right) 437.91 353 P
-0.02 (shifted to align its decimal point with the greater e) 72 339 P
-0.02 (xponent. If e) 313.31 339 P
-0.02 (xponents are equal, magni-) 374.08 339 P
1.17 (tudes must be compared if signs dif) 72 325 P
1.17 (fer to determine what the sign of the result will be.) 249.36 325 P
0.83 (This is assumed to ha) 72 311 P
0.83 (v) 178.4 311 P
0.83 (e tak) 184.22 311 P
0.83 (en place before the code fragment sho) 207.91 311 P
0.83 (wn here, which sho) 395.18 311 P
0.83 (ws) 490.67 311 P
1.99 (the logic of handling numbers with dif) 72 297 P
1.99 (ferent signs and dif) 268.27 297 P
1.99 (ferent e) 366.24 297 P
1.99 (xponents. Symbol x) 404.35 297 P
(points to the lar) 72 283 T
(ger number; y to smaller) 146.78 283 T
(.) 264.11 283 T
13 10 Q
(sethi 0x3fe, %g5) 99 248.33 T
(!mask for sign and exponent with and) 195 248.33 T
(!or for fraction with andn) 153 236.33 T
(sll %g5,1,%g4) 99 224.33 T
(xor %g4,%g5,%g4) 99 212.33 T
(!single one at bit 23 for hidden bit) 189 212.33 T
(srl x,23,%g2) 99 200.33 T
(and %g2,0xff,%g2) 99 188.33 T
(!x exponent) 195 188.33 T
(srl y,23,%g3) 99 176.33 T
(and %g3,0xff,%g3) 99 164.33 T
(!y exponent) 195 164.33 T
(sub %g2,%g3,%g1) 99 152.33 T
(!alignment difference) 189 152.33 T
(andn y,%g5,%g3) 99 140.33 T
(!y fraction) 183 140.33 T
(or %g3,%g4,%g3) 99 128.33 T
(!y hidden bit) 183 128.33 T
(srl %g3,%g1,%g2) 99 116.33 T
(!downshift y magnitude to g2) 189 116.33 T
(sub %g0,%g1,%g1) 99 104.33 T
(!complement of shift) 189 104.33 T
(sll %g3,%g1,%g3) 99 92.33 T
(!upshift left over y for test) 189 92.33 T
FMENDPAGE
%%EndPage: "72" 78
%%Page: "73" 79
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(73) 528 17 T
13 10 Q
(addcc %g3,%g3,%g0) 135 722.33 T
(!test left over for rounding) 237 722.33 T
(!note: not IEEE754 rounding here) 189 710.33 T
(andn x,%g5,%g1) 135 698.33 T
(!x fraction) 219 698.33 T
(or %g1,%g4,%g1) 135 686.33 T
(!x hidden bit) 219 686.33 T
(subx %g1,%g2,%g1) 135 674.33 T
(!difference of magnitudes with) 231 674.33 T
(!simple rounding) 189 662.33 T
(scan %g1,0,%g2) 135 650.33 T
(!scan difference for leading one.) 219 650.33 T
(!Use of 0 as the scan mask is because) 189 638.33 T
(!of sign magnitude arithmetic assumed) 189 626.33 T
(!in this example. Leading 8 bits are) 189 614.33 T
(!guaranteed to be zero because of) 189 602.33 T
(!format. Question is, how many more) 189 590.33 T
(!till the first one?) 189 578.33 T
(!If two\325s complement arithmetic had) 189 566.33 T
(!been assumed, then there could have) 189 554.33 T
(!been leading ones or leading zeros) 189 542.33 T
(!depending on sign of result. Then) 189 530.33 T
(!instead of 0 as mask, scan would have) 189 518.33 T
(!used %g1 as mask as well as value.) 189 506.33 T
(!Question would have been, how many) 189 494.33 T
(!leading bits are the same as the sign?) 189 482.33 T
(subcc %g2,32,%g0) 135 470.33 T
(!test if all significant bits lost) 231 470.33 T
(blu 1f) 135 458.33 T
(!use unsigned compare for future compatibility) 189 458.33 T
(sub %g2,8,%g2) 135 446.33 T
(!remove effect of format\325s 8 leading 0\325s) 213 446.33 T
(!underflow due to loss of significant bits code would follow here) 135 434.33 T
(1:) 108 410.33 T
(sll %g1,%g2,%g1) 135 410.33 T
(!normalize result) 225 410.33 T
(andn %g1,%g4,%g1) 135 398.33 T
(!hide leading bit) 231 398.33 T
(srl x,23,%g3) 135 386.33 T
(and %g3,0xff,%g4) 135 374.33 T
(!x exponent in g4) 231 374.33 T
(subcc %g4,%g2,%g0) 135 362.33 T
(!test exponent underflow) 237 362.33 T
(bgu 2f) 135 350.33 T
(!use unsigned compare for future compatability) 189 350.33 T
(sub %g3,%g2,%g3) 135 338.33 T
(!subtract normalization shift from) 225 338.33 T
(!result sign and exponent) 135 326.33 T
(!exponent underflow code would follow here) 135 314.33 T
(2:) 108 290.33 T
(sll %g3,23,%g3) 135 290.33 T
(!place sign and exponent result in) 219 290.33 T
(!format position) 189 278.33 T
(retl) 135 266.33 T
(!exit\0502 cycles\051) 189 266.33 T
(or %g1,%g3,z) 135 254.33 T
(!combine with fraction) 207 254.33 T
2 12 Q
0.65 (Each instruction in this code fragment runs one c) 108 233 P
0.65 (ycle out of the instruction cache e) 348.32 233 P
0.65 (xcept) 514.01 233 P
0.23 (for the leaf routine which tak) 108 219 P
0.23 (es tw) 248.65 219 P
0.23 (o. That\325) 273.76 219 P
0.23 (s 32 c) 311.32 219 P
0.23 (ycles for this fragment. W) 339.59 219 P
0.23 (ithout scan as a) 465.66 219 P
0.63 (hardw) 108 205 P
0.63 (are instruction, the function w) 137.87 205 P
0.63 (ould ha) 284.58 205 P
0.63 (v) 320.64 205 P
0.63 (e to be performed as a softw) 326.46 205 P
0.63 (are routine that) 466.09 205 P
0.5 (tak) 108 191 P
0.5 (es 43 to 52 c) 122.54 191 P
0.5 (ycles for the usual cases. The fragment w) 185.02 191 P
0.5 (ould tak) 387 191 P
0.5 (e 74 to 83 c) 426.38 191 P
0.5 (ycles, more) 484.18 191 P
1.07 (than double the c) 108 177 P
1.07 (ycles. A softw) 193.35 177 P
1.07 (are substitute for scan w) 264.35 177 P
1.07 (ould consume instruction cache) 385.15 177 P
-0.3 (space. Attempts to speed up the binary tree search in the softw) 108 163 P
-0.3 (are routine by look up tables) 404.52 163 P
(based on leading bits w) 108 149 T
(ould consume data cache space.) 220.54 149 T
FMENDPAGE
%%EndPage: "73" 79
%%Page: "74" 80
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(74) 72 17 T
0 F
(A.3.2 Run length encoding with SCAN) 72 721 T
2 F
1.5 (The follo) 72 699 P
1.5 (wing code fragment sho) 117.53 699 P
1.5 (ws compression of long binary strings by looking for) 237.36 699 P
-0.22 (runs of all ones or all zeros and coding these so that lossless reconstruction is possible. F) 72 685 P
-0.22 (or) 494 685 P
1.14 (the e) 72 671 P
1.14 (xample, runs less than four in length are ignored and directly transmitted and runs) 95.95 671 P
1.2 (greater than sixteen are brok) 72 657 P
1.2 (en up for coding ef) 213.28 657 P
1.2 (\336cienc) 309.07 657 P
1.2 (y and coding simpli\336cation. Best) 340.88 657 P
0.97 (compression occurs for lo) 72 643 P
0.97 (w information content long binary strings such as background) 198.92 643 P
(sections of black and white raster lines.) 72 629 T
13 10 Q
(code) 99 616.33 T
(value) 126 616.33 T
(00000) 99 604.33 T
(reserved) 129 604.33 T
(00001) 99 592.33 T
(\322) 129 592.33 T
(00010) 99 580.33 T
(\322) 129 580.33 T
(00011) 99 568.33 T
(\322) 129 568.33 T
(------------------------------) 99 556.33 T
(00100) 99 544.33 T
(00001... or 11110...) 129 544.33 T
(00101) 99 532.33 T
(000001... or 111110...) 129 532.33 T
(00110) 99 520.33 T
(0000001... or 1111110...) 129 520.33 T
(...) 99 508.33 T
(01111) 99 496.33 T
(0000 0000 0000 0001... or 1111 1111 1111 1110...) 129 496.33 T
(10000) 99 484.33 T
(0000 0000 0000 0000 1... or 1111 1111 1111 1111 0...) 129 484.33 T
(-------------------------------------------------------) 99 472.33 T
(10001) 99 460.33 T
(0001...) 129 460.33 T
(10010) 99 448.33 T
(0010...) 129 448.33 T
(10011) 99 436.33 T
(0011...) 129 436.33 T
(...) 99 424.33 T
(11110) 99 412.33 T
(1110...) 129 412.33 T
(-----------------) 99 400.33 T
(11111) 99 388.33 T
(toggle) 129 388.33 T
2 12 Q
1.43 (The code fragment omits starting up the loop, reloading b) 72 367 P
1.43 (uf) 361.25 367 P
1.43 (fers with ne) 370.94 367 P
1.43 (w data, storing) 430.15 367 P
-0.02 (code and terminating the loop. Symbol x points to data se) 72 353 P
-0.02 (gment in some re) 347.97 353 P
-0.02 (gister ready for) 430.73 353 P
-0.3 (compression and symbol y points to its immediate successor) 72 339 P
-0.3 (. Symbol z points to some re) 358.96 339 P
-0.3 (g-) 494 339 P
(ister that will hold code for compression data.) 72 325 T
13 10 Q
(0:) 72 300.33 T
(scan x,x,%g1) 99 300.33 T
(!scan for how many bits are same as msb.) 171 300.33 T
(!g1 = 1 to 31 or >32 if all in x register.) 153 288.33 T
(!x is used as both the value to be scanned\050rs1\051) 153 276.33 T
(!and the mask\050rs2\051.) 153 264.33 T
(subcc %g1,4,%g0) 99 252.33 T
(!test if run at least length 4) 189 252.33 T
(bgeu 1f) 99 240.33 T
(!use unsigned compare for future compatability) 153 240.33 T
(subcc %g1,16,%g0) 99 228.33 T
(!test if run greater than length 16) 195 228.33 T
(!handle fixed length code, g1<4) 153 216.33 T
(srl x,28,%g2) 99 204.33 T
(!extract leading 4 bits of x as compression code) 171 204.33 T
(or %g2,16,%g2) 99 192.33 T
(!insert leading bit of code for fixed length) 177 192.33 T
(sll x,3,x) 99 180.33 T
(!shift rest of x in 2 steps) 153 180.33 T
(addcc x,x,x) 99 168.33 T
(!complete x shift and test last of 4 bits) 165 168.33 T
(bcs 2f) 99 156.33 T
(!separate cases for 1 or 0) 153 156.33 T
(addcc x,x,%g0) 99 144.33 T
(!test without shifting first of remaining bits) 177 144.33 T
(bcs 3f) 99 132.33 T
(!if last out bit =0 and first remaining bit =1) 153 132.33 T
(mov 1,%g4) 99 120.33 T
(!set new low priority toggle indicator) 153 120.33 T
(ba 3f) 99 108.33 T
(mov 0,%g4) 99 96.33 T
(!otherwise clear toggle indicator) 153 96.33 T
(!fixed length code overwrites any pending toggle) 153 84.33 T
FMENDPAGE
%%EndPage: "74" 80
%%Page: "75" 81
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(75) 528 17 T
13 10 Q
(2:) 108 722.33 T
(bcc 3f) 135 722.33 T
(!if last out bit =1 and first remaining bit =0) 189 722.33 T
(mov 1,%g4) 135 710.33 T
(!set new low priority toggle indicator) 189 710.33 T
(mov 0,%g4) 135 698.33 T
(!otherwise clear toggle indicator) 189 698.33 T
(!fixed length code overwrites any pending toggle) 189 686.33 T
(3:) 108 674.33 T
(srl y,28,%g3) 135 674.33 T
(!extract leading 4 bits of y) 207 674.33 T
(or x,%g3,x) 135 662.33 T
(!move them to right end of x) 195 662.33 T
(sll y,4,y) 135 650.33 T
(!shift rest of y with incoming trailing zeros) 189 650.33 T
(ba 5f) 135 638.33 T
(subcc %g5,4,%g5) 135 626.33 T
(!decrement counter of how many bits of x left) 225 626.33 T
(!handle run length code) 189 614.33 T
(1:) 108 602.33 T
(blu 4f) 135 602.33 T
(!skip ahead if run less than 16) 189 602.33 T
(!use unsigned compare for future compatability) 189 590.33 T
(sll %g4,1,%g4) 135 578.33 T
(!shift incomming toggle indicator to higher) 213 578.33 T
(!priority; handle runs at least 16) 189 566.33 T
(mov 16,%g2) 135 554.33 T
(!set compression code to 16) 195 554.33 T
(sll x,16,x) 135 542.33 T
(!ignore leading 16 bits of x and shift rest of x) 195 542.33 T
(srl y,16,%g3) 135 530.33 T
(!extract leading 16 bits of y) 207 530.33 T
(or x,%g3,x) 135 518.33 T
(!move them to right end of x) 195 518.33 T
(sll y,16,y) 135 506.33 T
(!shift rest of y with incomming trailing zeros) 195 506.33 T
(ba 5f) 135 494.33 T
(subcc %g5,16,%g5) 135 482.33 T
(!decrement counter of how many bits of x left) 231 482.33 T
(!handle runs of length 4 to 15) 189 470.33 T
(4:) 108 458.33 T
(mov %g1,%g2) 135 458.33 T
(!set compression code to scan result) 201 458.33 T
(sub %g0,%g1,%g1) 135 446.33 T
(!complement scan result) 225 446.33 T
(sll x,%g2,x) 135 434.33 T
(!ignore leading g2 bits of x and shift rest of x) 201 434.33 T
(srl y,%g1,%g3) 135 422.33 T
(!extract leading 32-g1 bits of y) 213 422.33 T
(or x,%g3,x) 135 410.33 T
(!move them to right end of x) 195 410.33 T
(sll y,%g2,y) 135 398.33 T
(!shift rest of y with incomming trailing zeros) 201 398.33 T
(subcc %g5,%g2,%g5) 135 386.33 T
(!decrement counter of how many bits of x left) 237 386.33 T
(or %g4,1,%g4) 135 374.33 T
(!toggle following compression code too) 207 374.33 T
(!one compression code to go) 189 362.33 T
(5:) 108 350.33 T
(bgu 6f) 135 350.33 T
(!skip ahead if there are still bits of x left) 189 350.33 T
(!use unsigned compare for future compatability) 189 338.33 T
(subcc %g6,1,%g6) 135 326.33 T
(!decrement counter of code fields left) 225 326.33 T
(!code for reloading y and shifting part of it into x if the old y had) 108 314.33 T
(!trailing zeros and resetting g5 to 32-#trailing zeros.) 108 302.33 T
( ...) 108 290.33 T
(6:) 108 278.33 T
(bg 7f) 135 278.33 T
(!skip ahead if room for more codes) 189 278.33 T
(andcc %g4,2,%g0) 135 266.33 T
(!test if toggle has priority) 225 266.33 T
(!code for storing codes and reinitializing g6) 189 254.33 T
( ...) 108 242.33 T
(7:) 108 230.33 T
(sll z,5,z) 135 230.33 T
(!make room for new code) 189 230.33 T
(be,a 0b) 135 218.33 T
(!if g4 bit1 off then no additional code) 189 218.33 T
(!if g4 bit1 on then insert toggle code first) 189 206.33 T
(or z,%g2,z) 135 194.33 T
(!insert new data code) 195 194.33 T
(andn %g4,2,%g4) 135 182.33 T
(!clear high priority toggle indicator) 219 182.33 T
(!without disturbing low priority toggle indicator) 108 170.33 T
(ba 5b) 135 158.33 T
(!check on how much code space left and append toggle) 165 158.33 T
(or z,0x1f,z) 135 146.33 T
(!back through 5,6,7 just once) 201 146.33 T
( ...) 108 134.33 T
2 12 Q
-0.01 (Each instruction in this code fragment runs one c) 108 113 P
-0.01 (ycle out of the instruction cache if it is in) 343.07 113 P
0.35 (the acti) 108 99 P
0.35 (v) 143.04 99 P
0.35 (e path for a particular case. Scan is in the acti) 148.86 99 P
0.35 (v) 369.62 99 P
0.35 (e path for all cases. W) 375.45 99 P
0.35 (ithout hard-) 483.33 99 P
0.29 (w) 108 85 P
0.29 (are implementation of Scan, the function w) 116.54 85 P
0.29 (ould require a softw) 325.78 85 P
0.29 (are subroutine taking 43) 422.83 85 P
FMENDPAGE
%%EndPage: "75" 81
%%Page: "76" 82
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(76) 72 17 T
0.11 (to 52 c) 72 721 P
0.11 (ycles instead of only 1. Additionally) 104.71 721 P
0.11 (, that routine w) 279.15 721 P
0.11 (ould consume instruction cache) 352.02 721 P
0.47 (space. Alternate v) 72 707 P
0.47 (ersions that might attempt to speed up the binary tree search with table) 159.07 707 P
(look up using leading bits as an inde) 72 693 T
(x w) 246.82 693 T
(ould consume data cache space.) 264.36 693 T
FMENDPAGE
%%EndPage: "76" 82
%%Page: "77" 83
612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(77) 528 17 T
0 14 Q
(Annex B Alter) 189.31 623.67 T
(nati) 282.42 623.67 T
(v) 305.62 623.67 T
(e W) 312.48 623.67 T
(indo) 335.94 623.67 T
(w Usage Models) 362.26 623.67 T
2 12 Q
(\050Informati) 291.92 601 T
(v) 340.94 601 T
(e\051) 346.76 601 T
0 F
(B.1 Ov) 108 557 T
(er) 149.22 557 T
(view) 159.76 557 T
2 F
1.04 (This section pro) 108 535 P
1.04 (vides an alternati) 187.23 535 P
1.04 (v) 270.99 535 P
1.04 (e to the standard SP) 276.81 535 P
1.04 (ARC programming model for the) 375.19 535 P
-0.1 (SP) 108 521 P
-0.1 (ARC-V8E processor) 120.24 521 P
-0.1 (. SP) 219.13 521 P
-0.1 (ARC-V8 processors pro) 237.27 521 P
-0.1 (vide a lar) 352.87 521 P
-0.1 (ge number of general purpose) 397.11 521 P
1.32 (re) 108 507 P
1.32 (gisters. At an) 117.14 507 P
1.32 (y instant, the SP) 183.27 507 P
1.32 (ARC CPU has 32 w) 264.15 507 P
1.32 (orking re) 365.99 507 P
1.32 (gisters a) 410.79 507 P
1.32 (v) 451.53 507 P
1.32 (ailable. The) 457.23 507 P
1.32 (y are) 515.03 507 P
0.3 (di) 108 493 P
0.3 (vided into 8 global re) 117.04 493 P
0.3 (gisters, and 24 re) 220.73 493 P
0.3 (gisters that compose a current o) 303.45 493 P
0.3 (v) 457.09 493 P
0.3 (erlapped \322re) 462.91 493 P
0.3 (gis-) 522 493 P
-0.1 (ter windo) 108 479 P
-0.1 (w\323.) 153.26 479 P
208.05 477.8 173.15 477.8 2 L
V
0.6 H
0 Z
N
-0.1 (The SP) 173.15 479 P
348.61 477.8 206.95 477.8 2 L
V
N
-0.1 (ARC Architecture Manual, V) 206.95 479 P
388.4 477.8 347.28 477.8 2 L
V
N
-0.1 (ersion 8) 347.28 479 P
-0.1 (requires that the number of re) 388.4 479 P
-0.1 (g-) 530 479 P
(ister windo) 108 465 T
(ws on an) 161.36 465 T
(y implementation f) 203.84 465 T
(all between 2 and 32.) 295.06 465 T
0.02 (The ab) 108 443 P
0.02 (undance of re) 140.77 443 P
0.02 (gisters and the windo) 205.93 443 P
0.02 (w re) 308.02 443 P
0.02 (gister model pro) 328.85 443 P
0.02 (vided by SP) 407.37 443 P
0.02 (ARC-V8 incurs) 464.32 443 P
1.86 (se) 108 429 P
1.86 (v) 117.7 429 P
1.86 (eral dra) 123.52 429 P
1.86 (wbacks and performance penalties when implemented in high performance,) 161.51 429 P
0.28 (real-time applications associated with embedded systems such as SP) 108 415 P
0.28 (ARC-V8E. One such) 437.78 415 P
0.14 (problem encountered is the lar) 108 401 P
0.14 (ge number of re) 254.31 401 P
0.14 (gisters that may need to be sa) 330.85 401 P
0.14 (v) 472.76 401 P
0.14 (ed at conte) 478.58 401 P
0.14 (xt) 530.66 401 P
0.49 (switch time leading to high conte) 108 387 P
0.49 (xt switch o) 269.93 387 P
0.49 (v) 323.39 387 P
0.49 (erhead. Another) 329.21 387 P
0.49 (, is the dif) 406.52 387 P
0.49 (\336culty in predict-) 455.69 387 P
-0.26 (ing the number of re) 108 373 P
-0.26 (gisters that will need to be sa) 204.74 373 P
-0.26 (v) 342.23 373 P
-0.26 (ed at conte) 348.05 373 P
-0.26 (xt switch time. This results in) 399.32 373 P
(all re) 108 359 T
(gisters being sa) 132.14 359 T
(v) 205.9 359 T
(ed with associated performance penalties.) 211.72 359 T
(In embedded applications, the follo) 108 337 T
(wing f) 277.34 337 T
(actors tak) 308.22 337 T
(e precedence:) 354.42 337 T
(\321) 144 315 T
(Reduced a) 162 315 T
(v) 212.08 315 T
(erage conte) 217.9 315 T
(xt-switch times) 272.69 315 T
(\321) 144 293 T
-0.09 (Constant \050or small w) 162 293 P
-0.09 (orst-case deterministic\051 conte) 261.95 293 P
-0.09 (xt-switch and procedure-call) 402.89 293 P
(times) 162 279 T
(There are se) 108 257 T
(v) 166.33 257 T
(eral alternati) 172.15 257 T
(v) 232.16 257 T
(es kno) 237.98 257 T
(wn to accommodate the abo) 268.68 257 T
(v) 403.14 257 T
(e criteria.) 408.96 257 T
(Note:) 108 235 T
2 10 Q
0.54 (See Section D.8 of the) 144 222.33 P
250.05 221.33 238.93 221.33 2 L
V
0.5 H
N
0.54 (SP) 238.93 222.33 P
369.07 221.33 249.13 221.33 2 L
V
N
0.54 (ARC Architecture Manual, V) 249.13 222.33 P
400.44 221.33 367.96 221.33 2 L
V
N
0.54 (ersion 8) 367.96 222.33 P
0.54 (, for descriptions of other re) 400.44 222.33 P
0.54 (gister) 514.65 222.33 P
0.54 (-) 536.67 222.33 P
(windo) 144 210.33 T
(w usage models. \050Note that model \322[C]\323 in D.8 is the one described in more detail belo) 168.75 210.33 T
(w) 516.78 210.33 T
(.\051) 523.35 210.33 T
FMENDPAGE
%%EndPage: "77" 83
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(78) 72 17 T
0 F
(B.2 Single Register W) 72 721 T
(indo) 189.78 721 T
(w Model) 212.34 721 T
2 F
0.86 (An alternate mechanism for the SP) 72 677 P
0.86 (ARC-V8E windo) 242.86 677 P
0.86 (w re) 327.08 677 P
0.86 (gister programming model, The) 348.76 677 P
(Single Re) 72 663 T
(gister W) 118.82 663 T
(indo) 159.34 663 T
(w Model, is described. This Model:) 180.37 663 T
(\321) 90 641 T
(A) 108 641 T
(v) 115.78 641 T
(oids the typical windo) 121.54 641 T
(w \322o) 227.57 641 T
(v) 250.38 641 T
(er\337o) 256.2 641 T
(w\323 processing o) 277.9 641 T
(v) 355.03 641 T
(erhead) 360.85 641 T
(\321) 90 619 T
(Reduces the number of re) 108 619 T
(gisters that need to be sa) 231.12 619 T
(v) 348.53 619 T
(ed on a conte) 354.35 619 T
(xt switch) 417.82 619 T
-0.16 (This model a) 72 597 P
-0.16 (v) 134.11 597 P
-0.16 (oids using the standard SP) 139.87 597 P
-0.16 (ARC-V8 re) 264.8 597 P
-0.16 (gister windo) 320.12 597 P
-0.16 (wing mechanism; instead,) 379.33 597 P
0.2 (it treats the SP) 72 583 P
0.2 (ARC processor as a con) 141.16 583 P
0.2 (v) 256.77 583 P
0.2 (entional CPU with a \337at set of 32 general purpose) 262.59 583 P
0.22 (re) 72 569 P
0.22 (gisters. The compiler generates code to sa) 81.14 569 P
0.22 (v) 283.15 569 P
0.22 (e re) 288.97 569 P
0.22 (gisters around procedure calls when nec-) 306.65 569 P
-0.17 (essary) 72 555 P
-0.17 (. Dedicating a re) 101.21 555 P
-0.17 (gister windo) 179.84 555 P
-0.17 (w to a single process is possible. If a process has a win-) 239.04 555 P
2.07 (do) 72 541 P
2.07 (w dedicated to it, the conte) 83.7 541 P
2.07 (xt of a process is al) 223.2 541 P
2.07 (w) 325.75 541 P
2.07 (ays a) 334.3 541 P
2.07 (v) 360.45 541 P
2.07 (ailable without reference to) 366.15 541 P
0.11 (memory) 72 527 P
0.11 (. Thus, little memory access is required for a conte) 111.22 527 P
0.11 (xt switch. In the e) 354.98 527 P
0.11 (xample illus-) 440.89 527 P
1.9 (trated in Figure 3, four of the eight re) 72 513 P
1.9 (gister windo) 265.97 513 P
1.9 (ws are dedicated to four processes.) 327.23 513 P
1.07 (When an interrupt or another conte) 72 499 P
1.07 (xt switching e) 245.45 499 P
1.07 (v) 314.62 499 P
1.07 (ent is detected, the SP) 320.44 499 P
1.07 (ARC processor) 429.27 499 P
0.16 (automatically switches to a ne) 72 485 P
0.16 (w windo) 217 485 P
0.16 (w \050which is not sho) 258.53 485 P
0.16 (wn in diagram\051. Thus, the local) 352.87 485 P
(re) 72 471 T
(gisters between the reserv) 81.14 471 T
(ed windo) 205.26 471 T
(ws are reserv) 249.29 471 T
(ed for interrupt handling.) 312.41 471 T
0 F
(Figur) 92.15 196 T
(e 13:) 120.61 196 T
(Alter) 147.93 196 T
(nati) 174.4 196 T
(v) 194.29 196 T
(e W) 200.17 196 T
(indo) 220.28 196 T
(w Model f) 242.84 196 T
(or Machine with 8 Register W) 293.86 196 T
(indo) 447.95 196 T
(ws) 470.51 196 T
2 F
1.34 (T) 72 158 P
1.34 (able3 belo) 78.37 158 P
1.34 (w sho) 129.07 158 P
1.34 (ws ho) 158.43 158 P
1.34 (w a Single Re) 187.8 158 P
1.34 (gister W) 258.63 158 P
1.34 (indo) 300.48 158 P
1.34 (w Model compiler will use re) 321.52 158 P
1.34 (gisters.) 469.67 158 P
0.54 (Notice that the \322in,) 72 144 P
0.54 (\323 \322local,) 164.09 144 P
0.54 (\323 and \322out\323 grouping ha) 203.77 144 P
0.54 (v) 320.99 144 P
0.54 (e been replaced by a \337at re) 326.81 144 P
0.54 (gister \336le) 458.46 144 P
0.71 (%r0 through %r31. Ev) 72 130 P
0.71 (en with tw) 182.59 130 P
0.71 (o re) 234.55 130 P
0.71 (gisters reserv) 253.4 130 P
0.71 (ed for future use, 11 re) 317.58 130 P
0.71 (gisters are no) 430.24 130 P
0.71 (w) 495.34 130 P
(a) 72 116 T
(v) 77.09 116 T
(ailable for local v) 82.79 116 T
(ariables, thereby minimizing e) 166.8 116 T
(xpensi) 312.6 116 T
(v) 343.63 116 T
(e load/store operations.) 349.45 116 T
72 81 504 729 C
148.47 206 427.53 445 C
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 -201 -115 199 225 267.05 227 154.47 212 FMBEGINEPSF
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userdict /Adobe_Illustrator881 72 dict dup begin put
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3 -1 roll pop
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-156 -4.5 L
-123 -4.5 L
s
-139.5 0 m
S
U
u
-123 -13.5 m
-123 -4.5 L
-156 -4.5 L
-156 -13.5 L
-123 -13.5 L
s
-139.5 -9 m
S
U
U
u
0 O
0 g
1 w
/_Univers-CondensedBold 8 12 0 0 z
[1 0 0 1 -156 -25.5]e
5 (Stack)t
T
U
U
u
u
/_Helvetica-Black 8 10 0 1 z
[1 0 0 1 -176 172.5]e
1 (\245)t
1 (\245)t
1 (\245)t
T
U
u
u
0 R
0 G
0.5 w
-159 140.5 m
-159 149.5 L
-192 149.5 L
-192 140.5 L
-159 140.5 L
s
-175.5 145 m
S
U
u
-159 131.5 m
-159 140.5 L
-192 140.5 L
-192 131.5 L
-159 131.5 L
s
-175.5 136 m
S
U
u
-159 122.5 m
-159 131.5 L
-192 131.5 L
-192 122.5 L
-159 122.5 L
s
-175.5 127 m
S
U
U
u
0 O
0 g
1 w
/_Univers-CondensedBold 8 12 0 0 z
[1 0 0 1 -192 110.5]e
5 (Stack)t
T
U
U
u
u
/_Helvetica-Black 8 10 0 1 z
[1 0 0 1 156 196.5]e
1 (\245)t
1 (\245)t
1 (\245)t
T
U
u
u
0 R
0 G
0.5 w
173 164.5 m
173 173.5 L
140 173.5 L
140 164.5 L
173 164.5 L
s
156.5 169 m
S
U
u
173 155.5 m
173 164.5 L
140 164.5 L
140 155.5 L
173 155.5 L
s
156.5 160 m
S
U
u
173 146.5 m
173 155.5 L
140 155.5 L
140 146.5 L
173 146.5 L
s
156.5 151 m
S
U
U
u
0 O
0 g
1 w
/_Univers-CondensedBold 8 12 0 0 z
[1 0 0 1 140 134.5]e
5 (Stack)t
T
U
U
-646.5 218 m
649.5 218 L
N
u
0 O
0 g
-36.5 -114 m
-36.5 -57 L
-146.5 -57 L
-146.5 -114 L
-36.5 -114 L
f
1 g
0 R
0 G
0.5 w
-45.5 -105 m
-45.5 -48 L
-155.5 -48 L
-155.5 -105 L
-45.5 -105 L
b
u
0 g
1 w
/_Univers-CondensedBold 8 11 0 0 z
[1 0 0 1 -147.5 -63.5]e
28 (r0 - r7 Global Register)t
27 (r8 - r31 Local Registers)t
T
U
U
u
/_Univers-CondensedBold 8 10 0 0 z
[1 0 0 1 -121.7139 -97.5]e
17 (Working Registers)t
T
U
u
0.85 g
0 R
0 G
-127.7139 -98 m
-127.7139 -79 L
-146.7139 -79 L
-146.7139 -98 L
-127.7139 -98 L
b
-137.2139 -88.5 m
B
U
%%PageTrailer
%%Trailer
Adobe_Illustrator881 /terminate get exec
Adobe_customcolor /terminate get exec
Adobe_cshow /terminate get exec
Adobe_cmykcolor /terminate get exec
Adobe_packedarray /terminate get exec
%%EOF
%%EndDocument
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
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[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
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7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(79) 528 17 T
0 F
(B.3 Conclusion) 108 387 T
2 F
0.97 (The abo) 108 365 P
0.97 (v) 147.78 365 P
0.97 (e alternati) 153.6 365 P
0.97 (v) 201.92 365 P
0.97 (e windo) 207.74 365 P
0.97 (w re) 246.74 365 P
0.97 (gister model, The Single W) 268.52 365 P
0.97 (indo) 404.25 365 P
0.97 (w Re) 425.28 365 P
0.97 (gister Model, pro-) 451.07 365 P
1.45 (vides enhanced functionality for the SP) 108 351 P
1.45 (ARC-V8E processor) 303.12 351 P
1.45 (. Both impro) 403.56 351 P
1.45 (v) 467.29 351 P
1.45 (ements in the) 473.11 351 P
0.15 (speed of procedure calls and returns and the guaranteeing of constant or w) 108 337 P
0.15 (orst-case deter-) 466.22 337 P
0.13 (ministic conte) 108 323 P
0.13 (xt switch times are accommodated by the enhanced windo) 175.62 323 P
0.13 (w re) 456.27 323 P
0.13 (gister model.) 477.21 323 P
(Other solutions ha) 108 309 T
(v) 195.76 309 T
(e been proposed and may be equally ef) 201.58 309 T
(\336cient.) 388.22 309 T
2 10 Q
(Compatibility Note:) 108 284.33 T
0.76 (Assembly language or computer output from SP) 144 272.33 P
0.76 (ARC-V8 ABI conforming programs will not run) 340.98 272.33 P
(on the single re) 144 260.33 T
(gister windo) 205.23 260.33 T
(w model.) 254.7 260.33 T
0 F
(Register) 161.73 692.33 T
(Use) 253.23 692.33 T
(Comments) 382.45 692.33 T
2 12 Q
(r31) 149.5 671 T
2 10 Q
(Stack Pointer) 221.5 672.33 T
(also referred to as) 312.5 672.33 T
0 F
(sp) 386.36 672.33 T
2 12 Q
(r30) 149.5 649 T
2 10 Q
(Frame Pointer) 221.5 650.33 T
(also referred to as) 312.5 650.33 T
0 F
(fp) 386.36 650.33 T
2 12 Q
(r25 - r29) 149.5 627 T
2 10 Q
(Scratch Re) 221.5 628.33 T
(gisters) 264.95 628.33 T
(used by the compiler for temporary v) 312.5 628.33 T
(alues) 461.11 628.33 T
2 12 Q
(r24) 149.5 605 T
2 10 Q
(Return v) 221.5 606.33 T
(alue) 255.97 606.33 T
2.68 (start of quad precision v) 312.5 606.33 P
2.68 (alue or address of) 419.64 606.33 P
0 F
(struct) 312.5 594.33 T
2 12 Q
(r16 - r23) 149.5 573 T
2 10 Q
(Input P) 221.5 574.33 T
(arameters) 250.52 574.33 T
(additional parameters placed on the stack) 312.5 574.33 T
2 12 Q
(r15) 149.5 551 T
2 10 Q
(Return Address) 221.5 552.33 T
(address of the procedure call instruction) 312.5 552.33 T
2 12 Q
(r4 - r14) 149.5 529 T
2 10 Q
(Re) 221.5 530.33 T
(gister V) 232.46 530.33 T
(ariables) 263.29 530.33 T
(local v) 312.5 530.33 T
(ariables) 339.19 530.33 T
2 12 Q
(r3) 149.5 507 T
2 10 Q
(Special Use) 221.5 508.33 T
1 F
(r) 312.5 508.33 T
(eserved) 316.02 508.33 T
2 F
( for the user) 346.56 508.33 T
2 12 Q
(r1 - r2) 149.5 485 T
2 10 Q
(Reserv) 221.5 486.33 T
(ed) 249.12 486.33 T
1 F
7.04 (r) 312.5 486.33 P
7.04 (eserved) 316.02 486.33 P
2 F
7.04 ( for future \050position-independent) 346.56 486.33 P
(code\051) 312.5 474.33 T
2 12 Q
(r0) 149.5 453 T
2 10 Q
(Zero V) 221.5 454.33 T
(alue) 248.99 454.33 T
(al) 312.5 454.33 T
(w) 319.62 454.33 T
(ays contains the v) 326.74 454.33 T
(alue zero) 397.87 454.33 T
0 12 Q
(T) 163.9 431 T
(able 15:) 170.8 431 T
(Register Usage in the Single Register W) 214.13 431 T
(indo) 417.22 431 T
(w Model) 439.78 431 T
143.5 704.75 143.5 445.25 2 L
V
0.5 H
0 Z
N
215.5 683.5 215.5 444.75 2 L
V
N
306.5 683.5 306.5 444.75 2 L
V
N
504.5 704.75 504.5 445.25 2 L
V
N
143.25 705 504.75 705 2 L
V
N
143.75 686.25 504.25 686.25 2 L
V
N
143.75 683.75 504.25 683.75 2 L
V
N
143.25 663 504.75 663 2 L
V
N
143.25 641 504.75 641 2 L
V
N
143.25 619 504.75 619 2 L
V
N
143.25 587 504.75 587 2 L
V
N
143.25 565 504.75 565 2 L
V
N
143.25 543 504.75 543 2 L
V
N
143.25 521 504.75 521 2 L
V
N
143.25 499 504.75 499 2 L
V
N
143.25 467 504.75 467 2 L
V
N
143.25 445 504.75 445 2 L
V
N
FMENDPAGE
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7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
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(80) 72 17 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
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[ 1 1 0 0 0 0 1]
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[ 0 1 0 0 1 0 1]
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7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(81) 528 17 T
0 14 Q
(Annex C Summary of Operation Codes, ASIs and ASRs) 153.47 623.67 T
2 12 Q
(\050Normati) 294.58 601 T
(v) 338.27 601 T
(e\051) 344.09 601 T
0 F
(C.1 Operation Codes) 108 557 T
2 F
(\321) 126 535 T
(Di) 144 535 T
(vide Step-DIVScc: op=2, op3= 011101) 155.7 535 T
2 9.6 Q
(2) 344.22 532 T
2 12 Q
( /\0501D) 349.02 535 T
2 9.6 Q
(16) 374.02 532 T
2 12 Q
(\051) 383.62 535 T
(\321) 126 513 T
(Scan-SCAN: op=2, op3=101100) 144 513 T
2 9.6 Q
(2) 301.2 510 T
2 12 Q
(/ \0502C) 306 513 T
2 9.6 Q
(16) 330.34 510 T
2 12 Q
(\051) 339.94 513 T
2 10 Q
(Compatibility Note) 108 488.33 T
(The SCAN operation code, op3= 2C) 144 476.33 T
2 8 Q
(16) 290.18 473.83 T
2 10 Q
(, con\337icts with the SP) 298.18 476.33 T
(ARC-V9 opcode for MO) 384.77 476.33 T
(Vcc.) 484.53 476.33 T
0 12 Q
(C.2 ASI Assignments) 108 433 T
2 F
-0.1 (The follo) 108 411 P
-0.1 (wing re) 151.93 411 P
-0.1 (vision is made to the recommended ASI assignments for ASI\325) 187.85 411 P
-0.1 (s 30) 483.89 411 P
2 9.6 Q
-0.08 (16) 503.46 408 P
2 12 Q
-0.1 (-FF) 513.06 411 P
2 9.6 Q
-0.08 (16) 530.4 408 P
2 12 Q
(from T) 108 397 T
(able I-1 in the SP) 140.7 397 T
(ARC-V8 Architecture Manual:) 222.92 397 T
0 F
(C.3 ASRs) 108 161 T
2 F
(\321) 126 139 T
(ASR-17: T) 144 139 T
(rap SVT Flag, bit 0) 196.58 139 T
0 10 Q
(ASI) 228.16 346.33 T
(Function) 342.83 346.33 T
2 F
(30-6F) 204.5 326.33 T
(unassigned) 280.5 326.33 T
(70-7F) 204.5 306.33 T
1 F
(r) 280.5 306.33 T
(eserved) 284.02 306.33 T
2 F
( for diagnostic f) 314.56 306.33 T
(acility) 378.06 306.33 T
(80-BF) 204.5 286.33 T
1 F
(r) 280.5 286.33 T
(eserved) 284.02 286.33 T
2 F
(*) 314.56 286.33 T
(C0-EF) 204.5 266.33 T
(unassigned*) 280.5 266.33 T
(F0-FF) 204.5 246.33 T
1 F
(r) 280.5 246.33 T
(eserved) 284.02 246.33 T
2 F
( for diagnostic f) 314.56 246.33 T
(acility*) 378.06 246.33 T
0 F
(*) 296.32 226.33 T
2 F
(may be accessible in user mode) 301.32 226.33 T
0 12 Q
(T) 255.05 205 T
(able 16:) 261.95 205 T
(ASI Assignments) 305.28 205 T
198.5 358.75 198.5 219.25 2 L
V
0.5 H
0 Z
N
449.5 358.75 449.5 219.25 2 L
V
N
198.25 359 449.75 359 2 L
V
N
198.75 340.25 449.25 340.25 2 L
V
N
198.75 337.75 449.25 337.75 2 L
V
N
198.75 240.25 449.25 240.25 2 L
V
N
198.75 237.75 449.25 237.75 2 L
V
N
198.25 219 449.75 219 2 L
V
N
FMENDPAGE
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7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(82) 72 17 T
FMENDPAGE
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612 792 0 FMBEGINPAGE
[0 0 0 1 0 0 0]
[ 0 1 1 0 1 0 0]
[ 1 0 1 0 0 1 0]
[ 1 1 0 0 0 0 1]
[ 1 0 0 0 0 1 1]
[ 0 1 0 0 1 0 1]
[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 475.99 748 T
(83) 528 17 T
0 14 Q
(Annex D List of options) 249.72 623.67 T
2 12 Q
(\050Normati) 294.58 601 T
(v) 338.27 601 T
(e\051) 344.09 601 T
0 F
(D) 108 557 T
(.1 Intr) 116.42 557 T
(oduction) 154.87 557 T
2 F
0.78 (The list included in this anne) 108 535 P
0.78 (x sho) 250.71 535 P
0.78 (ws which V8E e) 276.86 535 P
0.78 (xtensions to the SP) 358 535 P
0.78 (ARC-V8 architec-) 450.91 535 P
2.37 (ture there are, in which combinations the) 108 521 P
2.37 (y are allo) 318.36 521 P
2.37 (wed or advised, and where in the) 367.46 521 P
(SP) 108 507 T
(ARC-V8E spec the) 120.24 507 T
(y are described.) 212.71 507 T
1.4 (The options are numbered according to the chapters in the SP) 108 485 P
1.4 (ARC-V8E spec in which) 416.15 485 P
1.54 (the) 108 471 P
1.54 (y are described; the sub numbering does, though, not necessarily follo) 122.48 471 P
1.54 (w the section) 473.59 471 P
(numbering and subsection numbering as in the SP) 108 457 T
(ARC-V8E spec..) 347.22 457 T
0 F
(D) 108 413 T
(.2 Instructions) 116.42 413 T
2 F
(The follo) 108 391 T
(wing options are de\336ned.) 152.03 391 T
(The) 108 377 T
(y can be implemented not at all, separately or in an) 126.48 377 T
(y combination:) 371.26 377 T
(2.1. Di) 108 355 T
(vide Step:) 140.7 355 T
(See Chapter 2.1) 288 355 T
(2.2. Scan) 108 341 T
(See Chapter 2.2) 288 341 T
(2.3. Multiply Accumulate) 108 327 T
(See Chapter 2.3) 288 327 T
(2.4. Alternate W) 108 313 T
(indo) 187.5 313 T
(w Pointer) 208.54 313 T
(See Chapter 2.4) 288 313 T
(2.5. P) 108 299 T
(artial WRPSR) 135.49 299 T
(See Chapter 2.5) 288 299 T
(2.6. Non Pri) 108 285 T
(vile) 166.37 285 T
(ged ASI Access) 184.19 285 T
(See Chapter 2.6) 288 285 T
0 F
(D) 108 241 T
(.3 MMU) 116.42 241 T
2 F
(None or just one of the options belo) 108 219 T
(w can be implemented:) 280.02 219 T
(3.1. Basic reference MMU) 108 197 T
(See SP) 288 197 T
(ARC-V8 spec) 320.57 197 T
(3.2. Embedded Reference MMU) 108 183 T
(See Chapter 3.2) 288 183 T
(3.3. Cacheability Control) 108 169 T
(See Chapter 3.3) 288 169 T
FMENDPAGE
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[ 0 0 1 0 1 1 0]
7 FrameSetSepColors
FrameNoSep
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
2 12 Q
0 X
0 0 0 1 0 0 0 K
(SPARC-V8E) 72 748 T
1 F
(SP) 265.19 748 T
(ARC-V8E Release 1 Ar) 277.44 748 T
(c) 391.64 748 T
(hitectur) 396.79 748 T
(e Speci\336cation) 433.68 748 T
2 F
(84) 72 17 T
0 F
(D) 72 721 T
(.4 T) 80.42 721 T
(raps) 105.54 721 T
2 F
(The option belo) 72 699.3 T
(w may or may not be supported:) 147.7 699.3 T
(4.1. Single V) 72 677.6 T
(ector T) 134 677.6 T
(rapping) 167.9 677.6 T
(See Chapter 4.) 252 677.6 T
0 F
(D) 72 633.9 T
(.5 P) 80.42 633.9 T
(eripheral Extensions) 105.52 633.9 T
2 F
(5.1. Input Handler:) 72 612.2 T
(See Chapter 5.2) 288 612.2 T
-0.03 ( An) 90 598.5 P
-0.03 (y number of input handlers can be supported. The) 107.46 598.5 P
-0.03 (y will usually b) 346.04 598.5 P
-0.03 (ut not necessarily) 420.06 598.5 P
(be used as inputs to other options as described in chapter 5.) 90 584.8 T
(5.2. Interrupt Controller:) 72 563.1 T
(See Chapter 5.3.1 and 5.3.2.) 288 563.1 T
0.14 ( One or more such controllers may be implemented. The) 90 549.4 P
0.14 (y will usually be preceded by) 362.34 549.4 P
-0.25 (Input Handlers <5.1>, and if more than one Interrupt Controller <5.2> is implemented,) 90 535.7 P
(then their outputs are combined as an Extended Interrupt Controller <5.3>.) 90 522 T
(5.3. Extended Interrupt Controller:) 72 500.3 T
(See Chapter 5.3.3.) 288 500.3 T
0.36 (If more than one Interrupt Controller <5.2> is implemented then the) 90 486.6 P
0.36 (y should be com-) 419.92 486.6 P
(bined into an Extended Interrupt Controller <5.3>.) 90 472.9 T
(5.4. Inte) 72 451.2 T
(grated Interrupt Request Controller:) 111.48 451.2 T
(See Chapter 5.4.) 288 451.2 T
(None or one \322IIRC\323 <5.4> can be implemented.) 90 437.5 T
(<5.4> can not be implemented together with circuitry <5.2> or <5.3>.) 90 423.8 T
(5.5. Programmable Pulse Generators:) 72 402.1 T
(See Chapter 5.5.1.) 288 402.1 T
1.05 (An) 90 388.4 P
1.05 (y number of such Counter/T) 104.48 388.4 P
1.05 (imer/Pulsers may be implemented. The) 244.24 388.4 P
1.05 (y will usually) 436.56 388.4 P
0.09 (be preceded by Input Handlers <5.1>; their outputs will usually be connected to Inter-) 90 374.7 P
0.61 (rupt Controllers <5.2> b) 90 361 P
0.61 (ut the) 208.44 361 P
0.61 (y can also be otherwise connected; that is implementor) 235.87 361 P
(de\336ned.) 90 347.3 T
(5.6. Simple Counters) 72 325.6 T
(See Chapter 5.5.2.) 288 325.6 T
2.01 (An) 90 311.9 P
2.01 (y number of Simple Counters may be implemented. The) 104.48 311.9 P
2.01 (y may be preceded by) 390.67 311.9 P
0.75 (Input Handlers <5.1>; their outputs may be connected to Interrupt circuitry <5.2> or) 90 298.2 P
(<5.4>) 90 284.5 T
(5.7. Simple T) 72 262.8 T
(imers) 136.92 262.8 T
(See Chapter 5.5.3.) 288 262.8 T
0.42 (An) 90 249.1 P
0.42 (y number of Simple T) 104.48 249.1 P
0.42 (imers may be implemented. The) 211.76 249.1 P
0.42 (y may be preceded by Input) 368.25 249.1 P
(Handlers <5.1>; their outputs may be connected to Interrupt circuitry <5.2> or <5.4>.) 90 235.4 T
0 F
(D) 72 191.7 T
(.6 Diagnostics) 80.42 191.7 T
2 F
-0.3 (None or just one of the options belo) 72 170 P
-0.3 (w may be implemented: The) 241.95 170 P
-0.3 (y share functionality; their) 377.9 170 P
(implementation is optimized for dif) 72 156.3 T
(ferent desires.) 242.36 156.3 T
(6.1. T) 72 134.6 T
(race enhancing DSU:) 99.91 134.6 T
(See Chapter 6.1.1.) 288 134.6 T
(A ne) 90 120.9 T
(xt v) 112.81 120.9 T
(ersion of the SP) 130.97 120.9 T
(ARC-V8E spec will contain more details.) 206.2 120.9 T
(6.2. Pin ef) 72 99.2 T
(fecti) 121.03 99.2 T
(v) 142.06 99.2 T
(e DSU:) 147.88 99.2 T
(See Chapter 6.1.2.) 288 99.2 T
( A ne) 90 85.5 T
(xt v) 115.81 85.5 T
(ersion of the SP) 133.97 85.5 T
(ARC-V8E spec will contain more details.) 209.2 85.5 T
FMENDPAGE
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%%+ Times-Italic
%%+ Times-Roman
%%+ NewCenturySchlbk-Roman
%%+ NewCenturySchlbk-Bold
%%+ NewCenturySchlbk-Italic
%%+ Helvetica
%%+ Helvetica-Oblique
%%+ Symbol
%%+ Courier-Bold
%%+ Helvetica-Bold
%%+ NewCenturySchlbk-BoldItalic
%%+ Times-BoldItalic
%%+ Courier
%%EOF
| PostScript | 2 | JeeeK/awesome-cpus | SPARC/architecture-v8e.ps | [
"CC0-1.0"
]
|
# This module deals with transforming data between the form that is passed to
# user macros and returned from them, and the internal compiler AST form used
# otherwise. Also, deals with inserting macros into compilation environments.
ast-errors = require \./esvalid-partial
{ is-expression } = require \esutils .ast
statementify = require \./es-statementify
# Only used directly by aliases
import-compilerspace-macro = (env, name, func) ->
env.import-macro name, func
# Only used by transform macros, which run on the initial AST
create-transform-macro = (env, func) ->
(...args) ->
result = func.apply env, args
if typeof! result is \Array
return result
else return [ result ]
module.exports = {
import-compilerspace-macro,
create-transform-macro
}
| LiveScript | 4 | 0xflotus/eslisp | src/import-macro.ls | [
"ISC"
]
|
/*
* Copyright (c) 2021 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Empty file */
| Linker Script | 0 | ldalek/zephyr | include/zephyr/linker/app_smem_pinned_aligned.ld | [
"Apache-2.0"
]
|
{% if some_eval %}
Clearly, the song is: {{ content }}.
{% endif %} | Twig | 3 | tidytrax/cphalcon | tests/_data/fixtures/views/layouts/twig.twig | [
"BSD-3-Clause"
]
|
464405544153541662433126634024104464024334635453666206521002236144110431041441224436265610520315133260432562454316054055,15.8
533061544350530124240251006342531510013555100246015243103140433545113505461532430200121221000000000000000645231402235562,15.8
304046201516261304012542234351300043331134143333150233310202000045351465451444063325142360444010146000312444065463333150,15.8
304056460433331304010135422412300061021140451333156103650641000046124122561444014246546452444026153150001444054333333332,15.8
304054646121332304032564610232300014646415632333152164515631000046426515630444062605513330444041413350500444063244440555,15.8
304054640640611344010135440342344061024661361333154105011341044024563332362444064543332111444060324054661444041324654460,15.8
304066613334660344055413333260344031103334134333153502515134044043603144134444053203333234444063403450150444025402644161,15.8
563332663243231010651440163542250641513503011631541332305141151000203333251440333020351642651103565046641646543333054332,15.8
613244444444440510043001110000014333333563360210043001114450421544444444410121556555555566321111116111106621166511165106,15.8
533333333333331610135046645512300146154465141611123555551141533432111115461236023166365642336466634665141232313313235300,15.8
5222121210111341135554360240200235524406415512142246543446426242612206603346650362136153215,13.7
51333652033351640640342043342651315600363652533311463146245131116336156432645515566243635162406645415541233405615604561246615135633516066561545332431431604451612051032420616065645103363616544240446532,20.10
5333113052633202345115616,5.5
42133332340511613410543256133055,8.4
515610431,3.3
5446066306115046224544652,5.5 | Myghty | 0 | Mythius/Minigames | UnderTile/levels.myt | [
"MIT"
]
|
# Verify that we build in parallel correctly. We do this by running two tasks,
# each of which requires the other to have run before it is willing to complete.
#
#
# The wait-for-file script will exit after ~1s, so if both commands aren't
# started within that time period then the build will fail.
# RUN: rm -rf %t.build
# RUN: mkdir -p %t.build
# RUN: cp %s %t.build/build.ninja
# RUN: cp %S/Inputs/wait-for-file %t.build
# RUN: %{llbuild} ninja build --chdir %t.build --no-db
rule CUSTOM
command = ${COMMAND}
build cleanup: CUSTOM
command = rm -f node-{A,B}-semaphore
build node-A: CUSTOM cleanup
command = touch node-B-semaphore && ./wait-for-file node-A-semaphore
build node-B: CUSTOM cleanup
command = touch node-A-semaphore && ./wait-for-file node-B-semaphore
build both: phony node-A node-B
default both
| Ninja | 5 | uraimo/swift-llbuild | tests/Ninja/Build/parallel.ninja | [
"Apache-2.0"
]
|
defmodule ChatApiWeb.ForwardingAddressControllerTest do
use ChatApiWeb.ConnCase, async: true
import ChatApi.Factory
alias ChatApi.ForwardingAddresses.ForwardingAddress
@update_attrs %{
forwarding_email_address: "[email protected]",
source_email_address: "[email protected]",
description: "some updated description",
state: "some updated state"
}
@invalid_attrs %{
forwarding_email_address: nil
}
setup %{conn: conn} do
account = insert(:account)
user = insert(:user, account: account)
forwarding_address = insert(:forwarding_address, account: account)
conn = put_req_header(conn, "accept", "application/json")
authed_conn = Pow.Plug.assign_current_user(conn, user, [])
{:ok,
conn: conn,
authed_conn: authed_conn,
account: account,
forwarding_address: forwarding_address}
end
describe "index" do
test "lists all forwarding addresses", %{
authed_conn: authed_conn,
forwarding_address: forwarding_address
} do
resp = get(authed_conn, Routes.forwarding_address_path(authed_conn, :index))
ids = json_response(resp, 200)["data"] |> Enum.map(& &1["id"])
assert ids == [forwarding_address.id]
end
end
describe "show forwarding_address" do
test "shows forwarding_address by id", %{
account: account,
authed_conn: authed_conn
} do
forwarding_address = insert(:forwarding_address, %{account: account})
conn =
get(
authed_conn,
Routes.forwarding_address_path(authed_conn, :show, forwarding_address.id)
)
assert json_response(conn, 200)["data"]
end
test "renders 404 when asking for another user's forwarding_address", %{
authed_conn: authed_conn
} do
# Create a new account and give it a forwarding_address
another_account = insert(:account)
forwarding_address =
insert(:forwarding_address, %{
forwarding_email_address: "[email protected]",
account: another_account
})
# Using the original session, try to delete the new account's forwarding_address
conn =
get(
authed_conn,
Routes.forwarding_address_path(authed_conn, :show, forwarding_address.id)
)
assert json_response(conn, 404)
end
end
describe "create forwarding_address" do
test "renders forwarding_address when data is valid", %{
authed_conn: authed_conn,
account: account
} do
resp =
post(authed_conn, Routes.forwarding_address_path(authed_conn, :create),
forwarding_address:
params_for(:forwarding_address,
account: account,
forwarding_email_address: "[email protected]"
)
)
assert %{"id" => id} = json_response(resp, 201)["data"]
resp = get(authed_conn, Routes.forwarding_address_path(authed_conn, :show, id))
account_id = account.id
assert %{
"id" => ^id,
"account_id" => ^account_id,
"object" => "forwarding_address",
"forwarding_email_address" => "[email protected]"
} = json_response(resp, 200)["data"]
end
test "renders errors when data is invalid", %{authed_conn: authed_conn} do
conn =
post(authed_conn, Routes.forwarding_address_path(authed_conn, :create),
forwarding_address: @invalid_attrs
)
assert json_response(conn, 422)["errors"] != %{}
end
end
describe "update forwarding_address" do
test "renders forwarding_address when data is valid", %{
authed_conn: authed_conn,
forwarding_address: %ForwardingAddress{id: id} = forwarding_address
} do
conn =
put(authed_conn, Routes.forwarding_address_path(authed_conn, :update, forwarding_address),
forwarding_address: @update_attrs
)
assert %{"id" => ^id} = json_response(conn, 200)["data"]
conn = get(authed_conn, Routes.forwarding_address_path(authed_conn, :show, id))
account_id = forwarding_address.account_id
assert %{
"id" => ^id,
"account_id" => ^account_id,
"object" => "forwarding_address",
"forwarding_email_address" => "[email protected]",
"source_email_address" => "[email protected]",
"description" => "some updated description",
"state" => "some updated state"
} = json_response(conn, 200)["data"]
end
test "renders errors when data is invalid", %{
authed_conn: authed_conn,
forwarding_address: forwarding_address
} do
conn =
put(authed_conn, Routes.forwarding_address_path(authed_conn, :update, forwarding_address),
forwarding_address: @invalid_attrs
)
assert json_response(conn, 422)["errors"] != %{}
end
test "renders 404 when editing another account's forwarding_address",
%{authed_conn: authed_conn} do
# Create a new account and give it a forwarding_address
another_account = insert(:account)
forwarding_address =
insert(:forwarding_address, %{
forwarding_email_address: "[email protected]",
account: another_account
})
# Using the original session, try to update the new account's forwarding_address
conn =
put(
authed_conn,
Routes.forwarding_address_path(authed_conn, :update, forwarding_address),
forwarding_address: @update_attrs
)
assert json_response(conn, 404)
end
end
describe "delete forwarding_address" do
test "deletes chosen forwarding_address", %{
authed_conn: authed_conn,
forwarding_address: forwarding_address
} do
conn =
delete(
authed_conn,
Routes.forwarding_address_path(authed_conn, :delete, forwarding_address)
)
assert response(conn, 204)
assert_error_sent(404, fn ->
get(authed_conn, Routes.forwarding_address_path(authed_conn, :show, forwarding_address))
end)
end
test "renders 404 when deleting another account's forwarding_address",
%{authed_conn: authed_conn} do
# Create a new account and give it a forwarding_address
another_account = insert(:account)
forwarding_address =
insert(:forwarding_address, %{
forwarding_email_address: "[email protected]",
account: another_account
})
# Using the original session, try to delete the new account's forwarding_address
conn =
delete(
authed_conn,
Routes.forwarding_address_path(authed_conn, :delete, forwarding_address)
)
assert json_response(conn, 404)
end
end
end
| Elixir | 4 | ZmagoD/papercups | test/chat_api_web/controllers/forwarding_address_controller_test.exs | [
"MIT"
]
|
object SelectLanguageForm: TSelectLanguageForm
Left = 200
Top = 108
BorderIcons = [biSystemMenu]
BorderStyle = bsDialog
Caption = 'SelectLanguageForm'
ClientHeight = 140
ClientWidth = 297
Color = clBtnFace
Font.Charset = DEFAULT_CHARSET
Font.Color = clWindowText
Font.Height = -11
Font.Name = 'MS Sans Serif'
Font.Style = []
OldCreateOrder = True
Scaled = False
DesignSize = (
297
140)
PixelsPerInch = 96
TextHeight = 13
object Bevel: TBevel
Left = 0
Top = 97
Width = 297
Height = 1
Anchors = [akLeft, akRight, akBottom]
Shape = bsTopLine
end
object CancelButton: TNewButton
Left = 214
Top = 108
Width = 75
Height = 23
Anchors = [akRight, akBottom]
Cancel = True
Caption = '*'
ModalResult = 2
TabOrder = 2
end
object OKButton: TNewButton
Left = 133
Top = 108
Width = 75
Height = 23
Anchors = [akRight, akBottom]
Caption = '*'
Default = True
ModalResult = 1
TabOrder = 1
end
object MainPanel: TPanel
Left = 0
Top = 0
Width = 297
Height = 97
Anchors = [akLeft, akTop, akRight, akBottom]
BevelOuter = bvNone
Color = clWindow
TabOrder = 0
DesignSize = (
297
97)
object IconBitmapImage: TBitmapImage
Left = 8
Top = 8
Width = 32
Height = 32
end
object LangCombo: TNewComboBox
Left = 56
Top = 56
Width = 233
Height = 21
Style = csDropDownList
Anchors = [akLeft, akTop, akRight]
DropDownCount = 16
Sorted = True
TabOrder = 1
end
object SelectLabel: TNewStaticText
Left = 56
Top = 8
Width = 233
Height = 39
Anchors = [akLeft, akTop, akRight]
AutoSize = False
Caption = '*'
TabOrder = 0
WordWrap = True
end
end
end
| Pascal | 3 | Patriccollu/issrc | Projects/SelLangForm.dfm | [
"FSFAP"
]
|
doctype
html
head
title "Swift is like TypeScript"
meta (:charset utf-8)
link (:rel stylesheet) (:href css/style.css)
link (:rel stylesheet) (:href css/highlightjs-github.css)
script (:src js/highlight.9.12.0.js)
script "hljs.initHighlightingOnLoad();"
body
a (:target _blank)
:href https://github.com/alhazmy13/swift-is-like-TypeScript
img#fork-me (:src https://raw.githubusercontent.com/alhazmy13/swift-is-like-typescript/gh-pages/fork-me.png)
#note
= "Swift is like TypeScript"
.section
.title BASICS
.case (.name "Hello World") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/hello-world.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/hello-world.ts)
.case (.name "Variables And Constants") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/variables-and-constants.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/variables-and-constants.ts)
.case (.name "Explicit Types") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/explicit-types.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/explicit-types.ts)
.case (.name "Type Coercion") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/type-coercion.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/type-coercion.ts)
.case (.name "String Interpolation") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/string-interpolation.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/string-interpolation.ts)
.case (.name "Range Operator") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/range-operator.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/range-operator.ts)
.case (.name "Inclusive Range Operator") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/inclusive-range-operator.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/inclusive-range-operator.ts)
.section
.title COLLECTIONS
.case (.name "Arrays") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/arrays.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/arrays.ts)
.case (.name "Maps") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/maps.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/maps.ts)
.case (.name "Empty Collections") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/empty-collections.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/empty-collections.ts)
.section
.title FUNCTIONS
.case (.name "Functions") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/functions.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/functions.ts)
.case (.name "Tuple Return") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/tuple-return.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/tuple-return.ts)
.case (.name "Variable Number Of Arguments") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/variable-number-of-arguments.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/variable-number-of-arguments.ts)
.case (.name "Function Type") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/function-type.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/function-type.ts)
.case (.name "Map") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/map.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/map.ts)
.case (.name "Sort") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/sort.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/sort.ts)
.case (.name "Named Arguments") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/named-arguments.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/named-arguments.ts)
.section
.title CLASSES
.case (.name "Declaration") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/declaration.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/declaration.ts)
.case (.name "Usage") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/usage.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/usage.ts)
.case (.name "Subclass") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/subclass.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/subclass.ts)
.case (.name "Checking Type") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/checking-type.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/checking-type.ts)
.case (.name "Pattern Matching") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/pattern-matching.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/pattern-matching.ts)
.case (.name "Downcasting") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/downcasting.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/downcasting.ts)
.case (.name "Protocol") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/protocol.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/protocol.ts)
.case (.name "Extensions") $ .pair
.card (.lang Swift) $ pre.code $ code (@insert code/extensions.swift)
.card (.lang TypeScript) $ pre.code $ code (@insert code/extensions.ts)
| Cirru | 4 | alhazmy13/swift-is-like-typescript | index.cirru | [
"MIT"
]
|
[Files]
Source: RevitPythonShell\bin\Debug 2014\PythonConsoleControl.dll; DestDir: {app};
Source: RevitPythonShell\bin\Debug 2014\RevitPythonShell.dll; DestDir: {app};
Source: RevitPythonShell\bin\Debug 2014\RpsRuntime.dll; DestDir: {app};
Source: RequiredLibraries\ICSharpCode.AvalonEdit.dll; DestDir: {app};
Source: RequiredLibraries\IronPython.dll; DestDir: {app};
Source: RequiredLibraries\IronPython.Modules.dll; DestDir: {app};
Source: RequiredLibraries\Microsoft.Scripting.Metadata.dll; DestDir: {app};
Source: RequiredLibraries\Microsoft.Dynamic.dll; DestDir: {app};
Source: RequiredLibraries\Microsoft.Scripting.dll; DestDir: {app};
Source: RevitPythonShell\RevitPythonShell.xml; DestDir: {userappdata}\RevitPythonShell_Vasari; Flags: onlyifdoesntexist;
Source: "RevitPythonShell\init.py"; DestDir: "{userappdata}\RevitPythonShell_Vasari"; Flags: onlyifdoesntexist
Source: "RevitPythonShell\startup.py"; DestDir: "{userappdata}\RevitPythonShell_Vasari"; Flags: onlyifdoesntexist
[code]
{ HANDLE INSTALL PROCESS STEPS }
procedure CurStepChanged(CurStep: TSetupStep);
var
AddInFilePath: String;
AddInFileContents: String;
begin
if CurStep = ssPostInstall then
begin
{ GET LOCATION OF USER AppData (Roaming) }
AddInFilePath := ExpandConstant('{userappdata}\Autodesk\Vasari\Addins\2014\RevitPythonShell_Vasari.addin');
{ CREATE NEW ADDIN FILE }
AddInFileContents := '<?xml version="1.0" encoding="utf-16" standalone="no"?>' + #13#10;
AddInFileContents := AddInFileContents + '<RevitAddIns>' + #13#10;
AddInFileContents := AddInFileContents + ' <AddIn Type="Application">' + #13#10;
AddInFileContents := AddInFileContents + ' <Name>RevitPythonShell</Name>' + #13#10;
AddInFileContents := AddInFileContents + ' <Assembly>' + ExpandConstant('{app}') + '\RevitPythonShell.dll</Assembly>' + #13#10;
AddInFileContents := AddInFileContents + ' <AddInId>3a7a1d24-51ed-462b-949f-1ddcca12008d</AddInId>' + #13#10;
AddInFileContents := AddInFileContents + ' <FullClassName>RevitPythonShell.RevitPythonShellApplication</FullClassName>' + #13#10;
AddInFileContents := AddInFileContents + ' <VendorId>RIPS</VendorId>' + #13#10;
AddInFileContents := AddInFileContents + ' </AddIn>' + #13#10;
AddInFileContents := AddInFileContents + '</RevitAddIns>' + #13#10;
SaveStringToFile(AddInFilePath, AddInFileContents, False);
end;
end;
[Setup]
AppName=RevitPythonShell for Vasari Beta3
AppVerName=RevitPythonShell for Vasari Beta3
RestartIfNeededByRun=false
DefaultDirName={pf32}\RevitPythonShell_for_Vasari_Beta3
OutputBaseFilename=Setup_RevitPythonShell_Vasari_Beta3
ShowLanguageDialog=auto
FlatComponentsList=false
UninstallFilesDir={app}\Uninstall
UninstallDisplayName=RevitPythonShell for Vasari Beta3
AppVersion=2014.1
VersionInfoVersion=2014.1
VersionInfoDescription=RevitPythonShell for Vasari Beta3
VersionInfoTextVersion=RevitPythonShell for Vasari Beta3
| Inno Setup | 3 | PavelAltynnikov/revitpythonshell | Setup_RevitPythonShell_Vasari_Beta3.iss | [
"MIT"
]
|
(datatype lns-expr
N : number;
___________________
[num N] : num-expr;
S : string;
___________________
[str S] : str-expr;
E1 : num-expr; E2 : num-expr;
_____________________________
[plus E1 E2] : num-expr;
E1 : num-expr; E2 : num-expr;
_____________________________
[times E1 E2] : num-expr;
E1 : str-expr; E2 : str-expr;
_____________________________
[cat E1 E2] : str-expr;
E : str-expr;
___________________
[len E] : num-expr;
E1 : T1;
X : T1 >> E2 : T2;
___________________
[let E1 X E2] : T2;)
| Shen | 4 | ajnavarro/language-dataset | data/github.com/sheganinans/pfpl-shen/26bc29a573038e6e2171cd22b10438bc0d4b9766/pfpl-4.shen | [
"MIT"
]
|
CLASS WebBrowser INHERIT OleControl
EXPORT Okay AS LOGIC
METHOD Display(cText AS STRING, lHtml AS LOGIC) AS VOID PASCAL
LOCAL cFileName AS STRING
LOCAL ptrFile AS PTR
LOCAL nSize AS DWORD
// Turn an string into an HTM or TXT file for display in a browser control
// Returns the filename is successful
cFileName := GetTempFilePath() + "temp."+IF(lHtml, "htm", "txt")
nSize := SLen(cText)
ptrFile := FCreate(cFileName, FC_NORMAL) // overwrite any file which is there
IF ptrFile != NULL_PTR
IF FWrite(ptrFile, cText, nSize) != nSize
cFileName := "" // failed the write
ENDIF
FClose(ptrFile)
ELSE
cFileName := "" // failed to open the file
ENDIF
IF !Empty(cFileName)
Send(SELF, #Navigate, cFileName)
ENDIF
RETURN
METHOD GoEnd()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #Navigate, "#end" )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD GoTop()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #Navigate, "#top" )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD HTMLPageGoBack()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #GoBack )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD HTMLPageGoForward()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #GoForward )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
CONSTRUCTOR( oWindow, xID, oPoint, oDimension, lDataAware )
Default( @xID, -1 )
Default( @oPoint, Point{} )
Default( @oDimension, Dimension{} )
Default( @lDataAware, FALSE )
SUPER( oWindow, xID, oPoint, oDimension, lDataAware )
SELF:SetStyle(WS_BORDER, FALSE)
SELF:SetExStyle(WS_EX_CLIENTEDGE, FALSE)
SELF:Caption := "WebBrowser"
SELF:HyperLabel := HyperLabel{ #WebBrowser, NULL_STRING, NULL_STRING, NULL_STRING }
SELF:Okay := SELF:CreateEmbedding( "Shell.Explorer" )
RETURN SELF
METHOD PageSetup()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #ExecWB, OLECMDID_PAGESETUP, OLECMDEXECOPT_DODEFAULT, NIL, NIL )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD Print()
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #ExecWB, OLECMDID_PRINT, OLECMDEXECOPT_DODEFAULT, NIL, NIL )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD PrintPreview()
// Only used by IE 5.5 which is a great feature
LOCAL bError AS CODEBLOCK
bError:=ErrorBlock({ |x| WebBrowserTrapError(x) })
BEGIN SEQUENCE
Send( SELF, #ExecWB, OLECMDID_PRINTPREVIEW, OLECMDEXECOPT_DODEFAULT, NIL, NIL )
ErrorBlock(bError)
RECOVER
ErrorBlock( bError )
END SEQUENCE
RETURN SELF
METHOD Quit( )
// Exits application and closes the open document.
LOCAL oMethod AS cOleMethod
LOCAL uRetValue AS USUAL
oMethod := cOleMethod{}
oMethod:symName := String2Symbol("Quit")
oMethod:iMemberid := 300
oMethod:wInvokeKind := INVOKE_METHOD
uRetValue := SELF:oAuto:__Invoke(oMethod, DWORD(_BP+16),PCount())
RETURN (uRetValue)
END CLASS
STATIC FUNCTION WebBrowserTrapError(oError AS Error)
BREAK oError
RETURN NIL
| xBase | 4 | JohanNel/XSharpPublic | Samples/VOExporterExamples/Before/Email/CLASS WebBrowser.prg | [
"Apache-2.0"
]
|
=pod
=head1 NAME
ASN1_item_sign, ASN1_item_sign_ex, ASN1_item_sign_ctx,
ASN1_item_verify, ASN1_item_verify_ex, ASN1_item_verify_ctx -
ASN1 sign and verify
=head1 SYNOPSIS
#include <openssl/x509.h>
int ASN1_item_sign_ex(const ASN1_ITEM *it, X509_ALGOR *algor1,
X509_ALGOR *algor2, ASN1_BIT_STRING *signature,
const void *data, const ASN1_OCTET_STRING *id,
EVP_PKEY *pkey, const EVP_MD *md, OSSL_LIB_CTX *libctx,
const char *propq);
int ASN1_item_sign(const ASN1_ITEM *it, X509_ALGOR *algor1, X509_ALGOR *algor2,
ASN1_BIT_STRING *signature, const void *data,
EVP_PKEY *pkey, const EVP_MD *md);
int ASN1_item_sign_ctx(const ASN1_ITEM *it, X509_ALGOR *algor1,
X509_ALGOR *algor2, ASN1_BIT_STRING *signature,
const void *data, EVP_MD_CTX *ctx);
int ASN1_item_verify_ex(const ASN1_ITEM *it, const X509_ALGOR *alg,
const ASN1_BIT_STRING *signature, const void *data,
const ASN1_OCTET_STRING *id, EVP_PKEY *pkey,
OSSL_LIB_CTX *libctx, const char *propq);
int ASN1_item_verify(const ASN1_ITEM *it, const X509_ALGOR *alg,
const ASN1_BIT_STRING *signature, const void *data,
EVP_PKEY *pkey);
int ASN1_item_verify_ctx(const ASN1_ITEM *it, const X509_ALGOR *alg,
const ASN1_BIT_STRING *signature, const void *data,
EVP_MD_CTX *ctx);
=head1 DESCRIPTION
ASN1_item_sign_ex() is used to sign arbitrary ASN1 data using a data object
I<data>, the ASN.1 structure I<it>, private key I<pkey> and message digest I<md>.
The data that is signed is formed by taking the data object in I<data> and
converting it to der format using the ASN.1 structure I<it>.
The I<data> that will be signed, and a structure containing the signature may
both have a copy of the B<X509_ALGOR>. The ASN1_item_sign_ex() function will
write the correct B<X509_ALGOR> to the structs based on the algorithms and
parameters that have been set up. If one of I<algor1> or I<algor2> points to the
B<X509_ALGOR> of the I<data> to be signed, then that B<X509_ALGOR> will first be
written before the signature is generated.
Examples of valid values that can be used by the ASN.1 structure I<it> are
ASN1_ITEM_rptr(X509_CINF), ASN1_ITEM_rptr(X509_REQ_INFO) and
ASN1_ITEM_rptr(X509_CRL_INFO).
The B<OSSL_LIB_CTX> specified in I<libctx> and the property query string
specified in I<props> are used when searching for algorithms in providers.
The generated signature is set into I<signature>.
The optional parameter I<id> can be NULL, but can be set for special key types.
See EVP_PKEY_CTX_set1_id() for further info. The output parameters <algor1> and
I<algor2> are ignored if they are NULL.
ASN1_item_sign() is similar to ASN1_item_sign_ex() but uses default values of
NULL for the I<id>, I<libctx> and I<propq>.
ASN1_item_sign_ctx() is similiar to ASN1_item_sign() but uses the parameters
contained in digest context I<ctx>.
ASN1_item_verify_ex() is used to verify the signature I<signature> of internal
data I<data> using the public key I<pkey> and algorithm identifier I<alg>.
The data that is verified is formed by taking the data object in I<data> and
converting it to der format using the ASN.1 structure I<it>.
The B<OSSL_LIB_CTX> specified in I<libctx> and the property query string
specified in I<props> are used when searching for algorithms in providers.
The optional parameter I<id> can be NULL, but can be set for special key types.
See EVP_PKEY_CTX_set1_id() for further info.
ASN1_item_verify() is similar to ASN1_item_verify_ex() but uses default values of
NULL for the I<id>, I<libctx> and I<propq>.
ASN1_item_verify_ctx() is similiar to ASN1_item_verify() but uses the parameters
contained in digest context I<ctx>.
=head1 RETURN VALUES
All sign functions return the size of the signature in bytes for success and
zero for failure.
All verify functions return 1 if the signature is valid and 0 if the signature
check fails. If the signature could not be checked at all because it was
ill-formed or some other error occurred then -1 is returned.
=head1 EXAMPLES
In the following example a 'MyObject' object is signed using the key contained
in an EVP_MD_CTX. The signature is written to MyObject.signature. The object is
then output in DER format and then loaded back in and verified.
#include <openssl/x509.h>
#include <openssl/asn1t.h>
/* An object used to store the ASN1 data fields that will be signed */
typedef struct MySignInfoObject_st
{
ASN1_INTEGER *version;
X509_ALGOR sig_alg;
} MySignInfoObject;
DECLARE_ASN1_FUNCTIONS(MySignInfoObject)
/*
* A higher level object containing the ASN1 fields, signature alg and
* output signature.
*/
typedef struct MyObject_st
{
MySignInfoObject info;
X509_ALGOR sig_alg;
ASN1_BIT_STRING *signature;
} MyObject;
DECLARE_ASN1_FUNCTIONS(MyObject)
/* The ASN1 definition of MySignInfoObject */
ASN1_SEQUENCE_cb(MySignInfoObject, NULL) = {
ASN1_SIMPLE(MySignInfoObject, version, ASN1_INTEGER)
ASN1_EMBED(MySignInfoObject, sig_alg, X509_ALGOR),
} ASN1_SEQUENCE_END_cb(MySignInfoObject, MySignInfoObject)
/* new, free, d2i & i2d functions for MySignInfoObject */
IMPLEMENT_ASN1_FUNCTIONS(MySignInfoObject)
/* The ASN1 definition of MyObject */
ASN1_SEQUENCE_cb(MyObject, NULL) = {
ASN1_EMBED(MyObject, info, MySignInfoObject),
ASN1_EMBED(MyObject, sig_alg, X509_ALGOR),
ASN1_SIMPLE(MyObject, signature, ASN1_BIT_STRING)
} ASN1_SEQUENCE_END_cb(MyObject, MyObject)
/* new, free, d2i & i2d functions for MyObject */
IMPLEMENT_ASN1_FUNCTIONS(MyObject)
int test_asn1_item_sign_verify(const char *mdname, EVP_PKEY *pkey, long version)
{
int ret = 0;
unsigned char *obj_der = NULL;
const unsigned char *p = NULL;
MyObject *obj = NULL, *loaded_obj = NULL;
const ASN1_ITEM *it = ASN1_ITEM_rptr(MySignInfoObject);
EVP_MD_CTX *sctx = NULL, *vctx = NULL;
int len;
/* Create MyObject and set its version */
obj = MyObject_new();
if (obj == NULL)
goto err;
if (!ASN1_INTEGER_set(obj->info.version, version))
goto err;
/* Set the key and digest used for signing */
sctx = EVP_MD_CTX_new();
if (sctx == NULL
|| !EVP_DigestSignInit_ex(sctx, NULL, mdname, NULL, NULL, pkey))
goto err;
/*
* it contains the mapping between ASN.1 data and an object MySignInfoObject
* obj->info is the 'MySignInfoObject' object that will be
* converted into DER data and then signed.
* obj->signature will contain the output signature.
* obj->sig_alg is filled with the private key's signing algorithm id.
* obj->info.sig_alg is another copy of the signing algorithm id that sits
* within MyObject.
*/
len = ASN1_item_sign_ctx(it, &obj->sig_alg, &obj->info.sig_alg,
obj->signature, &obj->info, sctx);
if (len <= 0
|| X509_ALGOR_cmp(&obj->sig_alg, &obj->info.sig_alg) != 0)
goto err;
/* Output MyObject in der form */
len = i2d_MyObject(obj, &obj_der);
if (len <= 0)
goto err;
/* Set the key and digest used for verifying */
vctx = EVP_MD_CTX_new();
if (vctx == NULL
|| !EVP_DigestVerifyInit_ex(vctx, NULL, mdname, NULL, NULL, pkey))
goto err;
/* Load the der data back into an object */
p = obj_der;
loaded_obj = d2i_MyObject(NULL, &p, len);
if (loaded_obj == NULL)
goto err;
/* Verify the loaded object */
ret = ASN1_item_verify_ctx(it, &loaded_obj->sig_alg, loaded_obj->signature,
&loaded_obj->info, vctx);
err:
OPENSSL_free(obj_der);
MyObject_free(loaded_obj);
MyObject_free(obj);
EVP_MD_CTX_free(sctx);
EVP_MD_CTX_free(vctx);
return ret;
}
=head1 SEE ALSO
L<X509_sign(3)>,
L<X509_verify(3)>
=head1 HISTORY
ASN1_item_sign_ex() and ASN1_item_verify_ex() were added in OpenSSL 3.0.
=head1 COPYRIGHT
Copyright 2020-2021 The OpenSSL Project Authors. All Rights Reserved.
Licensed under the Apache License 2.0 (the "License"). You may not use
this file except in compliance with the License. You can obtain a copy
in the file LICENSE in the source distribution or at
L<https://www.openssl.org/source/license.html>.
=cut
| Pod | 5 | pmesnier/openssl | doc/man3/ASN1_item_sign.pod | [
"Apache-2.0"
]
|
=pod
=head1 NAME
PKCS5_PBE_keyivgen, PKCS5_PBE_keyivgen_ex, PKCS5_pbe2_set, PKCS5_pbe2_set_iv,
PKCS5_pbe2_set_iv_ex, PKCS5_pbe_set, PKCS5_pbe_set_ex, PKCS5_pbe2_set_scrypt,
PKCS5_pbe_set0_algor, PKCS5_pbe_set0_algor_ex,
PKCS5_v2_PBE_keyivgen, PKCS5_v2_PBE_keyivgen_ex,
PKCS5_v2_scrypt_keyivgen, PKCS5_v2_scrypt_keyivgen_ex,
PKCS5_pbkdf2_set, PKCS5_pbkdf2_set_ex, EVP_PBE_scrypt, EVP_PBE_scrypt_ex
- PKCS#5 Password based encryption routines
=head1 SYNOPSIS
#include <openssl/evp.h>
int PKCS5_PBE_keyivgen(EVP_CIPHER_CTX *ctx, const char *pass, int passlen,
ASN1_TYPE *param, const EVP_CIPHER *cipher,
const EVP_MD *md, int en_de);
int PKCS5_PBE_keyivgen_ex(EVP_CIPHER_CTX *cctx, const char *pass, int passlen,
ASN1_TYPE *param, const EVP_CIPHER *cipher,
const EVP_MD *md, int en_de, OSSL_LIB_CTX *libctx,
const char *propq);
int PKCS5_v2_PBE_keyivgen(EVP_CIPHER_CTX *ctx, const char *pass, int passlen,
ASN1_TYPE *param, const EVP_CIPHER *cipher,
const EVP_MD *md, int en_de);
int PKCS5_v2_PBE_keyivgen_ex(EVP_CIPHER_CTX *ctx, const char *pass, int passlen,
ASN1_TYPE *param, const EVP_CIPHER *cipher,
const EVP_MD *md, int en_de,
OSSL_LIB_CTX *libctx, const char *propq);
int EVP_PBE_scrypt(const char *pass, size_t passlen,
const unsigned char *salt, size_t saltlen,
uint64_t N, uint64_t r, uint64_t p, uint64_t maxmem,
unsigned char *key, size_t keylen);
int EVP_PBE_scrypt_ex(const char *pass, size_t passlen,
const unsigned char *salt, size_t saltlen,
uint64_t N, uint64_t r, uint64_t p, uint64_t maxmem,
unsigned char *key, size_t keylen,
OSSL_LIB_CTX *ctx, const char *propq);
int PKCS5_v2_scrypt_keyivgen(EVP_CIPHER_CTX *ctx, const char *pass,
int passlen, ASN1_TYPE *param,
const EVP_CIPHER *c, const EVP_MD *md, int en_de);
int PKCS5_v2_scrypt_keyivgen_ex(EVP_CIPHER_CTX *ctx, const char *pass,
int passlen, ASN1_TYPE *param,
const EVP_CIPHER *c, const EVP_MD *md, int en_de,
OSSL_LIB_CTX *libctx, const char *propq);
#include <openssl/x509.h>
int PKCS5_pbe_set0_algor(X509_ALGOR *algor, int alg, int iter,
const unsigned char *salt, int saltlen);
int PKCS5_pbe_set0_algor_ex(X509_ALGOR *algor, int alg, int iter,
const unsigned char *salt, int saltlen,
OSSL_LIB_CTX *libctx);
X509_ALGOR *PKCS5_pbe_set(int alg, int iter,
const unsigned char *salt, int saltlen);
X509_ALGOR *PKCS5_pbe_set_ex(int alg, int iter,
const unsigned char *salt, int saltlen,
OSSL_LIB_CTX *libctx);
X509_ALGOR *PKCS5_pbe2_set(const EVP_CIPHER *cipher, int iter,
unsigned char *salt, int saltlen);
X509_ALGOR *PKCS5_pbe2_set_iv(const EVP_CIPHER *cipher, int iter,
unsigned char *salt, int saltlen,
unsigned char *aiv, int prf_nid);
X509_ALGOR *PKCS5_pbe2_set_iv_ex(const EVP_CIPHER *cipher, int iter,
unsigned char *salt, int saltlen,
unsigned char *aiv, int prf_nid,
OSSL_LIB_CTX *libctx);
X509_ALGOR *PKCS5_pbe2_set_scrypt(const EVP_CIPHER *cipher,
const unsigned char *salt, int saltlen,
unsigned char *aiv, uint64_t N, uint64_t r,
uint64_t p);
X509_ALGOR *PKCS5_pbkdf2_set(int iter, unsigned char *salt, int saltlen,
int prf_nid, int keylen);
X509_ALGOR *PKCS5_pbkdf2_set_ex(int iter, unsigned char *salt, int saltlen,
int prf_nid, int keylen,
OSSL_LIB_CTX *libctx);
=head1 DESCRIPTION
=head2 Key Derivation
PKCS5_PBE_keyivgen() and PKCS5_PBE_keyivgen_ex() take a password I<pass> of
length I<passlen>, parameters I<param> and a message digest function I<md_type>
and performs a key derivation according to PKCS#5 PBES1. The resulting key is
then used to initialise the cipher context I<ctx> with a cipher I<cipher> for
encryption (I<en_de>=1) or decryption (I<en_de>=0).
I<pass> is an optional parameter and can be NULL. If I<passlen> is -1, then the
function will calculate the length of I<pass> using strlen().
PKCS5_v2_PBE_keyivgen() and PKCS5_v2_PBE_keyivgen_ex() are similar to the above
but instead use PKCS#5 PBES2 as the encryption algorithm using the supplied
parameters.
PKCS5_v2_scrypt_keyivgen() and PKCS5_v2_scrypt_keyivgen_ex() use SCRYPT as the
key derivation part of the encryption algorithm.
I<salt> is the salt used in the derivation of length I<saltlen>. If the
I<salt> is NULL, then I<saltlen> must be 0. The function will not
attempt to calculate the length of the I<salt> because it is not assumed to
be NULL terminated.
I<iter> is the iteration count and its value should be greater than or
equal to 1. RFC 2898 suggests an iteration count of at least 1000. Any
I<iter> less than 1 is treated as a single iteration.
I<digest> is the message digest function used in the derivation.
Functions ending in _ex() take optional parameters I<libctx> and I<propq> which
are used to select appropriate algorithm implementations.
=head2 Algorithm Identifier Creation
PKCS5_pbe_set(), PKCS5_pbe_set_ex(), PKCS5_pbe2_set(), PKCS5_pbe2_set_iv(),
PKCS5_pbe2_set_iv_ex() and PKCS5_pbe2_set_scrypt() generate an B<X509_ALGOR>
object which represents an AlgorithmIdentifier containing the algorithm OID and
associated parameters for the PBE algorithm.
PKCS5_pbkdf2_set() and PKCS5_pbkdf2_set_ex() generate an B<X509_ALGOR>
object which represents an AlgorithmIdentifier containing the algorithm OID and
associated parameters for the PBKDF2 algorithm.
PKCS5_pbe_set0_algor() and PKCS5_pbe_set0_algor_ex() set the PBE algorithm OID and
parameters into the supplied B<X509_ALGOR>.
=head1 NOTES
The *_keyivgen() functions are typically used in PKCS#12 to encrypt objects.
These functions make no assumption regarding the given password.
It will simply be treated as a byte sequence.
=head1 RETURN VALUES
PKCS5_PBE_keyivgen(), PKCS5_v2_PBE_keyivgen(),
PKCS5_v2_PBE_keyivgen_ex(), PKCS5_v2_scrypt_keyivgen(),
PKCS5_v2_scrypt_keyivgen_ex(), PKCS5_pbe_set0_algor() and
PKCS5_pbe_set0_algor_ex() return 1 for success and 0 if an error occurs.
PKCS5_pbe_set(), PKCS5_pbe_set_ex(), PKCS5_pbe2_set(), PKCS5_pbe2_set_iv(),
PKCS5_pbe2_set_iv_ex(), PKCS5_pbe2_set_scrypt(),
PKCS5_pbkdf2_set() and PKCS5_pbkdf2_set_ex() return an B<X509_ALGOR> object or
NULL if an error occurs.
=head1 CONFORMING TO
IETF RFC 8018 (L<https://tools.ietf.org/html/rfc8018>)
=head1 SEE ALSO
L<EVP_PBE_CipherInit_ex(3)>,
L<PKCS12_pbe_crypt_ex(3)>,
L<passphrase-encoding(7)>
=head1 HISTORY
PKCS5_v2_PBE_keyivgen_ex(), EVP_PBE_scrypt_ex(), PKCS5_v2_scrypt_keyivgen_ex(),
PKCS5_pbe_set0_algor_ex(), PKCS5_pbe_set_ex(), PKCS5_pbe2_set_iv_ex() and
PKCS5_pbkdf2_set_ex() were added in OpenSSL 3.0.
From OpenSSL 3.0 the PBKDF1 algorithm used in PKCS5_PBE_keyivgen() and
PKCS5_PBE_keyivgen_ex() has been moved to the legacy provider as an EVP_KDF.
=head1 COPYRIGHT
Copyright 2021 The OpenSSL Project Authors. All Rights Reserved.
Licensed under the Apache License 2.0 (the "License"). You may not use
this file except in compliance with the License. You can obtain a copy
in the file LICENSE in the source distribution or at
L<https://www.openssl.org/source/license.html>.
=cut
| Pod | 4 | pmesnier/openssl | doc/man3/PKCS5_PBE_keyivgen.pod | [
"Apache-2.0"
]
|
/*
* Copyright 2018 The OpenSSL Project Authors. All Rights Reserved.
*
* Licensed under the OpenSSL license (the "License"). You may not use
* this file except in compliance with the License. You can obtain a copy
* in the file LICENSE in the source distribution or at
* https://www.openssl.org/source/license.html
*/
/*
* Here is an STORE loader for ENGINE backed keys. It relies on deprecated
* functions, and therefore need to have deprecation warnings suppressed.
* This file is not compiled at all in a '--api=3 no-deprecated' configuration.
*/
#define OPENSSL_SUPPRESS_DEPRECATED
#include "apps.h"
#ifndef OPENSSL_NO_ENGINE
# include <stdarg.h>
# include <string.h>
# include <openssl/engine.h>
# include <openssl/store.h>
/*
* Support for legacy private engine keys via the 'org.openssl.engine:' scheme
*
* org.openssl.engine:{engineid}:{keyid}
*
* Note: we ONLY support ENGINE_load_private_key() and ENGINE_load_public_key()
* Note 2: This scheme has a precedent in code in PKIX-SSH. for exactly
* this sort of purpose.
*/
/* Local definition of OSSL_STORE_LOADER_CTX */
struct ossl_store_loader_ctx_st {
ENGINE *e; /* Structural reference */
char *keyid;
int expected;
int loaded; /* 0 = key not loaded yet, 1 = key loaded */
};
static OSSL_STORE_LOADER_CTX *OSSL_STORE_LOADER_CTX_new(ENGINE *e, char *keyid)
{
OSSL_STORE_LOADER_CTX *ctx = OPENSSL_zalloc(sizeof(*ctx));
if (ctx != NULL) {
ctx->e = e;
ctx->keyid = keyid;
}
return ctx;
}
static void OSSL_STORE_LOADER_CTX_free(OSSL_STORE_LOADER_CTX *ctx)
{
if (ctx != NULL) {
ENGINE_free(ctx->e);
OPENSSL_free(ctx->keyid);
OPENSSL_free(ctx);
}
}
static OSSL_STORE_LOADER_CTX *engine_open(const OSSL_STORE_LOADER *loader,
const char *uri,
const UI_METHOD *ui_method,
void *ui_data)
{
const char *p = uri, *q;
ENGINE *e = NULL;
char *keyid = NULL;
OSSL_STORE_LOADER_CTX *ctx = NULL;
if (!CHECK_AND_SKIP_CASE_PREFIX(p, ENGINE_SCHEME_COLON))
return NULL;
/* Look for engine ID */
q = strchr(p, ':');
if (q != NULL /* There is both an engine ID and a key ID */
&& p[0] != ':' /* The engine ID is at least one character */
&& q[1] != '\0') { /* The key ID is at least one character */
char engineid[256];
size_t engineid_l = q - p;
strncpy(engineid, p, engineid_l);
engineid[engineid_l] = '\0';
e = ENGINE_by_id(engineid);
keyid = OPENSSL_strdup(q + 1);
}
if (e != NULL && keyid != NULL)
ctx = OSSL_STORE_LOADER_CTX_new(e, keyid);
if (ctx == NULL) {
OPENSSL_free(keyid);
ENGINE_free(e);
}
return ctx;
}
static int engine_expect(OSSL_STORE_LOADER_CTX *ctx, int expected)
{
if (expected == 0
|| expected == OSSL_STORE_INFO_PUBKEY
|| expected == OSSL_STORE_INFO_PKEY) {
ctx->expected = expected;
return 1;
}
return 0;
}
static OSSL_STORE_INFO *engine_load(OSSL_STORE_LOADER_CTX *ctx,
const UI_METHOD *ui_method, void *ui_data)
{
EVP_PKEY *pkey = NULL, *pubkey = NULL;
OSSL_STORE_INFO *info = NULL;
if (ctx->loaded == 0) {
if (ENGINE_init(ctx->e)) {
if (ctx->expected == 0
|| ctx->expected == OSSL_STORE_INFO_PKEY)
pkey =
ENGINE_load_private_key(ctx->e, ctx->keyid,
(UI_METHOD *)ui_method, ui_data);
if ((pkey == NULL && ctx->expected == 0)
|| ctx->expected == OSSL_STORE_INFO_PUBKEY)
pubkey =
ENGINE_load_public_key(ctx->e, ctx->keyid,
(UI_METHOD *)ui_method, ui_data);
ENGINE_finish(ctx->e);
}
}
ctx->loaded = 1;
if (pubkey != NULL)
info = OSSL_STORE_INFO_new_PUBKEY(pubkey);
else if (pkey != NULL)
info = OSSL_STORE_INFO_new_PKEY(pkey);
if (info == NULL) {
EVP_PKEY_free(pkey);
EVP_PKEY_free(pubkey);
}
return info;
}
static int engine_eof(OSSL_STORE_LOADER_CTX *ctx)
{
return ctx->loaded != 0;
}
static int engine_error(OSSL_STORE_LOADER_CTX *ctx)
{
return 0;
}
static int engine_close(OSSL_STORE_LOADER_CTX *ctx)
{
OSSL_STORE_LOADER_CTX_free(ctx);
return 1;
}
int setup_engine_loader(void)
{
OSSL_STORE_LOADER *loader = NULL;
if ((loader = OSSL_STORE_LOADER_new(NULL, ENGINE_SCHEME)) == NULL
|| !OSSL_STORE_LOADER_set_open(loader, engine_open)
|| !OSSL_STORE_LOADER_set_expect(loader, engine_expect)
|| !OSSL_STORE_LOADER_set_load(loader, engine_load)
|| !OSSL_STORE_LOADER_set_eof(loader, engine_eof)
|| !OSSL_STORE_LOADER_set_error(loader, engine_error)
|| !OSSL_STORE_LOADER_set_close(loader, engine_close)
|| !OSSL_STORE_register_loader(loader)) {
OSSL_STORE_LOADER_free(loader);
loader = NULL;
}
return loader != NULL;
}
void destroy_engine_loader(void)
{
OSSL_STORE_LOADER *loader = OSSL_STORE_unregister_loader(ENGINE_SCHEME);
OSSL_STORE_LOADER_free(loader);
}
#else /* !OPENSSL_NO_ENGINE */
int setup_engine_loader(void)
{
return 0;
}
void destroy_engine_loader(void)
{
}
#endif
| C | 4 | lbbxsxlz/openssl | apps/lib/engine_loader.c | [
"Apache-2.0"
]
|
int[][] grid = new int[4][4];
boolean isGameOver() {
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
if (grid[i][j] == 0) {
return false;
}
if (i != 3 && grid[i][j] == grid[i + 1][j]) {
return false;
}
if (j != 3 && grid[i][j] == grid[i][j + 1]) {
return false;
}
}
}
return true;
}
boolean got2048(){
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
if (grid[i][j] == 2048) {
return true;
}
}
}
return false;
}
int[][] blankGrid() {
int[][] a = {
{0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0}
};
return a;
}
void setup() {
size(400, 400);
grid = blankGrid();
addNumber(2);
}
void addNumber(int num) {
int startingspots = 0;
while(startingspots < num){
int x = (int)random(4);
int y = (int)random(4);
if(grid[x][y] == 0)
{
float r = random(1);
grid[x][y] = r > 0.5 ? 4 : 2;
startingspots++;
}
}
}
boolean compare(int[][] a, int[][] b) {
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
if ( a[i][j] != b[i][j]) {
return true;
}
}
}
return false;
}
int[][] copyGrid(int[][] grid) {
int[][] extra = blankGrid();
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
extra[i][j] = grid[i][j];
}
}
return extra;
}
void reverse(int arr[], int start, int end)
{
int temp;
if (start >= end)
return;
temp = arr[start];
arr[start] = arr[end];
arr[end] = temp;
reverse(arr, start+1, end-1);
}
int[][] flipGrid(int[][] grid) {
for (int i = 0; i < 4; i++) {
reverse(grid[i],0,3);
}
return grid;
}
int[][] rotateGrid(int grid[][]) {
int[][] newGrid = blankGrid();
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
newGrid[i][j] = grid[j][i];
}
}
return newGrid;
}
// One "move"
void keyPressed() {
boolean flipped = false;
boolean rotated = false;
boolean played = true;
if (keyCode == DOWN) {
} else if (keyCode == UP) {
grid = flipGrid(grid);
flipped = true;
} else if (keyCode == RIGHT) {
grid = rotateGrid(grid);
rotated = true;
} else if (keyCode == LEFT) {
grid = rotateGrid(grid);
grid = flipGrid(grid);
rotated = true;
flipped = true;
} else {
played = false;
}
if (played) {
int[][] past = copyGrid(grid);
for (int i = 0; i < 4; i++) {
grid[i] = operate(grid[i]);
}
boolean changed = compare(past, grid);
if (flipped) {
grid = flipGrid(grid);
}
if (rotated) {
grid = rotateGrid(grid);
grid = rotateGrid(grid);
grid = rotateGrid(grid);
}
if (changed) {
addNumber(1);
}
boolean gameover = isGameOver();
boolean wingame = got2048();
if (gameover) {
print("GAME OVER");
}
if(wingame) {
print("You have reached 2048!!!");
}
}
}
int[] operate(int[] row) {
row = slide(row);
row = combine(row);
row = slide(row);
return row;
}
void draw() {
background(255);
drawGrid();
}
int[] slide(int[] row) {
int[] arr = new int[4];
int index=3;
for(int i = 3 ; i >= 0 ;i--)
{
if(row[i] != 0)
{
arr[index] = row[i];
index--;
}
}
return arr;
}
int[] combine(int[] row) {
for (int i = 3; i >= 1; i--) {
int a = row[i];
int b = row[i - 1];
if (a == b) {
row[i] = a + b;
//score += row[i];
row[i - 1] = 0;
}
}
return row;
}
void drawGrid() {
int w = 100;
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
noFill();
strokeWeight(2);
stroke(0);
rect(i * w, j * w, w, w);
int val = grid[i][j];
if (grid[i][j] != 0) {
textAlign(CENTER,CENTER);
String s = "" + val;
int len = s.length() - 1;
int[] sizes = {64, 64, 32, 16};
fill(0);
noStroke();
textSize(sizes[len]);
text(val, i * w + w / 2, j * w + w / 2);
}
}
}
}
| Processing | 4 | aerinkayne/website | CodingChallenges/CC_094_2048/Processing/CC_094_2048/CC_094_2048.pde | [
"MIT"
]
|
lexer grammar LexerA;
A : 'a';
B : 'b';
C : 'c';
| ANTLR | 3 | maximmenshikov/antlr4 | runtime/Swift/Tests/Antlr4Tests/LexerA.g4 | [
"BSD-3-Clause"
]
|
@media screen and {}
| CSS | 0 | mengxy/swc | crates/swc_css_parser/tests/recovery/at-rule/media/feature/input.css | [
"Apache-2.0"
]
|
" Vim syntax file
" Language: XSD (XML Schema)
" Maintainer: Johannes Zellner <[email protected]>
" Last Change: Tue, 27 Apr 2004 14:54:59 CEST
" Filenames: *.xsd
" $Id: xsd.vim,v 1.1 2004/06/13 18:20:48 vimboss Exp $
" REFERENCES:
" [1] http://www.w3.org/TR/xmlschema-0
"
" Quit when a syntax file was already loaded
if exists("b:current_syntax")
finish
endif
runtime syntax/xml.vim
syn cluster xmlTagHook add=xsdElement
syn case match
syn match xsdElement '\%(xsd:\)\@<=all'
syn match xsdElement '\%(xsd:\)\@<=annotation'
syn match xsdElement '\%(xsd:\)\@<=any'
syn match xsdElement '\%(xsd:\)\@<=anyAttribute'
syn match xsdElement '\%(xsd:\)\@<=appInfo'
syn match xsdElement '\%(xsd:\)\@<=attribute'
syn match xsdElement '\%(xsd:\)\@<=attributeGroup'
syn match xsdElement '\%(xsd:\)\@<=choice'
syn match xsdElement '\%(xsd:\)\@<=complexContent'
syn match xsdElement '\%(xsd:\)\@<=complexType'
syn match xsdElement '\%(xsd:\)\@<=documentation'
syn match xsdElement '\%(xsd:\)\@<=element'
syn match xsdElement '\%(xsd:\)\@<=enumeration'
syn match xsdElement '\%(xsd:\)\@<=extension'
syn match xsdElement '\%(xsd:\)\@<=field'
syn match xsdElement '\%(xsd:\)\@<=group'
syn match xsdElement '\%(xsd:\)\@<=import'
syn match xsdElement '\%(xsd:\)\@<=include'
syn match xsdElement '\%(xsd:\)\@<=key'
syn match xsdElement '\%(xsd:\)\@<=keyref'
syn match xsdElement '\%(xsd:\)\@<=length'
syn match xsdElement '\%(xsd:\)\@<=list'
syn match xsdElement '\%(xsd:\)\@<=maxInclusive'
syn match xsdElement '\%(xsd:\)\@<=maxLength'
syn match xsdElement '\%(xsd:\)\@<=minInclusive'
syn match xsdElement '\%(xsd:\)\@<=minLength'
syn match xsdElement '\%(xsd:\)\@<=pattern'
syn match xsdElement '\%(xsd:\)\@<=redefine'
syn match xsdElement '\%(xsd:\)\@<=restriction'
syn match xsdElement '\%(xsd:\)\@<=schema'
syn match xsdElement '\%(xsd:\)\@<=selector'
syn match xsdElement '\%(xsd:\)\@<=sequence'
syn match xsdElement '\%(xsd:\)\@<=simpleContent'
syn match xsdElement '\%(xsd:\)\@<=simpleType'
syn match xsdElement '\%(xsd:\)\@<=union'
syn match xsdElement '\%(xsd:\)\@<=unique'
hi def link xsdElement Statement
" vim: ts=8
| VimL | 4 | uga-rosa/neovim | runtime/syntax/xsd.vim | [
"Vim"
]
|
{
"options": {
"step": {
"on_supervisor": {
"title": "\u062d\u062f\u062f \u0637\u0631\u064a\u0642\u0629 \u0627\u0644\u0627\u062a\u0635\u0627\u0644"
}
}
}
} | JSON | 1 | MrDelik/core | homeassistant/components/zwave_js/translations/ar.json | [
"Apache-2.0"
]
|
'$Revision:$'
'
DirWalker project
Copyright 2013 Philippe Quesnel
Licensed under the Academic Free License version 3.0
'
'-- Module body'
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> () From: ( | {
'Category: system\x7fComment: for: [i:0] & [i<10] & [i: i succ] Do: [
i printLine
]\x7fModuleInfo: Module: forStatement InitialContents: FollowSlot\x7fVisibility: public'
for: forBlocksCollector Do: execBlock = ( |
blocks.
init.
step.
test.
|
blocks: forBlocksCollector asVector.
init: blocks at: 0.
test: blocks at: 1.
step: blocks at: 2.
init value.
test whileTrue: [
execBlock value.
step value.
]).
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot'
forStatement = bootstrap define: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () ToBe: bootstrap addSlotsTo: (
bootstrap remove: 'directory' From:
bootstrap remove: 'fileInTimeString' From:
bootstrap remove: 'myComment' From:
bootstrap remove: 'postFileIn' From:
bootstrap remove: 'revision' From:
bootstrap remove: 'subpartNames' From:
globals modules init copy ) From: bootstrap setObjectAnnotationOf: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( |
{} = 'ModuleInfo: Creator: globals modules forStatement.
CopyDowns:
globals modules init. copy
SlotsToOmit: directory fileInTimeString myComment postFileIn revision subpartNames.
\x7fIsComplete: '.
| ) .
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot\x7fVisibility: public'
directory <- 'system'.
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: InitializeToExpression: (_CurrentTimeString)\x7fVisibility: public'
fileInTimeString <- _CurrentTimeString.
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot'
myComment <- ''.
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot'
postFileIn = ( |
| resend.postFileIn).
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot\x7fVisibility: public'
revision <- '$Revision:$'.
} | )
bootstrap addSlotsTo: bootstrap stub -> 'globals' -> 'modules' -> 'forStatement' -> () From: ( | {
'ModuleInfo: Module: forStatement InitialContents: FollowSlot\x7fVisibility: private'
subpartNames <- ''.
} | )
'-- Side effects'
globals modules forStatement postFileIn
| Self | 2 | phques/dir-walker-langcomp | dirWalker1.self/system/forStatement.self | [
"AFL-3.0"
]
|
grant.type=password
client.id=baeldung-soap-services
client.secret=d2ba7af8-f7d2-4c97-b4a5-3c88b59920ae
url=http://localhost:8080/auth/realms/baeldung-soap-services/protocol/openid-connect/token
| INI | 1 | DBatOWL/tutorials | spring-boot-modules/spring-boot-keycloak/src/test/resources/application-test.properties | [
"MIT"
]
|
package org.xtendroid.xtendroidtest.activities
import android.app.ProgressDialog
import android.os.AsyncTask
import java.util.ArrayList
import org.xtendroid.app.AndroidActivity
import org.xtendroid.app.OnCreate
import org.xtendroid.xtendroidtest.R
import static extension org.xtendroid.utils.AsyncBuilder.*
@AndroidActivity(R.layout.activity_main) class BgTaskActivity {
var tasks = new ArrayList<AsyncTask>
@OnCreate
def init() {
// Create a determinate progress bar
val pd = new ProgressDialog(this)
pd.max = 50
pd.progress = 0
pd.indeterminate = false
pd.progressStyle = ProgressDialog.STYLE_HORIZONTAL
// Use AsynBuilder to run a background task
var task = async(pd) [a, params|
// Do some work in the background thread
for (i : 1..50) {
Thread.sleep(100)
// update the progress
a.progress(i)
}
// we have access to the parameters too
return "Back from bg task with " + params?.get(0)
].first [
// This runs before the background task
mainHello.text = "Running bg task..."
].then [String result|
// this runs with the result of the background thread
mainHello.text = result
].onProgress [Object[] values|
// this runs if progress is published in the background thread
pd.progress = values.get(0) as Integer
].onError [Exception error|
// this runs if an error occurred anywhere else
mainHello.text = '''Error! ยซerror.class.nameยป ยซerror.messageยป'''
].start("Param1") // don't forget to call start to kick-off the task
// keep a pointer to all tasks so we can cancel them later
tasks.add(task)
}
override protected onDestroy() {
// cancel any running tasks
tasks.forEach[ it.cancel(true) ]
super.onDestroy()
}
} | Xtend | 5 | kusl/Xtendroid | XtendroidTest/src/org/xtendroid/xtendroidtest/activities/BgTaskActivity.xtend | [
"MIT"
]
|
import locale from '../locale/el_GR';
export default locale;
| TypeScript | 1 | zchengsite/ant-design-vue | components/locale-provider/el_GR.ts | [
"MIT"
]
|
// POV 3.x input script : plot.pov
// try povray +H834 +W669 -Iplot.pov -Oplot.pov.tga +P +X +A +FT +C
#if (version < 3.5)
#error "POV3DisplayDevice has been compiled for POV-Ray 3.5 or above.\nPlease upgrade POV-Ray or recompile VMD."
#end
#declare VMD_clip_on=array[3] {0, 0, 0};
#declare VMD_clip=array[3];
#declare VMD_scaledclip=array[3];
#declare VMD_line_width=0.0020;
#macro VMDC ( C1 )
texture { pigment { rgbt C1 }}
#end
#macro VMD_point (P1, R1, C1)
#local T = texture { finish { ambient 1.0 diffuse 0.0 phong 0.0 specular 0.0 } pigment { C1 } }
#if(VMD_clip_on[2])
intersection {
sphere {P1, R1 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
VMD_clip[2]
}
#else
sphere {P1, R1 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#end
#macro VMD_line (P1, P2, C1)
#local T = texture { finish { ambient 1.0 diffuse 0.0 phong 0.0 specular 0.0 } pigment { C1 } }
#if(VMD_clip_on[2])
intersection {
cylinder {P1, P2, VMD_line_width texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
VMD_clip[2]
}
#else
cylinder {P1, P2, VMD_line_width texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#end
#macro VMD_sphere (P1, R1, C1)
#local T = texture { pigment { C1 } }
#if(VMD_clip_on[2])
intersection {
sphere {P1, R1 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
VMD_clip[2]
}
#else
sphere {P1, R1 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#end
#macro VMD_cylinder (P1, P2, R1, C1, O1)
#local T = texture { pigment { C1 } }
#if(VMD_clip_on[2])
intersection {
cylinder {P1, P2, R1 #if(O1) open #end texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
VMD_clip[2]
}
#else
cylinder {P1, P2, R1 #if(O1) open #end texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#end
#macro VMD_cone (P1, P2, R1, C1)
#local T = texture { pigment { C1 } }
#if(VMD_clip_on[2])
intersection {
cone {P1, R1, P2, VMD_line_width texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
VMD_clip[2]
}
#else
cone {P1, R1, P2, VMD_line_width texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#end
#macro VMD_triangle (P1, P2, P3, N1, N2, N3, C1)
#local T = texture { pigment { C1 } }
smooth_triangle {P1, N1, P2, N2, P3, N3 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
#macro VMD_tricolor (P1, P2, P3, N1, N2, N3, C1, C2, C3)
#local NX = P2-P1;
#local NY = P3-P1;
#local NZ = vcross(NX, NY);
#local T = texture { pigment {
average pigment_map {
[1 gradient x color_map {[0 rgb 0] [1 C2*3]}]
[1 gradient y color_map {[0 rgb 0] [1 C3*3]}]
[1 gradient z color_map {[0 rgb 0] [1 C1*3]}]
}
matrix <1.01,0,1,0,1.01,1,0,0,1,-.002,-.002,-1>
matrix <NX.x,NX.y,NX.z,NY.x,NY.y,NY.z,NZ.x,NZ.y,NZ.z,P1.x,P1.y,P1.z>
} }
smooth_triangle {P1, N1, P2, N2, P3, N3 texture {T} #if(VMD_clip_on[1]) clipped_by {VMD_clip[1]} #end no_shadow}
#end
camera {
orthographic
location <0.0000, 0.0000, -2.0000>
look_at <-0.0000, -0.0000, 2.0000>
up <0.0000, 3.0000, 0.0000>
right <2.4065, 0.0000, 0.0000>
}
light_source {
<-0.1000, 0.1000, -1.0000>
color rgb<1.000, 1.000, 1.000>
parallel
point_at <0.0, 0.0, 0.0>
}
light_source {
<1.0000, 2.0000, -0.5000>
color rgb<1.000, 1.000, 1.000>
parallel
point_at <0.0, 0.0, 0.0>
}
background {
color rgb<0.350, 0.350, 0.350>
}
#default { texture {
finish { ambient 0.000 diffuse 0.650 phong 0.1 phong_size 40.000 specular 0.500 }
} }
#declare VMD_line_width=0.0020;
VMD_sphere(<-1.1562,-1.1562,-1.1562>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<-1.1562,-1.1562,1.1534>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<-1.1562,1.1534,-1.1562>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<-1.1562,1.1534,1.1534>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<1.1534,-1.1562,-1.1562>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<1.1534,-1.1562,1.1534>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<1.1534,1.1534,-1.1562>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_sphere(<1.1534,1.1534,1.1534>,0.0240,rgbt<0.000,0.000,1.000,0.000>)
VMD_cylinder(<-1.15622640,-1.15622652,-1.15622652>,<-1.15622640,-1.15622652,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,-1.15622652,-1.15622652>,<-1.15622640,1.15336001,-1.15622652>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,-1.15622652,-1.15622652>,<1.15336013,-1.15622652,-1.15622652>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,-1.15622652,1.15336001>,<1.15336013,-1.15622652,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,1.15336001,-1.15622652>,<-1.15622640,1.15336001,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<1.15336013,-1.15622652,-1.15622652>,<1.15336013,1.15336001,-1.15622652>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,-1.15622652,1.15336001>,<-1.15622640,1.15336001,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<-1.15622640,1.15336001,-1.15622652>,<1.15336013,1.15336001,-1.15622652>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<1.15336013,-1.15622652,-1.15622652>,<1.15336013,-1.15622652,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<1.15336013,1.15336001,1.15336001>,<-1.15622640,1.15336001,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<1.15336013,1.15336001,1.15336001>,<1.15336013,-1.15622652,1.15336001>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
VMD_cylinder(<1.15336013,1.15336001,1.15336001>,<1.15336013,1.15336001,-1.15622652>0.0238,rgbt<0.000,0.000,1.000,0.000>,1)
// MoleculeID: 1 ReprID: 0 Beginning CPK
// MoleculeID: 1 ReprID: 0 Beginning VDW
VMD_sphere(<-0.6785,-0.6785,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5781,-0.5781,-0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8464,-0.6519,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8989,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0318,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0940,-0.6542,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,-0.7051,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,0.6785,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5781,0.5781,0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8464,0.6519,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8989,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0318,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0940,0.6542,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,0.7050,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,-0.6785,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5781,-0.5781,0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8464,-0.6519,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8989,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0318,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0940,-0.6542,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,-0.7051,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,0.6785,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5781,0.5781,-0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8464,0.6519,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8989,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0318,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0940,0.6542,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,0.7050,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,-0.4778,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.6519,-0.5044,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.5781,-0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.5781,-1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,-0.5020,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.4512,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,0.4778,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.6519,0.5043,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.5781,-0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.5781,-1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,0.5020,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.4512,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,0.4778,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.6519,0.5043,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.5781,0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.5781,1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,0.5020,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.4512,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,-0.4778,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.6519,-0.5044,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.5781,0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.5781,1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,-0.5020,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.4512,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,-0.6785,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,-0.8464,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.8989,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-1.0318,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,-1.0940,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-1.0527,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,-0.6785,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,-0.8464,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.8989,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-1.0318,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,-1.0940,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-1.0527,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,0.6785,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,0.8464,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.8989,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,1.0318,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,1.0940,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,1.0527,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,0.6785,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,0.8464,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.8989,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,1.0318,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,1.0940,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,1.0527,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,-0.4778,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5781,-0.5781,-0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8464,-0.5044,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8989,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0318,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0940,-0.5020,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,-0.4512,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,0.4778,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5781,0.5781,0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8464,0.5043,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.8989,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0318,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0940,0.5020,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,0.4512,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,0.4778,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5781,0.5781,-0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8464,0.5043,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8989,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0318,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0940,0.5020,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,0.4512,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,-0.4778,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5781,-0.5781,0.5781>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8464,-0.5044,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.8989,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0318,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0940,-0.5020,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,-0.4512,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,-0.6785,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.6519,-0.8464,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.8989,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-1.0318,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,-1.0940,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-1.0527,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,-0.6785,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.6519,-0.8464,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.8989,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-1.0318,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,-1.0940,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-1.0527,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6785,0.6785,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.6519,0.8464,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.8989,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,1.0318,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,1.0940,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,1.0527,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6785,0.6785,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.6519,0.8464,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.8989,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,1.0318,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,1.0940,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,1.0527,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,-0.6785,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,-0.6519,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.5781,-0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.5781,-1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,-0.6542,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.7051,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,0.6785,-0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,0.6519,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.5781,-0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.5781,-1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,0.6542,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.7050,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,-0.6785,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,-0.6519,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.5781,0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.5781,1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,-0.6542,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.7051,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,0.6785,0.6785>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,0.6519,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.5781,0.8989>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.5781,1.0318>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,0.6542,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.7050,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.8464,0.6519,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<1.0940,0.6542,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,0.7050,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.8464,-0.6519,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<1.0940,-0.6542,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,-0.7051,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.8464,0.6519,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-1.0940,0.6542,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,0.7050,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.8464,-0.6519,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-1.0940,-0.6542,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,-0.7051,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.5043,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,0.5020,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.4512,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.5044,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,-0.5020,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.4512,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.5044,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,-0.5020,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.4512,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.5043,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,0.5020,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.4512,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,0.8464,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,1.0940,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,1.0527,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,0.8464,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,1.0940,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,1.0527,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,-0.8464,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,-1.0940,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-1.0527,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,-0.8464,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,-1.0940,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-1.0527,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.8464,0.5043,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-1.0940,0.5020,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,0.4512,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.8464,-0.5044,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-1.0940,-0.5020,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-1.0527,-0.4512,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.8464,-0.5044,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<1.0940,-0.5020,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,-0.4512,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.8464,0.5043,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<1.0940,0.5020,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<1.0527,0.4512,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.8464,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,1.0940,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,1.0527,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.8464,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,1.0940,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,1.0527,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.8464,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,-1.0940,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-1.0527,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.8464,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,-1.0940,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-1.0527,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,0.6519,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,0.6542,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.7050,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,-0.6519,0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,-0.6542,1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.7051,1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,0.6519,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,0.6542,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.7050,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,-0.6519,-0.8464>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,-0.6542,-1.0940>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.7051,-1.0527>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,0.4778,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.3098,0.5043,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.2574,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1244,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.0622,0.5020,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,0.4512,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,-0.4778,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.3098,-0.5044,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.2574,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1244,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.0622,-0.5020,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,-0.4512,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,0.4778,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.3098,0.5043,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.2574,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1244,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.0622,0.5020,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,0.4512,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,-0.4778,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.3098,-0.5044,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.2574,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1244,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.0622,-0.5020,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,-0.4512,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.3098,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.2574,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.1244,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,0.0622,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.1036,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.3098,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.2574,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.1244,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,0.0622,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.1036,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.3098,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.2574,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.1244,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,-0.0622,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.1036,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.3098,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.2574,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.1244,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,-0.0622,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.1036,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,0.6519,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.2574,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1244,0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.0622,0.6542,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,0.7050,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,-0.6519,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.2574,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1244,-0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.0622,-0.6542,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,-0.7051,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,-0.6519,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.2574,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1244,-0.5781,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.0622,-0.6542,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,-0.7051,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,0.6519,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.2574,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1244,0.5781,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.0622,0.6542,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,0.7050,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,0.4778,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,0.3098,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.2574,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.1244,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,0.0622,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.1036,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,0.4778,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,0.3098,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.2574,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.1244,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,0.0622,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.1036,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.4778,-0.4778,0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<-0.5044,-0.3098,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.2574,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.1244,0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,-0.0622,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.1036,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.4778,-0.4778,-0.4778>,0.0336,rgbt<0.600,0.600,0.600,0.000>)
VMD_sphere(<0.5043,-0.3098,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.2574,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.1244,-0.5781>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,-0.0622,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.1036,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,-0.5044,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.0622,-0.5020,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,-0.4512,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,0.5043,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.0622,0.5020,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,0.4512,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,-0.5044,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.0622,-0.5020,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,-0.4512,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,0.5043,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.0622,0.5020,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,0.4512,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.3098,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,-0.0622,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.1036,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.3098,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,-0.0622,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.1036,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.3098,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,0.0622,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.1036,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.3098,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,0.0622,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.1036,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,-0.6519,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.0622,-0.6542,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,-0.7051,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.3098,0.6519,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.0622,0.6542,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.1036,0.7050,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,0.6519,0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.0622,0.6542,0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,0.7050,0.7050>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.3098,-0.6519,-0.6519>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.0622,-0.6542,-0.6542>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.1036,-0.7051,-0.7051>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,-0.3098,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,-0.0622,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.1036,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,-0.3098,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,-0.0622,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.1036,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,0.3098,-0.5044>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,0.0622,-0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.1036,-0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,0.3098,0.5043>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,0.0622,0.5020>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.1036,0.4512>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,-0.5044,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.5781,0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.5781,0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,-0.5020,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.4512,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,0.5043,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.5781,0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.5781,0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,0.5020,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.4512,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,0.5043,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.5781,-0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.5781,-0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5020,0.5020,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.4512,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,-0.5044,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.5781,-0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.5781,-0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5020,-0.5020,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.4512,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.6519,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,-0.5781,0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,-0.5781,0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,-0.6542,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.7051,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.6519,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,0.5781,0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,0.5781,0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,0.6542,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.7050,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.6519,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5781,-0.5781,-0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.5781,-0.5781,-0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.6542,-0.6542,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.7051,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.6519,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5781,0.5781,-0.2574>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.5781,0.5781,-0.1244>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.6542,0.6542,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.7050,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,0.5043,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,0.5020,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,0.4512,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,-0.5044,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,-0.5020,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,-0.4512,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.5044,-0.5044,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.5020,-0.5020,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.4512,-0.4512,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.5043,0.5043,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.5020,0.5020,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.4512,0.4512,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,0.6519,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,0.6542,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,0.7050,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,-0.6519,-0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,-0.6542,-0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,-0.7051,-0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<-0.6519,0.6519,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<-0.6542,0.6542,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<-0.7051,0.7050,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_sphere(<0.6519,-0.6519,0.3098>,0.0291,rgbt<1.000,0.000,0.000,0.000>)
VMD_sphere(<0.6542,-0.6542,0.0622>,0.0336,rgbt<0.250,0.750,0.750,0.000>)
VMD_sphere(<0.7050,-0.7051,0.1036>,0.0224,rgbt<1.000,1.000,1.000,0.000>)
VMD_cylinder(<-0.84640163,-0.65187728,-0.50435019>,<-0.87263066,-0.61499548,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,-0.57811368>,<-0.96532744,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,-0.57811368>,<-0.87263066,-0.61499548,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,-0.57811368>,<-0.87263066,-0.54123193,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,-0.57811368>,<-1.06290293,-0.61615926,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,-0.57811368>,<-1.06290293,-0.54006815,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,-0.57811368>,<-0.96532744,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.65420479,-0.50202268>,<-1.07333195,-0.67962813,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.65420479,-0.50202268>,<-1.06290293,-0.61615926,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,-0.70505142,-0.45117599>,<-1.07333195,-0.67962813,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,0.65187538,0.50434828>,<-0.87263066,0.61499357,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,0.57811189>,<-0.96532744,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,0.57811189>,<-0.87263066,0.54123008,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,0.57811189>,<-0.87263066,0.61499357,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,0.57811189>,<-1.06290293,0.54006648,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,0.57811189>,<-1.06290293,0.61615741,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,0.57811189>,<-0.96532744,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.65420294,0.50202084>,<-1.06290293,0.61615741,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.65420294,0.50202084>,<-1.07333195,0.67962623,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,0.70504963,0.45117402>,<-1.07333195,0.67962623,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,-0.65187728,0.50434828>,<0.87262917,-0.61499548,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,0.57811189>,<0.87262917,-0.61499548,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,0.57811189>,<0.87262917,-0.54123193,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,0.57811189>,<0.96532583,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,0.57811189>,<0.96532583,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,0.57811189>,<1.06290126,-0.61615926,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,0.57811189>,<1.06290126,-0.54006815,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.65420479,0.50202084>,<1.07333016,-0.67962813,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.65420479,0.50202084>,<1.06290126,-0.61615926,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,-0.70505142,0.45117402>,<1.07333016,-0.67962813,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,0.65187538,-0.50435019>,<0.87262917,0.61499357,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,-0.57811368>,<0.87262917,0.54123008,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,-0.57811368>,<0.87262917,0.61499357,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,-0.57811368>,<0.96532583,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,-0.57811368>,<0.96532583,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,-0.57811368>,<1.06290126,0.54006648,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,-0.57811368>,<1.06290126,0.61615741,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.65420294,-0.50202268>,<1.06290126,0.61615741,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.65420294,-0.50202268>,<1.07333016,0.67962623,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,0.70504963,-0.45117599>,<1.07333016,0.67962623,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.50435019,-0.84640175>,<-0.61499536,-0.54123193,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.89885980>,<-0.61499536,-0.54123193,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.89885980>,<-0.54123181,-0.61499548,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.89885980>,<-0.57811356,-0.57811368,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-1.03179526>,<-0.61615914,-0.54006815,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-1.03179526>,<-0.54006803,-0.61615926,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-1.03179526>,<-0.57811356,-0.57811368,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.50202268,-1.09401095>,<-0.67962801,-0.47659934,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.50202268,-1.09401095>,<-0.61615914,-0.54006815,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.45117599,-1.05265319>,<-0.67962801,-0.47659934,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.50434828,-0.84640175>,<0.61499369,0.54123008,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.89885980>,<0.54123020,0.61499357,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.89885980>,<0.61499369,0.54123008,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.89885980>,<0.57811201,0.57811189,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-1.03179526>,<0.54006660,0.61615741,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-1.03179526>,<0.61615753,0.54006648,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-1.03179526>,<0.57811201,0.57811189,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.50202084,-1.09401095>,<0.61615753,0.54006648,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.50202084,-1.09401095>,<0.67962635,0.47659743,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.45117402,-1.05265319>,<0.67962635,0.47659743,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.50434828,0.84639990>,<-0.61499536,0.54123008,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.89885795>,<-0.61499536,0.54123008,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.89885795>,<-0.54123181,0.61499357,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.89885795>,<-0.57811356,0.57811189,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,1.03179348>,<-0.61615914,0.54006648,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,1.03179348>,<-0.57811356,0.57811189,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,1.03179348>,<-0.54006803,0.61615741,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.50202084,1.09400904>,<-0.67962801,0.47659743,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.50202084,1.09400904>,<-0.61615914,0.54006648,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.45117402,1.05265129>,<-0.67962801,0.47659743,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.50435019,0.84639990>,<0.61499369,-0.54123193,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.89885795>,<0.54123020,-0.61499548,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.89885795>,<0.61499369,-0.54123193,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.89885795>,<0.57811201,-0.57811368,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,1.03179348>,<0.54006660,-0.61615926,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,1.03179348>,<0.57811201,-0.57811368,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,1.03179348>,<0.61615753,-0.54006815,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.50202268,1.09400904>,<0.61615753,-0.54006815,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.50202268,1.09400904>,<0.67962635,-0.47659934,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.45117599,1.05265129>,<0.67962635,-0.47659934,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.84640175,-0.65187728>,<-0.54123181,-0.87263077,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,-0.57811368>,<-0.61499536,-0.87263077,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,-0.57811368>,<-0.57811356,-0.96532756,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,-0.57811368>,<-0.54123181,-0.87263077,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,-0.57811368>,<-0.61615914,-1.06290317,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,-0.57811368>,<-0.54006803,-1.06290317,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,-0.57811368>,<-0.57811356,-0.96532756,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-1.09401095,-0.65420479>,<-0.47659922,-1.07333207,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-1.09401095,-0.65420479>,<-0.54006803,-1.06290317,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-1.05265319,-0.70505142>,<-0.47659922,-1.07333207,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.84640175,0.65187538>,<0.54123020,-0.87263077,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,0.57811189>,<0.54123020,-0.87263077,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,0.57811189>,<0.57811201,-0.96532756,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,0.57811189>,<0.61499369,-0.87263077,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,0.57811189>,<0.54006660,-1.06290317,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,0.57811189>,<0.61615753,-1.06290317,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,0.57811189>,<0.57811201,-0.96532756,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-1.09401095,0.65420294>,<0.47659755,-1.07333207,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-1.09401095,0.65420294>,<0.54006660,-1.06290317,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-1.05265319,0.70504963>,<0.47659755,-1.07333207,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.84639990,-0.65187728>,<0.54123020,0.87262905,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,-0.57811368>,<0.54123020,0.87262905,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,-0.57811368>,<0.61499369,0.87262905,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,-0.57811368>,<0.57811201,0.96532571,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,-0.57811368>,<0.54006660,1.06290114,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,-0.57811368>,<0.57811201,0.96532571,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,-0.57811368>,<0.61615753,1.06290114,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,1.09400904,-0.65420479>,<0.47659755,1.07333004,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,1.09400904,-0.65420479>,<0.54006660,1.06290114,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,1.05265129,-0.70505142>,<0.47659755,1.07333004,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.84639990,0.65187538>,<-0.54123181,0.87262905,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,0.57811189>,<-0.61499536,0.87262905,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,0.57811189>,<-0.54123181,0.87262905,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,0.57811189>,<-0.57811356,0.96532571,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,0.57811189>,<-0.61615914,1.06290114,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,0.57811189>,<-0.57811356,0.96532571,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,0.57811189>,<-0.54006803,1.06290114,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,1.09400904,0.65420294>,<-0.54006803,1.06290114,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,1.09400904,0.65420294>,<-0.47659922,1.07333004,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,1.05265129,0.70504963>,<-0.47659922,1.07333004,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,-0.50435019,-0.65187728>,<0.87262917,-0.54123193,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,-0.57811368>,<0.87262917,-0.61499548,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,-0.57811368>,<0.87262917,-0.54123193,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,-0.57811368,-0.57811368>,<0.96532583,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,-0.57811368>,<0.96532583,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,-0.57811368>,<1.06290126,-0.61615926,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,-0.57811368,-0.57811368>,<1.06290126,-0.54006815,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.50202268,-0.65420479>,<1.07333016,-0.47659934,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.50202268,-0.65420479>,<1.06290126,-0.54006815,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,-0.45117599,-0.70505142>,<1.07333016,-0.47659934,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,0.50434828,0.65187538>,<0.87262917,0.54123008,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,0.57811189>,<0.87262917,0.54123008,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,0.57811189>,<0.87262917,0.61499357,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.89885807,0.57811189,0.57811189>,<0.96532583,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,0.57811189>,<0.96532583,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,0.57811189>,<1.06290126,0.54006648,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.03179359,0.57811189,0.57811189>,<1.06290126,0.61615741,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.50202084,0.65420294>,<1.07333016,0.47659743,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.50202084,0.65420294>,<1.06290126,0.54006648,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,0.45117402,0.70504963>,<1.07333016,0.47659743,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,0.50434828,-0.65187728>,<-0.87263066,0.54123008,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,-0.57811368>,<-0.96532744,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,-0.57811368>,<-0.87263066,0.54123008,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,0.57811189,-0.57811368>,<-0.87263066,0.61499357,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,-0.57811368>,<-1.06290293,0.54006648,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,-0.57811368>,<-1.06290293,0.61615741,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,0.57811189,-0.57811368>,<-0.96532744,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.50202084,-0.65420479>,<-1.07333195,0.47659743,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.50202084,-0.65420479>,<-1.06290293,0.54006648,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,0.45117402,-0.70505142>,<-1.07333195,0.47659743,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,-0.50435019,0.65187538>,<-0.87263066,-0.54123193,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,0.57811189>,<-0.96532744,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,0.57811189>,<-0.87263066,-0.61499548,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.89885968,-0.57811368,0.57811189>,<-0.87263066,-0.54123193,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,0.57811189>,<-1.06290293,-0.61615926,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,0.57811189>,<-1.06290293,-0.54006815,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.03179514,-0.57811368,0.57811189>,<-0.96532744,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.50202268,0.65420294>,<-1.06290293,-0.54006815,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.50202268,0.65420294>,<-1.07333195,-0.47659934,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,-0.45117599,0.70504963>,<-1.07333195,-0.47659934,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.84640175,-0.50435019>,<0.61499369,-0.87263077,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,-0.57811368>,<0.54123020,-0.87263077,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,-0.57811368>,<0.57811201,-0.96532756,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.89885980,-0.57811368>,<0.61499369,-0.87263077,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,-0.57811368>,<0.54006660,-1.06290317,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,-0.57811368>,<0.61615753,-1.06290317,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-1.03179526,-0.57811368>,<0.57811201,-0.96532756,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-1.09401095,-0.50202268>,<0.61615753,-1.06290317,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-1.09401095,-0.50202268>,<0.67962635,-1.07333207,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-1.05265319,-0.45117599>,<0.67962635,-1.07333207,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.84640175,0.50434828>,<-0.61499536,-0.87263077,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,0.57811189>,<-0.61499536,-0.87263077,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,0.57811189>,<-0.57811356,-0.96532756,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.89885980,0.57811189>,<-0.54123181,-0.87263077,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,0.57811189>,<-0.61615914,-1.06290317,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,0.57811189>,<-0.54006803,-1.06290317,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-1.03179526,0.57811189>,<-0.57811356,-0.96532756,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-1.09401095,0.50202084>,<-0.67962801,-1.07333207,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-1.09401095,0.50202084>,<-0.61615914,-1.06290317,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-1.05265319,0.45117402>,<-0.67962801,-1.07333207,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.84639990,0.50434828>,<0.61499369,0.87262905,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,0.57811189>,<0.54123020,0.87262905,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,0.57811189>,<0.61499369,0.87262905,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.89885795,0.57811189>,<0.57811201,0.96532571,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,0.57811189>,<0.54006660,1.06290114,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,0.57811189>,<0.57811201,0.96532571,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,1.03179348,0.57811189>,<0.61615753,1.06290114,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,1.09400904,0.50202084>,<0.61615753,1.06290114,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,1.09400904,0.50202084>,<0.67962635,1.07333004,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,1.05265129,0.45117402>,<0.67962635,1.07333004,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.84639990,-0.50435019>,<-0.61499536,0.87262905,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,-0.57811368>,<-0.61499536,0.87262905,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,-0.57811368>,<-0.54123181,0.87262905,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.89885795,-0.57811368>,<-0.57811356,0.96532571,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,-0.57811368>,<-0.61615914,1.06290114,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,-0.57811368>,<-0.57811356,0.96532571,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,1.03179348,-0.57811368>,<-0.54006803,1.06290114,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,1.09400904,-0.50202268>,<-0.67962801,1.07333004,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,1.09400904,-0.50202268>,<-0.61615914,1.06290114,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,1.05265129,-0.45117599>,<-0.67962801,1.07333004,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.65187728,-0.84640175>,<0.54123020,-0.61499548,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.89885980>,<0.54123020,-0.61499548,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.89885980>,<0.57811201,-0.57811368,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.89885980>,<0.61499369,-0.54123193,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-1.03179526>,<0.54006660,-0.61615926,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-1.03179526>,<0.61615753,-0.54006815,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-1.03179526>,<0.57811201,-0.57811368,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.65420479,-1.09401095>,<0.47659755,-0.67962813,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.65420479,-1.09401095>,<0.54006660,-0.61615926,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.70505142,-1.05265319>,<0.47659755,-0.67962813,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.65187538,-0.84640175>,<-0.54123181,0.61499357,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.89885980>,<-0.61499536,0.54123008,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.89885980>,<-0.57811356,0.57811189,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.89885980>,<-0.54123181,0.61499357,-0.87263077>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-1.03179526>,<-0.61615914,0.54006648,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-1.03179526>,<-0.54006803,0.61615741,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-1.03179526>,<-0.57811356,0.57811189,-0.96532756>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.65420294,-1.09401095>,<-0.54006803,0.61615741,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.65420294,-1.09401095>,<-0.47659922,0.67962623,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.70504963,-1.05265319>,<-0.47659922,0.67962623,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.65187728,0.84639990>,<-0.54123181,-0.61499548,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.89885795>,<-0.61499536,-0.54123193,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.89885795>,<-0.54123181,-0.61499548,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.89885795>,<-0.57811356,-0.57811368,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,1.03179348>,<-0.61615914,-0.54006815,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,1.03179348>,<-0.54006803,-0.61615926,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,1.03179348>,<-0.57811356,-0.57811368,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.65420479,1.09400904>,<-0.47659922,-0.67962813,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.65420479,1.09400904>,<-0.54006803,-0.61615926,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.70505142,1.05265129>,<-0.47659922,-0.67962813,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.65187538,0.84639990>,<0.54123020,0.61499357,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.89885795>,<0.54123020,0.61499357,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.89885795>,<0.61499369,0.54123008,0.87262905>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.89885795>,<0.57811201,0.57811189,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,1.03179348>,<0.54006660,0.61615741,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,1.03179348>,<0.61615753,0.54006648,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,1.03179348>,<0.57811201,0.57811189,0.96532571>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.65420294,1.09400904>,<0.47659755,0.67962623,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.65420294,1.09400904>,<0.54006660,0.61615741,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.70504963,1.05265129>,<0.47659755,0.67962623,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,0.65187538,0.50434828>,<0.87262917,0.61499357,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<1.09400916,0.65420294,0.50202084>,<1.06290126,0.61615741,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.65420294,0.50202084>,<1.07333016,0.67962623,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,0.70504963,0.45117402>,<1.07333016,0.67962623,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,-0.65187728,-0.50435019>,<0.87262917,-0.61499548,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<1.09400916,-0.65420479,-0.50202268>,<1.07333016,-0.67962813,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.65420479,-0.50202268>,<1.06290126,-0.61615926,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,-0.70505142,-0.45117599>,<1.07333016,-0.67962813,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,0.65187538,-0.50435019>,<-0.87263066,0.61499357,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-1.09401083,0.65420294,-0.50202268>,<-1.06290293,0.61615741,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.65420294,-0.50202268>,<-1.07333195,0.67962623,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,0.70504963,-0.45117599>,<-1.07333195,0.67962623,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,-0.65187728,0.50434828>,<-0.87263066,-0.61499548,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-1.09401083,-0.65420479,0.50202084>,<-1.07333195,-0.67962813,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.65420479,0.50202084>,<-1.06290293,-0.61615926,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,-0.70505142,0.45117402>,<-1.07333195,-0.67962813,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.50434828,0.84639990>,<0.61499369,0.54123008,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,0.50202084,1.09400904>,<0.61615753,0.54006648,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.50202084,1.09400904>,<0.67962635,0.47659743,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.45117402,1.05265129>,<0.67962635,0.47659743,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.50435019,0.84639990>,<-0.61499536,-0.54123193,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,-0.50202268,1.09400904>,<-0.67962801,-0.47659934,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.50202268,1.09400904>,<-0.61615914,-0.54006815,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.45117599,1.05265129>,<-0.67962801,-0.47659934,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.50435019,-0.84640175>,<0.61499369,-0.54123193,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,-0.50202268,-1.09401095>,<0.61615753,-0.54006815,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.50202268,-1.09401095>,<0.67962635,-0.47659934,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.45117599,-1.05265319>,<0.67962635,-0.47659934,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.50434828,-0.84640175>,<-0.61499536,0.54123008,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,0.50202084,-1.09401095>,<-0.67962801,0.47659743,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.50202084,-1.09401095>,<-0.61615914,0.54006648,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.45117402,-1.05265319>,<-0.67962801,0.47659743,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.84639990,0.65187538>,<0.54123020,0.87262905,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,1.09400904,0.65420294>,<0.47659755,1.07333004,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,1.09400904,0.65420294>,<0.54006660,1.06290114,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,1.05265129,0.70504963>,<0.47659755,1.07333004,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.84639990,-0.65187728>,<-0.54123181,0.87262905,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,1.09400904,-0.65420479>,<-0.47659922,1.07333004,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,1.09400904,-0.65420479>,<-0.54006803,1.06290114,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,1.05265129,-0.70505142>,<-0.47659922,1.07333004,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.84640175,0.65187538>,<-0.54123181,-0.87263077,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,-1.09401095,0.65420294>,<-0.54006803,-1.06290317,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-1.09401095,0.65420294>,<-0.47659922,-1.07333207,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-1.05265319,0.70504963>,<-0.47659922,-1.07333207,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.84640175,-0.65187728>,<0.54123020,-0.87263077,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,-1.09401095,-0.65420479>,<0.47659755,-1.07333207,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-1.09401095,-0.65420479>,<0.54006660,-1.06290317,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-1.05265319,-0.70505142>,<0.47659755,-1.07333207,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,0.50434828,0.65187538>,<-0.87263066,0.54123008,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-1.09401083,0.50202084,0.65420294>,<-1.07333195,0.47659743,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,0.50202084,0.65420294>,<-1.06290293,0.54006648,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,0.45117402,0.70504963>,<-1.07333195,0.47659743,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.84640163,-0.50435019,-0.65187728>,<-0.87263066,-0.54123193,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-1.09401083,-0.50202268,-0.65420479>,<-1.07333195,-0.47659934,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.09401083,-0.50202268,-0.65420479>,<-1.06290293,-0.54006815,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-1.05265307,-0.45117599,-0.70505142>,<-1.07333195,-0.47659934,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,-0.50435019,0.65187538>,<0.87262917,-0.54123193,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<1.09400916,-0.50202268,0.65420294>,<1.06290126,-0.54006815,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,-0.50202268,0.65420294>,<1.07333016,-0.47659934,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,-0.45117599,0.70504963>,<1.07333016,-0.47659934,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.84640002,0.50434828,-0.65187728>,<0.87262917,0.54123008,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<1.09400916,0.50202084,-0.65420479>,<1.07333016,0.47659743,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.09400916,0.50202084,-0.65420479>,<1.06290126,0.54006648,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<1.05265141,0.45117402,-0.70505142>,<1.07333016,0.47659743,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.84639990,0.50434828>,<-0.61499536,0.87262905,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,1.09400904,0.50202084>,<-0.67962801,1.07333004,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,1.09400904,0.50202084>,<-0.61615914,1.06290114,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,1.05265129,0.45117402>,<-0.67962801,1.07333004,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.84639990,-0.50435019>,<0.61499369,0.87262905,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,1.09400904,-0.50202268>,<0.61615753,1.06290114,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,1.09400904,-0.50202268>,<0.67962635,1.07333004,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,1.05265129,-0.45117599>,<0.67962635,1.07333004,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.84640175,-0.50435019>,<-0.61499536,-0.87263077,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,-1.09401095,-0.50202268>,<-0.67962801,-1.07333207,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-1.09401095,-0.50202268>,<-0.61615914,-1.06290317,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-1.05265319,-0.45117599>,<-0.67962801,-1.07333207,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.84640175,0.50434828>,<0.61499369,-0.87263077,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,-1.09401095,0.50202084>,<0.61615753,-1.06290317,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-1.09401095,0.50202084>,<0.67962635,-1.07333207,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-1.05265319,0.45117402>,<0.67962635,-1.07333207,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.65187538,0.84639990>,<-0.54123181,0.61499357,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,0.65420294,1.09400904>,<-0.54006803,0.61615741,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.65420294,1.09400904>,<-0.47659922,0.67962623,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.70504963,1.05265129>,<-0.47659922,0.67962623,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.65187728,0.84639990>,<0.54123020,-0.61499548,0.87262905>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,-0.65420479,1.09400904>,<0.47659755,-0.67962813,1.07333004>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.65420479,1.09400904>,<0.54006660,-0.61615926,1.06290114>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.70505142,1.05265129>,<0.47659755,-0.67962813,1.07333004>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.65187538,-0.84640175>,<0.54123020,0.61499357,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,0.65420294,-1.09401095>,<0.47659755,0.67962623,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.65420294,-1.09401095>,<0.54006660,0.61615741,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.70504963,-1.05265319>,<0.47659755,0.67962623,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.65187728,-0.84640175>,<-0.54123181,-0.61499548,-0.87263077>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,-0.65420479,-1.09401095>,<-0.47659922,-0.67962813,-1.07333207>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.65420479,-1.09401095>,<-0.54006803,-0.61615926,-1.06290317>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.70505142,-1.05265319>,<-0.47659922,-0.67962813,-1.07333207>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,0.50434828,-0.50435019>,<0.28359497,0.54123008,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,-0.57811368>,<0.19089818,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,-0.57811368>,<0.28359497,0.54123008,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,-0.57811368>,<0.28359497,0.61499357,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,-0.57811368>,<0.09332263,0.54006648,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,-0.57811368>,<0.09332263,0.61615741,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,-0.57811368>,<0.19089818,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,-0.50202268>,<-0.00000072,0.50202084,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,-0.50202268>,<0.08289361,0.47659743,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,-0.50202268>,<0.09332263,0.54006648,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,0.45117402,-0.45117599>,<0.08289361,0.47659743,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,-0.50435019,0.50434828>,<0.28359497,-0.54123193,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,0.57811189>,<0.19089818,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,0.57811189>,<0.28359497,-0.61499548,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,0.57811189>,<0.28359497,-0.54123193,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,0.57811189>,<0.09332263,-0.61615926,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,0.57811189>,<0.09332263,-0.54006815,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,0.57811189>,<0.19089818,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,0.50202084>,<-0.00000072,-0.50202268,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,0.50202084>,<0.08289361,-0.47659934,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,0.50202084>,<0.09332263,-0.54006815,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,-0.45117599,0.45117402>,<0.08289361,-0.47659934,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,0.50434828,0.50434828>,<-0.28359652,0.54123008,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,0.57811189>,<-0.28359652,0.54123008,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,0.57811189>,<-0.28359652,0.61499357,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,0.57811189>,<-0.19089973,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,0.57811189>,<-0.19089973,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,0.57811189>,<-0.09332418,0.54006648,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,0.57811189>,<-0.09332418,0.61615741,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,0.50202084>,<-0.08289528,0.47659743,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,0.50202084>,<-0.00000072,0.50202084,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,0.50202084>,<-0.09332418,0.54006648,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,0.45117402,0.45117402>,<-0.08289528,0.47659743,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,-0.50435019,-0.50435019>,<-0.28359652,-0.54123193,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,-0.57811368>,<-0.28359652,-0.61499548,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,-0.57811368>,<-0.28359652,-0.54123193,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,-0.57811368>,<-0.19089973,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,-0.57811368>,<-0.19089973,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,-0.57811368>,<-0.09332418,-0.61615926,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,-0.57811368>,<-0.09332418,-0.54006815,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,-0.50202268>,<-0.09332418,-0.54006815,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,-0.50202268>,<-0.08289528,-0.47659934,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,-0.50202268>,<-0.00000072,-0.50202268,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,-0.45117599,-0.45117599>,<-0.08289528,-0.47659934,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.30982387,-0.65187728>,<0.61499369,0.28359485,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,-0.57811368>,<0.54123020,0.28359485,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,-0.57811368>,<0.57811201,0.19089806,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,-0.57811368>,<0.61499369,0.28359485,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,-0.57811368>,<0.54006660,0.09332252,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,-0.57811368>,<0.61615753,0.09332252,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,-0.57811368>,<0.57811201,0.19089806,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,-0.65420479>,<0.65420306,-0.00000083,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,-0.65420479>,<0.61615753,0.09332252,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,-0.65420479>,<0.67962635,0.08289349,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.10357237,-0.70505142>,<0.67962635,0.08289349,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.30982387,0.65187538>,<-0.61499536,0.28359485,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,0.57811189>,<-0.61499536,0.28359485,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,0.57811189>,<-0.57811356,0.19089806,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,0.57811189>,<-0.54123181,0.28359485,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,0.57811189>,<-0.61615914,0.09332252,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,0.57811189>,<-0.54006803,0.09332252,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,0.57811189>,<-0.57811356,0.19089806,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,0.65420294>,<-0.65420467,-0.00000083,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,0.65420294>,<-0.67962801,0.08289349,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,0.65420294>,<-0.61615914,0.09332252,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.10357237,0.70504963>,<-0.67962801,0.08289349,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.30982572,-0.65187728>,<-0.61499536,-0.28359663,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,-0.57811368>,<-0.61499536,-0.28359663,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,-0.57811368>,<-0.54123181,-0.28359663,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,-0.57811368>,<-0.57811356,-0.19089985,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,-0.57811368>,<-0.61615914,-0.09332430,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,-0.57811368>,<-0.57811356,-0.19089985,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,-0.57811368>,<-0.54006803,-0.09332430,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,-0.65420479>,<-0.67962801,-0.08289540,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,-0.65420479>,<-0.65420467,-0.00000083,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,-0.65420479>,<-0.61615914,-0.09332430,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.10357428,-0.70505142>,<-0.67962801,-0.08289540,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.30982572,0.65187538>,<0.61499369,-0.28359663,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,0.57811189>,<0.54123020,-0.28359663,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,0.57811189>,<0.61499369,-0.28359663,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,0.57811189>,<0.57811201,-0.19089985,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,0.57811189>,<0.54006660,-0.09332430,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,0.57811189>,<0.57811201,-0.19089985,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,0.57811189>,<0.61615753,-0.09332430,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,0.65420294>,<0.61615753,-0.09332430,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,0.65420294>,<0.65420306,-0.00000083,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,0.65420294>,<0.67962635,-0.08289540,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.10357428,0.70504963>,<0.67962635,-0.08289540,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,0.65187538,-0.65187728>,<-0.28359652,0.61499357,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,-0.57811368>,<-0.28359652,0.54123008,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,-0.57811368>,<-0.28359652,0.61499357,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,0.57811189,-0.57811368>,<-0.19089973,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,-0.57811368>,<-0.19089973,0.57811189,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,-0.57811368>,<-0.09332418,0.54006648,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,0.57811189,-0.57811368>,<-0.09332418,0.61615741,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,-0.65420479>,<-0.09332418,0.61615741,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,-0.65420479>,<-0.08289528,0.67962623,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,-0.65420479>,<-0.00000072,0.65420294,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,0.70504963,-0.70505142>,<-0.08289528,0.67962623,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,-0.65187728,0.65187538>,<-0.28359652,-0.61499548,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,0.57811189>,<-0.28359652,-0.61499548,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,0.57811189>,<-0.28359652,-0.54123193,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.25736749,-0.57811368,0.57811189>,<-0.19089973,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,0.57811189>,<-0.19089973,-0.57811368,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,0.57811189>,<-0.09332418,-0.61615926,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.12443197,-0.57811368,0.57811189>,<-0.09332418,-0.54006815,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,0.65420294>,<-0.08289528,-0.67962813,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,0.65420294>,<-0.09332418,-0.61615926,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,0.65420294>,<-0.00000072,-0.65420479,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,-0.70505142,0.70504963>,<-0.08289528,-0.67962813,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,-0.65187728,-0.65187728>,<0.28359497,-0.61499548,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,-0.57811368>,<0.19089818,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,-0.57811368>,<0.28359497,-0.61499548,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,-0.57811368,-0.57811368>,<0.28359497,-0.54123193,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,-0.57811368>,<0.09332263,-0.61615926,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,-0.57811368>,<0.09332263,-0.54006815,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,-0.57811368,-0.57811368>,<0.19089818,-0.57811368,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,-0.65420479>,<-0.00000072,-0.65420479,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,-0.65420479>,<0.08289361,-0.67962813,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,-0.65420479>,<0.09332263,-0.61615926,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,-0.70505142,-0.70505142>,<0.08289361,-0.67962813,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,0.65187538,0.65187538>,<0.28359497,0.61499357,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,0.57811189>,<0.19089818,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,0.57811189>,<0.28359497,0.54123008,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.25736594,0.57811189,0.57811189>,<0.28359497,0.61499357,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,0.57811189>,<0.09332263,0.54006648,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,0.57811189>,<0.09332263,0.61615741,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.12443042,0.57811189,0.57811189>,<0.19089818,0.57811189,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,0.65420294>,<-0.00000072,0.65420294,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,0.65420294>,<0.09332263,0.61615741,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,0.65420294>,<0.08289361,0.67962623,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,0.70504963,0.70504963>,<0.08289361,0.67962623,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.30982387,-0.50435019>,<-0.54123181,0.28359485,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,-0.57811368>,<-0.61499536,0.28359485,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,-0.57811368>,<-0.57811356,0.19089806,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.25736582,-0.57811368>,<-0.54123181,0.28359485,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,-0.57811368>,<-0.61615914,0.09332252,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,-0.57811368>,<-0.54006803,0.09332252,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.12443030,-0.57811368>,<-0.57811356,0.19089806,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,-0.50202268>,<-0.50202256,-0.00000083,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,-0.50202268>,<-0.54006803,0.09332252,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,-0.50202268>,<-0.47659922,0.08289349,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.10357237,-0.45117599>,<-0.47659922,0.08289349,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.30982387,0.50434828>,<0.54123020,0.28359485,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,0.57811189>,<0.54123020,0.28359485,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,0.57811189>,<0.57811201,0.19089806,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.25736582,0.57811189>,<0.61499369,0.28359485,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,0.57811189>,<0.54006660,0.09332252,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,0.57811189>,<0.61615753,0.09332252,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.12443030,0.57811189>,<0.57811201,0.19089806,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,0.50202084>,<0.50202096,-0.00000083,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,0.50202084>,<0.47659755,0.08289349,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,0.50202084>,<0.54006660,0.09332252,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.10357237,0.45117402>,<0.47659755,0.08289349,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.30982572,0.50434828>,<-0.54123181,-0.28359663,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,0.57811189>,<-0.61499536,-0.28359663,0.61499357>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,0.57811189>,<-0.54123181,-0.28359663,0.54123008>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.25736761,0.57811189>,<-0.57811356,-0.19089985,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,0.57811189>,<-0.61615914,-0.09332430,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,0.57811189>,<-0.57811356,-0.19089985,0.57811189>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.12443209,0.57811189>,<-0.54006803,-0.09332430,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,0.50202084>,<-0.47659922,-0.08289540,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,0.50202084>,<-0.54006803,-0.09332430,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,0.50202084>,<-0.50202256,-0.00000083,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.10357428,0.45117402>,<-0.47659922,-0.08289540,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.30982572,-0.50435019>,<0.54123020,-0.28359663,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,-0.57811368>,<0.54123020,-0.28359663,-0.54123193>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,-0.57811368>,<0.61499369,-0.28359663,-0.61499548>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.25736761,-0.57811368>,<0.57811201,-0.19089985,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,-0.57811368>,<0.54006660,-0.09332430,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,-0.57811368>,<0.57811201,-0.19089985,-0.57811368>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.12443209,-0.57811368>,<0.61615753,-0.09332430,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,-0.50202268>,<0.47659755,-0.08289540,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,-0.50202268>,<0.50202096,-0.00000083,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,-0.50202268>,<0.54006660,-0.09332430,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.10357428,-0.45117599>,<0.47659755,-0.08289540,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,-0.50435019,0.50434828>,<-0.28359652,-0.54123193,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,0.50202084>,<-0.08289528,-0.47659934,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,0.50202084>,<-0.09332418,-0.54006815,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.50202268,0.50202084>,<-0.00000072,-0.50202268,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,-0.45117599,0.45117402>,<-0.08289528,-0.47659934,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,0.50434828,-0.50435019>,<-0.28359652,0.54123008,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,-0.50202268>,<-0.08289528,0.47659743,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,-0.50202268>,<-0.09332418,0.54006648,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.50202084,-0.50202268>,<-0.00000072,0.50202084,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,0.45117402,-0.45117599>,<-0.08289528,0.47659743,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,-0.50435019,-0.50435019>,<0.28359497,-0.54123193,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,-0.50202268>,<-0.00000072,-0.50202268,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,-0.50202268>,<0.09332263,-0.54006815,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.50202268,-0.50202268>,<0.08289361,-0.47659934,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,-0.45117599,-0.45117599>,<0.08289361,-0.47659934,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,0.50434828,0.50434828>,<0.28359497,0.54123008,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,0.50202084>,<-0.00000072,0.50202084,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,0.50202084>,<0.08289361,0.47659743,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.50202084,0.50202084>,<0.09332263,0.54006648,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,0.45117402,0.45117402>,<0.08289361,0.47659743,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.30982572,0.65187538>,<-0.61499536,-0.28359663,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,0.65420294>,<-0.67962801,-0.08289540,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,0.65420294>,<-0.65420467,-0.00000083,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.06221652,0.65420294>,<-0.61615914,-0.09332430,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.10357428,0.70504963>,<-0.67962801,-0.08289540,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.30982572,-0.65187728>,<0.61499369,-0.28359663,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,-0.65420479>,<0.61615753,-0.09332430,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,-0.65420479>,<0.65420306,-0.00000083,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.06221652,-0.65420479>,<0.67962635,-0.08289540,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.10357428,-0.70505142>,<0.67962635,-0.08289540,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.30982387,0.65187538>,<0.61499369,0.28359485,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,0.65420294>,<0.65420306,-0.00000083,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,0.65420294>,<0.61615753,0.09332252,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.06221473,0.65420294>,<0.67962635,0.08289349,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.10357237,0.70504963>,<0.67962635,0.08289349,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.30982387,-0.65187728>,<-0.61499536,0.28359485,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,-0.65420479>,<-0.65420467,-0.00000083,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,-0.65420479>,<-0.67962801,0.08289349,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.06221473,-0.65420479>,<-0.61615914,0.09332252,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.10357237,-0.70505142>,<-0.67962801,0.08289349,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,-0.65187728,0.65187538>,<0.28359497,-0.61499548,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,0.65420294>,<-0.00000072,-0.65420479,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,0.65420294>,<0.08289361,-0.67962813,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,-0.65420479,0.65420294>,<0.09332263,-0.61615926,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,-0.70505142,0.70504963>,<0.08289361,-0.67962813,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.30982399,0.65187538,-0.65187728>,<0.28359497,0.61499357,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,-0.65420479>,<-0.00000072,0.65420294,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,-0.65420479>,<0.09332263,0.61615741,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.06221485,0.65420294,-0.65420479>,<0.08289361,0.67962623,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.10357249,0.70504963,-0.70505142>,<0.08289361,0.67962623,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,0.65187538,0.65187538>,<-0.28359652,0.61499357,0.61499357>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,0.65420294>,<-0.09332418,0.61615741,0.61615741>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,0.65420294>,<-0.00000072,0.65420294,0.65420294>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,0.65420294,0.65420294>,<-0.08289528,0.67962623,0.67962623>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,0.70504963,0.70504963>,<-0.08289528,0.67962623,0.67962623>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.30982560,-0.65187728,-0.65187728>,<-0.28359652,-0.61499548,-0.61499548>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,-0.65420479>,<-0.08289528,-0.67962813,-0.67962813>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,-0.65420479>,<-0.00000072,-0.65420479,-0.65420479>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.06221640,-0.65420479,-0.65420479>,<-0.09332418,-0.61615926,-0.61615926>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.10357416,-0.70505142,-0.70505142>,<-0.08289528,-0.67962813,-0.67962813>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.30982572,0.50434828>,<0.54123020,-0.28359663,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,0.50202084>,<0.47659755,-0.08289540,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,0.50202084>,<0.50202096,-0.00000083,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.06221652,0.50202084>,<0.54006660,-0.09332430,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.10357428,0.45117402>,<0.47659755,-0.08289540,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.30982572,-0.50435019>,<-0.54123181,-0.28359663,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,-0.50202268>,<-0.54006803,-0.09332430,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,-0.50202268>,<-0.47659922,-0.08289540,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.06221652,-0.50202268>,<-0.50202256,-0.00000083,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.10357428,-0.45117599>,<-0.47659922,-0.08289540,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.30982387,-0.50435019>,<0.54123020,0.28359485,-0.54123193>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,-0.50202268>,<0.50202096,-0.00000083,-0.50202268>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,-0.50202268>,<0.47659755,0.08289349,-0.47659934>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.06221473,-0.50202268>,<0.54006660,0.09332252,-0.54006815>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.10357237,-0.45117599>,<0.47659755,0.08289349,-0.47659934>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.30982387,0.50434828>,<-0.54123181,0.28359485,0.54123008>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,0.50202084>,<-0.50202256,-0.00000083,0.50202084>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,0.50202084>,<-0.47659922,0.08289349,0.47659743>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.06221473,0.50202084>,<-0.54006803,0.09332252,0.54006648>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.10357237,0.45117402>,<-0.47659922,0.08289349,0.47659743>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.50435019,0.30982387>,<0.54123020,-0.54123193,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.25736582>,<0.54123020,-0.54123193,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.25736582>,<0.61499369,-0.61499548,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.25736582>,<0.57811201,-0.57811368,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.12443030>,<0.54006660,-0.54006815,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.12443030>,<0.61615753,-0.61615926,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,0.12443030>,<0.57811201,-0.57811368,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,0.06221473>,<0.50202096,-0.50202268,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,0.06221473>,<0.47659755,-0.47659934,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,0.06221473>,<0.54006660,-0.54006815,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.45117599,0.10357237>,<0.47659755,-0.47659934,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.50434828,0.30982387>,<-0.54123181,0.54123008,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.25736582>,<-0.61499536,0.61499357,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.25736582>,<-0.54123181,0.54123008,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.25736582>,<-0.57811356,0.57811189,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.12443030>,<-0.61615914,0.61615741,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.12443030>,<-0.54006803,0.54006648,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,0.12443030>,<-0.57811356,0.57811189,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,0.06221473>,<-0.50202256,0.50202084,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,0.06221473>,<-0.47659922,0.47659743,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,0.06221473>,<-0.54006803,0.54006648,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.45117402,0.10357237>,<-0.47659922,0.47659743,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.50434828,-0.30982572>,<0.54123020,0.54123008,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.25736761>,<0.54123020,0.54123008,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.25736761>,<0.61499369,0.61499357,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.25736761>,<0.57811201,0.57811189,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.12443209>,<0.54006660,0.54006648,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.12443209>,<0.57811201,0.57811189,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,-0.12443209>,<0.61615753,0.61615741,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,-0.06221652>,<0.47659755,0.47659743,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,-0.06221652>,<0.50202096,0.50202084,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,-0.06221652>,<0.54006660,0.54006648,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.45117402,-0.10357428>,<0.47659755,0.47659743,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.50435019,-0.30982572>,<-0.54123181,-0.54123193,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.25736761>,<-0.61499536,-0.61499548,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.25736761>,<-0.54123181,-0.54123193,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.25736761>,<-0.57811356,-0.57811368,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.12443209>,<-0.61615914,-0.61615926,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.12443209>,<-0.57811356,-0.57811368,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,-0.12443209>,<-0.54006803,-0.54006815,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,-0.06221652>,<-0.54006803,-0.54006815,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,-0.06221652>,<-0.47659922,-0.47659934,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,-0.06221652>,<-0.50202256,-0.50202268,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.45117599,-0.10357428>,<-0.47659922,-0.47659934,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.65187728,0.30982387>,<-0.61499536,-0.61499548,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.25736582>,<-0.61499536,-0.61499548,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.25736582>,<-0.57811356,-0.57811368,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.25736582>,<-0.54123181,-0.54123193,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.12443030>,<-0.61615914,-0.61615926,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.12443030>,<-0.54006803,-0.54006815,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,-0.57811368,0.12443030>,<-0.57811356,-0.57811368,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,0.06221473>,<-0.65420467,-0.65420479,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,0.06221473>,<-0.67962801,-0.67962813,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,0.06221473>,<-0.61615914,-0.61615926,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.70505142,0.10357237>,<-0.67962801,-0.67962813,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.65187538,0.30982387>,<0.61499369,0.61499357,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.25736582>,<0.54123020,0.54123008,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.25736582>,<0.57811201,0.57811189,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.25736582>,<0.61499369,0.61499357,0.28359485>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.12443030>,<0.54006660,0.54006648,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.12443030>,<0.61615753,0.61615741,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,0.57811189,0.12443030>,<0.57811201,0.57811189,0.19089806>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,0.06221473>,<0.65420306,0.65420294,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,0.06221473>,<0.61615753,0.61615741,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,0.06221473>,<0.67962635,0.67962623,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.70504963,0.10357237>,<0.67962635,0.67962623,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.65187728,-0.30982572>,<0.61499369,-0.61499548,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.25736761>,<0.54123020,-0.54123193,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.25736761>,<0.61499369,-0.61499548,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.25736761>,<0.57811201,-0.57811368,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.12443209>,<0.54006660,-0.54006815,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.12443209>,<0.61615753,-0.61615926,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.57811201,-0.57811368,-0.12443209>,<0.57811201,-0.57811368,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,-0.06221652>,<0.65420306,-0.65420479,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,-0.06221652>,<0.61615753,-0.61615926,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,-0.06221652>,<0.67962635,-0.67962813,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.70505142,-0.10357428>,<0.67962635,-0.67962813,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.65187538,-0.30982572>,<-0.61499536,0.61499357,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.25736761>,<-0.61499536,0.61499357,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.25736761>,<-0.54123181,0.54123008,-0.28359663>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.25736761>,<-0.57811356,0.57811189,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.12443209>,<-0.61615914,0.61615741,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.12443209>,<-0.54006803,0.54006648,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.57811356,0.57811189,-0.12443209>,<-0.57811356,0.57811189,-0.19089985>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,-0.06221652>,<-0.65420467,0.65420294,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,-0.06221652>,<-0.67962801,0.67962623,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,-0.06221652>,<-0.61615914,0.61615741,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.70504963,-0.10357428>,<-0.67962801,0.67962623,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,0.50434828,-0.30982572>,<-0.54123181,0.54123008,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,-0.06221652>,<-0.47659922,0.47659743,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,-0.06221652>,<-0.50202256,0.50202084,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,0.50202084,-0.06221652>,<-0.54006803,0.54006648,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,0.45117402,-0.10357428>,<-0.47659922,0.47659743,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,-0.50435019,-0.30982572>,<0.54123020,-0.54123193,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,-0.06221652>,<0.47659755,-0.47659934,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,-0.06221652>,<0.50202096,-0.50202268,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,-0.50202268,-0.06221652>,<0.54006660,-0.54006815,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,-0.45117599,-0.10357428>,<0.47659755,-0.47659934,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.50435007,-0.50435019,0.30982387>,<-0.54123181,-0.54123193,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,0.06221473>,<-0.50202256,-0.50202268,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,0.06221473>,<-0.54006803,-0.54006815,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.50202256,-0.50202268,0.06221473>,<-0.47659922,-0.47659934,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.45117587,-0.45117599,0.10357237>,<-0.47659922,-0.47659934,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.50434840,0.50434828,0.30982387>,<0.54123020,0.54123008,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,0.06221473>,<0.50202096,0.50202084,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,0.06221473>,<0.47659755,0.47659743,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.50202096,0.50202084,0.06221473>,<0.54006660,0.54006648,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.45117414,0.45117402,0.10357237>,<0.47659755,0.47659743,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,0.65187538,-0.30982572>,<0.61499369,0.61499357,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,-0.06221652>,<0.61615753,0.61615741,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,-0.06221652>,<0.65420306,0.65420294,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,0.65420294,-0.06221652>,<0.67962635,0.67962623,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,0.70504963,-0.10357428>,<0.67962635,0.67962623,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,-0.65187728,-0.30982572>,<-0.61499536,-0.61499548,-0.28359663>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,-0.06221652>,<-0.67962801,-0.67962813,-0.08289540>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,-0.06221652>,<-0.65420467,-0.65420479,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,-0.65420479,-0.06221652>,<-0.61615914,-0.61615926,-0.09332430>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,-0.70505142,-0.10357428>,<-0.67962801,-0.67962813,-0.08289540>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<-0.65187716,0.65187538,0.30982387>,<-0.61499536,0.61499357,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,0.06221473>,<-0.65420467,0.65420294,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,0.06221473>,<-0.67962801,0.67962623,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.65420467,0.65420294,0.06221473>,<-0.61615914,0.61615741,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<-0.70505130,0.70504963,0.10357237>,<-0.67962801,0.67962623,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
VMD_cylinder(<0.65187550,-0.65187728,0.30982387>,<0.61499369,-0.61499548,0.28359485>0.0067,rgbt<1.000,0.000,0.000,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,0.06221473>,<0.65420306,-0.65420479,-0.00000083>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,0.06221473>,<0.61615753,-0.61615926,0.09332252>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.65420306,-0.65420479,0.06221473>,<0.67962635,-0.67962813,0.08289349>0.0067,rgbt<0.250,0.750,0.750,0.000>,1)
VMD_cylinder(<0.70504975,-0.70505142,0.10357237>,<0.67962635,-0.67962813,0.08289349>0.0067,rgbt<1.000,1.000,1.000,0.000>,1)
// End of POV-Ray 3.x generation
| POV-Ray SDL | 5 | benjaminbolbrinker/RASPA2 | Docs/InputFiles/Figures/IRMOF1-Asymetric/plot.pov | [
"MIT"
]
|
/* -*- Mode: IDL; tab-width: 2; indent-tabs-mode: nil; c-basic-offset: 2 -*- */
/* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/.
*
* The origin of this IDL file is
* http://dev.w3.org/fxtf/geometry/
*
* Copyright ยฉ 2012 W3Cยฎ (MIT, ERCIM, Keio), All Rights Reserved. W3C
* liability, trademark and document use rules apply.
*/
[Pref="layout.css.DOMMatrix.enabled",
Constructor(optional (DOMString or sequence<unrestricted double>) init)]
interface DOMMatrixReadOnly {
// These attributes are simple aliases for certain elements of the 4x4 matrix
readonly attribute unrestricted double a;
readonly attribute unrestricted double b;
readonly attribute unrestricted double c;
readonly attribute unrestricted double d;
readonly attribute unrestricted double e;
readonly attribute unrestricted double f;
readonly attribute unrestricted double m11;
readonly attribute unrestricted double m12;
readonly attribute unrestricted double m13;
readonly attribute unrestricted double m14;
readonly attribute unrestricted double m21;
readonly attribute unrestricted double m22;
readonly attribute unrestricted double m23;
readonly attribute unrestricted double m24;
readonly attribute unrestricted double m31;
readonly attribute unrestricted double m32;
readonly attribute unrestricted double m33;
readonly attribute unrestricted double m34;
readonly attribute unrestricted double m41;
readonly attribute unrestricted double m42;
readonly attribute unrestricted double m43;
readonly attribute unrestricted double m44;
// Immutable transform methods
DOMMatrix translate(unrestricted double tx,
unrestricted double ty,
optional unrestricted double tz = 0);
DOMMatrix scale(unrestricted double scale,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0);
DOMMatrix scale3d(unrestricted double scale,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0,
optional unrestricted double originZ = 0);
DOMMatrix scaleNonUniform(unrestricted double scaleX,
optional unrestricted double scaleY = 1,
optional unrestricted double scaleZ = 1,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0,
optional unrestricted double originZ = 0);
DOMMatrix rotate(unrestricted double angle,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0);
DOMMatrix rotateFromVector(unrestricted double x,
unrestricted double y);
DOMMatrix rotateAxisAngle(unrestricted double x,
unrestricted double y,
unrestricted double z,
unrestricted double angle);
DOMMatrix skewX(unrestricted double sx);
DOMMatrix skewY(unrestricted double sy);
DOMMatrix multiply(DOMMatrix other);
DOMMatrix flipX();
DOMMatrix flipY();
DOMMatrix inverse();
// Helper methods
readonly attribute boolean is2D;
readonly attribute boolean isIdentity;
DOMPoint transformPoint(optional DOMPointInit point);
[Throws] Float32Array toFloat32Array();
[Throws] Float64Array toFloat64Array();
stringifier;
[Default] object toJSON();
};
[Pref="layout.css.DOMMatrix.enabled",
Constructor,
Constructor(DOMString transformList),
Constructor(DOMMatrixReadOnly other),
Constructor(Float32Array array32),
Constructor(Float64Array array64),
Constructor(sequence<unrestricted double> numberSequence)]
interface DOMMatrix : DOMMatrixReadOnly {
// These attributes are simple aliases for certain elements of the 4x4 matrix
inherit attribute unrestricted double a;
inherit attribute unrestricted double b;
inherit attribute unrestricted double c;
inherit attribute unrestricted double d;
inherit attribute unrestricted double e;
inherit attribute unrestricted double f;
inherit attribute unrestricted double m11;
inherit attribute unrestricted double m12;
inherit attribute unrestricted double m13;
inherit attribute unrestricted double m14;
inherit attribute unrestricted double m21;
inherit attribute unrestricted double m22;
inherit attribute unrestricted double m23;
inherit attribute unrestricted double m24;
inherit attribute unrestricted double m31;
inherit attribute unrestricted double m32;
inherit attribute unrestricted double m33;
inherit attribute unrestricted double m34;
inherit attribute unrestricted double m41;
inherit attribute unrestricted double m42;
inherit attribute unrestricted double m43;
inherit attribute unrestricted double m44;
// Mutable transform methods
DOMMatrix multiplySelf(DOMMatrix other);
DOMMatrix preMultiplySelf(DOMMatrix other);
DOMMatrix translateSelf(unrestricted double tx,
unrestricted double ty,
optional unrestricted double tz = 0);
DOMMatrix scaleSelf(unrestricted double scale,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0);
DOMMatrix scale3dSelf(unrestricted double scale,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0,
optional unrestricted double originZ = 0);
DOMMatrix scaleNonUniformSelf(unrestricted double scaleX,
optional unrestricted double scaleY = 1,
optional unrestricted double scaleZ = 1,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0,
optional unrestricted double originZ = 0);
DOMMatrix rotateSelf(unrestricted double angle,
optional unrestricted double originX = 0,
optional unrestricted double originY = 0);
DOMMatrix rotateFromVectorSelf(unrestricted double x,
unrestricted double y);
DOMMatrix rotateAxisAngleSelf(unrestricted double x,
unrestricted double y,
unrestricted double z,
unrestricted double angle);
DOMMatrix skewXSelf(unrestricted double sx);
DOMMatrix skewYSelf(unrestricted double sy);
DOMMatrix invertSelf();
[Throws] DOMMatrix setMatrixValue(DOMString transformList);
};
| WebIDL | 4 | tlively/wasm-bindgen | crates/web-sys/webidls/enabled/DOMMatrix.webidl | [
"Apache-2.0",
"MIT"
]
|
namespace UnitTests.FSharpInterfaces
open System.Threading.Tasks
type public IFSharpBaseInterface =
abstract Echo: int -> Task<int>
abstract MultipleParameterEcho: string -> int -> Task<string*int>
| F# | 4 | JohnDebono/orleans | test/Misc/TestFSharpInterfaces/IFSharpBaseInterface.fs | [
"MIT"
]
|
#define rustg_read_toml_file(path) json_decode(call(RUST_G, "toml_file_to_json")(path) || "null")
| DM | 3 | MCHSL/rust-g | dmsrc/toml.dm | [
"MIT"
]
|
package com.baeldung.annotations;
import org.springframework.beans.factory.annotation.Value;
public class Engine {
@Value("8")
private int cylinderCount;
@Value("${engine.fuelType}")
private String fuelType;
public Engine() {
this(8);
}
public Engine(@Value("8") int cylinderCount) {
this.cylinderCount = cylinderCount;
}
@Value("8")
public void setCylinderCount(int cylinderCount) {
this.cylinderCount = cylinderCount;
}
}
| Java | 4 | zeesh49/tutorials | spring-mvc-java/src/main/java/com/baeldung/annotations/Engine.java | [
"MIT"
]
|
//
// Copyright (c) 2007, Brian Frank and Andy Frank
// Licensed under the Academic Free License version 3.0
//
// History:
// 3 Jan 07 Brian Frank Creation
//
**
** SlotTest
**
class SlotTest : Test
{
//////////////////////////////////////////////////////////////////////////
// Find
//////////////////////////////////////////////////////////////////////////
Void testFind()
{
verifySame(Slot.find("sys::Int.plus"), Int#plus)
verifySame(Slot.findMethod("sys::Int.plus"), Int#plus)
verifySame(Slot.findFunc("sys::Int.minus"), Int#minus.func)
verifySame(Pod.find("sys::Int.foo", false), null)
verifyEq(Slot.findField("sys::Int.isSpace", false), null)
verifyEq(Slot.findMethod("sys::Float.pi", false), null)
verifyErr(UnknownPodErr#) { Slot.find("badPodName::Foo.bar") }
verifyErr(UnknownTypeErr#) { Slot.find("sys::Foo.bar") }
verifyErr(UnknownSlotErr#) { Slot.find("sys::Int.foo") }
verifyErr(CastErr#) { Slot.findField("sys::Int.isSpace") }
verifyErr(CastErr#) { Slot.findMethod("sys::Float.pi") }
}
//////////////////////////////////////////////////////////////////////////
// Find
//////////////////////////////////////////////////////////////////////////
Void testFlags()
{
a := SlotsA.make
b := SlotsB.make
s := Type.of(a).slot("a")
verifyEq(s.qname, "testSys::SlotsA.a")
verifyEq(s.isField, true); verifyEq(s.isMethod, false)
verifyEq(s.isConst, false); verifyEq(s.isCtor, false)
verifyEq(s.isPublic, true); verifyEq(s.isProtected, false)
verifyEq(s.isPrivate, false); verifyEq(s.isInternal, false)
verifyEq(s.isNative, false); verifyEq(s.isOverride, false)
verifyEq(s.isStatic, false); verifyEq(s.isSynthetic, false)
verifyEq(s.isVirtual, true)
s = Type.of(b).slot("a")
verifyEq(s.qname, "testSys::SlotsB.a")
verifyEq(s.isField, true); verifyEq(s.isMethod, false)
verifyEq(s.isConst, false); verifyEq(s.isCtor, false)
verifyEq(s.isPublic, true); verifyEq(s.isProtected, false)
verifyEq(s.isPrivate, false); verifyEq(s.isInternal, false)
verifyEq(s.isNative, false); verifyEq(s.isOverride, true)
verifyEq(s.isStatic, false); verifyEq(s.isSynthetic, false)
verifyEq(s.isVirtual, false)
s = Type.of(a).slot("b")
verifyEq(s.qname, "testSys::SlotsA.b")
verifyEq(s.isField, false); verifyEq(s.isMethod, true)
verifyEq(s.isConst, false); verifyEq(s.isCtor, false)
verifyEq(s.isPublic, false); verifyEq(s.isProtected, true)
verifyEq(s.isPrivate, false); verifyEq(s.isInternal, false)
verifyEq(s.isNative, false); verifyEq(s.isOverride, false)
verifyEq(s.isStatic, false); verifyEq(s.isSynthetic, false)
verifyEq(s.isVirtual, true)
s = Type.of(b).slot("b")
verifyEq(s.qname, "testSys::SlotsB.b")
verifyEq(s.isField, false); verifyEq(s.isMethod, true)
verifyEq(s.isConst, false); verifyEq(s.isCtor, false)
verifyEq(s.isPublic, false); verifyEq(s.isProtected, true)
verifyEq(s.isPrivate, false); verifyEq(s.isInternal, false)
verifyEq(s.isNative, false); verifyEq(s.isOverride, true)
verifyEq(s.isStatic, false); verifyEq(s.isSynthetic, false)
verifyEq(s.isVirtual, false)
s = Type.of(a).slot("c")
verifyEq(s.qname, "testSys::SlotsA.c")
verifyEq(s.isField, true); verifyEq(s.isMethod, false)
verifyEq(s.isConst, true); verifyEq(s.isCtor, false)
verifyEq(s.isPublic, false); verifyEq(s.isProtected, false)
verifyEq(s.isPrivate, false); verifyEq(s.isInternal, true)
verifyEq(s.isNative, false); verifyEq(s.isOverride, false)
verifyEq(s.isStatic, true); verifyEq(s.isSynthetic, false)
verifyEq(s.isVirtual, false)
}
}
**************************************************************************
** SlotsA
**************************************************************************
class SlotsA
{
virtual Str a := "SlotsA"
protected virtual Str b() { return "SlotsA" }
internal static const Int c := 77
}
class SlotsB : SlotsA
{
override final Str a := "SlotsB"
protected override final Str b() { return "SlotsB" }
}
| Fantom | 4 | fanx-dev/fanx | library/testSys/fan/reflect/SlotTest.fan | [
"AFL-3.0"
]
|
#tag Class
Protected Class HTTPSocketAsync
Inherits URLConnection
#tag Event
Function AuthenticationRequested(realm As String, ByRef name As String, ByRef password As String) As Boolean
if RaiseEvent AuthenticationRequested( realm, name, password ) then
return true
end if
if Username <> "" then
name = Username.ToText
password = self.Password.ToText
return true
else
return false
end if
End Function
#tag EndEvent
#tag Event
Sub ContentReceived(URL As String, HTTPStatus As Integer, content As String)
url = Kaju.StripURLCredentials( url )
if not AllowRedirection and url <> RequestedURL then
content = ""
httpStatus = 302
elseif content.Encoding is nil and Encodings.UTF8.IsValidData( content ) then
content = content.DefineEncoding( Encodings.UTF8 )
end if
RaiseEvent ContentReceived( url, httpStatus, content )
End Sub
#tag EndEvent
#tag Method, Flags = &h0
Sub Get(url As String, allowRedirect As Boolean)
self.AllowRedirection = allowRedirect
Disconnect
SetSecure url
super.Send "GET", url
End Sub
#tag EndMethod
#tag Method, Flags = &h0
Sub Get(url As String, file As FolderItem, allowRedirect As Boolean)
self.AllowRedirection = allowRedirect
Disconnect
SetSecure url
super.Send "GET", url, file
End Sub
#tag EndMethod
#tag Method, Flags = &h0
Sub GetSync(url As String, file As FolderItem, timeout As Integer = 0)
self.AllowRedirection = true
Disconnect
SetSecure url
super.SendSync "GET", url, file, timeout
End Sub
#tag EndMethod
#tag Method, Flags = &h0
Function GetSync(url As String, timeout As Integer = 0) As String
self.AllowRedirection = true
Disconnect
SetSecure url
return super.SendSync( "GET", url, timeout )
End Function
#tag EndMethod
#tag Method, Flags = &h21
Private Sub Send(method As String, url As String, File As FolderItem)
super.Send Method, URL, File
End Sub
#tag EndMethod
#tag Method, Flags = &h21
Private Sub Send(method as Text, url as Text)
super.Send method, url
End Sub
#tag EndMethod
#tag Method, Flags = &h21
Private Sub SendSync(method As String, URL As String, file As FolderItem, timeout As Integer = 0)
super.SendSync method, URL, file, timeout
End Sub
#tag EndMethod
#tag Method, Flags = &h21
Private Function SendSync(method As String, URL As String, timeout As Integer = 0) As String
return super.SendSync( method, URL, timeout )
End Function
#tag EndMethod
#tag Method, Flags = &h21
Private Sub SetSecure(ByRef url As String)
AllowCertificateValidation = true
Username = ""
Password = ""
ClearRequestHeaders
RequestHeader( "Cache-Control" ) = "private, no-cache, max-age=0"
RequestHeader( "Pragma" ) = "no-cache"
url = url.ConvertEncoding( Encodings.UTF8 )
RequestedURL = Kaju.StripURLCredentials( url )
#if not TargetMacOS then
//
// See if the username and password has been specified
//
dim rx as new RegEx
rx.SearchPattern = "^(https?://)([^:/\x20@]+):([^:/\x20@]*)@(.*)"
dim match as RegExMatch = rx.Search( url )
if match isa RegExMatch then
Username = DecodeURLComponent( match.SubExpressionString( 2 ) ).DefineEncoding( Encodings.UTF8 )
Password = DecodeURLComponent( match.SubExpressionString( 3 ) ).DefineEncoding( Encodings.UTF8 )
url = match.SubExpressionString( 1 ) + match.SubExpressionString( 4 )
url = url.DefineEncoding( Encodings.UTF8 )
//
// Set the request header manually
//
dim encoded as string = EncodeBase64( Username + ":" + Password ).DefineEncoding( Encodings.UTF8 )
RequestHeader( "Authorization" ) = "Basic " + encoded.ToText
end if
#endif
End Sub
#tag EndMethod
#tag Hook, Flags = &h0
Event AuthenticationRequested(realm As String, ByRef name As String, ByRef password As String) As Boolean
#tag EndHook
#tag Hook, Flags = &h0
Event ContentReceived(url As String, httpStatus As Integer, content As String)
#tag EndHook
#tag Property, Flags = &h21
Private AllowRedirection As Boolean = False
#tag EndProperty
#tag Property, Flags = &h21
Private Password As String
#tag EndProperty
#tag Property, Flags = &h21
Private RequestedURL As String
#tag EndProperty
#tag Property, Flags = &h21
Private Username As String
#tag EndProperty
#tag ViewBehavior
#tag ViewProperty
Name="AllowCertificateValidation"
Visible=false
Group="Behavior"
InitialValue=""
Type="Boolean"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="HTTPStatusCode"
Visible=false
Group="Behavior"
InitialValue=""
Type="Integer"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="Index"
Visible=true
Group="ID"
InitialValue="-2147483648"
Type="Integer"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="Left"
Visible=true
Group="Position"
InitialValue="0"
Type="Integer"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="Name"
Visible=true
Group="ID"
InitialValue=""
Type="String"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="Super"
Visible=true
Group="ID"
InitialValue=""
Type="String"
EditorType=""
#tag EndViewProperty
#tag ViewProperty
Name="Top"
Visible=true
Group="Position"
InitialValue="0"
Type="Integer"
EditorType=""
#tag EndViewProperty
#tag EndViewBehavior
End Class
#tag EndClass
| Xojo | 3 | dakanji/Kaju | Kaju Classes/Kaju/HTTPSocketAsync.xojo_code | [
"MIT"
]
|
#
mes 2, EM_WSIZE, EM_PSIZE
exp $_m_a_i_n
pro $_m_a_i_n, 0
zero
rom 0
one
rom 1
mone
rom -1
big
rom 258
/* Or var with var */
loe zero
loe one
ior EM_WSIZE
loc 1
cmu EM_WSIZE
zeq *1
loc __LINE__
cal $fail
asp 4
1
/* Or big var with const */
loe big
loc 1
ior EM_WSIZE
loc 259
cmu EM_WSIZE
zeq *2
loc __LINE__
cal $fail
asp 4
2
/* Or const with var */
loc 0
loe one
ior EM_WSIZE
loc 1
cmu EM_WSIZE
zeq *3
loc __LINE__
cal $fail
asp 4
3
/* Or var with big const */
loe zero
loc 1000
ior EM_WSIZE
loc 1000
cmu EM_WSIZE
zeq *4
loc __LINE__
cal $fail
asp 4
4
/* Or big const with var */
loc 1000
loe one
ior EM_WSIZE
loc 1001
cmu EM_WSIZE
zeq *5
loc __LINE__
cal $fail
asp 4
5
/* Or big const with negative var */
loc 1000
loe mone
ior EM_WSIZE
loc -1
cmu EM_WSIZE
zeq *6
loc __LINE__
cal $fail
asp 4
6
/* Or big var with negative const */
loe big
loc -1
ior EM_WSIZE
loc -1
cmu EM_WSIZE
zeq *7
loc __LINE__
cal $fail
asp 4
7
/* Or var with big low-byte-zero const */
loe big
loc 256
ior EM_WSIZE
loc 258
cmu EM_WSIZE
zeq *8
loc __LINE__
cal $fail
asp 4
8
cal $finished
end
| Eiffel | 4 | wyan/ack | tests/plat/core/ior_e.e | [
"BSD-3-Clause"
]
|
struct NInts<const N: usize>([u8; N]);
impl NInts<const N: usize> {} //~ ERROR unexpected `const` parameter declaration
fn main() {
let _: () = 42; //~ ERROR mismatched types
}
fn banana(a: <T<const N: usize>>::BAR) {}
//~^ ERROR unexpected `const` parameter declaration
//~| ERROR cannot find type `T` in this scope
fn chaenomeles() {
path::path::Struct::<const N: usize>()
//~^ ERROR unexpected `const` parameter declaration
//~| ERROR failed to resolve: use of undeclared crate or module `path`
}
| Rust | 2 | ohno418/rust | src/test/ui/parser/const-param-decl-on-type-instead-of-impl.rs | [
"ECL-2.0",
"Apache-2.0",
"MIT-0",
"MIT"
]
|
module util/graph[node]
/*
* Utilities for some common operations and contraints
* on graphs.
*
* author: Greg Dennis
*/
open util/relation as rel
/** graph in undirected */
pred undirected [r: node->node] {
symmetric[r]
}
/** graph has no self-loops */
pred noSelfLoops[r: node->node] {
irreflexive[r]
}
/** graph is weakly connected */
pred weaklyConnected[r: node->node] {
all n1, n2: node | n1 in n2.*(r + ~r) // Changed from ^ to * to permit singleton
}
/** graph is strongly connected */
pred stronglyConnected[r: node->node] {
all n1, n2: node | n1 in n2.*r // Changed from ^ to * to permit singleton
}
/** graph is rooted at root */
pred rootedAt[r: node->node, root: node] {
node in root.*r
}
/** graph is a ring */
pred ring [r: node->node] {
all n: node | one n.r && rootedAt[r, n]
}
/** graph is a dag */
pred dag [r: node->node] {
acyclic[r, node]
}
/** graph is a forest */
pred forest [r: node->node] {
dag[r]
all n: node | lone r.n
}
/** graph is a tree */
pred tree [r: node->node] {
forest[r]
lone root: node | no r.root
}
/** graph is a tree rooted at root */
pred treeRootedAt[r: node->node, root: node] {
forest[r]
rootedAt[r, root]
}
/** returns the roots of the graph */
fun roots [r: node->node] : set node {
node - node.^r
}
/** returns the leaves of the grpah */
fun leaves [r: node->node] : set node {
node - node.^~r
}
/** returns the inner nodes (non-leaves) of the graph */
fun innerNodes [r: node->node] : set node {
node - leaves[r]
}
| Alloy | 5 | Kaixi26/org.alloytools.alloy | org.alloytools.alloy.core/src/main/resources/models/util/graph.als | [
"Apache-2.0"
]
|
doc('input.xml')//title/text() | XQuery | 4 | mrdziuban/basex | basex-core/src/test/resources/input.xq | [
"BSD-3-Clause"
]
|
PREFIX : <http://www.example.org>
SELECT ?P (COUNT(?O) AS ?C)
WHERE { ?S ?P ?O }
GROUP BY ?P
| SPARQL | 3 | yanaspaula/rdf4j | testsuites/sparql/src/main/resources/testcases-sparql-1.1-w3c/aggregates/agg02.rq | [
"BSD-3-Clause"
]
|
#!/usr/bin/env bash
set -e
echo "Installing remote dependencies"
(cd remote && rm -rf node_modules)
for i in {1..3}; do # try 3 times, for Terrapin
yarn --cwd remote --frozen-lockfile --check-files && break
if [ $i -eq 3 ]; then
echo "Yarn failed too many times" >&2
exit 1
fi
echo "Yarn failed $i, trying again..."
done
| Shell | 4 | DeprecatedLuxas/openvscode-server | build/azure-pipelines/linux/scripts/install-remote-dependencies.sh | [
"MIT"
]
|
../available_vhosts/wknd-muzik_publish.vhost | ApacheConf | 4 | vikas-nexteon/wknd-muzik | dispatcher/src/conf.d/enabled_vhosts/wknd-muzik_publish.vhost | [
"Apache-2.0"
]
|
package com.baeldung.junit5.order;
import static org.junit.Assert.assertEquals;
import org.junit.jupiter.api.AfterAll;
import org.junit.jupiter.api.MethodOrderer.OrderAnnotation;
import org.junit.jupiter.api.Order;
import org.junit.jupiter.api.Test;
import org.junit.jupiter.api.TestMethodOrder;
@TestMethodOrder(OrderAnnotation.class)
public class OrderAnnotationUnitTest {
private static StringBuilder output = new StringBuilder("");
@Test
@Order(1)
public void firstTest() {
output.append("a");
}
@Test
@Order(2)
public void secondTest() {
output.append("b");
}
@Test
@Order(3)
public void thirdTest() {
output.append("c");
}
@AfterAll
public static void assertOutput() {
assertEquals(output.toString(), "abc");
}
}
| Java | 4 | DBatOWL/tutorials | testing-modules/junit-5/src/test/java/com/baeldung/junit5/order/OrderAnnotationUnitTest.java | [
"MIT"
]
|
Parser: Parser.lex.o Parser.y.o yywrap.o
gcc -g -o Parser Parser.lex.o Parser.y.o yywrap.o
Parser.h: Parser.y
bison -d Parser.y
mv Parser.tab.h Parser.h
Parser.y.c: Parser.y
bison -d Parser.y
mv Parser.tab.c Parser.y.c
Parser.lex.o: Parser.lex.c Parser.h
gcc -g -c Parser.lex.c -o Parser.lex.o
Parser.y.o: Parser.y.c
gcc -g -c Parser.y.c -o Parser.y.o
yywrap.o: yywrap.c
gcc -g -o yywrap.o -c yywrap.c
Parser.lex.c: Parser.lex
flex Parser.lex
mv lex.yy.c Parser.lex.c
clean:
rm -f Parser.lex.o
rm -f Parser.y.o
rm -f yywrap.o
rm -f Parser.tab.h
rm -f Parser.tab.c
rm -f Parser.h
rm -f Parser.y.c
rm -f Parser.exe
rm -f Parser.lex.c
| Bison | 4 | robertsmeets/rjhg-pl | src/Makefile.bison | [
"MIT"
]
|
definition module StalinSort
from StdOverloaded import class <
stalinSort :: [a] -> [a] | < a
| Clean | 2 | abrudz/stalin-sort | clean/StalinSort.dcl | [
"MIT"
]
|
<!DOCTYPE html>
<html>
<head>
<title>Leaflet debug page</title>
<link rel="stylesheet" href="../../dist/leaflet.css" />
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<link rel="stylesheet" href="../css/screen.css" />
<script src="../../dist/leaflet-src.js"></script>
</head>
<body>
<div id="map"></div>
<script>
var map = L.map('map', {
crs: L.CRS.Simple
}).setView([0, 0], 0);
L.polygon([
[-200, -50],
[-40, 250],
[200, 100]
]).addTo(map);
L.marker([-200, -200]).addTo(map);
L.marker([200, -200]).addTo(map);
L.marker([200, 200]).addTo(map);
L.marker([-200, 200]).addTo(map);
L.marker([0, 0]).addTo(map);
L.imageOverlay('http://leafletjs.com/docs/images/logo.png', [[0, 0], [73, 220]]).addTo(map);
var grid = L.gridLayer({
attribution: 'Grid Layer'
});
grid.createTile = function (coords) {
var tile = document.createElement('div');
tile.innerHTML = [coords.x, coords.y, coords.z].join(', ');
tile.style.outline = '1px solid red';
tile.style.background = 'white';
return tile;
};
map.addLayer(grid);
L.circle([0, 0], 100, {color: 'red'}).addTo(map);
</script>
</body>
</html>
| HTML | 3 | pcmill/Leaflet | debug/map/simple-proj.html | [
"BSD-2-Clause"
]
|
(* 3 lines 1 code 1 comments 1 blanks *)
val main : unit -> transaction page (* uncounted comment *)
| UrWeb | 0 | alexmaco/tokei | tests/data/urweb_urs.urs | [
"Apache-2.0",
"MIT"
]
|
/**
* This file is part of the Phalcon Framework.
*
* (c) Phalcon Team <[email protected]>
*
* For the full copyright and license information, please view the LICENSE.txt
* file that was distributed with this source code.
*/
namespace Phalcon\Db;
/**
* Constants for Phalcon\Db
*/
class Enum
{
const FETCH_ASSOC = \Pdo::FETCH_ASSOC;
const FETCH_BOTH = \Pdo::FETCH_BOTH;
const FETCH_BOUND = \Pdo::FETCH_BOUND;
const FETCH_CLASS = \Pdo::FETCH_CLASS;
const FETCH_CLASSTYPE = \Pdo::FETCH_CLASSTYPE;
const FETCH_COLUMN = \Pdo::FETCH_COLUMN;
const FETCH_FUNC = \Pdo::FETCH_FUNC;
const FETCH_GROUP = \Pdo::FETCH_GROUP;
const FETCH_INTO = \Pdo::FETCH_INTO;
const FETCH_KEY_PAIR = \Pdo::FETCH_KEY_PAIR;
const FETCH_LAZY = \Pdo::FETCH_LAZY;
const FETCH_NAMED = \Pdo::FETCH_NAMED;
const FETCH_NUM = \Pdo::FETCH_NUM;
const FETCH_OBJ = \Pdo::FETCH_OBJ;
const FETCH_PROPS_LATE = \Pdo::FETCH_PROPS_LATE;
const FETCH_SERIALIZE = \Pdo::FETCH_SERIALIZE;
const FETCH_UNIQUE = \Pdo::FETCH_UNIQUE;
}
| Zephir | 3 | tidytrax/cphalcon | phalcon/Db/Enum.zep | [
"BSD-3-Clause"
]
|
#world {
text-name: 'foo';
text-face-name: Helvetica;
}
| CartoCSS | 1 | nimix/carto | test/rendering/noquote_font.mss | [
"Apache-2.0"
]
|
{# Copyright 2016 The Chromium Authors. All rights reserved. #}
{# Use of this source code is governed by a BSD-style license that can be #}
{# found in the LICENSE file. #}
// Generated by //build/android/generate_gradle.py
apply plugin: "java"
{% if template_type == 'java_binary' %}
apply plugin: "application"
{% endif %}
sourceSets {
main {
java.srcDirs = [
{% for path in main.java_dirs %}
"{{ path }}",
{% endfor %}
]
{% if main.java_excludes is defined %}
java.filter.exclude([
{% for path in main.java_excludes %}
"{{ path }}",
{% endfor %}
])
{% endif %}
}
}
sourceCompatibility = JavaVersion.VERSION_1_8
targetCompatibility = JavaVersion.VERSION_1_8
{% if template_type == 'java_binary' %}
applicationName = "{{ target_name }}"
{% if main_class %}
mainClassName = "{{ main_class }}"
{% endif %}
{% endif %}
{% if template_type in ('java_binary', 'java_library') %}
archivesBaseName = "{{ target_name }}"
{% endif %}
{% include 'dependencies.jinja' %}
| HTML+Django | 2 | zealoussnow/chromium | build/android/gradle/java.jinja | [
"BSD-3-Clause-No-Nuclear-License-2014",
"BSD-3-Clause"
]
|
import json
const
message = "hello world"
multiLine = """
foo
bar
"""
numbers = @[1, 2, 3]
type Options = enum
A,
B,
C
## Top-level comment
type
SomeStruct* = ref object
value*: string
proc someFunc*(): string =
## Function docs
##
## More docs
result = message
proc someOtherFunc(startingValue: int): (string, int) =
var num = startingValue
num += 1
if num > 10 * 10 * 10:
echo "Encountered an error"
raise newException(ValueError, "Value was over 1000")
("Fizz", num)
proc `+=`(a: var SomeStruct, b: SomeStruct): string =
a.value.add(b.value)
return a.value
echo someFunc()
echo(someOtherFunc(123))
discard someFunc()
| Nimrod | 5 | JesseVermeulen123/bat | tests/syntax-tests/source/nim/main.nim | [
"Apache-2.0",
"MIT"
]
|
pub const a_bool = false;
| Zig | 0 | aruniiird/zig | test/stage1/behavior/namespace_depends_on_compile_var/b.zig | [
"MIT"
]
|
include "../../../../resources/config/varnish-3/fos_debug.vcl";
include "../../../../resources/config/varnish-3/fos_refresh.vcl";
include "../../../../resources/config/varnish-3/fos_purge.vcl";
include "../../../../resources/config/varnish-3/fos_ban.vcl";
include "../../../../resources/config/varnish-3/fos_custom_ttl.vcl";
backend default {
.host = "127.0.0.1";
.port = "8080";
}
acl invalidators {
"127.0.0.1";
}
sub vcl_recv {
call fos_ban_recv;
call fos_purge_recv;
call fos_refresh_recv;
}
sub vcl_fetch {
call fos_ban_fetch;
call fos_custom_ttl_fetch;
}
sub vcl_hit {
call fos_purge_hit;
}
sub vcl_miss {
call fos_purge_miss;
}
sub vcl_deliver {
call fos_debug_deliver;
call fos_ban_deliver;
}
| VCL | 4 | PeerJ/FOSHttpCache | tests/Functional/Fixtures/varnish-3/fos.vcl | [
"MIT"
]
|
export default fn => {
self.onmessage = async ({ data: msg }) => {
try {
switch (msg) {
case "next":
if (!(await import.meta.webpackHot.check(true)))
throw new Error("No update found");
await fn();
self.postMessage("next");
break;
default:
throw new Error("Unexpected message");
}
} catch (e) {
self.postMessage("error: " + e.stack);
}
};
};
| JavaScript | 4 | fourstash/webpack | test/hotCases/worker/move-between-runtime/worker.js | [
"MIT"
]
|
#include "unittest/gtest.hpp"
#include "arch/barrier.hpp"
#include "containers/scoped.hpp"
namespace unittest {
struct barrier_and_values_t {
thread_barrier_t barrier;
// Get them in opposite cache lines for good measure.
static const int values_size = 512;
char values[values_size];
static const int low_index = 0;
static const int high_index = 256;
barrier_and_values_t() : barrier(2) {
memset(values, 0, values_size);
}
};
struct barrier_arg_t {
barrier_and_values_t *bav;
int number;
int indexA;
int indexB;
bool error;
};
void *run_barrier_thread(void *v_arg) {
barrier_arg_t *arg = static_cast<barrier_arg_t *>(v_arg);
barrier_and_values_t *bav = arg->bav;
int number = arg->number;
int indexA = arg->indexA;
int indexB = arg->indexB;
for (int i = 0; i < 1000; ++i) {
bav->values[indexA] = number;
bav->barrier.wait();
arg->error |= (bav->values[indexB] == number);
bav->values[indexB] = number;
bav->barrier.wait();
arg->error |= (bav->values[indexA] == number);
}
return nullptr;
}
TEST(BarrierTest, OneThousandTest) {
scoped_ptr_t<barrier_and_values_t> p(new barrier_and_values_t);
barrier_arg_t bav1, bav2;
bav1.bav = bav2.bav = p.get();
bav1.number = 0;
bav2.number = 1;
bav1.indexA = bav2.indexB = barrier_and_values_t::low_index;
bav2.indexA = bav1.indexB = barrier_and_values_t::high_index;
bav1.error = bav2.error = false;
pthread_t th1, th2;
int res = pthread_create(&th1, nullptr, run_barrier_thread, &bav1);
guarantee_xerr(res == 0, res, "pthread_create (for th1) failed");
res = pthread_create(&th2, nullptr, run_barrier_thread, &bav2);
guarantee_xerr(res == 0, res, "pthread_create (for th2) failed");
void *dummy;
res = pthread_join(th1, &dummy);
guarantee_xerr(res == 0, res, "pthread_join (for th1) failed");
res = pthread_join(th2, &dummy);
guarantee_xerr(res == 0, res, "pthread_join (for th2) failed");
ASSERT_FALSE(bav1.error);
ASSERT_FALSE(bav2.error);
}
} // namespace unittest
| C++ | 4 | zadcha/rethinkdb | src/unittest/barrier_test.cc | [
"Apache-2.0"
]
|
#lang scribble/base
@(require
scribble/manual
"defs.rkt")
Theoreticians often use sophisticated notation to communicate and reason about
key ideas in their theories and models.
Notation is often domain-specific or even invented on-the-fly when creating a
new theory or model.
Proof assistants aid theoreticians by rigorously checking formal models, but
have poor support for allowing users to @emph{conveniently} define and use
@emph{sophisticated} notation.
For example, in a proof assistant like Coq or Agda, users can easily define
simple notation like @code{ฮ โข e : t}, but to use BNF notation the user must use
a preprocessing tool external to the proof assistant, which is cumbersome.
To support convenient and sophisticated extension, we can use @emph{language
extension} as a fundamental part of the design of a proof assistant.
By starting from language extension we can not only facilitate convenient and
sophisticated user-defined extensions, but also get a single, compositional
system for writing all extensions to the core proof language.
We describe how to design a language-extension system that supports safe,
convenient, and sophisticated user-defined extensions, and how to design a
proof assistant based on language extension.
We evaluate this design by building a proof assistant that features a small
dependent type theory as the core language and implementing the following
extensions in small user-defined libraries: pattern matching for inductive
types, dependently typed staged meta-programming, a tactic language, and BNF
and inference-rule notation for inductive type definitions. | Racket | 3 | bluephoenix47/cic-redex | cur-paper/abstract.scrbl | [
"BSD-2-Clause"
]
|
/* Copyright 2016 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
#include "tensorflow/core/util/mirror_pad_mode.h"
#include "tensorflow/core/framework/graph.pb.h"
#include "tensorflow/core/framework/node_def_util.h"
#include "tensorflow/core/lib/core/errors.h"
namespace tensorflow {
Status GetNodeAttr(const NodeDef& node_def, StringPiece attr_name,
MirrorPadMode* value) {
string str_value;
TF_RETURN_IF_ERROR(GetNodeAttr(node_def, attr_name, &str_value));
if (str_value == "REFLECT") {
*value = MirrorPadMode::REFLECT;
} else if (str_value == "SYMMETRIC") {
*value = MirrorPadMode::SYMMETRIC;
} else {
return errors::NotFound(str_value, " is not an allowed padding mode.");
}
return Status::OK();
}
string GetMirrorPadModeAttrString() { return "mode: {'REFLECT', 'SYMMETRIC'}"; }
} // end namespace tensorflow
| C++ | 4 | abhaikollara/tensorflow | tensorflow/core/util/mirror_pad_mode.cc | [
"Apache-2.0"
]
|
CREATE TABLE `tb_aafdasghga` (
`col_uayhwfkoln` longtext CHARACTER SET utf8mb4,
`col_qskwbkbegb` decimal(16,0) DEFAULT NULL,
`col_fxicikwsct` float NOT NULL,
`col_ygghjheerk` text CHARACTER SET utf8,
`col_zbenqlvted` binary(1) DEFAULT NULL,
`col_ixseptopfk` date DEFAULT '2019-07-04',
`col_iafihazdod` char(1) NOT NULL,
UNIQUE KEY `col_fxicikwsct` (`col_fxicikwsct`),
UNIQUE KEY `col_zbenqlvted` (`col_zbenqlvted`)
) ENGINE=InnoDB DEFAULT CHARSET=latin1;
| SQL | 3 | yuanweikang2020/canal | parse/src/test/resources/ddl/alter/mysql_25.sql | [
"Apache-2.0"
]
|
-- Test data.
CREATE DATABASE showdb;
USE showdb;
CREATE TABLE tbl(a STRING, b INT, c STRING, d STRING) USING parquet;
CREATE VIEW view_1 AS SELECT * FROM tbl;
CREATE VIEW view_2 AS SELECT * FROM tbl WHERE c='a';
CREATE GLOBAL TEMP VIEW view_3 AS SELECT 1 as col1;
CREATE TEMPORARY VIEW view_4(e INT) USING parquet;
-- SHOW VIEWS
SHOW VIEWS;
SHOW VIEWS FROM showdb;
SHOW VIEWS IN showdb;
SHOW VIEWS IN global_temp;
-- SHOW VIEWS WITH wildcard match
SHOW VIEWS 'view_*';
SHOW VIEWS LIKE 'view_1*|view_2*';
SHOW VIEWS IN showdb 'view_*';
SHOW VIEWS IN showdb LIKE 'view_*';
-- Error when database not exists
SHOW VIEWS IN wrongdb LIKE 'view_*';
-- Clean Up
DROP VIEW global_temp.view_3;
DROP VIEW view_4;
USE default;
DROP DATABASE showdb CASCADE;
| SQL | 4 | OlegPt/spark | sql/core/src/test/resources/sql-tests/inputs/show-views.sql | [
"Apache-2.0"
]
|
/*
* Copyright 2007 The Fornax Project Team, including the original
* author or authors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package org.sculptor.generator.template.doc
import javax.inject.Inject
import org.sculptor.generator.chain.ChainOverridable
import org.sculptor.generator.ext.Helper
import org.sculptor.generator.util.OutputSlot
import sculptormetamodel.Application
/**
* Generates summary documentation of the domain model.
*/
@ChainOverridable
class ModelDocCssTmpl {
@Inject extension Helper helper
def String docCss(Application it) {
fileOutput("DomainModelDoc.css", OutputSlot.TO_DOC, '''
/* main elements */
body,div,td {
font-family: Arial, Helvetica, sans-serif;
font-size: 12px;
color: #000;
}
body {
background-color: #fff;
background-position: top center;
background-repeat: no-repeat;
text-align: center;
min-width: 800px;
margin-top: 30px;
margin-left: 30px;
margin-right: auto;
}
div {
text-align: left;
}
div .toc {
display:block;
margin-left:105px;
}
/* header and footer elements */
#wrap {
margin:0 auto;
position:relative;
float:center;
top: 0px;
left:0px;
width:750px;
text-align:left;
}
#main {
margin:0 auto;
position:relative;
float:left;
top: 35px;
left:0px;
width:700px;
height:700px;
text-align:left;
}
#graph {
margin:0 auto;
position:relative;
float:left;
top: 35px;
left:0px;
text-align:left;
}
#module_graph {
margin:0 auto;
position:relative;
float:left;
top: 35px;
bottom: 35px;
left:0px;
text-align:left;
}
#services {
margin:0 auto;
position:relative;
float:left;
top: 35px;
width:100%;
}
#consumers {
margin:0 auto;
position:relative;
float:left;
top: 35px;
width:100%;
}
#domainObjects {
margin:0 auto;
position:relative;
float:left;
top: 35px;
width:100%;
}
.footer {
background:#fff;
border:none;
margin-top:20px;
border-top:1px solid #999999;
width:100%;
}
.footer td {color:#999999;}
.footer a:link {color: #7db223;}
h1,h2,h3 {
font-family: Helvetica, sans-serif;
color: #ae8658;
}
h1 {
font-size: 20px;
line-height: 26px;
}
h2 {
font-size: 18px;
line-height: 20px;
}
h3 {
font-size: 15px;
line-height: 21px;
color:#555;
}
h4 {
font-size: 14px;
line-height: 20px;
}
a {
text-decoration: underline;
font-size: 13px;
}
a:link {
color: #ae8658;
}
a:hover {
color: #456314;
}
a:active {
color: #ae8658;
}
a:visited {
color: #ae8658;
}
/* table elements */
table {
background: #EEEEEE;
margin: 2px 0 0 0;
border: 1px solid #BBBBBB;
border-collapse: collapse;
}
table table {
margin: -5px 0;
border: 0px solid #e0e7d3;
width: 100%;
}
table td,table th {
padding: 5px;
border: 1px solid #BBBBBB;
}
table th {
font-size: 11px;
text-align: left;
font-weight: bold;
color: #FFFFFF;
}
table thead {
font-weight: bold;
font-style: italic;
background-color: #BBBBBB;
}
caption {
caption-side: top;
width: auto;
text-align: left;
font-size: 12px;
color: #848f73;
padding-bottom: 4px;
}
table a:link {color: #303030;}
#menu {
background: #eee;
position:relative;
float:left;
top: 35px;
left:0px;
width:300px;
}
#menu ul{
list-style: none;
margin: 0;
padding: 0;
}
#menu ul li{
padding: 0px;
margin-left: 20px;
}
#menu a, #menu h2 {
display: block;
margin: 0;
color:#FFFFFF;
}
#menu h2 {
color: #fff;
background: #648C1D;
font-weight:bold;
font-size: 2em;
}
#menu a {
color: #666666;
background: #efefef;
text-decoration: none;
padding: 2px 12px;
}
#menu a:hover {
color: #648C1D;
background: #fff;
}
img {
border: 0;
}
#graph img {
display: block;
max-width: 680px;
max-height: 680px;
}
#module_graph img {
display: block;
max-width: 680px;
max-height: 680px;
}
#operation {
margin-left:40px;
}
#operation_parameters {
margin-left:20px;
}
#operation_returns {
margin-left:20px;
}
'''
)
}
}
| Xtend | 4 | sculptor/sculptor | sculptor-generator/sculptor-generator-templates/src/main/java/org/sculptor/generator/template/doc/ModelDocCssTmpl.xtend | [
"Apache-2.0"
]
|
/*---------------------------------------------------------------------------------------------
* Copyright (c) Microsoft Corporation. All rights reserved.
* Licensed under the MIT License. See License.txt in the project root for license information.
*--------------------------------------------------------------------------------------------*/
.monaco-workbench .call-hierarchy .results,
.monaco-workbench .call-hierarchy .message {
display: none;
}
.monaco-workbench .call-hierarchy[data-state="data"] .results {
display: inherit;
height: 100%;
}
.monaco-workbench .call-hierarchy[data-state="message"] .message {
display: flex;
align-items: center;
justify-content: center;
height: 100%;
}
.monaco-workbench .call-hierarchy .editor,
.monaco-workbench .call-hierarchy .tree {
height: 100%;
}
.monaco-workbench .call-hierarchy .tree .callhierarchy-element {
display: flex;
flex: 1;
flex-flow: row nowrap;
align-items: center;
}
.monaco-workbench .call-hierarchy .tree .callhierarchy-element .monaco-icon-label {
padding-left: 4px;
}
| CSS | 2 | chanmaoooo/vscode | src/vs/workbench/contrib/callHierarchy/browser/media/callHierarchy.css | [
"MIT"
]
|
globals
[
max-resource ; maximum amount any patch can hold
]
patches-own
[
resource-here ; the current amount of resource on this patch
max-resource-here ; the maximum amount of resource this patch can hold
]
turtles-own
[
wealth ; the amount of resource a turtle has
vision ; how many patches ahead a turtle can see
norm-min-resource ; minimum amount of resources on patch before agent will harvest
copied-norm
harvestedlevel
]
;;;
;;; SETUP AND HELPERS
;;;
to setup
clear-all
;; set global variables to appropriate values
set max-resource 50
;; call other procedures to set up various parts of the world
setup-patches
setup-turtles
reset-ticks
end
;; set up the initial amounts of resource each patch has
to setup-patches
;; give some patches the highest amount of resource possible --
;; these patches are the "best land"
ask patches
[ set max-resource-here 0
if (random-float 100.0) <= percent-best-land
[ set max-resource-here max-resource
set resource-here max-resource-here ] ]
;; spread that resource around the window a little and put a little back
;; into the patches that are the "best land" found above
repeat 5
[ ask patches with [max-resource-here != 0]
[ set resource-here max-resource-here ]
diffuse resource-here 0.25 ]
repeat 10
[ diffuse resource-here 0.25 ] ;; spread the resource around some more
ask patches
[ set resource-here floor resource-here ;; round resource levels to whole numbers
set max-resource-here resource-here ;; initial resource level is also maximum
recolor-patch ]
end
to recolor-patch ;; patch procedure -- use color to indicate resource level
set pcolor scale-color yellow resource-here 0 max-resource
end
;; set up the initial values for the turtle variables
to setup-turtles
set-default-shape turtles "person"
crt num-people
[ move-to one-of patches ;; put turtles on patch centers
set size 1.5 ;; easier to see
set color red
set norm-min-resource min-resource
set-initial-turtle-vars ]
end
to set-initial-turtle-vars
face one-of neighbors4
set wealth 0
set vision 1 + random max-vision
end
;;;
;;; GO AND HELPERS
;;;
to go
ask turtles [ turn-towards-resource ] ;; choose direction holding most resource within the turtle's vision
ask turtles [ fd 1]
harvest
ask turtles [ set wealth wealth * discount]
monitor
if imitate? [imitate]
ask turtles [
if wealth < 0 [set wealth 0 set norm-min-resource [norm-min-resource] of one-of turtles with [who != self]]]
ask patches [ grow-resource ]
ask turtles [set size 0.5 + 2 * norm-min-resource]
tick
end
;; determine the direction which is most profitable for each turtle in
;; the surrounding patches within the turtles' vision
to turn-towards-resource ;; turtle procedure
set heading 0
let best-direction [0]
let best-amount resource-ahead
set heading 90
if (resource-ahead = best-amount) [
set best-direction lput 90 best-direction]
if (resource-ahead > best-amount)
[ set best-direction [90]
set best-amount resource-ahead ]
set heading 180
if (resource-ahead = best-amount) [
set best-direction lput 180 best-direction]
if (resource-ahead > best-amount)
[ set best-direction [180]
set best-amount resource-ahead ]
set heading 270
if (resource-ahead = best-amount) [
set best-direction lput 270 best-direction]
if (resource-ahead > best-amount)
[ set best-direction [270]
set best-amount resource-ahead ]
ifelse best-amount > norm-min-resource [
set heading one-of best-direction
][
set heading one-of [0 90 180 270]
]
end
to-report resource-ahead ;; turtle procedure
let total 0
let how-far 1
repeat vision
[ set total total + [resource-here] of patch-ahead how-far
set how-far how-far + 1 ]
report total
end
to grow-resource ;; patch procedure
if max-resource-here > 0 [
set resource-here resource-here + regrowth-rate * resource-here * (1 - resource-here / max-resource-here)]
recolor-patch
end
;; each turtle harvests the resource on its patch.
to harvest
ask turtles [set harvestedlevel 10]
ask turtles [ if resource-here >= 1 and resource-here >= (norm-min-resource * max-resource-here) [
set harvestedlevel resource-here / max-resource-here
set resource-here resource-here - 1
set wealth wealth + 1]
]
ask turtles [recolor-patch ]
end
to imitate
ask turtles [set copied-norm norm-min-resource]
ask turtles [
let otheragent one-of other turtles-here
if otheragent != nobody [
let ratio 0
if [wealth] of otheragent > 0 [set ratio wealth / [wealth] of otheragent]
let probability 1 - ratio
if probability > 1 [set probability 1]
if probability < 0 [set probability 0]
if random-float 1 < probability [
set copied-norm [norm-min-resource] of otheragent + random-normal 0 stdeverror
if copied-norm > 1 [set copied-norm 1]
if copied-norm < 0 [set copied-norm 0]
]
]
]
ask turtles [set norm-min-resource copied-norm]
end
to monitor
ask turtles [
if wealth > costpunish [
let otheragent min-one-of turtles in-radius radius [harvestedlevel]
if otheragent != nobody [
if [harvestedlevel] of otheragent < norm-min-resource [
set wealth wealth - costpunish
ask otheragent [set wealth wealth - costpunished]
]
]
]
]
end
@#$#@#$#@
GRAPHICS-WINDOW
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189
85
222
setup
setup
NIL
1
T
OBSERVER
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176
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go
go
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1
T
OBSERVER
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max-vision
max-vision
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259
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num-people
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1000
250
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percent-best-land
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%
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Resource
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"" ""
PENS
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SLIDER
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80
177
113
min-resource
min-resource
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HORIZONTAL
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discount
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Wealth
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NIL
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PENS
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SWITCH
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imitate?
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332
stdeverror
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costpunish
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costpunished
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@#$#@#$#@
## WHAT IS IT?
This model simulates the distribution of wealth. "The rich get richer and the poor get poorer" is a familiar saying that expresses inequity in the distribution of wealth. In this simulation, we see Pareto's law, in which there are a large number of "poor" or red people, fewer "middle class" or green people, and many fewer "rich" or blue people.
## HOW IT WORKS
This model is adapted from Epstein & Axtell's "Sugarscape" model. It uses grain instead of sugar. Each patch has an amount of grain and a grain capacity (the amount of grain it can grow). People collect grain from the patches, and eat the grain to survive. How much grain each person accumulates is his or her wealth.
The model begins with a roughly equal wealth distribution. The people then wander around the landscape gathering as much grain as they can. Each person attempts to move in the direction where the most grain lies. Each time tick, each person eats a certain amount of grain. This amount is called their metabolism. People also have a life expectancy. When their lifespan runs out, or they run out of grain, they die and produce a single offspring. The offspring has a random metabolism and a random amount of grain, ranging from the poorest person's amount of grain to the richest person's amount of grain. (There is no inheritance of wealth.)
To observe the equity (or the inequity) of the distribution of wealth, a graphical tool called the Lorenz curve is utilized. We rank the population by their wealth and then plot the percentage of the population that owns each percentage of the wealth (e.g. 30% of the wealth is owned by 50% of the population). Hence the ranges on both axes are from 0% to 100%.
Another way to understand the Lorenz curve is to imagine that there are 100 dollars of wealth available in a society of 100 people. Each individual is 1% of the population and each dollar is 1% of the wealth. Rank the individuals in order of their wealth from greatest to least: the poorest individual would have the lowest ranking of 1 and so forth. Then plot the proportion of the rank of an individual on the y-axis and the portion of wealth owned by this particular individual and all the individuals with lower rankings on the x-axis. For example, individual Y with a ranking of 20 (20th poorest in society) would have a percentage ranking of 20% in a society of 100 people (or 100 rankings) --- this is the point on the y-axis. The corresponding plot on the x-axis is the proportion of the wealth that this individual with ranking 20 owns along with the wealth owned by the all the individuals with lower rankings (from rankings 1 to 19). A straight line with a 45 degree incline at the origin (or slope of 1) is a Lorenz curve that represents perfect equality --- everyone holds an equal part of the available wealth. On the other hand, should only one family or one individual hold all of the wealth in the population (i.e. perfect inequity), then the Lorenz curve will be a backwards "L" where 100% of the wealth is owned by the last percentage proportion of the population. In practice, the Lorenz curve actually falls somewhere between the straight 45 degree line and the backwards "L".
For a numerical measurement of the inequity in the distribution of wealth, the Gini index (or Gini coefficient) is derived from the Lorenz curve. To calculate the Gini index, find the area between the 45 degree line of perfect equality and the Lorenz curve. Divide this quantity by the total area under the 45 degree line of perfect equality (this number is always 0.5 --- the area of 45-45-90 triangle with sides of length 1). If the Lorenz curve is the 45 degree line then the Gini index would be 0; there is no area between the Lorenz curve and the 45 degree line. If, however, the Lorenz curve is a backwards "L", then the Gini-Index would be 1 --- the area between the Lorenz curve and the 45 degree line is 0.5; this quantity divided by 0.5 is 1. Hence, equality in the distribution of wealth is measured on a scale of 0 to 1 --- more inequity as one travels up the scale. Another way to understand (and equivalently compute) the Gini index, without reference to the Lorenz curve, is to think of it as the mean difference in wealth between all possible pairs of people in the population, expressed as a proportion of the average wealth (see Deltas, 2003 for more).
## HOW TO USE IT
The PERCENT-BEST-LAND slider determines the initial density of patches that are seeded with the maximum amount of grain. This maximum is adjustable via the MAX-GRAIN variable in the SETUP procedure in the procedures window. The GRAIN-GROWTH-INTERVAL slider determines how often grain grows. The NUM-GRAIN-GROWN slider sets how much grain is grown each time GRAIN-GROWTH-INTERVAL allows grain to be grown.
The NUM-PEOPLE slider determines the initial number of people. LIFE-EXPECTANCY-MIN is the shortest number of ticks that a person can possibly live. LIFE-EXPECTANCY-MAX is the longest number of ticks that a person can possibly live. The METABOLISM-MAX slider sets the highest possible amount of grain that a person could eat per clock tick. The MAX-VISION slider is the furthest possible distance that any person could see.
GO starts the simulation. The TIME ELAPSED monitor shows the total number of clock ticks since the last setup. The CLASS PLOT shows a line plot of the number of people in each class over time. The CLASS HISTOGRAM shows the same information in the form of a histogram. The LORENZ CURVE plot shows the Lorenz curve of the population at a particular time as well as the 45 degree line of equality. The GINI-INDEX V. TIME plot shows the Gini index at the time that the Lorenz curve is drawn. The LORENZ CURVE and the GINI-INDEX V. TIME plots are updated every 5 passes through the GO procedure.
## THINGS TO NOTICE
Notice the distribution of wealth. Are the classes equal?
This model usually demonstrates Pareto's Law, in which most of the people are poor, fewer are middle class, and very few are rich. Why does this happen?
Do poor families seem to stay poor? What about the rich and the middle class people?
Watch the CLASS PLOT to see how long it takes for the classes to reach stable values.
As time passes, does the distribution get more equalized or more skewed? (Hint: observe the Gini index plot.)
Try to find resources from the U.S. Government Census Bureau for the U.S.'s Gini coefficient. Are the Gini coefficients that you calculate from the model comparable to those of the Census Bureau? Why or why not?
Is there a trend in the plotting of the Gini index with respect to time? Does the plot oscillate? Or does it stabilize to a certain number?
## THINGS TO TRY
Are there any settings that do not result in a demonstration of Pareto's Law?
Play with the NUM-GRAIN-GROWN slider, and see how this affects the distribution of wealth.
How much does the LIFE-EXPECTANCY-MAX matter?
Change the value of the MAX-GRAIN variable (in the `setup` procedure in the Code tab). Do outcomes differ?
Experiment with the PERCENT-BEST-LAND and NUM-PEOPLE sliders. How do these affect the outcome of the distribution of wealth?
Try having all the people start in one location. See what happens.
Try setting everyone's initial wealth as being equal. Does the initial endowment of an individual still arrive at an unequal distribution in wealth? Is it less so when setting random initial wealth for each individual?
Try setting all the individual's wealth and vision to being equal. Do you still arrive at an unequal distribution of wealth? Is it more equal in the measure of the Gini index than with random endowments of vision?
## EXTENDING THE MODEL
Have each newborn inherit a percentage of the wealth of its parent.
Add a switch or slider which has the patches grow back all or a percentage of their grain capacity, rather than just one unit of grain.
Allow the grain to give an advantage or disadvantage to its carrier, such as every time some grain is eaten or harvested, pollution is created.
Would this model be the same if the wealth were randomly distributed (as opposed to a gradient)? Try different landscapes, making SETUP buttons for each new landscape.
Try allowing metabolism or vision or another characteristic to be inherited. Will we see any sort of evolution? Will the "fittest" survive?
Try adding in seasons into the model. That is to say have the grain grow better in a section of the landscape during certain times and worse at others.
How could you change the model to achieve wealth equality?
The way the procedures are set up now, one person will sometimes follow another. You can see this by setting the number of people relatively low, such as 50 or 100, and having a long life expectancy. Why does this phenomenon happen? Try adding code to prevent this from occurring. (Hint: When and how do people check to see which direction they should move in?)
## NETLOGO FEATURES
Examine how the landscape of color is created --- note the use of the `scale-color` reporter. Each patch is given a value, and `scale-color` reports a color for each patch that is scaled according to its value.
Note the use of lists in drawing the Lorenz Curve and computing the Gini index.
## CREDITS AND REFERENCES
This model is based on a model described in Epstein, J. & Axtell R. (1996). Growing Artificial Societies: Social Science from the Bottom Up. Washington, DC: Brookings Institution Press.
For an explanation of Pareto's Law, see http://www.xrefer.com/entry/445978.
For more on the calculation of the Gini index see:
* Deltas, George (2003). The Small-Sample Bias of the Gini Coefficient: Results and Implications for Empirical Research. The Review of Economics and Statistics, February 2003, 85(1): 226-234.
In particular, note that if one is calculating the Gini index of a sample for the purpose of estimating the value for a larger population, a small correction factor to the method used here may be needed for small samples.
## HOW TO CITE
If you mention this model in a publication, we ask that you include these citations for the model itself and for the NetLogo software:
- Wilensky, U. (1998). NetLogo Wealth Distribution model. http://ccl.northwestern.edu/netlogo/models/WealthDistribution. Center for Connected Learning and Computer-Based Modeling, Northwestern University, Evanston, IL.
- Wilensky, U. (1999). NetLogo. http://ccl.northwestern.edu/netlogo/. Center for Connected Learning and Computer-Based Modeling, Northwestern University, Evanston, IL.
## COPYRIGHT AND LICENSE
Copyright 1998 Uri Wilensky.
This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 3.0 License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-sa/3.0/ or send a letter to Creative Commons, 559 Nathan Abbott Way, Stanford, California 94305, USA.
Commercial licenses are also available. To inquire about commercial licenses, please contact Uri Wilensky at [email protected].
This model was created as part of the project: CONNECTED MATHEMATICS: MAKING SENSE OF COMPLEX PHENOMENA THROUGH BUILDING OBJECT-BASED PARALLEL MODELS (OBPML). The project gratefully acknowledges the support of the National Science Foundation (Applications of Advanced Technologies Program) -- grant numbers RED #9552950 and REC #9632612.
This model was converted to NetLogo as part of the projects: PARTICIPATORY SIMULATIONS: NETWORK-BASED DESIGN FOR SYSTEMS LEARNING IN CLASSROOMS and/or INTEGRATED SIMULATION AND MODELING ENVIRONMENT. The project gratefully acknowledges the support of the National Science Foundation (REPP & ROLE programs) -- grant numbers REC #9814682 and REC-0126227. Converted from StarLogoT to NetLogo, 2001.
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Polygon -10899396 true false 195 90 225 75 245 75 260 89 269 108 261 124 240 105 225 105 210 105
Polygon -10899396 true false 105 90 75 75 55 75 40 89 31 108 39 124 60 105 75 105 90 105
Polygon -10899396 true false 132 85 134 64 107 51 108 17 150 2 192 18 192 52 169 65 172 87
Polygon -10899396 true false 85 204 60 233 54 254 72 266 85 252 107 210
Polygon -7500403 true true 119 75 179 75 209 101 224 135 220 225 175 261 128 261 81 224 74 135 88 99
wheel
false
0
Circle -7500403 true true 3 3 294
Circle -16777216 true false 30 30 240
Line -7500403 true 150 285 150 15
Line -7500403 true 15 150 285 150
Circle -7500403 true true 120 120 60
Line -7500403 true 216 40 79 269
Line -7500403 true 40 84 269 221
Line -7500403 true 40 216 269 79
Line -7500403 true 84 40 221 269
x
false
0
Polygon -7500403 true true 270 75 225 30 30 225 75 270
Polygon -7500403 true true 30 75 75 30 270 225 225 270
@#$#@#$#@
NetLogo 5.0.2
@#$#@#$#@
@#$#@#$#@
@#$#@#$#@
@#$#@#$#@
@#$#@#$#@
default
0.0
-0.2 0 1.0 0.0
0.0 1 1.0 0.0
0.2 0 1.0 0.0
link direction
true
0
Line -7500403 true 150 150 30 225
Line -7500403 true 150 150 270 225
@#$#@#$#@
0
@#$#@#$#@
| NetLogo | 5 | ajnavarro/language-dataset | data/github.com/comses/intro-to-abm/0138451b48c0a23ca6ca19378bf5c3bb25ddcc3e/assets/netlogo/resourceharvest.nlogo | [
"MIT"
]
|
= The Molly Project =
http://mollyproject.org/
The Molly Project is a Django-based Python application which provides a
framework for creating a mobile web portal for higher education institutions.
Please do Fork our code! We're looking for more contributors to the project.
{{https://secure.travis-ci.org/mollyproject/mollyproject.png?branch=master|Build Status}}
== Get Started ==
The 'quickinstall' script will automate the whole process of deploying Molly for
you on Linux (particularly Fedora and Ubuntu), including configuring Postgres
as needed.
For more information, please read the docs: http://docs.mollyproject.org/
== Get in Touch ==
At the time of writing there are a few primary methods of getting (free, best
effort) support for the Molly Project:
* Issue Tracker: http://issues.mollyproject.org/
* Mailing lists: https://sourceforge.net/mail/?group_id=309230
* IRC: irc://irc.freenode.net/#molly
* Email the main contributing team (Mobile Oxford at Oxford University
Computing Services): [email protected]
| Creole | 1 | mollyproject/mollyproject | README.creole | [
"Apache-2.0"
]
|
<!doctype html>
<html>
<head>
<script src="../test_bootstrap.js"></script>
<script type="text/javascript">
goog.require('bot.dom');
goog.require('goog.testing.jsunit');
</script>
</head>
<body>
<h1>Page for Shadow DOM tests</h1>
<div id="is-shown">Foo</div>
<div id="is-shown-in-shadow"></div>
<div id="is-shown-directly-in-shadow"></div>
<div id="is-shown-in-slot"><div>Foo</div></div>
<div id="get-parent"><div></div></div>
<div id="get-parent-slot"><div></div></div>
<div id="get-text">Foo</div>
<div id="get-text-shadow"></div>
<div id="get-text-slot">Foo</div>
<div id="get-text-slots">
<div slot="a">Foo</div>
<div slot="b">Bar</div>
<div slot="c">Baz</div>
</div>
<script>
var elementIsShownInShadow;
var elementIsShown;
var elementIsShownDirectlyInShadow;
var elementIsShownInSlot;
var elementGetParent;
var elementGetParentSlot;
var elementGetText;
var elementGetTextShadow;
var elementGetTextSlot;
var elementGetTextSlots;
if (bot.dom.IS_SHADOW_DOM_ENABLED) {
elementIsShownInShadow =
document.querySelector('#is-shown-in-shadow');
elementIsShownInShadow.attachShadow({ mode: 'open' });
elementIsShownInShadow.shadowRoot.innerHTML =
'<div><div class="test">Foo</div></div>';
elementIsShownDirectlyInShadow =
document.querySelector('#is-shown-directly-in-shadow');
elementIsShownDirectlyInShadow.attachShadow({ mode: 'open' });
elementIsShownDirectlyInShadow.shadowRoot.innerHTML =
'<div>Foo</div>';
elementIsShown = document.querySelector('#is-shown');
elementIsShownInSlot =
document.querySelector('#is-shown-in-slot');
elementIsShownInSlot.attachShadow({ mode: 'open' });
elementIsShownInSlot.shadowRoot.innerHTML =
'<slot></slot>';
elementGetParent =
document.querySelector('#get-parent');
elementGetParentSlot =
document.querySelector('#get-parent-slot');
elementGetParentSlot.attachShadow({ mode: 'open' });
elementGetParentSlot.shadowRoot.innerHTML =
'<div><slot></slot></div>';
elementGetText =
document.querySelector('#get-text');
elementGetTextShadow =
document.querySelector('#get-text-shadow');
elementGetTextShadow.attachShadow({ mode: 'open' });
elementGetTextShadow.shadowRoot.innerHTML = 'foo';
elementGetTextSlot =
document.querySelector('#get-text-slot');
elementGetTextSlot.attachShadow({ mode: 'open' });
elementGetTextSlot.shadowRoot.innerHTML =
'<span>a</span><slot></slot><span>b</span>';
elementGetTextSlots =
document.querySelector('#get-text-slots');
elementGetTextSlots.attachShadow({ mode: 'open' });
elementGetTextSlots.shadowRoot.innerHTML =
'<slot name="a">Default</slot><slot name="b">Default</slot>';
}
function testIsShown() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
assert(bot.dom.isShown(elementIsShown));
elementIsShown.style.display = 'none';
assertFalse(bot.dom.isShown(elementIsShown));
}
function testIsShownInShadow() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
var el = elementIsShownInShadow
.shadowRoot
.querySelector('.test');
assert(bot.dom.isShown(el));
elementIsShownInShadow.style.display = 'none';
assertFalse(bot.dom.isShown(el));
}
function testIsShownDirectlyInShadow() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
var el = elementIsShownDirectlyInShadow
.shadowRoot
.querySelector('div');
assert(bot.dom.isShown(el));
elementIsShownDirectlyInShadow.style.display = 'none';
assertFalse(bot.dom.isShown(el));
}
function testIsShownInSlot() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
var el = elementIsShownInSlot.children[0];
assert(bot.dom.isShown(el));
elementIsShownInSlot.style.display = 'none';
assertFalse(bot.dom.isShown(el));
elementIsShownInSlot.style.display = '';
// Remove the slot, so our child is no longer slotted
elementIsShownInSlot.shadowRoot.innerHTML = '';
assertFalse(bot.dom.isShown(el));
}
function testGetParentNodeInComposedDom() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
var el = elementGetParent.children[0];
assertEquals(elementGetParent, bot.dom.getParentNodeInComposedDom(el));
el = elementGetParentSlot.children[0];
assertEquals(
elementGetParentSlot.shadowRoot.querySelector('div'),
bot.dom.getParentNodeInComposedDom(el)
);
elementGetParentSlot.shadowRoot.innerHTML = '';
assertEquals(null, bot.dom.getParentNodeInComposedDom(el));
}
function testGetVisibleText() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
assertEquals('Foo', bot.dom.getVisibleText(elementGetText));
}
function testGetVisibleTextInShadow() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
assertEquals('foo', bot.dom.getVisibleText(elementGetTextShadow));
}
function testGetVisibleTextInSlot() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
assertEquals('aFoob', bot.dom.getVisibleText(elementGetTextSlot));
}
function testGetVisibleTextInSlots() {
if (!bot.dom.IS_SHADOW_DOM_ENABLED) {
return;
}
assertEquals('Foo\nBar', bot.dom.getVisibleText(elementGetTextSlots));
}
</script>
</body>
</html>
| HTML | 4 | weilandia/selenium | javascript/atoms/test/html5/shadow_dom_test.html | [
"Apache-2.0"
]
|
insheet using "/home/skipper/statsmodels/statsmodels-skipper/scikits/statsmodels/datasets/macrodata/macrodata.csv", double clear
gen qtrdate=yq(year,quarter)
format qtrdate %tq
tsset qtrdate
gen lgdp = log(realgdp)
gen lcons = log(realcons)
gen linv = log(realinv)
gen gdp = D.lgdp
gen cons = D.lcons
gen inv = D.linv
matrix A = (1,0,0\.,1,0\.,.,1)
matrix B = (.,0,0\0,.,0\0,0,.)
svar gdp cons inv, aeq(A) beq(B) lags(1/3) var
| Stata | 3 | madhushree14/statsmodels | statsmodels/tsa/vector_ar/tests/svar.do | [
"BSD-3-Clause"
]
|
-@ var title: String = "Kitten list"
- import org.preownedkittens.database._
- import play.api.data._
-@ val kittens: List[Kitten]
-@ val attributes: List[Attribute]
%h1
=kittens.size()
kitten(s)
%ul
= collection(kittens, "list")
%h2
Please find me a kitten!
%form{:action => "/selected", :method => "POST"}
%table
%tr
%td Attribute 1
%td
= render("select_attribute.scaml", Map("name" -> "select1", "it" -> attributes))
%tr
%td Attribute 2
%td
= render("select_attribute.scaml", Map("name" -> "select2", "it" -> attributes))
%tr
%td Attribute 3
%td
= render("select_attribute.scaml", Map("name" -> "select3", "it" -> attributes))
%input#findKitten{:type => "submit", :value => "Find me a kitten"}
| Scaml | 3 | matthewfarwell/sbt-in-action-examples | chapter8/website/src/main/resources/app/views/kittens.scaml | [
"Unlicense"
]
|
functor
import
Timer(setTimer mTime) at 'x-oz://boot/Timer'
export
Alarm Delay TimerHandler DelayHandler
define
TimerBox
proc {TimerHandler _}
{Send TimerBox tick}
end
proc {DelayHandler E}
case E of delay(T V) then {Alarm T V} end
end
fun {Alarm T}
Synch
in
{Send TimerBox task({Timer.mTime}+T Synch)}
!!Synch
end
proc {Delay T}
{Wait {Alarm T}}
end
proc {ProcessTask Msgs Tasks}
case Tasks of nil then {ProcessMsg Msgs nil}
[] task(T V)|Tail then
if T=<{Timer.mTime} then V=unit {ProcessTask Msgs Tail}
else {Timer.setTimer T} {ProcessMsg Msgs Tasks} end
end
end
proc {ProcessMsg Msgs Tasks}
case Msgs of M|Msgs then
case M
of tick then {ProcessTask Msgs Tasks}
[] task(T _) then {ProcessTask Msgs {Insert Tasks T M}}
end
end
end
fun {Insert Tasks T Task}
case Tasks of nil then [Task]
[] (Head=task(T2 _))|Tail then
if T<T2 then Task|Tasks
else Head|{Insert Tail T Task} end
end
end
thread {ProcessMsg {NewPort $ TimerBox} nil} end
end
| Oz | 3 | Ahzed11/mozart2 | lib/main/sp/Timer.oz | [
"BSD-2-Clause"
]
|
<%@ params(aBlock() : String) %>Output of block: ${aBlock()} | Gosu | 2 | tcmoore32/sheer-madness | gosu-test/src/test/gosu/gw/internal/gosu/regression/TemplateThatTakesABlock.gst | [
"Apache-2.0"
]
|
-include ../tools.mk
all: $(call NATIVE_STATICLIB,foo)
$(RUSTC) foo.rs -C extra-filename=-383hf8 -C prefer-dynamic
$(RUSTC) bar.rs
$(call RUN,bar)
| Makefile | 3 | Eric-Arellano/rust | src/test/run-make-fulldeps/issue-15460/Makefile | [
"ECL-2.0",
"Apache-2.0",
"MIT-0",
"MIT"
]
|
DAFETF NAIF DAF ENCODED TRANSFER FILE
'DAF/CK '
'2'
'6'
' < DAFCAT: CK CONCATENATION > '
BEGIN_ARRAY 1 19
'LRO_LROCWAC DATA TYPE 3 '
'1021C7912B1^C'
'1021C79B9469^C'
'-14E74'
'-14C08'
'3'
'1'
19
'FFFFFFFFDD124^0'
'-55C00A72539C44^-4'
'-669E2602EFAE0C^-4'
'-223144AB21DAC8^-8'
'-8E91400FCEC9B^-6'
'8820BB752205D^-6'
'511262E8673D34^-A'
'FFFFFFFFDCEC9^0'
'-5355D6109945BC^-4'
'-68F2BCD855CF14^-4'
'-2204A945BF1C6E^-8'
'-960E2589483EB^-6'
'8EE58207C6E1A8^-6'
'52384E4607121C^-A'
'1021C7912B1^C'
'1021C79B9469^C'
'1021C7912B1^C'
'1^1'
'2^1'
END_ARRAY 1 19
TOTAL_ARRAYS 1
~NAIF/SPC BEGIN COMMENTS~
This CK is for testing with the image: /home/pgiroux/Desktop/M103595705LE.cub
This CK was generated using the following command: {}
~NAIF/SPC END COMMENTS~
| XC | 3 | ladoramkershner/ale | tests/pytests/data/M103595705LE/lrolc_2009181_2009213_v10_1_sliced_-85620.xc | [
"Unlicense"
]
|
/*
* Copyright (c) 2021, Linus Groh <[email protected]>
*
* SPDX-License-Identifier: BSD-2-Clause
*/
#include <AK/FlyString.h>
#include <LibJS/Runtime/TypedArray.h>
#include <LibWeb/Bindings/Wrapper.h>
#include <LibWeb/Encoding/TextEncoder.h>
namespace Web::Encoding {
// https://encoding.spec.whatwg.org/#dom-textencoder-encode
JS::Uint8Array* TextEncoder::encode(String const& input) const
{
auto& global_object = wrapper()->global_object();
// NOTE: The AK::String returned from PrimitiveString::string() is always UTF-8, regardless of the internal string type, so most of these steps are no-ops.
// 1. Convert input to an I/O queue of scalar values.
// 2. Let output be the I/O queue of bytes ยซ end-of-queue ยป.
// 3. While true:
// 1. Let item be the result of reading from input.
// 2. Let result be the result of processing an item with item, an instance of the UTF-8 encoder, input, output, and "fatal".
// 3. Assert: result is not an error.
// 4. If result is finished, then convert output into a byte sequence and return a Uint8Array object wrapping an ArrayBuffer containing output.
auto byte_buffer = input.to_byte_buffer();
// FIXME: Support `TypedArray::create()` with existing `ArrayBuffer`, so that we don't have to allocate two `ByteBuffer`s.
auto* typed_array = JS::Uint8Array::create(global_object, byte_buffer.size());
typed_array->viewed_array_buffer()->buffer() = move(byte_buffer);
return typed_array;
}
// https://encoding.spec.whatwg.org/#dom-textencoder-encoding
FlyString const& TextEncoder::encoding()
{
static FlyString encoding = "utf-8"sv;
return encoding;
}
}
| C++ | 4 | r00ster91/serenity | Userland/Libraries/LibWeb/Encoding/TextEncoder.cpp | [
"BSD-2-Clause"
]
|
# This file is distributed under the same license as the Django package.
#
# Translators:
# Allisson Azevedo <[email protected]>, 2014
# Carlos E C Leite - Cadu <[email protected]>, 2015-2016,2019
# Eduardo Cereto Carvalho, 2011
# semente, 2012
# Jannis Leidel <[email protected]>, 2011
# Lucas Infante <[email protected]>, 2015
msgid ""
msgstr ""
"Project-Id-Version: django\n"
"Report-Msgid-Bugs-To: \n"
"POT-Creation-Date: 2019-09-08 17:27+0200\n"
"PO-Revision-Date: 2019-10-09 16:09+0000\n"
"Last-Translator: Carlos E C Leite - Cadu <[email protected]>\n"
"Language-Team: Portuguese (Brazil) (http://www.transifex.com/django/django/"
"language/pt_BR/)\n"
"MIME-Version: 1.0\n"
"Content-Type: text/plain; charset=UTF-8\n"
"Content-Transfer-Encoding: 8bit\n"
"Language: pt_BR\n"
"Plural-Forms: nplurals=2; plural=(n > 1);\n"
msgid "GIS"
msgstr "GIS"
msgid "The base GIS field."
msgstr "O campo GIS base."
msgid ""
"The base Geometry field โ maps to the OpenGIS Specification Geometry type."
msgstr ""
"O campo Geometry bรกsico - aponta para o tipo OpenGis Specification "
"Geometry. "
msgid "Point"
msgstr "Ponto"
msgid "Line string"
msgstr "Linha string"
msgid "Polygon"
msgstr "Polรญgono"
msgid "Multi-point"
msgstr "Multiponto"
msgid "Multi-line string"
msgstr "Multilinha string"
msgid "Multi polygon"
msgstr "Multipolรญgono"
msgid "Geometry collection"
msgstr "Coleรงรฃo geomรฉtrica"
msgid "Extent Aggregate Field"
msgstr "Campo agregado extendido"
msgid "Raster Field"
msgstr "Campo Raster."
msgid "No geometry value provided."
msgstr "Nenhum valor geomรฉtrico fornecido."
msgid "Invalid geometry value."
msgstr "Valor geomรฉtrico invรกlido."
msgid "Invalid geometry type."
msgstr "Tipo geomรฉtrico invรกlido."
msgid ""
"An error occurred when transforming the geometry to the SRID of the geometry "
"form field."
msgstr ""
"Ocorreu um erro ao transformar a geometria para o SRID do campo de "
"formulรกrio de geometria."
msgid "Delete all Features"
msgstr "Deletar todas os elementos"
msgid "WKT debugging window:"
msgstr "Janela de debug WKT"
msgid "Debugging window (serialized value)"
msgstr "Janela de debug (valor seralizado)"
msgid "No feeds are registered."
msgstr "Nenhum feed foi registrado."
#, python-format
msgid "Slug %r isnโt registered."
msgstr "O Slug %r nรฃo estรก registrado."
| Gettext Catalog | 4 | jpmallarino/django | django/contrib/gis/locale/pt_BR/LC_MESSAGES/django.po | [
"BSD-3-Clause",
"0BSD"
]
|
datatype color = Red | White | Blue
fun c2s c =
case c of
Red => "Red"
| White => "White"
| Blue => "Blue"
val show_color = mkShow c2s
datatype list a = Nil | Cons of a * list a
fun isNil (t ::: Type) (ls : list t) =
case ls of
Nil => True
| _ => False
fun delist (ls : list string) : xml body [] [] =
case ls of
Nil => <xml>Nil</xml>
| Cons (h, t) => <xml>{[h]} :: {delist t}</xml>
fun main () : transaction page =
sInt <- source 0;
sFloat <- source 1.23;
sBoth <- source (7, 42.1);
sOpt <- source None;
sBool <- source True;
sColor <- source White;
sList <- source Nil;
return <xml><body>
<dyn signal={n <- signal sInt; return <xml>{[n + 3]}</xml>}/> <a onclick={set sInt 1}>Change</a><br/>
<dyn signal={n <- signal sFloat; return <xml>{[n + 1.0]}</xml>}/> <a onclick={set sFloat 4.56}>Change</a><br/>
<dyn signal={p <- signal sBoth; return <xml>{[p.1]}, {[p.2]}</xml>}/>;
<dyn signal={p <- signal sBoth; case p of
(7, _) => return <xml>Initial</xml>
| (fst, snd) => return <xml>{[fst]}, {[snd]}</xml>}/>
<a onclick={set sBoth (8, 100.001)}>Change</a><br/>
<dyn signal={o <- signal sOpt; case o of
None => return <xml>None</xml>
| Some n => return <xml>{[n]}</xml>}/>
<a onclick={set sOpt (Some 7)}>Change</a><br/>
<dyn signal={b <- signal sBool; return <xml>{[b]}</xml>}/>
<dyn signal={b <- signal sBool; if b then return <xml>Yes</xml> else return <xml>No</xml>}/>
<a onclick={set sBool False}>Change</a><br/>
<dyn signal={c <- signal sColor; return <xml>{[c]}</xml>}/>
<a onclick={set sColor Red}>Red</a>
<a onclick={set sColor White}>White</a>
<a onclick={set sColor Blue}>Blue</a><br/>
<dyn signal={ls <- signal sList; return <xml>{[isNil ls]}</xml>}/>;
<dyn signal={ls <- signal sList; return <xml>{delist ls}</xml>}/>
<a onclick={set sList (Cons ("A", Cons ("B", Nil)))}>Change</a><br/>
</body></xml>
| UrWeb | 4 | apple314159/urweb | tests/stypes.ur | [
"BSD-3-Clause"
]
|
#(assert:string=? (lyp:this-file)
(lyp:expand-path (lyp:join-path lyp:cwd "spec/user_files/inc/scheme_interface_test_contd.ly")))
#(assert:string=? (lyp:this-dir)
(lyp:expand-path (lyp:join-path lyp:cwd "spec/user_files/inc")))
\pinclude "../scheme_interface_test_3.ly" | LilyPond | 3 | HolgerPeters/lyp | spec/user_files/inc/scheme_interface_test_contd.ly | [
"MIT"
]
|
particle_system smoke
{
src = "assets/particles/smoke.png"
blendmode = add
gravity = 0,0,0
velocity = 0,0.2,0
lifetime = 2
lifetime_variance = 0.2
colour = 255,255,255,255
rotation_speed = 0.5
scale_affector = 2.4
size = 0.01
emit_rate = 15
spawn_radius = 0.1
release_count = 0
forces
{
force = -0.7,0.85,0
//force = -1,-0.2,0
//force = -1,-0.2,0
//force = -1,-0.2,0
}
affector colour
{
}
} | Component Pascal | 4 | fallahn/crogine | samples/threat_level/assets/particles/smoke.cps | [
"FTL",
"Zlib"
]
|
(defmodule test_case
(export (a 2) (a-1 2) (b 2) (d-1 2) (d-2 2))
;; We can have any attributes
(compile export_all)
(compiler lfe_comp))
(defun a (x y)
(if (> (length x) y) 'yes 'no))
(defun a-1 (x y)
(if (let ((z (length x))) (> z y)) 'yes 'no))
(defun b (x y)
(if (andalso (is_integer x) (> (+ x 1) y)) 'yes 'no))
(defun c (x y)
(case (bbb x)
((tuple 'ok z) (when (> z 5)) (bbb z))
((tuple 'ok z) (bbb z))))
;; This case is not optimised by the core compiler.
(defun d-1 (x y)
(case (list x y)
(('a 1) (tuple 'yes 1))
(('a 2) (tuple 'yes 2))
(('b _) 'no)))
;; This case is optimised by the core compiler.
(defun d-2 (x y)
(case (tuple x y)
((tuple 'a 1) (tuple 'yes 1))
((tuple 'a 2) (tuple 'yes 2))
((tuple 'b _) 'no)))
(defun bbb (x)
(tuple 'ok x))
| LFE | 5 | haetze/lfe | dev/test_case.lfe | [
"Apache-2.0"
]
|
exec("swigtest.start", -1);
s = new_Square(10);
// Functions
checkequal(do_op(s, areapt()), 100.0, "Square area");
checkequal(do_op(s, perimeterpt()), 40.0, "Square perimeter");
// Variables
checkequal(do_op(s, areavar_get()), 100.0, "Square area");
areavar_set(perimeterpt());
checkequal(do_op(s, areavar_get()), 40.0, "Square perimeter");
// Constants
checkequal(do_op(s, AREAPT_get()), 100.0, "Square area");
checkequal(do_op(s, PERIMPT_get()), 40.0, "Square perimeter");
delete_Square(s);
exec("swigtest.quit", -1);
| Scilab | 3 | kyletanyag/LL-Smartcard | cacreader/swig-4.0.2/Examples/test-suite/scilab/member_pointer_runme.sci | [
"BSD-3-Clause"
]
|
r = ''
:PLAIN
:WHILE while r.length < 9
break PLAIN if r.length > 1
:FOR for i til 2
r += i
continue WHILE
ok 0
eq r, \00
eq void, :if 1
switch
break _
true
r = :outer
:inner break inner
break outer if false
1
eq r, 1
compileThrows 'unknown label "a"' 1 'break a'
compileThrows 'duplicate label "b"' 2 '''
:b
:b break b
'''
| LiveScript | 2 | vendethiel/LiveScript | test/label.ls | [
"MIT"
]
|
%%%
%%% Authors:
%%% Gert Smolka, <[email protected]>
%%% Christian Schulte, <[email protected]>
%%%
%%% Copyright:
%%% Gert Smolka, 1997-2000
%%% Christian Schulte, 1997-2000
%%%
%%% Last change:
%%% $Date$ by $Author$
%%% $Revision$
%%%
%%% This file is part of Mozart, an implementation
%%% of Oz 3
%%% http://www.mozart-oz.org
%%%
%%% See the file "LICENSE" or
%%% http://www.mozart-oz.org/LICENSE.html
%%% for information on usage and redistribution
%%% of this file, and for a DISCLAIMER OF ALL
%%% WARRANTIES.
%%%
functor
import
FD Search
export
Return
define
fun {Knights N}
NN = N*N
%% The fields of the board are numbered from 1..NN
%% according to their lexicographic order, that is,
%% (1,1), (1,2), ..., (2,1), (2,2), ..., (N,N)
%%
%% Field: X x Y --> Field
fun {Field X Y}
X*N + Y
end
%% Neighbours: Field --> List of fields
fun {Neighbours F}
X = F mod N
Y = F div N
in
{FoldR [~2#~1 ~2#1 ~1#~2 ~1#2 1#~2 1#2 2#~1 2#1]
fun {$ U#V In}
A = X+U
B = Y+V
in
if A>=0 andthen A<N andthen B>=0 andthen B<N
then A + B*N | In
else In
end
end
nil}
end
in
proc {$ Solution}
Pred = {FD.tuple pred NN 0#NN-1}
Succ = {FD.tuple succ NN 0#NN-1}
Jump = {FD.tuple jump NN 0#NN-1} % field --> jump
in
{FD.distinct Jump}
Solution = Jump
% there are no solutions for odd N
N mod 2 = 0
% tour starts as follows: (1,1), (2,3), ...
Jump.({Field 0 0}+1) = 0
Jump.({Field 1 2}+1) = 1
% for every field F
{For 0 NN-1 1
proc {$ F}
F1=F+1
Nbs = {Neighbours F}
PF = Pred.F1
SF = Succ.F1
JF = Jump.F1
in
PF :: Nbs
SF :: Nbs
%% redundant constraint: avoid trivial cycles
SF \=: PF
%% for every neighbour G of F
{ForAll Nbs
proc {$ G}
G1=G+1 JG=Jump.G1
in
JF\=:JG
(SF=:G)
= (F=:Pred.G1)
= ((JG =: JF + 1) +
(JG =: JF - NN + 1) =: 1)
%%= (Jump.G =: {FD.modI Jump.F NN}+1)
end}
end}
{FD.distribute naive Succ}
end
end
Return = knights(proc {$}
{Search.base.one {Knights 12} _}
end
keys:[bench knights]
bench:1)
end
| Oz | 4 | Ahzed11/mozart2 | platform-test/bench/knights.oz | [
"BSD-2-Clause"
]
|
import React from "react"
import { useAuth0 } from "@auth0/auth0-react"
const Header = () => {
const { isAuthenticated, loginWithRedirect, logout } = useAuth0()
return (
<header className="bg-gray-100 text-gray-700 body-font border-b">
<div className="container mx-auto flex flex-wrap pt-3 pb-3 flex-col md:flex-row justify-between items-center">
<span className="text-xl">Gatsby Hosting Functions</span>
{isAuthenticated ? (
<button
onClick={() => logout({ returnTo: window.location.origin })}
className="inline-flex items-center text-white bg-gray-600 border-0 py-1 px-3 focus:outline-none hover:bg-gray-800 rounded text-base md:mt-0"
>
Logout
<svg
fill="none"
stroke="currentColor"
strokeLinecap="round"
strokeLinejoin="round"
strokeWidth="2"
className="w-4 h-4 ml-1"
viewBox="0 0 24 24"
>
<path d="M5 12h14M12 5l7 7-7 7"></path>
</svg>
</button>
) : (
<button
onClick={() => loginWithRedirect()}
className="inline-flex items-center text-white bg-gray-600 border-0 py-1 px-3 focus:outline-none hover:bg-gray-800 rounded text-base md:mt-0"
>
Login
<svg
fill="none"
stroke="currentColor"
strokeLinecap="round"
strokeLinejoin="round"
strokeWidth="2"
className="w-4 h-4 ml-1"
viewBox="0 0 24 24"
>
<path d="M5 12h14M12 5l7 7-7 7"></path>
</svg>
</button>
)}
</div>
</header>
)
}
export default Header
| JavaScript | 4 | waltercruz/gatsby | examples/functions-auth0/src/components/header.js | [
"MIT"
]
|
#lang scribble/manual
@title[#:style '(toc)]{The RacketScript Language and Compiler}
@defmodule[racketscript/base #:lang #:use-sources (racketscript/interop)]
@(author
(author+email "Vishesh Yadav" "[email protected]" #:obfuscate? #t)
(author+email "Stephen Chang" "[email protected]" #:obfuscate? #t))
RacketScript is an experimental Racket to JavaScript (ES6)
compiler. It allows programmers to use both JavaScript's and Racket's
ecosystem and aims to make this interoperability as smooth as
possible.
@local-table-of-contents[]
@include-section{start.scrbl}
@include-section{ffi.scrbl}
| Racket | 3 | arthertz/racketscript | racketscript-doc/racketscript/scribblings/racketscript.scrbl | [
"MIT"
]
|
class PaneletMode
attr_accessor \
:name,
:panelet_state,
:panelet_controller
def init(config)
@name = config[:name]
@panelet_state = config[:panelet_state]
@panelet_controller = config[:panelet_controller]
end
end | Opal | 3 | bcavileer/digest-rails | app/assets/javascripts/digest-rails/opal_lib/hold/panelet_mode.js.opal | [
"MIT"
]
|
# Tests that Spack ignores rule names
cflags = -Wall
rule check
command = gcc $cflags -c $in -o $out
build foo: check foo.c
| Ninja | 4 | kkauder/spack | lib/spack/spack/test/data/ninja/negative/rule/build.ninja | [
"ECL-2.0",
"Apache-2.0",
"MIT-0",
"MIT"
]
|
import React from "react"
import { Redirect } from "@reach/router"
class Home extends React.Component {
render() {
return <Redirect from="/" to="/components/" />
}
}
export default Home
| JavaScript | 4 | cwlsn/gatsby | examples/styleguide/src/pages/index.js | [
"MIT"
]
|
module examples/case_studies/ins
/*
* Models an Intentional Naming System (INS), a scheme for
* dynamic resource discovery in a dynamic environment.
*
* For a detailed description, see:
* http://sdg.lcs.mit.edu/pubs/2000/INS_ASE00.pdf
*
* author: Sarfraz Khurshid
*/
open util/relation as rel
sig Attribute {}
sig Value {}
sig Record {}
one sig Wildcard extends Value {}
sig AVTree {
values: set Value,
attributes: set Attribute,
root: values - Wildcard,
av: attributes one -> some (values - root),
va: (values - Wildcard) one -> attributes
}{
// values (and attributes) of tree are those reachable from root
values = root.*(va.av)
}
sig Query extends AVTree {} {all a:attributes | one a.av}
sig DB extends AVTree {
records : set Record,
recs: (values - root) some -> records,
lookup : Query -> (values -> records)
}{
Wildcard !in values
}
fact AddInvariants {
all db: DB {
all v: db.values | no v.(db.recs) & v.^(~(db.av).~(db.va)).(db.recs)
all a: db.attributes | all disj v1, v2: a.(db.av) |
(some rr: *((db.va).(db.av)).(db.recs) | no v1.rr & v2.rr)
}
}
pred Get [db: DB, r: Record, q: Query] {
q.values = r.~(db.recs).*(~(db.av).~(db.va))
q.attributes = q.values.~(db.av)
q.root = db.root
all a : attributes| a.~(q.va) = a.~(db.va)
all v : values | v.~(q.av) = v.~(db.av)
}
pred Conforms [db: DB, q: Query, r: Record] {
some p: Query {
db.Get[r, p]
q.va in p.va
(q.av - Attribute -> Wildcard) in p.av
}
}
pred indSubset[db : DB, q: Query, r: set Record, v: Value] {
all a : v.(q.va) |
(a.(q.av) in a.(db.av) => r in (a.(q.av)).(q.(db.lookup))) &&
(a.(q.av) = Wildcard => r in a.(db.av).*((db.va).(db.av)).(db.recs))
}
pred Lookup[db: DB, q: Query, found: set Record] {
all v: Value | not v.(q.va) in v.(db.va) => no v.(q.(db.lookup))
all v: Value | all a : v.(q.va) |
a.(q.av) != Wildcard && not a.(q.av) in a.(db.av) => no v.(q.(db.lookup))
all v: Value - Wildcard |
no v.(q.va) => v.(q.(db.lookup)) = v.*((db.va).(db.av)).(db.recs)
all v: Value |
some v.(q.va) => indSubset[db, q, v.(q.(db.lookup)), v] &&
(no r: Record - v.(q.(db.lookup)) | indSubset[db, q, v.(q.(db.lookup)) + r, v])
found = db.root.(q.(db.lookup))
}
assert CorrectLookup {
all db: DB | all q : Query | all r : Record |
Conforms [db,q,r] <=> db.Lookup[q, r]
}
pred Add [me: DB, adv: Query, r: Record, db: DB] {
// restricted version - only advertisements with fresh attributes and values added
no me.attributes & adv.attributes
me.values & adv.values = me.root
me.root = adv.root
Wildcard !in adv.values
r !in me.records
db.values = me.values + adv.values
db.attributes = me.attributes + adv.attributes
db.root = me.root
db.av = me.av + adv.av
db.va = me.va + adv.va
db.recs = me.recs + ((db.values - dom[db.va]) -> r)
}
pred RemoveWildCard[me: Query, q: Query] {
q.values = me.values - Wildcard
q.attributes = me.attributes - Wildcard.~(me.av)
q.root = me.root
q.av = me.av - Attribute -> Wildcard
q.va = me.va - Value -> Wildcard.~(me.av)
}
assert MissingAttributeAsWildcard {
all db : DB, q, q1 : Query, found: set Record |
db.Lookup[q, found] && q.RemoveWildCard[q1] => db.Lookup[q1, found]
}
| Alloy | 4 | haslab/Electrum | electrum/src/main/resources/models/examples/case_studies/ins.als | [
"MIT"
]
|
const url = new URL("image.png", import.meta.url);
it("should output asset with path", () => {
expect(url + "").toBe("data:,");
});
| JavaScript | 3 | fourstash/webpack | test/configCases/asset-modules/ignore/index.js | [
"MIT"
]
|
- if current_user && controller_name != 'registries' && ['new', 'create'].include?(action_name) && !Registry.any?
.alert.alert-danger.fade.in.text-left.alert-dismissible
button.close data-dismiss="alert" type="button"
span aria-hidden="true" ×
span.sr-only Close
.alert-message
.alert-icon.pull-left
i.fa.fa-exclamation-circle.fa-3x
p
| No registry found.
- if current_user.admin?
p
= link_to 'Click here', new_admin_registry_path
| to complete configuration.
- else
p Ask an administrator to complete configuration.
- flash.each do |key, value|
- if key == 'notice' || key == 'alert'
= render template: 'shared/_notification.html.slim',
locals: { messages: value, alert: key, float: flash[:float] }
= render template: 'shared/_notification.html.slim',
locals: { messages: nil, alert: 'info', float: true }
| Slim | 3 | xybots/Portus | app/views/shared/_notifications.html.slim | [
"Apache-2.0"
]
|
/*
Grammar for COU hierarchy class
*/
%{
#include "descriptor.hpp"
#include "coudefs.hpp"
using namespace std;
int yyparse(void);
int yylex(void);
void yyerror(const char *str)
{
extern int g_line;
extern char* yytext;
cerr << "error[" << g_line << "]: " << str << endl;
cerr << "before symbol: " << yytext << endl;
}
ClassDescriptor* cur = 0;
%}
%union
{
std::string* m_str;
int m_int;
}
%start cou
%token <m_str> ID "identifier"
%printer { debug_stream() << *$$; } ID
%destructor { delete $$; } ID
%%
cou : '(' classes ')'
;
classes
: classes class
| class
;
class : '(' ID { cur = get_class(*$2); } '(' bases ')' '(' attributes ')' '(' methods ')' ')' { cur->finalize(); }
;
bases : bases ID { cur->add_base(get_class(*$2)); }
| /* empty */
;
attributes : attributes ID { cur->add_attr(*$2); }
| /* empty */
;
methods
: methods ID { cur->add_mthd(*$2); }
| methods operator
| /* empty */
;
operator
: '+'
| '-'
| '*'
| '/'
| '%'
| '^'
| '@'
| '$'
| '~'
| '!'
| '|'
| '&'
| '&''&'
| '|''|'
| '='
| '<'
| '>'
| '<''='
| '>''='
| '=''='
| '!''='
| '\\''\\'
;
%%
| Yacc | 5 | akrzemi1/Mach7 | media/papers/OpenPatternMatching/artifact/code/msvc/COUParser/cou.y | [
"BSD-3-Clause"
]
|
package com.baeldung;
import ratpack.groovy.Groovy
import ratpack.groovy.test.GroovyRatpackMainApplicationUnderTest;
import ratpack.test.http.TestHttpClient;
import ratpack.test.ServerBackedApplicationUnderTest;
import org.junit.Test;
import org.junit.runner.RunWith
import org.junit.runners.JUnit4
import ratpack.test.MainClassApplicationUnderTest
class RatpackGroovySpec {
ServerBackedApplicationUnderTest ratpackGroovyApp = new MainClassApplicationUnderTest(RatpackGroovyApp.class)
@Delegate TestHttpClient client = TestHttpClient.testHttpClient(ratpackGroovyApp)
@Test
void "test if app is started"() {
when:
get("")
then:
assert response.statusCode == 200
assert response.body.text == "Hello World from Ratpack with Groovy!!"
}
@Test
void "test greet with name"() {
when:
get("greet/Lewis")
then:
assert response.statusCode == 200
assert response.body.text == "Hello Lewis!!!"
}
@Test
void "test fetchUsers"() {
when:
get("fetchUsers")
then:
assert response.statusCode == 200
assert response.body.text == '[{"ID":1,"TITLE":"Mr","NAME":"Norman Potter","COUNTRY":"USA"},{"ID":2,"TITLE":"Miss","NAME":"Ketty Smith","COUNTRY":"FRANCE"}]'
}
}
| Groovy | 4 | DBatOWL/tutorials | ratpack/src/test/groovy/com/baeldung/RatpackGroovySpec.groovy | [
"MIT"
]
|
FileSystem do(
ensureDirectory = method(
"takes one argument that is the relative or absolute path to something that should be a directory. if it exists but isn't a directory, a condition will be signalled. if it exists, and is a directory, nothing is done, and if it doesn't exist it will be created.",
dir,
if(exists?(dir),
if(file?(dir),
bind(restart(ignore, fn()),
error!(Condition Error IO, text: "Can't create directory #{dir}, since it already exists and is a file"))),
createDirectory!(dir, true)
)
)
readLines = method(
"reads the full content of a file and returns a list containing each line of the file as a separate element of the list.",
filename,
if(System windows?,
readFully(filename) split("\r\n"),
readFully(filename) split("\n"))
)
)
| Ioke | 5 | olabini/ioke | src/builtin/D45_fileSystem.ik | [
"ICU",
"MIT"
]
|
Red [
Title: "Supporting Red functions for the test GUI backend"
Author: "Nenad Rakocevic"
File: %gui.red
Tabs: 4
Rights: "Copyright (C) 2017-2018 Red Foundation. All rights reserved."
License: {
Distributed under the Boost Software License, Version 1.0.
See https://github.com/red/red/blob/master/BSL-License.txt
}
]
offset-to-face: function [face [object!] pos [pair!]][
if block? face/pane [
extra: either face/type = 'window [0x0][face/offset]
foreach f face/pane [
if all [
object? f
f/visible?
within? pos - extra f/offset f/size
][
face: offset-to-face f pos - extra
break
]
]
]
face
]
make-event-wrapper: routine [
type [word!]
face [object!]
args [integer!]
][
stack/set-last as red-value! gui/OS-make-event type face args
]
do-event: function [
evt-name [word!]
/with args
/at offset [pair!]
/flags flag-list [block!]
][
flags: 0
window: last system/view/screens/1/pane
face: any [window/selected window]
if offset [face: offset-to-face window offset]
unless face [print "*** Do-event Error: no face selected!" exit]
;-- event pre-processing --
if args [
unless block? args [args: reduce [args]]
insert args evt-name
parse args [
'key pos: [char! | word!] (
if 'enter = char: pos/1 [char: lf]
flags: flags or to-integer char
)
| 'select pos: integer! (flags: flags or pos/1)
| to end
]
remove args
]
all [
find [click dbl-click down up] evt-name
find [check radio] face/type
evt-name: 'change
]
;-- pass event to View engine --
state: system/view/awake make-event-wrapper evt-name face flags
;-- event post-processing --
switch evt-name [
key [
if all [
not find [stop done] state
char >= 32
find [field area] face/type
][
either s: face/text [
modify s 'owned none ;-- disable object events on face/text
][
face/text: s: make string! 8
]
append s char
modify s 'owned face
]
do-event 'change
]
select [
set-quiet in face 'selected flags and FFFFh
do-event/with 'change flags
]
]
]
input-string: function [face [object!] text [string!]][
set-focus face
foreach c text [do-event/with 'key c]
do-event/with 'key 'enter
] | Red | 5 | 0xflotus/red | modules/view/backends/test/gui.red | [
"BSL-1.0",
"BSD-3-Clause"
]
|
#!/bin/bash
ARCHIVE=jq-1.5.tar.gz
SCRIPT_DIR=$(cd `dirname $0` && pwd)
cd $SCRIPT_DIR
rm -rf ./_install
if [ ! -f $ARCHIVE ]; then
wget https://github.com/stedolan/jq/releases/download/jq-1.5/$ARCHIVE
fi
tar zxvf $ARCHIVE
cd jq-1.5 || exit 1
./configure --host=arm-openwrt-linux --disable-docs
| JSONiq | 3 | bolt1502/yi-hack | src/jq/init.jq | [
"MIT"
]
|
/**
* @license
* Copyright Google LLC All Rights Reserved.
*
* Use of this source code is governed by an MIT-style license that can be
* found in the LICENSE file at https://angular.io/license
*/
describe('ProxySpec', () => {
let ProxyZoneSpec: any;
let delegate: ZoneSpec;
let proxyZoneSpec: any;
let proxyZone: Zone;
beforeEach(() => {
ProxyZoneSpec = (Zone as any)['ProxyZoneSpec'];
expect(typeof ProxyZoneSpec).toBe('function');
delegate = {name: 'delegate'};
proxyZoneSpec = new ProxyZoneSpec(delegate);
proxyZone = Zone.current.fork(proxyZoneSpec);
});
describe('properties', () => {
it('should expose ProxyZone in the properties', () => {
expect(proxyZone.get('ProxyZoneSpec')).toBe(proxyZoneSpec);
});
it('should assert that it is in or out of ProxyZone', () => {
let rootZone = Zone.current;
while (rootZone.parent) {
rootZone = rootZone.parent;
}
rootZone.run(() => {
expect(() => ProxyZoneSpec.assertPresent()).toThrow();
expect(ProxyZoneSpec.isLoaded()).toBe(false);
expect(ProxyZoneSpec.get()).toBe(undefined);
proxyZone.run(() => {
expect(ProxyZoneSpec.isLoaded()).toBe(true);
expect(() => ProxyZoneSpec.assertPresent()).not.toThrow();
expect(ProxyZoneSpec.get()).toBe(proxyZoneSpec);
});
});
});
it('should reset properties', () => {
expect(proxyZone.get('myTestKey')).toBe(undefined);
proxyZoneSpec.setDelegate({name: 'd1', properties: {'myTestKey': 'myTestValue'}});
expect(proxyZone.get('myTestKey')).toBe('myTestValue');
proxyZoneSpec.resetDelegate();
expect(proxyZone.get('myTestKey')).toBe(undefined);
});
});
describe('delegate', () => {
it('should set/reset delegate', () => {
const defaultDelegate: ZoneSpec = {name: 'defaultDelegate'};
const otherDelegate: ZoneSpec = {name: 'otherDelegate'};
const proxyZoneSpec = new ProxyZoneSpec(defaultDelegate);
const proxyZone = Zone.current.fork(proxyZoneSpec);
expect(proxyZoneSpec.getDelegate()).toEqual(defaultDelegate);
proxyZoneSpec.setDelegate(otherDelegate);
expect(proxyZoneSpec.getDelegate()).toEqual(otherDelegate);
proxyZoneSpec.resetDelegate();
expect(proxyZoneSpec.getDelegate()).toEqual(defaultDelegate);
});
});
describe('forwarding', () => {
beforeEach(() => {
proxyZoneSpec = new ProxyZoneSpec();
proxyZone = Zone.current.fork(proxyZoneSpec);
});
it('should fork', () => {
const forkedZone = proxyZone.fork({name: 'fork'});
expect(forkedZone).not.toBe(proxyZone);
expect(forkedZone.name).toBe('fork');
let called = false;
proxyZoneSpec.setDelegate({
name: '.',
onFork:
(parentZoneDelegate: ZoneDelegate, currentZone: Zone, targetZone: Zone,
zoneSpec: ZoneSpec) => {
expect(currentZone).toBe(proxyZone);
expect(targetZone).toBe(proxyZone), expect(zoneSpec.name).toBe('fork2');
called = true;
}
});
proxyZone.fork({name: 'fork2'});
expect(called).toBe(true);
});
it('should intercept', () => {
const fn = (a: any) => a;
expect(proxyZone.wrap(fn, 'test')('works')).toEqual('works');
proxyZoneSpec.setDelegate({
name: '.',
onIntercept:
(parentZoneDelegate: ZoneDelegate, currentZone: Zone, targetZone: Zone,
delegate: Function, source: string): Function => {
return () => '(works)';
}
});
expect(proxyZone.wrap(fn, 'test')('works')).toEqual('(works)');
});
it('should invoke', () => {
const fn = () => 'works';
expect(proxyZone.run(fn)).toEqual('works');
proxyZoneSpec.setDelegate({
name: '.',
onInvoke:
(parentZoneDelegate: ZoneDelegate, currentZone: Zone, targetZone: Zone,
delegate: Function, applyThis: any, applyArgs: any[], source: string) => {
return `(${
parentZoneDelegate.invoke(targetZone, delegate, applyThis, applyArgs, source)})`;
}
});
expect(proxyZone.run(fn)).toEqual('(works)');
});
it('should handleError', () => {
const error = new Error('TestError');
const fn = () => {
throw error;
};
expect(() => proxyZone.run(fn)).toThrow(error);
proxyZoneSpec.setDelegate({
name: '.',
onHandleError:
(parentZoneDelegate: ZoneDelegate, currentZone: Zone, targetZone: Zone, error: any):
boolean => {
expect(error).toEqual(error);
return false;
}
});
expect(() => proxyZone.runGuarded(fn)).not.toThrow();
});
it('should Task', () => {
const fn = (): any => null;
const task = proxyZone.scheduleMacroTask('test', fn, {}, () => null, () => null);
expect(task.source).toEqual('test');
proxyZone.cancelTask(task);
});
});
describe('delegateSpec change', () => {
let log: string[] = [];
beforeEach(() => {
log = [];
});
it('should trigger hasTask when invoke', (done: Function) => {
const zoneSpec1 = {
name: 'zone1',
onHasTask: (delegate: ZoneDelegate, curr: Zone, target: Zone, hasTask: HasTaskState) => {
log.push(`zoneSpec1 hasTask: ${hasTask.microTask},${hasTask.macroTask}`);
return delegate.hasTask(target, hasTask);
}
};
const zoneSpec2 = {
name: 'zone2',
onHasTask: (delegate: ZoneDelegate, curr: Zone, target: Zone, hasTask: HasTaskState) => {
log.push(`zoneSpec2 hasTask: ${hasTask.microTask},${hasTask.macroTask}`);
return delegate.hasTask(target, hasTask);
}
};
proxyZoneSpec.setDelegate(zoneSpec1);
proxyZone.run(() => {
setTimeout(() => {
log.push('timeout in zoneSpec1');
}, 50);
});
proxyZoneSpec.setDelegate(zoneSpec2);
proxyZone.run(() => {
Promise.resolve(1).then(() => {
log.push('then in zoneSpec2');
});
});
proxyZoneSpec.setDelegate(null);
proxyZone.run(() => {
setTimeout(() => {
log.push('timeout in null spec');
}, 50);
});
proxyZoneSpec.setDelegate(zoneSpec2);
proxyZone.run(() => {
Promise.resolve(1).then(() => {
log.push('then in zoneSpec2');
});
});
setTimeout(() => {
expect(log).toEqual([
'zoneSpec1 hasTask: false,true', 'zoneSpec2 hasTask: false,true',
'zoneSpec2 hasTask: true,true', 'zoneSpec2 hasTask: true,true', 'then in zoneSpec2',
'then in zoneSpec2', 'zoneSpec2 hasTask: false,true', 'timeout in zoneSpec1',
'timeout in null spec', 'zoneSpec2 hasTask: false,false'
]);
done();
}, 300);
});
});
});
| TypeScript | 5 | raghavendramohan/angular | packages/zone.js/test/zone-spec/proxy.spec.ts | [
"MIT"
]
|
BstartsJ | PureBasic | 0 | cnheider/onnx | onnx/backend/test/data/node/test_slice/test_data_set_0/input_1.pb | [
"MIT"
]
|
// Exploit.cpp : Defines the entry point for the console application.
//
#include <Windows.h>
#include "Exploit.h"
#include "Win32kLeaker.h"
#include "Exploiter.h"
#include "FontData.h"
static VOID ExecutePayload(LPVOID lpPayload)
{
VOID(*lpCode)() = (VOID(*)())lpPayload;
lpCode();
return;
}
VOID Exploit(LPVOID lpPayload)
{
// Variables.
DWORD cFonts;
PVOID pFontData = (PVOID)fontData;
DWORD ExAllocatePoolWithTag_offset;
ULONGLONG win32kBaseAddr;
ULONGLONG ntBaseAddr;
ExploiterInit();
// Leak the win32k base address.
win32kBaseAddr = LeakWin32kAddress();
if (win32kBaseAddr == NULL) {
return;
}
ExploiterSetupFirstChain(win32kBaseAddr);
ExploiterDoFengShui();
// Trigger the memory corruption: Render the font and cause memory overwrite.
cFonts = 0;
HANDLE fh = AddFontMemResourceEx(pFontData, sizeof(fontData), 0, &cFonts);
// Clean up: remove the font from memory.
RemoveFontMemResourceEx(fh);
// First Stage: Leak ntoskrnl
ExploiterRunFirstChain();
ntBaseAddr = ExploiterGetNtBase();
// Second Stage: elevate privileges
ExploiterSetupSecondChain(win32kBaseAddr, ntBaseAddr);
ExploiterRunSecondChain();
ExpoiterCleanUp();
// Exetue msf payload
ExecutePayload(lpPayload);
}
| C++ | 2 | OsmanDere/metasploit-framework | external/source/exploits/CVE-2015-2426/dll/src/Exploit.cpp | [
"BSD-2-Clause",
"BSD-3-Clause"
]
|
check_args = (name, more) ->
error "flow template takes arguments: name" unless name
if name\match "%u"
error "name should be underscore form, all lowercase"
if more
error "got a second argument to generator, did you mean to pass a string?"
filename = (name) ->
"flows/#{name}.moon"
content = (name) ->
[[import Flow from require "lapis.flow"
class ]].. name .. [[ extends Flow
]]
write = (writer, name) ->
import camelize from require "lapis.util"
tail_name = name\match("[^.]+$") or name
class_name = camelize(tail_name) .. "Flow"
path = writer\mod_to_path name
writer\write filename(path), content class_name
{:check_args, :write}
| MoonScript | 4 | tommy-mor/lapis | lapis/cmd/templates/flow.moon | [
"MIT",
"Unlicense"
]
|
#!/usr/bin/pike
// -*- mode: pike -*-
// $Id: spellcheck.pike,v 1.1 2004-05-19 18:13:26 bfulgham Exp $
// http://www.bagley.org/~doug/shootout/
void main() {
array(string) a = Stdio.read_file("Usr.Dict.Words")/"\n";
mapping dictionary = mkmapping(a, allocate(sizeof(a), 1));
while (string word = Stdio.stdin.gets()) {
if (!dictionary[word]) write("%s\n", word);
}
}
| Pike | 3 | kragen/shootout | bench/spellcheck/spellcheck.pike | [
"BSD-3-Clause"
]
|
# this file and {QtAssistant, QAssistantClient} were copied from the
# Qt 4.6.3 source code, directory "include/QtAssistant". This file
# was modified so that the Q* headers are located in the same
# directory as this file, and found relative to the .pro file that
# uses this file.
SYNCQT.HEADER_FILES = qassistantclient.h qassistantclient_global.h include/QtAssistant/QtAssistant
SYNCQT.HEADER_CLASSES = include/QtAssistant/QAssistantClient
SYNCQT.PRIVATE_HEADER_FILES =
| QMake | 2 | davidlrichmond/macports-ports | devel/qt-assistant/files/qmake/lib/include/QtAssistant/headers.pri | [
"BSD-3-Clause"
]
|
package {{invokerPackage}};
import com.fasterxml.jackson.core.JsonGenerationException;
import com.fasterxml.jackson.core.JsonGenerator;
import com.fasterxml.jackson.databind.ObjectMapper;
import com.fasterxml.jackson.databind.SerializerProvider;
import com.fasterxml.jackson.databind.ser.std.StdSerializer;
{{#java8}}
import com.fasterxml.jackson.datatype.jsr310.JavaTimeModule;
{{/java8}}
{{#joda}}
import com.fasterxml.jackson.datatype.joda.JodaModule;
import org.joda.time.DateTime;
import org.joda.time.LocalDate;
import org.joda.time.format.ISODateTimeFormat;
{{/joda}}
import javax.ws.rs.ext.ContextResolver;
import javax.ws.rs.ext.Provider;
import java.io.IOException;
@Provider
public class JacksonConfig implements ContextResolver<ObjectMapper> {
private final ObjectMapper objectMapper;
public JacksonConfig() throws Exception {
objectMapper = new ObjectMapper()
.setDateFormat(new RFC3339DateFormat()){{#legacyDates}};{{/legacyDates}}
{{#java8}}
.registerModule(new JavaTimeModule());
{{/java8}}
{{#joda}}
.registerModule(new JodaModule() {
{
addSerializer(DateTime.class, new StdSerializer<DateTime>(DateTime.class) {
@Override
public void serialize(DateTime value, JsonGenerator jgen, SerializerProvider provider) throws IOException, JsonGenerationException {
jgen.writeString(ISODateTimeFormat.dateTimeNoMillis().print(value));
}
});
addSerializer(LocalDate.class, new StdSerializer<LocalDate>(LocalDate.class) {
@Override
public void serialize(LocalDate value, JsonGenerator jgen, SerializerProvider provider) throws IOException, JsonGenerationException {
jgen.writeString(ISODateTimeFormat.date().print(value));
}
});
}
});
{{/joda}}
}
public ObjectMapper getContext(Class<?> arg0) {
return objectMapper;
}
} | HTML+Django | 4 | Nirostar/swagger-codegen | modules/swagger-codegen/src/main/resources/JavaJaxRS/resteasy/JacksonConfig.mustache | [
"Apache-2.0"
]
|
<div class="modal wide hidden" id="modal-hotkeys">
<h3>MARKDOWN & HOTKEYS</h3>
<p>here's all the cool things you can do without lifting your hands off the keyboard.</p>
<b></b>
<section>
<p class="hidden-below-tablet" ><strong>HOTKEYS</strong></p>
<table class="hidden-below-tablet lowercase">
<tr style="border-bottom: 1px solid #AAA;">
<th>action</th>
<th>mac os</th>
<th>unix & windows</th>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><b>Bold</b></td>
<td><span class="tag">โ</span> + <span class="tag">b</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">b</span></td>
</tr>
<tr>
<td><em>Italic</em></td>
<td><span class="tag">โ</span> + <span class="tag">i</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">i</span></td>
</tr>
<tr>
<td><u>Underline</u></td>
<td><span class="tag">โ</span> + <span class="tag">u</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">u</span></td>
</tr>
<tr>
<td><s>Strike</s></td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">s</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">s</span></td>
</tr>
<tr>
<td><span style="border-left: 4px solid #ccc; margin-bottom: 5px; margin-top: 5px; padding-left: 6px;"></span> Quote</td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">9</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">9</span></td>
</tr>
<tr>
<td><<span style="color:red;">Code</span> /></td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">0</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">0</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon is-small"><i class="fa fa-fw fa-check-circle-o"></i></span> Checklist</td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">6</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">6</span></td>
</tr>
<tr>
<td>1. Numbered List</td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">7</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">7</span></td>
</tr>
<tr>
<td>โ Bulleted List</td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">8</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">8</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-tag fa-fw "></i></span> Tag Document</td>
<td><span class="tag"><i>#hashtag</i></span> โ <span class="tag">tab</span></td>
<td><span class="tag"><i>#hashtag</i></span> โ <span class="tag">tab</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-clock-o fa-fw"></i></span> Show Recent Docs</td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">r</span></td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">r</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-folder fa-fw"></i></span> Show All Folders</td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">f</span></td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">f</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-window-minimize fa-fw"></i></span> Minimize File Preview</td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">m</span></td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">m</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-window-maximize fa-fw"></i></span> Maximize File Preview</td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">m</span></td>
<td><span class="tag">alt</span> + <span class="tag">Shift</span> + <span class="tag">m</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-search fa-fw"></i></span> Open Search </td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">o</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">o</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-tag fa-fw "></i></span> Navigate Search Results</td>
<td><span class="tag">Arrow keys ( ↑ ↓ )</td>
<td><span class="tag">Arrow keys ( ↑ ↓ )</td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-tag fa-fw "></i></span> Open Search Result</td>
<td><span class="tag"><span class="tag"><b>⏎</b></span></td>
<td><span class="tag"><span class="tag"><b>⏎</b></span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-tag fa-fw "></i></span> Attach/Link Search Result</td>
<td><span class="tag">Shift</span> + <span class="tag"><span class="tag"><b>⏎</b></span></td>
<td><span class="tag">Shift</span> + <span class="tag"><span class="tag"><b>⏎</b></span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span>Clear Formatting</span></td>
<td><span class="tag">โ</span> + <span class="tag">\</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">\</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-indent fa-fw"></i></span> Indent Left</td>
<td><span class="tag">โ</span> + <span class="tag">[</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">[</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-indent fa-fw fa-rotate-180"></i></span> Indent Right</td>
<td><span class="tag">โ</span> + <span class="tag">]</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">]</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-link fa-fw"></i></span> Hyperlink</td>
<td><span class="tag">โ</span> + <span class="tag">k</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">k</span></td>
</tr>
<tr>
<td>formula</td>
<td><span class="tag">โ</span> + <span class="tag">Shift</span> + <span class="tag">k</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">k</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-save fa-fw"></i></span> Force Save</td>
<td><span class="tag">โ</span> + <span class="tag">s</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">s</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-undo fa-fw"></i></span> Undo</td>
<td><span class="tag">โ</span> + <span class="tag">z</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">z</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-repeat fa-fw"></i></span> Redo</td>
<td><span class="tag">โ</span>+ <span class="tag">Shift</span> + <span class="tag">z</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">Shift</span> + <span class="tag">z</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-bars fa-fw"></i></span> Toggle Menu</td>
<td><span class="tag">โ</span> + <span class="tag">.</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">.</span></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-keyboard-o fa-fw "></i></span> Markdown & Hotkeys</span></td>
<td><span class="tag">โ</span> + <span class="tag">/</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">/</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
<td> </td>
</tr>
<tr>
<td><strong>paper / pdf mode</strong></td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-bars fa-fw"></i></span> Activate Paper / PDF Mode</td>
<td><span class="tag">โ</span> + <span class="tag">p</span></td>
<td><span class="tag">ctrl</span> + <span class="tag">p</span></td>
</tr>
<tr>
<td><span>Insert Page-Break</span></td>
<td><span class="tag">โ</span> + <span class="tag"><b>⏎</b></span></td>
<td><span class="tag">ctrl</span> + <span class="tag"><b>⏎</b></span></td>
</tr>
<tr>
<td><span>Prev Page</span></td>
<td><span class="tag">fn</span> + <span class="tag">Arrow ( ↑ )</span></td>
<td><span class="tag">Page Up</span></td>
</tr>
<tr>
<td><span>Next Page</span></td>
<td><span class="tag">fn</span> + <span class="tag">Arrow ( ↓ )</span></td>
<td> <span class="tag">Page Down</span></td>
</tr>
</table>
<br><br class="hidden-below-tablet">
<p><strong>MARKDOWN SHORTCUTS</strong></p>
<table class="lowercase">
<tr style="border-bottom: 1px solid #AAA;">
<th>Style</th>
<th>Markdown</th>
</tr>
<tr>
<td> </td>
<td> </td>
</tr>
<tr>
<td>lg header</td>
<td><span class="tag">#</span> + <span class="tag">space</span></td>
</tr>
<tr>
<td>md header</td>
<td><span class="tag">##</span> + <span class="tag">space</span></td>
</tr>
<tr>
<td>sm header</td>
<td><span class="tag">###</span> + <span class="tag">space</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
</tr>
<tr>
<td><b>Bold</b></td>
<td><span class="tag"><b>**bold**</b></span> <span class="hidden-below-tablet"> or <span class="tag"><b>__bold__</b></span></span></td>
</tr>
<tr>
<td><em>Italic</em></td>
<td><span class="tag"><b>*italic*</b></span> <span class="hidden-below-tablet"> or <span class="tag"><b>_italic_</b></span></span></td>
</tr>
<tr>
<td><s>Strike</s></td>
<td><span class="tag"><b>~~strike~~</b></span></td>
</tr>
<tr>
<td><span style="border-left: 4px solid #ccc; margin-bottom: 5px; margin-top: 5px; padding-left: 6px;"></span> Quote</td>
<td><span class="tag"><b>></b></span> + <span class="tag">space</span></td>
</tr>
<tr>
<td><code>Inline Code</code></td>
<td><span class="tag"><b>`code`</b></span></td>
</tr>
<tr>
<td><<span style="color:red;">Code</span> /> <span class="hidden-below-tablet small">(with highlighting)</span></td>
<td><span class="tag"><b>```</b></span> + <span class="tag"><b>⏎</b></span></td>
</tr>
<tr>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon is-small"><i class="fa fa-fw fa-circle-o"></i></span> Checklist</td>
<td><span class="tag"><b>[ ]</b></span> + <span class="tag">space</span></td>
</tr>
<tr>
<td><span class="icon is-small"><i class="fa fa-fw fa-check-circle-o"></i></span> <s>Checklist</s></td>
<td><span class="tag"><b>[x]</b></span> + <span class="tag">space</span></td>
</tr>
<tr>
<td>1. Num<span class="hidden-below-tablet">bered</span> List</td>
<td><span class="tag"><b>1.</b></span> + <span class="tag">space</span></td>
</tr>
<tr>
<td>โ Bull<span class="hidden-below-tablet">eted</span> List</td>
<td><span class="tag"><b>*</b></span> + <span class="tag">space</span></td>
</tr>
<tr>
<td> </td>
<td> </td>
</tr>
<tr>
<td><span class="icon"><i class="fa fa-fw fa-minus"></i></span> Divider</td>
<td><span class="tag"><b>---</b></span></td>
</tr>
<tr class="hidden-below-tablet">
<td><span class="icon"><i class="fa fa-link fa-fw"></i></span> Hyperlink</td>
<td><span class="tag"><b>[Cryptee](https://crypt.ee)</b></span> + <span class="tag"><b>⏎</b></span></td>
</tr>
<tr>
<td> </td>
<td> </td>
</tr>
</table>
</section>
<button class="action r sm" onclick="hideActiveModal()">close</button>
</div> | Kit | 3 | pws1453/web-client | source/imports/app/docs-modal-hotkeys.kit | [
"MIT"
]
|
;; this gives an gentle introduction to hy for a quick trial head to
;; http://try-hy.appspot.com
;;
; Semicolon comments, like other LISPS
;; s-expression basics
; lisp programs are made of symbolic expressions or sexps which
; resemble
(some-function args)
; now the quintessential hello world
(print "hello world")
;; simple data types
; All simple data types are exactly similar to their python counterparts
; which
42 ; => 42
3.14 ; => 3.14
True ; => True
4+10j ; => (4+10j) a complex number
; lets start with some really simple arithmetic
(+ 4 1) ;=> 5
; the operator is applied to all arguments, like other lisps
(+ 4 1 2 3) ;=> 10
(- 2 1) ;=> 1
(* 4 2) ;=> 8
(/ 4 1) ;=> 4
(% 4 2) ;=> 0 the modulo operator
; power is represented by ** operator like python
(** 3 2) ;=> 9
; nesting forms will do the expected thing
(+ 2 (* 4 2)) ;=> 10
; also logical operators and or not and equal to etc. do as expected
(= 5 4) ;=> False
(not (= 5 4)) ;=> True
;; variables
; variables are set using setv, variable names can use utf-8 except
; for ()[]{}",'`;#|
(setv a 42)
(setv ฯ 3.14159)
(def *foo* 42)
;; other container data types
; strings, lists, tuples & dicts
; these are exactly same as python's container types
"hello world" ;=> "hello world"
; string operations work similar to python
(+ "hello " "world") ;=> "hello world"
; lists are created using [], indexing starts at 0
(setv mylist [1 2 3 4])
; tuples are immutable data structures
(setv mytuple (, 1 2))
; dictionaries are key value pairs
(setv dict1 {"key1" 42 "key2" 21})
; :name can be used to define keywords in hy which can be used for keys
(setv dict2 {:key1 41 :key2 20})
; use `get' to get the element at an index/key
(get mylist 1) ;=> 2
(get dict1 "key1") ;=> 42
; Alternatively if keywords were used they can directly be called
(:key1 dict2) ;=> 41
;; functions and other program constructs
; functions are defined using defn, the last sexp is returned by default
(defn greet [name]
"A simple greeting" ; an optional docstring
(print "hello " name))
(greet "bilbo") ;=> "hello bilbo"
; functions can take optional arguments as well as keyword arguments
(defn foolists [arg1 &optional [arg2 2]]
[arg1 arg2])
(foolists 3) ;=> [3 2]
(foolists 10 3) ;=> [10 3]
; you can use rest arguments and kwargs too:
(defn something-fancy [wow &rest descriptions &kwargs props]
(print "Look at" wow)
(print "It's" descriptions)
(print "And it also has:" props))
(something-fancy "My horse" "amazing" :mane "spectacular")
; you use apply instead of the splat operators:
(apply something-fancy ["My horse" "amazing"] { "mane" "spectacular" })
; anonymous functions are created using `fn' or `lambda' constructs
; which are similar to `defn'
(map (fn [x] (* x x)) [1 2 3 4]) ;=> [1 4 9 16]
;; Sequence operations
; hy has some builtin utils for sequence operations etc.
; retrieve the first element using `first' or `car'
(setv mylist [1 2 3 4])
(setv mydict {"a" 1 "b" 2})
(first mylist) ;=> 1
; slice lists using slice
(slice mylist 1 3) ;=> [2 3]
; or, in hy 0.11, use cut instead:
(cut mylist 1 3) ;=> [2 3]
; get elements from a list or dict using `get'
(get mylist 1) ;=> 2
(get mydict "b") ;=> 2
; list indexing starts from 0 same as python
; assoc can set elements at keys/indexes
(assoc mylist 2 10) ; makes mylist [1 2 10 4]
(assoc mydict "c" 3) ; makes mydict {"a" 1 "b" 2 "c" 3}
; there are a whole lot of other core functions which makes working with
; sequences fun
;; Python interop
;; import works just like in python
(import datetime)
(import [functools [partial reduce]]) ; imports fun1 and fun2 from module1
(import [matplotlib.pyplot :as plt]) ; doing an import foo as bar
; all builtin python methods etc. are accessible from hy
; a.foo(arg) is called as (.foo a arg)
(.split (.strip "hello world ")) ;=> ["hello" "world"]
; there is a shortcut for executing multiple functions on a value called the
; "threading macro", denoted by an arrow:
(-> "hello world " (.strip) (.split)) ;=> ["hello" "world]
; the arrow passes the value along the calls as the first argument, for instance:
(-> 4 (* 3) (+ 2))
; is the same as:
(+ (* 4 3) 2)
; there is also a "threading tail macro", which instead passes the value as the
; second argument. compare:
(-> 4 (- 2) (+ 1)) ;=> 3
(+ (- 4 2) 1) ;=> 3
; to:
(->> 4 (- 2) (+ 1)) ;=> -1
(+ 1 (- 2 4)) ;=> -1
;; Conditionals
; (if condition (body-if-true) (body-if-false)
(if (= passcode "moria")
(print "welcome")
(print "Speak friend, and Enter!"))
; nest multiple if else if clauses with cond
(cond
[(= someval 42)
(print "Life, universe and everything else!")]
[(> someval 42)
(print "val too large")]
[(< someval 42)
(print "val too small")])
; group statements with do, these are executed sequentially
; forms like defn have an implicit do
(do
(setv someval 10)
(print "someval is set to " someval)) ;=> 10
; create lexical bindings with `let', all variables defined thusly
; have local scope
(let [[nemesis {"superman" "lex luther"
"sherlock" "moriarty"
"seinfeld" "newman"}]]
(for [(, h v) (.items nemesis)]
(print (.format "{0}'s nemesis was {1}" h v))))
;; classes
; classes are defined in the following way
(defclass Wizard [object]
[[--init-- (fn [self spell]
(setv self.spell spell) ; init the spell attr
None)]
[get-spell (fn [self]
self.spell)]])
; or, in hy 0.11:
(defclass Wizard [object]
(defn --init-- [self spell]
(setv self.spell spell))
(defn get-spell [self]
self.spell))
;; do checkout hylang.org
| Hy | 5 | semperos/conjure | dev/hy/sandbox.hy | [
"Unlicense"
]
|
.img {
display: inline-block;
width: 100%;
margin: 5px 0;
}
.actions {
position: relative;
bottom: 55px;
right: 10px;
width: 100%;
height: 0px;
text-align: right;
float: left;
}
.actions a {
background-color: #fff;
padding: 5px;
border-radius: 5px;
margin: 5px;
float: right;
}
| CSS | 3 | blomqma/next.js | examples/with-unsplash/components/UImage/UImage.module.css | [
"MIT"
]
|
#!/usr/bin/env bash
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership.
# The ASF licenses this file to You under the Apache License, Version 2.0
# (the "License"); you may not use this file except in compliance with
# the License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# This script is a basic example script to get resource information about NVIDIA GPUs.
# It assumes the drivers are properly installed and the nvidia-smi command is available.
# It is not guaranteed to work on all setups so please test and customize as needed
# for your environment. It can be passed into SPARK via the config
# spark.{driver/executor}.resource.gpu.discoveryScript to allow the driver or executor to discover
# the GPUs it was allocated. It assumes you are running within an isolated container where the
# GPUs are allocated exclusively to that driver or executor.
# It outputs a JSON formatted string that is expected by the
# spark.{driver/executor}.resource.gpu.discoveryScript config.
#
# Example output: {"name": "gpu", "addresses":["0","1","2","3","4","5","6","7"]}
ADDRS=`nvidia-smi --query-gpu=index --format=csv,noheader | sed -e ':a' -e 'N' -e'$!ba' -e 's/\n/","/g'`
echo {\"name\": \"gpu\", \"addresses\":[\"$ADDRS\"]}
| Shell | 4 | OlegPt/spark | examples/src/main/scripts/getGpusResources.sh | [
"Apache-2.0"
]
|
/*##############################################################################
HPCC SYSTEMS software Copyright (C) 2012 HPCC Systemsยฎ.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
############################################################################## */
//skip type==thorlcr TBD
//nothor
MyFixedRec := RECORD
STRING1 Value1;
STRING1 Value2;
END;
FixedFile := DATASET([{'C','G'},
{'C','C'},
{'A','X'},
{'B','G'},
{'A','B'}],MyFixedRec);
MyVarRec := RECORD
STRING1 Value1;
STRING Value2;
END;
VarFile := DATASET([{'C','G'},
{'C','C'},
{'A','X'},
{'B','G'},
{'A','B'}],MyVarRec);
dedup1 := DEDUP(VarFile, Value2, ALL, HASH);
dedup2 := DEDUP(FixedFile, Value2, ALL, HASH);
sequential(
output(dedup1),
output(dedup2)
);
| ECL | 3 | miguelvazq/HPCC-Platform | testing/regress/ecl/dedup_hash.ecl | [
"Apache-2.0"
]
|
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