text
stringlengths 992
1.04M
|
|---|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 1 14:05:15 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/bram/bram_stub.v
// Design : bram
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *)
module bram(clka, wea, addra, dina, clkb, addrb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[10:0],dina[15:0],clkb,addrb[10:0],doutb[15:0]" */;
input clka;
input [0:0]wea;
input [10:0]addra;
input [15:0]dina;
input clkb;
input [10:0]addrb;
output [15:0]doutb;
endmodule
|
/**
* $Id: bus_clk_bridge.v 961 2014-01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya system bus clock crossing bridge.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* Clock domain bridge for system bus.
*
*
* /------\
* SYSTEM | | PROCESSING
* BUS <-----> | SYNC | <-----> BUS
* | |
* \------/
*
*
* System bus runs on one clock domain while processing runs on separate. To
* simplify transition of writing and reading data this bridge was created.
*
*/
module bus_clk_bridge
(
// system bus
input sys_clk_i , //!< bus clock
input sys_rstn_i , //!< bus reset - active low
input [ 32-1: 0] sys_addr_i , //!< bus address
input [ 32-1: 0] sys_wdata_i , //!< bus write data
input [ 4-1: 0] sys_sel_i , //!< bus write byte select
input sys_wen_i , //!< bus write enable
input sys_ren_i , //!< bus read enable
output [ 32-1: 0] sys_rdata_o , //!< bus read data
output sys_err_o , //!< bus error indicator
output sys_ack_o , //!< bus acknowledge signal
// Destination bus
input clk_i , //!< clock
input rstn_i , //!< reset - active low
output reg [ 32-1: 0] addr_o , //!< address
output reg [ 32-1: 0] wdata_o , //!< write data
output wen_o , //!< write enable
output ren_o , //!< read enable
input [ 32-1: 0] rdata_i , //!< read data
input err_i , //!< error indicator
input ack_i //!< acknowledge signal
);
//---------------------------------------------------------------------------------
// Synchronize signals between clock domains
reg sys_rd ;
reg sys_wr ;
reg sys_do ;
reg [ 2-1: 0] sys_sync ;
reg sys_done ;
reg dst_do ;
reg [ 2-1: 0] dst_sync ;
reg dst_done ;
always @(posedge sys_clk_i) begin
if (sys_rstn_i == 1'b0) begin
sys_rd <= 1'b0 ;
sys_wr <= 1'b0 ;
sys_do <= 1'b0 ;
sys_sync <= 2'h0 ;
sys_done <= 1'b0 ;
end
else begin
if ((sys_do == sys_done) && (sys_wen_i || sys_ren_i)) begin
addr_o <= sys_addr_i ;
wdata_o <= sys_wdata_i ;
sys_rd <= sys_ren_i ;
sys_wr <= sys_wen_i ;
sys_do <= !sys_do ;
end
sys_sync <= {sys_sync[0], dst_done};
sys_done <= sys_sync[1];
end
end
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
dst_do <= 1'b0 ;
dst_sync <= 2'h0 ;
dst_done <= 1'b0 ;
end
else begin
dst_sync <= {dst_sync[0], sys_do};
dst_do <= dst_sync[1];
if (ack_i && (dst_do != dst_done))
dst_done <= dst_do;
end
end
assign ren_o = sys_rd && (dst_sync[1]^dst_do);
assign wen_o = sys_wr && (dst_sync[1]^dst_do);
assign sys_rdata_o = rdata_i ;
assign sys_err_o = err_i ;
assign sys_ack_o = sys_done ^ sys_sync[1] ;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
module shift_in (
data_in,
wr_en,
shift_en,
data_out,
clk,
rst
);
parameter WIDTH=1;
input [(64*WIDTH)-1:0] data_in;
input wr_en;
input shift_en;
output [(16*WIDTH)-1:0] data_out;
input clk;
input rst;
wire [(64*WIDTH)-1:0] reg_in;
wire [(64*WIDTH)-1:0] reg_out;
reg line_wr_en;
reg s_or_w_;
always @ (shift_en or wr_en)
begin
casex({shift_en,wr_en})
2'b00:
begin
line_wr_en <= 1'b0;
s_or_w_ <= 1'bx;
end
2'b01:
begin
line_wr_en <= 1'b1;
s_or_w_ <= 1'b0;
end
2'b10:
begin
line_wr_en <= 1'b1;
s_or_w_ <= 1'b1;
end
default:
begin
line_wr_en <= 1'bx;
s_or_w_ <= 1'bx;
end
endcase
end
register #(WIDTH*16) reg_line[3:0](.out(reg_out), .in(reg_in), .wr_en(line_wr_en), .clk(clk), .rst(rst));
mux_2_to_1 #(WIDTH*16) line3_mux(.out(reg_in[(WIDTH*64)-1:(WIDTH*48)]), .in({{WIDTH*16{1'bx}},data_in[(WIDTH*64)-1:(WIDTH*48)]}), .select(s_or_w_));
mux_2_to_1 #(WIDTH*16) line2_mux(.out(reg_in[(WIDTH*48)-1:(WIDTH*32)]), .in({reg_out[(WIDTH*64)-1:WIDTH*48],data_in[(WIDTH*48)-1:(WIDTH*32)]}), .select(s_or_w_));
mux_2_to_1 #(WIDTH*16) line1_mux(.out(reg_in[(WIDTH*32)-1:(WIDTH*16)]), .in({reg_out[(WIDTH*48)-1:WIDTH*32],data_in[(WIDTH*32)-1:(WIDTH*16)]}), .select(s_or_w_));
mux_2_to_1 #(WIDTH*16) line0_mux(.out(reg_in[(WIDTH*16)-1:0]), .in({reg_out[(WIDTH*32)-1:WIDTH*16],data_in[(WIDTH*16)-1:0]}), .select(s_or_w_));
assign data_out = reg_out[(WIDTH*16)-1:0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2011 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit bit_out;
output bit [30:0] vec_out;
output bit [123:0] wide_out;
output bit did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003-09-17 13:08:53 rherveille Exp $
//
// $Date: 2003-09-17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the
// time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//------------------------------------------------------------------------------
//-- (c) Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle.
//-- Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- _____| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------>
//--
//------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
// wasca_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [27:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [24:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
wasca_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port), // custom_instruction_master.readra
.reset_req (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O311A_4_V
`define SKY130_FD_SC_MS__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O311A_4_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
// $Id: testbench.v 1853 2010-03-24 03:06:21Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
module testbench
();
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
`include "parameters.v"
parameter Tclk = 4;
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width
= port_idx_width + ((num_resource_classes > 1) ? 1 : 0);
// total number of bits required for storing routing information
localparam route_info_width
= num_resource_classes * router_addr_width + node_addr_width;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// width of counter for remaining flits
localparam flit_ctr_width = clogb(max_payload_length);
// total number of bits required for storing header information
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(la_route_info_width + route_info_width) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(la_route_info_width + route_info_width + payload_length_width) :
-1;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flow control signals
localparam flow_ctrl_width = 1 + vc_idx_width;
// select set of feedback polynomials used for LFSRs
parameter lfsr_index = 0;
// number of bits in address that are considered base address
parameter cfg_node_addr_width = 10;
// width of register selector part of control register address
parameter cfg_reg_addr_width = 6;
// width of configuration bus addresses
localparam cfg_addr_width = cfg_node_addr_width + cfg_reg_addr_width;
// width of control register data
parameter cfg_data_width = 32;
// base address width for interface bus
localparam io_node_addr_width = cfg_node_addr_width;
// register index width for interface bus
localparam io_reg_addr_width = cfg_reg_addr_width;
// width of interface bus addresses
localparam io_addr_width = cfg_addr_width;
// width of interface bus datapath
localparam io_data_width = cfg_data_width;
// width of run cycle counter
parameter num_packets_width = 16;
// width of arrival rate LFSR
parameter arrival_rv_width = 16;
// width of message class selection LFSR
parameter mc_idx_rv_width = 4;
// width of resource class selection LFSR
parameter rc_idx_rv_width = 4;
// width of payload length selection LFSR
parameter plength_idx_rv_width = 4;
// number of selectable payload lengths
parameter num_plength_vals = 2;
// width of register that holds the number of outstanding packets
parameter packet_count_width = 8;
// number of bits in delay counter for acknowledgement (i.e., log2 of
// interval before acknowledgement is sent)
parameter done_delay_width = 4;
// number of node control signals to generate
parameter node_ctrl_width = 2;
// number of node status signals to accept
parameter node_status_width = 1;
// RNG seed value
parameter initial_seed = 0;
reg reset;
reg clk;
reg [0:io_node_addr_width-1] io_node_addr_base;
reg io_write;
reg io_read;
reg [0:cfg_addr_width-1] io_addr;
reg [0:cfg_data_width-1] io_write_data;
wire [0:cfg_data_width-1] io_read_data;
wire io_done;
wire error;
tc_router_wrap
#(.topology(topology),
.num_flit_buffers(num_flit_buffers),
.num_header_buffers(num_header_buffers),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.perf_ctr_enable(perf_ctr_enable),
.perf_ctr_width(perf_ctr_width),
.error_capture_mode(error_capture_mode),
.track_vcs_at_output(track_vcs_at_output),
.router_type(router_type),
.flit_data_width(flit_data_width),
.dim_order(dim_order),
.int_flow_ctrl_type(int_flow_ctrl_type),
.header_fifo_type(header_fifo_type),
.fbf_regfile_type(fbf_regfile_type),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.ctrl_crossbar_type(ctrl_crossbar_type),
.data_crossbar_type(data_crossbar_type),
.reset_type(reset_type),
.lfsr_index(lfsr_index),
.cfg_node_addr_width(cfg_node_addr_width),
.cfg_reg_addr_width(cfg_reg_addr_width),
.cfg_data_width(cfg_data_width),
.num_packets_width(num_packets_width),
.arrival_rv_width(arrival_rv_width),
.mc_idx_rv_width(mc_idx_rv_width),
.rc_idx_rv_width(rc_idx_rv_width),
.plength_idx_rv_width(plength_idx_rv_width),
.num_plength_vals(num_plength_vals),
.packet_count_width(packet_count_width))
dut
(.clk(clk),
.reset(reset),
.io_node_addr_base(io_node_addr_base),
.io_write(io_write),
.io_read(io_read),
.io_addr(io_addr),
.io_write_data(io_write_data),
.io_read_data(io_read_data),
.io_done(io_done),
.error(error));
reg clk_en;
always
begin
clk <= clk_en;
#(Tclk/2);
clk <= 1'b0;
#(Tclk/2);
end
always @(posedge clk)
begin
if(error)
begin
$display("error detected, cyc=%d", $time);
$stop;
end
end
reg done;
integer i, j;
integer seed = initial_seed;
initial
begin
reset = 1'b0;
clk_en = 1'b0;
io_node_addr_base = 'd0;
#(Tclk);
#(Tclk/4);
reset = 1'b1;
io_write = 1'b0;
io_read = 1'b0;
io_addr = 'b0;
io_write_data = 'b0;
done = 1'b0;
#(Tclk);
reset = 1'b0;
#(Tclk);
clk_en = 1'b1;
#(Tclk);
// disable reset (i.e., enable reset_b)
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 'd0;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
io_write_data[0] = 1'b1;
io_write_data[2] = 1'b1;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// enable clocks
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 'd0;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
io_write_data[0] = 1'b1;
io_write_data[1] = 1'b1;
io_write_data[2] = 1'b1;
io_write_data[3] = 1'b1;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set LFSR seeds
for(j = (num_ports - num_nodes_per_router); j < num_ports; j = j + 1)
begin
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + j;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd3;
for(i = 0; i < cfg_data_width; i = i + 1)
io_write_data[i] = $dist_uniform(seed, 0, 1);
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
end
// set number of packets
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd4;
io_write_data = 'd0;
io_write_data[0:num_packets_width-1] = 'd1024;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set arrival rate threshold
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd5;
io_write_data = 'd0;
io_write_data[0:arrival_rv_width-1] = 'd4096;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set packet length selection threshold
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd6;
io_write_data = 'd0;
io_write_data[0:plength_idx_rv_width-1] = 'd8;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set packet length values
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd7;
io_write_data = 'd0;
io_write_data[0:payload_length_width-1] = 'd0;
io_write_data[payload_length_width:2*payload_length_width-1] = 'd4;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set message class selection thresholds
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd8;
io_write_data = 'd0;
io_write_data[0:mc_idx_rv_width-1] = 'd10;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// set resource class selection thresholds
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd9;
io_write_data = 'd0;
io_write_data[0:rc_idx_rv_width-1] = 'd12;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(10*Tclk);
// start experiment
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
io_write_data[0] = 'd1;
io_write_data[1] = 'd0;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
// wait for experiment to finish
while(!done)
begin
#(10*Tclk);
io_read = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd1;
io_write_data = 'd0;
while(!io_done)
#(Tclk);
done = ~io_read_data[0];
#(Tclk);
io_read = 1'b0;
while(io_done)
#(Tclk);
end
done = 1'b0;
#(Tclk);
// disable nodes
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// disable router clocks
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 'd0;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
io_write_data[0] = 1'b1;
io_write_data[1] = 1'b1;
io_write_data[2] = 1'b1;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(Tclk);
// reset number of packets
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd4;
io_write_data = 'd0;
io_write_data[0:num_packets_width-1] = 'd1024;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(10*Tclk);
// restart experiment in loopback mode
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
io_write_data[0] = 'd1;
io_write_data[1] = 'd1;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
// wait for experiment to finish
while(!done)
begin
#(10*Tclk);
io_read = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd1;
io_write_data = 'd0;
while(!io_done)
#(Tclk);
done = ~io_read_data[0];
#(Tclk);
io_read = 1'b0;
while(io_done)
#(Tclk);
end
done = 1'b0;
#(Tclk);
// disable nodes
io_write = 1'b1;
io_addr[0:cfg_node_addr_width-1] = 1 + num_ports;
io_addr[cfg_node_addr_width:cfg_addr_width-1] = 'd0;
io_write_data = 'd0;
while(!io_done)
#(Tclk);
#(Tclk);
io_write = 1'b0;
while(io_done)
#(Tclk);
#(3*Tclk/4);
#(Tclk);
$finish;
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_4kx16_dc.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_4kx16_dc (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdusedw,
wrfull,
wrusedw);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output rdempty;
output [11:0] rdusedw;
output wrfull;
output [11:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4kx16_dc_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////////////
// File name : mt48lc4m16.v
//////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2008 Free Model Foundry; http://www.freemodelfoundry.com
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License version 2 as
// published by the Free Software Foundation.
//
// MODIFICATION HISTORY:
//
// version: | author: | mod date: | changes made:
// V1.0 S.Janevski 08 Feb 27 Initial release
// V1.1 S.Janevski 08 Mar 26 Assertions of wrong DQM settings during powerup removed
//////////////////////////////////////////////////////////////////////////////
// PART DESCRIPTION:
//
// Library: RAM
// Technology: LVTTL
// Part: mt48lc4m16
//
// Description: 1M x 16 x 4Banks SDRAM
//
//////////////////////////////////////////////////////////////////////////////
// Known Bugs:
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION //
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/100 ps
module mt48lc4m16
(
A11 ,
A10 ,
A9 ,
A8 ,
A7 ,
A6 ,
A5 ,
A4 ,
A3 ,
A2 ,
A1 ,
A0 ,
DQ15 ,
DQ14 ,
DQ13 ,
DQ12 ,
DQ11 ,
DQ10 ,
DQ9 ,
DQ8 ,
DQ7 ,
DQ6 ,
DQ5 ,
DQ4 ,
DQ3 ,
DQ2 ,
DQ1 ,
DQ0 ,
BA0 ,
BA1 ,
DQMH ,
DQML ,
CLK ,
CKE ,
WENeg ,
RASNeg ,
CSNeg ,
CASNeg );
////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations
////////////////////////////////////////////////////////////////////////
input A11 ;
input A10 ;
input A9 ;
input A8 ;
input A7 ;
input A6 ;
input A5 ;
input A4 ;
input A3 ;
input A2 ;
input A1 ;
input A0 ;
inout DQ15 ;
inout DQ14 ;
inout DQ13 ;
inout DQ12 ;
inout DQ11 ;
inout DQ10 ;
inout DQ9 ;
inout DQ8 ;
inout DQ7 ;
inout DQ6 ;
inout DQ5 ;
inout DQ4 ;
inout DQ3 ;
inout DQ2 ;
inout DQ1 ;
inout DQ0 ;
input BA0 ;
input BA1 ;
input DQMH ;
input DQML ;
input CLK ;
input CKE ;
input WENeg ;
input RASNeg ;
input CSNeg ;
input CASNeg ;
// interconnect path delay signals
wire A11_ipd ;
wire A10_ipd ;
wire A9_ipd ;
wire A8_ipd ;
wire A7_ipd ;
wire A6_ipd ;
wire A5_ipd ;
wire A4_ipd ;
wire A3_ipd ;
wire A2_ipd ;
wire A1_ipd ;
wire A0_ipd ;
wire [11 : 0] A;
assign A = {A11_ipd,
A10_ipd,
A9_ipd,
A8_ipd,
A7_ipd,
A6_ipd,
A5_ipd,
A4_ipd,
A3_ipd,
A2_ipd,
A1_ipd,
A0_ipd };
wire DQ15_ipd ;
wire DQ14_ipd ;
wire DQ13_ipd ;
wire DQ12_ipd ;
wire DQ11_ipd ;
wire DQ10_ipd ;
wire DQ9_ipd ;
wire DQ8_ipd ;
wire DQ7_ipd ;
wire DQ6_ipd ;
wire DQ5_ipd ;
wire DQ4_ipd ;
wire DQ3_ipd ;
wire DQ2_ipd ;
wire DQ1_ipd ;
wire DQ0_ipd ;
wire [15 : 0 ] DQIn;
assign DQIn = { DQ15_ipd,
DQ14_ipd,
DQ13_ipd,
DQ12_ipd,
DQ11_ipd,
DQ10_ipd,
DQ9_ipd,
DQ8_ipd,
DQ7_ipd,
DQ6_ipd,
DQ5_ipd,
DQ4_ipd,
DQ3_ipd,
DQ2_ipd,
DQ1_ipd,
DQ0_ipd };
wire [15 : 0] DQOut;
assign DQOut = { DQ15,
DQ14,
DQ13,
DQ12,
DQ11,
DQ10,
DQ9,
DQ8,
DQ7,
DQ6,
DQ5,
DQ4,
DQ3,
DQ2,
DQ1,
DQ0 };
wire BA0_ipd ;
wire BA1_ipd ;
wire DQM1_ipd ;
wire DQM0_ipd ;
wire CLK_ipd ;
wire CKE_ipd ;
wire WENeg_ipd ;
wire RASNeg_ipd ;
wire CSNeg_ipd ;
wire CASNeg_ipd ;
integer bank;
integer bank_tmp;
// internal delays
reg rct_in ;
reg rct_out;
reg [3:0] rcdt_in ;
reg [3:0] rcdt_out;
reg pre_in ;
reg pre_out ;
reg refreshed_in ;
reg refreshed_out ;
reg rcar_out ;
reg rcar_in ;
reg [3:0] ras_in = 1'b0;
reg [3:0] ras_out = 1'b0;
reg [15 : 0] DQ_zd = 16'bz;
assign {DQ15_zd,
DQ14_zd,
DQ13_zd,
DQ12_zd,
DQ11_zd,
DQ10_zd,
DQ9_zd,
DQ8_zd,
DQ7_zd,
DQ6_zd,
DQ5_zd,
DQ4_zd,
DQ3_zd,
DQ2_zd,
DQ1_zd,
DQ0_zd } = DQ_zd;
parameter UserPreload = 1'b1;
// parameter mem_file_name = "none"; //"mt48lc4m16.mem";
parameter mem_file_name = "mt48lc4m16.mem";
parameter TimingModel = "DefaultTimingModel";
parameter PartID = "mt48lc4m16";
parameter hi_bank = 3;
parameter depth = 25'h100000;
reg PoweredUp = 1'b0;
reg CKEreg = 1'b0;
reg CAS_Lat ;
reg CAS_Lat2;
reg [15:0] DataDrive = 16'bz ;
// Memory array declaration
integer Mem [0:(hi_bank+1)*depth*2-1];
// Type definition for state machine
parameter pwron = 5'd0;
parameter precharge = 5'd1;
parameter idle = 5'd2;
parameter mode_set = 5'd3;
parameter self_refresh = 5'd4;
parameter auto_refresh = 5'd5;
parameter pwrdwn = 5'd6;
parameter bank_act = 5'd7;
parameter bank_act_pwrdwn = 5'd8;
parameter write = 5'd9;
parameter write_suspend = 5'd10;
parameter read = 5'd11;
parameter read_suspend = 5'd12;
parameter write_auto_pre = 5'd13;
parameter read_auto_pre = 5'd14;
reg [4:0] statebank [hi_bank:0];
reg [4:0] debug_state;
// Type definition for commands
parameter desl = 4'd0;
parameter nop = 4'd1;
parameter bst = 4'd2;
parameter rd = 4'd3;
parameter writ = 4'd4;
parameter act = 4'd5;
parameter pre = 4'd6;
parameter mrs = 4'd7;
parameter ref = 4'd8;
reg [3:0] command = desl;
// burst type
parameter sequential = 1'b0;
parameter interleave = 1'b1;
reg Burst ;
// write burst mode
parameter programmed = 1'b0;
parameter single = 1'b1;
reg WB ;
//burst sequences
integer intab [0:63];
reg [19:0] MemAddr [hi_bank:0];
integer BurstCnt [hi_bank:0];
integer StartAddr [hi_bank:0];
integer BurstInc [hi_bank:0];
integer BaseLoc [hi_bank:0];
integer Loc;
integer BurstLen;
integer Burst_Bits;
reg written = 1'b0;
reg chip_en = 1'b0;
integer cur_bank;
reg [11:0] ModeReg ;
integer Ref_Cnt = 0;
time Next_Ref = 0;
reg [8*8:1] BankString ;
reg Viol = 1'b0;
reg [15:0] DataDriveOut = 16'bz;
reg [15:0] DataDrive1 = 16'bz;
reg [15:0] DataDrive2 = 16'bz;
reg [15:0] DataDrive3 = 16'bz;
reg DQM0_reg0 ;
reg DQM0_reg1 ;
reg DQM0_reg2 ;
reg DQM1_reg0 ;
reg DQM1_reg1 ;
reg DQM1_reg2 ;
// tdevice values: values for internal delays
parameter TRAS_VAL = 37;
parameter TRCD_VAL = 15;
time tdevice_TRASmin = 37;
time tdevice_TRASmax = 1200000;
time tdevice_TRC = 66;
time tdevice_TRCAR = 60;
time tdevice_TRCD = TRCD_VAL;
time tdevice_TRP = 15;
///////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////
buf (A11_ipd, A11);
buf (A10_ipd, A10);
buf (A9_ipd , A9 );
buf (A8_ipd , A8 );
buf (A7_ipd , A7 );
buf (A6_ipd , A6 );
buf (A5_ipd , A5 );
buf (A4_ipd , A4 );
buf (A3_ipd , A3 );
buf (A2_ipd , A2 );
buf (A1_ipd , A1 );
buf (A0_ipd , A0 );
buf (DQ15_ipd , DQ15 );
buf (DQ14_ipd , DQ14 );
buf (DQ13_ipd , DQ13 );
buf (DQ12_ipd , DQ12 );
buf (DQ11_ipd , DQ11 );
buf (DQ10_ipd , DQ10 );
buf (DQ9_ipd , DQ9 );
buf (DQ8_ipd , DQ8 );
buf (DQ7_ipd , DQ7 );
buf (DQ6_ipd , DQ6 );
buf (DQ5_ipd , DQ5 );
buf (DQ4_ipd , DQ4 );
buf (DQ3_ipd , DQ3 );
buf (DQ2_ipd , DQ2 );
buf (DQ1_ipd , DQ1 );
buf (DQ0_ipd , DQ0 );
buf (CASNeg_ipd, CASNeg);
buf (RASNeg_ipd, RASNeg);
buf (BA0_ipd , BA0 );
buf (BA1_ipd , BA1 );
buf (DQM0_ipd , DQML );
buf (DQM1_ipd , DQMH );
buf (CLK_ipd , CLK );
buf (CKE_ipd , CKE );
buf (WENeg_ipd , WENeg );
buf (CSNeg_ipd , CSNeg );
///////////////////////////////////////////////////////////////////////////
// Propagation delay Section
///////////////////////////////////////////////////////////////////////////
nmos (DQ15 , DQ15_zd , 1);
nmos (DQ14 , DQ14_zd , 1);
nmos (DQ13 , DQ13_zd , 1);
nmos (DQ12 , DQ12_zd , 1);
nmos (DQ11 , DQ11_zd , 1);
nmos (DQ10 , DQ10_zd , 1);
nmos (DQ9 , DQ9_zd , 1);
nmos (DQ8 , DQ8_zd , 1);
nmos (DQ7 , DQ7_zd , 1);
nmos (DQ6 , DQ6_zd , 1);
nmos (DQ5 , DQ5_zd , 1);
nmos (DQ4 , DQ4_zd , 1);
nmos (DQ3 , DQ3_zd , 1);
nmos (DQ2 , DQ2_zd , 1);
nmos (DQ1 , DQ1_zd , 1);
nmos (DQ0 , DQ0_zd , 1);
wire deg;
wire chip_act;
assign chip_act = chip_en;
wire chip_act_deg;
assign chip_act_deg = chip_act && deg;
wire cas_latency2;
wire cas_latency3;
assign cas_latency2 = ~CAS_Lat && CAS_Lat2;
assign cas_latency3 = CAS_Lat && CAS_Lat2;
specify
// tipd delays: interconnect path delays, mapped to input port delays.
// In Verilog it is not necessary to declare any tipd delay variables,
// they can be taken from SDF file
// With all the other delays real delays would be taken from SDF file
// tpd delays
specparam tpd_CLK_DQ0 = 1;
specparam tpd_CLK_DQ1 = 1;
// tpw values: pulse widths
specparam tpw_CLK_posedge = 1;
specparam tpw_CLK_negedge = 1;
// tsetup values: setup times
specparam tsetup_DQ0_CLK = 1; // tDS
// thold values: hold times
specparam thold_DQ0_CLK = 1; // tDH
// tperiod_min: minimum clock period = 1/max freq
specparam tperiod_CLK_cl1_eq_1_posedge = 1;
specparam tperiod_CLK_cl2_eq_1_posedge = 1;
// tdevice values: values for internal delays
specparam tdevice_REF = 15625 ;
///////////////////////////////////////////////////////////////////////
// Input Port Delays don't require Verilog description
///////////////////////////////////////////////////////////////////////
// Path delays //
///////////////////////////////////////////////////////////////////////
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ0) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ1) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ2) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ3) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ4) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ5) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ6) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ7) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ8) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ9) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ10) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ11) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ12) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ13) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ14) = tpd_CLK_DQ0;
if (~CAS_Lat && CAS_Lat2) (CLK *> DQ15) = tpd_CLK_DQ0;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ0) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ1) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ2) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ3) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ4) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ5) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ6) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ7) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ8) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ9) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ10) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ11) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ12) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ13) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ14) = tpd_CLK_DQ1;
if (CAS_Lat && CAS_Lat2) (CLK *> DQ15) = tpd_CLK_DQ1;
////////////////////////////////////////////////////////////////////////
// Timing Check Section
////////////////////////////////////////////////////////////////////////
$setup (BA0 , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (BA1 , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (DQML, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (DQMH, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (CKE , posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (WENeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (CSNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (CASNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (RASNeg, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (DQ0 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ1 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ2 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ3 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ4 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ5 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ6 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ7 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ8 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ9 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ10 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ11 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ12 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ13 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ14 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (DQ15 ,posedge CLK &&& chip_act_deg, tsetup_DQ0_CLK, Viol);
$setup (A0, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A1, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A2, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A3, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A4, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A5, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A6, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A7, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A8, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A9, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A10, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$setup (A11, posedge CLK &&& chip_act, tsetup_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, BA0, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, BA1, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, DQML, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, DQMH, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, CKE , thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, CASNeg, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, RASNeg, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, WENeg, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, CSNeg, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A0, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A1, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A2, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A3, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A4, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A5, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A6, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A7, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A8, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A9, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A10, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act, A11, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ0, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ1, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ2, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ3, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ4, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ5, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ6, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ7, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ8, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ9, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ10, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ11, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ12, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ13, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ14, thold_DQ0_CLK, Viol);
$hold (posedge CLK &&& chip_act_deg, DQ15, thold_DQ0_CLK, Viol);
$width (posedge CLK &&& chip_act, tpw_CLK_posedge);
$width (negedge CLK &&& chip_act, tpw_CLK_negedge);
$period (posedge CLK &&& cas_latency2, tperiod_CLK_cl1_eq_1_posedge);
$period (posedge CLK &&& cas_latency3, tperiod_CLK_cl2_eq_1_posedge);
endspecify
task generate_out ;
output [15:0] DataDrive;
input Bank;
integer Bank;
integer location;
begin
location = Bank * depth * 2 + Loc;
DataDrive[7:0] = 8'bx;
if (Mem[location] > -1)
DataDrive[7:0] = Mem[location];
DataDrive[15:8] = 8'bx;
if (Mem[location+1] > -1)
DataDrive[15:8] = Mem[location+1];
end
endtask
task MemWrite;
input Bank;
integer Bank;
integer location;
begin
location = Bank * depth * 2 + Loc;
if (~DQM0_ipd)
begin
Mem[location] = -1;
if (~Viol)
Mem[location] = DQIn[7:0];
end
if (~DQM1_ipd)
begin
Mem[location+1] = -1;
if (~Viol)
Mem[location+1] = DQIn[15:8];
end
end
endtask
task BurstIncProc;
input Bank;
integer Bank;
begin
BurstInc[Bank] = 0;
if (Burst_Bits == 1)
BurstInc[Bank] = A[0:0];
if (Burst_Bits == 2)
BurstInc[Bank] = A[1:0];
if (Burst_Bits == 3)
BurstInc[Bank] = A[2:0];
if (Burst_Bits == 7)
BurstInc[Bank] = A[6:0];
end
endtask
task NextStateAuto;
input Bank;
input state;
integer Bank;
reg [4:0] state;
begin
if (~A[10])
statebank[Bank] = state;
else if (A[10])
if (state == write)
statebank[Bank] = write_auto_pre;
else
statebank[Bank] = read_auto_pre;
end
endtask
//////////////////////////////////////////////////////////////////////////
// Main Behavior Block //
//////////////////////////////////////////////////////////////////////////
// chech when data is generated from model to avoid setup/hold check in
// those occasion
reg deq;
always @(DQIn, DQOut)
begin
if (DQIn==DQOut)
deq=1'b1;
else
deq=1'b0;
end
assign deg=deq;
// initialize burst sequences
initial
begin
intab[0] = 0;
intab[1] = 1;
intab[2] = 2;
intab[3] = 3;
intab[4] = 4;
intab[5] = 5;
intab[6] = 6;
intab[7] = 7;
intab[8] = 1;
intab[9] = 0;
intab[10] = 3;
intab[11] = 2;
intab[12] = 5;
intab[13] = 4;
intab[14] = 7;
intab[15] = 6;
intab[16] = 2;
intab[17] = 3;
intab[18] = 0;
intab[19] = 1;
intab[20] = 6;
intab[21] = 7;
intab[22] = 4;
intab[23] = 5;
intab[24] = 3;
intab[25] = 2;
intab[26] = 1;
intab[27] = 0;
intab[28] = 7;
intab[29] = 6;
intab[30] = 5;
intab[31] = 4;
intab[32] = 4;
intab[33] = 5;
intab[34] = 6;
intab[35] = 7;
intab[36] = 0;
intab[37] = 1;
intab[38] = 2;
intab[39] = 3;
intab[40] = 5;
intab[41] = 4;
intab[42] = 7;
intab[43] = 6;
intab[44] = 1;
intab[45] = 0;
intab[46] = 3;
intab[47] = 2;
intab[48] = 6;
intab[49] = 7;
intab[50] = 4;
intab[51] = 5;
intab[52] = 2;
intab[53] = 3;
intab[54] = 0;
intab[55] = 1;
intab[56] = 7;
intab[57] = 6;
intab[58] = 5;
intab[59] = 4;
intab[60] = 3;
intab[61] = 2;
intab[62] = 1;
intab[63] = 0;
end
// initialize memory and load preload files if any
initial
begin: InitMemory
integer i;
for (i=0; i<=((hi_bank+1)*depth*2 - 1); i=i+1)
begin
Mem[i] = -1;
end
// Memory preload file
// mt48lc4m16.mem file
// @bbbbbb - <bbbbbb> stands for address within memory,
// dd - <dd> is word to be written at Mem(bbbbbb++)
// (bbbbbb is incremented at every load)
if (UserPreload && !(mem_file_name == "none"))
$readmemh(mem_file_name,Mem);
end
//Power Up time 100 us;
initial
begin
PoweredUp = 1'b0;
statebank[0] = pwron;
statebank[1] = pwron;
statebank[2] = pwron;
statebank[3] = pwron;
$display ("Powering up! Time: %d", $time);
#100 PoweredUp = 1'b1;
$display ("Powerup Finished at %d", $time);
end
always @(posedge ras_in[0])
begin:TRASrise0
// $display ("ras in for bank 0 high, tdevice_TRASmin = %d", tdevice_TRASmin);
ras_out[0] <= #tdevice_TRASmin ras_in[0];
end
always @(negedge ras_in[0])
begin:TRASfall0
ras_out[0] <= #tdevice_TRASmax ras_in[0];
end
always @(posedge ras_in[1])
begin:TRASrise1
ras_out[1] <= #tdevice_TRASmin ras_in[1];
end
always @(negedge ras_in[1])
begin:TRASfall1
ras_out[1] <= #tdevice_TRASmax ras_in[1];
end
always @(posedge ras_in[2])
begin:TRASrise2
ras_out[2] <= #tdevice_TRASmin ras_in[2];
end
always @(negedge ras_in[2])
begin:TRASfall2
ras_out[2] <= #tdevice_TRASmax ras_in[2];
end
always @(posedge ras_in[3])
begin:TRASrise3
ras_out[3] <= #tdevice_TRASmin ras_in[3];
end
always @(negedge ras_in[3])
begin:TRASfall3
ras_out[3] <= #tdevice_TRASmax ras_in[3];
end
always @(posedge rcdt_in[0])
begin:TRCDrise0
// $display ("TRD went high");
rcdt_out[0] <= #5 1'b1;
end
always @(negedge rcdt_in[0])
begin:TRCDfall0
// $display ("TRD went low");
rcdt_out[0] <= #tdevice_TRCD 1'b0;
end
always @(posedge rcdt_in[1])
begin:TRCDrise1
rcdt_out[1] <= #5 1'b1;
end
always @(negedge rcdt_in[1])
begin:TRCDfall1
rcdt_out[1] <= #tdevice_TRCD 1'b0;
end
always @(posedge rcdt_in[2])
begin:TRCDrise2
rcdt_out[2] <= #5 1'b1;
end
always @(negedge rcdt_in[2])
begin:TRCDfall2
rcdt_out[2] <= #tdevice_TRCD 1'b0;
end
always @(posedge rcdt_in[3])
begin:TRCDrise3
rcdt_out[3] <= #5 1'b1;
end
always @(negedge rcdt_in[3])
begin:TRCDfall3
rcdt_out[3] <= #tdevice_TRCD 1'b0;
end
/////////////////////////////////////////////////////////////////////////
// Functional Section
/////////////////////////////////////////////////////////////////////////
always @(posedge CLK)
begin
if ($time > Next_Ref && PoweredUp && Ref_Cnt > 0)
begin
Ref_Cnt = Ref_Cnt - 1;
// Next_Ref = $time + tdevice_REF;
Next_Ref = $time + 15625;
end
if (CKEreg)
begin
if (~CSNeg_ipd)
chip_en = 1;
else
chip_en = 0;
end
if (CKEreg && ~CSNeg_ipd)
begin
if (WENeg_ipd == 1'bx)
$display(" Unusable value for WENeg ");
if (RASNeg_ipd == 1'bx)
$display(" Unusable value for RASNeg ");
if (CASNeg_ipd == 1'bx)
$display(" Unusable value for CASNeg ");
// Command Decode
if (RASNeg_ipd && CASNeg_ipd && WENeg_ipd)
command = nop;
else if (~RASNeg_ipd && CASNeg_ipd && WENeg_ipd)
command = act;
else if (RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd)
command = rd;
else if (RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd)
command = writ;
else if (RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd)
command = bst;
else if (~RASNeg_ipd && CASNeg_ipd && ~WENeg_ipd)
command = pre;
else if (~RASNeg_ipd && ~CASNeg_ipd && WENeg_ipd)
command = ref;
else if (~RASNeg_ipd && ~CASNeg_ipd && ~WENeg_ipd)
command = mrs;
// PowerUp Check
if (~(PoweredUp) && command != nop)
begin
$display (" Incorrect power up. Command %h issued before ", command);
$display (" power up complete. ");
end
// Bank Decode
if (~BA0_ipd && ~BA1_ipd)
cur_bank = 0;
else if (BA0_ipd && ~BA1_ipd)
cur_bank = 1;
else if (~BA0_ipd && BA1_ipd)
cur_bank = 2;
else if (BA0_ipd && BA1_ipd)
cur_bank = 3;
else
begin
$display ("Could not decode bank selection - results");
$display ("may be incorrect.");
end
end
// The Big State Machine
if (CKEreg)
begin
if (CSNeg_ipd == 1'bx)
$display ("Unusable value for CSNeg");
if (CSNeg_ipd)
command = nop;
// DQM pipeline
DQM0_reg2 = DQM0_reg1;
DQM0_reg1 = DQM0_reg0;
DQM0_reg0 = DQM0_ipd;
DQM1_reg2 = DQM1_reg1;
DQM1_reg1 = DQM1_reg0;
DQM1_reg0 = DQM1_ipd;
// by default data drive is Z, might get over written in one
// of the passes below
DataDrive = 16'bz;
debug_state <= statebank[0];
for (bank = 0; bank <= hi_bank; bank = bank + 1)
begin
case (statebank[bank])
pwron :
begin
if (~PoweredUp)
begin
if (command != nop)
$display ("Only NOPs allowed during power up.");
DataDrive = 16'bz;
end
else if (command == pre && (cur_bank == bank || A[10]))
begin
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
end
end
precharge :
begin
//$display ("\tRAM: Precharge");
if (cur_bank == bank)
// It is only an error if this bank is selected
if (command != nop && command != pre)
begin
$display ("Illegal command received ");
$display ("during precharge.",$time);
end
end
idle :
begin
if (command == nop || command == bst || command == pre
|| cur_bank != bank)
begin
end
else if (command == mrs)
begin
if (statebank[0] == idle && statebank[1] == idle &&
statebank[2] == idle && statebank[3] == idle)
begin
ModeReg = A;
statebank[bank] = mode_set;
end
end
else if (command == ref)
begin
if (statebank[0] == idle && statebank[1] == idle &&
statebank[2] == idle && statebank[3] == idle)
if (CKE)
begin
statebank[bank] = auto_refresh;
statebank[bank] <= #tdevice_TRCAR idle;
end
else
begin
statebank[0] = self_refresh;
statebank[1] = self_refresh;
statebank[2] = self_refresh;
statebank[3] = self_refresh;
end
end
else if (command == act)
begin
$display ("\tRAM: Activate Command Received");
statebank[bank] = bank_act;
ras_in[bank] = 1'b1;
ras_in [bank] <= #70 1'b0;
rct_in = 1'b1;
rct_in <= #1 1'b0;
rcdt_in[bank] = 1'b1;
rcdt_in[bank] <= #1 1'b0;
MemAddr[bank][19:8] = A; // latch row addr
end
else
$display ("Illegal command received in idle state.",$time);
end
mode_set :
begin
$display ("\tRAM: Setting mode to %h", ModeReg);
if (ModeReg[7] != 0 || ModeReg[8] != 0)
$display ("Illegal operating mode set.");
if (command != nop)
begin
$display ("Illegal command received during mode");
$display ("set.",$time);
end
// read burst length
if (ModeReg[2:0] == 3'b000)
begin
BurstLen = 1;
Burst_Bits = 0;
end
else if (ModeReg[2:0] == 3'b001)
begin
BurstLen = 2;
Burst_Bits = 1;
end
else if (ModeReg[2:0] == 3'b010)
begin
BurstLen = 4;
Burst_Bits = 2;
end
else if (ModeReg[2:0] == 3'b011)
begin
BurstLen = 8;
Burst_Bits = 3;
end
else if (ModeReg[2:0] == 3'b111)
begin
BurstLen = 256;
Burst_Bits = 7;
end
else
$display ("Invalid burst length specified.");
$display ("Burst Length set to %d", BurstLen);
// read burst type
if (~ModeReg[3]) begin
Burst = sequential;
$display ("Burst Type == Sequential");
end
else if (ModeReg[3])
Burst = interleave;
else
$display ("Invalid burst type specified.");
// read CAS latency
if (ModeReg[6:4] == 3'b010)
begin
CAS_Lat = 1'b0;
CAS_Lat2 = 1'b1;
end
else if (ModeReg[6:4] == 3'b011)
begin
CAS_Lat = 1'b1;
CAS_Lat2 = 1'b1;
end
else
$display ("CAS Latency set incorrecty");
// write burst mode
if (~ModeReg[9])
WB = programmed;
else if (ModeReg[9])
WB = single;
else
$display ("Invalid burst type specified.");
statebank[bank] = idle;
end
auto_refresh :
begin
//$display ("\tRAM: Auto Refresh Entered");
if (Ref_Cnt < 8192)
Ref_Cnt = Ref_Cnt + 1;
if (command != nop)
begin
//$display ("Illegal command received during autorefresh: %h", command);
//$display ("auto_refresh.",$time);
end
end
bank_act :
begin
$display ("\tRAM: Bank Activate");
if (command == pre && (cur_bank == bank || A[10]))
begin
if (~ras_out[bank])
begin
$display ("precharge command does not meet tRAS");
$display ("time", $time);
end
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
end
else if (command == nop || command == bst
|| cur_bank != bank)
begin
end
else if (command == rd)
begin
if (rcdt_out[bank])
begin
$display ("read command received too soon");
$display ("after active",$time);
$display ("rcdt_out[bank] == %d", rcdt_out[bank]);
end
if (A[10] == 1'bx)
begin
$display ("A(10) = X during read command.");
$display ("Next state unknown.");
end
MemAddr[bank][7:0] = 8'b0;// clr old addr
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
BurstIncProc(bank);
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
generate_out(DataDrive,bank);
BurstCnt[bank] = 1;
NextStateAuto(bank, read);
bank_tmp = bank;
end
else if (command == writ)
begin
if (rcdt_out[bank])
begin
$display ("write command received too soon");
$display ("after active",$time);
$display ("bank: %h", bank);
$display ("rcdt_out[bank] = %d", rcdt_out[bank]);
end
if (A[10] == 1'bx)
begin
$display ("A(10) = X during write command.");
$display ("Next state unknown.");
end
MemAddr[bank][7:0] = 8'b0; // clr old addr
BurstIncProc(bank);
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
MemWrite(bank);
BurstCnt[bank] = 1'b1;
NextStateAuto(bank, write);
written = 1'b1;
end
else if (cur_bank == bank || command == mrs)
begin
$display ("Illegal command received in");
$display ("active state",$time);
end
end
write :
begin
$display ("\tRAM: Write: %h", DQIn);
if (command == bst)
begin
statebank[bank] = bank_act;
BurstCnt[bank] = 1'b0;
end
else if (command == rd)
if (cur_bank == bank)
begin
MemAddr[bank][7:0] = 8'b0;// clr old addr
BurstIncProc(bank);
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
generate_out(DataDrive, bank);
BurstCnt[bank] = 1'b1;
NextStateAuto(bank, read);
end
else
statebank[bank] = bank_act;
else if (command == writ)
if (cur_bank == bank)
begin
MemAddr[bank][7:0] = 8'b0;// clr old addr
BurstIncProc(bank);
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
MemWrite(bank);
BurstCnt[bank] = 1'b1;
if (A[10])
statebank[bank] = write_auto_pre;
end
else
statebank[bank] = bank_act;
else if (command == pre && (cur_bank == bank || A[10]))
begin
if (~ras_out[bank])
begin
$display ("precharge command does not meet tRAS time",$time);
end
if (~DQM0_ipd)
begin
$display ("DQM0 should be held high, data is");
$display ("lost.",$time);
end
if (~DQM1_ipd)
begin
$display ("DQM1 should be held high, data is");
$display ("lost.",$time);
end
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
end
else if (command == nop || cur_bank != bank)
if (BurstCnt[bank] == BurstLen || WB == single)
begin
statebank[bank] = bank_act;
BurstCnt[bank] = 1'b0;
ras_in[bank] = 1'b1;
end
else
begin
if (Burst == sequential)
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
else
BurstInc[bank] =
intab[StartAddr[bank]*8 + BurstCnt[bank]];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
MemWrite(bank);
BurstCnt[bank] = BurstCnt[bank] + 1;
end
else if (cur_bank == bank)
$display ("Illegal command received in write state",$time);
end
read :
begin
$display ("\tRAM: Read");
if (command == bst)
begin
statebank[bank] = bank_act;
BurstCnt[bank] = 1'b0;
end
else if (command == rd)
if (cur_bank == bank)
begin
MemAddr[bank][7:0] = 8'b0;// clr old addr
BurstIncProc(bank);
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
generate_out(DataDrive, bank);
BurstCnt[bank] = 1'b1;
NextStateAuto(bank, read);
end
else
statebank[bank] = bank_act;
else if (command == writ)
if (cur_bank == bank)
begin
if (rcdt_out[bank])
begin
$display ("write command received too soon after active",$time);
$display ("Bank: %h", bank);
$display ("rcdt_out[bank]: %h", rcdt_out[bank]);
end
if (A[10] == 1'bx)
begin
$display ("A(10) = X during write command.");
$display ("Next state unknown.");
end
MemAddr[bank][7:0] = 8'b0;// clr old addr
BurstIncProc(bank);
// latch col addr
if (Burst_Bits == 0)
MemAddr[bank][7:0] = A[7:0];
if (Burst_Bits == 1)
MemAddr[bank][7:1] = A[7:1];
if (Burst_Bits == 2)
MemAddr[bank][7:2] = A[7:2];
if (Burst_Bits == 3)
MemAddr[bank][7:3] = A[7:3];
if (Burst_Bits == 7)
MemAddr[bank][7:7] = A[7:7];
StartAddr[bank] = BurstInc[bank] % 8;
BaseLoc[bank] = MemAddr[bank];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
MemWrite(bank);
BurstCnt[bank] = 1'b1;
NextStateAuto(bank,write);
end
else
statebank[bank] = bank_act;
else if (command == pre && (cur_bank == bank || A[10]))
begin
if (~ras_out[bank])
begin
$display ("Precharge command does not meet tRAS time",$time);
end
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
end
else if (command == nop || cur_bank != bank)
begin
if (BurstCnt[bank] == BurstLen)
begin
statebank[bank] = bank_act;
BurstCnt[bank] = 1'b0;
ras_in[bank] = 1'b1;
end
else
begin
if (Burst == sequential)
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
else
BurstInc[bank] =
intab[StartAddr[bank]*8 + BurstCnt[bank]];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
generate_out(DataDrive, bank);
BurstCnt[bank] = BurstCnt[bank] + 1;
end
end
else if (cur_bank == bank)
$display ("Illegal command received in read state",$time);
end
write_auto_pre :
begin
$display ("\tRAM: Write with auto precharge");
if (command == nop || cur_bank != bank)
if (BurstCnt[bank] == BurstLen || WB == single)
begin
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
BurstCnt[bank] = 1'b0;
ras_in[bank] = 1'b1;
end
else
begin
if (Burst == sequential)
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
else
BurstInc[bank] =
intab[StartAddr[bank]*8 + BurstCnt[bank]];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
MemWrite(bank);
BurstCnt[bank] = BurstCnt[bank] + 1;
end
else
$display ("Illegal command received in write state.",$time);
end
read_auto_pre :
begin
$display ("\tRAM: Read with auto precharge");
if (command == nop || (cur_bank != bank && command != rd
&& command != writ))
if (BurstCnt[bank] == BurstLen)
begin
$display ("\tRAM: Read W/ SP Continue Reading");
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
BurstCnt[bank] = 1'b0;
ras_in[bank] = 1'b1;
end
else
begin
$display ("\tRAM: Read W/ AP Start Reading");
if (Burst == sequential)
BurstInc[bank] = (BurstInc[bank]+1) % BurstLen;
else
BurstInc[bank] =
intab[StartAddr[bank]*8 + BurstCnt[bank]];
Loc = 2*(BaseLoc[bank] + BurstInc[bank]);
generate_out(DataDrive, bank);
BurstCnt[bank] = BurstCnt[bank] + 1;
end
else if ((command == rd || command == writ) && cur_bank
!= bank)
begin
$display ("\tRAM: Case 3");
statebank[bank] = precharge;
statebank[bank] <= #tdevice_TRP idle;
end
else
$display ("Illegal command received in read state",$time);
end
endcase
end
// Check Refresh Status
if (written && (Ref_Cnt == 0))
$display ("memory not refreshed (by ref_cnt)", $time);
DataDrive3 = DataDrive2;
DataDrive2 = DataDrive1;
DataDrive1 = DataDrive;
end
// Latency adjustments and DQM read masking
if (~DQM0_reg1)
if (CAS_Lat && CAS_Lat2)
DataDriveOut[7:0] = DataDrive3[7:0];
else
DataDriveOut[7:0] = DataDrive2[7:0];
else
DataDriveOut[7:0] = 8'bz;
if (~DQM1_reg1)
if (CAS_Lat && CAS_Lat2)
DataDriveOut[15:8] = DataDrive3[15:8];
else
DataDriveOut[15:8] = DataDrive2[15:8];
else
DataDriveOut[15:8] = 8'bz;
// The Powering-up State Machine
if (~CKEreg && CKE_ipd)
begin
if (CSNeg_ipd == 1'bx)
$display ("Unusable value for CSNeg");
if (CSNeg_ipd)
command = nop;
case (statebank[cur_bank])
write_suspend :
begin
statebank[cur_bank] = write;
end
read_suspend :
begin
statebank[cur_bank] = read;
end
self_refresh :
begin
statebank[0] <= #tdevice_TRP idle;
statebank[1] <= #tdevice_TRP idle;
statebank[2] <= #tdevice_TRP idle;
statebank[3] <= #tdevice_TRP idle;
Ref_Cnt = 8192;
if (command != nop)
begin
$display ("Illegal command received during self");
$display ("refresh",$time);
end
end
pwrdwn :
begin
statebank[0] = idle;
statebank[1] = idle;
statebank[2] = idle;
statebank[3] = idle;
end
bank_act_pwrdwn :
begin
statebank[cur_bank] = bank_act;
end
endcase
end
// The Powering-down State Machine
if (CKEreg && ~CKE_ipd)
begin
if (CSNeg_ipd == 1'bx)
$display ("Unusable value for CSNeg");
if (CSNeg_ipd)
command = nop;
case (statebank[cur_bank])
idle :
begin
if (command == nop)
begin
statebank[0] = pwrdwn;
statebank[1] = pwrdwn;
statebank[2] = pwrdwn;
statebank[3] = pwrdwn;
end
end
write :
begin
statebank[cur_bank] = write_suspend;
end
read :
begin
statebank[cur_bank] = read_suspend;
end
bank_act :
begin
statebank[cur_bank] = bank_act_pwrdwn;
end
endcase
end
CKEreg = CKE_ipd;
end
always @(DataDriveOut)
begin
DQ_zd = DataDriveOut;
end
reg TRASMIN_In, TRASMAX_In, TRC_In , TRCAR_In;
reg TRCD_In , TRP_In , TWR_In;
wire TRASMIN_Out,TRASMAX_Out,TRC_Out,TRCAR_Out, TRCD_Out, TRP_Out, TWR_Out;
BUFFER BUF_TRASMIN (TRASMIN_Out , TRASMIN_In);
BUFFER BUF_TRASMAX (TRASMAX_Out , TRASMAX_In);
BUFFER BUF_TRC (TRC_Out , TRC_In);
BUFFER BUF_TRCAR (TRCAR_Out, TRCAR_In);
BUFFER BUF_TRCD (TRCD_Out , TRCD_In);
BUFFER BUF_TRP (TRP_Out , TRP_In);
initial
begin
TRASMIN_In = 1;
TRASMAX_In = 1;
TRC_In = 1;
TRCAR_In = 1;
TRCD_In = 1'b1;
TRP_In = 1;
TWR_In = 1;
end
/*
always @(posedge TRC_Out)
begin
tdevice_TRC = $time;
end
always @(posedge TRASMIN_Out)
begin
tdevice_TRASmin = $time;
end
always @(posedge TRASMAX_Out)
begin
tdevice_TRASmax = $time;
end
always @(posedge TRCAR_Out)
begin
tdevice_TRCAR = $time;
end
always @(posedge TRCD_Out)
begin
tdevice_TRCD = $time;
end
always @(posedge TRP_Out)
begin
tdevice_TRP = $time;
end
*/
endmodule
module BUFFER (OUT,IN);
input IN;
output OUT;
buf (OUT, IN);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_Loop_1_proc_line_buffer_0_0_val_ram (addr0, ce0, q0, addr1, ce1, d1, we1, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1921;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
end
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_Loop_1_proc_line_buffer_0_0_val(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd1921;
parameter AddressWidth = 32'd11;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
image_filter_Loop_1_proc_line_buffer_0_0_val_ram image_filter_Loop_1_proc_line_buffer_0_0_val_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ));
endmodule
|
`timescale 1ns / 1ps
// KCP53002 Furcula to Wishbone bus bridge
//
// Note that Furcula is, in reality, a slight modification of Wishbone.
// Since these two interconnects share so many signals in common, the
// interface to the bridge is kept very small.
module bridge(
// FURCULA BUS
input f_signed_i,
input [1:0] f_siz_i,
input [2:0] f_adr_i,
input [63:0] f_dat_i,
output [63:0] f_dat_o,
// WISHBONE BUS
output [7:0] wb_sel_o,
output [63:0] wb_dat_o,
input [63:0] wb_dat_i
);
// Wishbone SEL_O signal generation.
wire size_byte = (f_siz_i == 2'b00);
wire size_hword = (f_siz_i == 2'b01);
wire size_word = (f_siz_i == 2'b10);
wire size_dword = (f_siz_i == 2'b11);
wire ab7 = f_adr_i[2:0] == 3'b111;
wire ab6 = f_adr_i[2:0] == 3'b110;
wire ab5 = f_adr_i[2:0] == 3'b101;
wire ab4 = f_adr_i[2:0] == 3'b100;
wire ab3 = f_adr_i[2:0] == 3'b011;
wire ab2 = f_adr_i[2:0] == 3'b010;
wire ab1 = f_adr_i[2:0] == 3'b001;
wire ab0 = f_adr_i[2:0] == 3'b000;
wire ah3 = f_adr_i[2:1] == 2'b11;
wire ah2 = f_adr_i[2:1] == 2'b10;
wire ah1 = f_adr_i[2:1] == 2'b01;
wire ah0 = f_adr_i[2:1] == 2'b00;
wire aw1 = f_adr_i[2] == 1'b1;
wire aw0 = f_adr_i[2] == 1'b0;
wire den = size_dword;
wire wen1 = size_word & aw1;
wire wen0 = size_word & aw0;
wire hen3 = size_hword & ah3;
wire hen2 = size_hword & ah2;
wire hen1 = size_hword & ah1;
wire hen0 = size_hword & ah0;
wire ben7 = size_byte & ab7;
wire ben6 = size_byte & ab6;
wire ben5 = size_byte & ab5;
wire ben4 = size_byte & ab4;
wire ben3 = size_byte & ab3;
wire ben2 = size_byte & ab2;
wire ben1 = size_byte & ab1;
wire ben0 = size_byte & ab0;
wire sel7 = den | wen1 | hen3 | ben7;
wire sel6 = den | wen1 | hen3 | ben6;
wire sel5 = den | wen1 | hen2 | ben5;
wire sel4 = den | wen1 | hen2 | ben4;
wire sel3 = den | wen0 | hen1 | ben3;
wire sel2 = den | wen0 | hen1 | ben2;
wire sel1 = den | wen0 | hen0 | ben1;
wire sel0 = den | wen0 | hen0 | ben0;
assign wb_sel_o = {sel7, sel6, sel5, sel4, sel3, sel2, sel1, sel0};
// Furcula-to-Wishbone Data Routing
wire [7:0] od7 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[63:56] : 0);
wire [7:0] od6 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[55:48] : 0);
wire [7:0] od5 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[47:40] : 0);
wire [7:0] od4 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[7:0] : 0) |
(size_dword ? f_dat_i[39:32] : 0);
wire [7:0] od3 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[31:24] : 0) |
(size_dword ? f_dat_i[31:24] : 0);
wire [7:0] od2 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[7:0] : 0) |
(size_word ? f_dat_i[23:16] : 0) |
(size_dword ? f_dat_i[23:16] : 0);
wire [7:0] od1 =
(size_byte ? f_dat_i[7:0] : 0) |
(size_hword ? f_dat_i[15:8] : 0) |
(size_word ? f_dat_i[15:8] : 0) |
(size_dword ? f_dat_i[15:8] : 0);
wire [7:0] od0 = f_dat_i[7:0];
assign wb_dat_o = {od7, od6, od5, od4, od3, od2, od1, od0};
// Wishbone to Furcula Data Routing
wire [31:0] id2 =
(wen1 ? wb_dat_i[63:32] : 0) |
(wen0 ? wb_dat_i[31:0] : 0);
wire [15:0] id1 =
(hen3 ? wb_dat_i[63:48] : 0) |
(hen2 ? wb_dat_i[47:32] : 0) |
(hen1 ? wb_dat_i[31:16] : 0) |
(hen0 ? wb_dat_i[15:0] : 0);
wire [7:0] id0 =
(ben7 ? wb_dat_i[63:56] : 0) |
(ben6 ? wb_dat_i[55:48] : 0) |
(ben5 ? wb_dat_i[47:40] : 0) |
(ben4 ? wb_dat_i[39:32] : 0) |
(ben3 ? wb_dat_i[31:24] : 0) |
(ben2 ? wb_dat_i[23:16] : 0) |
(ben1 ? wb_dat_i[15:8] : 0) |
(ben0 ? wb_dat_i[7:0] : 0);
wire [63:32] id2s = (f_signed_i ? {32{id2[31]}} : 32'd0);
wire [63:16] id1s = (f_signed_i ? {48{id1[15]}} : 48'd0);
wire [63:8] id0s = (f_signed_i ? {56{id0[7]}} : 56'd0);
assign f_dat_o =
(size_dword ? wb_dat_i : 0) |
(size_word ? {id2s, id2} : 0) |
(size_hword ? {id1s, id1} : 0) |
(size_byte ? {id0s, id0} : 0);
endmodule
|
/*
File: eproto_tx.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
/*
########################################################################
EPIPHANY eLink TX Protocol block
########################################################################
This block takes standard eMesh protocol (104-bit transactions) and
encodes the bytes into 8-byte parallel outputs for the output
serializers.
*/
module eproto_tx (/*AUTOARG*/
// Outputs
emtx_rd_wait, emtx_wr_wait, emtx_ack, txframe_p, txdata_p,
// Inputs
reset, emtx_access, emtx_write, emtx_datamode, emtx_ctrlmode,
emtx_dstaddr, emtx_srcaddr, emtx_data, txlclk_p, tx_rd_wait,
tx_wr_wait
);
// System reset input
input reset;
// Input from TX Arbiter
input emtx_access;
input emtx_write;
input [1:0] emtx_datamode;
input [3:0] emtx_ctrlmode;
input [31:0] emtx_dstaddr;
input [31:0] emtx_srcaddr;
input [31:0] emtx_data;
output emtx_rd_wait;
output emtx_wr_wait;
output emtx_ack;
// Parallel interface, 8 eLink bytes at a time
input txlclk_p; // Parallel-rate clock from eClock block
output [7:0] txframe_p;
output [63:0] txdata_p;
input tx_rd_wait; // The wait signals are passed through
input tx_wr_wait; // to the emesh interfaces
//#############
//# Configuration bits
//#############
//############
//# Local regs & wires
//############
reg emtx_ack; // Acknowledge transaction
reg [7:0] txframe_p;
reg [63:0] txdata_p;
//############
//# Logic
//############
// TODO: Bursts
always @( posedge txlclk_p or posedge reset ) begin
if( reset ) begin
emtx_ack <= 1'b0;
txframe_p <= 'd0;
txdata_p <= 'd0;
end else begin
if( emtx_access & ~emtx_ack ) begin
emtx_ack <= 1'b1;
txframe_p <= 8'h3F;
txdata_p <=
{ 8'd0, // Not used
8'd0,
~emtx_write, 7'd0, // B0- TODO: For bursts, add the inc bit
emtx_ctrlmode, emtx_dstaddr[31:28], // B1
emtx_dstaddr[27:4], // B2, B3, B4
emtx_dstaddr[3:0], emtx_datamode, emtx_write, emtx_access // B5
};
end else if( emtx_ack ) begin // if ( emtx_access & ~emtx_ack )
emtx_ack <= 1'b0;
txframe_p <= 8'hFF;
txdata_p <= { emtx_data, emtx_srcaddr };
end else begin
emtx_ack <= 1'b0;
txframe_p <= 8'h00;
txdata_p <= 64'd0;
end
end // else: !if( reset )
end // always @ ( posedge txlclk_p or reset )
//#############################
//# Wait signals
//#############################
reg rd_wait_sync;
reg wr_wait_sync;
reg emtx_rd_wait;
reg emtx_wr_wait;
always @( posedge txlclk_p ) begin
rd_wait_sync <= tx_rd_wait;
emtx_rd_wait <= rd_wait_sync;
wr_wait_sync <= tx_wr_wait;
emtx_wr_wait <= wr_wait_sync;
end
endmodule // eproto_tx
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:40:38 05/31/2011
// Design Name: main
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/main_tf.v
// Project Name: sd2snes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module main_tf;
// Inputs
reg CLKIN;
reg [23:0] SNES_ADDR;
reg SNES_READ;
reg SNES_WRITE;
reg SNES_CS;
reg SNES_CPU_CLK;
reg SNES_REFRESH;
reg SNES_SYSCLK;
reg SPI_MOSI;
reg SPI_SS;
reg MCU_OVR;
reg [3:0] SD_DAT;
// Outputs
wire SNES_DATABUS_OE;
wire SNES_DATABUS_DIR;
wire IRQ_DIR;
wire [22:0] ROM_ADDR;
wire ROM_CE;
wire ROM_OE;
wire ROM_WE;
wire ROM_BHE;
wire ROM_BLE;
wire [18:0] RAM_ADDR;
wire RAM_CE;
wire RAM_OE;
wire RAM_WE;
wire DAC_MCLK;
wire DAC_LRCK;
wire DAC_SDOUT;
// Bidirs
wire [7:0] SNES_DATA;
wire SNES_IRQ;
wire [15:0] ROM_DATA;
wire [7:0] RAM_DATA;
wire SPI_MISO;
wire SPI_SCK;
wire SD_CMD;
wire SD_CLK;
// Instantiate the Unit Under Test (UUT)
main uut (
.CLKIN(CLKIN),
.SNES_ADDR(SNES_ADDR),
.SNES_READ(SNES_READ),
.SNES_WRITE(SNES_WRITE),
.SNES_CS(SNES_CS),
.SNES_DATA(SNES_DATA),
.SNES_CPU_CLK(SNES_CPU_CLK),
.SNES_REFRESH(SNES_REFRESH),
.SNES_IRQ(SNES_IRQ),
.SNES_DATABUS_OE(SNES_DATABUS_OE),
.SNES_DATABUS_DIR(SNES_DATABUS_DIR),
.IRQ_DIR(IRQ_DIR),
.SNES_SYSCLK(SNES_SYSCLK),
.ROM_DATA(ROM_DATA),
.ROM_ADDR(ROM_ADDR),
.ROM_CE(ROM_CE),
.ROM_OE(ROM_OE),
.ROM_WE(ROM_WE),
.ROM_BHE(ROM_BHE),
.ROM_BLE(ROM_BLE),
.RAM_DATA(RAM_DATA),
.RAM_ADDR(RAM_ADDR),
.RAM_CE(RAM_CE),
.RAM_OE(RAM_OE),
.RAM_WE(RAM_WE),
.SPI_MOSI(SPI_MOSI),
.SPI_MISO(SPI_MISO),
.SPI_SS(SPI_SS),
.SPI_SCK(SPI_SCK),
.MCU_OVR(MCU_OVR),
.DAC_MCLK(DAC_MCLK),
.DAC_LRCK(DAC_LRCK),
.DAC_SDOUT(DAC_SDOUT),
.SD_DAT(SD_DAT),
.SD_CMD(SD_CMD),
.SD_CLK(SD_CLK)
);
integer i;
reg [7:0] SNES_DATA_OUT;
reg [7:0] SNES_DATA_IN;
assign SNES_DATA = (!SNES_READ) ? 8'bZ : SNES_DATA_IN;
initial begin
// Initialize Inputs
CLKIN = 0;
SNES_ADDR = 0;
SNES_READ = 1;
SNES_WRITE = 1;
SNES_CS = 0;
SNES_CPU_CLK = 0;
SNES_REFRESH = 0;
SNES_SYSCLK = 0;
SPI_MOSI = 0;
SPI_SS = 0;
MCU_OVR = 1;
SD_DAT = 0;
// Wait 100 ns for global reset to finish
#500;
// Add stimulus here
SNES_ADDR = 24'h208000;
SNES_DATA_IN = 8'h1f;
SNES_WRITE = 0;
#100 SNES_WRITE = 1;
#100;
for (i = 0; i < 4096; i = i + 1) begin
#140 SNES_READ = 0;
SNES_CPU_CLK = 1;
#140 SNES_READ = 1;
SNES_CPU_CLK = 0;
end
end
always #24 CLKIN = ~CLKIN;
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_BLACKBOX_V
`define SKY130_FD_SC_LP__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Up-Sizer
// Up-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data and Read Data Up-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Up-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_axi_upsizer #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// parameter integer C_FIFO_MODE = 0,
parameter integer C_FIFO_MODE = 1,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface
input wire s_axi_aresetn,
input wire s_axi_aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface
input wire m_axi_aresetn,
input wire m_axi_aclk,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
localparam integer P_CONV_LIGHT_WT = 0;
localparam integer P_AXI4 = 0;
localparam integer C_FIFO_DEPTH_LOG = 5;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NO_FIFO = 0;
localparam integer P_PKTFIFO = 1;
localparam integer P_PKTFIFO_CLK = 2;
localparam integer P_DATAFIFO = 3;
localparam integer P_DATAFIFO_CLK = 4;
localparam P_CLK_CONV = ((C_FIFO_MODE == P_PKTFIFO_CLK) || (C_FIFO_MODE == P_DATAFIFO_CLK));
localparam integer C_M_AXI_AW_REGISTER = 0;
// Simple register AW output.
// Range: 0, 1
localparam integer C_M_AXI_W_REGISTER = 1; // Parameter not used; W reg always implemented.
localparam integer C_M_AXI_AR_REGISTER = 0;
// Simple register AR output.
// Range: 0, 1
localparam integer C_S_AXI_R_REGISTER = 0;
// Simple register R output (SI).
// Range: 0, 1
localparam integer C_M_AXI_R_REGISTER = 1;
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
localparam integer P_RID_QUEUE = ((C_SUPPORTS_ID != 0) && !((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK))) ? 1 : 0;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire aclk;
wire m_aclk;
wire sample_cycle;
wire sample_cycle_early;
wire sm_aresetn;
wire s_aresetn_i;
wire [C_S_AXI_ID_WIDTH-1:0] sr_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_awaddr ;
wire [8-1:0] sr_awlen ;
wire [3-1:0] sr_awsize ;
wire [2-1:0] sr_awburst ;
wire [2-1:0] sr_awlock ;
wire [4-1:0] sr_awcache ;
wire [3-1:0] sr_awprot ;
wire [4-1:0] sr_awregion ;
wire [4-1:0] sr_awqos ;
wire sr_awvalid ;
wire sr_awready ;
wire [C_S_AXI_ID_WIDTH-1:0] sr_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_araddr ;
wire [8-1:0] sr_arlen ;
wire [3-1:0] sr_arsize ;
wire [2-1:0] sr_arburst ;
wire [2-1:0] sr_arlock ;
wire [4-1:0] sr_arcache ;
wire [3-1:0] sr_arprot ;
wire [4-1:0] sr_arregion ;
wire [4-1:0] sr_arqos ;
wire sr_arvalid ;
wire sr_arready ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_wdata ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_wstrb ;
wire sr_wlast ;
wire sr_wvalid ;
wire sr_wready ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_rdata ;
wire [2-1:0] mr_rresp ;
wire mr_rlast ;
wire mr_rvalid ;
wire mr_rready ;
wire m_axi_rready_i;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_ii ;
wire [3:0] s_axi_awregion_ii;
wire [3:0] s_axi_arregion_ii;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen : s_axi_awlen[3:0];
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlock[0] : s_axi_awlock;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen : s_axi_arlen[3:0];
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlock[0] : s_axi_arlock;
assign sr_awlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen_ii: {4'b0, s_axi_awlen_ii};
assign sr_awlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_awlock_ii} : s_axi_awlock_ii;
assign sr_arlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen_ii: {4'b0, s_axi_arlen_ii};
assign sr_arlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_arlock_ii} : s_axi_arlock_ii;
assign sr_awregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awregion_ii : 4'b0;
assign sr_arregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arregion_ii : 4'b0;
assign aclk = s_axi_aclk;
assign sm_aresetn = s_axi_aresetn & m_axi_aresetn;
generate
if (P_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end else begin : gen_sync_conv
wire fast_aclk;
wire slow_aclk;
reg s_aresetn_r;
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = m_axi_aclk;
assign slow_aclk = s_axi_aclk;
end else begin : gen_fastclk_si
assign fast_aclk = s_axi_aclk;
assign slow_aclk = m_axi_aclk;
end
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_aresetn_r;
always @(negedge sm_aresetn, posedge fast_aclk) begin
if (~sm_aresetn) begin
s_aresetn_r <= 1'b0;
end else if (s_axi_aresetn & m_axi_aresetn & sample_cycle_early) begin
s_aresetn_r <= 1'b1;
end
end
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
end
end else begin : gen_no_clk_conv
assign m_aclk = s_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end // gen_clock_conv
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (aclk),
.s_axi_awid (s_axi_awid ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awlen (s_axi_awlen_i ),
.s_axi_awsize (s_axi_awsize ),
.s_axi_awburst (s_axi_awburst ),
.s_axi_awlock (s_axi_awlock_i ),
.s_axi_awcache (s_axi_awcache ),
.s_axi_awprot (s_axi_awprot ),
.s_axi_awregion (s_axi_awregion ),
.s_axi_awqos (s_axi_awqos ),
.s_axi_awuser (1'b0 ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid (s_axi_arid ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arlen (s_axi_arlen_i ),
.s_axi_arsize (s_axi_arsize ),
.s_axi_arburst (s_axi_arburst ),
.s_axi_arlock (s_axi_arlock_i ),
.s_axi_arcache (s_axi_arcache ),
.s_axi_arprot (s_axi_arprot ),
.s_axi_arregion (s_axi_arregion ),
.s_axi_arqos (s_axi_arqos ),
.s_axi_aruser (1'b0 ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rid ( ) ,
.s_axi_rdata ( ) ,
.s_axi_rresp ( ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( ) ,
.s_axi_rready ( 1'b0 ) ,
.m_axi_awid (sr_awid ),
.m_axi_awaddr (sr_awaddr ),
.m_axi_awlen (s_axi_awlen_ii),
.m_axi_awsize (sr_awsize ),
.m_axi_awburst (sr_awburst ),
.m_axi_awlock (s_axi_awlock_ii),
.m_axi_awcache (sr_awcache ),
.m_axi_awprot (sr_awprot ),
.m_axi_awregion (s_axi_awregion_ii ),
.m_axi_awqos (sr_awqos ),
.m_axi_awuser (),
.m_axi_awvalid (sr_awvalid ),
.m_axi_awready (sr_awready ),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (sr_arid ),
.m_axi_araddr (sr_araddr ),
.m_axi_arlen (s_axi_arlen_ii),
.m_axi_arsize (sr_arsize ),
.m_axi_arburst (sr_arburst ),
.m_axi_arlock (s_axi_arlock_ii),
.m_axi_arcache (sr_arcache ),
.m_axi_arprot (sr_arprot ),
.m_axi_arregion (s_axi_arregion_ii ),
.m_axi_arqos (sr_arqos ),
.m_axi_aruser (),
.m_axi_arvalid (sr_arvalid ),
.m_axi_arready (sr_arready ),
.m_axi_rid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.m_axi_rresp ( 2'b00 ),
.m_axi_rlast ( 1'b0 ),
.m_axi_ruser ( 1'b0 ),
.m_axi_rvalid ( 1'b0 ),
.m_axi_rready ( )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i ;
wire [8-1:0] m_axi_awlen_i ;
wire [3-1:0] m_axi_awsize_i ;
wire [2-1:0] m_axi_awburst_i ;
wire [2-1:0] m_axi_awlock_i ;
wire [4-1:0] m_axi_awcache_i ;
wire [3-1:0] m_axi_awprot_i ;
wire [4-1:0] m_axi_awregion_i ;
wire [4-1:0] m_axi_awqos_i ;
wire m_axi_awvalid_i ;
wire m_axi_awready_i ;
wire s_axi_bvalid_i ;
wire [2-1:0] s_axi_bresp_i ;
wire [C_AXI_ADDR_WIDTH-1:0] wr_cmd_si_addr;
wire [8-1:0] wr_cmd_si_len;
wire [3-1:0] wr_cmd_si_size;
wire [2-1:0] wr_cmd_si_burst;
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_id_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire wpush;
wire wpop;
reg [C_FIFO_DEPTH_LOG-1:0] wcnt;
// Write Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (C_SUPPORTS_ID),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
.cmd_id (wr_cmd_id),
.cmd_id_ready (wr_cmd_id_ready),
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_id (),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_awid),
.S_AXI_AADDR (sr_awaddr),
.S_AXI_ALEN (sr_awlen),
.S_AXI_ASIZE (sr_awsize),
.S_AXI_ABURST (sr_awburst),
.S_AXI_ALOCK (sr_awlock),
.S_AXI_ACACHE (sr_awcache),
.S_AXI_APROT (sr_awprot),
.S_AXI_AREGION (sr_awregion),
.S_AXI_AQOS (sr_awqos),
.S_AXI_AVALID (sr_awvalid),
.S_AXI_AREADY (sr_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i ),
.M_AXI_ALEN (m_axi_awlen_i ),
.M_AXI_ASIZE (m_axi_awsize_i ),
.M_AXI_ABURST (m_axi_awburst_i ),
.M_AXI_ALOCK (m_axi_awlock_i ),
.M_AXI_ACACHE (m_axi_awcache_i ),
.M_AXI_APROT (m_axi_awprot_i ),
.M_AXI_AREGION (m_axi_awregion_i ),
.M_AXI_AQOS (m_axi_awqos_i ),
.M_AXI_AVALID (m_axi_awvalid_i ),
.M_AXI_AREADY (m_axi_awready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_w_upsizer
// Packet FIFO Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_write_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (m_axi_awaddr_i ),
.S_AXI_AWLEN (m_axi_awlen_i ),
.S_AXI_AWSIZE (m_axi_awsize_i ),
.S_AXI_AWBURST (m_axi_awburst_i ),
.S_AXI_AWLOCK (m_axi_awlock_i ),
.S_AXI_AWCACHE (m_axi_awcache_i ),
.S_AXI_AWPROT (m_axi_awprot_i ),
.S_AXI_AWREGION (m_axi_awregion_i ),
.S_AXI_AWQOS (m_axi_awqos_i ),
.S_AXI_AWVALID (m_axi_awvalid_i ),
.S_AXI_AWREADY (m_axi_awready_i ),
// Master Interface Write Address Port
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWREGION (m_axi_awregion),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_w_upsizer
// Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer #
(
.C_FAMILY ("rtl"),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
assign m_axi_awaddr = m_axi_awaddr_i ;
assign m_axi_awlen = m_axi_awlen_i ;
assign m_axi_awsize = m_axi_awsize_i ;
assign m_axi_awburst = m_axi_awburst_i ;
assign m_axi_awlock = m_axi_awlock_i ;
assign m_axi_awcache = m_axi_awcache_i ;
assign m_axi_awprot = m_axi_awprot_i ;
assign m_axi_awregion = m_axi_awregion_i ;
assign m_axi_awqos = m_axi_awqos_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_awready_i = m_axi_awready ;
end // gen_w_upsizer
// Write Response channel.
assign wr_cmd_id_ready = s_axi_bvalid_i & s_axi_bready;
assign s_axi_bid = wr_cmd_id;
assign s_axi_bresp = s_axi_bresp_i;
assign s_axi_bvalid = s_axi_bvalid_i;
if (P_CLK_CONV) begin : gen_b_clk_conv
if (C_AXI_IS_ACLK_ASYNC == 0) begin : gen_b_sync_conv
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( 2 ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_CONV_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_axi_bresp ) ,
.S_VALID ( m_axi_bvalid ) ,
.S_READY ( m_axi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_axi_bresp_i ) ,
.M_VALID ( s_axi_bvalid_i ) ,
.M_READY ( s_axi_bready )
);
end else begin : gen_b_async_conv
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_DIN_WIDTH_WACH(63),
.C_DIN_WIDTH_WDCH(38),
.C_DIN_WIDTH_WRCH(3),
.C_DIN_WIDTH_RACH(63),
.C_DIN_WIDTH_RDCH(36),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(2),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(32),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(5),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(29),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) dw_fifogen_b_async (
.m_aclk(m_axi_aclk),
.s_aclk(s_axi_aclk),
.s_aresetn(sm_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp_i),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid_i),
.s_axi_bready(s_axi_bready),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(5'b0),
.axi_b_prog_empty_thresh(5'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
end else begin : gen_b_passthru
assign m_axi_bready = s_axi_bready;
assign s_axi_bresp_i = m_axi_bresp;
assign s_axi_bvalid_i = m_axi_bvalid;
end // gen_b
end else begin : NO_WRITE
assign sr_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
assign m_axi_wvalid = 1'b0;
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i ;
wire [8-1:0] m_axi_arlen_i ;
wire [3-1:0] m_axi_arsize_i ;
wire [2-1:0] m_axi_arburst_i ;
wire [2-1:0] m_axi_arlock_i ;
wire [4-1:0] m_axi_arcache_i ;
wire [3-1:0] m_axi_arprot_i ;
wire [4-1:0] m_axi_arregion_i ;
wire [4-1:0] m_axi_arqos_i ;
wire m_axi_arvalid_i ;
wire m_axi_arready_i ;
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [C_AXI_ADDR_WIDTH-1:0] rd_cmd_si_addr;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_si_id;
wire [8-1:0] rd_cmd_si_len;
wire [3-1:0] rd_cmd_si_size;
wire [2-1:0] rd_cmd_si_burst;
// Read Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
// .C_FIFO_MODE (0),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (P_RID_QUEUE),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_arid),
.S_AXI_AADDR (sr_araddr),
.S_AXI_ALEN (sr_arlen),
.S_AXI_ASIZE (sr_arsize),
.S_AXI_ABURST (sr_arburst),
.S_AXI_ALOCK (sr_arlock),
.S_AXI_ACACHE (sr_arcache),
.S_AXI_APROT (sr_arprot),
.S_AXI_AREGION (sr_arregion),
.S_AXI_AQOS (sr_arqos),
.S_AXI_AVALID (sr_arvalid),
.S_AXI_AREADY (sr_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i ),
.M_AXI_ALEN (m_axi_arlen_i ),
.M_AXI_ASIZE (m_axi_arsize_i ),
.M_AXI_ABURST (m_axi_arburst_i ),
.M_AXI_ALOCK (m_axi_arlock_i ),
.M_AXI_ACACHE (m_axi_arcache_i ),
.M_AXI_APROT (m_axi_arprot_i ),
.M_AXI_AREGION (m_axi_arregion_i ),
.M_AXI_AQOS (m_axi_arqos_i ),
.M_AXI_AVALID (m_axi_arvalid_i ),
.M_AXI_AREADY (m_axi_arready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_r_upsizer
// Packet FIFO Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_read_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_ARADDR (m_axi_araddr_i ),
.S_AXI_ARLEN (m_axi_arlen_i ),
.S_AXI_ARSIZE (m_axi_arsize_i ),
.S_AXI_ARBURST (m_axi_arburst_i ),
.S_AXI_ARLOCK (m_axi_arlock_i ),
.S_AXI_ARCACHE (m_axi_arcache_i ),
.S_AXI_ARPROT (m_axi_arprot_i ),
.S_AXI_ARREGION (m_axi_arregion_i ),
.S_AXI_ARQOS (m_axi_arqos_i ),
.S_AXI_ARVALID (m_axi_arvalid_i ),
.S_AXI_ARREADY (m_axi_arready_i ),
// Master Interface Write Address Port
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARREGION (m_axi_arregion),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
// Slave Interface Write Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Write Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_r_upsizer
// Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (mr_rdata),
.M_AXI_RRESP (mr_rresp),
.M_AXI_RLAST (mr_rlast),
.M_AXI_RVALID (mr_rvalid),
.M_AXI_RREADY (mr_rready)
);
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (0),
.C_AXI_ID_WIDTH (1),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_R (C_M_AXI_R_REGISTER)
)
mi_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (m_aclk),
.s_axi_awid ( 1'b0 ),
.s_axi_awaddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_awlen ( 8'b0 ),
.s_axi_awsize ( 3'b0 ),
.s_axi_awburst ( 2'b0 ),
.s_axi_awlock ( 1'b0 ),
.s_axi_awcache ( 4'b0 ),
.s_axi_awprot ( 3'b0 ),
.s_axi_awregion ( 4'b0 ),
.s_axi_awqos ( 4'b0 ),
.s_axi_awuser ( 1'b0 ),
.s_axi_awvalid ( 1'b0 ),
.s_axi_awready ( ),
.s_axi_wid ( 1'b0 ),
.s_axi_wdata ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid ( 1'b0 ),
.s_axi_araddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_arlen ( 8'b0 ),
.s_axi_arsize ( 3'b0 ),
.s_axi_arburst ( 2'b0 ),
.s_axi_arlock ( 1'b0 ),
.s_axi_arcache ( 4'b0 ),
.s_axi_arprot ( 3'b0 ),
.s_axi_arregion ( 4'b0 ),
.s_axi_arqos ( 4'b0 ),
.s_axi_aruser ( 1'b0 ),
.s_axi_arvalid ( 1'b0 ),
.s_axi_arready ( ),
.s_axi_rid (),
.s_axi_rdata (mr_rdata ),
.s_axi_rresp (mr_rresp ),
.s_axi_rlast (mr_rlast ),
.s_axi_ruser (),
.s_axi_rvalid (mr_rvalid ),
.s_axi_rready (mr_rready ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready (1'b0),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready (1'b0),
.m_axi_rid (1'b0 ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_ruser (1'b0 ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready_i )
);
assign m_axi_araddr = m_axi_araddr_i ;
assign m_axi_arlen = m_axi_arlen_i ;
assign m_axi_arsize = m_axi_arsize_i ;
assign m_axi_arburst = m_axi_arburst_i ;
assign m_axi_arlock = m_axi_arlock_i ;
assign m_axi_arcache = m_axi_arcache_i ;
assign m_axi_arprot = m_axi_arprot_i ;
assign m_axi_arregion = m_axi_arregion_i ;
assign m_axi_arqos = m_axi_arqos_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_arready_i = m_axi_arready ;
assign m_axi_rready = m_axi_rready_i;
end // gen_r_upsizer
end else begin : NO_READ
assign sr_arready = 1'b0;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
assign mr_rready = 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
//deps: sdram_controller3.v, IS42S16160.v
`timescale 1ns/1ps
module sdram_controller3_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [12:0] DRAM_ADDR; // From controller of sdram_controller3.v
wire [1:0] DRAM_BA; // From controller of sdram_controller3.v
wire DRAM_CAS_N; // From controller of sdram_controller3.v
wire DRAM_CKE; // From controller of sdram_controller3.v
wire DRAM_CLK; // From controller of sdram_controller3.v
wire DRAM_CS_N; // From controller of sdram_controller3.v
wire [15:0] DRAM_DQ; // To/From controller of sdram_controller3.v
wire [1:0] DRAM_DQM; // From controller of sdram_controller3.v
wire DRAM_RAS_N; // From controller of sdram_controller3.v
wire DRAM_WE_N; // From controller of sdram_controller3.v
wire [31:0] data_out; // From controller of sdram_controller3.v
wire data_valid; // From controller of sdram_controller3.v
wire write_complete; // From controller of sdram_controller3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg [23:0] address; // To controller of sdram_controller3.v
reg [31:0] data_in; // To controller of sdram_controller3.v
reg req_read; // To controller of sdram_controller3.v
reg req_write; // To controller of sdram_controller3.v
reg rst; // To controller of sdram_controller3.v
// End of automatics
sdram_controller3 controller(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
.data_valid (data_valid),
.write_complete (write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (address[23:0]),
.req_read (req_read),
.req_write (req_write),
.data_in (data_in[31:0]));
IS42S16160 RAM (
// Inouts
.Dq (DRAM_DQ[15:0]),
// Inputs
.Addr (DRAM_ADDR[12:0]),
.Ba (DRAM_BA[1:0]),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm (DRAM_DQM[1:0]));
initial begin
rst = 1;
CLOCK_50 = 0;
CLOCK_100 = 0;
CLOCK_100_del_3ns = 0;
address = 0;
req_read = 0;
req_write = 0;
data_in = 0;
$dumpfile("dump.vcd");
$dumpvars;
#3000 $finish;
end
always #10 CLOCK_50 <= ~CLOCK_50;
always #5 begin
CLOCK_100 <= ~CLOCK_100;
end
always @(CLOCK_100) begin
#3
CLOCK_100_del_3ns <= CLOCK_100;
end
initial begin
#20 rst = 0;
#1000 address = 16;
data_in = 32'h12345678;
req_write = 1;
#20 req_write = 0;
@(posedge write_complete) #60
address = 16;
req_read = 1;
#20
req_read = 0;
end // initial begin
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
wire start;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_hs_demo s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:30 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_0_stub.v
// Design : zynq_design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0, FTMT_P2F_TRIGACK_0, FTMT_P2F_TRIG_0, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,FTMT_F2P_TRIG_0,FTMT_F2P_TRIGACK_0,FTMT_P2F_TRIGACK_0,FTMT_P2F_TRIG_0,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
wire [33:0] data_p_s;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
assign data_p = data_p_s[31:0];
MULT_MACRO #(
.LATENCY (3),
.A_DATA_WIDTH (17),
.B_DATA_WIDTH (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A ({1'b0, data_a}),
.B ({1'b0, data_b}),
.P (data_p_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
oDIN,
oCS_n,
oSCLK,
iDOUT,
oADC_12_bit_channel_0,
oADC_12_bit_channel_1,
oADC_12_bit_channel_2,
oADC_12_bit_channel_3,
oADC_12_bit_channel_4,
oADC_12_bit_channel_5,
oADC_12_bit_channel_6,
oADC_12_bit_channel_7
);
input iRST;
input iCLK;
input iCLK_n;
input iGO;
output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;
output reg [11:0] oADC_12_bit_channel_0;
output reg [11:0] oADC_12_bit_channel_1;
output reg [11:0] oADC_12_bit_channel_2;
output reg [11:0] oADC_12_bit_channel_3;
output reg [11:0] oADC_12_bit_channel_4;
output reg [11:0] oADC_12_bit_channel_5;
output reg [11:0] oADC_12_bit_channel_6;
output reg [11:0] oADC_12_bit_channel_7;
reg [2:0] channel;
reg data;
reg go_en;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [31:0] adc_counter;
assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
always@( iCLK )//posedge iGO or posedge iRST)
begin
if(iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end
always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end
always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)
data <= channel[2];
else if (cont == 3)
data <= channel[1];
else if (cont == 4)
data <= channel[0];
else
data <= 0;
end
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
end
else
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
begin
if ( adc_counter < 32'd20 )
begin
adc_counter <= adc_counter + 1'b1;
end
else
begin
if (channel == 3'd0)
oADC_12_bit_channel_0 <= adc_data;
else if (channel == 3'd1)
oADC_12_bit_channel_1 <= adc_data;
else if (channel == 3'd2)
oADC_12_bit_channel_2 <= adc_data;
else if (channel == 3'd3)
oADC_12_bit_channel_3 <= adc_data;
else if (channel == 3'd4)
oADC_12_bit_channel_4 <= adc_data;
else if (channel == 3'd5)
oADC_12_bit_channel_5 <= adc_data;
else if (channel == 3'd6)
oADC_12_bit_channel_6 <= adc_data;
else if (channel == 3'd7)
oADC_12_bit_channel_7 <= adc_data;
adc_counter <= 32'd0;
channel <= channel + 1'b1;
end
end
end
end
endmodule
|
`timescale 1ns/1ns
`define IDLE 2'b00
`define LOAD 2'b01
`define CNTING 2'b10
`define INT 2'b11
`define MODE_0 2'b00
`define MODE_1 2'b01
module coco_timer (clk_i,rst_i,add_i,we_i,dat_i,dat_o,irq);
input [3:2] add_i;
input clk_i,rst_i,we_i;
input [31:0] dat_i;
output [31:0] dat_o;
output irq;
reg [31:0] count;
reg [31:0] preset;
reg [31:0] ctrl;
reg _irq;
reg [1:0] curr_state,next_state;
assign dat_o=(add_i==2'b00)?ctrl:
(add_i==2'b01)?preset:
(add_i==2'b10)?count:
32'h12345678;
assign irq=_irq;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
count<=31'h0000_0000;
preset<=31'h0000_0000;
ctrl<=31'h0000_0000;
_irq<=0;
curr_state<=`IDLE;
end // if(rst)
else if (we_i) begin
if (add_i==2'b00) begin
ctrl<=dat_i;
curr_state<=next_state;
end // if(dat_i)
else if (add_i==2'b01) begin
preset<=dat_i;
_irq<=0;
next_state<=`LOAD;
end // if(add_i=2'b01)
else if (add_i==2'b10) begin
count<=dat_i;
curr_state<=next_state;
end
else begin
curr_state<=next_state;
end
end // if(we)
else begin
curr_state<=next_state;
end
end // always @ (posedge clk_i or posedge rst_i)
always @(curr_state or ctrl or count) begin
next_state=`IDLE;
if (!ctrl[0]) begin
next_state=`IDLE;
end // if(ctrl[0])
else begin
case (curr_state)
`IDLE: begin
if (ctrl[2:1]==`MODE_1) begin
next_state=`LOAD;
end // if(ctrl[2:1])
//ctrl[2:1]==`MODE_0
else if (ctrl[0] && count>1) begin
next_state=`CNTING;
end
else begin
next_state=`IDLE;
end
end // case: IDLE
`LOAD: begin
next_state=`CNTING;
end
`CNTING: begin
if (count==1) begin
next_state=`INT;
end // if(count==1)
else begin
next_state=`CNTING;
end
end
default: begin
next_state=`IDLE;
end
endcase // case(curr_state)
end
end // always @ (curr_state)
always @(posedge clk_i or posedge rst_i) begin
case (next_state)
`CNTING: begin
count<=count-1;
end
`INT: begin
_irq<=(ctrl[3]&&ctrl[2:1]==`MODE_0);
end
`LOAD: begin
count<=preset;
_irq<=0;
end
default: begin
//do nothing
end
endcase // case(next_state)
end
endmodule // cp0
|
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate unary nor ~|(value)
// SJW - ~| in behavioral assignment to reg.
module main;
reg [3:0] vect;
reg error;
reg result;
initial
begin
error = 0;
for(vect=4'b0001;vect<4'b1111;vect = vect + 1)
begin
result = ~| vect;
if(result !== 1'b0)
begin
$display("FAILED - Unary nor ~|(%b)=%b",vect,result);
error = 1'b1;
end
end
#1;
vect = 4'b0000;
result = ~| vect;
if(result !== 1'b1)
begin
$display("FAILED - Unary nor |~(%b)=%b",vect,result);
error = 1'b1;
end
if(error === 0 )
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:40:46 12/20/2010
// Design Name:
// Module Name: clk_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_test(
input clk,
input sysclk,
output [31:0] snes_sysclk_freq
);
reg [31:0] snes_sysclk_freq_r;
assign snes_sysclk_freq = snes_sysclk_freq_r;
reg [31:0] sysclk_counter;
reg [31:0] sysclk_value;
initial snes_sysclk_freq_r = 32'hFFFFFFFF;
initial sysclk_counter = 0;
initial sysclk_value = 0;
reg [1:0] sysclk_sreg;
always @(posedge clk) sysclk_sreg <= {sysclk_sreg[0], sysclk};
wire sysclk_rising = (sysclk_sreg == 2'b01);
always @(posedge clk) begin
if(sysclk_counter < 96000000) begin
sysclk_counter <= sysclk_counter + 1;
if(sysclk_rising) sysclk_value <= sysclk_value + 1;
end else begin
snes_sysclk_freq_r <= sysclk_value;
sysclk_counter <= 0;
sysclk_value <= 0;
end
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module efifo_module
#(
parameter DATA_WIDTH = 16,
parameter DEPTH = 2
)(
// inputs:
clk,
rd,
rst_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ DATA_WIDTH - 1 : 0 ] rd_data;
input clk;
input rd;
input rst_n;
input wr;
input [ DATA_WIDTH - 1 : 0 ] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ DEPTH - 1 : 0 ] entries;
reg [ DATA_WIDTH - 1 : 0 ] entry_0;
reg [ DATA_WIDTH - 1 : 0 ] entry_1;
wire full;
reg rd_address;
reg [ DATA_WIDTH - 1 : 0 ] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == DEPTH;
assign almost_full = entries >= DEPTH - 1;
assign empty = entries == 0;
assign almost_empty = entries <= DEPTH - 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=next_pc+32'd4;
end
end
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)] : No.
- [d mumble (b a 5)] : Yes (grumble mumble).
- [d bool (b a 5)] : Yes (grumble bool).
- [e bool true] : Yes (grumble bool).
- [e mumble (b c 0)] : Yes (grumble mumble).
- [e bool (b c 0)] : No.
- [c] : No (type mumble).
[] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
Confused by definition of "element" here.
x: 0 elements (just the continuation of the data structure)
y: 1 element (a bool, and the continuation of baz)
[] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
Check ([3 + 4] ++ nil).
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| 0 => nil
| S count' => n :: repeat n count'
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s. induction s as [|h t].
Case "s = []". simpl. reflexivity.
Case "s = h::t". simpl. rewrite IHt. simpl. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros X l. induction l as [|v l'].
Case "l = []". simpl. reflexivity.
Case "l = v::l'". simpl. rewrite rev_snoc. rewrite IHl'. reflexivity.
Qed.
Theorem snoc_append : forall X (l:list X) x,
snoc l x = l ++ [x].
Proof.
intros X l x. induction l as [|y l'].
Case "l=[]". reflexivity.
Case "l=y::l'". simpl. rewrite IHl'. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v. induction l1 as [|x l'].
Case "l1 = []". simpl. reflexivity.
Case "l1=x::l'". simpl. rewrite IHl'. reflexivity.
Qed.
Theorem rev_app : forall X (l:list X) x,
x :: rev l = rev (l ++ [x]).
Proof.
intros X l. induction l as [|y l'].
Case "l=[]". simpl. reflexivity.
Case "l=y::l'". intros. simpl.
rewrite snoc_append.
rewrite <- IHl'.
simpl.
rewrite snoc_append.
reflexivity.
Qed.
(** [] *)
Theorem cons_app_assoc : forall X (l1 l2:list X) x,
(x :: l1) ++ l2 = x :: (l1 ++ l2).
Proof.
intros. reflexivity. Qed.
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
forall X Y : Type, list X -> list Y -> list (X*Y)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print?
[(1,false);(2,false)] : list (nat*bool)
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([],[])
| (x,y) :: ls => (x :: fst (split ls), y :: snd (split ls))
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| x :: _ => Some x
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z := f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros X Y Z f p. destruct p. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (negb (ble_nat n 7)) (evenb n)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun n => negb (test n)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc : forall (X Y : Type)
(f : X -> Y) (l : list X) (x : X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros X Y f l x. induction l as [|h l'].
Case "l = []". simpl. reflexivity.
Case "l=h::l'". simpl. rewrite IHl'. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros X Y f l. induction l as [|x l'].
Case "l = []". simpl. reflexivity.
Case "l=x::l'". simpl. rewrite map_snoc. rewrite IHl'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| x :: ls => (f x) ++ (flat_map f ls)
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different?
List flattening
*)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
reflexivity. Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros X x1 x2 k1 k2 f H H0.
unfold override.
rewrite H0.
rewrite H.
reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros X l. induction l as [|x l'].
Case "l = []". reflexivity.
Case "l=x::l'".
simpl.
unfold fold_length.
simpl.
rewrite <- IHl'.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x ly => (f x) :: ly) l [].
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
Theorem fold_map_correct : forall X Y (f : X -> Y) (l : list X),
map f l = fold_map f l.
Proof.
intros X Y f l. induction l as [|x l'].
Case "l = []". reflexivity.
Case "l = x::l'".
simpl.
rewrite IHl'.
unfold fold_map.
simpl.
reflexivity.
Qed.
(** [] *)
(* $Date: 2013-09-26 14:40:26 -0400 (Thu, 26 Sep 2013) $ *)
|
extern "C" int checkWgAvailable();
extern "C" void prepareNextWg();
extern "C" int hardDisGetWgId();
extern "C" int hardDisGetWfCnt();
extern "C" int hardDisGetWfNumThrds();
extern "C" int hardDisGetVregSize();
extern "C" int hardDisGetVregSizePerWf();
extern "C" int hardDisGetSregSize() ;
extern "C" int hardDisGetSregSizePerWf();
extern "C" int hardDisGetLdsSize();
extern "C" int hardDisGetGdsSize();
extern "C" int hardDisGetPc();
module dispatcher_hard_host (/*AUTOARG*/
// Outputs
host_wg_valid, host_wg_id, host_num_wf, host_wf_size,
host_vgpr_size_total, host_sgpr_size_total, host_lds_size_total,
host_gds_size_total, host_vgpr_size_per_wf, host_sgpr_size_per_wf,
host_start_pc,
// Inputs
inflight_wg_buffer_host_rcvd_ack, inflight_wg_buffer_host_wf_done,
inflight_wg_buffer_host_wf_done_wg_id, clk, rst
) ;
// Resource accounting parameters
parameter WG_ID_WIDTH = 6;
parameter WG_SLOT_ID_WIDTH = 6;
parameter WF_COUNT_WIDTH = 4;
parameter WAVE_ITEM_WIDTH = 6;
parameter VGPR_ID_WIDTH = 8;
parameter SGPR_ID_WIDTH = 4;
parameter LDS_ID_WIDTH = 8;
parameter GDS_ID_WIDTH = 14;
parameter MEM_ADDR_WIDTH = 32;
// Output from cu
output host_wg_valid;
output [WG_ID_WIDTH-1:0] host_wg_id;
output [WF_COUNT_WIDTH-1:0] host_num_wf;
output [WAVE_ITEM_WIDTH-1:0] host_wf_size; // number of work itens in the last wf
output [VGPR_ID_WIDTH :0] host_vgpr_size_total;
output [SGPR_ID_WIDTH :0] host_sgpr_size_total;
output [LDS_ID_WIDTH :0] host_lds_size_total;
output [GDS_ID_WIDTH :0] host_gds_size_total;
output [VGPR_ID_WIDTH :0] host_vgpr_size_per_wf;
output [SGPR_ID_WIDTH :0] host_sgpr_size_per_wf;
output [MEM_ADDR_WIDTH-1:0] host_start_pc;
// Input from CU
input inflight_wg_buffer_host_rcvd_ack;
input inflight_wg_buffer_host_wf_done;
input [WG_ID_WIDTH-1:0] inflight_wg_buffer_host_wf_done_wg_id;
input clk,rst;
reg host_wg_valid_i;
reg [WG_ID_WIDTH-1:0] host_wg_id_i;
reg [WF_COUNT_WIDTH-1:0] host_num_wf_i;
reg [WAVE_ITEM_WIDTH-1:0] host_wf_size_i; // number of work itens in the last wf
reg [VGPR_ID_WIDTH :0] host_vgpr_size_total_i;
reg [SGPR_ID_WIDTH :0] host_sgpr_size_total_i;
reg [LDS_ID_WIDTH :0] host_lds_size_total_i;
reg [GDS_ID_WIDTH :0] host_gds_size_total_i;
reg [VGPR_ID_WIDTH :0] host_vgpr_size_per_wf_i;
reg [SGPR_ID_WIDTH :0] host_sgpr_size_per_wf_i;
reg [MEM_ADDR_WIDTH-1:0] host_start_pc_i;
reg initialized;
always @ ( posedge clk or posedge rst ) begin
if(rst) begin
host_wg_valid_i = 0;
host_wg_id_i = 0;
host_num_wf_i = 0;
host_wf_size_i = 0;
host_vgpr_size_total_i = 0;
host_sgpr_size_total_i = 0;
host_lds_size_total_i = 0;
host_gds_size_total_i = 0;
host_vgpr_size_per_wf_i = 0;
host_sgpr_size_per_wf_i = 0;
host_start_pc_i = 0;
initialized = 0;
end
else begin
if(inflight_wg_buffer_host_rcvd_ack ||
!initialized) begin
if(checkWgAvailable()) begin
host_wg_valid_i = 1'b1;
host_wg_id_i = hardDisGetWgId();
host_num_wf_i = hardDisGetWfCnt();
host_wf_size_i = hardDisGetWfNumThrds();
host_vgpr_size_total_i = hardDisGetVregSize();
host_sgpr_size_total_i = hardDisGetSregSize();
host_lds_size_total_i = hardDisGetLdsSize();
host_gds_size_total_i = hardDisGetGdsSize();
host_vgpr_size_per_wf_i = hardDisGetVregSizePerWf();
host_sgpr_size_per_wf_i = hardDisGetSregSizePerWf();
host_start_pc_i = hardDisGetPc();
prepareNextWg();
initialized = 1'b1;
end
else begin
host_wg_valid_i = 1'b0;
end // else: !if(checkWgAvailable())
end // if (inflight_wg_buffer_host_rcvd_ack ||...
end // else: !if(rst)
end // always @ ( posedge clk or posedge rst )
assign host_wg_valid = host_wg_valid_i;
assign host_wg_id = host_wg_id_i;
assign host_num_wf = host_num_wf_i;
assign host_wf_size = host_wf_size_i;
assign host_vgpr_size_total = host_vgpr_size_total_i;
assign host_sgpr_size_total = host_sgpr_size_total_i;
assign host_lds_size_total = host_lds_size_total_i;
assign host_gds_size_total = host_gds_size_total_i;
assign host_vgpr_size_per_wf = host_vgpr_size_per_wf_i;
assign host_sgpr_size_per_wf = host_sgpr_size_per_wf_i;
assign host_start_pc = host_start_pc_i;
endmodule // dispatcher_hard_host
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
`define AUTOTB_DUT adder
`define AUTOTB_DUT_INST AESL_inst_adder
`define AUTOTB_TOP apatb_adder_top
`define AUTOTB_LAT_RESULT_FILE "adder.result.lat.rb"
`define AUTOTB_PER_RESULT_TRANS_FILE "adder.performance.result.transaction.xml"
`define AUTOTB_TOP_INST AESL_inst_apatb_adder_top
`define AUTOTB_MAX_ALLOW_LATENCY 15000000
`define AUTOTB_TRANSACTION_NUM 1
`define AUTOTB_CLOCK_PERIOD 10.000000
`define LENGTH_a 1
`define LENGTH_b 1
`define LENGTH_c 1
`define AESL_DEPTH_a 1
`define AESL_DEPTH_b 1
`define AESL_DEPTH_c 1
`define AUTOTB_TVIN_a "../tv/cdatafile/c.adder.autotvin_a.dat"
`define AUTOTB_TVIN_b "../tv/cdatafile/c.adder.autotvin_b.dat"
`define AUTOTB_TVIN_a_out_wrapc "../tv/rtldatafile/rtl.adder.autotvin_a.dat"
`define AUTOTB_TVIN_b_out_wrapc "../tv/rtldatafile/rtl.adder.autotvin_b.dat"
`define AUTOTB_TVOUT_c "../tv/cdatafile/c.adder.autotvout_c.dat"
`define AUTOTB_TVOUT_c_out_wrapc "../tv/rtldatafile/rtl.adder.autotvout_c.dat"
module `AUTOTB_TOP;
task read_token;
input integer fp;
output reg [199 : 0] token;
reg [7:0] c;
reg intoken;
reg done;
begin
token = "";
intoken = 0;
done = 0;
while (!done) begin
c = $fgetc(fp);
if (c == 8'hff) begin // EOF
done = 1;
end
else if (c == " " || c == "\011" || c == "\012" || c == "\015") begin // blank
if (intoken) begin
done = 1;
end
end
else begin // valid character
intoken = 1;
token = (token << 8) | c;
end
end
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
reg [31 : 0] AESL_mLatCnterIn [0 : `AUTOTB_TRANSACTION_NUM + 1];
reg [31 : 0] AESL_mLatCnterIn_addr;
reg [31 : 0] AESL_mLatCnterOut [0 : `AUTOTB_TRANSACTION_NUM + 1];
reg [31 : 0] AESL_mLatCnterOut_addr ;
reg [31 : 0] AESL_clk_counter ;
wire s_axi_AXI_CTRL_AWVALID;
wire s_axi_AXI_CTRL_AWREADY;
wire [5 : 0] s_axi_AXI_CTRL_AWADDR;
wire s_axi_AXI_CTRL_WVALID;
wire s_axi_AXI_CTRL_WREADY;
wire [31 : 0] s_axi_AXI_CTRL_WDATA;
wire [3 : 0] s_axi_AXI_CTRL_WSTRB;
wire s_axi_AXI_CTRL_ARVALID;
wire s_axi_AXI_CTRL_ARREADY;
wire [5 : 0] s_axi_AXI_CTRL_ARADDR;
wire s_axi_AXI_CTRL_RVALID;
wire s_axi_AXI_CTRL_RREADY;
wire [31 : 0] s_axi_AXI_CTRL_RDATA;
wire [1 : 0] s_axi_AXI_CTRL_RRESP;
wire s_axi_AXI_CTRL_BVALID;
wire s_axi_AXI_CTRL_BREADY;
wire [1 : 0] s_axi_AXI_CTRL_BRESP;
wire ap_clk;
wire ap_rst_n;
wire interrupt;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire AXI_CTRL_read_data_finish;
wire AXI_CTRL_write_data_finish;
wire AESL_slave_start;
wire AESL_slave_write_start_in;
wire AESL_slave_write_start_finish;
reg AESL_slave_ready;
wire AESL_slave_output_done;
reg ready_rise = 0;
reg start_rise = 0;
reg slave_start_status = 0;
reg slave_done_status = 0;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.s_axi_AXI_CTRL_AWVALID(s_axi_AXI_CTRL_AWVALID),
.s_axi_AXI_CTRL_AWREADY(s_axi_AXI_CTRL_AWREADY),
.s_axi_AXI_CTRL_AWADDR(s_axi_AXI_CTRL_AWADDR),
.s_axi_AXI_CTRL_WVALID(s_axi_AXI_CTRL_WVALID),
.s_axi_AXI_CTRL_WREADY(s_axi_AXI_CTRL_WREADY),
.s_axi_AXI_CTRL_WDATA(s_axi_AXI_CTRL_WDATA),
.s_axi_AXI_CTRL_WSTRB(s_axi_AXI_CTRL_WSTRB),
.s_axi_AXI_CTRL_ARVALID(s_axi_AXI_CTRL_ARVALID),
.s_axi_AXI_CTRL_ARREADY(s_axi_AXI_CTRL_ARREADY),
.s_axi_AXI_CTRL_ARADDR(s_axi_AXI_CTRL_ARADDR),
.s_axi_AXI_CTRL_RVALID(s_axi_AXI_CTRL_RVALID),
.s_axi_AXI_CTRL_RREADY(s_axi_AXI_CTRL_RREADY),
.s_axi_AXI_CTRL_RDATA(s_axi_AXI_CTRL_RDATA),
.s_axi_AXI_CTRL_RRESP(s_axi_AXI_CTRL_RRESP),
.s_axi_AXI_CTRL_BVALID(s_axi_AXI_CTRL_BVALID),
.s_axi_AXI_CTRL_BREADY(s_axi_AXI_CTRL_BREADY),
.s_axi_AXI_CTRL_BRESP(s_axi_AXI_CTRL_BRESP),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst_n = AESL_reset;
assign ap_rst_n_n = ~AESL_reset;
assign AESL_reset = rst;
assign AESL_start = start;
assign AESL_ce = ce;
assign AESL_continue = continue;
assign AESL_slave_write_start_in = slave_start_status & AXI_CTRL_write_data_finish;
assign AESL_slave_start = AESL_slave_write_start_finish;
assign AESL_done = slave_done_status & AXI_CTRL_read_data_finish;
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
slave_start_status <= 1;
end
else begin
if (AESL_start == 1 ) begin
start_rise = 1;
end
if (start_rise == 1 && AESL_done == 1 ) begin
slave_start_status <= 1;
end
if (AESL_slave_write_start_in == 1) begin
slave_start_status <= 0;
start_rise = 0;
end
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
else begin
if (AESL_ready == 1 ) begin
ready_rise = 1;
end
if (ready_rise == 1 && AESL_done_delay == 1 ) begin
AESL_slave_ready <= 1;
end
if (AESL_slave_ready == 1) begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
end
end
always @ (posedge AESL_clock)
begin
if (AESL_done == 1) begin
slave_done_status <= 0;
end
else if (AESL_slave_output_done == 1 ) begin
slave_done_status <= 1;
end
end
AESL_axi_slave_AXI_CTRL AESL_AXI_SLAVE_AXI_CTRL(
.clk (AESL_clock),
.reset (AESL_reset),
.TRAN_s_axi_AXI_CTRL_AWADDR (s_axi_AXI_CTRL_AWADDR),
.TRAN_s_axi_AXI_CTRL_AWVALID (s_axi_AXI_CTRL_AWVALID),
.TRAN_s_axi_AXI_CTRL_AWREADY (s_axi_AXI_CTRL_AWREADY),
.TRAN_s_axi_AXI_CTRL_WVALID (s_axi_AXI_CTRL_WVALID),
.TRAN_s_axi_AXI_CTRL_WREADY (s_axi_AXI_CTRL_WREADY),
.TRAN_s_axi_AXI_CTRL_WDATA (s_axi_AXI_CTRL_WDATA),
.TRAN_s_axi_AXI_CTRL_WSTRB (s_axi_AXI_CTRL_WSTRB),
.TRAN_s_axi_AXI_CTRL_ARADDR (s_axi_AXI_CTRL_ARADDR),
.TRAN_s_axi_AXI_CTRL_ARVALID (s_axi_AXI_CTRL_ARVALID),
.TRAN_s_axi_AXI_CTRL_ARREADY (s_axi_AXI_CTRL_ARREADY),
.TRAN_s_axi_AXI_CTRL_RVALID (s_axi_AXI_CTRL_RVALID),
.TRAN_s_axi_AXI_CTRL_RREADY (s_axi_AXI_CTRL_RREADY),
.TRAN_s_axi_AXI_CTRL_RDATA (s_axi_AXI_CTRL_RDATA),
.TRAN_s_axi_AXI_CTRL_RRESP (s_axi_AXI_CTRL_RRESP),
.TRAN_s_axi_AXI_CTRL_BVALID (s_axi_AXI_CTRL_BVALID),
.TRAN_s_axi_AXI_CTRL_BREADY (s_axi_AXI_CTRL_BREADY),
.TRAN_s_axi_AXI_CTRL_BRESP (s_axi_AXI_CTRL_BRESP),
.TRAN_AXI_CTRL_read_data_finish(AXI_CTRL_read_data_finish),
.TRAN_AXI_CTRL_write_data_finish(AXI_CTRL_write_data_finish),
.TRAN_AXI_CTRL_ready_out (AESL_ready),
.TRAN_AXI_CTRL_ready_in (AESL_slave_ready),
.TRAN_AXI_CTRL_done_out (AESL_slave_output_done),
.TRAN_AXI_CTRL_idle_out (AESL_idle),
.TRAN_AXI_CTRL_write_start_in (AESL_slave_write_start_in),
.TRAN_AXI_CTRL_write_start_finish (AESL_slave_write_start_finish),
.TRAN_AXI_CTRL_transaction_done_in (AESL_done_delay),
.TRAN_AXI_CTRL_interrupt (interrupt),
.TRAN_AXI_CTRL_start_in (AESL_slave_start)
);
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 1);
while(AESL_ready_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
initial begin : generate_ready_cnt_proc
ready_cnt = 0;
wait(AESL_reset === 1);
while(ready_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
ready_cnt = ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
initial begin : generate_done_cnt_proc
done_cnt = 0;
wait(AESL_reset === 1);
while(done_cnt != `AUTOTB_TRANSACTION_NUM) begin
while(AESL_done !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
done_cnt = done_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
@(posedge AESL_clock);
# 0.4;
$finish;
end
initial fork
AESL_clock = 0;
forever #(`AUTOTB_CLOCK_PERIOD/2) AESL_clock = ~AESL_clock;
join
initial begin : initial_process
integer rand;
rst = 0;
# 100;
repeat(3) @(posedge AESL_clock);
rst = 1;
end
initial begin : start_process
integer rand;
start = 0;
ce = 1;
wait(AESL_reset === 1);
@(posedge AESL_clock);
start <= 1;
while(done_cnt != `AUTOTB_TRANSACTION_NUM) begin
@(posedge AESL_clock);
end
start <= 0;
end
always @(AESL_done)
begin
if(done_cnt < `AUTOTB_TRANSACTION_NUM - 1)
continue = AESL_done;
else
continue = 0;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == `AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
assign ready = (ready_initial | AESL_done_delay);
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready_wire = (ready_initial | AESL_done_delay);
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt != `AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < `AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == `AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
// Write "[[[runtime]]]" and "[[[/runtime]]]" for output-only transactor
initial begin : write_output_transactor_c_runtime_process
integer fp;
fp = $fopen(`AUTOTB_TVOUT_c_out_wrapc, "w");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_c_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait(done_cnt == `AUTOTB_TRANSACTION_NUM)
repeat(2) @(posedge AESL_clock);
# 0.2;
fp = $fopen(`AUTOTB_TVOUT_c_out_wrapc, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_c_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_clk_counter <= 0;
end
else begin
AESL_clk_counter = AESL_clk_counter + 1;
end
end
always @ (posedge AESL_clock or negedge AESL_reset) begin
if(AESL_reset === 0)
begin
AESL_mLatCnterOut_addr = 0;
AESL_mLatCnterOut[AESL_mLatCnterOut_addr] = AESL_clk_counter + 1;
end
else if (AESL_done && AESL_mLatCnterOut_addr < `AUTOTB_TRANSACTION_NUM + 1) begin
AESL_mLatCnterOut[AESL_mLatCnterOut_addr] = AESL_clk_counter;
AESL_mLatCnterOut_addr = AESL_mLatCnterOut_addr + 1;
end
end
always @ (posedge AESL_clock or negedge AESL_reset) begin
if(AESL_reset === 0)
begin
AESL_mLatCnterIn_addr = 0;
end
else if (AESL_slave_write_start_finish && AESL_mLatCnterIn_addr < `AUTOTB_TRANSACTION_NUM + 1) begin
AESL_mLatCnterIn[AESL_mLatCnterIn_addr] = AESL_clk_counter;
AESL_mLatCnterIn_addr = AESL_mLatCnterIn_addr + 1;
end
end
initial begin : performance_check
integer transaction_counter;
integer i;
integer fp;
integer latthistime;
integer lattotal;
integer latmax;
integer latmin;
integer thrthistime;
integer thrtotal;
integer thrmax;
integer thrmin;
integer lataver;
integer thraver;
reg [31 : 0] lat_array [0 : `AUTOTB_TRANSACTION_NUM];
reg [31 : 0] thr_array [0 : `AUTOTB_TRANSACTION_NUM];
i = 0;
lattotal = 0;
latmax = 0;
latmin = 32'h 7fffffff;
lataver = 0;
thrtotal = 0;
thrmax = 0;
thrmin = 32'h 7fffffff;
thraver = 0;
@(negedge AESL_clock);
@(posedge AESL_reset);
while (done_cnt != `AUTOTB_TRANSACTION_NUM) begin
@(posedge AESL_clock);
end
#0.001
latmax = 0;
latmin = 0;
lataver = 0;
thrmax = 0;
thrmin = 0;
thraver = 0;
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latmax);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latmin);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", lataver);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", latmax);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", latmin);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", lataver);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay (fp,"%20s%16s%16s","","latency","interval");
for (i = 0; i < AESL_mLatCnterOut_addr; i = i + 1) begin
$fdisplay (fp,"transaction%8d: 0 0",i );
end
$fclose(fp);
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2017 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation "[ ]" := nil (format "[ ]") : list_scope.
Notation "[ x ]" := (cons x nil) : list_scope.
Notation "[ x ; y ; .. ; z ]" := (cons x (cons y .. (cons z nil) ..)) : list_scope.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y nil) ..) (compat "8.4") : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Generic facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H as H H0.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H as H H0; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes.
Hint Immediate app_eq_nil: datatypes.
Hint Resolve app_eq_unit app_inj_tail: datatypes.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. now injection H as ->.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(******************************************)
(** ** Counting occurrences of an element *)
(******************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
clear Hfinjective.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l'].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. now inversion_clear 1.
Qed.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. now inversion_clear 1.
+ right. now inversion_clear 1.
Qed.
End One_predicate.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
apply Exists_Forall_neg; trivial.
intro x. destruct (Pdec x); [now left|now right].
Qed.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists.
Hint Constructors Forall.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: trace_buffer.v
// Description: Trace port buffer
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7
// |
// --trace_buffer
//-----------------------------------------------------------------------------
module processing_system7_v5_5_trace_buffer #
(
parameter integer FIFO_SIZE = 128,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_DELAY_CLKS = 12
)
(
input wire TRACE_CLK,
input wire RST,
input wire TRACE_VALID_IN,
input wire [3:0] TRACE_ATID_IN,
input wire [31:0] TRACE_DATA_IN,
output wire TRACE_VALID_OUT,
output wire [3:0] TRACE_ATID_OUT,
output wire [31:0] TRACE_DATA_OUT
);
//------------------------------------------------------------
// Architecture section
//------------------------------------------------------------
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
integer i;
integer temp_log;
begin
temp_log = 0;
for(i=bit_depth; i > 0; i = i>>1)
clogb2 = temp_log;
temp_log=temp_log+1;
end
endfunction
localparam DEPTH = clogb2(FIFO_SIZE-1);
wire [31:0] reset_zeros;
reg [31:0] trace_pedge; // write enable for FIFO
reg [31:0] ti;
reg [31:0] tom;
reg [3:0] atid;
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
reg [4:0] dly_ctr;
reg [DEPTH-1:0] fifo_wp;
reg [DEPTH-1:0] fifo_rp;
reg fifo_re;
wire fifo_empty;
wire fifo_full;
reg fifo_full_reg;
assign reset_zeros = 32'h0;
// Pipeline Stage for Traceport ATID ports
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
atid <= reset_zeros;
end
else begin
atid <= TRACE_ATID_IN;
end
end
assign TRACE_ATID_OUT = atid;
/////////////////////////////////////////////
// Generate FIFO data based on TRACE_VALID_IN
/////////////////////////////////////////////
generate
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
/////////////////////////////////////////////
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(TRACE_VALID_IN ) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
/////////////////////////////////////////////
// Generate FIFO data based on data edge
/////////////////////////////////////////////
end else begin : gen_data_edge_detector
/////////////////////////////////////////////
// purpose: check for pos edge on any trace input
always @(posedge TRACE_CLK) begin
// process pedge_ti
// rising clock edge
if((RST == 1'b1)) begin
ti <= reset_zeros;
trace_pedge <= reset_zeros;
end
else begin
ti <= TRACE_DATA_IN;
trace_pedge <= (~ti & TRACE_DATA_IN);
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
// posedge only
end
end
// memory update process
// Update memory when positive edge detected and FIFO not full
always @(posedge TRACE_CLK) begin
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
trace_fifo[fifo_wp] <= trace_pedge;
end
end
// fifo write pointer
always @(posedge TRACE_CLK) begin
// process
if(RST == 1'b1) begin
fifo_wp <= {DEPTH{1'b0}};
end
else if(|(trace_pedge) == 1'b1) begin
if(fifo_wp == (FIFO_SIZE - 1)) begin
if (fifo_empty) begin
fifo_wp <= {DEPTH{1'b0}};
end
end
else begin
fifo_wp <= fifo_wp + 1;
end
end
end
end
endgenerate
always @(posedge TRACE_CLK) begin
tom <= trace_fifo[fifo_rp] ;
end
// // fifo write pointer
// always @(posedge TRACE_CLK) begin
// // process
// if(RST == 1'b1) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else if(|(trace_pedge) == 1'b1) begin
// if(fifo_wp == (FIFO_SIZE - 1)) begin
// fifo_wp <= {DEPTH{1'b0}};
// end
// else begin
// fifo_wp <= fifo_wp + 1;
// end
// end
// end
// fifo read pointer update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_rp <= {DEPTH{1'b0}};
fifo_re <= 1'b0;
end
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
fifo_re <= 1'b1;
if(fifo_rp == (FIFO_SIZE - 1)) begin
fifo_rp <= {DEPTH{1'b0}};
end
else begin
fifo_rp <= fifo_rp + 1;
end
end
else begin
fifo_re <= 1'b0;
end
end
// delay counter update
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
dly_ctr <= 5'h0;
end
else if (fifo_re == 1'b1) begin
dly_ctr <= C_DELAY_CLKS-1;
end
else if(dly_ctr != 5'h0) begin
dly_ctr <= dly_ctr - 1;
end
end
// fifo empty update
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
// fifo full update
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
always @(posedge TRACE_CLK) begin
if(RST == 1'b1) begin
fifo_full_reg <= 1'b0;
end
else if (fifo_empty) begin
fifo_full_reg <= 1'b0;
end else begin
fifo_full_reg <= fifo_full;
end
end
// always @(posedge TRACE_CLK) begin
// if(RST == 1'b1) begin
// fifo_full_reg <= 1'b0;
// end
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
// fifo_full_reg <= 1'b1;
// end
// else begin
// fifo_full_reg <= 1'b0;
// end
// end
//
assign TRACE_DATA_OUT = tom;
assign TRACE_VALID_OUT = fifo_re;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001d),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000100000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000004),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//----------------------------------------------------------------------
// my6502mc: my6502 mpu microcode decoder
//----------------------------------------------------------------------
module my6502mc (
input [7:0] opcode, // opcode
input [2:0] cyc_cnt, // execution cycle count
output reg [55:0] opc_inst, // opcode decode by instruction
output reg [7:0] opc_flag, // modified flag indicator
output opc_src_a_ar, // alu source a indicator (a reg)
output opc_src_a_xr, // alu source a indicator (x reg)
output opc_src_a_yr, // alu source a indicator (y reg)
output opc_src_a_sp, // alu source a indicator (sp reg)
output opc_src_a_ps, // alu source a indicator (ps reg)
output opc_src_a_din, // alu source a indicator (din)
output opc_src_b_din, // alu source b indicator (din)
output opc_dst_ar, // alu destination indicator (a reg)
output opc_dst_xr, // alu destination indicator (x reg)
output opc_dst_yr, // alu destination indicator (y reg)
output opc_dst_sp, // alu destination indicator (sp reg)
output opc_dst_ps, // alu destination indicator (ps reg)
output opc_dst_dout, // alu destination indicator (dout)
output mc_fetch_en, // opcode fetch enable
output mc_din_le, // data input latch enable
output mc_pc_chg, // change program counter value
output mc_addr_pc, // output program counter value
output mc_addr_zp, // output zero page address
output mc_addr_abs, // output absolute address
output mc_addr_sp, // output stack address
output mc_addr_vl, // output interrupt vector(low) address
output mc_addr_vh, // output interrupt vector(high) address
output mc_dout_pch, // output pc value(high) to data bus
output mc_dout_pcl, // output pc value(low) to data bus
output mc_oe_next, // set output enable in next cycle
output mc_alu_inst_op, // use alu for instruction operation
output mc_alu_add_xr, // add x to input data
output mc_alu_add_yr, // add y to input data
output mc_alu_add_z, // add 0 to input data
output mc_alu_inc_din, // increment input data
output mc_alu_inc_reg, // increment saved data
output mc_alu_inc_sp, // increment stack pointer value
output mc_alu_dec_sp, // decrement stack pointer value
output mc_brk_if_set, // interrupt i flag setting timing
output mc_br_chk // branch condition check timing
);
//----------------------------------------------------------------------
// internal regs and nets
//----------------------------------------------------------------------
// number of decoded instructions
parameter NUM_OF_INST = 56;
// internal nets
reg [12:0] src_dst;
reg [15:0] mc_exec;
//----------------------------------------------------------------------
// instruction bit position
//----------------------------------------------------------------------
parameter I_ADC = 0;
parameter I_AND = 1;
parameter I_ASL = 2;
parameter I_BCC = 3;
parameter I_BCS = 4;
parameter I_BEQ = 5;
parameter I_BIT = 6;
parameter I_BMI = 7;
parameter I_BNE = 8;
parameter I_BPL = 9;
parameter I_BRK = 10;
parameter I_BVC = 11;
parameter I_BVS = 12;
parameter I_CLC = 13;
parameter I_CLD = 14;
parameter I_CLI = 15;
parameter I_CLV = 16;
parameter I_CMP = 17;
parameter I_CPX = 18;
parameter I_CPY = 19;
parameter I_DEC = 20;
parameter I_DEX = 21;
parameter I_DEY = 22;
parameter I_EOR = 23;
parameter I_INC = 24;
parameter I_INX = 25;
parameter I_INY = 26;
parameter I_JMP = 27;
parameter I_JSR = 28;
parameter I_LDA = 29;
parameter I_LDX = 30;
parameter I_LDY = 31;
parameter I_LSR = 32;
parameter I_NOP = 33;
parameter I_ORA = 34;
parameter I_PHA = 35;
parameter I_PHP = 36;
parameter I_PLA = 37;
parameter I_PLP = 38;
parameter I_ROL = 39;
parameter I_ROR = 40;
parameter I_RTI = 41;
parameter I_RTS = 42;
parameter I_SBC = 43;
parameter I_SEC = 44;
parameter I_SED = 45;
parameter I_SEI = 46;
parameter I_STA = 47;
parameter I_STX = 48;
parameter I_STY = 49;
parameter I_TAX = 50;
parameter I_TAY = 51;
parameter I_TSX = 52;
parameter I_TXA = 53;
parameter I_TXS = 54;
parameter I_TYA = 55;
//----------------------------------------------------------------------
// opcodes
//----------------------------------------------------------------------
parameter ADC_IMM = 8'h69;
parameter ADC_ZP = 8'h65;
parameter ADC_ZX = 8'h75;
parameter ADC_ABS = 8'h6D;
parameter ADC_AX = 8'h7D;
parameter ADC_AY = 8'h79;
parameter ADC_IX = 8'h61;
parameter ADC_IY = 8'h71;
parameter AND_IMM = 8'h29;
parameter AND_ZP = 8'h25;
parameter AND_ZX = 8'h35;
parameter AND_ABS = 8'h2D;
parameter AND_AX = 8'h3D;
parameter AND_AY = 8'h39;
parameter AND_IX = 8'h21;
parameter AND_IY = 8'h31;
parameter ASL_ACC = 8'h0A;
parameter ASL_ZP = 8'h06;
parameter ASL_ZX = 8'h16;
parameter ASL_ABS = 8'h0E;
parameter ASL_AX = 8'h1E;
parameter BCC = 8'h90;
parameter BCS = 8'hB0;
parameter BEQ = 8'hF0;
parameter BIT_ZP = 8'h24;
parameter BIT_ABS = 8'h2C;
parameter BMI = 8'h30;
parameter BNE = 8'hD0;
parameter BPL = 8'h10;
parameter BRK = 8'h00;
parameter BVC = 8'h50;
parameter BVS = 8'h70;
parameter CLC = 8'h18;
parameter CLD = 8'hD8;
parameter CLI = 8'h58;
parameter CLV = 8'hB8;
parameter CMP_IMM = 8'hC9;
parameter CMP_ZP = 8'hC5;
parameter CMP_ZX = 8'hD5;
parameter CMP_ABS = 8'hCD;
parameter CMP_AX = 8'hDD;
parameter CMP_AY = 8'hD9;
parameter CMP_IX = 8'hC1;
parameter CMP_IY = 8'hD1;
parameter CPX_IMM = 8'hE0;
parameter CPX_ZP = 8'hE4;
parameter CPX_ABS = 8'hEC;
parameter CPY_IMM = 8'hC0;
parameter CPY_ZP = 8'hC4;
parameter CPY_ABS = 8'hCC;
parameter DEC_ZP = 8'hC6;
parameter DEC_ZX = 8'hD6;
parameter DEC_ABS = 8'hCE;
parameter DEC_AX = 8'hDE;
parameter DEX = 8'hCA;
parameter DEY = 8'h88;
parameter EOR_IMM = 8'h49;
parameter EOR_ZP = 8'h45;
parameter EOR_ZX = 8'h55;
parameter EOR_ABS = 8'h4D;
parameter EOR_AX = 8'h5D;
parameter EOR_AY = 8'h59;
parameter EOR_IX = 8'h41;
parameter EOR_IY = 8'h51;
parameter INC_ZP = 8'hE6;
parameter INC_ZX = 8'hF6;
parameter INC_ABS = 8'hEE;
parameter INC_AX = 8'hFE;
parameter INX = 8'hE8;
parameter INY = 8'hC8;
parameter JMP_ABS = 8'h4C;
parameter JMP_IND = 8'h6C;
parameter JSR_ABS = 8'h20;
parameter LDA_IMM = 8'hA9;
parameter LDA_ZP = 8'hA5;
parameter LDA_ZX = 8'hB5;
parameter LDA_ABS = 8'hAD;
parameter LDA_AX = 8'hBD;
parameter LDA_AY = 8'hB9;
parameter LDA_IX = 8'hA1;
parameter LDA_IY = 8'hB1;
parameter LDX_IMM = 8'hA2;
parameter LDX_ZP = 8'hA6;
parameter LDX_ZY = 8'hB6;
parameter LDX_ABS = 8'hAE;
parameter LDX_AY = 8'hBE;
parameter LDY_IMM = 8'hA0;
parameter LDY_ZP = 8'hA4;
parameter LDY_ZX = 8'hB4;
parameter LDY_ABS = 8'hAC;
parameter LDY_AX = 8'hBC;
parameter LSR_ACC = 8'h4A;
parameter LSR_ZP = 8'h46;
parameter LSR_ZX = 8'h56;
parameter LSR_ABS = 8'h4E;
parameter LSR_AX = 8'h5E;
parameter NOP = 8'hEA;
parameter ORA_IMM = 8'h09;
parameter ORA_ZP = 8'h05;
parameter ORA_ZX = 8'h15;
parameter ORA_ABS = 8'h0D;
parameter ORA_AX = 8'h1D;
parameter ORA_AY = 8'h19;
parameter ORA_IX = 8'h01;
parameter ORA_IY = 8'h11;
parameter PHA = 8'h48;
parameter PHP = 8'h08;
parameter PLA = 8'h68;
parameter PLP = 8'h28;
parameter ROL_ACC = 8'h2A;
parameter ROL_ZP = 8'h26;
parameter ROL_ZX = 8'h36;
parameter ROL_ABS = 8'h2E;
parameter ROL_AX = 8'h3E;
parameter ROR_ACC = 8'h6A;
parameter ROR_ZP = 8'h66;
parameter ROR_ZX = 8'h76;
parameter ROR_ABS = 8'h6E;
parameter ROR_AX = 8'h7E;
parameter RTI = 8'h40;
parameter RTS = 8'h60;
parameter SBC_IMM = 8'hE9;
parameter SBC_ZP = 8'hE5;
parameter SBC_ZX = 8'hF5;
parameter SBC_ABS = 8'hED;
parameter SBC_AX = 8'hFD;
parameter SBC_AY = 8'hF9;
parameter SBC_IX = 8'hE1;
parameter SBC_IY = 8'hF1;
parameter SEC = 8'h38;
parameter SED = 8'hF8;
parameter SEI = 8'h78;
parameter STA_ZP = 8'h85;
parameter STA_ZX = 8'h95;
parameter STA_ABS = 8'h8D;
parameter STA_AX = 8'h9D;
parameter STA_AY = 8'h99;
parameter STA_IX = 8'h81;
parameter STA_IY = 8'h91;
parameter STX_ZP = 8'h86;
parameter STX_ZY = 8'h96;
parameter STX_ABS = 8'h8E;
parameter STY_ZP = 8'h84;
parameter STY_ZX = 8'h94;
parameter STY_ABS = 8'h8C;
parameter TAX = 8'hAA;
parameter TAY = 8'hA8;
parameter TSX = 8'hBA;
parameter TXA = 8'h8A;
parameter TXS = 8'h9A;
parameter TYA = 8'h98;
//----------------------------------------------------------------------
// opcode decode by instruction
//----------------------------------------------------------------------
always @* begin
opc_inst = {NUM_OF_INST{1'b0}};
case (opcode)
ADC_IMM : opc_inst[I_ADC] = 1'b1;
ADC_ZP : opc_inst[I_ADC] = 1'b1;
ADC_ZX : opc_inst[I_ADC] = 1'b1;
ADC_ABS : opc_inst[I_ADC] = 1'b1;
ADC_AX : opc_inst[I_ADC] = 1'b1;
ADC_AY : opc_inst[I_ADC] = 1'b1;
ADC_IX : opc_inst[I_ADC] = 1'b1;
ADC_IY : opc_inst[I_ADC] = 1'b1;
AND_IMM : opc_inst[I_AND] = 1'b1;
AND_ZP : opc_inst[I_AND] = 1'b1;
AND_ZX : opc_inst[I_AND] = 1'b1;
AND_ABS : opc_inst[I_AND] = 1'b1;
AND_AX : opc_inst[I_AND] = 1'b1;
AND_AY : opc_inst[I_AND] = 1'b1;
AND_IX : opc_inst[I_AND] = 1'b1;
AND_IY : opc_inst[I_AND] = 1'b1;
ASL_ACC : opc_inst[I_ASL] = 1'b1;
ASL_ZP : opc_inst[I_ASL] = 1'b1;
ASL_ZX : opc_inst[I_ASL] = 1'b1;
ASL_ABS : opc_inst[I_ASL] = 1'b1;
ASL_AX : opc_inst[I_ASL] = 1'b1;
BCC : opc_inst[I_BCC] = 1'b1;
BCS : opc_inst[I_BCS] = 1'b1;
BEQ : opc_inst[I_BEQ] = 1'b1;
BIT_ZP : opc_inst[I_BIT] = 1'b1;
BIT_ABS : opc_inst[I_BIT] = 1'b1;
BMI : opc_inst[I_BMI] = 1'b1;
BNE : opc_inst[I_BNE] = 1'b1;
BPL : opc_inst[I_BPL] = 1'b1;
BRK : opc_inst[I_BRK] = 1'b1;
BVC : opc_inst[I_BVC] = 1'b1;
BVS : opc_inst[I_BVS] = 1'b1;
CLC : opc_inst[I_CLC] = 1'b1;
CLD : opc_inst[I_CLD] = 1'b1;
CLI : opc_inst[I_CLI] = 1'b1;
CLV : opc_inst[I_CLV] = 1'b1;
CMP_IMM : opc_inst[I_CMP] = 1'b1;
CMP_ZP : opc_inst[I_CMP] = 1'b1;
CMP_ZX : opc_inst[I_CMP] = 1'b1;
CMP_ABS : opc_inst[I_CMP] = 1'b1;
CMP_AX : opc_inst[I_CMP] = 1'b1;
CMP_AY : opc_inst[I_CMP] = 1'b1;
CMP_IX : opc_inst[I_CMP] = 1'b1;
CMP_IY : opc_inst[I_CMP] = 1'b1;
CPX_IMM : opc_inst[I_CPX] = 1'b1;
CPX_ZP : opc_inst[I_CPX] = 1'b1;
CPX_ABS : opc_inst[I_CPX] = 1'b1;
CPY_IMM : opc_inst[I_CPY] = 1'b1;
CPY_ZP : opc_inst[I_CPY] = 1'b1;
CPY_ABS : opc_inst[I_CPY] = 1'b1;
DEC_ZP : opc_inst[I_DEC] = 1'b1;
DEC_ZX : opc_inst[I_DEC] = 1'b1;
DEC_ABS : opc_inst[I_DEC] = 1'b1;
DEC_AX : opc_inst[I_DEC] = 1'b1;
DEX : opc_inst[I_DEX] = 1'b1;
DEY : opc_inst[I_DEY] = 1'b1;
EOR_IMM : opc_inst[I_EOR] = 1'b1;
EOR_ZP : opc_inst[I_EOR] = 1'b1;
EOR_ZX : opc_inst[I_EOR] = 1'b1;
EOR_ABS : opc_inst[I_EOR] = 1'b1;
EOR_AX : opc_inst[I_EOR] = 1'b1;
EOR_AY : opc_inst[I_EOR] = 1'b1;
EOR_IX : opc_inst[I_EOR] = 1'b1;
EOR_IY : opc_inst[I_EOR] = 1'b1;
INC_ZP : opc_inst[I_INC] = 1'b1;
INC_ZX : opc_inst[I_INC] = 1'b1;
INC_ABS : opc_inst[I_INC] = 1'b1;
INC_AX : opc_inst[I_INC] = 1'b1;
INX : opc_inst[I_INX] = 1'b1;
INY : opc_inst[I_INY] = 1'b1;
JMP_ABS : opc_inst[I_JMP] = 1'b1;
JMP_IND : opc_inst[I_JMP] = 1'b1;
JSR_ABS : opc_inst[I_JSR] = 1'b1;
LDA_IMM : opc_inst[I_LDA] = 1'b1;
LDA_ZP : opc_inst[I_LDA] = 1'b1;
LDA_ZX : opc_inst[I_LDA] = 1'b1;
LDA_ABS : opc_inst[I_LDA] = 1'b1;
LDA_AX : opc_inst[I_LDA] = 1'b1;
LDA_AY : opc_inst[I_LDA] = 1'b1;
LDA_IX : opc_inst[I_LDA] = 1'b1;
LDA_IY : opc_inst[I_LDA] = 1'b1;
LDX_IMM : opc_inst[I_LDX] = 1'b1;
LDX_ZP : opc_inst[I_LDX] = 1'b1;
LDX_ZY : opc_inst[I_LDX] = 1'b1;
LDX_ABS : opc_inst[I_LDX] = 1'b1;
LDX_AY : opc_inst[I_LDX] = 1'b1;
LDY_IMM : opc_inst[I_LDY] = 1'b1;
LDY_ZP : opc_inst[I_LDY] = 1'b1;
LDY_ZX : opc_inst[I_LDY] = 1'b1;
LDY_ABS : opc_inst[I_LDY] = 1'b1;
LDY_AX : opc_inst[I_LDY] = 1'b1;
LSR_ACC : opc_inst[I_LSR] = 1'b1;
LSR_ZP : opc_inst[I_LSR] = 1'b1;
LSR_ZX : opc_inst[I_LSR] = 1'b1;
LSR_ABS : opc_inst[I_LSR] = 1'b1;
LSR_AX : opc_inst[I_LSR] = 1'b1;
NOP : opc_inst[I_NOP] = 1'b1;
ORA_IMM : opc_inst[I_ORA] = 1'b1;
ORA_ZP : opc_inst[I_ORA] = 1'b1;
ORA_ZX : opc_inst[I_ORA] = 1'b1;
ORA_ABS : opc_inst[I_ORA] = 1'b1;
ORA_AX : opc_inst[I_ORA] = 1'b1;
ORA_AY : opc_inst[I_ORA] = 1'b1;
ORA_IX : opc_inst[I_ORA] = 1'b1;
ORA_IY : opc_inst[I_ORA] = 1'b1;
PHA : opc_inst[I_PHA] = 1'b1;
PHP : opc_inst[I_PHP] = 1'b1;
PLA : opc_inst[I_PLA] = 1'b1;
PLP : opc_inst[I_PLP] = 1'b1;
ROL_ACC : opc_inst[I_ROL] = 1'b1;
ROL_ZP : opc_inst[I_ROL] = 1'b1;
ROL_ZX : opc_inst[I_ROL] = 1'b1;
ROL_ABS : opc_inst[I_ROL] = 1'b1;
ROL_AX : opc_inst[I_ROL] = 1'b1;
ROR_ACC : opc_inst[I_ROR] = 1'b1;
ROR_ZP : opc_inst[I_ROR] = 1'b1;
ROR_ZX : opc_inst[I_ROR] = 1'b1;
ROR_ABS : opc_inst[I_ROR] = 1'b1;
ROR_AX : opc_inst[I_ROR] = 1'b1;
RTI : opc_inst[I_RTI] = 1'b1;
RTS : opc_inst[I_RTS] = 1'b1;
SBC_IMM : opc_inst[I_SBC] = 1'b1;
SBC_ZP : opc_inst[I_SBC] = 1'b1;
SBC_ZX : opc_inst[I_SBC] = 1'b1;
SBC_ABS : opc_inst[I_SBC] = 1'b1;
SBC_AX : opc_inst[I_SBC] = 1'b1;
SBC_AY : opc_inst[I_SBC] = 1'b1;
SBC_IX : opc_inst[I_SBC] = 1'b1;
SBC_IY : opc_inst[I_SBC] = 1'b1;
SEC : opc_inst[I_SEC] = 1'b1;
SED : opc_inst[I_SED] = 1'b1;
SEI : opc_inst[I_SEI] = 1'b1;
STA_ZP : opc_inst[I_STA] = 1'b1;
STA_ZX : opc_inst[I_STA] = 1'b1;
STA_ABS : opc_inst[I_STA] = 1'b1;
STA_AX : opc_inst[I_STA] = 1'b1;
STA_AY : opc_inst[I_STA] = 1'b1;
STA_IX : opc_inst[I_STA] = 1'b1;
STA_IY : opc_inst[I_STA] = 1'b1;
STX_ZP : opc_inst[I_STX] = 1'b1;
STX_ZY : opc_inst[I_STX] = 1'b1;
STX_ABS : opc_inst[I_STX] = 1'b1;
STY_ZP : opc_inst[I_STY] = 1'b1;
STY_ZX : opc_inst[I_STY] = 1'b1;
STY_ABS : opc_inst[I_STY] = 1'b1;
TAX : opc_inst[I_TAX] = 1'b1;
TAY : opc_inst[I_TAY] = 1'b1;
TSX : opc_inst[I_TSX] = 1'b1;
TXA : opc_inst[I_TXA] = 1'b1;
TXS : opc_inst[I_TXS] = 1'b1;
TYA : opc_inst[I_TYA] = 1'b1;
endcase
end
//----------------------------------------------------------------------
// alu source/dest and modified flag decoder
//----------------------------------------------------------------------
// alu source/dest indicator assignments
assign opc_src_a_ar = src_dst[12]; // alu source a indicator (a reg)
assign opc_src_a_xr = src_dst[11]; // alu source a indicator (x reg)
assign opc_src_a_yr = src_dst[10]; // alu source a indicator (y reg)
assign opc_src_a_sp = src_dst[ 9]; // alu source a indicator (sp reg)
assign opc_src_a_ps = src_dst[ 8]; // alu source a indicator (ps reg)
assign opc_src_a_din = src_dst[ 7]; // alu source a indicator (din)
assign opc_src_b_din = src_dst[ 6]; // alu source b indicator (din)
assign opc_dst_ar = src_dst[ 5]; // alu destination indicator (a reg)
assign opc_dst_xr = src_dst[ 4]; // alu destination indicator (x reg)
assign opc_dst_yr = src_dst[ 3]; // alu destination indicator (y reg)
assign opc_dst_sp = src_dst[ 2]; // alu destination indicator (sp reg)
assign opc_dst_ps = src_dst[ 1]; // alu destination indicator (ps reg)
assign opc_dst_dout = src_dst[ 0]; // alu destination indicator (dout)
// alu source/dest and modified flag decoder
always @* begin
case (opcode)
// AXYSPD D AXYSPD NV-B DIZC
ADC_IMM : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_ZP : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_ZX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_ABS : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_AX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_AY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_IX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
ADC_IY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
// AXYSPD D AXYSPD NV-B DIZC
AND_IMM : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_ZP : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_ZX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_ABS : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_AX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_AY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_IX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
AND_IY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
ASL_ACC : {src_dst, opc_flag} = {13'b 100000_0_100000, 8'b 1000_0011};
ASL_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ASL_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ASL_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ASL_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
BCC : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BCS : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BEQ : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BMI : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BNE : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BPL : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BVC : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
BVS : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
BIT_ZP : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1100_0010};
BIT_ABS : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1100_0010};
// AXYSPD D AXYSPD NV-B DIZC
BRK : {src_dst, opc_flag} = {13'b 000010_0_000001, 8'b 0001_0100};
// AXYSPD D AXYSPD NV-B DIZC
CLC : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0001};
CLD : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_1000};
CLI : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0100};
CLV : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0100_0000};
// AXYSPD D AXYSPD NV-B DIZC
CMP_IMM : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_ZP : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_ZX : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_ABS : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_AX : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_AY : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_IX : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
CMP_IY : {src_dst, opc_flag} = {13'b 100000_1_000000, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
CPX_IMM : {src_dst, opc_flag} = {13'b 010000_1_000000, 8'b 1000_0011};
CPX_ZP : {src_dst, opc_flag} = {13'b 010000_1_000000, 8'b 1000_0011};
CPX_ABS : {src_dst, opc_flag} = {13'b 010000_1_000000, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
CPY_IMM : {src_dst, opc_flag} = {13'b 001000_1_000000, 8'b 1000_0011};
CPY_ZP : {src_dst, opc_flag} = {13'b 001000_1_000000, 8'b 1000_0011};
CPY_ABS : {src_dst, opc_flag} = {13'b 001000_1_000000, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
DEC_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
DEC_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
DEC_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
DEC_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
DEX : {src_dst, opc_flag} = {13'b 010000_0_010000, 8'b 1000_0010};
DEY : {src_dst, opc_flag} = {13'b 001000_0_001000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
EOR_IMM : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_ZP : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_ZX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_ABS : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_AX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_AY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_IX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
EOR_IY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
INC_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
INC_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
INC_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
INC_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
INX : {src_dst, opc_flag} = {13'b 010000_0_010000, 8'b 1000_0010};
INY : {src_dst, opc_flag} = {13'b 001000_0_001000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
JMP_ABS : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
JMP_IND : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
JSR_ABS : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
LDA_IMM : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_ZP : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_ZX : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_ABS : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_AX : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_AY : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_IX : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
LDA_IY : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
LDX_IMM : {src_dst, opc_flag} = {13'b 000000_1_010000, 8'b 1000_0010};
LDX_ZP : {src_dst, opc_flag} = {13'b 000000_1_010000, 8'b 1000_0010};
LDX_ZY : {src_dst, opc_flag} = {13'b 000000_1_010000, 8'b 1000_0010};
LDX_ABS : {src_dst, opc_flag} = {13'b 000000_1_010000, 8'b 1000_0010};
LDX_AY : {src_dst, opc_flag} = {13'b 000000_1_010000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
LDY_IMM : {src_dst, opc_flag} = {13'b 000000_1_001000, 8'b 1000_0010};
LDY_ZP : {src_dst, opc_flag} = {13'b 000000_1_001000, 8'b 1000_0010};
LDY_ZX : {src_dst, opc_flag} = {13'b 000000_1_001000, 8'b 1000_0010};
LDY_ABS : {src_dst, opc_flag} = {13'b 000000_1_001000, 8'b 1000_0010};
LDY_AX : {src_dst, opc_flag} = {13'b 000000_1_001000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
LSR_ACC : {src_dst, opc_flag} = {13'b 100000_0_100000, 8'b 1000_0011};
LSR_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
LSR_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
LSR_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
LSR_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
NOP : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
ORA_IMM : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_ZP : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_ZX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_ABS : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_AX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_AY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_IX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
ORA_IY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
PHA : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
PHP : {src_dst, opc_flag} = {13'b 000010_0_000001, 8'b 0000_0000};
PLA : {src_dst, opc_flag} = {13'b 000000_1_100000, 8'b 1000_0010};
PLP : {src_dst, opc_flag} = {13'b 000000_1_000010, 8'b 1111_1111};
// AXYSPD D AXYSPD NV-B DIZC
ROL_ACC : {src_dst, opc_flag} = {13'b 100000_0_100000, 8'b 1000_0011};
ROL_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROL_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROL_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROL_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
ROR_ACC : {src_dst, opc_flag} = {13'b 100000_0_100000, 8'b 1000_0011};
ROR_ZP : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROR_ZX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROR_ABS : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
ROR_AX : {src_dst, opc_flag} = {13'b 000001_0_000001, 8'b 1000_0011};
// AXYSPD D AXYSPD NV-B DIZC
RTI : {src_dst, opc_flag} = {13'b 000000_1_000010, 8'b 1111_1111};
// AXYSPD D AXYSPD NV-B DIZC
RTS : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
SBC_IMM : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_ZP : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_ZX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_ABS : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_AX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_AY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_IX : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
SBC_IY : {src_dst, opc_flag} = {13'b 100000_1_100000, 8'b 1100_0011};
// AXYSPD D AXYSPD NV-B DIZC
SEC : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0001};
SED : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_1000};
SEI : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0100};
// AXYSPD D AXYSPD NV-B DIZC
STA_ZP : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_ZX : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_ABS : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_AX : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_AY : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_IX : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
STA_IY : {src_dst, opc_flag} = {13'b 100000_0_000001, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
STX_ZP : {src_dst, opc_flag} = {13'b 010000_0_000001, 8'b 0000_0000};
STX_ZY : {src_dst, opc_flag} = {13'b 010000_0_000001, 8'b 0000_0000};
STX_ABS : {src_dst, opc_flag} = {13'b 010000_0_000001, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
STY_ZP : {src_dst, opc_flag} = {13'b 001000_0_000001, 8'b 0000_0000};
STY_ZX : {src_dst, opc_flag} = {13'b 001000_0_000001, 8'b 0000_0000};
STY_ABS : {src_dst, opc_flag} = {13'b 001000_0_000001, 8'b 0000_0000};
// AXYSPD D AXYSPD NV-B DIZC
TAX : {src_dst, opc_flag} = {13'b 100000_0_010000, 8'b 1000_0010};
TAY : {src_dst, opc_flag} = {13'b 100000_0_001000, 8'b 1000_0010};
TSX : {src_dst, opc_flag} = {13'b 000100_0_010000, 8'b 1000_0010};
TXA : {src_dst, opc_flag} = {13'b 010000_0_100000, 8'b 1000_0010};
TXS : {src_dst, opc_flag} = {13'b 010000_0_000100, 8'b 0000_0000};
TYA : {src_dst, opc_flag} = {13'b 001000_0_100000, 8'b 1000_0010};
// AXYSPD D AXYSPD NV-B DIZC
default : {src_dst, opc_flag} = {13'b 000000_0_000000, 8'b 0000_0000};
endcase
end
//----------------------------------------------------------------------
// execution timing decoder
//----------------------------------------------------------------------
// microcode assignments
assign mc_fetch_en = mc_exec[15]; // opcode fetch enable
assign mc_din_le = mc_exec[14]; // data input latch enable
assign mc_pc_chg = mc_exec[13]; // change program counter value
assign mc_addr_pc = mc_exec[12]; // output program counter value
assign mc_addr_zp = mc_exec[11]; // output zero page address
assign mc_addr_abs = mc_exec[10]; // output absolute address
assign mc_addr_sp = mc_exec[ 9]; // output stack address
assign mc_oe_next = mc_exec[ 8]; // set output enable in next cycle
assign mc_alu_inst_op = mc_exec[ 7]; // use alu for instruction operation
assign mc_alu_add_xr = mc_exec[ 6]; // add x to input data
assign mc_alu_add_yr = mc_exec[ 5]; // add y to input data
assign mc_alu_add_z = mc_exec[ 4]; // add 0 to input data
assign mc_alu_inc_din = mc_exec[ 3]; // increment input data
assign mc_alu_inc_reg = mc_exec[ 2]; // increment saved data
assign mc_alu_inc_sp = mc_exec[ 1]; // increment stack pointer value
assign mc_alu_dec_sp = mc_exec[ 0]; // decrement stack pointer value
// execution timing decoder
always @* begin
mc_exec = {16{1'b0}};
case (opcode)
//--------------------------------------------------
// accumulator
//--------------------------------------------------
ASL_ACC,
LSR_ACC,
ROL_ACC,
ROR_ACC:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0000; // PC+1 -- R - -
3'd1: mc_exec = 16'b 101_1000_0_1000_0000; // PC+1 OP R a 0
endcase
//--------------------------------------------------
// immediate
//--------------------------------------------------
AND_IMM,
ORA_IMM,
EOR_IMM,
ADC_IMM,
SBC_IMM,
CMP_IMM,
CPX_IMM,
CPY_IMM,
LDA_IMM,
LDX_IMM,
LDY_IMM:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 DATA R - -
3'd1: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R *a d
endcase
//--------------------------------------------------
// zero page
//--------------------------------------------------
AND_ZP,
ORA_ZP,
EOR_ZP,
ADC_ZP,
SBC_ZP,
CMP_ZP,
CPX_ZP,
CPY_ZP,
LDA_ZP,
LDX_ZP,
LDY_ZP,
BIT_ZP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0100_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 011_1000_0_0000_0000; // ZA DATA R - -
3'd2: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R *a d
endcase
STA_ZP,
STX_ZP,
STY_ZP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0100_1_1000_0000; // PC+1 ZA R *a 0
3'd1: mc_exec = 16'b 001_1000_0_0000_0000; // ZA DATA W - -
3'd2: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
ASL_ZP,
LSR_ZP,
ROL_ZP,
ROR_ZP,
INC_ZP,
DEC_ZP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0100_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 010_0000_0_0000_0000; // ZA DATA R - -
3'd2: mc_exec = 16'b 000_0000_1_1000_0000; // ZA -- R d 0
3'd3: mc_exec = 16'b 001_1000_0_0000_0000; // ZA DATA W - -
3'd4: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
//--------------------------------------------------
// zero page, x
//--------------------------------------------------
AND_ZX,
ORA_ZX,
EOR_ZX,
ADC_ZX,
SBC_ZX,
CMP_ZX,
LDA_ZX,
LDY_ZX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 000_0100_0_0100_0000; // PC+1 -- R x d
3'd2: mc_exec = 16'b 011_1000_0_0000_0000; // ZA+X DATA R - -
3'd3: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R *a d
endcase
STA_ZX,
STY_ZX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_1000_0000; // PC+1 ZA R *a 0
3'd1: mc_exec = 16'b 000_0100_1_0100_0000; // PC+1 -- R x d
3'd2: mc_exec = 16'b 001_1000_0_0000_0000; // ZA+X DATA W - -
3'd3: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
ASL_ZX,
LSR_ZX,
ROL_ZX,
ROR_ZX,
INC_ZX,
DEC_ZX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 000_0100_0_0100_0000; // PC+1 -- R x d
3'd2: mc_exec = 16'b 010_0000_0_0000_0000; // ZA+X DATA R - -
3'd3: mc_exec = 16'b 000_0000_1_1000_0000; // ZA+X -- R d 0
3'd4: mc_exec = 16'b 001_1000_0_0000_0000; // ZA+X DATA W - -
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
//--------------------------------------------------
// zero page, y
//--------------------------------------------------
LDX_ZY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 000_0100_0_0010_0000; // PC+1 -- R y d
3'd2: mc_exec = 16'b 011_1000_0_0000_0000; // ZA+Y DATA R - -
3'd3: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R 0 d
endcase
STX_ZY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_1000_0000; // PC+1 ZA R x 0
3'd1: mc_exec = 16'b 000_0100_1_0010_0000; // PC+1 -- R y d
3'd2: mc_exec = 16'b 001_1000_0_0000_0000; // ZA+Y DATA W - -
3'd3: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
//--------------------------------------------------
// absolute
//--------------------------------------------------
AND_ABS,
ORA_ABS,
EOR_ABS,
ADC_ABS,
SBC_ABS,
CMP_ABS,
CPX_ABS,
CPY_ABS,
LDA_ABS,
LDX_ABS,
LDY_ABS,
BIT_ABS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0001_0000; // PC+2 AH R 0 d
3'd2: mc_exec = 16'b 011_1000_0_0000_0000; // A DATA R - -
3'd3: mc_exec = 16'b 101_1000_0_1000_0000; // PC+3 OP R *a d
endcase
STA_ABS,
STX_ABS,
STY_ABS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_1000_0000; // PC+1 AL R *a 0
3'd1: mc_exec = 16'b 010_0010_1_0001_0000; // PC+2 AH R 0 d
3'd2: mc_exec = 16'b 001_1000_0_0000_0000; // A DATA W - -
3'd3: mc_exec = 16'b 101_1000_0_0000_0000; // PC+3 OP R - -
endcase
ASL_ABS,
LSR_ABS,
ROL_ABS,
ROR_ABS,
INC_ABS,
DEC_ABS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0001_0000; // PC+2 AH R 0 d
3'd2: mc_exec = 16'b 010_0000_0_0000_0000; // A DATA R - -
3'd3: mc_exec = 16'b 000_0000_1_1000_0000; // A -- R d 0
3'd4: mc_exec = 16'b 001_1000_0_0000_0000; // A DATA W - -
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // PC+3 OP R - -
endcase
JMP_ABS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 newPCL R - -
3'd1: mc_exec = 16'b 011_0010_0_0001_0000; // PC+2 newPCH R 0 d
3'd2: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
endcase
JSR_ABS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 newPCL R - -
3'd1: mc_exec = 16'b 000_0001_1_0000_0001; // PC+1 -- R s 0
3'd2: mc_exec = 16'b 000_0001_1_0000_0001; // S PCH W s 0
3'd3: mc_exec = 16'b 001_1000_0_0000_0000; // S-1 PCL+2 W - -
3'd4: mc_exec = 16'b 011_0010_0_0001_0000; // PC+2 newPCH R 0 d
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
endcase
//--------------------------------------------------
// absolute, x
//--------------------------------------------------
AND_AX,
ORA_AX,
EOR_AX,
ADC_AX,
SBC_AX,
CMP_AX,
LDA_AX,
LDY_AX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0100_0000; // PC+2 AH R x d
3'd2: mc_exec = 16'b 011_1000_0_0000_0000; // A+X DATA R - -
3'd3: mc_exec = 16'b 101_1000_0_1000_0000; // PC+3 OP R *a d
endcase
STA_AX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_1000_0000; // PC+1 AL R a 0
3'd1: mc_exec = 16'b 010_0010_1_0100_0000; // PC+2 AH R x d
3'd2: mc_exec = 16'b 001_1000_0_0000_0000; // A+X DATA W - -
3'd3: mc_exec = 16'b 101_1000_0_0000_0000; // PC+3 OP R - -
endcase
ASL_AX,
LSR_AX,
ROL_AX,
ROR_AX,
INC_AX,
DEC_AX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0100_0000; // PC+2 AH R x d
3'd2: mc_exec = 16'b 010_0000_0_0000_0000; // A+X DATA R - -
3'd3: mc_exec = 16'b 000_0000_1_1000_0000; // A+X -- R d 0
3'd4: mc_exec = 16'b 001_1000_0_0000_0000; // A+X DATA W - -
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // PC+3 OP R - -
endcase
//--------------------------------------------------
// absolute, y
//--------------------------------------------------
AND_AY,
ORA_AY,
EOR_AY,
ADC_AY,
SBC_AY,
CMP_AY,
LDA_AY,
LDX_AY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0010_0000; // PC+2 AH R y d
3'd2: mc_exec = 16'b 011_1000_0_0000_0000; // A+Y DATA R - -
3'd3: mc_exec = 16'b 101_1000_0_1000_0000; // PC+3 OP R *a d
endcase
STA_AY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_1000_0000; // PC+1 AL R a 0
3'd1: mc_exec = 16'b 010_0010_1_0010_0000; // PC+2 AH R y d
3'd2: mc_exec = 16'b 001_1000_0_0000_0000; // A+Y DATA W - -
3'd3: mc_exec = 16'b 101_1000_0_0000_0000; // PC+3 OP R - -
endcase
//--------------------------------------------------
// indirect, x
//--------------------------------------------------
AND_IX,
ORA_IX,
EOR_IX,
ADC_IX,
SBC_IX,
CMP_IX,
LDA_IX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 000_0100_0_0100_0000; // PC+1 -- R x d
3'd2: mc_exec = 16'b 010_0100_0_0000_0100; // ZA+X AL R r 0
3'd3: mc_exec = 16'b 010_0010_0_0001_0000; // ZA+X+1 AH R 0 d
3'd4: mc_exec = 16'b 011_1000_0_0000_0000; // A DATA R - -
3'd5: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R *a d
endcase
STA_IX:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0000_0_1000_0000; // PC+1 ZA R a 0
3'd1: mc_exec = 16'b 000_0100_0_0100_0000; // PC+1 -- R x d
3'd2: mc_exec = 16'b 010_0100_0_0000_0100; // ZA+X AL R r 0
3'd3: mc_exec = 16'b 010_0010_1_0001_0000; // ZA+X+1 AH R 0 d
3'd4: mc_exec = 16'b 001_1000_0_0000_0000; // A DATA W - -
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
//--------------------------------------------------
// indirect, y
//--------------------------------------------------
AND_IY,
ORA_IY,
EOR_IY,
ADC_IY,
SBC_IY,
CMP_IY,
LDA_IY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0100_0_0000_0000; // PC+1 ZA R - -
3'd1: mc_exec = 16'b 010_0100_0_0000_1000; // ZA AL R d 0
3'd2: mc_exec = 16'b 010_0010_0_0010_0000; // ZA+1 AH R y d
3'd3: mc_exec = 16'b 011_1000_0_0000_0000; // A+Y DATA R - -
3'd4: mc_exec = 16'b 101_1000_0_1000_0000; // PC+2 OP R *a d
endcase
STA_IY:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 010_0100_0_1000_0000; // PC+1 ZA R a 0
3'd1: mc_exec = 16'b 010_0100_0_0000_1000; // ZA AL R d 0
3'd2: mc_exec = 16'b 010_0010_1_0010_0000; // ZA+1 AH R y d
3'd3: mc_exec = 16'b 001_1000_0_0000_0000; // A+Y DATA W - -
3'd4: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
endcase
//--------------------------------------------------
// indirect
//--------------------------------------------------
JMP_IND:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 AL R - -
3'd1: mc_exec = 16'b 010_0010_0_0001_0000; // PC+2 AH R 0 d
3'd2: mc_exec = 16'b 010_0010_0_0000_0100; // A newPCL R r 0
3'd3: mc_exec = 16'b 011_0010_0_0001_0000; // A+1 newPCH R 0 d
3'd4: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
endcase
//--------------------------------------------------
// implied
//--------------------------------------------------
TAX,
TXA,
TAY,
TYA,
TSX,
TXS,
INX,
INY,
DEX,
DEY,
CLC,
CLD,
CLI,
CLV,
SEC,
SED,
SEI,
NOP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0000; // PC+1 -- R - -
3'd1: mc_exec = 16'b 101_1000_0_1000_0000; // PC+1 OP R *a 0
endcase
PHA,
PHP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0001_1_1000_0000; // PC+1 -- R *a 0
3'd1: mc_exec = 16'b 000_1000_0_0000_0001; // S REG W s 0
3'd2: mc_exec = 16'b 101_1000_0_0000_0000; // PC+1 OP R - -
endcase
PLA,
PLP:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0010; // PC+1 -- R s 0
3'd1: mc_exec = 16'b 000_0001_0_0000_0000; // PC+1 -- R - -
3'd2: mc_exec = 16'b 010_1000_0_0000_0000; // S+1 REG R - -
3'd3: mc_exec = 16'b 101_1000_0_1001_0000; // PC+1 OP R 0 d
endcase
RTI:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0010; // PC+1 -- R s 0
3'd1: mc_exec = 16'b 000_0001_0_0000_0010; // PC+1 -- R s 0
3'd2: mc_exec = 16'b 010_0001_0_0000_0010; // S+1 P R s 0
3'd3: mc_exec = 16'b 010_0001_0_1001_0000; // S+2 newPCL R 0 d
3'd4: mc_exec = 16'b 011_0010_0_0001_0000; // S+3 newPCH R 0 d
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
endcase
RTS:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0010; // PC+1 -- R s 0
3'd1: mc_exec = 16'b 000_0001_0_0000_0010; // PC+1 -- R s 0
3'd2: mc_exec = 16'b 010_0001_0_0000_0000; // S+1 newPCL R - -
3'd3: mc_exec = 16'b 011_0010_0_0001_0000; // S+2 newPCH R 0 d
3'd4: mc_exec = 16'b 001_1000_0_0000_0000; // newPC -- R - -
3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // newPC+1 OP R - -
endcase
BRK:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0001_1_0000_0001; // PC+1 -- R s 0
3'd1: mc_exec = 16'b 000_0001_1_0000_0001; // S PCH W s 0
3'd2: mc_exec = 16'b 000_0001_1_1000_0000; // S-1 PCL+2 W p 0
3'd3: mc_exec = 16'b 000_0000_0_0000_0001; // S-2 P W s 0
3'd4: mc_exec = 16'b 010_0000_0_0000_0000; // VA newPCL R - -
3'd5: mc_exec = 16'b 011_0010_0_0001_0000; // VA+1 newPCH R 0 d
3'd6: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
endcase
// // nmi/irq cycle
// case (cyc_cnt) //
// // FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// // EIC CPBP E PDDD NNNE // a b
// // TNC S XYZ DRSS // PC OP R
// 3'd0: mc_exec = 16'b 000_0001_1_0000_0001; // *PC -- R s 0
// 3'd1: mc_exec = 16'b 000_0001_1_0000_0001; // S *PCH W s 0
// 3'd2: mc_exec = 16'b 000_0001_1_1000_0000; // S-1 *PCL W p 0
// 3'd3: mc_exec = 16'b 000_0000_0_0000_0001; // S-2 P W s 0
// 3'd4: mc_exec = 16'b 010_0000_0_0000_0000; // VA newPCL R - -
// 3'd5: mc_exec = 16'b 011_0010_0_0001_0000; // VA+1 newPCH R 0 d
// 3'd6: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
// endcase
// // reset cycle
// case (cyc_cnt) //
// // FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// // EIC CPBP E PDDD NNNE // a b
// // TNC S XYZ DRSS // PC OP R
// 3'd0: mc_exec = 16'b 000_0001_0_0000_0001; // *PC -- R s 0
// 3'd1: mc_exec = 16'b 000_0001_0_0000_0001; // S -- *R s 0
// 3'd2: mc_exec = 16'b 000_0001_0_1000_0000; // S-1 -- *R p 0
// 3'd3: mc_exec = 16'b 000_0000_0_0000_0001; // S-2 -- *R s 0
// 3'd4: mc_exec = 16'b 010_0000_0_0000_0000; // VA newPCL R - -
// 3'd5: mc_exec = 16'b 011_0010_0_0001_0000; // VA+1 newPCH R 0 d
// 3'd6: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
// endcase
//--------------------------------------------------
// relative
//--------------------------------------------------
BEQ,
BNE,
BCS,
BCC,
BVS,
BVC,
BMI,
BPL:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 OFS R - -
3'd1: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R pcl d
endcase
//--------------------------------------------------
// undefined opcode (same as nop)
//--------------------------------------------------
default:
case (cyc_cnt)
// FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// EIC CPBP E PDDD NNNE // a b
// TNC S XYZ DRSS // PC OP R
3'd0: mc_exec = 16'b 000_0000_0_0000_0000; // PC+1 -- R - -
3'd1: mc_exec = 16'b 101_1000_0_0000_0000; // PC+1 OP R - -
endcase
endcase
end
//----------------------------------------------------------------------
// other microcodes
//----------------------------------------------------------------------
// BRK:
// case (cyc_cnt)
// // FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// // EIC CPBP E PDDD NNNE // a b
// // TNC S XYZ DRSS // PC OP R
// 3'd0: mc_exec = 16'b 000_0001_1_0000_0001; // PC+1 -- R s 0
// 3'd1: mc_exec = 16'b 000_0001_1_0000_0001; // S PCH W s 0
// 3'd2: mc_exec = 16'b 000_0001_1_1000_0000; // S-1 PCL+2 W p 0
// 3'd3: mc_exec = 16'b 000_0000_0_0000_0001; // S-2 P W s 0
// 3'd4: mc_exec = 16'b 010_0000_0_0000_0000; // VA newPCL R - -
// 3'd5: mc_exec = 16'b 011_0010_0_0001_0000; // VA+1 newPCH R 0 d
// 3'd6: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
// endcase
// JSR_ABS:
// case (cyc_cnt)
// // FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// // EIC CPBP E PDDD NNNE // a b
// // TNC S XYZ DRSS // PC OP R
// 3'd0: mc_exec = 16'b 010_0000_0_0000_0000; // PC+1 newPCL R - -
// 3'd1: mc_exec = 16'b 000_0001_1_0000_0001; // PC+1 -- R s 0
// 3'd2: mc_exec = 16'b 000_0001_1_0000_0001; // S PCH W s 0
// 3'd3: mc_exec = 16'b 001_1000_0_0000_0000; // S-1 PCL+2 W - -
// 3'd4: mc_exec = 16'b 011_0010_0_0001_0000; // PC+2 newPCH R 0 d
// 3'd5: mc_exec = 16'b 101_1000_0_0000_0000; // newPC OP R - -
// endcase
// interrupt vector address timing
assign mc_addr_vl = (opcode == BRK ) & (cyc_cnt == 3'd3);
assign mc_addr_vh = (opcode == BRK ) & (cyc_cnt == 3'd4);
// pc value(high/low) data output timing
assign mc_dout_pch = (opcode == BRK ) & (cyc_cnt == 3'd0)
| (opcode == JSR_ABS) & (cyc_cnt == 3'd1);
assign mc_dout_pcl = (opcode == BRK ) & (cyc_cnt == 3'd1)
| (opcode == JSR_ABS) & (cyc_cnt == 3'd2);
// interrupt i flag setting timing
assign mc_brk_if_set = (opcode == BRK ) & (cyc_cnt == 3'd2);
// BEQ,
// BNE,
// BCS,
// BCC,
// BVS,
// BVC,
// BMI,
// BPL:
// case (cyc_cnt)
// // FDP PZAS O OAAA IIID // ADDR DIO R/W ALU
// // EIC CPBP E PDDD NNNE // a b
// // TNC S XYZ DRSS // PC OP R
// 3'd0: mc_exec = 16'b 011_1000_0_0000_0000; // PC+1 OFS R - -
// 3'd1: mc_exec = 16'b 101_1000_0_0000_0000; // PC+2 OP R - -
// endcase
// branch condition check timing
assign mc_br_chk = (opcode == BEQ) & (cyc_cnt == 3'd1)
| (opcode == BNE) & (cyc_cnt == 3'd1)
| (opcode == BCS) & (cyc_cnt == 3'd1)
| (opcode == BCC) & (cyc_cnt == 3'd1)
| (opcode == BVS) & (cyc_cnt == 3'd1)
| (opcode == BVC) & (cyc_cnt == 3'd1)
| (opcode == BMI) & (cyc_cnt == 3'd1)
| (opcode == BPL) & (cyc_cnt == 3'd1);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_on GENCLK
reg [31:0] long;
reg [63:0] quad;
wire [31:0] longout;
wire [63:0] quadout;
wire [7:0] narrow = long[7:0];
sub sub (/*AUTOINST*/
// Outputs
.longout (longout[31:0]),
.quadout (quadout[63:0]),
// Inputs
.narrow (narrow[7:0]),
.quad (quad[63:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
long <= 32'h12345678;
quad <= 64'h12345678_abcdef12;
end
if (cyc==2) begin
if (longout !== 32'h79) $stop;
if (quadout !== 64'h12345678_abcdef13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
wire [31:0] longout = $c32("(",narrow,"+1)");
wire [63:0] quadout = $c64("(",quad,"+1)");
`else
wire [31:0] longout = narrow + 8'd1;
wire [63:0] quadout = quad + 64'd1;
`endif
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output CLKDV_OUT;
output DCM_SP_LOCKED_OUT;
input dcm_progclk;
input dcm_progdata;
input dcm_progen;
input dcm_reset;
output dcm_progdone;
output dcm_locked;
output [2:1] dcm_status;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFX1_BUF;
wire CLKFX2_BUF;
wire CLKDV_BUF;
wire GND_BIT;
wire dcm_progclk_buf;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLKFX1_BUFG_INST (.I(CLKFX1_BUF),
.O(CLKFX1_OUT));
BUFG CLKFX2_BUFG_INST (.I(CLKFX2_BUF),
.O(CLKFX2_OUT));
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG DCMPROGCLK_BUFG_INST (.I(dcm_progclk),
.O(dcm_progclk_buf));
// 100 MHZ osc gives fixed 50MHz CLKFX1, 12.5MHZ CLKDV
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX1_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(DCM_SP_LOCKED_OUT),
.PSDONE(),
.STATUS());
DCM_CLKGEN #(
.CLKFX_DIVIDE(100), // 100Mhz osc so gives steps of 1MHz
.CLKFX_MULTIPLY(SPEED_MHZ),
.CLKFXDV_DIVIDE(2), // Unused
.CLKIN_PERIOD(10.0),
.CLKFX_MD_MAX(0.000),
.SPREAD_SPECTRUM("NONE"),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_INST (
.CLKIN(CLKIN_IBUFG),
.CLKFX(CLKFX2_BUF),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata),
.PROGEN(dcm_progen),
.PROGDONE(dcm_progdone),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(dcm_reset)
);
endmodule
|
module opc8cpu(input[23:0] din,input clk,input reset_b,input[1:0] int_b,input clken,output vpa,output vda,output[23:0] dout,output[23:0] address,output rnw);
parameter HALT=5'h00,NOT=5'h01,OR=5'h02,XOR=5'h03,BPERM=5'h04,ROR=5'h05,LSR=5'h06,ASR=5'h07,ROL=5'h08,RTI=5'h09,PPSR=5'h0A,GPSR=5'h0B;
parameter BROR=5'h0C, BROL=5'h0D,MOV=5'h10,JSR=5'h11,CMP=5'h12,SUB=5'h13,ADD=5'h14,AND=5'h15,STO=5'h16,LD=5'h17;
parameter FET=3'h0,FET1=3'h1,EAD=3'h2,RDM=3'h3,EXEC=3'h4,WRM=3'h5,INT=3'h6,EI=3,S=2,C=1,Z=0,INT_VECTOR0=24'h2,INT_VECTOR1=24'h4;
reg [7:0] PSR_q; (* RAM_STYLE="DISTRIBUTED" *)
reg [23:0] PC_q,PCI_q, RF_q[14:0], RF_pipe_q, OR_q, result;
reg [4:0] IR_q;
reg [3:0] swiid,PSRI_q,dst_q,src_q, pred_q;
reg [2:0] FSM_q, FSM_d;
reg zero,carry,sign,enable_int,reset_s0_b,reset_s1_b,subnotadd_q, rnw_q, vpa_q, vda_q;
wire pred = (pred_q[0] ^ (pred_q[1]?(pred_q[2]?PSR_q[S]:PSR_q[Z]):(pred_q[2]?PSR_q[C]:1)));
wire [23:0] RF_sout = {24{(|src_q)&&IR_q[4:2]!=3'b111}} & ((src_q==4'hF)? PC_q : RF_q[src_q]);
wire [23:0] bytes = (IR_q==BROL)?{OR_q[15:0],OR_q[23:16]}:{OR_q[7:0],OR_q[23:8]};
assign {rnw,dout,address}= {rnw_q, RF_pipe_q, (vpa_q)? PC_q : OR_q};
assign {vpa,vda} = {vpa_q, vda_q};
always @( * ) begin
case (IR_q)
AND,OR :{carry,result} = {PSR_q[C],(IR_q==AND)?(RF_pipe_q & OR_q):(RF_pipe_q | OR_q)};
ROL,NOT :{carry,result} = (IR_q==NOT)? {PSR_q[C], ~OR_q} : {OR_q, PSR_q[C]};
ADD,SUB,CMP :{carry,result} = RF_pipe_q + OR_q + subnotadd_q; // OR_q negated in EAD if required for sub/cmp
XOR,GPSR :{carry,result} = (IR_q==GPSR)?{PSR_q[C],8'b0,PSR_q}:{PSR_q[C],RF_pipe_q ^ OR_q};
ROR,ASR,LSR :{result,carry} = {(IR_q==ROR)?PSR_q[C]:(IR_q==ASR)?OR_q[23]:1'b0,OR_q};
BROL,BROR :{carry,result} = { (IR_q==BROL)? (|OR_q[23:16]): (|OR_q[7:0]), OR_q};
default :{carry,result} = {PSR_q[C],OR_q} ;
endcase // case ( IR_q )
{swiid,enable_int,sign,carry,zero} = (IR_q==PPSR)?OR_q[7:0]:(dst_q!=4'hF)?{PSR_q[7:3],result[23],carry,!(|result)}:PSR_q;
case (FSM_q)
FET : FSM_d = (din[20:19]==2'b11)? FET1 : EAD;
FET1 : FSM_d = EAD; // Could check predicates here to speed up skipped double word instructions
EAD : FSM_d = (!pred) ? FET : (IR_q==LD) ? RDM : (IR_q==STO) ? WRM : EXEC;
EXEC : FSM_d = ((!(&int_b) & PSR_q[EI])||(IR_q==PPSR&&(|swiid)))?INT:(dst_q==4'hF||IR_q==JSR)?FET:(din[20:19]==2'b11)?FET1:EAD;
WRM : FSM_d = (!(&int_b) & PSR_q[EI])?INT:FET;
default: FSM_d = (FSM_q==RDM)? EXEC : FET;
endcase
end // always @ ( * )
always @(posedge clk)
if (clken) begin
RF_pipe_q <= (dst_q==4'hF)? PC_q : RF_q[dst_q] & {24{(|dst_q)}};
// Sign extension on short immediates only if source field==0 being done on reading memory - may move this to EAD state...
OR_q <= (FSM_q==EAD)?(IR_q==BROL||IR_q==BROR)? bytes: ((RF_sout+OR_q)^{24{(IR_q==SUB||IR_q==CMP)}}):(FSM_q==FET||FSM_q==EXEC)?{{16{(din[7]&(|din[11:8]))}}, din[7:0]}:din;
{reset_s0_b,reset_s1_b, subnotadd_q} <= {reset_b,reset_s0_b, IR_q!=ADD};
if (!reset_s1_b) begin
{PC_q,PCI_q,PSRI_q,PSR_q,FSM_q,vda_q} <= 0;
{rnw_q, vpa_q} <= 2'b11;
end
else begin
{FSM_q, rnw_q} <= {FSM_d, !(FSM_d==WRM) } ;
{vpa_q, vda_q} <= {FSM_d==FET||FSM_d==FET1||FSM_d==EXEC,FSM_d==RDM||FSM_d==WRM};
if ((FSM_q==FET)||(FSM_q==EXEC))
{pred_q, IR_q, dst_q, src_q} <= { din[23:21],(din[20:19]==2'b11)?2'b10: din[20:19], din[18:8]}; // Alias 'long' opcodes to short equivalent
else if (FSM_q==EAD & IR_q==CMP )
dst_q <= 4'b0; // Zero dest address after reading it in EAD for CMP operations
if ( FSM_q == INT )
{PC_q,PCI_q,PSRI_q,PSR_q[EI]} <= {(!int_b[1])?INT_VECTOR1:INT_VECTOR0,PC_q,PSR_q[3:0],1'b0};
else if (FSM_q==FET||FSM_q==FET1)
PC_q <= PC_q + 1;
else if ( FSM_q == EXEC) begin
PC_q <= (IR_q==RTI)?PCI_q: (dst_q==4'hF) ? result[23:0] : (IR_q==JSR)?OR_q:((!(&int_b)&&PSR_q[EI])||(IR_q==PPSR&&(|swiid)))?PC_q:PC_q + 1;
PSR_q <= (IR_q==RTI)?{4'b0,PSRI_q}:{swiid,enable_int,sign,carry,zero};
RF_q[dst_q] <= (IR_q==JSR)? PC_q : result ;
end
end
end
endmodule // opc8cpu
|
//======================================================================
//
// rosc_entropy_core.v
// -------------------
// Digitial ring oscillator based entropy generation core.
// This version implements 32 separate oscillators where each
// oscillator can be enabled or disabled.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module rosc_entropy_core(
input wire clk,
input wire reset_n,
input wire [31 : 0] opa,
input wire [31 : 0] opb,
input wire [31 : 0] rosc_en,
input wire [7 : 0] rosc_cycles,
output wire [31 : 0] raw_entropy,
output wire [31 : 0] rosc_outputs,
output wire [31 : 0] entropy_data,
output wire entropy_valid,
input wire entropy_ack,
output wire [7 : 0] debug,
input wire debug_update
);
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
localparam ADDER_WIDTH = 2;
localparam DEBUG_DELAY = 32'h002c4b40;
localparam NUM_SHIFT_BITS = 8'h20;
localparam SAMPLE_CLK_CYCLES = 8'hff;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] ent_shift_reg;
reg [31 : 0] ent_shift_new;
reg ent_shift_we;
reg [31 : 0] entropy_reg;
reg entropy_we;
reg entropy_valid_reg;
reg entropy_valid_new;
reg entropy_valid_we;
reg bit_we_reg;
reg bit_we_new;
reg [7 : 0] bit_ctr_reg;
reg [7 : 0] bit_ctr_new;
reg bit_ctr_inc;
reg bit_ctr_we;
reg [7 : 0] sample_ctr_reg;
reg [7 : 0] sample_ctr_new;
reg [31 : 0] debug_delay_ctr_reg;
reg [31 : 0] debug_delay_ctr_new;
reg debug_delay_ctr_we;
reg [7 : 0] debug_reg;
reg debug_we;
reg debug_update_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] rosc_we;
// Ugly in-line Xilinx attribute to preserve the registers.
(* equivalent_register_removal = "no" *)
wire [31 : 0] rosc_dout;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rosc_outputs = rosc_dout;
assign raw_entropy = ent_shift_reg;
assign entropy_data = entropy_reg;
assign entropy_valid = entropy_valid_reg;
assign debug = debug_reg;
//----------------------------------------------------------------
// module instantiations.
//
// 32 oscillators each ADDER_WIDTH wide. We want them to run
// as fast as possible to maximize differences over time.
// We also only sample the oscillators SAMPLE_CLK_CYCLES number
// of cycles.
//----------------------------------------------------------------
genvar i;
generate
for(i = 0 ; i < 32 ; i = i + 1)
begin: oscillators
rosc #(.WIDTH(ADDER_WIDTH)) rosc_array(.clk(clk),
.we(rosc_we[i]),
.reset_n(reset_n),
.opa(opa[(ADDER_WIDTH - 1) : 0]),
.opb(opb[(ADDER_WIDTH - 1) : 0]),
.dout(rosc_dout[i])
);
end
endgenerate
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
ent_shift_reg <= 32'h00000000;
entropy_reg <= 32'h00000000;
entropy_valid_reg <= 0;
bit_ctr_reg <= 8'h00;
sample_ctr_reg <= 8'h00;
debug_delay_ctr_reg <= 32'h00000000;
debug_reg <= 8'h00;
debug_update_reg <= 0;
end
else
begin
sample_ctr_reg <= sample_ctr_new;
debug_update_reg <= debug_update;
if (ent_shift_we)
begin
ent_shift_reg <= ent_shift_new;
end
if (bit_ctr_we)
begin
bit_ctr_reg <= bit_ctr_new;
end
if (entropy_we)
begin
entropy_reg <= ent_shift_reg;
end
if (entropy_valid_we)
begin
entropy_valid_reg <= entropy_valid_new;
end
if (debug_delay_ctr_we)
begin
debug_delay_ctr_reg <= debug_delay_ctr_new;
end
if (debug_we)
begin
debug_reg <= ent_shift_reg[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
// debug_out
//
// Logic that updates the debug port.
//----------------------------------------------------------------
always @*
begin : debug_out
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 0;
debug_we = 0;
if (debug_update_reg)
begin
debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
debug_delay_ctr_we = 1;
end
if (debug_delay_ctr_reg == DEBUG_DELAY)
begin
debug_delay_ctr_new = 32'h00000000;
debug_delay_ctr_we = 1;
debug_we = 1;
end
end
//----------------------------------------------------------------
// entropy_out
//
// Logic that implements the random output control. If we have
// added more than NUM_SHIFT_BITS we raise the entropy_valid flag.
// When we detect and ACK, the valid flag is dropped.
//----------------------------------------------------------------
always @*
begin : entropy_out
bit_ctr_new = 8'h00;
bit_ctr_we = 0;
entropy_we = 0;
entropy_valid_new = 0;
entropy_valid_we = 0;
if (bit_ctr_inc)
begin
if (bit_ctr_reg < NUM_SHIFT_BITS)
begin
bit_ctr_new = bit_ctr_reg + 1'b1;
bit_ctr_we = 1;
end
else
begin
entropy_we = 1;
entropy_valid_new = 1;
entropy_valid_we = 1;
end
end
if (entropy_ack)
begin
bit_ctr_new = 8'h00;
bit_ctr_we = 1;
entropy_valid_new = 0;
entropy_valid_we = 1;
end
end
//----------------------------------------------------------------
// entropy_gen
//
// Logic that implements the actual entropy bit value generator
// by XOR mixing the oscillator outputs. These outputs are
// sampled once every SAMPLE_CLK_CYCLES.
//----------------------------------------------------------------
always @*
begin : entropy_gen
reg ent_bit;
bit_ctr_inc = 0;
rosc_we = 32'h00000000;
ent_shift_we = 0;
ent_bit = ^rosc_dout;
ent_shift_new = {ent_shift_reg[30 : 0], ent_bit};
sample_ctr_new = sample_ctr_reg + 1'b1;
if (sample_ctr_reg == SAMPLE_CLK_CYCLES)
begin
sample_ctr_new = 8'h00;
bit_ctr_inc = 1;
rosc_we = rosc_en;
ent_shift_we = 1;
end
end
endmodule // rosc_entropy_core
//======================================================================
// EOF rosc_entropy_core.v
//======================================================================
|
/*
File: ewrapper_link_receiver.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_link_receiver (/*AUTOARG*/
// Outputs
rxi_wr_wait, rxi_rd_wait, emesh_clk_inb, emesh_access_inb,
emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
// Inputs
reset, rxi_data, rxi_lclk, rxi_frame, emesh_wr_wait_outb,
emesh_rd_wait_outb
);
//#########
//# INPUTS
//#########
input reset; //reset input
//# From the lvds-serdes
input [63:0] rxi_data; //Eight Parallel Byte words
input rxi_lclk; //receive clock (synchronized to the data)
input [7:0] rxi_frame; //Parallel frame signals representing
// 4 transmission clock cycles
//# From the emesh interface
input emesh_wr_wait_outb;
input emesh_rd_wait_outb;
//##########
//# OUTPUTS
//##########
//# To the transmitter
output rxi_wr_wait; //wait indicator
output rxi_rd_wait; //wait indicator
//# To the emesh interface
output emesh_clk_inb;
output emesh_access_inb;
output emesh_write_inb;
output [1:0] emesh_datamode_inb;
output [3:0] emesh_ctrlmode_inb;
output [31:0] emesh_dstaddr_inb;
output [31:0] emesh_srcaddr_inb;
output [31:0] emesh_data_inb;
/*AUTOINPUT*/
/*AUTOWIRE*/
//#########
//# Wires
//#########
wire emesh_wr_access_inb;
wire emesh_wr_write_inb;
wire [1:0] emesh_wr_datamode_inb;
wire [3:0] emesh_wr_ctrlmode_inb;
wire [31:0] emesh_wr_dstaddr_inb;
wire [31:0] emesh_wr_srcaddr_inb;
wire [31:0] emesh_wr_data_inb;
wire emesh_rd_access_inb;
wire emesh_rd_write_inb;
wire [1:0] emesh_rd_datamode_inb;
wire [3:0] emesh_rd_ctrlmode_inb;
wire [31:0] emesh_rd_dstaddr_inb;
wire [31:0] emesh_rd_srcaddr_inb;
wire [31:0] emesh_rd_data_inb;
wire select_write_tran;
wire wr_wait;
wire rd_wait;
wire emesh_access_tmp;
//###############
//# Emesh clock
//###############
assign emesh_clk_inb = rxi_lclk;
//######################################
//# Write-Read Transactions Arbitration
//# Write has a higher priority ALWAYS
//######################################
assign select_write_tran = emesh_wr_access_inb & ~emesh_wr_wait_outb;
assign emesh_access_inb = emesh_access_tmp & ~emesh_wr_wait_outb;
assign wr_wait = emesh_wr_wait_outb;
assign rd_wait = emesh_rd_access_inb & select_write_tran |
(emesh_wr_wait_outb | emesh_rd_wait_outb);
assign emesh_srcaddr_inb[31:0] =
select_write_tran ? emesh_wr_srcaddr_inb[31:0] :
emesh_rd_srcaddr_inb[31:0];
assign emesh_dstaddr_inb[31:0] =
select_write_tran ? emesh_wr_dstaddr_inb[31:0] :
emesh_rd_dstaddr_inb[31:0];
assign emesh_datamode_inb[1:0] =
select_write_tran ? emesh_wr_datamode_inb[1:0] :
emesh_rd_datamode_inb[1:0];
assign emesh_ctrlmode_inb[3:0] =
select_write_tran ? emesh_wr_ctrlmode_inb[3:0] :
emesh_rd_ctrlmode_inb[3:0];
assign emesh_data_inb[31:0] = select_write_tran ? emesh_wr_data_inb[31:0] :
emesh_rd_data_inb[31:0];
assign emesh_access_tmp = select_write_tran ? emesh_wr_access_inb :
emesh_rd_access_inb;
assign emesh_write_inb = select_write_tran ? emesh_wr_write_inb :
emesh_rd_write_inb;
//############################################
//# Write Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b0),
.emesh_wait_outb (wr_wait),
.rxi_wait (rxi_wr_wait),
.emesh_\(.*\) (emesh_wr_\1[]),
);
*/
ewrapper_link_rxi wr_rxi(/*AUTOINST*/
// Outputs
.rxi_wait (rxi_wr_wait), // Templated
.emesh_access_inb (emesh_wr_access_inb), // Templated
.emesh_write_inb (emesh_wr_write_inb), // Templated
.emesh_datamode_inb (emesh_wr_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_wr_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (wr_wait), // Templated
.rxi_rd (1'b0)); // Templated
//############################################
//# Read Transactions Receiver Instantiation
//############################################
/*ewrapper_link_rxi AUTO_TEMPLATE(
.rxi_rd (1'b1),
.emesh_wait_outb (rd_wait),
.rxi_wait (rxi_rd_wait),
.emesh_\(.*\) (emesh_rd_\1[]),
);
*/
ewrapper_link_rxi rd_rxi(/*AUTOINST*/
// Outputs
.rxi_wait (rxi_rd_wait), // Templated
.emesh_access_inb (emesh_rd_access_inb), // Templated
.emesh_write_inb (emesh_rd_write_inb), // Templated
.emesh_datamode_inb (emesh_rd_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emesh_rd_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
// Inputs
.reset (reset),
.rxi_data (rxi_data[63:0]),
.rxi_lclk (rxi_lclk),
.rxi_frame (rxi_frame[7:0]),
.emesh_wait_outb (rd_wait), // Templated
.rxi_rd (1'b1)); // Templated
endmodule // ewrapper_link_receiver
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_icmp(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall, i_settings);
parameter DATA_WIDTH = 32;
parameter MODE_WIDTH = 4;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output reg o_dataout;
output o_dataout_valid;
input i_stall;
input [MODE_WIDTH-1:0] i_settings;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire signed [DATA_WIDTH-1:0] sdataa;
wire signed [DATA_WIDTH-1:0] sdatab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_stall);
assign sdataa = dataa;
assign sdatab = datab;
always @(*)
begin
case (i_settings)
5'h0: // EQ
begin
o_dataout <= (dataa == datab) ? 1'b1 : 1'b0;
end
5'h1: // NE
begin
o_dataout <= (dataa != datab) ? 1'b1 : 1'b0;
end
5'h2: // UGT
begin
o_dataout <= (dataa > datab) ? 1'b1 : 1'b0;
end
5'h3: // UGE
begin
o_dataout <= (dataa >= datab) ? 1'b1 : 1'b0;
end
5'h4: // ULT
begin
o_dataout <= (dataa < datab) ? 1'b1 : 1'b0;
end
5'h5: // ULE
begin
o_dataout <= (dataa <= datab) ? 1'b1 : 1'b0;
end
5'h6: // SGT
begin
o_dataout <= (sdataa > sdatab) ? 1'b1 : 1'b0;
end
5'h7: // SGE
begin
o_dataout <= (sdataa >= sdatab) ? 1'b1 : 1'b0;
end
5'h8: // SLT
begin
o_dataout <= (sdataa < sdatab) ? 1'b1 : 1'b0;
end
5'h9: // SLE
begin
o_dataout <= (sdataa <= sdatab) ? 1'b1 : 1'b0;
end
default:
begin
o_dataout <= 1'b0;
end
endcase
end
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_tx when to transmit the next bit
//-- __ __
//-- __| |________________________________________________________| |________________
//-- -> <- 1 clock cycle
//--
//---------------------------------------------------------------------------------------
module baudgen_tx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is 0, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
// $Id: unused_reg.v 1914 2007-07-11 23:58:33Z grg $
//
// Module: unused_reg.v
// Project: NetFPGA
// Description: Unused register block
//
///////////////////////////////////////////////////////////////////////////////
module unused_reg
#(
parameter REG_ADDR_WIDTH = 5
)
(
// Register interface signals
input reg_req,
output reg_ack,
input reg_rd_wr_L,
input [REG_ADDR_WIDTH - 1:0] reg_addr,
output [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
reg reg_req_d1;
assign reg_rd_data = 'h dead_beef;
// Only generate an ack on a new request
assign reg_ack = reg_req && !reg_req_d1;
always @(posedge clk)
begin
reg_req_d1 <= reg_req;
end
endmodule // unused_reg
|
module bts ( z , a , e);
inout z ; wire z ;
input a ; wire a ;
input e ; wire e ;
assign #4 z= ( (e==1'b1)? a : 1'bz );
endmodule
module test();
reg [1:0] aa;
wire [1:0] zz;
reg [1:0] ee;
bts sub1 (.z(zz[1]), .a(aa[1]), .e(ee[1]));
bts sub0 (.z(zz[0]), .a(aa[0]), .e(ee[0]));
initial begin
// $dumpvars;
ee=2'b00;
aa=2'b00; #100;
if (zz !== 2'bzz) begin
$display("FAILED -- (1) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2'b11; #100;
if (zz !== 2'bzz) begin
$display("FAILED -- (2) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2'b00; #100;
if (zz !== 2'bzz) begin
$display("FAILED -- (3) All disabled, expected HiZ, got %b", zz);
$finish;
end
aa=2'b11; #100;
if (zz !== 2'bzz) begin
$display("FAILED -- (4) All disabled, expected HiZ, got %b", zz);
$finish;
end
ee=2'b11;
aa=2'b00; #100;
if (zz !== 2'b00) begin
$display("FAILED -- (5) All enabled, expected 00, got %b", zz);
$finish;
end
aa=2'b11; #100;
if (zz !== 2'b11) begin
$display("FAILED -- (6) All enabled, expected 11, got %b", zz);
$finish;
end
aa=2'b00; #100;
if (zz !== 2'b00) begin
$display("FAILED -- (7) All enabled, expected 00, got %b", zz);
$finish;
end
aa=2'b11; #100;
if (zz !== 2'b11) begin
$display("FAILED -- (8) All enabled, expected 11, got %b", zz);
$finish;
end
$display("PASSED");
end
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Up-Sizer
// Up-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data and Read Data Up-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Up-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_7_axi_upsizer #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// parameter integer C_FIFO_MODE = 0,
parameter integer C_FIFO_MODE = 1,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface
input wire s_axi_aresetn,
input wire s_axi_aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface
input wire m_axi_aresetn,
input wire m_axi_aclk,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
localparam integer P_CONV_LIGHT_WT = 0;
localparam integer P_AXI4 = 0;
localparam integer C_FIFO_DEPTH_LOG = 5;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NO_FIFO = 0;
localparam integer P_PKTFIFO = 1;
localparam integer P_PKTFIFO_CLK = 2;
localparam integer P_DATAFIFO = 3;
localparam integer P_DATAFIFO_CLK = 4;
localparam P_CLK_CONV = ((C_FIFO_MODE == P_PKTFIFO_CLK) || (C_FIFO_MODE == P_DATAFIFO_CLK));
localparam integer C_M_AXI_AW_REGISTER = 0;
// Simple register AW output.
// Range: 0, 1
localparam integer C_M_AXI_W_REGISTER = 1; // Parameter not used; W reg always implemented.
localparam integer C_M_AXI_AR_REGISTER = 0;
// Simple register AR output.
// Range: 0, 1
localparam integer C_S_AXI_R_REGISTER = 0;
// Simple register R output (SI).
// Range: 0, 1
localparam integer C_M_AXI_R_REGISTER = 1;
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
localparam integer P_RID_QUEUE = ((C_SUPPORTS_ID != 0) && !((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK))) ? 1 : 0;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire aclk;
wire m_aclk;
wire sample_cycle;
wire sample_cycle_early;
wire sm_aresetn;
wire s_aresetn_i;
wire [C_S_AXI_ID_WIDTH-1:0] sr_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_awaddr ;
wire [8-1:0] sr_awlen ;
wire [3-1:0] sr_awsize ;
wire [2-1:0] sr_awburst ;
wire [2-1:0] sr_awlock ;
wire [4-1:0] sr_awcache ;
wire [3-1:0] sr_awprot ;
wire [4-1:0] sr_awregion ;
wire [4-1:0] sr_awqos ;
wire sr_awvalid ;
wire sr_awready ;
wire [C_S_AXI_ID_WIDTH-1:0] sr_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_araddr ;
wire [8-1:0] sr_arlen ;
wire [3-1:0] sr_arsize ;
wire [2-1:0] sr_arburst ;
wire [2-1:0] sr_arlock ;
wire [4-1:0] sr_arcache ;
wire [3-1:0] sr_arprot ;
wire [4-1:0] sr_arregion ;
wire [4-1:0] sr_arqos ;
wire sr_arvalid ;
wire sr_arready ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_wdata ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_wstrb ;
wire sr_wlast ;
wire sr_wvalid ;
wire sr_wready ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_rdata ;
wire [2-1:0] mr_rresp ;
wire mr_rlast ;
wire mr_rvalid ;
wire mr_rready ;
wire m_axi_rready_i;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_ii ;
wire [3:0] s_axi_awregion_ii;
wire [3:0] s_axi_arregion_ii;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen : s_axi_awlen[3:0];
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlock[0] : s_axi_awlock;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen : s_axi_arlen[3:0];
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlock[0] : s_axi_arlock;
assign sr_awlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen_ii: {4'b0, s_axi_awlen_ii};
assign sr_awlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_awlock_ii} : s_axi_awlock_ii;
assign sr_arlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen_ii: {4'b0, s_axi_arlen_ii};
assign sr_arlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_arlock_ii} : s_axi_arlock_ii;
assign sr_awregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awregion_ii : 4'b0;
assign sr_arregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arregion_ii : 4'b0;
assign aclk = s_axi_aclk;
assign sm_aresetn = s_axi_aresetn & m_axi_aresetn;
generate
if (P_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end else begin : gen_sync_conv
wire fast_aclk;
wire slow_aclk;
reg s_aresetn_r;
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = m_axi_aclk;
assign slow_aclk = s_axi_aclk;
end else begin : gen_fastclk_si
assign fast_aclk = s_axi_aclk;
assign slow_aclk = m_axi_aclk;
end
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_aresetn_r;
always @(negedge sm_aresetn, posedge fast_aclk) begin
if (~sm_aresetn) begin
s_aresetn_r <= 1'b0;
end else if (s_axi_aresetn & m_axi_aresetn & sample_cycle_early) begin
s_aresetn_r <= 1'b1;
end
end
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_6_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
end
end else begin : gen_no_clk_conv
assign m_aclk = s_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end // gen_clock_conv
axi_register_slice_v2_1_7_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (aclk),
.s_axi_awid (s_axi_awid ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awlen (s_axi_awlen_i ),
.s_axi_awsize (s_axi_awsize ),
.s_axi_awburst (s_axi_awburst ),
.s_axi_awlock (s_axi_awlock_i ),
.s_axi_awcache (s_axi_awcache ),
.s_axi_awprot (s_axi_awprot ),
.s_axi_awregion (s_axi_awregion ),
.s_axi_awqos (s_axi_awqos ),
.s_axi_awuser (1'b0 ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid (s_axi_arid ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arlen (s_axi_arlen_i ),
.s_axi_arsize (s_axi_arsize ),
.s_axi_arburst (s_axi_arburst ),
.s_axi_arlock (s_axi_arlock_i ),
.s_axi_arcache (s_axi_arcache ),
.s_axi_arprot (s_axi_arprot ),
.s_axi_arregion (s_axi_arregion ),
.s_axi_arqos (s_axi_arqos ),
.s_axi_aruser (1'b0 ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rid ( ) ,
.s_axi_rdata ( ) ,
.s_axi_rresp ( ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( ) ,
.s_axi_rready ( 1'b0 ) ,
.m_axi_awid (sr_awid ),
.m_axi_awaddr (sr_awaddr ),
.m_axi_awlen (s_axi_awlen_ii),
.m_axi_awsize (sr_awsize ),
.m_axi_awburst (sr_awburst ),
.m_axi_awlock (s_axi_awlock_ii),
.m_axi_awcache (sr_awcache ),
.m_axi_awprot (sr_awprot ),
.m_axi_awregion (s_axi_awregion_ii ),
.m_axi_awqos (sr_awqos ),
.m_axi_awuser (),
.m_axi_awvalid (sr_awvalid ),
.m_axi_awready (sr_awready ),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (sr_arid ),
.m_axi_araddr (sr_araddr ),
.m_axi_arlen (s_axi_arlen_ii),
.m_axi_arsize (sr_arsize ),
.m_axi_arburst (sr_arburst ),
.m_axi_arlock (s_axi_arlock_ii),
.m_axi_arcache (sr_arcache ),
.m_axi_arprot (sr_arprot ),
.m_axi_arregion (s_axi_arregion_ii ),
.m_axi_arqos (sr_arqos ),
.m_axi_aruser (),
.m_axi_arvalid (sr_arvalid ),
.m_axi_arready (sr_arready ),
.m_axi_rid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.m_axi_rresp ( 2'b00 ),
.m_axi_rlast ( 1'b0 ),
.m_axi_ruser ( 1'b0 ),
.m_axi_rvalid ( 1'b0 ),
.m_axi_rready ( )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i ;
wire [8-1:0] m_axi_awlen_i ;
wire [3-1:0] m_axi_awsize_i ;
wire [2-1:0] m_axi_awburst_i ;
wire [2-1:0] m_axi_awlock_i ;
wire [4-1:0] m_axi_awcache_i ;
wire [3-1:0] m_axi_awprot_i ;
wire [4-1:0] m_axi_awregion_i ;
wire [4-1:0] m_axi_awqos_i ;
wire m_axi_awvalid_i ;
wire m_axi_awready_i ;
wire s_axi_bvalid_i ;
wire [2-1:0] s_axi_bresp_i ;
wire [C_AXI_ADDR_WIDTH-1:0] wr_cmd_si_addr;
wire [8-1:0] wr_cmd_si_len;
wire [3-1:0] wr_cmd_si_size;
wire [2-1:0] wr_cmd_si_burst;
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_id_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire wpush;
wire wpop;
reg [C_FIFO_DEPTH_LOG-1:0] wcnt;
// Write Address Channel.
axi_dwidth_converter_v2_1_7_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (C_SUPPORTS_ID),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
.cmd_id (wr_cmd_id),
.cmd_id_ready (wr_cmd_id_ready),
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_id (),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_awid),
.S_AXI_AADDR (sr_awaddr),
.S_AXI_ALEN (sr_awlen),
.S_AXI_ASIZE (sr_awsize),
.S_AXI_ABURST (sr_awburst),
.S_AXI_ALOCK (sr_awlock),
.S_AXI_ACACHE (sr_awcache),
.S_AXI_APROT (sr_awprot),
.S_AXI_AREGION (sr_awregion),
.S_AXI_AQOS (sr_awqos),
.S_AXI_AVALID (sr_awvalid),
.S_AXI_AREADY (sr_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i ),
.M_AXI_ALEN (m_axi_awlen_i ),
.M_AXI_ASIZE (m_axi_awsize_i ),
.M_AXI_ABURST (m_axi_awburst_i ),
.M_AXI_ALOCK (m_axi_awlock_i ),
.M_AXI_ACACHE (m_axi_awcache_i ),
.M_AXI_APROT (m_axi_awprot_i ),
.M_AXI_AREGION (m_axi_awregion_i ),
.M_AXI_AQOS (m_axi_awqos_i ),
.M_AXI_AVALID (m_axi_awvalid_i ),
.M_AXI_AREADY (m_axi_awready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_w_upsizer
// Packet FIFO Write Data channel.
axi_dwidth_converter_v2_1_7_w_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_write_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (m_axi_awaddr_i ),
.S_AXI_AWLEN (m_axi_awlen_i ),
.S_AXI_AWSIZE (m_axi_awsize_i ),
.S_AXI_AWBURST (m_axi_awburst_i ),
.S_AXI_AWLOCK (m_axi_awlock_i ),
.S_AXI_AWCACHE (m_axi_awcache_i ),
.S_AXI_AWPROT (m_axi_awprot_i ),
.S_AXI_AWREGION (m_axi_awregion_i ),
.S_AXI_AWQOS (m_axi_awqos_i ),
.S_AXI_AWVALID (m_axi_awvalid_i ),
.S_AXI_AWREADY (m_axi_awready_i ),
// Master Interface Write Address Port
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWREGION (m_axi_awregion),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_w_upsizer
// Write Data channel.
axi_dwidth_converter_v2_1_7_w_upsizer #
(
.C_FAMILY ("rtl"),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
assign m_axi_awaddr = m_axi_awaddr_i ;
assign m_axi_awlen = m_axi_awlen_i ;
assign m_axi_awsize = m_axi_awsize_i ;
assign m_axi_awburst = m_axi_awburst_i ;
assign m_axi_awlock = m_axi_awlock_i ;
assign m_axi_awcache = m_axi_awcache_i ;
assign m_axi_awprot = m_axi_awprot_i ;
assign m_axi_awregion = m_axi_awregion_i ;
assign m_axi_awqos = m_axi_awqos_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_awready_i = m_axi_awready ;
end // gen_w_upsizer
// Write Response channel.
assign wr_cmd_id_ready = s_axi_bvalid_i & s_axi_bready;
assign s_axi_bid = wr_cmd_id;
assign s_axi_bresp = s_axi_bresp_i;
assign s_axi_bvalid = s_axi_bvalid_i;
if (P_CLK_CONV) begin : gen_b_clk_conv
if (C_AXI_IS_ACLK_ASYNC == 0) begin : gen_b_sync_conv
axi_clock_converter_v2_1_6_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( 2 ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_CONV_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_axi_bresp ) ,
.S_VALID ( m_axi_bvalid ) ,
.S_READY ( m_axi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_axi_bresp_i ) ,
.M_VALID ( s_axi_bvalid_i ) ,
.M_READY ( s_axi_bready )
);
end else begin : gen_b_async_conv
fifo_generator_v13_0_1 #(
.C_COMMON_CLOCK(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_DIN_WIDTH_WACH(63),
.C_DIN_WIDTH_WDCH(38),
.C_DIN_WIDTH_WRCH(3),
.C_DIN_WIDTH_RACH(63),
.C_DIN_WIDTH_RDCH(36),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(2),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(32),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(5),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(29),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) dw_fifogen_b_async (
.m_aclk(m_axi_aclk),
.s_aclk(s_axi_aclk),
.s_aresetn(sm_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp_i),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid_i),
.s_axi_bready(s_axi_bready),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(5'b0),
.axi_b_prog_empty_thresh(5'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
end else begin : gen_b_passthru
assign m_axi_bready = s_axi_bready;
assign s_axi_bresp_i = m_axi_bresp;
assign s_axi_bvalid_i = m_axi_bvalid;
end // gen_b
end else begin : NO_WRITE
assign sr_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
assign m_axi_wvalid = 1'b0;
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i ;
wire [8-1:0] m_axi_arlen_i ;
wire [3-1:0] m_axi_arsize_i ;
wire [2-1:0] m_axi_arburst_i ;
wire [2-1:0] m_axi_arlock_i ;
wire [4-1:0] m_axi_arcache_i ;
wire [3-1:0] m_axi_arprot_i ;
wire [4-1:0] m_axi_arregion_i ;
wire [4-1:0] m_axi_arqos_i ;
wire m_axi_arvalid_i ;
wire m_axi_arready_i ;
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [C_AXI_ADDR_WIDTH-1:0] rd_cmd_si_addr;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_si_id;
wire [8-1:0] rd_cmd_si_len;
wire [3-1:0] rd_cmd_si_size;
wire [2-1:0] rd_cmd_si_burst;
// Read Address Channel.
axi_dwidth_converter_v2_1_7_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
// .C_FIFO_MODE (0),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (P_RID_QUEUE),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_arid),
.S_AXI_AADDR (sr_araddr),
.S_AXI_ALEN (sr_arlen),
.S_AXI_ASIZE (sr_arsize),
.S_AXI_ABURST (sr_arburst),
.S_AXI_ALOCK (sr_arlock),
.S_AXI_ACACHE (sr_arcache),
.S_AXI_APROT (sr_arprot),
.S_AXI_AREGION (sr_arregion),
.S_AXI_AQOS (sr_arqos),
.S_AXI_AVALID (sr_arvalid),
.S_AXI_AREADY (sr_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i ),
.M_AXI_ALEN (m_axi_arlen_i ),
.M_AXI_ASIZE (m_axi_arsize_i ),
.M_AXI_ABURST (m_axi_arburst_i ),
.M_AXI_ALOCK (m_axi_arlock_i ),
.M_AXI_ACACHE (m_axi_arcache_i ),
.M_AXI_APROT (m_axi_arprot_i ),
.M_AXI_AREGION (m_axi_arregion_i ),
.M_AXI_AQOS (m_axi_arqos_i ),
.M_AXI_AVALID (m_axi_arvalid_i ),
.M_AXI_AREADY (m_axi_arready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_r_upsizer
// Packet FIFO Read Data channel.
axi_dwidth_converter_v2_1_7_r_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_read_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_ARADDR (m_axi_araddr_i ),
.S_AXI_ARLEN (m_axi_arlen_i ),
.S_AXI_ARSIZE (m_axi_arsize_i ),
.S_AXI_ARBURST (m_axi_arburst_i ),
.S_AXI_ARLOCK (m_axi_arlock_i ),
.S_AXI_ARCACHE (m_axi_arcache_i ),
.S_AXI_ARPROT (m_axi_arprot_i ),
.S_AXI_ARREGION (m_axi_arregion_i ),
.S_AXI_ARQOS (m_axi_arqos_i ),
.S_AXI_ARVALID (m_axi_arvalid_i ),
.S_AXI_ARREADY (m_axi_arready_i ),
// Master Interface Write Address Port
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARREGION (m_axi_arregion),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
// Slave Interface Write Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Write Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_r_upsizer
// Read Data channel.
axi_dwidth_converter_v2_1_7_r_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (mr_rdata),
.M_AXI_RRESP (mr_rresp),
.M_AXI_RLAST (mr_rlast),
.M_AXI_RVALID (mr_rvalid),
.M_AXI_RREADY (mr_rready)
);
axi_register_slice_v2_1_7_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (0),
.C_AXI_ID_WIDTH (1),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_R (C_M_AXI_R_REGISTER)
)
mi_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (m_aclk),
.s_axi_awid ( 1'b0 ),
.s_axi_awaddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_awlen ( 8'b0 ),
.s_axi_awsize ( 3'b0 ),
.s_axi_awburst ( 2'b0 ),
.s_axi_awlock ( 1'b0 ),
.s_axi_awcache ( 4'b0 ),
.s_axi_awprot ( 3'b0 ),
.s_axi_awregion ( 4'b0 ),
.s_axi_awqos ( 4'b0 ),
.s_axi_awuser ( 1'b0 ),
.s_axi_awvalid ( 1'b0 ),
.s_axi_awready ( ),
.s_axi_wid ( 1'b0 ),
.s_axi_wdata ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid ( 1'b0 ),
.s_axi_araddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_arlen ( 8'b0 ),
.s_axi_arsize ( 3'b0 ),
.s_axi_arburst ( 2'b0 ),
.s_axi_arlock ( 1'b0 ),
.s_axi_arcache ( 4'b0 ),
.s_axi_arprot ( 3'b0 ),
.s_axi_arregion ( 4'b0 ),
.s_axi_arqos ( 4'b0 ),
.s_axi_aruser ( 1'b0 ),
.s_axi_arvalid ( 1'b0 ),
.s_axi_arready ( ),
.s_axi_rid (),
.s_axi_rdata (mr_rdata ),
.s_axi_rresp (mr_rresp ),
.s_axi_rlast (mr_rlast ),
.s_axi_ruser (),
.s_axi_rvalid (mr_rvalid ),
.s_axi_rready (mr_rready ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready (1'b0),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready (1'b0),
.m_axi_rid (1'b0 ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_ruser (1'b0 ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready_i )
);
assign m_axi_araddr = m_axi_araddr_i ;
assign m_axi_arlen = m_axi_arlen_i ;
assign m_axi_arsize = m_axi_arsize_i ;
assign m_axi_arburst = m_axi_arburst_i ;
assign m_axi_arlock = m_axi_arlock_i ;
assign m_axi_arcache = m_axi_arcache_i ;
assign m_axi_arprot = m_axi_arprot_i ;
assign m_axi_arregion = m_axi_arregion_i ;
assign m_axi_arqos = m_axi_arqos_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_arready_i = m_axi_arready ;
assign m_axi_rready = m_axi_rready_i;
end // gen_r_upsizer
end else begin : NO_READ
assign sr_arready = 1'b0;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
assign mr_rready = 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic single-channel AXI FIFO
// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
// Transfers received on the AXI slave port are pushed onto the FIFO.
// FIFO output, when available, is presented on the AXI master port and
// popped when the master port responds (M_READY).
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_fifo
// fifo_gen
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_12_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the fifo_generator wrapper file when simulating
// the core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v13_1_4 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_12_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Interface outputs are synchronized using ordinary flops for improved timing.
//--------------------------------------------------------------------------
// Structure:
// axic_reg_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i = 1'b0;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_12_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_ndeep_srl #
(
parameter C_FAMILY = "rtl", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam integer P_SRLASIZE = 5;
localparam integer P_SRLDEPTH = 32;
localparam integer P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
localparam integer P_SHIFT_DEPTH = 2**C_A_WIDTH;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
if (C_FAMILY == "rtl") begin : gen_rtl_shifter
if (C_A_WIDTH <= P_SRLASIZE) begin : gen_inferred_srl
reg [P_SRLDEPTH-1:0] shift_reg = {P_SRLDEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SRLDEPTH-2:0], D};
assign Q = shift_reg[a_i];
end else begin : gen_logic_shifter // Very wasteful
reg [P_SHIFT_DEPTH-1:0] shift_reg = {P_SHIFT_DEPTH{1'b0}};
always @(posedge CLK)
if (CE)
shift_reg <= {shift_reg[P_SHIFT_DEPTH-2:0], D};
assign Q = shift_reg[a_i];
end
end else begin : gen_primitive_shifter
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_0_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
end
endgenerate
endmodule
`default_nettype wire
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI data fifo module:
// 5-channel memory-mapped AXI4 interfaces.
// SRL or BRAM based FIFO on AXI W and/or R channels.
// FIFO to accommodate various data flow rates through the AXI interconnect
//
// Verilog-standard: Verilog 2001
//-----------------------------------------------------------------------------
//
// Structure:
// axi_data_fifo
// fifo_generator
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_12_axi_data_fifo #
(
parameter C_FAMILY = "virtex7",
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_WRITE_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_WRITE_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_WRITE_FIFO_DELAY = 0, // 0 = No, 1 = Yes
// Indicates whether AWVALID and WVALID assertion is delayed until:
// a. the corresponding WLAST is stored in the FIFO, or
// b. no WLAST is stored and the FIFO is full.
// 0 means AW channel is pass-through and
// WVALID is asserted whenever FIFO is not empty.
parameter integer C_AXI_READ_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_READ_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_READ_FIFO_DELAY = 0) // 0 = No, 1 = Yes
// Indicates whether ARVALID assertion is delayed until the
// the remaining vacancy of the FIFO is at least the burst length
// as indicated by ARLEN.
// 0 means AR channel is pass-through.
// System Signals
(input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready);
localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;
localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;
localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;
localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;
localparam P_PRIM_FIFO_TYPE = "512x72" ;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;
localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
generate
if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign s_axi_awready = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_wready = m_axi_wready;
assign s_axi_bid = m_axi_bid;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_buser = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_rid = m_axi_rid;
assign s_axi_rdata = m_axi_rdata;
assign s_axi_rresp = m_axi_rresp;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_ruser = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = s_axi_rready;
end else begin : gen_fifo
wire [4-1:0] s_axi_awregion_i;
wire [4-1:0] s_axi_arregion_i;
wire [4-1:0] m_axi_awregion_i;
wire [4-1:0] m_axi_arregion_i;
wire [C_AXI_ID_WIDTH-1:0] s_axi_wid_i;
wire [C_AXI_ID_WIDTH-1:0] m_axi_wid_i;
assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;
assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;
assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;
assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;
assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};
assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};
fifo_generator_v13_1_4 #(
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
.C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_BUSER(1),
.C_HAS_AXI_RUSER(1),
.C_HAS_AXI_WUSER(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
.C_DIN_WIDTH_RACH(P_WIDTH_RACH),
.C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),
.C_DIN_WIDTH_WACH(P_WIDTH_WACH),
.C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),
.C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),
.C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),
.C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),
.C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),
.C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),
.C_WRCH_TYPE(2),
.C_COMMON_CLOCK(1),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(1),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.s_aclk(aclk),
.s_aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awregion(s_axi_awregion_i),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid_i),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awregion(m_axi_awregion_i),
.m_axi_awuser(m_axi_awuser),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid_i),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arregion(s_axi_arregion_i),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arregion(m_axi_arregion_i),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_aclk(aclk),
.m_aclk_en(1'b1),
.s_aclk_en(1'b1),
.s_axi_wuser(s_axi_wuser),
.s_axi_buser(s_axi_buser),
.m_axi_wuser(m_axi_wuser),
.m_axi_buser(m_axi_buser),
.s_axi_aruser(s_axi_aruser),
.s_axi_ruser(s_axi_ruser),
.m_axi_aruser(m_axi_aruser),
.m_axi_ruser(m_axi_ruser),
.almost_empty(),
.almost_full(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_prog_full(),
.axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_prog_full(),
.axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(),
.dbiterr(),
.din(18'b0),
.dout(),
.empty(),
.full(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full(),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.rd_clk(1'b0),
.rd_data_count(),
.rd_en(1'b0),
.rd_rst(1'b0),
.rst(1'b0),
.sbiterr(),
.srst(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_clk(1'b0),
.wr_data_count(),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
endgenerate
endmodule
|
module wb_arbiter_tb
#(parameter NUM_MASTERS = 5)
(input wb_clk_i,
input wb_rst_i,
output done);
localparam aw = 32;
localparam dw = 32;
localparam MEMORY_SIZE_BITS = 8;
localparam MEMORY_SIZE_WORDS = 2**MEMORY_SIZE_BITS;
wire [aw-1:0] wbs_m2s_adr;
wire [dw-1:0] wbs_m2s_dat;
wire [3:0] wbs_m2s_sel;
wire wbs_m2s_we ;
wire wbs_m2s_cyc;
wire wbs_m2s_stb;
wire [2:0] wbs_m2s_cti;
wire [1:0] wbs_m2s_bte;
wire [dw-1:0] wbs_s2m_dat;
wire wbs_s2m_ack;
wire wbs_s2m_err;
wire wbs_s2m_rty;
wire [NUM_MASTERS*aw-1:0] wbm_m2s_adr;
wire [NUM_MASTERS*dw-1:0] wbm_m2s_dat;
wire [NUM_MASTERS*4-1:0] wbm_m2s_sel;
wire [NUM_MASTERS-1:0] wbm_m2s_we ;
wire [NUM_MASTERS-1:0] wbm_m2s_cyc;
wire [NUM_MASTERS-1:0] wbm_m2s_stb;
wire [NUM_MASTERS*3-1:0] wbm_m2s_cti;
wire [NUM_MASTERS*2-1:0] wbm_m2s_bte;
wire [NUM_MASTERS*dw-1:0] wbm_s2m_dat;
wire [NUM_MASTERS-1:0] wbm_s2m_ack;
wire [NUM_MASTERS-1:0] wbm_s2m_err;
wire [NUM_MASTERS-1:0] wbm_s2m_rty;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wire [NUM_MASTERS-1:0] done_int;
genvar i;
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : masters
wb_bfm_transactor
#(.MEM_HIGH((i+1)*MEMORY_SIZE_WORDS-1),
.MEM_LOW (i*MEMORY_SIZE_WORDS))
wb_bfm_transactor0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wbm_m2s_adr[i*aw+:aw]),
.wb_dat_o (wbm_m2s_dat[i*dw+:dw]),
.wb_sel_o (wbm_m2s_sel[i*4+:4]),
.wb_we_o (wbm_m2s_we[i] ),
.wb_cyc_o (wbm_m2s_cyc[i]),
.wb_stb_o (wbm_m2s_stb[i]),
.wb_cti_o (wbm_m2s_cti[i*3+:3]),
.wb_bte_o (wbm_m2s_bte[i*2+:2]),
.wb_dat_i (wbm_s2m_dat[i*dw+:dw]),
.wb_ack_i (wbm_s2m_ack[i]),
.wb_err_i (wbm_s2m_err[i]),
.wb_rty_i (wbm_s2m_rty[i]),
//Test Control
.done(done_int[i]));
end // block: slaves
endgenerate
integer idx;
assign done = &done_int;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
for(idx=0;idx<NUM_MASTERS;idx=idx+1)
$display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
$display("All tests passed!");
end
end
wb_arbiter
#(.num_masters(NUM_MASTERS))
wb_arbiter0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
// Master Interface
.wbm_adr_i (wbm_m2s_adr),
.wbm_dat_i (wbm_m2s_dat),
.wbm_sel_i (wbm_m2s_sel),
.wbm_we_i (wbm_m2s_we ),
.wbm_cyc_i (wbm_m2s_cyc),
.wbm_stb_i (wbm_m2s_stb),
.wbm_cti_i (wbm_m2s_cti),
.wbm_bte_i (wbm_m2s_bte),
.wbm_dat_o (wbm_s2m_dat),
.wbm_ack_o (wbm_s2m_ack),
.wbm_err_o (wbm_s2m_err),
.wbm_rty_o (wbm_s2m_rty),
// Wishbone Slave interface
.wbs_adr_o (wbs_m2s_adr),
.wbs_dat_o (wbs_m2s_dat),
.wbs_sel_o (wbs_m2s_sel),
.wbs_we_o (wbs_m2s_we),
.wbs_cyc_o (wbs_m2s_cyc),
.wbs_stb_o (wbs_m2s_stb),
.wbs_cti_o (wbs_m2s_cti),
.wbs_bte_o (wbs_m2s_bte),
.wbs_dat_i (wbs_s2m_dat),
.wbs_ack_i (wbs_s2m_ack),
.wbs_err_i (wbs_s2m_err),
.wbs_rty_i (wbs_s2m_rty));
assign slave_writes = wb_mem_model0.writes;
assign slave_reads = wb_mem_model0.reads;
time start_time[NUM_MASTERS-1:0];
time ack_delay[NUM_MASTERS-1:0];
integer num_transactions[NUM_MASTERS-1:0];
generate
for(i=0;i<NUM_MASTERS;i=i+1) begin : wait_time
initial begin
ack_delay[i] = 0;
num_transactions[i] = 0;
while(1) begin
@(posedge wbm_m2s_cyc[i]);
start_time[i] = $time;
@(posedge wbm_s2m_ack[i]);
ack_delay[i] = ack_delay[i] + $time-start_time[i];
num_transactions[i] = num_transactions[i]+1;
end
end
end
endgenerate
wb_bfm_memory #(.DEBUG (0),
.mem_size_bytes(MEMORY_SIZE_WORDS*(dw/8)*NUM_MASTERS))
wb_mem_model0
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_i (wbs_m2s_adr),
.wb_dat_i (wbs_m2s_dat),
.wb_sel_i (wbs_m2s_sel),
.wb_we_i (wbs_m2s_we),
.wb_cyc_i (wbs_m2s_cyc),
.wb_stb_i (wbs_m2s_stb),
.wb_cti_i (wbs_m2s_cti),
.wb_bte_i (wbs_m2s_bte),
.wb_dat_o (wbs_s2m_dat),
.wb_ack_o (wbs_s2m_ack),
.wb_err_o (wbs_s2m_err),
.wb_rty_o (wbs_s2m_rty));
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "/auto/home-scf-07/zhiyango/ee577b/projs/processor/syn/src/control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:15]=reg_A[0:7]*reg_B[0:7];
result[16:31]=reg_A[16:23]*reg_B[16:23];
result[32:47]=reg_A[32:39]*reg_B[32:39];
result[48:63]=reg_A[48:55]*reg_B[48:55];
result[64:79]=reg_A[64:71]*reg_B[64:71];
result[80:95]=reg_A[80:87]*reg_B[80:87];
result[96:111]=reg_A[96:103]*reg_B[96:103];
result[112:127]=reg_A[112:119]*reg_B[112:119];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:31]=reg_A[0:15]*reg_B[0:15];
result[32:63]=reg_A[32:47]*reg_B[32:47];
result[64:95]=reg_A[64:79]*reg_B[64:79];
result[96:127]=reg_A[96:111]*reg_B[96:111];
end
default: // aluwsrl AND `aa AND Default
begin
result=128'd0;
end
endcase
end
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:15]=reg_A[8:15]*reg_B[8:15];
result[16:31]=reg_A[24:31]*reg_B[24:31];
result[32:47]=reg_A[40:47]*reg_B[40:47];
result[48:63]=reg_A[56:63]*reg_B[56:63];
result[64:79]=reg_A[72:79]*reg_B[72:79];
result[80:95]=reg_A[88:95]*reg_B[88:95];
result[96:111]=reg_A[104:111]*reg_B[104:111];
result[112:127]=reg_A[120:127]*reg_B[120:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:31]=reg_A[16:31]*reg_B[16:31];
result[32:63]=reg_A[48:63]*reg_B[48:63];
result[64:95]=reg_A[80:95]*reg_B[80:95];
result[96:127]=reg_A[112:127]*reg_B[112:127];
end
default: // aluwsrl AND `aa AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../top/config.vh"
module dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
input [13:0] tx_i_i;
input [13:0] tx_q_i;
output [13:0] tx_data_o;
output tx_sync_o;
`ifdef TX_RATE_MAX
wire clk128;
reg clk64_d;
reg [13:0] tx_data_o;
// Create a 128 MHz clock
dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
// Register the clk64 clock in the clk128 domain
always @(posedge clk128)
clk64_d <= #1 clk_i;
// Register the tx data in the clk128 domain
always @(posedge clk128)
tx_data_o <= #1 clk64_d ? tx_i_i : tx_q_i;
assign tx_sync_o = clk64_d;
`else // !`ifdef TX_RATE_MAX
assign tx_data_o = strobe_i ? tx_q_i : tx_i_i;
assign tx_sync_o = strobe_i;
`endif // !`ifdef TX_RATE_MAX
endmodule // dac_interface
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_pio_0 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: crossbar.v
//
// Description:
// This module is a M-master to N-slave AXI axi_crossbar_v2_1_crossbar switch.
// The interface of this module consists of a vectored slave and master interface
// in which all slots are sized and synchronized to the native width and clock
// of the interconnect.
// The SAMD axi_crossbar_v2_1_crossbar supports only AXI4 and AXI3 protocols.
// All width, clock and protocol conversions are done outside this block, as are
// any pipeline registers or data FIFOs.
// This module contains all arbitration, decoders and channel multiplexing logic.
// It also contains the diagnostic registers and control interface.
//
//-----------------------------------------------------------------------------
//
// Structure:
// crossbar
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
// splitter
// wdata_router
// axic_reg_srl_fifo
// wdata_mux
// axic_reg_srl_fifo
// mux_enc
// addr_decoder
// comparator_static
// axic_srl_fifo
// axi_register_slice
// addr_arbiter
// mux_enc
// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_crossbar #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_SLAVE_SLOTS = 1,
parameter integer C_NUM_MASTER_SLOTS = 1,
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_PROTOCOL = 0,
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_BASE_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*64-1:0] C_S_AXI_HIGH_ID = {C_NUM_SLAVE_SLOTS*64{1'b0}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_WRITE = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_SLAVE_SLOTS-1:0] C_S_AXI_SUPPORTS_READ = {C_NUM_SLAVE_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_WRITE = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS-1:0] C_M_AXI_SUPPORTS_READ = {C_NUM_MASTER_SLOTS{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = {C_NUM_MASTER_SLOTS*32{1'b1}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = {C_NUM_SLAVE_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = {C_NUM_MASTER_SLOTS{32'h00000001}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE = 0,
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_W_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [(C_NUM_MASTER_SLOTS+1)*32-1:0] C_R_ISSUE_WIDTH = {C_NUM_MASTER_SLOTS+1{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_W_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_R_ACCEPT_WIDTH = {C_NUM_SLAVE_SLOTS{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_AWLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_AWLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_AWPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_AWQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WLAST,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_BRESP,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [C_NUM_SLAVE_SLOTS*8-1:0] S_AXI_ARLEN,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARSIZE,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARBURST,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_ARLOCK,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARCACHE,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] S_AXI_ARPROT,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARREGION,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] S_AXI_ARQOS,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARVALID,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] S_AXI_RRESP,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RLAST,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RVALID,
input wire [C_NUM_SLAVE_SLOTS-1:0] S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_AWLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_AWLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_AWPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_AWQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WLAST,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_BRESP,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [C_NUM_MASTER_SLOTS*8-1:0] M_AXI_ARLEN,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARSIZE,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARBURST,
output wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_ARLOCK,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARCACHE,
output wire [C_NUM_MASTER_SLOTS*3-1:0] M_AXI_ARPROT,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARREGION,
output wire [C_NUM_MASTER_SLOTS*4-1:0] M_AXI_ARQOS,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARVALID,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [C_NUM_MASTER_SLOTS*2-1:0] M_AXI_RRESP,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RLAST,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RVALID,
output wire [C_NUM_MASTER_SLOTS-1:0] M_AXI_RREADY
);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_NUM_MASTER_SLOTS_LOG = f_ceil_log2(C_NUM_MASTER_SLOTS);
localparam integer P_NUM_SLAVE_SLOTS_LOG = f_ceil_log2((C_NUM_SLAVE_SLOTS>1) ? C_NUM_SLAVE_SLOTS : 2);
localparam integer P_AXI_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 1;
localparam integer P_ST_AWMESG_WIDTH = 2+4+4 + C_AXI_AWUSER_WIDTH;
localparam integer P_AA_AWMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_AWMESG_WIDTH;
localparam integer P_ST_ARMESG_WIDTH = 2+4+4 + C_AXI_ARUSER_WIDTH;
localparam integer P_AA_ARMESG_WIDTH = C_AXI_ID_WIDTH + C_AXI_ADDR_WIDTH + 8+3+2+3+4 + P_ST_ARMESG_WIDTH;
localparam integer P_ST_BMESG_WIDTH = 2 + C_AXI_BUSER_WIDTH;
localparam integer P_ST_RMESG_WIDTH = 2 + C_AXI_RUSER_WIDTH + C_AXI_DATA_WIDTH;
localparam integer P_WR_WMESG_WIDTH = C_AXI_DATA_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_WUSER_WIDTH + P_AXI_WID_WIDTH;
localparam [31:0] P_BYPASS = 32'h00000000;
localparam [31:0] P_FWD_REV = 32'h00000001;
localparam [31:0] P_SIMPLE = 32'h00000007;
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_READ = {1'b1, C_M_AXI_SUPPORTS_READ[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)-1:0] P_M_AXI_SUPPORTS_WRITE = {1'b1, C_M_AXI_SUPPORTS_WRITE[0+:C_NUM_MASTER_SLOTS]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_WRITE_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_CONNECTIVITY = {{32{1'b1}}, C_M_AXI_READ_CONNECTIVITY[0+:C_NUM_MASTER_SLOTS*32]};
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_WRITE_CONNECTIVITY = f_si_write_connectivity(0);
localparam [C_NUM_SLAVE_SLOTS*32-1:0] P_S_AXI_READ_CONNECTIVITY = f_si_read_connectivity(0);
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_READ_ISSUING = {32'h00000001, C_M_AXI_READ_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam [(C_NUM_MASTER_SLOTS+1)*32-1:0] P_M_AXI_WRITE_ISSUING = {32'h00000001, C_M_AXI_WRITE_ISSUING[0+:C_NUM_MASTER_SLOTS*32]};
localparam P_DECERR = 2'b11;
//---------------------------------------------------------------------------
// Functions
//---------------------------------------------------------------------------
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID (RNG00) to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID
(
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer slot
);
begin
f_extend_ID = C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] | (s_id & (C_S_AXI_BASE_ID[slot*64+:C_AXI_ID_WIDTH] ^ C_S_AXI_HIGH_ID[slot*64+:C_AXI_ID_WIDTH]));
end
endfunction
// Write connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_write_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_WRITE_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_write_connectivity = result;
end
endfunction
// Read connectivity array transposed
function [C_NUM_SLAVE_SLOTS*32-1:0] f_si_read_connectivity
(
input integer null_arg
);
integer si_slot;
integer mi_slot;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS*32{1'b1}};
for (si_slot=0; si_slot<C_NUM_SLAVE_SLOTS; si_slot=si_slot+1) begin
for (mi_slot=0; mi_slot<C_NUM_MASTER_SLOTS; mi_slot=mi_slot+1) begin
result[si_slot*32+mi_slot] = C_M_AXI_READ_CONNECTIVITY[mi_slot*32+si_slot];
end
end
f_si_read_connectivity = result;
end
endfunction
genvar gen_si_slot;
genvar gen_mi_slot;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] si_st_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_AWMESG_WIDTH-1:0] st_tmp_awmesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_AWMESG_WIDTH-1:0] tmp_aa_awmesg ;
wire [P_AA_AWMESG_WIDTH-1:0] aa_mi_awmesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_awlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_awprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_awregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_awerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_awtarget_enc ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_wm_awgrant_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_awtarget_hot ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_awvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_ss_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_wr_awready ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] ss_aa_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] sa_wm_awready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awready ;
wire aa_sa_awvalid ;
wire aa_sa_awready ;
wire aa_mi_arready ;
wire mi_awvalid_en ;
wire sa_wm_awvalid_en ;
wire sa_wm_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] si_st_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_ST_ARMESG_WIDTH-1:0] st_tmp_armesg ;
wire [C_NUM_SLAVE_SLOTS*P_AA_ARMESG_WIDTH-1:0] tmp_aa_armesg ;
wire [P_AA_ARMESG_WIDTH-1:0] aa_mi_armesg ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] st_aa_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] st_aa_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] st_aa_arlock ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] st_aa_arprot ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] st_aa_arregion ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] st_aa_arerror ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_aa_artarget_hot ;
wire [C_NUM_SLAVE_SLOTS*(P_NUM_MASTER_SLOTS_LOG+1)-1:0] st_aa_artarget_enc ;
wire [(C_NUM_MASTER_SLOTS+1)-1:0] aa_mi_artarget_hot ;
wire [P_NUM_SLAVE_SLOTS_LOG*1-1:0] aa_mi_argrant_enc ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid_qual ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arvalid ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] st_aa_arready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_arready ;
wire aa_mi_arvalid ;
wire mi_awready_mux ;
wire [C_NUM_SLAVE_SLOTS*P_ST_BMESG_WIDTH-1:0] st_si_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_BMESG_WIDTH-1:0] st_mr_bmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] st_mr_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_bid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_bid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] bid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_bid ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_bresp ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_BUSER_WIDTH-1:0] mi_buser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_bready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] bready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_ST_RMESG_WIDTH-1:0] st_si_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*P_ST_RMESG_WIDTH-1:0] st_mr_rmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] st_mr_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] st_mr_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] st_mr_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] st_mr_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] st_mr_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] st_tmp_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_mr_rid_target ;
wire [(C_NUM_MASTER_SLOTS+1)*P_NUM_SLAVE_SLOTS_LOG-1:0] debug_rid_target_i ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] rid_match ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_rid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_rdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_RUSER_WIDTH-1:0] mi_ruser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rlast ;
wire [(C_NUM_MASTER_SLOTS+1)*2-1:0] mi_rresp ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_rready ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] rready_carry ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] si_wr_wmesg ;
wire [C_NUM_SLAVE_SLOTS*P_WR_WMESG_WIDTH-1:0] wr_wm_wmesg ;
wire [C_NUM_SLAVE_SLOTS*1-1:0] wr_wm_wlast ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wvalid ;
wire [C_NUM_SLAVE_SLOTS*(C_NUM_MASTER_SLOTS+1)-1:0] wr_tmp_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_NUM_SLAVE_SLOTS-1:0] tmp_wm_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*P_WR_WMESG_WIDTH-1:0] wm_mr_wmesg ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] wm_mr_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] wm_mr_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] wm_mr_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] wm_mr_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] wm_mr_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH-1:0] mi_wdata ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_DATA_WIDTH/8-1:0] mi_wstrb ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_WUSER_WIDTH-1:0] mi_wuser ;
wire [(C_NUM_MASTER_SLOTS+1)*C_AXI_ID_WIDTH-1:0] mi_wid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wlast ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wvalid ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_wready ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] w_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_push ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] r_cmd_pop ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_awmaxissuing ;
wire [(C_NUM_MASTER_SLOTS+1)*1-1:0] mi_armaxissuing ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] w_issuing_cnt ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] r_issuing_cnt ;
reg [8-1:0] debug_aw_trans_seq_i ;
reg [8-1:0] debug_ar_trans_seq_i ;
wire [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_trans_seq_i ;
reg [(C_NUM_MASTER_SLOTS+1)*8-1:0] debug_w_beat_cnt_i ;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (~ARESETN) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ARESETN;
end
end
wire reset;
assign reset = ~aresetn_d;
generate
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_slave_slots
if (C_S_AXI_SUPPORTS_READ[gen_si_slot]) begin : gen_si_read
axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (read channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_READ),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_R_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_ARMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_RMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_READ_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_ar
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_ARID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_ARADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_ARLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_ARSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_ARBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_ARLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_ARPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_ARREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.S_AVALID (S_AXI_ARVALID[gen_si_slot]),
.S_AREADY (S_AXI_ARREADY[gen_si_slot]),
.M_AID (st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_arlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_arsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_arlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_arprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_arregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_artarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_arerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_arvalid_qual[gen_si_slot]),
.M_AVALID (st_aa_arvalid[gen_si_slot]),
.M_AREADY (st_aa_arready[gen_si_slot]),
.S_RID (S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH]),
.S_RLAST (S_AXI_RLAST[gen_si_slot]),
.S_RVALID (S_AXI_RVALID[gen_si_slot]),
.S_RREADY (S_AXI_RREADY[gen_si_slot]),
.M_RID (st_mr_rid),
.M_RLAST (st_mr_rlast),
.M_RMESG (st_mr_rmesg),
.M_RVALID (st_mr_rvalid),
.M_RREADY (st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_ar_trans_seq_i : 8'h0)
);
assign si_st_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH] = {
S_AXI_ARUSER[gen_si_slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH],
S_AXI_ARQOS[gen_si_slot*4+:4],
S_AXI_ARCACHE[gen_si_slot*4+:4],
S_AXI_ARBURST[gen_si_slot*2+:2]
};
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = {
st_tmp_armesg[gen_si_slot*P_ST_ARMESG_WIDTH+:P_ST_ARMESG_WIDTH],
st_aa_arregion[gen_si_slot*4+:4],
st_aa_arprot[gen_si_slot*3+:3],
st_aa_arlock[gen_si_slot*2+:2],
st_aa_arsize[gen_si_slot*3+:3],
st_aa_arlen[gen_si_slot*8+:8],
st_aa_araddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_arid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_RRESP[gen_si_slot*2+:2] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+:2];
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2 +: C_AXI_RUSER_WIDTH];
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = st_si_rmesg[gen_si_slot*P_ST_RMESG_WIDTH+2+C_AXI_RUSER_WIDTH +: C_AXI_DATA_WIDTH];
end else begin : gen_no_si_read
assign S_AXI_ARREADY[gen_si_slot] = 1'b0;
assign st_aa_arvalid[gen_si_slot] = 1'b0;
assign st_aa_arvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_armesg[gen_si_slot*P_AA_ARMESG_WIDTH+:P_AA_ARMESG_WIDTH] = 0;
assign S_AXI_RID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_RRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_RUSER[gen_si_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign S_AXI_RDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign S_AXI_RVALID[gen_si_slot] = 1'b0;
assign S_AXI_RLAST[gen_si_slot] = 1'b0;
assign st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_artarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_read
if (C_S_AXI_SUPPORTS_WRITE[gen_si_slot]) begin : gen_si_write
axi_crossbar_v2_1_si_transactor # // "ST": SI Transactor (write channel)
(
.C_FAMILY (C_FAMILY),
.C_SI (gen_si_slot),
.C_DIR (P_WRITE),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_NUM_M (C_NUM_MASTER_SLOTS),
.C_NUM_M_LOG (P_NUM_MASTER_SLOTS_LOG),
.C_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE[gen_si_slot*32+:32]),
.C_ACCEPTANCE_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:32]),
.C_ID_WIDTH (C_AXI_ID_WIDTH),
.C_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH[gen_si_slot*32+:32]),
.C_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AMESG_WIDTH (P_ST_AWMESG_WIDTH),
.C_RMESG_WIDTH (P_ST_BMESG_WIDTH),
.C_BASE_ID (C_S_AXI_BASE_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_HIGH_ID (C_S_AXI_HIGH_ID[gen_si_slot*64+:C_AXI_ID_WIDTH]),
.C_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD[gen_si_slot*32+:32]),
.C_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_HIGH_ADDR (C_M_AXI_HIGH_ADDR),
.C_TARGET_QUAL (P_S_AXI_WRITE_CONNECTIVITY[gen_si_slot*32+:C_NUM_MASTER_SLOTS]),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (C_RANGE_CHECK),
.C_ADDR_DECODE (C_ADDR_DECODE),
.C_ERR_MODE (C_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
si_transactor_aw
(
.ACLK (ACLK),
.ARESET (reset),
.S_AID (f_extend_ID(S_AXI_AWID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot)),
.S_AADDR (S_AXI_AWADDR[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.S_ALEN (S_AXI_AWLEN[gen_si_slot*8+:8]),
.S_ASIZE (S_AXI_AWSIZE[gen_si_slot*3+:3]),
.S_ABURST (S_AXI_AWBURST[gen_si_slot*2+:2]),
.S_ALOCK (S_AXI_AWLOCK[gen_si_slot*2+:2]),
.S_APROT (S_AXI_AWPROT[gen_si_slot*3+:3]),
// .S_AREGION (S_AXI_AWREGION[gen_si_slot*4+:4]),
.S_AMESG (si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.S_AVALID (S_AXI_AWVALID[gen_si_slot]),
.S_AREADY (S_AXI_AWREADY[gen_si_slot]),
.M_AID (st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.M_AADDR (st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH]),
.M_ALEN (st_aa_awlen[gen_si_slot*8+:8]),
.M_ASIZE (st_aa_awsize[gen_si_slot*3+:3]),
.M_ALOCK (st_aa_awlock[gen_si_slot*2+:2]),
.M_APROT (st_aa_awprot[gen_si_slot*3+:3]),
.M_AREGION (st_aa_awregion[gen_si_slot*4+:4]),
.M_AMESG (st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH]),
.M_ATARGET_HOT (st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_ATARGET_ENC (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]),
.M_AERROR (st_aa_awerror[gen_si_slot*8+:8]),
.M_AVALID_QUAL (st_aa_awvalid_qual[gen_si_slot]),
.M_AVALID (st_ss_awvalid[gen_si_slot]),
.M_AREADY (st_ss_awready[gen_si_slot]),
.S_RID (S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_RMESG (st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH]),
.S_RLAST (),
.S_RVALID (S_AXI_BVALID[gen_si_slot]),
.S_RREADY (S_AXI_BREADY[gen_si_slot]),
.M_RID (st_mr_bid),
.M_RLAST ({(C_NUM_MASTER_SLOTS+1){1'b1}}),
.M_RMESG (st_mr_bmesg),
.M_RVALID (st_mr_bvalid),
.M_RREADY (st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_RTARGET (st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.DEBUG_A_TRANS_SEQ (C_DEBUG ? debug_aw_trans_seq_i : 8'h0)
);
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign si_st_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH] = {
S_AXI_AWUSER[gen_si_slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH],
S_AXI_AWQOS[gen_si_slot*4+:4],
S_AXI_AWCACHE[gen_si_slot*4+:4],
S_AXI_AWBURST[gen_si_slot*2+:2]
};
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = {
st_tmp_awmesg[gen_si_slot*P_ST_AWMESG_WIDTH+:P_ST_AWMESG_WIDTH],
st_aa_awregion[gen_si_slot*4+:4],
st_aa_awprot[gen_si_slot*3+:3],
st_aa_awlock[gen_si_slot*2+:2],
st_aa_awsize[gen_si_slot*3+:3],
st_aa_awlen[gen_si_slot*8+:8],
st_aa_awaddr[gen_si_slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH],
st_aa_awid[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]
};
assign S_AXI_BRESP[gen_si_slot*2+:2] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+:2];
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = st_si_bmesg[gen_si_slot*P_ST_BMESG_WIDTH+2 +: C_AXI_BUSER_WIDTH];
// AW SI-transactor transfer completes upon completion of both W-router address acceptance (command push) and AW arbitration
axi_crossbar_v2_1_splitter # // "SS": Splitter from SI-Transactor (write channel)
(
.C_NUM_M (2)
)
splitter_aw_si
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (st_ss_awvalid[gen_si_slot]),
.S_READY (st_ss_awready[gen_si_slot]),
.M_VALID ({ss_wr_awvalid[gen_si_slot], ss_aa_awvalid[gen_si_slot]}),
.M_READY ({ss_wr_awready[gen_si_slot], ss_aa_awready[gen_si_slot]})
);
axi_crossbar_v2_1_wdata_router # // "WR": Write data Router
(
.C_FAMILY (C_FAMILY),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS+1),
.C_SELECT_WIDTH (P_NUM_MASTER_SLOTS_LOG+1),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ACCEPT_WIDTH[gen_si_slot*32+:6])
)
wdata_router_w
(
.ACLK (ACLK),
.ARESET (reset),
// Write transfer input from the current SI-slot
.S_WMESG (si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.S_WLAST (S_AXI_WLAST[gen_si_slot]),
.S_WVALID (S_AXI_WVALID[gen_si_slot]),
.S_WREADY (S_AXI_WREADY[gen_si_slot]),
// Vector of write transfer outputs to each MI-slot's W-mux
.M_WMESG (wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH]),
.M_WLAST (wr_wm_wlast[gen_si_slot]),
.M_WVALID (wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
.M_WREADY (wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)]),
// AW command push from local SI-slot
.S_ASELECT (st_aa_awtarget_enc[gen_si_slot*(P_NUM_MASTER_SLOTS_LOG+1)+:(P_NUM_MASTER_SLOTS_LOG+1)]), // Target MI-slot
.S_AVALID (ss_wr_awvalid[gen_si_slot]),
.S_AREADY (ss_wr_awready[gen_si_slot])
);
assign si_wr_wmesg[gen_si_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH] = {
((C_AXI_PROTOCOL == P_AXI3) ? f_extend_ID(S_AXI_WID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH], gen_si_slot) : 1'b0),
S_AXI_WUSER[gen_si_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH],
S_AXI_WSTRB[gen_si_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8],
S_AXI_WDATA[gen_si_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]
};
end else begin : gen_no_si_write
assign S_AXI_AWREADY[gen_si_slot] = 1'b0;
assign ss_aa_awvalid[gen_si_slot] = 1'b0;
assign st_aa_awvalid_qual[gen_si_slot] = 1'b1;
assign tmp_aa_awmesg[gen_si_slot*P_AA_AWMESG_WIDTH+:P_AA_AWMESG_WIDTH] = 0;
assign S_AXI_BID[gen_si_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign S_AXI_BRESP[gen_si_slot*2+:2] = 0;
assign S_AXI_BUSER[gen_si_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign S_AXI_BVALID[gen_si_slot] = 1'b0;
assign st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign S_AXI_WREADY[gen_si_slot] = 1'b0;
assign wr_wm_wmesg[gen_si_slot*(P_WR_WMESG_WIDTH)+:P_WR_WMESG_WIDTH] = 0;
assign wr_wm_wlast[gen_si_slot] = 1'b0;
assign wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
assign st_aa_awtarget_hot[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+:(C_NUM_MASTER_SLOTS+1)] = 0;
end // gen_si_write
end // gen_slave_slots
for (gen_mi_slot=0; gen_mi_slot<C_NUM_MASTER_SLOTS+1; gen_mi_slot=gen_mi_slot+1) begin : gen_master_slots
if (P_M_AXI_SUPPORTS_READ[gen_mi_slot]) begin : gen_mi_read
if (C_NUM_SLAVE_SLOTS>1) begin : gen_rid_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_READ_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
rid_decoder_inst
(
.ADDR (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_rid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (rid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_rid_decoder
assign tmp_mr_rid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign rid_match[gen_mi_slot] = 1'b1;
end
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = {
st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH],
st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH],
st_mr_rresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_read
assign tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign rid_match[gen_mi_slot] = 1'b0;
assign st_mr_rmesg[gen_mi_slot*P_ST_RMESG_WIDTH+:P_ST_RMESG_WIDTH] = 0;
end // gen_mi_read
if (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot]) begin : gen_mi_write
if (C_NUM_SLAVE_SLOTS>1) begin : gen_bid_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_SLAVE_SLOTS),
.C_NUM_TARGETS_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_NUM_RANGES (1),
.C_ADDR_WIDTH (C_AXI_ID_WIDTH),
.C_TARGET_ENC (C_DEBUG),
.C_TARGET_HOT (1),
.C_REGION_ENC (0),
.C_BASE_ADDR (C_S_AXI_BASE_ID),
.C_HIGH_ADDR (C_S_AXI_HIGH_ID),
.C_TARGET_QUAL (P_M_AXI_WRITE_CONNECTIVITY[gen_mi_slot*32+:C_NUM_SLAVE_SLOTS]),
.C_RESOLUTION (0)
)
bid_decoder_inst
(
.ADDR (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.TARGET_HOT (tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.TARGET_ENC (debug_bid_target_i[gen_mi_slot*P_NUM_SLAVE_SLOTS_LOG+:P_NUM_SLAVE_SLOTS_LOG]),
.MATCH (bid_match[gen_mi_slot]),
.REGION ()
);
end else begin : gen_no_bid_decoder
assign tmp_mr_bid_target[gen_mi_slot] = 1'b1; // All response transfers route to solo SI-slot.
assign bid_match[gen_mi_slot] = 1'b1;
end
axi_crossbar_v2_1_wdata_mux # // "WM": Write data Mux, per MI-slot (incl error-handler)
(
.C_FAMILY (C_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_SELECT_WIDTH (P_NUM_SLAVE_SLOTS_LOG),
.C_WMESG_WIDTH (P_WR_WMESG_WIDTH),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6])
)
wdata_mux_w
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of write transfer inputs from each SI-slot's W-router
.S_WMESG (wr_wm_wmesg),
.S_WLAST (wr_wm_wlast),
.S_WVALID (tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
.S_WREADY (tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS]),
// Write transfer output to the current MI-slot
.M_WMESG (wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+:P_WR_WMESG_WIDTH]),
.M_WLAST (wm_mr_wlast[gen_mi_slot]),
.M_WVALID (wm_mr_wvalid[gen_mi_slot]),
.M_WREADY (wm_mr_wready[gen_mi_slot]),
// AW command push from AW arbiter output
.S_ASELECT (aa_wm_awgrant_enc), // SI-slot selected by arbiter
.S_AVALID (sa_wm_awvalid[gen_mi_slot]),
.S_AREADY (sa_wm_awready[gen_mi_slot])
);
if (C_DEBUG) begin : gen_debug_w
// DEBUG WRITE BEAT COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
if (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot]) begin
if (mi_wlast[gen_mi_slot]) begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= 0;
end else begin
debug_w_beat_cnt_i[gen_mi_slot*8+:8] <= debug_w_beat_cnt_i[gen_mi_slot*8+:8] + 1;
end
end
end
end // clocked process
// DEBUG W-CHANNEL TRANSACTION SEQUENCE QUEUE
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]),
.C_USE_FULL (0)
)
debug_w_seq_fifo
(
.ACLK (ACLK),
.ARESET (reset),
.S_MESG (debug_aw_trans_seq_i),
.S_VALID (sa_wm_awvalid[gen_mi_slot]),
.S_READY (),
.M_MESG (debug_w_trans_seq_i[gen_mi_slot*8+:8]),
.M_VALID (),
.M_READY (mi_wvalid[gen_mi_slot] & mi_wready[gen_mi_slot] & mi_wlast[gen_mi_slot])
);
end // gen_debug_w
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH +: C_AXI_DATA_WIDTH];
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH +: C_AXI_DATA_WIDTH/8];
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8 +: C_AXI_WUSER_WIDTH];
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = wm_mr_wmesg[gen_mi_slot*P_WR_WMESG_WIDTH+C_AXI_DATA_WIDTH+(C_AXI_DATA_WIDTH/8)+C_AXI_WUSER_WIDTH +: P_AXI_WID_WIDTH];
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = {
st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH],
st_mr_bresp[gen_mi_slot*2+:2]
};
end else begin : gen_no_mi_write
assign tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign bid_match[gen_mi_slot] = 1'b0;
assign wm_mr_wvalid[gen_mi_slot] = 0;
assign wm_mr_wlast[gen_mi_slot] = 0;
assign wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = 0;
assign wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = 0;
assign wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign st_mr_bmesg[gen_mi_slot*P_ST_BMESG_WIDTH+:P_ST_BMESG_WIDTH] = 0;
assign tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+:C_NUM_SLAVE_SLOTS] = 0;
assign sa_wm_awready[gen_mi_slot] = 0;
end // gen_mi_write
for (gen_si_slot=0; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_trans_si
// Transpose handshakes from W-router (SxM) to W-mux (MxS).
assign tmp_wm_wvalid[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot] = wr_tmp_wvalid[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot];
assign wr_tmp_wready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_wm_wready[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
// Transpose response enables from ID decoders (MxS) to si_transactors (SxM).
assign st_tmp_bid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_bid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
assign st_tmp_rid_target[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = tmp_mr_rid_target[gen_mi_slot*C_NUM_SLAVE_SLOTS+gen_si_slot];
end // gen_trans_si
assign bready_carry[gen_mi_slot] = st_tmp_bready[gen_mi_slot];
assign rready_carry[gen_mi_slot] = st_tmp_rready[gen_mi_slot];
for (gen_si_slot=1; gen_si_slot<C_NUM_SLAVE_SLOTS; gen_si_slot=gen_si_slot+1) begin : gen_resp_carry_si
assign bready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_BREADY if ...
bready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_bready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates BREADY for that MI-slot.
assign rready_carry[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] = // Generate M_RREADY if ...
rready_carry[(gen_si_slot-1)*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot] | // For any SI-slot (OR carry-chain across all SI-slots), ...
st_tmp_rready[gen_si_slot*(C_NUM_MASTER_SLOTS+1)+gen_mi_slot]; // The write SI transactor indicates RREADY for that MI-slot.
end // gen_resp_carry_si
assign w_cmd_push[gen_mi_slot] = mi_awvalid[gen_mi_slot] && mi_awready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_push[gen_mi_slot] = mi_arvalid[gen_mi_slot] && mi_arready[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
assign w_cmd_pop[gen_mi_slot] = st_mr_bvalid[gen_mi_slot] && st_mr_bready[gen_mi_slot] && P_M_AXI_SUPPORTS_WRITE[gen_mi_slot];
assign r_cmd_pop[gen_mi_slot] = st_mr_rvalid[gen_mi_slot] && st_mr_rready[gen_mi_slot] && st_mr_rlast[gen_mi_slot] && P_M_AXI_SUPPORTS_READ[gen_mi_slot];
// Disqualify arbitration of SI-slot if targeted MI-slot has reached its issuing limit.
assign mi_awmaxissuing[gen_mi_slot] = (w_issuing_cnt[gen_mi_slot*8 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_WRITE_ISSUING[gen_mi_slot*32 +: (C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~w_cmd_pop[gen_mi_slot];
assign mi_armaxissuing[gen_mi_slot] = (r_issuing_cnt[gen_mi_slot*8 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] ==
P_M_AXI_READ_ISSUING[gen_mi_slot*32 +: (C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)]) & ~r_cmd_pop[gen_mi_slot];
always @(posedge ACLK) begin
if (reset) begin
w_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
r_issuing_cnt[gen_mi_slot*8+:8] <= 0; // Some high-order bits remain constant 0
end else begin
if (w_cmd_push[gen_mi_slot] && ~w_cmd_pop[gen_mi_slot]) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (w_cmd_pop[gen_mi_slot] && ~w_cmd_push[gen_mi_slot] && (|w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= w_issuing_cnt[gen_mi_slot*8+:(C_W_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
if (r_cmd_push[gen_mi_slot] && ~r_cmd_pop[gen_mi_slot]) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] + 1;
end else if (r_cmd_pop[gen_mi_slot] && ~r_cmd_push[gen_mi_slot] && (|r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)])) begin
r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] <= r_issuing_cnt[gen_mi_slot*8+:(C_R_ISSUE_WIDTH[gen_mi_slot*32+:6]+1)] - 1;
end
end
end // Clocked process
// Reg-slice must break combinatorial path from M_BID and M_RID inputs to M_BREADY and M_RREADY outputs.
// (See m_rready_i and m_resp_en combinatorial assignments in si_transactor.)
// Reg-slice incurs +1 latency, but no bubble-cycles.
axi_register_slice_v2_1_axi_register_slice # // "MR": MI-side R/B-channel Reg-slice, per MI-slot (pass-through if only 1 SI-slot configured)
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL ((C_AXI_PROTOCOL == P_AXI3) ? P_AXI3 : P_AXI4),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (1),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (1),
.C_AXI_ARUSER_WIDTH (1),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_REG_CONFIG_AW (P_BYPASS),
.C_REG_CONFIG_AR (P_BYPASS),
.C_REG_CONFIG_W (P_BYPASS),
.C_REG_CONFIG_R (P_M_AXI_SUPPORTS_READ[gen_mi_slot] ? P_FWD_REV : P_BYPASS),
.C_REG_CONFIG_B (P_M_AXI_SUPPORTS_WRITE[gen_mi_slot] ? P_SIMPLE : P_BYPASS)
)
reg_slice_mi
(
.aresetn (ARESETN),
.aclk (ACLK),
.s_axi_awid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_awaddr ({1{1'b0}}),
.s_axi_awlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_awsize ({3{1'b0}}),
.s_axi_awburst ({2{1'b0}}),
.s_axi_awlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_awcache ({4{1'b0}}),
.s_axi_awprot ({3{1'b0}}),
.s_axi_awregion ({4{1'b0}}),
.s_axi_awqos ({4{1'b0}}),
.s_axi_awuser ({1{1'b0}}),
.s_axi_awvalid ({1{1'b0}}),
.s_axi_awready (),
.s_axi_wid (wm_mr_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.s_axi_wdata (wm_mr_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.s_axi_wstrb (wm_mr_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.s_axi_wlast (wm_mr_wlast[gen_mi_slot]),
.s_axi_wuser (wm_mr_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.s_axi_wvalid (wm_mr_wvalid[gen_mi_slot]),
.s_axi_wready (wm_mr_wready[gen_mi_slot]),
.s_axi_bid (st_mr_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_bresp (st_mr_bresp[gen_mi_slot*2+:2] ),
.s_axi_buser (st_mr_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.s_axi_bvalid (st_mr_bvalid[gen_mi_slot*1+:1] ),
.s_axi_bready (st_mr_bready[gen_mi_slot*1+:1] ),
.s_axi_arid ({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_araddr ({1{1'b0}}),
.s_axi_arlen ({((C_AXI_PROTOCOL == P_AXI3) ? 4 : 8){1'b0}}),
.s_axi_arsize ({3{1'b0}}),
.s_axi_arburst ({2{1'b0}}),
.s_axi_arlock ({((C_AXI_PROTOCOL == P_AXI3) ? 2 : 1){1'b0}}),
.s_axi_arcache ({4{1'b0}}),
.s_axi_arprot ({3{1'b0}}),
.s_axi_arregion ({4{1'b0}}),
.s_axi_arqos ({4{1'b0}}),
.s_axi_aruser ({1{1'b0}}),
.s_axi_arvalid ({1{1'b0}}),
.s_axi_arready (),
.s_axi_rid (st_mr_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.s_axi_rdata (st_mr_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.s_axi_rresp (st_mr_rresp[gen_mi_slot*2+:2] ),
.s_axi_rlast (st_mr_rlast[gen_mi_slot*1+:1] ),
.s_axi_ruser (st_mr_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.s_axi_rvalid (st_mr_rvalid[gen_mi_slot*1+:1] ),
.s_axi_rready (st_mr_rready[gen_mi_slot*1+:1] ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready ({1{1'b0}}),
.m_axi_wid (mi_wid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.m_axi_wdata (mi_wdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.m_axi_wstrb (mi_wstrb[gen_mi_slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8]),
.m_axi_wlast (mi_wlast[gen_mi_slot]),
.m_axi_wuser (mi_wuser[gen_mi_slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH]),
.m_axi_wvalid (mi_wvalid[gen_mi_slot]),
.m_axi_wready (mi_wready[gen_mi_slot]),
.m_axi_bid (mi_bid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_bresp (mi_bresp[gen_mi_slot*2+:2] ),
.m_axi_buser (mi_buser[gen_mi_slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] ),
.m_axi_bvalid (mi_bvalid[gen_mi_slot*1+:1] ),
.m_axi_bready (mi_bready[gen_mi_slot*1+:1] ),
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready ({1{1'b0}}),
.m_axi_rid (mi_rid[gen_mi_slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] ),
.m_axi_rdata (mi_rdata[gen_mi_slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] ),
.m_axi_rresp (mi_rresp[gen_mi_slot*2+:2] ),
.m_axi_rlast (mi_rlast[gen_mi_slot*1+:1] ),
.m_axi_ruser (mi_ruser[gen_mi_slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] ),
.m_axi_rvalid (mi_rvalid[gen_mi_slot*1+:1] ),
.m_axi_rready (mi_rready[gen_mi_slot*1+:1] )
);
end // gen_master_slots (Next gen_mi_slot)
// Highest row of *ready_carry contains accumulated OR across all SI-slots, for each MI-slot.
assign st_mr_bready = bready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
assign st_mr_rready = rready_carry[(C_NUM_SLAVE_SLOTS-1)*(C_NUM_MASTER_SLOTS+1) +: C_NUM_MASTER_SLOTS+1];
// Assign MI-side B, R and W channel ports (exclude error handler signals).
assign mi_bid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_BID;
assign mi_bvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_BVALID;
assign mi_bresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_BRESP;
assign mi_buser[0+:C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH] = M_AXI_BUSER;
assign M_AXI_BREADY = mi_bready[0+:C_NUM_MASTER_SLOTS];
assign mi_rid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] = M_AXI_RID;
assign mi_rlast[0+:C_NUM_MASTER_SLOTS] = M_AXI_RLAST;
assign mi_rvalid[0+:C_NUM_MASTER_SLOTS] = M_AXI_RVALID;
assign mi_rresp[0+:C_NUM_MASTER_SLOTS*2] = M_AXI_RRESP;
assign mi_ruser[0+:C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH] = M_AXI_RUSER;
assign mi_rdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH] = M_AXI_RDATA;
assign M_AXI_RREADY = mi_rready[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WLAST = mi_wlast[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WVALID = mi_wvalid[0+:C_NUM_MASTER_SLOTS];
assign M_AXI_WUSER = mi_wuser[0+:C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH];
assign M_AXI_WID = (C_AXI_PROTOCOL == P_AXI3) ? mi_wid[0+:C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH] : 0;
assign M_AXI_WDATA = mi_wdata[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH];
assign M_AXI_WSTRB = mi_wstrb[0+:C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8];
assign mi_wready[0+:C_NUM_MASTER_SLOTS] = M_AXI_WREADY;
axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AW channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_AWMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_aw
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AW command request inputs
.S_MESG (tmp_aa_awmesg),
.S_TARGET_HOT (st_aa_awtarget_hot),
.S_VALID (ss_aa_awvalid),
.S_VALID_QUAL (st_aa_awvalid_qual),
.S_READY (ss_aa_awready),
// Granted AW command output
.M_MESG (aa_mi_awmesg),
.M_TARGET_HOT (aa_mi_awtarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_wm_awgrant_enc), // SI-slot index of granted command
.M_VALID (aa_sa_awvalid),
.M_READY (aa_sa_awready),
.ISSUING_LIMIT (mi_awmaxissuing)
);
// Broadcast AW transfer payload to all MI-slots
assign M_AXI_AWID = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_AWADDR = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_AWLEN = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_AWSIZE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_AWLOCK = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_AWPROT = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_AWREGION = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_AWBURST = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_AWCACHE = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_AWQOS = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_AWUSER = {C_NUM_MASTER_SLOTS{aa_mi_awmesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_AWUSER_WIDTH]}};
axi_crossbar_v2_1_addr_arbiter # // "AA": Addr Arbiter (AR channel)
(
.C_FAMILY (C_FAMILY),
.C_NUM_M (C_NUM_MASTER_SLOTS+1),
.C_NUM_S (C_NUM_SLAVE_SLOTS),
.C_NUM_S_LOG (P_NUM_SLAVE_SLOTS_LOG),
.C_MESG_WIDTH (P_AA_ARMESG_WIDTH),
.C_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY)
)
addr_arbiter_ar
(
.ACLK (ACLK),
.ARESET (reset),
// Vector of SI-side AR command request inputs
.S_MESG (tmp_aa_armesg),
.S_TARGET_HOT (st_aa_artarget_hot),
.S_VALID_QUAL (st_aa_arvalid_qual),
.S_VALID (st_aa_arvalid),
.S_READY (st_aa_arready),
// Granted AR command output
.M_MESG (aa_mi_armesg),
.M_TARGET_HOT (aa_mi_artarget_hot), // MI-slot targeted by granted command
.M_GRANT_ENC (aa_mi_argrant_enc),
.M_VALID (aa_mi_arvalid), // SI-slot index of granted command
.M_READY (aa_mi_arready),
.ISSUING_LIMIT (mi_armaxissuing)
);
if (C_DEBUG) begin : gen_debug_trans_seq
// DEBUG WRITE TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_aw_trans_seq_i <= 1;
end else begin
if (aa_sa_awvalid && aa_sa_awready) begin
debug_aw_trans_seq_i <= debug_aw_trans_seq_i + 1;
end
end
end
// DEBUG READ TRANSACTION SEQUENCE COUNTER
always @(posedge ACLK) begin
if (reset) begin
debug_ar_trans_seq_i <= 1;
end else begin
if (aa_mi_arvalid && aa_mi_arready) begin
debug_ar_trans_seq_i <= debug_ar_trans_seq_i + 1;
end
end
end
end // gen_debug_trans_seq
// Broadcast AR transfer payload to all MI-slots
assign M_AXI_ARID = {C_NUM_MASTER_SLOTS{aa_mi_armesg[0+:C_AXI_ID_WIDTH]}};
assign M_AXI_ARADDR = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+:C_AXI_ADDR_WIDTH]}};
assign M_AXI_ARLEN = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]}};
assign M_AXI_ARSIZE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8 +:3]}};
assign M_AXI_ARLOCK = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3 +:2]}};
assign M_AXI_ARPROT = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2 +:3]}};
assign M_AXI_ARREGION = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3 +:4]}};
assign M_AXI_ARBURST = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4 +:2]}};
assign M_AXI_ARCACHE = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2 +:4]}};
assign M_AXI_ARQOS = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4 +:4]}};
assign M_AXI_ARUSER = {C_NUM_MASTER_SLOTS{aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH+8+3+2+3+4+2+4+4 +:C_AXI_ARUSER_WIDTH]}};
// AW arbiter command transfer completes upon completion of both M-side AW-channel transfer and W-mux address acceptance (command push).
axi_crossbar_v2_1_splitter # // "SA": Splitter for Write Addr Arbiter
(
.C_NUM_M (2)
)
splitter_aw_mi
(
.ACLK (ACLK),
.ARESET (reset),
.S_VALID (aa_sa_awvalid),
.S_READY (aa_sa_awready),
.M_VALID ({mi_awvalid_en, sa_wm_awvalid_en}),
.M_READY ({mi_awready_mux, sa_wm_awready_mux})
);
assign mi_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{mi_awvalid_en}};
assign mi_awready_mux = |(aa_mi_awtarget_hot & mi_awready);
assign M_AXI_AWVALID = mi_awvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_awready[0+:C_NUM_MASTER_SLOTS] = M_AXI_AWREADY;
assign sa_wm_awvalid = aa_mi_awtarget_hot & {C_NUM_MASTER_SLOTS+1{sa_wm_awvalid_en}};
assign sa_wm_awready_mux = |(aa_mi_awtarget_hot & sa_wm_awready);
assign mi_arvalid = aa_mi_artarget_hot & {C_NUM_MASTER_SLOTS+1{aa_mi_arvalid}};
assign aa_mi_arready = |(aa_mi_artarget_hot & mi_arready);
assign M_AXI_ARVALID = mi_arvalid[0+:C_NUM_MASTER_SLOTS]; // Slot C_NUM_MASTER_SLOTS+1 is the error handler
assign mi_arready[0+:C_NUM_MASTER_SLOTS] = M_AXI_ARREADY;
// MI-slot # C_NUM_MASTER_SLOTS is the error handler
if (C_RANGE_CHECK) begin : gen_decerr_slave
axi_crossbar_v2_1_decerr_slave #
(
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_RESP (P_DECERR)
)
decerr_slave_inst
(
.S_AXI_ACLK (ACLK),
.S_AXI_ARESET (reset),
.S_AXI_AWID (aa_mi_awmesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_AWVALID (mi_awvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_AWREADY (mi_awready[C_NUM_MASTER_SLOTS]),
.S_AXI_WLAST (mi_wlast[C_NUM_MASTER_SLOTS]),
.S_AXI_WVALID (mi_wvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_WREADY (mi_wready[C_NUM_MASTER_SLOTS]),
.S_AXI_BID (mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_BRESP (mi_bresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_BUSER (mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH]),
.S_AXI_BVALID (mi_bvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_BREADY (mi_bready[C_NUM_MASTER_SLOTS]),
.S_AXI_ARID (aa_mi_armesg[0+:C_AXI_ID_WIDTH]),
.S_AXI_ARLEN (aa_mi_armesg[C_AXI_ID_WIDTH+C_AXI_ADDR_WIDTH +:8]),
.S_AXI_ARVALID (mi_arvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_ARREADY (mi_arready[C_NUM_MASTER_SLOTS]),
.S_AXI_RID (mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH]),
.S_AXI_RDATA (mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH]),
.S_AXI_RRESP (mi_rresp[C_NUM_MASTER_SLOTS*2+:2]),
.S_AXI_RUSER (mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH]),
.S_AXI_RLAST (mi_rlast[C_NUM_MASTER_SLOTS]),
.S_AXI_RVALID (mi_rvalid[C_NUM_MASTER_SLOTS]),
.S_AXI_RREADY (mi_rready[C_NUM_MASTER_SLOTS])
);
end else begin : gen_no_decerr_slave
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_wready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_arready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_awready[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_bid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_bresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_buser[C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = 0;
assign mi_bvalid[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rid[C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = 0;
assign mi_rdata[C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = 0;
assign mi_rresp[C_NUM_MASTER_SLOTS*2+:2] = 0;
assign mi_ruser[C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = 0;
assign mi_rlast[C_NUM_MASTER_SLOTS] = 1'b0;
assign mi_rvalid[C_NUM_MASTER_SLOTS] = 1'b0;
end // gen_decerr_slave
endgenerate
endmodule
`default_nettype wire
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_axi_basic_rx_null_gen.v
// Version : 3.0
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digest: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2
2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
endcase
end
assign new_pkt_len =
{{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
//assign new_pkt_len =
// {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
//
// Copyright (c) 2012-2013 Jonathan Woodruff
// Copyright (c) 2013 Bjoern A. Zeeb
// Copyright (c) 2014 A. Theodore Markettos
// Copyright (c) 2014 Robert M. Norton
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249
// ("MRC2"), as part of the DARPA MRC research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
`define ENABLE_LED
`define ENABLE_BUTTONS
`define ENABLE_ETHERNET
`define ENABLE_SDCARD
`define ENABLE_UART
`define ENABLE_DDR2_1
`define ENABLE_DIP
`define ENABLE_SLIDE
`define ENABLE_SEG
`define ENABLE_TEMP
`define ENABLE_CSENSE
`define ENABLE_FLASH
`define ENABLE_SSRAM
`define ENABLE_USB
`define ENABLE_HDMI
`define ENABLE_MTL
`ifndef ENABLE_DDR2_1
`ifndef ENABLE_DDR2_2
`define DISABLE_TERMINATION
`endif
`endif
`ifndef ENABLE_FLASH
`ifndef ENABLE_SSRAM
`define DISABLE_FSM
`endif
`endif
module DE4_BERI (
////// clock inputs
//input GCLKIN,
//output GCLKOUT_FPGA,
//inout [2:0] MAX_CONF_D,
//output [2:0] MAX_PLL_D,
input OSC_50_Bank2,
input OSC_50_Bank3,
input OSC_50_Bank4,
//input OSC_50_Bank5,
//input OSC_50_Bank6,
//input OSC_50_Bank7,
//input PLL_CLKIN_p,
`ifdef ENABLE_LED
output [7:0] LED, // 8x LEDs
`endif
`ifdef ENABLE_BUTTONS
input [3:0] BUTTON, // 4x buttons
`endif
input CPU_RESET_n,
//inout EXT_IO,
`ifdef ENABLE_ETHERNET
////// Ethernet MAC x 4
input [3:0] ETH_INT_n,
output [3:0] ETH_MDC,
inout [3:0] ETH_MDIO,
output ETH_RST_n,
input [3:0] ETH_RX_p,
output [3:0] ETH_TX_p,
`endif
`ifdef ENABLE_SDCARD
////// SD card socket
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT,
input SD_WP_n,
`endif
`ifdef ENABLE_UART
////// UART
output UART_TXD,
input UART_CTS,
input UART_RXD,
output UART_RTS,
`endif
`ifdef ENABLE_DDR2_1
////// DDR2 SODIMM 1
output [15:0] M1_DDR2_addr,
output [2:0] M1_DDR2_ba,
output M1_DDR2_cas_n,
output [1:0] M1_DDR2_cke,
inout [1:0] M1_DDR2_clk,
inout [1:0] M1_DDR2_clk_n,
output [1:0] M1_DDR2_cs_n,
output [7:0] M1_DDR2_dm,
inout [63:0] M1_DDR2_dq,
inout [7:0] M1_DDR2_dqs,
inout [7:0] M1_DDR2_dqsn,
output [1:0] M1_DDR2_odt,
output M1_DDR2_ras_n,
output [1:0] M1_DDR2_SA,
output M1_DDR2_SCL,
inout M1_DDR2_SDA,
output M1_DDR2_we_n,
`endif
`ifdef ENABLE_DDR2_2
////// DDR2 SODIMM 2
output [15:0] M2_DDR2_addr,
output [2:0] M2_DDR2_ba,
output M2_DDR2_cas_n,
output [1:0] M2_DDR2_cke,
inout [1:0] M2_DDR2_clk,
inout [1:0] M2_DDR2_clk_n,
output [1:0] M2_DDR2_cs_n,
output [7:0] M2_DDR2_dm,
inout [63:0] M2_DDR2_dq,
inout [7:0] M2_DDR2_dqs,
inout [7:0] M2_DDR2_dqsn,
output [1:0] M2_DDR2_odt,
output M2_DDR2_ras_n,
output [1:0] M2_DDR2_SA,
output M2_DDR2_SCL,
inout M2_DDR2_SDA,
output M2_DDR2_we_n,
`endif
`ifndef DISABLE_TERMINATION
// termination for DDR2 DIMMs
input termination_blk0_rup_pad,
input termination_blk0_rdn_pad,
`endif
`ifdef ENABLE_DIP
input [7:0] SW, // 8x DIP switches
`endif
`ifdef ENABLE_SLIDE
input [3:0] SLIDE_SW, // 4x slide switches
`endif
`ifdef ENABLE_SEG
// 2x 7-segment displays
output [6:0] SEG0_D,
output SEG0_DP,
output [6:0] SEG1_D,
output SEG1_DP,
`endif
`ifdef ENABLE_TEMP
// temperature sensors
input TEMP_INT_n,
output TEMP_SMCLK,
inout TEMP_SMDAT,
`endif
`ifdef ENABLE_CSENSE
// current sensors
output CSENSE_ADC_FO,
output [1:0] CSENSE_CS_n,
output CSENSE_SCK,
output CSENSE_SDI,
input CSENSE_SDO,
`endif
output FAN_CTRL, // fan control
`ifndef DISABLE_FSM
// flash and SRAM shared data bus
output [25:1] FSM_A,
inout [15:0] FSM_D,
`endif
`ifdef ENABLE_FLASH
// Flash memory
output FLASH_ADV_n,
output FLASH_CE_n,
output FLASH_CLK,
output FLASH_OE_n,
output FLASH_RESET_n,
input FLASH_RYBY_n,
output FLASH_WE_n,
`endif
`ifdef ENABLE_SSRAM
// synchronous SRAM
output SSRAM_ADV,
output SSRAM_BWA_n,
output SSRAM_BWB_n,
output SSRAM_CE_n,
output SSRAM_CKE_n,
output SSRAM_CLK,
output SSRAM_OE_n,
output SSRAM_WE_n,
`endif
// HSMC port A and B
`ifdef ENABLE_HDMI
// HDMI interface board on HSMC port A
//inout HDMI_SDA,
//output HDMI_SCL,
output [11:0] HDMI_TX_RD,
output [11:0] HDMI_TX_GD,
inout HDMI_TX_PCSCL,
inout HDMI_TX_PCSDA,
output HDMI_TX_RST_N,
input HDMI_TX_INT_N,
output [3:0] HDMI_TX_DSD_L,
output [3:0] HDMI_TX_DSD_R,
output [11:0] HDMI_TX_BD,
output HDMI_TX_PCLK,
output HDMI_TX_DCLK,
output HDMI_TX_SCK,
output HDMI_TX_WS,
output HDMI_TX_MCLK,
output [3:0] HDMI_TX_I2S,
output HDMI_TX_DE,
output HDMI_TX_VS,
output HDMI_TX_HS,
output HDMI_TX_SPDIF,
inout HDMI_TX_CEC,
`endif
// GPIO port 0
input [31:0] GPIO0_D,
`ifdef ENABLE_USB
output [17:1] OTG_A,
output OTG_CS_n,
inout [31:0] OTG_D,
output OTG_DC_DACK,
input OTG_DC_DREQ,
input OTG_DC_IRQ,
output OTG_HC_DACK,
input OTG_HC_DREQ,
input OTG_HC_IRQ,
output OTG_OE_n,
output OTG_RESET_n,
output OTG_WE_n,
`endif
`ifdef ENABLE_MTL
// GPIO port 1 connect to MTL capacitive touch screen
output mtl_dclk,
output [7:0] mtl_r,
output [7:0] mtl_g,
output [7:0] mtl_b,
output mtl_hsd,
output mtl_vsd,
output mtl_touch_i2cscl,
inout mtl_touch_i2csda,
input mtl_touch_int
`endif
`ifdef ENABLE_PCIE
,
//PCI Express
input PCIE_PREST_n,
input PCIE_REFCLK_p,
//input HSMA_REFCLK_p,
input [3:0] PCIE_RX_p,
input PCIE_SMBCLK,
inout PCIE_SMBDAT,
output [3:0] PCIE_TX_p,
output PCIE_WAKE_n
`endif
);
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc;
wire enet_mdio_in;
wire enet_mdio_oen;
wire enet_mdio_out;
wire enet_refclk_125MHz;
wire lvds_rxp;
wire lvds_txp;
wire enet1_mdc;
wire enet1_mdio_in;
wire enet1_mdio_oen;
wire enet1_mdio_out;
wire lvds_rxp1;
wire lvds_txp1;
// Assign outputs that are not used to 0
//assign MAX_PLL_D = 3'b0;
//assign ETH_MDC[3:1] = 3'b0;
assign M1_DDR2_SA = 1'b0;
assign CSENSE_CS_n = 1'b0;
assign CSENSE_ADC_FO = 1'b0;
assign CSENSE_SCK = 1'b0;
assign CSENSE_SDI = 1'b0;
//assign GCLKOUT_FPGA = 1'b0;
assign M1_DDR2_SCL = 1'b0;
//// Ethernet
assign ETH_RST_n = rstn;
assign ETH_TX_p[3:2] = 2'b0;
assign lvds_rxp = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp;
assign lvds_rxp1 = ETH_RX_p[1];
assign ETH_TX_p[1] = lvds_txp1;
assign enet_mdio_in = ETH_MDIO[0];
assign enet1_mdio_in = ETH_MDIO[1];
assign ETH_MDIO[0] = (!enet_mdio_oen ? enet_mdio_out : 1'bz);
assign ETH_MDIO[1] = (!enet1_mdio_oen ? enet1_mdio_out : 1'bz);
// Allow the other two tri-state interfaces to float.
assign ETH_MDIO[2] = 1'bz;
assign ETH_MDIO[3] = 1'bz;
assign ETH_MDC[0] = enet_mdc;
assign ETH_MDC[1] = enet1_mdc;
// Set unused interface clocks to high.
assign ETH_MDC[2] = 1'b1;
assign ETH_MDC[3] = 1'b1;
wire clk100;
wire [7:0] LED_n;
assign LED = ~LED_n;
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_Bank2),
.c0(enet_refclk_125MHz)
);
`ifdef ENABLE_PCIE
wire clk125;
//PCI Express clock
pll_125 pll_125_pcie (
.inclk0(OSC_50_Bank2),
.c0(clk125)
);
assign reconfig_clk = OSC_50_Bank3;
wire reconfig_fromgxb;
wire reconfig_togxb;
wire reconfig_busy;
altgx_reconfig altgx_reconfig_pcie (
.reconfig_clk(reconfig_clk),
.reconfig_fromgxb(reconfig_fromgxb),
.busy(reconfig_busy),
.reconfig_togxb(reconfig_togxb)
);
`endif
wire qsys_sysclk;
wire qsys_sysreset_n;
//wire sramClk;
assign SSRAM_CLK = qsys_sysclk;
(* keep = 1 *) wire clk27;
display_pll display_pll_ins (
.inclk0(OSC_50_Bank2),
.c0(clk27)
);
assign HDMI_TX_PCLK = clk27;
// synchronize reset signal
reg rstn, rstn_metastable;
always @(posedge OSC_50_Bank2)
begin
rstn_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn <= rstn_metastable;
end
reg rstn100, rstn100_metastable;
always @(posedge qsys_sysclk)
begin
rstn100_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn100 <= rstn100_metastable;
end
(* noprune *) reg rstn27;
reg rstn27sample;
always @(posedge clk27)
begin
rstn27sample <= rstn;
rstn27 <= rstn27sample;
end
reg [7:0] SW_P;
always @(posedge OSC_50_Bank2) SW_P <= ~SW; // positive version of DIP switches
assign SEG1_DP = ~1'b0;
assign SEG0_DP = ~1'b0;
reg [3:0] slide_sw_metastable, slide_sw_sync;
always @(posedge OSC_50_Bank2)
begin
slide_sw_metastable <= SLIDE_SW;
slide_sw_sync <= slide_sw_metastable;
end
// assign PCIE_WAKE_n = 1'b0;
// assign PCIE_SMBDATA = 1'bz;
/* signals for the old Terasic resistive touch screen (currently unused)
wire [7:0] vga_R, vga_G, vga_B;
wire vga_DEN, vga_HD, vga_VD;
assign vga_DEN = 1'b0;
assign vga_HD = 1'b0;
assign vga_VD = 1'b0;
assign vga_R = 8'd0;
assign vga_G = 8'd0;
assign vga_B = 8'd0;
assign lcdtouchLTM_R = vga_R;
assign lcdtouchLTM_G = vga_G;
assign lcdtouchLTM_B = vga_B;
assign lcdtouchLTM_DEN = vga_DEN;
assign lcdtouchLTM_HD = vga_HD;
assign lcdtouchLTM_VD = vga_VD;
assign lcdtouchLTM_GREST = rstn27;
assign lcdtouchLTM_NCLK = clk27;
assign lcdtouchLTM_SCEN = 1'b1;
assign lcdtouchLTM_ADC_DCLK = 1'b1;
assign lcdtouchLTM_ADC_DIN = 1'b1;*/
// clock for multitouch screen
assign mtl_dclk = clk27;
(* keep = 1 *) wire ssram_data_outen;
(* keep = 1 *) wire [15:0] ssram_data_out;
// instantiate the touch screen controller provided by Terasic (encrypted block)
reg touch_ready_0;
reg [9:0] touch_x1_0, touch_x2_0;
reg [8:0] touch_y1_0, touch_y2_0;
reg [1:0] touch_count_0;
reg [7:0] touch_gesture_0;
reg touch_ready_1;
reg [9:0] touch_x1_1, touch_x2_1;
reg [8:0] touch_y1_1, touch_y2_1;
reg [1:0] touch_count_1;
reg [7:0] touch_gesture_1;
wire touch_ready_2;
wire [9:0] touch_x1_2, touch_x2_2;
wire [8:0] touch_y1_2, touch_y2_2;
wire [1:0] touch_count_2;
wire [7:0] touch_gesture_2;
i2c_touch_config touch(
.iCLK(OSC_50_Bank2),
.iRSTN(rstn),
.iTRIG(!mtl_touch_int), // note that this signal is inverted
.oREADY(touch_ready_2),
.oREG_X1(touch_x1_2),
.oREG_Y1(touch_y1_2),
.oREG_X2(touch_x2_2),
.oREG_Y2(touch_y2_2),
.oREG_TOUCH_COUNT(touch_count_2),
.oREG_GESTURE(touch_gesture_2),
.I2C_SCLK(mtl_touch_i2cscl),
.I2C_SDAT(mtl_touch_i2csda));
// synchronize signals to qsys system clock
always @(posedge qsys_sysclk)
begin
touch_ready_1 <= touch_ready_2;
touch_x1_1 <= touch_x1_2;
touch_y1_1 <= touch_y1_2;
touch_x2_1 <= touch_x2_2;
touch_y2_1 <= touch_y2_2;
touch_count_1 <= touch_count_2;
touch_gesture_1 <= touch_gesture_2;
touch_ready_0 <= touch_ready_1;
touch_x1_0 <= touch_x1_1;
touch_y1_0 <= touch_y1_1;
touch_x2_0 <= touch_x2_1;
touch_y2_0 <= touch_y2_1;
touch_count_0 <= touch_count_1;
touch_gesture_0 <= touch_gesture_1;
end
// touch screen controller end
wire i2c_scl_oe_n;
wire i2c_scl_o;
wire i2c_scl_i = HDMI_TX_PCSCL;
wire i2c_sda_oe_n;
wire i2c_sda_o;
wire i2c_sda_i = HDMI_TX_PCSDA;
// tristate buffers
assign HDMI_TX_PCSCL = i2c_scl_oe_n==1'b0 ? i2c_scl_o : 1'bz;
assign HDMI_TX_PCSDA = i2c_sda_oe_n==1'b0 ? i2c_sda_o : 1'bz;
//wire gen_sck;
//wire gen_i2s;
//wire gen_ws;
assign HDMI_TX_SCK = 1'b0;
assign HDMI_TX_I2S = 4'b0;//{gen_i2s, gen_i2s, gen_i2s, gen_i2s};
assign HDMI_TX_WS = 1'b0;//gen_ws;
wire [31:0] otg_dout;
assign OTG_D = (!OTG_CS_n & OTG_OE_n) ? otg_dout : 32'hzzzzzzzz;
wire [16:0] otg_a_temp;
assign OTG_A[17:1] = otg_a_temp[16:0];
DE4_SOC DE4_SOC_inst(
// 1) global signals:
.clk_50_clk(OSC_50_Bank2),
.clk_125_clk(enet_refclk_125MHz),
.reset_reset_n(rstn),
.sysclk_clk(qsys_sysclk),
//.sysreset_reset_n(qsys_sysreset_n),
.leds_external_connection_export(LED_n),
// the_ddr2
.ddr2_global_reset_reset_n(),
.memory_mem_cke (M1_DDR2_cke), // ddr2.cke
.memory_mem_ck_n (M1_DDR2_clk_n), // .ck_n
.memory_mem_cas_n (M1_DDR2_cas_n), // .cas_n
.memory_mem_dq (M1_DDR2_dq), // .dq
.memory_mem_dqs (M1_DDR2_dqs), // .dqs
.memory_mem_odt (M1_DDR2_odt), // .odt
.memory_mem_cs_n (M1_DDR2_cs_n), // .cs_n
.memory_mem_ba (M1_DDR2_ba), // .ba
.memory_mem_dm (M1_DDR2_dm), // .dm
.memory_mem_we_n (M1_DDR2_we_n), // .we_n
.memory_mem_dqs_n (M1_DDR2_dqsn), // .dqs_n
.memory_mem_ras_n (M1_DDR2_ras_n), // .ras_n
.memory_mem_ck (M1_DDR2_clk), // .ck
.memory_mem_a (M1_DDR2_addr), // .a
.oct_rup (termination_blk0_rup_pad), // .oct_rup
.oct_rdn (termination_blk0_rdn_pad), // .oct_rdn
// ddr2 psd i2c
// .out_port_from_the_ddr2_i2c_scl(M1_DDR2_SCL),
// .out_port_from_the_ddr2_i2c_sa(M1_DDR2_SA),
// .bidir_port_to_and_from_the_ddr2_i2c_sda(M1_DDR2_SDA)
// ---------------------------------------------------------------------
// MAC (TSE) 0
.mac_mac_mdio_mdc (enet_mdc), // mac_mac_mdio.mdc
.mac_mac_mdio_mdio_in (enet_mdio_in), // .mdio_in
.mac_mac_mdio_mdio_out (enet_mdio_out), // .mdio_out
.mac_mac_mdio_mdio_oen (enet_mdio_oen), // .mdio_oen
//.mac_mac_misc_xon_gen, (/* input */) // mac_mac_misc.xon_gen
//.mac_mac_misc_xoff_gen, (/* input */) // .xoff_gen
//.mac_mac_misc_magic_wakeup, (/* output */) // .magic_wakeup
//.mac_mac_misc_magic_sleep_n, (/* input */) // .magic_sleep_n
//.mac_mac_misc_ff_tx_crc_fwd, (/* input */) // .ff_tx_crc_fwd
//.mac_mac_misc_ff_tx_septy, (/* output */) // .ff_tx_septy
//.mac_mac_misc_tx_ff_uflow, (/* output */) // .tx_ff_uflow
//.mac_mac_misc_ff_tx_a_full, (/* output */) // .ff_tx_a_full
//.mac_mac_misc_ff_tx_a_empty, (/* output */) // .ff_tx_a_empty
//.mac_mac_misc_rx_err_stat, (/* output[17:0] */) // .rx_err_stat
//.mac_mac_misc_rx_frm_type, (/* output[3:0] */) // .rx_frm_type
//.mac_mac_misc_ff_rx_dsav, (/* output */) // .ff_rx_dsav
//.mac_mac_misc_ff_rx_a_full, (/* output */) // .ff_rx_a_full
//.mac_mac_misc_ff_rx_a_empty, (/* output */) // .ff_rx_a_empty
//.mac_status_led_crs, (/* output */) // mac_status_led.crs
//.mac_status_led_link, (/* output */) // .link
//.mac_status_led_col, (/* output */) // .col
//.mac_status_led_an, (/* output */) // .an
//.mac_status_led_char_err, (/* output */) // .char_err
//.mac_status_led_disp_err, (/* output */) // .disp_err
//.mac_serdes_control_export, (/* output */) // mac_serdes_control.export
.mac_serial_txp (lvds_txp), // mac_serial.txp
.mac_serial_rxp (lvds_rxp), // .rxp
// ---------------------------------------------------------------------
// MAC (TSE) 1
.mac1_mac_mdio_mdc (enet1_mdc), // mac1_mac_mdio.mdc
.mac1_mac_mdio_mdio_in (enet1_mdio_in), // .mdio_in
.mac1_mac_mdio_mdio_out (enet1_mdio_out), // .mdio_out
.mac1_mac_mdio_mdio_oen (enet1_mdio_oen), // .mdio_oen
//.mac1_mac_misc_xon_gen, ( input ) // mac1_mac_misc.xon_gen
//.mac1_mac_misc_xoff_gen, ( input ) // .xoff_gen
//.mac1_mac_misc_magic_wakeup, ( output ) // .magic_wakeup
//.mac1_mac_misc_magic_sleep_n, ( input ) // .magic_sleep_n
//.mac1_mac_misc_ff_tx_crc_fwd, ( input ) // .ff_tx_crc_fwd
//.mac1_mac_misc_ff_tx_septy, ( output ) // .ff_tx_septy
//.mac1_mac_misc_tx_ff_uflow, ( output ) // .tx_ff_uflow
//.mac1_mac_misc_ff_tx_a_full, ( output ) // .ff_tx_a_full
//.mac1_mac_misc_ff_tx_a_empty, ( output ) // .ff_tx_a_empty
//.mac1_mac_misc_rx_err_stat, ( output[17:0] ) // .rx_err_stat
//.mac1_mac_misc_rx_frm_type, ( output[3:0] ) // .rx_frm_type
//.mac1_mac_misc_ff_rx_dsav, ( output ) // .ff_rx_dsav
//.mac1_mac_misc_ff_rx_a_full, ( output ) // .ff_rx_a_full
//.mac1_mac_misc_ff_rx_a_empty, ( output ) // .ff_rx_a_empty
//.mac1_status_led_crs, ( output ) // mac1_status_led.crs
//.mac1_status_led_link, ( output ) // .link
//.mac1_status_led_col, ( output ) // .col
//.mac1_status_led_an, ( output ) // .an
//.mac1_status_led_char_err, ( output ) // .char_err
//.mac1_status_led_disp_err, ( output ) // .disp_err
//.mac1_serdes_control_export, ( output ) // mac1_serdes_control.export
.mac1_serial_txp (lvds_txp1), // mac1_serial.txp
.mac1_serial_rxp (lvds_rxp1), // .rxp
// ---------------------------------------------------------------------/
.sd_b_SD_cmd (SD_CMD), // sd.b_SD_cmd
.sd_b_SD_dat (SD_DAT[0]), // .b_SD_dat
.sd_b_SD_dat3 (SD_DAT[3]), // .b_SD_dat3
.sd_o_SD_clock (SD_CLK), // .o_SD_clock
.mem_ssram_adv (SSRAM_ADV), // fbssram_1.ssram_adv
.mem_ssram_bwa_n (SSRAM_BWA_n), // .ssram_bwa_n
.mem_ssram_bwb_n (SSRAM_BWB_n), // .ssram_bwb_n
.mem_ssram_ce_n (SSRAM_CE_n), // .ssram_ce_n
.mem_ssram_cke_n (SSRAM_CKE_n), // .ssram_cke_n
.mem_ssram_oe_n (SSRAM_OE_n), // .ssram_oe_n
.mem_ssram_we_n (SSRAM_WE_n), // .ssram_we_n
.mem_fsm_a (FSM_A), // .fsm_a
.mem_fsm_d_out (ssram_data_out), // .fsm_d_out
.mem_fsm_d_in (FSM_D), // .fsm_d_in
.mem_fsm_dout_req (ssram_data_outen), // .fsm_dout_req
.mem_flash_adv_n (FLASH_ADV_n),
.mem_flash_ce_n (FLASH_CE_n),
.mem_flash_clk (FLASH_CLK),
.mem_flash_oe_n (FLASH_OE_n),
.mem_flash_we_n (FLASH_WE_n),
.touch_x1 (touch_x1_0), // .touch_x1
.touch_y1 (touch_y1_0), // .touch_y1
.touch_x2 (touch_x2_0), // .touch_x2
.touch_y2 (touch_y2_0), // .touch_y2
.touch_count_gesture ({touch_count_0,touch_gesture_0}), // .touch_count_gesture
.touch_touch_valid (touch_ready_0), // .touch_touch_valid
// .sram_clk_clk (sramClk), // sram_clk.clk
// .sram_clk_clk (SSRAM_CLK)
// .display_clk_clk (clk27),
.coe_hdmi_r(HDMI_TX_RD),
.coe_hdmi_g(HDMI_TX_GD),
.coe_hdmi_b(HDMI_TX_BD),
.coe_hdmi_hsd(HDMI_TX_HS),
.coe_hdmi_vsd(HDMI_TX_VS),
.coe_hdmi_de(HDMI_TX_DE),
.coe_tpadlcd_mtl_r(mtl_r),
.coe_tpadlcd_mtl_g(mtl_g),
.coe_tpadlcd_mtl_b(mtl_b),
.coe_tpadlcd_mtl_hsd(mtl_hsd),
.coe_tpadlcd_mtl_vsd(mtl_vsd),
.clk_27_clk (clk27),
.coe_i2c_scl_i (i2c_scl_i),
.coe_i2c_scl_o (i2c_scl_o),
.coe_i2c_scl_oe_n (i2c_scl_oe_n),
.coe_i2c_sda_i (i2c_sda_i),
.coe_i2c_sda_o (i2c_sda_o),
.coe_i2c_sda_oe_n (i2c_sda_oe_n),
.hdmi_tx_reset_n_external_connection_export (HDMI_TX_RST_N),
// .i2s_tx_conduit_end_sck (gen_sck), // i2s_tx_conduit_end.sck
// .i2s_tx_conduit_end_ws (gen_ws), // .ws
// .i2s_tx_conduit_end_sd (gen_i2s),
.usb_coe_cs_n (OTG_CS_n), // usb.coe_cs_n
.usb_coe_rd_n (OTG_OE_n), // .coe_rd_n
.usb_coe_din (OTG_D), // .coe_din
.usb_coe_dout (otg_dout), // .coe_dout
.usb_coe_a (otg_a_temp), // .coe_a
.usb_coe_dc_irq_in (OTG_DC_IRQ), // .coe_dc_irq_in
.usb_coe_hc_irq_in (OTG_HC_IRQ), // .coe_hc_irq_in
//.usb_coe_dc_dreq_in (OTG_DC_DREQ), // .coe_dc_dreq_in
//.usb_coe_hc_dreq_in (OTG_HC_DREQ), // .coe_hc_dreq_in
//.usb_coe_dc_dack (OTG_DC_DACK), // .coe_dc_dack
//.usb_coe_hc_dack (OTG_HC_DACK), // .coe_hc_dack
.usb_coe_wr_n (OTG_WE_n), // .coe_wr_n
.fan_fan_on_pwm (FAN_CTRL), //
.fan_temp_lower_seg_n (SEG0_D), // .temp_lower_seg_n
.fan_temp_upper_seg_n (SEG1_D), // .temp_upper_seg_n.
.switches_export ({SLIDE_SW[3:0], BUTTON[3:0], SW_P[7:0]}),
.rs232_stx_pad_o (UART_TXD), // rs232.stx_pad_o
.rs232_srx_pad_i (UART_RXD), // .srx_pad_i
.rs232_rts_pad_o (UART_RTS), // .rts_pad_o
.rs232_cts_pad_i (UART_CTS), // .cts_pad_i
.rs232_dtr_pad_o (), // .dtr_pad_o
// I have no idea what these should be by default. Should see Simon's example project.
.rs232_dsr_pad_i (1'b1), // .dsr_pad_i
.rs232_ri_pad_i (1'b1), // .ri_pad_i
.rs232_dcd_pad_i (1'b1) // .dcd_pad_i
`ifdef ENABLE_PCIE
,
.pciexpressstream_0_refclk_export (PCIE_REFCLK_p),
.pciexpressstream_0_fixedclk_clk (clk125),
.pciexpressstream_0_cal_blk_clk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_gxbclk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_togxb_data (reconfig_togxb),
.pciexpressstream_0_reconfig_fromgxb_0_data (reconfig_fromgxb),
.pciexpressstream_0_reconfig_busy_busy_altgxb_reconfig (reconfig_busy),
.pciexpressstream_0_pcie_rstn_export (PCIE_PREST_n),
.pciexpressstream_0_rx_in_rx_datain_0 (PCIE_RX_p[0]),
.pciexpressstream_0_rx_in_rx_datain_1 (PCIE_RX_p[1]),
.pciexpressstream_0_rx_in_rx_datain_2 (PCIE_RX_p[2]),
.pciexpressstream_0_rx_in_rx_datain_3 (PCIE_RX_p[3]),
.pciexpressstream_0_tx_out_tx_dataout_0 (PCIE_TX_p[0]),
.pciexpressstream_0_tx_out_tx_dataout_1 (PCIE_TX_p[1]),
.pciexpressstream_0_tx_out_tx_dataout_2 (PCIE_TX_p[2]),
.pciexpressstream_0_tx_out_tx_dataout_3 (PCIE_TX_p[3])
`endif
);
// handle USB (OTG) reset signal
assign OTG_RESET_n = rstn100;
// handle unused flash reset signal
assign FLASH_RESET_n = rstn100;
// handle tristate ssram data bus
assign FSM_D = ssram_data_outen ? ssram_data_out : 16'bzzzzzzzzzzzzzzzz;
endmodule
|
module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_slave_wrp #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
// If the fifo depth is zero, the module will perform the write ack here,
// otherwise it will take the write ack from the input s_writeack.
parameter integer FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer PIPELINE = 1 // 0|1
)
(
input clock,
input resetn,
acl_arb_intf m_intf,
input logic s_writeack,
acl_ic_wrp_intf wrp_intf,
output logic stall
);
generate
if( NUM_MASTERS > 1 )
begin
// This slave endpoint may not directly talk to the ACTUAL slave. In
// this case we need a fifo to store which master each write ack should
// go to. If FIFO_DEPTH is 0 then we assume the writeack can be
// generated right here (the way it was done originally)
if( FIFO_DEPTH > 0 )
begin
// We don't have to worry about bursts, we'll fifo each transaction
// since writeack behaves like readdatavalid
logic rf_empty, rf_full;
acl_ll_fifo #(
.WIDTH( ID_W ),
.DEPTH( FIFO_DEPTH )
)
write_fifo(
.clk( clock ),
.reset( ~resetn ),
.data_in( m_intf.req.id ),
.write( ~m_intf.stall & m_intf.req.write ),
.data_out( wrp_intf.id ),
.read( wrp_intf.ack & ~rf_empty),
.empty( rf_empty ),
.full( rf_full )
);
// Register slave writeack to guarantee fifo output is ready
always @( posedge clock or negedge resetn )
begin
if( !resetn )
wrp_intf.ack <= 1'b0;
else
wrp_intf.ack <= s_writeack;
end
assign stall = rf_full;
end
else if( PIPELINE == 1 )
begin
assign stall = 1'b0;
always @( posedge clock or negedge resetn )
if( !resetn )
begin
wrp_intf.ack <= 1'b0;
wrp_intf.id <= 'x; // don't need to reset
end
else
begin
// Always register the id. The ack signal acts as the enable.
wrp_intf.id <= m_intf.req.id;
wrp_intf.ack <= 1'b0;
if( ~m_intf.stall & m_intf.req.write )
// A valid write cycle. Ack it.
wrp_intf.ack <= 1'b1;
end
end
else
begin
assign wrp_intf.id = m_intf.req.id;
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end
end
else // NUM_MASTERS == 1
begin
// Only one master so don't need to check the id.
if ( FIFO_DEPTH == 0 )
begin
assign wrp_intf.ack = ~m_intf.stall & m_intf.req.write;
assign stall = 1'b0;
end
else
begin
assign wrp_intf.ack = s_writeack;
assign stall = 1'b0;
end
end
endgenerate
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.0/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/02/08 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [2:0] a;
reg [2:0] b;
reg q;
f6 f6 (/*AUTOINST*/
// Outputs
.q (q),
// Inputs
.a (a[2:0]),
.b (b[2:0]),
.clk (clk));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 3'b000;
b <= 3'b100;
end
if (cyc==2) begin
a <= 3'b011;
b <= 3'b001;
if (q != 1'b0) $stop;
end
if (cyc==3) begin
a <= 3'b011;
b <= 3'b011;
if (q != 1'b0) $stop;
end
if (cyc==9) begin
if (q != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module f6 (a, b, clk, q);
input [2:0] a;
input [2:0] b;
input clk;
output q;
reg out;
function func6;
reg result;
input [5:0] src;
begin
if (src[5:0] == 6'b011011) begin
result = 1'b1;
end
else begin
result = 1'b0;
end
func6 = result;
end
endfunction
wire [5:0] w6 = {a, b};
always @(posedge clk) begin
out <= func6(w6);
end
assign q = out;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
// user signals
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
input wire [31:0] ap_return,
output wire [31:0] P_mode,
output wire [31:0] P_index1,
output wire [31:0] P_index2,
output wire [31:0] P_intIn_index3,
output wire [31:0] P_floatIn
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// 0x18 : Data signal of P_mode
// bit 31~0 - P_mode[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of P_index1
// bit 31~0 - P_index1[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of P_index2
// bit 31~0 - P_index2[31:0] (Read/Write)
// 0x2c : reserved
// 0x30 : Data signal of P_intIn_index3
// bit 31~0 - P_intIn_index3[31:0] (Read/Write)
// 0x34 : reserved
// 0x38 : Data signal of P_floatIn
// bit 31~0 - P_floatIn[31:0] (Read/Write)
// 0x3c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_AP_RETURN_0 = 6'h10,
ADDR_P_MODE_DATA_0 = 6'h18,
ADDR_P_MODE_CTRL = 6'h1c,
ADDR_P_INDEX1_DATA_0 = 6'h20,
ADDR_P_INDEX1_CTRL = 6'h24,
ADDR_P_INDEX2_DATA_0 = 6'h28,
ADDR_P_INDEX2_CTRL = 6'h2c,
ADDR_P_INTIN_INDEX3_DATA_0 = 6'h30,
ADDR_P_INTIN_INDEX3_CTRL = 6'h34,
ADDR_P_FLOATIN_DATA_0 = 6'h38,
ADDR_P_FLOATIN_CTRL = 6'h3c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
RDIDLE = 2'd0,
RDDATA = 2'd1,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
wire int_ap_idle;
wire int_ap_ready;
reg int_ap_done;
reg int_ap_start;
reg int_auto_restart;
reg int_gie;
reg [1:0] int_ier;
reg [1:0] int_isr;
reg [31:0] int_ap_return;
reg [31:0] int_P_mode;
reg [31:0] int_P_index1;
reg [31:0] int_P_index2;
reg [31:0] int_P_intIn_index3;
reg [31:0] int_P_floatIn;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRIDLE;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDIDLE;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_AP_RETURN_0: begin
rdata <= int_ap_return[31:0];
end
ADDR_P_MODE_DATA_0: begin
rdata <= int_P_mode[31:0];
end
ADDR_P_INDEX1_DATA_0: begin
rdata <= int_P_index1[31:0];
end
ADDR_P_INDEX2_DATA_0: begin
rdata <= int_P_index2[31:0];
end
ADDR_P_INTIN_INDEX3_DATA_0: begin
rdata <= int_P_intIn_index3[31:0];
end
ADDR_P_FLOATIN_DATA_0: begin
rdata <= int_P_floatIn[31:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign int_ap_idle = ap_idle;
assign int_ap_ready = ap_ready;
assign P_mode = int_P_mode;
assign P_index1 = int_P_index1;
assign P_index2 = int_P_index2;
assign P_intIn_index3 = int_P_intIn_index3;
assign P_floatIn = int_P_floatIn;
// int_ap_start
always @(posedge ACLK) begin
if (ARESET)
int_ap_start <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
int_ap_start <= 1'b1;
else if (int_ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
end
// int_ap_done
always @(posedge ACLK) begin
if (ARESET)
int_ap_done <= 1'b0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_done <= 1'b1;
else if (ar_hs && raddr == ADDR_AP_CTRL)
int_ap_done <= 1'b0; // clear on read
end
end
// int_auto_restart
always @(posedge ACLK) begin
if (ARESET)
int_auto_restart <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
int_auto_restart <= WDATA[7];
end
end
// int_gie
always @(posedge ACLK) begin
if (ARESET)
int_gie <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
end
// int_ier
always @(posedge ACLK) begin
if (ARESET)
int_ier <= 1'b0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[1:0];
end
end
// int_isr[0]
always @(posedge ACLK) begin
if (ARESET)
int_isr[0] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
end
// int_isr[1]
always @(posedge ACLK) begin
if (ARESET)
int_isr[1] <= 1'b0;
else if (ACLK_EN) begin
if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
end
// int_ap_return
always @(posedge ACLK) begin
if (ARESET)
int_ap_return <= 0;
else if (ACLK_EN) begin
if (ap_done)
int_ap_return <= ap_return;
end
end
// int_P_mode[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_mode[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_MODE_DATA_0)
int_P_mode[31:0] <= (WDATA[31:0] & wmask) | (int_P_mode[31:0] & ~wmask);
end
end
// int_P_index1[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_index1[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_INDEX1_DATA_0)
int_P_index1[31:0] <= (WDATA[31:0] & wmask) | (int_P_index1[31:0] & ~wmask);
end
end
// int_P_index2[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_index2[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_INDEX2_DATA_0)
int_P_index2[31:0] <= (WDATA[31:0] & wmask) | (int_P_index2[31:0] & ~wmask);
end
end
// int_P_intIn_index3[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_intIn_index3[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_INTIN_INDEX3_DATA_0)
int_P_intIn_index3[31:0] <= (WDATA[31:0] & wmask) | (int_P_intIn_index3[31:0] & ~wmask);
end
end
// int_P_floatIn[31:0]
always @(posedge ACLK) begin
if (ARESET)
int_P_floatIn[31:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_P_FLOATIN_DATA_0)
int_P_floatIn[31:0] <= (WDATA[31:0] & wmask) | (int_P_floatIn[31:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_1_V
`define SKY130_FD_SC_LP__AND4B_1_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_1 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and4b_1 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3_SYMBOL_V
`define SKY130_FD_SC_LS__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_1_V
`define SKY130_FD_SC_HS__SEDFXBP_1_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_1 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_1_V
|
module ControlUnit(input[5:0] opcode,
input[5:0] funct,
output reg reg_dst,
output reg reg_write,
output reg[1:0] alu_src,
output reg[3:0] alu_op,
output reg branch,
output reg mem_write,
output reg mem_to_reg,
output reg zero_sign_ext,
output reg mult_op,
output reg mfhi,
output reg mflo);
always @(opcode, funct) begin
// Make sure that all output have an initial value assigned in
// order to prevent synthesis of sequential logic.
reg_dst = 1'bx;
reg_write = 1'bx;
alu_src = 2'bxx;
alu_op = 4'bxxxx;
branch = 1'bx;
mem_write = 1'bx;
mem_to_reg = 1'bx;
zero_sign_ext = 1'bx;
mult_op = 1'b0; // use the multiply/div alu
mfhi = 1'b0; // move from hi
mflo = 1'b0; // move from lo
// Check opcode
case (opcode)
// If opcode is 0, check funct
6'h00: begin
// Common signals
reg_dst = 1;
reg_write = 1;
alu_src = 0;
branch = 0;
mem_write = 0;
mem_to_reg = 0;
// ALU operation depends on funct
case (funct)
// add
6'h20: begin
alu_op = 4'b0000;
$display("\tInstruction 'add'");
end
//addu
6'h21: begin
alu_op = 4'b0000;
$display("\tInstruction 'addu'");
end
// sub
6'h22: begin
alu_op = 4'b0001;
$display("\tInstruction 'sub'");
end
// subu
6'h23: begin
alu_op = 4'b0001;
$display("\tInstruction 'subu'");
end
// and
6'h24: begin
alu_op = 4'b0010;
$display("\tInstruction 'and'");
end
// nor
6'h27: begin
alu_op = 4'b0100;
$display("\tInstruction 'nor'");
end
// or
6'h25: begin
alu_op = 4'b0011;
$display("\tInstruction 'or'");
end
// xor
6'h26: begin
alu_op = 4'b0101;
$display("\tInstruction 'xor'");
end
// sll
6'h0: begin
alu_op = 6;
alu_src = 2;
$display("\tInstruction 'sll'");
end
// srl
6'h2: begin
alu_op = 7;
alu_src = 2;
$display("\tInstruction 'srl'");
end
// sra
6'h3: begin
alu_op = 8;
alu_src = 2;
$display("\tInstruction 'sra'");
end
// sllv
6'h4: begin
alu_op = 6;
$display("\tInstruction 'sllv'");
end
// srlv
6'h6: begin
alu_op = 7;
$display("\tInstruction 'srlv'");
end
// srav
6'h7: begin
alu_op = 8;
$display("\tInstruction 'srav'");
end
// slt
6'h2a: begin
alu_op = 4'b1001;
$display("\tInstruction 'slt'");
end
// sltu
6'h2b: begin
alu_op = 4'b1010;
$display("\tInstruction 'sltu'");
end
// mult
6'h18: begin
mult_op = 1;
reg_write = 0;
alu_op = 4'b0010;
$display("\tInstruction 'mult'");
end
// multu
6'h19: begin
mult_op = 1;
reg_write = 0;
alu_op = 4'b0011;
$display("\tInstruction 'multu'");
end
// div
6'h1A: begin
mult_op = 1;
reg_write = 0;
alu_op = 4'b0000;
$display("\tInstruction 'div'");
end
// divu
6'h1B: begin
mult_op = 1;
reg_write = 0;
alu_op = 4'b0001;
$display("\tInstruction 'divu'");
end
// mfhi
6'h10: begin
alu_op = 4'b1111;
mfhi = 1;
$display("\tInstruction 'mfhi'");
end
// mflo
6'h12: begin
alu_op = 4'b1111;
mflo = 1;
$display("\tInstruction 'mflo'");
end
endcase
end
// lw
6'h23: begin
reg_dst = 0;
reg_write = 1;
alu_src = 1;
alu_op = 4'b0000;
branch = 0;
mem_write = 0;
mem_to_reg = 1;
zero_sign_ext = 0;
$display("\tInstruction 'lw'");
end
// sw
6'h2b: begin
reg_write = 0;
alu_src = 1;
alu_op = 4'b0000;
branch = 0;
mem_write = 1;
zero_sign_ext = 0;
$display("\tInstruction 'sw'");
end
// beq
6'h04: begin
reg_write = 0;
alu_src = 0;
alu_op = 4'b0001;
branch = 1;
mem_write = 0;
$display("\tInstruction 'beq'");
end
endcase
end
endmodule
|
/*
* File: imx_cbu.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description: Core Bridge Unit - ÇŽÓcoreµÄimxºÍƬÉÏ»¥Á¬ÐÒé
* IMXºÍWBµÄÒìͬ
1£¬IMXÎÞÐèslaveʹÓÃrtyÐźţ¬masterÔÚslaveûÓзµ»ØackÇ°±£³ÖÇëÇó
2£¬IMXÐèÒª·µ»Øµ±Ç°ÇëÇóµÄaddrÐźÅ
3£¬IMXµÄΨһÍê³ÉÐźÅΪack£¬errÔÚackΪÓÐЧʱֵ²ÅÓÐÒâÒå
* Task.I:
verification environment for complex imx-cbu-wb interaction
1, IMXÁ¬ÐøÇëÇóÇé¿ö
2, ²»Í¬×ÜÏßʱ¿ÌÈ¡ÏûIMXÇëÇóµÄÇé¿ö£¬È¡Ïûºó»Ö¸´ÓÐЧ»òÐÂÇëÇóÓÐЧµÄÇé¿ö
3, ÊÇ·ñ´æÔÚIMXÇëÇóÒ»Ö±ÓÐЧ£¬µ«µØÖ··¢Éú±ä»¯µÄÇé¿ö£¿´¦ÀíÆ÷ÄÚºËÓ¦¸Ã²»»á³öÏÖ£¬ÇëÇóÈ¡Ïûʱ±ØÐëÓÐÒ»ÅÄ¿ÕÏÐ
* Task.II:
¿çʱÖÓÓòÖ§³Ö
Burst´«ÊäÖ§³Ö
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module imx_cbu(
clk, rst,
wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o, wb_cti_o, wb_bte_o,
wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
cbu_dat_i, cbu_adr_i, cbu_rqt_i, cbu_we_i, cbu_sel_i,
cbu_ack_o, cbu_dat_o, cbu_err_o, cbu_adr_o
);
parameter dw = 32;
parameter aw = 32;
// currently no burst support
`define WB_CTI 3'b000
`define WB_BTE 2'b00
//
// core clock, reset and clock control
//
input clk; // core clock
input rst; // core reset
//
// core-bridge unit interface
//
input [aw-1:0] cbu_adr_i; // core request address
input [dw-1:0] cbu_dat_i; // core request data
input cbu_rqt_i; // core request valid
input cbu_we_i; // core request w/r flag
input [3:0] cbu_sel_i; // core request byte selects
output cbu_ack_o; // bus response valid(ack)
output cbu_err_o; // bus response error
output [dw-1:0] cbu_dat_o; // bus response data
output [aw-1:0] cbu_adr_o; // bus response address
//
// WISHBONE interface
//
input wb_ack_i; // normal termination
input wb_err_i; // termination with error
input wb_rty_i; // termination with retry
input [dw-1:0] wb_dat_i; // data input
output wb_cyc_o; // cycle valid output
output [aw-1:0] wb_adr_o; // address output
output wb_stb_o; // strobe output
output wb_we_o; // indicates write/read transfer
output [3:0] wb_sel_o; // byte select output
output [dw-1:0] wb_dat_o; // data output
output [2:0] wb_cti_o; // cycle type identifier
output [1:0] wb_bte_o; // burst type extension
//
// reg & wires
//
reg wb_cyc_o;
reg [aw-1:0] wb_adr_o;
reg wb_stb_o;
reg wb_we_o;
reg [3:0] wb_sel_o;
reg [dw-1:0] wb_dat_o;
reg [2:0] wb_cti_o;
reg [1:0] wb_bte_o;
reg [dw-1:0] cbu_dat_o;
reg cbu_ack_o;
reg cbu_err_o;
reg [aw-1:0] cbu_adr_o;
//
// logic implementation
//
// registered request
always @(posedge clk or posedge rst) begin
if (rst) begin
wb_cyc_o <= #1 1'b0;
wb_stb_o <= #1 1'b0;
wb_dat_o <= #1 32'd0;
wb_adr_o <= #1 32'd0;
wb_sel_o <= #1 4'd0;
wb_we_o <= #1 1'd0;
wb_cti_o <= #1 3'd0;
wb_bte_o <= #1 2'd0;
end
else begin
if (cbu_rqt_i)
begin
wb_cyc_o <= #1 cbu_rqt_i;
wb_stb_o <= #1 cbu_rqt_i;
wb_dat_o <= #1 cbu_dat_i;
wb_adr_o <= #1 cbu_adr_i;
wb_sel_o <= #1 cbu_sel_i;
wb_we_o <= #1 cbu_we_i;
wb_cti_o <= #1 `WB_CTI;
wb_bte_o <= #1 `WB_BTE;
end
else begin // when core cancel bus request
wb_cyc_o <= #1 1'b0;
wb_stb_o <= #1 1'b0;
wb_dat_o <= #1 32'd0;
wb_adr_o <= #1 32'd0;
wb_sel_o <= #1 4'd0;
wb_we_o <= #1 1'd0;
wb_cti_o <= #1 3'd0;
wb_bte_o <= #1 2'd0;
end
end
end
// registered request
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_ack_o <= #1 1'b0;
cbu_err_o <= #1 1'b0;
end
else begin
if (cbu_rqt_i)
begin
cbu_ack_o <= #1 wb_ack_i;
cbu_err_o <= #1 wb_err_i;
end
else begin
cbu_ack_o <= #1 1'b0;
cbu_err_o <= #1 1'b0;
end
end
end
// special case for IMX
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_dat_o <= #1 32'd0;
end
else begin
cbu_dat_o <= #1 wb_dat_i;
end
end
// special case for IMX
always @(posedge clk or posedge rst) begin
if (rst) begin
cbu_adr_o <= #1 32'd0;
end
else begin
cbu_adr_o <= #1 cbu_adr_i;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_d (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "c.array_arith.autotvin_d.dat",
TV_OUT = "impl_rtl.array_arith.autotvout_d.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 32;
parameter ADDR_WIDTH = 32'd 3;
parameter DEPTH = 32'd 5;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
// synthesis translate_off
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcierd_cdma_ecrc_check_128.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module performs the PCIE ECRC check on the 128-bit Avalon-ST RX data stream.
//-----------------------------------------------------------------------------
// Copyright (c) 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcierd_cdma_ecrc_check_128 (
input clk_in,
input srst,
input[139:0] rxdata,
input[15:0] rxdata_be,
input rx_stream_valid0,
output rx_stream_ready0_ecrc,
output reg [139:0] rxdata_ecrc,
output reg [15:0] rxdata_be_ecrc,
output reg rx_stream_valid0_ecrc,
input rx_stream_ready0,
output reg rx_ecrc_check_valid,
output reg [15:0] ecrc_bad_cnt
);
localparam RAM_DATA_WIDTH = 140;
localparam RAM_ADDR_WIDTH = 8;
localparam PIPELINE_DEPTH =4;
// Bits in rxdata
localparam SOP_BIT = 139;
localparam EOP_BIT = 136;
localparam EMPTY_BIT = 137;
wire rx_sop;
reg rx_sop_crc_in;
wire rx_eop;
reg rx_eop_reg;
reg rx_eop_crc_in;
reg [3:0] rx_empty;
wire [31:0] crc_32;
wire crcbad;
wire crcvalid;
// Set TLP length
reg [9:0] ctrlrx_cnt_len_dw;
reg [9:0] ctrlrx_cnt_len_dw_reg;
// Set when TLP is 3 DW header
wire ctrlrx_payload;
reg ctrlrx_payload_reg;
// Set when TLP is 3 DW header
wire ctrlrx_3dw;
reg ctrlrx_3dw_reg;
// Set when TLP are qword aligned
wire ctrlrx_qword_aligned;
reg ctrlrx_qword_aligned_reg;
// Set when the TD digest bit is set in the descriptor
wire ctrlrx_digest;
reg ctrlrx_digest_reg;
reg [PIPELINE_DEPTH-1:0] ctrlrx_digest_pipe;
reg[139:0] rxdata_pipeline [PIPELINE_DEPTH-1:0];
reg[15:0] rxdata_be_pipeline [PIPELINE_DEPTH-1:0];
reg[PIPELINE_DEPTH-1:0] rx_stream_valid_pipeline;
wire ctrlrx_3dw_aligned;
reg ctrlrx_3dw_aligned_reg;
wire ctrlrx_3dw_nonaligned;
reg ctrlrx_3dw_nonaligned_reg;
wire ctrlrx_4dw_non_aligned;
reg ctrlrx_4dw_non_aligned_reg;
wire ctrlrx_4dw_aligned;
reg ctrlrx_4dw_aligned_reg;
reg ctrlrx_single_cycle_reg;
integer i;
reg [127:0] rxdata_crc_reg ;
wire rx_valid_crc_in ;
wire [127:0] rxdata_byte_swap ;
wire [127:0] rxdata_crc_in ;
wire ctrlrx_single_cycle;
reg [10:0] rx_payld_remain_dw;
wire [10:0] rx_payld_len;
reg rx_valid_crc_pending;
reg single_crc_cyc;
reg send_rx_eop_crc_early;
reg debug_ctrlrx_4dw_offset0;
reg debug_ctrlrx_4dw_offset1;
reg debug_ctrlrx_4dw_offset2;
reg debug_ctrlrx_4dw_offset3;
reg debug_ctrlrx_3dw_offset0;
reg debug_ctrlrx_3dw_offset1;
reg debug_ctrlrx_3dw_offset2;
reg debug_ctrlrx_3dw_offset3;
reg debug_ctrlrx_4dw_offset0_nopayld;
reg debug_ctrlrx_4dw_offset1_nopayld;
reg debug_ctrlrx_4dw_offset2_nopayld;
reg debug_ctrlrx_4dw_offset3_nopayld;
reg debug_ctrlrx_3dw_offset0_nopayld;
reg debug_ctrlrx_3dw_offset1_nopayld;
reg debug_ctrlrx_3dw_offset2_nopayld;
reg debug_ctrlrx_3dw_offset3_nopayld;
wire[11:0] zeros12; assign zeros12 = 12'h0;
wire[7:0] zeros8; assign zeros8 = 8'h0;
wire[3:0] zeros4; assign zeros4 = 4'h0;
wire[15:0] rxdata_be_15_12; assign rxdata_be_15_12 = {rxdata_be[15:12], zeros12};
wire[15:0] rxdata_be_15_8; assign rxdata_be_15_8 = {rxdata_be[15:8], zeros8};
wire[15:0] rxdata_be_15_4; assign rxdata_be_15_4 = {rxdata_be[15:4], zeros4};
////////////////////////////////////////////////////////////////////////////
//
// Drop ECRC field from the data stream/rx_be.
// Regenerate rx_st_eop.
// Set TD bit to 0.
//
assign rx_payld_len = (rxdata[105:96] == 0) ? 11'h400 : {1'b0, rxdata[105:96]}; // account for 1024DW
always @ (posedge clk_in ) begin
if (srst==1'b1) begin
rxdata_ecrc <= 140'h0;
rxdata_be_ecrc <= 16'h0;
rx_payld_remain_dw <= 11'h0;
rx_stream_valid0_ecrc <= 1'b0;
end
else begin
rxdata_ecrc[138] <= 1'b0;
rx_stream_valid0_ecrc <= 1'b0; // default
/////////////////////////
// TLP has Digest
//
if (ctrlrx_digest==1'b1) begin
if (rx_sop==1'b1) begin
rxdata_ecrc[111] <= 1'b0;
rxdata_ecrc[135:112] <= rxdata[135:112];
rxdata_ecrc[110:0] <= rxdata[110:0];
rxdata_ecrc[SOP_BIT] <= 1'b1;
rxdata_ecrc[EOP_BIT] <= (rxdata[126]==1'b0) | ((ctrlrx_3dw==1'b1) & (ctrlrx_qword_aligned==1'b0) & (rxdata[105:96]==10'h1));
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be;
rx_stream_valid0_ecrc <= 1'b1;
// Load the # of payld DWs remaining in next cycles
if (rxdata[126]==1'b1) begin // if there is payload
if ((ctrlrx_3dw==1'b1) & (ctrlrx_qword_aligned==1'b0)) begin
rx_payld_remain_dw <= rx_payld_len - 1;
end
// 3DW aligned, or 4DW nonaligned
// Add 1 DW to account for empty field
else if ( //((ctrlrx_3dw==1'b1) & (ctrlrx_qword_aligned==1'b1)) |
((ctrlrx_3dw==1'b0) & (ctrlrx_qword_aligned==1'b0)) ) begin
rx_payld_remain_dw <= rx_payld_len + 1;
end
else begin
rx_payld_remain_dw <= rx_payld_len;
end
end
else begin
rx_payld_remain_dw <= 11'h0;
end
end
else if (rx_stream_valid0==1'b1) begin
rxdata_ecrc[SOP_BIT] <= 1'b0;
rxdata_ecrc[135:0] <= rxdata[135:0];
case (rx_payld_remain_dw)
11'h1: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_ecrc[EMPTY_BIT] <= 1'b1;
rxdata_be_ecrc <= rxdata_be_15_12;
end
11'h2: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_ecrc[EMPTY_BIT] <= 1'b1;
rxdata_be_ecrc <= rxdata_be_15_8;
end
11'h3: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be_15_4;
end
11'h4: begin
rxdata_ecrc[EOP_BIT] <= 1'b1;
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be[15:0];
end
default: begin
rxdata_ecrc[EOP_BIT] <= 1'b0;
rxdata_ecrc[EMPTY_BIT] <= 1'b0;
rxdata_be_ecrc <= rxdata_be[15:0];
end
endcase
rx_stream_valid0_ecrc <= (rx_payld_remain_dw > 11'h0) ? 1'b1 : 1'b0;
// Decrement payld count as payld is received
rx_payld_remain_dw <= (rx_payld_remain_dw < 4) ? 11'h0 : rx_payld_remain_dw - 11'h4;
end
end
///////////////
// No Digest
//
else begin
rxdata_ecrc <= rxdata;
rxdata_be_ecrc <= rxdata_be;
rx_stream_valid0_ecrc <= rx_stream_valid0;
end
end
end
////////////////////////////////////////////////////////////////////////////
//
// RX Avalon-ST input delayed of PIPELINE_DEPTH to RX Avalon-ST output
//
assign rx_stream_ready0_ecrc = rx_stream_ready0;
////////////////////////////////////////////////////////////////////////////
//
// CRC MegaCore instanciation
//
altpcierd_rx_ecrc_128 rx_ecrc_128 (
.reset_n (~srst),
.clk (clk_in),
.data (rxdata_crc_in[127:0]),
.datavalid (ctrlrx_digest_reg & rx_valid_crc_in), // use registered version of ctrlrx_digest since crc_in is delayed 1 cycle from input
.startofpacket (rx_sop_crc_in),
.endofpacket (rx_eop_crc_in),
.empty (rx_empty),
.crcbad (crcbad),
.crcvalid (crcvalid));
assign rx_valid_crc_in = (rx_sop_crc_in & (ctrlrx_single_cycle | rx_stream_valid0)) |
(rx_valid_crc_pending & rx_stream_valid0) |
(rx_eop_crc_in & ~send_rx_eop_crc_early);
// Inputs to the MegaCore
always @(posedge clk_in) begin
if (srst==1'b1) begin
rx_valid_crc_pending <= 1'b0;
rx_sop_crc_in <= 1'b0;
rx_eop_crc_in <= 1'b0;
rx_empty <= 1'b0;
send_rx_eop_crc_early <= 1'b0;
ctrlrx_3dw_aligned_reg <= 1'b0;
ctrlrx_3dw_nonaligned_reg <= 1'b0;
ctrlrx_4dw_non_aligned_reg <= 1'b0;
ctrlrx_4dw_aligned_reg <= 1'b0;
debug_ctrlrx_4dw_offset0 <= 1'b0;
debug_ctrlrx_4dw_offset1 <= 1'b0;
debug_ctrlrx_4dw_offset2 <= 1'b0;
debug_ctrlrx_4dw_offset3 <= 1'b0;
debug_ctrlrx_3dw_offset0 <= 1'b0;
debug_ctrlrx_3dw_offset1 <= 1'b0;
debug_ctrlrx_3dw_offset2 <= 1'b0;
debug_ctrlrx_3dw_offset3 <= 1'b0;
debug_ctrlrx_4dw_offset0_nopayld <= 1'b0;
debug_ctrlrx_4dw_offset1_nopayld <= 1'b0;
debug_ctrlrx_4dw_offset2_nopayld <= 1'b0;
debug_ctrlrx_4dw_offset3_nopayld <= 1'b0;
debug_ctrlrx_3dw_offset0_nopayld <= 1'b0;
debug_ctrlrx_3dw_offset1_nopayld <= 1'b0;
debug_ctrlrx_3dw_offset2_nopayld <= 1'b0;
debug_ctrlrx_3dw_offset3_nopayld <= 1'b0;
end
else begin
if ((rx_sop==1'b1) & (rx_stream_valid0==1'b1) & (ctrlrx_digest==1'b1) ) begin
rx_sop_crc_in <= 1'b1;
end
else if ((rx_sop_crc_in==1'b1) & (rx_valid_crc_in==1'b1)) begin
rx_sop_crc_in <= 1'b0;
end
ctrlrx_3dw_aligned_reg <= ctrlrx_3dw_aligned;
ctrlrx_3dw_nonaligned_reg <= ctrlrx_3dw_nonaligned;
ctrlrx_4dw_non_aligned_reg <= ctrlrx_4dw_non_aligned;
ctrlrx_4dw_aligned_reg <= ctrlrx_4dw_aligned;
if ((rx_stream_valid0==1'b1) & (rx_sop==1'b1)) begin
debug_ctrlrx_4dw_offset0 <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b1) & (rxdata[3:0]==4'h0); // no addr offset
debug_ctrlrx_4dw_offset1 <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b1) & (rxdata[3:0]==4'h4); // 1DW addr offset
debug_ctrlrx_4dw_offset2 <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b1) & (rxdata[3:0]==4'h8); // 2DW addr offset
debug_ctrlrx_4dw_offset3 <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b1) & (rxdata[3:0]==4'hc); // 3DW addr offset
debug_ctrlrx_3dw_offset0 <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b1) & (rxdata[35:32]==4'h0); // no addr offset
debug_ctrlrx_3dw_offset1 <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b1) & (rxdata[35:32]==4'h4); // 1DW addr offset
debug_ctrlrx_3dw_offset2 <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b1) & (rxdata[35:32]==4'h8); // 2DW addr offset
debug_ctrlrx_3dw_offset3 <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b1) & (rxdata[35:32]==4'hc); // 3DW addr offset
debug_ctrlrx_4dw_offset0_nopayld <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b0) & (rxdata[3:0]==4'h0); // no addr offset
debug_ctrlrx_4dw_offset1_nopayld <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b0) & (rxdata[3:0]==4'h4); // 1DW addr offset
debug_ctrlrx_4dw_offset2_nopayld <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b0) & (rxdata[3:0]==4'h8); // 2DW addr offset
debug_ctrlrx_4dw_offset3_nopayld <= (ctrlrx_3dw==1'b0) & (rxdata[126]==1'b0) & (rxdata[3:0]==4'hc); // 3DW addr offset
debug_ctrlrx_3dw_offset0_nopayld <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b0) & (rxdata[35:32]==4'h0); // no addr offset
debug_ctrlrx_3dw_offset1_nopayld <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b0) & (rxdata[35:32]==4'h4); // 1DW addr offset
debug_ctrlrx_3dw_offset2_nopayld <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b0) & (rxdata[35:32]==4'h8); // 2DW addr offset
debug_ctrlrx_3dw_offset3_nopayld <= (ctrlrx_3dw==1'b1) & (rxdata[126]==1'b0) & (rxdata[35:32]==4'hc); // 3DW addr offset
end
if ((rx_sop==1'b1) & (rx_stream_valid0==1'b1) & (ctrlrx_digest==1'b1)) begin
if ((ctrlrx_3dw==1'b1) & (ctrlrx_payload==1'b0)) begin
rx_eop_crc_in <= 1'b1; // Pack ECRC into single cycle
rx_empty <= 1'b0;
rx_valid_crc_pending <= 1'b0;
end
else begin
rx_eop_crc_in <= 1'b0; // multicycle
rx_empty <= 1'b0;
rx_valid_crc_pending <= 1'b1;
// eop is sent 1 cycle early when the payld is a multiple
// of 4DWs, and the TLP is 3DW Header aligned
send_rx_eop_crc_early <= (ctrlrx_3dw_aligned==1'b1) & (ctrlrx_payload==1'b1) & (rxdata[97:96]==2'h0);
end
end
else if (rx_valid_crc_pending == 1'b1) begin
// end crc data early
if (send_rx_eop_crc_early==1'b1) begin
rx_valid_crc_pending <= ((ctrlrx_cnt_len_dw == 10'h0) & (rx_stream_valid0==1'b1)) ? 1'b0 : 1'b1;
if ((ctrlrx_cnt_len_dw == 10'h4)& (rx_stream_valid0==1'b1)) begin
rx_eop_crc_in <= 1'b1;
rx_empty <= 4'h0;
end
end
// end on eop
else begin
// rx_valid_crc_pending <= (rx_eop_crc_in==1'b1) ? 1'b0 : rx_valid_crc_pending;
if ((rx_eop==1'b1) & (rx_stream_valid0==1'b1)) begin
rx_eop_crc_in <= 1'b1;
rx_valid_crc_pending <= 1'b0;
case (ctrlrx_cnt_len_dw)
10'h1: rx_empty <= 4'hc;
10'h2: rx_empty <= 4'h8;
10'h3: rx_empty <= 4'h4;
default: rx_empty <= 4'h0;
endcase
end
end
end
else begin
rx_eop_crc_in <= 1'b0;
rx_empty <= 4'h0;
end
end
end
// rxdata_byte_swap is :
// - Set variant bit to 1 The EP field is variant
// - Byte swap the data and not the header
// - The header is already byte order ready for the CRC (lower byte first) such as :
// | H0 byte 0,1,2,3
// rxdata[127:0] | H1 byte 4,5,6,7
// | H2 byte 8,9,10,11
// | H3 byte 12,13,14,15
// - The Data requires byte swaping
// rxdata
//
always @(posedge clk_in) begin
if (rx_stream_valid0==1'b1) begin
if (ctrlrx_3dw_aligned==1'b1) begin
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else
rxdata_crc_reg[127:0] <= {
rxdata[71:64 ], rxdata[79 : 72], rxdata[87 : 80], rxdata[95 : 88], //D1
rxdata[39:32 ], rxdata[47 : 40], rxdata[55 : 48], rxdata[63 : 56], // D2
rxdata[7:0 ], rxdata[15 : 8], rxdata[23 : 16], rxdata[31 : 24], // D3
rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120]}; // D0
end
else if (ctrlrx_4dw_non_aligned==1'b1) begin
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else begin
rxdata_crc_reg[127:0] <= {
rxdata[71:64 ], rxdata[79 : 72], rxdata[87 : 80], rxdata[95 : 88], //D1
rxdata[39:32 ], rxdata[47 : 40], rxdata[55 : 48], rxdata[63 : 56], // D2
rxdata[7:0 ], rxdata[15 : 8], rxdata[23 : 16], rxdata[31 : 24], // D3
rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120]}; // D0
end
end
else if (ctrlrx_4dw_aligned==1'b1) begin
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:0] <= rxdata[109:0];
end
else begin
rxdata_crc_reg[127:0] <= {
rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120], // D0
rxdata[71:64 ], rxdata[79 : 72], rxdata[87 : 80], rxdata[95 : 88], //D1
rxdata[39:32 ], rxdata[47 : 40], rxdata[55 : 48], rxdata[63 : 56], // D2
rxdata[7:0 ], rxdata[15 : 8], rxdata[23 : 16], rxdata[31 : 24] // D3
};
end
end
else // 3DW nonaligned
if (rx_sop==1'b1) begin
rxdata_crc_reg[127:121] <= rxdata[127:121];
rxdata_crc_reg[120] <= 1'b1;
rxdata_crc_reg[119:111] <= rxdata[119:111];
rxdata_crc_reg[110] <= 1'b1;
rxdata_crc_reg[109:32] <= rxdata[109:32];
if (ctrlrx_3dw==1'b1) begin
// 3 DWORD Header with payload byte swapping the first data D0
rxdata_crc_reg[31:24] <= rxdata[7:0];
rxdata_crc_reg[23:16] <= rxdata[15:8];
rxdata_crc_reg[15:8] <= rxdata[23:16];
rxdata_crc_reg[7:0] <= rxdata[31:24];
end
else
// 4 DWORD Header no need to swap bytes
rxdata_crc_reg[31:0] <= rxdata[31:0];
end
else
rxdata_crc_reg[127:0] <= {
rxdata[103:96], rxdata[111:104], rxdata[119:112], rxdata[127:120],
rxdata[71 :64], rxdata[79 :72 ], rxdata[87 :80 ], rxdata[95 : 88],
rxdata[39 :32], rxdata[47 :40 ], rxdata[55 :48 ], rxdata[63 : 56],
rxdata[7 :0 ], rxdata[15 : 8 ], rxdata[23 :16 ], rxdata[31 : 24]};
end
end
assign rxdata_crc_in[127:0] = (ctrlrx_3dw_aligned_reg==1'b1) ? {rxdata_crc_reg[127:32], // previous 3DW
rxdata[103:96 ], // current DW (byte flipped)
rxdata[111:104],
rxdata[119:112],
rxdata[127:120]} :
((ctrlrx_4dw_non_aligned_reg==1'b1) & (rx_sop_crc_in==1'b0)) ? {rxdata_crc_reg[127:32], // previous 3DW
rxdata[103:96 ], // current DW (byte flipped)
rxdata[111:104],
rxdata[119:112],
rxdata[127:120]} : rxdata_crc_reg[127:0];
//////////////////////////////////////////////////////////////////////////
//
// BAD ECRC Counter output (ecrc_bad_cnt
//
always @(posedge clk_in) begin
if (srst==1'b1) begin
rx_ecrc_check_valid <= 1'b1;
ecrc_bad_cnt <= 0;
end
else if ((crcvalid==1'b1) && (crcbad==1'b1)) begin
if (ecrc_bad_cnt<16'hFFFF)
ecrc_bad_cnt <= ecrc_bad_cnt+1;
if (rx_ecrc_check_valid==1'b1)
rx_ecrc_check_valid <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////
//
// Misc. Avalon-ST control signals
//
assign rx_sop = ((rxdata[139]==1'b1) && (rx_stream_valid0==1'b1))?1'b1:1'b0;
assign rx_eop = ((rxdata[136]==1'b1) && (rx_stream_valid0==1'b1))?1'b1:1'b0;
always @(posedge clk_in) begin
if (srst==1'b1) begin
ctrlrx_3dw_reg <=1'b0;
ctrlrx_qword_aligned_reg <=1'b0;
ctrlrx_digest_reg <=1'b0;
ctrlrx_single_cycle_reg <= 1'b0;
ctrlrx_payload_reg <=1'b0;
end
else begin
ctrlrx_3dw_reg <=ctrlrx_3dw;
ctrlrx_qword_aligned_reg <= ctrlrx_qword_aligned;
ctrlrx_digest_reg <=ctrlrx_digest;
ctrlrx_single_cycle_reg <= ctrlrx_single_cycle;
ctrlrx_payload_reg <= ctrlrx_payload;
end
end
assign ctrlrx_single_cycle = (rx_sop==1'b1) ? ((rx_eop==1'b1) ? 1'b1 : 1'b0) : ctrlrx_single_cycle_reg;
// ctrlrx_payload is set when the TLP has payload
assign ctrlrx_payload = (rx_sop==1'b1) ? ( (rxdata[126]==1'b1) ? 1'b1 : 1'b0) : ctrlrx_payload_reg;
// ctrlrx_3dw is set when the TLP has 3 DWORD header
assign ctrlrx_3dw = (rx_sop==1'b1) ? ((rxdata[125]==1'b0) ? 1'b1 : 1'b0) : ctrlrx_3dw_reg;
// ctrlrx_qword_aligned is set when the data are address aligned
assign ctrlrx_qword_aligned = (rx_sop==1'b1)? ((
((ctrlrx_3dw==1'b1) && (rxdata[34:32]==0)) ||
((ctrlrx_3dw==1'b0) && (rxdata[2:0]==0)) ) ? 1'b1: 1'b0 ) :
ctrlrx_qword_aligned_reg;
assign ctrlrx_digest = (rx_sop==1'b1) ? rxdata[111]:ctrlrx_digest_reg;
assign ctrlrx_3dw_aligned = ((ctrlrx_3dw==1'b1) && (ctrlrx_qword_aligned==1'b1))?1'b1:1'b0;
assign ctrlrx_3dw_nonaligned = ((ctrlrx_3dw==1'b1) &&
(ctrlrx_qword_aligned==1'b0))?1'b1:1'b0;
assign ctrlrx_4dw_non_aligned = ((ctrlrx_3dw==1'b0) && (ctrlrx_qword_aligned==1'b0))?1'b1:1'b0;
assign ctrlrx_4dw_aligned = ((ctrlrx_3dw==1'b0) && (ctrlrx_qword_aligned==1'b1))?1'b1:1'b0;
always @(posedge clk_in) begin
// ctrlrx_cnt_len_dw counts the number remaining
// number of DWORD in rxdata_crc_reg
ctrlrx_cnt_len_dw_reg <= (rx_stream_valid0) ? ctrlrx_cnt_len_dw : ctrlrx_cnt_len_dw_reg;
if (srst==1'b1)
ctrlrx_cnt_len_dw <= 0;
else if (rx_sop==1'b1) begin
single_crc_cyc <= 1'b0; // default
if (rxdata[126]==1'b0) begin // No payload
if (ctrlrx_3dw==1'b1) begin
ctrlrx_cnt_len_dw <= 0; // 1DW ECRC, subtract 1 since ECRC is packed with descriptor.
single_crc_cyc <= 1'b1;
end
else
ctrlrx_cnt_len_dw <= 1;
end
else if (ctrlrx_3dw==1'b0)
ctrlrx_cnt_len_dw <= rxdata[105:96] + 1; // Add ECRC field.
else
ctrlrx_cnt_len_dw <= rxdata[105:96]; // Add ECRC field.
end
else if (rx_stream_valid0) begin
if (ctrlrx_cnt_len_dw>3)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-4;
else if (ctrlrx_cnt_len_dw>2)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-3;
else if (ctrlrx_cnt_len_dw>1)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-2;
else if (ctrlrx_cnt_len_dw>0)
ctrlrx_cnt_len_dw <= ctrlrx_cnt_len_dw-1;
end
end
// for internal monitoring
assign crc_32 = (rx_eop_crc_in==1'b0)?0:
(ctrlrx_cnt_len_dw_reg[1:0]==0)? rxdata_crc_in[127:96]:
(ctrlrx_cnt_len_dw_reg[1:0]==1)? rxdata_crc_in[95:64]:
(ctrlrx_cnt_len_dw_reg[1:0]==2)? rxdata_crc_in[63:32]:
rxdata_crc_in[31:0];
endmodule
|
/*
* Simple 8-bit FPGA softcore CPU.
* Copyright (C) 2015 P. Heinonen.
* Licensed under the MIT License. For more details, read the LICENSE file.
*
* compiler: Icarus Verilog 0.9.7
* Timing analysis with GTKWave
*
*/
module waterbear(
input clk,
input rst,
output[7:0] PC);
// Control Unit stages
// Classic RISC type pipeline without MEM stage
parameter IF=2'b00;
parameter ID=2'b01;
parameter EX=2'b10;
parameter WB=2'b11;
// index for memcopy in store step
integer i;
// Control Unit registers
reg[1:0] control_unit_current;
reg[1:0] control_unit_next;
// mnemonics of opcodes
parameter LDR = 4'b001; // load
parameter STR = 4'b010; // store
parameter ADD = 4'b011; // add
parameter SUB = 4'b100; // substract
parameter EQU = 4'b101; // compare equal
parameter JMP = 4'b110; // jump
parameter HLT = 4'b111; // halt
// memory structure
reg[15:0] MEM[0:255]; // Main Memory - 16 bit wide 256 memory cells
reg[5:0] WORKMEM[0:127]; // ALU intermediate register
reg[5:0] DESTMEM[0:127]; // destination register
reg[5:0] R1; // accumulator
reg[7:0] PC; // program counter
reg[7:0] MAR; // Memory Address register
reg[15:0] MDR; // Memory Data/Buffer Register
reg[15:0] CIR; // Current Instruction Register
// instruction set structure
reg[4:0] reserved = 5'b00000;
reg[3:0] op_code = 0;
reg numbit = 0;
reg[5:0] operand = 0;
/*
RAM memory layout contains 256 memorycells which are 16-bit wide
to store instruction set.
+-----5----+---4----+---1----+---6-----+
INSTRUCTION SET | | | | |
STRUCTURE | RESERVED | OPCODE | NUMBIT | OPERAND |
| | | | |
+----------+--------+--------+---------+
*/
// initial cpu bootup
initial begin
// initialize memory and registers
init_regs();
// memory initialization for testbench
// Sample program calculates equation: x=5+7;
/*
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //Load value 5 into R1, mcode: 00000 001 1 000010
MEM[1] = {reserved, STR, 1'b0, 6'b001101}; //Store value from R1 in memory addr 13
MEM[2] = {reserved, LDR, 1'b1, 6'b000111}; //Load value 7 into R1
MEM[3] = {reserved, STR, 1'b0, 6'b001110}; //Store value from R1 in memory addr 14
MEM[4] = {reserved, LDR, 1'b0, 6'b001101}; //Load value from memory addr 13 into R1
MEM[5] = {reserved, ADD, 1'b0, 6'b001110}; //Add value from memory addr 14 to R1
MEM[6] = {reserved, STR, 1'b0, 6'b000010}; //Store value from R1 into memory addr 15
MEM[7] = {reserved, HLT, 1'b0, 6'b000000}; //Stop execution
*/
// Sample program: Counter to count from 0 to some user coded limit, here 5.
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //set count value to 5
MEM[1] = {reserved, STR, 1'b0, 6'b001111}; //store count value to address 15
MEM[2] = {reserved, LDR, 1'b1, 6'b000000}; //initialize count to zero
MEM[3] = {reserved, EQU, 1'b0, 6'b001111}; //check if count is complete, if yes skip next
MEM[4] = {reserved, JMP, 1'b1, 6'b000110}; //set PC to 6
MEM[5] = {reserved, HLT, 1'b0, 6'b000000}; //stop program
MEM[6] = {reserved, ADD, 1'b1, 6'b000001}; //increment counter in accumulator
MEM[7] = {reserved, JMP, 1'b1, 6'b000011}; //set PC to 3
end
// clock cycles
always @ (clk, rst) begin
if(rst) begin
init_regs();
end
else begin
// Control Unit Finite state machine
case(control_unit_current)
IF: begin
MAR = PC;
PC = PC +1;
MDR = MEM[MAR];
CIR = MDR;
control_unit_next=ID;
end
ID: begin
control_unit_next=EX;
InstructionDecoder(CIR, op_code, numbit, operand);
end
EX: begin
// execute ALU instructions
case(op_code)
LDR: begin
if(numbit==1) begin
R1 = operand; // direct assign
end else begin
R1 = WORKMEM[operand]; // assign from address
end
control_unit_next=WB;
end
STR: begin
WORKMEM[operand] = R1;
control_unit_next=WB;
end
ADD: begin
if(numbit==1) begin
R1=R1+operand;
end else begin
R1=R1+WORKMEM[operand];
end
control_unit_next=WB;
end
JMP : begin
PC=operand;
control_unit_next=WB;
end
EQU: begin
if(R1 == WORKMEM[operand]) begin
PC=PC+1;
end
control_unit_next=WB;
end
HLT: begin
control_unit_next=EX; // continue loop
end
default: begin end
endcase
end // end of execute ALU instructions
WB: begin
// Loop is synthesizable:
// http://www.lcdm-eng.com/papers/snug13_SNUG-SV-2013_Synthesizable-SystemVerilog_paper.pdf
for (i=0; i<127; i=i+1 ) begin
DESTMEM[i] <= WORKMEM[i];
end
control_unit_next=IF;
end
default: begin end
endcase
control_unit_current=control_unit_next;
end
end
// task to initialize registers and memory
task init_regs;
begin
PC = 0;
R1 = 0;
MDR = 0;
MAR = 0;
CIR = 0;
//WORKMEM = 0; //{0,128'h80};
//DESTMEM = 0; //{0,128'h80};
control_unit_current = IF;
numbit = 0;
operand = 0;
op_code = 0;
reserved = 0;
end
endtask
// in execute, Control Unit
task InstructionDecoder;
input[15:0] CIR;
output[3:0] op_code;
output numbit;
output[5:0] operand;
begin
op_code= CIR[10:7];
numbit=CIR[6:6];
operand=CIR[5:0];
end
endtask
endmodule
// For the test 4 core test
module multicore(
input clk,
input rst,
output[7:0] PC);
waterbear core1(clk, reset, PC);
waterbear core2(clk, reset, PC);
waterbear core3(clk, reset, PC);
waterbear core4(clk, reset, PC);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [63:0] d;
reg [31:0] c;
wire [31:0] q = crc (d, c);
reg [31:0] q_r;
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
q_r <= q;
c <= q;
d <= {d[62:0], ^d[63:48]};
//$write("%d crc(%x,%x)=%x\n", cyc, d, c, q);
if (cyc==1) begin
// Assign inputs randomly
q_r <= 32'h12345678;
c <= 32'h12345678;
d <= 64'hffffffff_ffffffff;
end
if (cyc==2) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==3) begin
d <= 64'hffffffff_ffffffff;
end
if (cyc==4) begin
d <= 64'h50183721_81a04b1a;
end
if (cyc==5) begin
end
if (cyc==9) begin
if (q !== 32'h38295e96) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
function [31:0] crc;
input [63:0] di;
input [31:0] ci;
reg [63:0] drev;
begin
drev = reverse(di);
crc = newcrc(drev, ci);
end
endfunction
function [63:0] reverse;
input [63:0] di;
integer i;
begin
reverse = 64'b0;
for (i=0; i<64; i=i+1) reverse[i] = di[63-i];
end
endfunction
function [31:0] newcrc;
input [63:0] D;
input [31:0] C;
reg [31:0] N;
reg [31:0] DT;
begin
N = 32'b0;
// Note this isn't a real CRC code; it's been munged for privacy
N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0]
^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1];
N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0]
^C[30]^C[27]^C[26]^C[20]^C[16]^C[14]^C[13]^C[11]^C[10]^C[8]^C[5]^C[0];
N[2] = D[63]^D[62]^D[61]^D[60]^D[55]^D[54]^D[52]^D[44]^D[43]^D[42]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[23]^D[22]^D[18]^D[16]^D[15]^D[13]^D[12]^D[11]
^C[31]^C[30]^C[27]^C[22]^C[21]^C[18]^C[15]^C[12]^C[11]^C[10]^C[7];
N[3] = D[62]^D[54]^D[50]^D[47]^D[46]^D[38]^D[36]^D[35]^D[34]^D[33]^D[32]^D[30]^D[27]^D[25]^D[21]^D[20]^D[19]^D[17]^D[15]^D[11]^D[8]^D[5]^D[3]^D[1]^D[0]
^C[28]^C[25]^C[24]^C[13]^C[11]^C[9]^C[8]^C[7]^C[3]^C[1];
N[4] = D[57]^D[54]^D[53]^D[52]^D[45]^D[44]^D[43]^D[39]^D[37]^D[34]^D[33]^D[32]^D[31]^D[28]^D[24]^D[23]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[1]^D[0]
^C[30]^C[24]^C[20]^C[16]^C[14]^C[11]^C[8]^C[7]^C[6]^C[5]^C[2];
N[5] = D[58]^D[57]^D[50]^D[49]^D[48]^D[47]^D[43]^D[39]^D[29]^D[26]^D[23]^D[22]^D[20]^D[18]^D[14]^D[10]^D[9]^D[6]^D[5]^D[4]^D[1]
^C[27]^C[24]^C[20]^C[19]^C[18]^C[14]^C[13]^C[12]^C[11]^C[8]^C[7]^C[1];
N[6] = D[63]^D[62]^D[61]^D[57]^D[51]^D[50]^D[47]^D[38]^D[37]^D[34]^D[30]^D[28]^D[27]^D[25]^D[21]^D[16]^D[15]^D[10]^D[9]^D[6]^D[5]^D[2]^D[1]
^C[31]^C[27]^C[25]^C[16]^C[13]^C[9]^C[8]^C[7]^C[0];
N[7] = ^D[62]^D[61]^D[59]^D[54]^D[52]^D[51]^D[49]^D[46]^D[45]^D[42]^D[41]^D[38]^D[35]^D[29]^D[26]^D[24]^D[15]^D[12]^D[11]^D[9]^D[2]^D[0]
^C[28]^C[27]^C[26]^C[20]^C[19]^C[18]^C[15]^C[12]^C[7]^C[4];
N[8] = D[62]^D[61]^D[60]^D[59]^D[52]^D[50]^D[48]^D[47]^D[46]^D[45]^D[44]^D[42]^D[41]^D[40]^D[30]^D[24]^D[23]^D[22]^D[19]^D[17]^D[11]^D[10]^D[7]^D[6]^D[2]
^C[31]^C[29]^C[27]^C[22]^C[21]^C[19]^C[17]^C[11]^C[9]^C[7]^C[6];
N[9] = D[62]^D[59]^D[58]^D[57]^D[54]^D[51]^D[50]^D[43]^D[41]^D[39]^D[28]^D[25]^D[24]^D[23]^D[22]^D[21]^D[18]^D[16]^D[15]^D[7]
^C[30]^C[29]^C[27]^C[25]^C[23]^C[22]^C[13]^C[12]^C[7]^C[6]^C[5]^C[1];
N[10] = D[61]^D[60]^D[58]^D[56]^D[54]^D[53]^D[51]^D[48]^D[46]^D[43]^D[42]^D[38]^D[37]^D[35]^D[33]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[10]^D[8]^D[6]^D[1]
^C[31]^C[30]^C[26]^C[25]^C[24]^C[21]^C[16]^C[12]^C[3]^C[2];
N[11] = D[59]^D[57]^D[56]^D[50]^D[49]^D[48]^D[47]^D[46]^D[45]^D[42]^D[41]^D[40]^D[33]^D[32]^D[30]^D[25]^D[21]^D[15]^D[14]^D[13]^D[12]^D[11]^D[5]^D[1]
^C[27]^C[25]^C[24]^C[21]^C[16]^C[12]^C[7]^C[3]^C[2]^C[1];
N[12] = D[62]^D[61]^D[59]^D[58]^D[56]^D[55]^D[53]^D[48]^D[47]^D[44]^D[43]^D[35]^D[31]^D[30]^D[28]^D[24]^D[23]^D[21]^D[14]^D[5]^D[2]
^C[28]^C[26]^C[25]^C[23]^C[22]^C[18]^C[16]^C[15]^C[6];
N[13] = D[63]^D[60]^D[58]^D[57]^D[55]^D[54]^D[53]^D[51]^D[47]^D[45]^D[42]^D[41]^D[38]^D[28]^D[26]^D[25]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[12]^D[11]
^C[29]^C[28]^C[25]^C[22]^C[19]^C[17]^C[16]^C[15]^C[14]^C[12]^C[10]^C[9];
N[14] = D[58]^D[56]^D[55]^D[52]^D[47]^D[43]^D[41]^D[40]^D[39]^D[38]^D[30]^D[26]^D[25]^D[22]^D[19]^D[17]^D[13]^D[11]^D[10]^D[9]^D[8]^D[3]^D[2]^D[0]
^C[31]^C[28]^C[20]^C[18]^C[17]^C[16]^C[15]^C[13]^C[11]^C[4]^C[2]^C[1];
N[15] = D[63]^D[62]^D[61]^D[59]^D[58]^D[48]^D[47]^D[43]^D[42]^D[35]^D[28]^D[26]^D[25]^D[24]^D[23]^D[22]^D[21]^D[20]^D[19]^D[17]^D[11]^D[7]^D[2]
^C[30]^C[29]^C[27]^C[24]^C[20]^C[17]^C[16]^C[15]^C[11]^C[9]^C[5];
N[16] = D[60]^D[57]^D[49]^D[46]^D[45]^D[43]^D[39]^D[36]^D[32]^D[30]^D[29]^D[28]^D[27]^D[26]^D[23]^D[20]^D[19]^D[17]^D[11]^D[8]^D[5]^D[1]
^C[28]^C[26]^C[23]^C[22]^C[18]^C[16]^C[13]^C[12]^C[10]^C[9]^C[6];
N[17] = D[63]^D[62]^D[61]^D[60]^D[58]^D[54]^D[53]^D[51]^D[48]^D[42]^D[41]^D[37]^D[36]^D[34]^D[28]^D[27]^D[26]^D[24]^D[13]^D[12]^D[9]^D[7]^D[4]^D[0]
^C[31]^C[30]^C[27]^C[23]^C[20]^C[17]^C[14]^C[9]^C[6]^C[4]^C[3]^C[0];
N[18] = D[63]^D[61]^D[59]^D[56]^D[52]^D[50]^D[47]^D[42]^D[37]^D[35]^D[34]^D[31]^D[30]^D[29]^D[22]^D[19]^D[17]^D[16]^D[11]^D[9]^D[8]^D[7]
^C[26]^C[22]^C[20]^C[19]^C[16]^C[11]^C[8]^C[6]^C[5]^C[0];
N[19] = D[62]^D[60]^D[52]^D[49]^D[44]^D[43]^D[42]^D[37]^D[33]^D[32]^D[29]^D[26]^D[19]^D[17]^D[16]^D[12]^D[10]^D[7]^D[6]^D[4]^D[3]^D[2]
^C[30]^C[29]^C[26]^C[25]^C[22]^C[19]^C[14]^C[7]^C[6]^C[5]^C[2]^C[0];
N[20] = D[63]^D[58]^D[54]^D[48]^D[47]^D[40]^D[39]^D[35]^D[34]^D[32]^D[31]^D[28]^D[27]^D[25]^D[18]^D[12]^D[9]^D[7]^D[5]^D[4]^D[3]^D[2]^D[1]
^C[31]^C[29]^C[28]^C[25]^C[19]^C[18]^C[17]^C[15]^C[10]^C[9]^C[6]^C[4];
N[21] = D[61]^D[59]^D[57]^D[56]^D[53]^D[48]^D[44]^D[43]^D[41]^D[35]^D[29]^D[26]^D[25]^D[20]^D[18]^D[17]^D[16]^D[12]^D[9]^D[6]^D[5]^D[3]^D[1]
^C[30]^C[27]^C[24]^C[23]^C[22]^C[21]^C[20]^C[13]^C[9]^C[3]^C[2];
N[22] = D[63]^D[62]^D[60]^D[57]^D[53]^D[51]^D[45]^D[44]^D[42]^D[34]^D[33]^D[27]^D[20]^D[19]^D[18]^D[15]^D[10]^D[9]^D[8]^D[4]^D[3]
^C[24]^C[23]^C[18]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[9]^C[6]^C[5];
N[23] = D[58]^D[56]^D[54]^D[51]^D[47]^D[43]^D[42]^D[40]^D[37]^D[36]^D[33]^D[25]^D[23]^D[20]^D[18]^D[16]^D[15]^D[12]^D[10]^D[8]^D[7]^D[5]^D[3]
^C[31]^C[27]^C[26]^C[23]^C[21]^C[18]^C[15]^C[11]^C[10]^C[8]^C[7]^C[1];
N[24] = D[60]^D[59]^D[52]^D[50]^D[48]^D[44]^D[39]^D[36]^D[35]^D[31]^D[30]^D[28]^D[27]^D[23]^D[22]^D[21]^D[19]^D[14]^D[13]^D[12]^D[9]^D[4]^D[1]^D[0]
^C[27]^C[25]^C[23]^C[21]^C[17]^C[11]^C[10]^C[4]^C[0];
N[25] = D[61]^D[60]^D[56]^D[54]^D[51]^D[46]^D[43]^D[41]^D[40]^D[38]^D[37]^D[36]^D[29]^D[28]^D[27]^D[22]^D[17]^D[15]^D[10]^D[7]^D[4]^D[2]
^C[29]^C[28]^C[26]^C[23]^C[18]^C[14]^C[13]^C[12]^C[11]^C[9]^C[8]^C[6];
N[26] = D[63]^D[62]^D[58]^D[55]^D[54]^D[52]^D[50]^D[39]^D[37]^D[36]^D[35]^D[33]^D[31]^D[29]^D[27]^D[18]^D[14]^D[10]^D[3]^D[2]^D[0]
^C[31]^C[27]^C[26]^C[25]^C[24]^C[21]^C[13]^C[12]^C[10]^C[1];
N[27] = D[62]^D[60]^D[58]^D[56]^D[55]^D[54]^D[51]^D[44]^D[41]^D[36]^D[34]^D[32]^D[31]^D[29]^D[28]^D[27]^D[23]^D[17]^D[12]^D[11]^D[8]^D[6]^D[4]^D[2]
^C[31]^C[30]^C[28]^C[27]^C[23]^C[19]^C[17]^C[16]^C[14]^C[12]^C[11]^C[10]^C[3];
N[28] = D[57]^D[54]^D[53]^D[51]^D[50]^D[48]^D[40]^D[38]^D[34]^D[33]^D[31]^D[30]^D[29]^D[27]^D[23]^D[21]^D[14]^D[9]^D[7]^D[6]^D[5]^D[4]^D[0]
^C[31]^C[30]^C[26]^C[24]^C[15]^C[14]^C[13]^C[7]^C[6]^C[4]^C[3]^C[0];
N[29] = D[62]^D[60]^D[55]^D[46]^D[45]^D[44]^D[43]^D[41]^D[40]^D[35]^D[33]^D[32]^D[30]^D[28]^D[25]^D[23]^D[22]^D[13]^D[8]^D[7]^D[6]^D[5]^D[4]^D[3]^D[1]^D[0]
^C[31]^C[28]^C[27]^C[18]^C[11]^C[8]^C[6]^C[4]^C[2]^C[1]^C[0];
N[30] = D[63]^D[62]^D[59]^D[58]^D[55]^D[52]^D[47]^D[44]^D[36]^D[35]^D[34]^D[31]^D[29]^D[22]^D[21]^D[20]^D[19]^D[15]^D[14]^D[10]^D[6]^D[3]^D[2]^D[0]
^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0];
N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0]
^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2];
newcrc = N;
end
endfunction
endmodule
|
`include "config.v"
module A2S_controller(
// system reset
rst,
// stream clk
Sclk,
// system sync(reset)
sync,
// Buffer read
Oen,
Oaddr,
obase,
osize,
oacnt,
obcnt,
// AXI Bus Signal
AXI_clk,
AXI_rst_n,
AXI_araddr,
AXI_arvalid,
AXI_arready,
AXI_rready,
AXI_rvalid,
AXI_rlast,
// Buffer write
a2s_addr,
a2s_en
);
parameter s0 = 3'd0;
parameter s1 = 3'd1;
parameter s2 = 3'd2;
parameter s3 = 3'd3;
input rst,Sclk,sync,Oen;
output[4:0] Oaddr;
input AXI_clk;
input AXI_rst_n;
output reg[31:0] AXI_araddr;
input AXI_arready,AXI_rvalid;
output reg AXI_rready,AXI_arvalid;
input AXI_rlast;
output reg[4:0] a2s_addr;
output a2s_en;
reg[21:0] cnt;
reg[31:0] bcnt;
reg start;
wire axi_start;
reg [2:0]state;
reg [31:0]AXI_araddr_reg;
input [31:0]obase;
input [23:6]osize;
output [23:6]oacnt;
output [31:0]obcnt;
assign Oaddr = cnt[4:0];
assign oacnt[23:6] = cnt[21:4];
assign obcnt = bcnt;
edgesync #(.e("pos")) start_sync
( .clk(AXI_clk)
, .async(start)
, .sync(axi_start)
);
always @(posedge Sclk or posedge rst)
begin
if( rst==1'b1 ) begin
start <= 1'b0;
cnt <= 22'h0;
bcnt <= 32'h0;
end
else begin
if ( sync==1'b1 )
begin
start <= 1'b0;
cnt <= 22'h0;
bcnt <= 32'h0;
end
else if( Oen==1'b1 )
begin
if( cnt[3:0]==4'hf )
begin
AXI_araddr_reg[5:0] <= 6'b000000;
AXI_araddr_reg[31:6] <= obase[31:6] + cnt[21:4];
cnt[3:0] <= 4'h0;
if( cnt[21:4]==(osize[23:6]-1'b1) )
begin
cnt[21:4] <= 18'h0;
bcnt <= bcnt + 32'h1;
end
else cnt[21:4] <= cnt[21:4]+18'h1;
end
else cnt[3:0] <= cnt[3:0] + 4'h1;
end
if( Oen==1'b1 && cnt[3:0]==4'hf && start==1'b0 ) start <= 1'b1;
else start <= 1'b0;
end
end
assign a2s_en = AXI_rvalid & AXI_rready;
always @(posedge AXI_clk)
begin
if( !AXI_rst_n ) begin
a2s_addr <= 5'b00000;
AXI_arvalid <= 1'b0;
AXI_rready <= 1'b0;
AXI_araddr <= obase;
state <= s0;
end
else begin
if( axi_start==1'b1 ) begin
state <= s1;
AXI_araddr <= AXI_araddr_reg;
end
else begin
case( state )
s0 : begin
AXI_rready <= AXI_rvalid;
end
s1 : begin
AXI_arvalid <= 1'b1;
if( AXI_arready==1'b1 && AXI_arvalid==1'b1 ) begin
state <= s2;
AXI_arvalid <= 1'b0;
a2s_addr[4] <= AXI_araddr[6];
a2s_addr[3:0] <= 4'h0;
AXI_rready <= 1'b1;
end
end
s2 : begin
if( a2s_en==1'b1 ) begin
a2s_addr[3:0] <= a2s_addr[3:0] + 1'b1;
if( AXI_rlast==1'b1 ) begin
state <= s0;
AXI_rready <= 1'b0;
end
end
end
endcase
end
end
end
endmodule
|
module datapath ( input CLK,
input CLK_MEM,
input RESET,
input RUN,
//Controller iface
input WRITE_REG, //write to register file
input WRITE_MEM, //write data memory
input ALUORMEM_WR, //write regfile from alu or from memory
input MEM_PARTIAL, //memory byte- or halfword access
input [1:0] MEM_OPTYPE, //mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
input MULTIPLY, //do multiplication and write hi&lo
input BRANCH_E, //branch equal
input BRANCH_NE, //branch not equal
input BRANCH_LEZ, //branch less than or equal zero
input BRANCH_LTZ, //branch less than zero
input BRANCH_GEZ, //branch greater than or equal zero
input BRANCH_GTZ, //branch greater than zero
input JUMP, //j-type jump
input JUMP_R, //jr, jalr
input ALU_SRC_B, //ALU Operand B 0 - reg_2, 1 - immediate
input [6:0] ALU_OP, //ALU Operation select
input [1:0] REG_DST, //write destination in regfile (0 - rt, 1 - rd, 1X -- 31)
input [1:0] IMMED_EXT, //immediate extension type (sign, zero, swap)
input [1:0] MFCOP_SEL, //move from cop sel. 0 - from alu, 1 - from HI, 2 - from LO, 3 -- from C0
output [5:0] OPCODE, //instruction opcode
output [5:0] FCODE, //instruction fcode
output [4:0] RT, //instruction RT field
//External inst memory iface
output [29:0] inst_mem_addr,
input [31:0] inst_mem_data,
//External data memory iface
output data_mem_we,
output [ 3:0] data_mem_be,
output [29:0] data_mem_addr,
output [31:0] data_mem_wdata,
input [31:0] data_mem_rdata );
//------------------------WIRE DEFINITIONS-----------------------------------//
//FETCH:
wire [31:0] branch_target, jump_target, jumpr_target, next_pc_reg, pc, pc_plus_4;
//DECODE:
wire [31:0] inst_d, pc_plus_4_d, rd1, rd2, regfile_wdata, immed_extend_d, immed_extend_sl2_d,
rd1_fwd, rd2_fwd;
wire [4:0] reg_dst_addr_w, rs_d, rt_d;
wire link_d, do_branch, stall, lw_stall, br_stall;
//EXECUTE:
wire [31:0] pc_plus_4_e, immed_extend_e, src_a_e, src_b_e,
src_a_fwd_e, src_b_fwd_e, src_a, src_b, hi_e,
lo_e, aluout_e, aluout_mux_e;
wire [6:0] alu_op_e;
wire [4:0] reg_dst_addr_e, rs_e, rt_e, rd_e, shamt_e;
wire [1:0] reg_dst_e, mfcop_sel_e, mem_optype_e;
wire write_reg_e, write_mem_e, aluormem_e, multiply_e,
alu_src_b_e, link_e, alu_zero, mem_partial_e;
//MEM:
wire [31:0] aluout_m, src_b_m, mem_reordered_m;
wire [4:0] reg_dst_addr_m;
wire [1:0] mem_optype_m;
wire write_reg_m, write_mem_m, aluormem_m, mem_partial_m;
//WRITEBACK:
wire [31:0] aluout_w, mem_reordered_w;
wire write_reg_w, aluormem_w;
//------------------------FETCH STAGE----------------------------------------//
assign pc_plus_4 = pc + 4;
assign stall = lw_stall | br_stall;
assign inst_mem_addr = pc[31:2];
wire [1:0] next_pc_select = JUMP ? 2'b11 :
JUMP_R ? 2'b10 :
do_branch ? 2'b01 :
2'b00 ;
mux4 pc_src_mux( next_pc_select,
pc_plus_4, //00: pc = pc + 4
branch_target, //01: conditional branch
jumpr_target, //10: from register file
jump_target, //11: from j-type instruction
next_pc_reg );
ffd pc_reg(CLK, RESET, ~stall & RUN, next_pc_reg, pc );
ffd #(64) pipe_reg_D(CLK, RESET, ~stall & RUN,
{ inst_mem_data,
pc_plus_4 },
{ inst_d,
pc_plus_4_d });
//---------------------------------------------------------------------------//
//------------------------DECODE STAGE---------------------------------------//
assign OPCODE = inst_d[31:26];
assign FCODE = inst_d [5:0];
assign RT = inst_d[20:16];
assign rs_d = inst_d[25:21];
assign rt_d = inst_d[20:16];
regfile rf_unit(.CLK (CLK_MEM ),
.WE (write_reg_w ),
.RD_ADDR_1 (rs_d ), //in_rd_addr
.RD_ADDR_2 (rt_d ), //in_rd_addr
.WR_ADDR_3 (reg_dst_addr_w ), //in_wr_addr
.W_DATA (regfile_wdata ), //in
.R_DATA_1 (rd1 ), //out
.R_DATA_2 (rd2 )); //out
//------IMMEDIATE EXTENSION--------
immed_extend immed_ext_unit(IMMED_EXT, inst_d[15:0], immed_extend_d);
//------BRANCH LOGIC-------
sl2 shl2_unit(immed_extend_d, immed_extend_sl2_d);
wire fwd_br_a = (rs_d != 0) && (rs_d == reg_dst_addr_m) && write_reg_m;
wire fwd_br_b = (rt_d != 0) && (rt_d == reg_dst_addr_m) && write_reg_m;
mux2 fwd_br_a_mux(fwd_br_a, rd1, //0 -- no forwarding
aluout_m, //1 -- forward from MEM
rd1_fwd );
mux2 fwd_br_b_mux(fwd_br_b, rd2, //0 -- no forwarding
aluout_m, //1 -- forward from MEM
rd2_fwd );
wire br_inst = BRANCH_E | BRANCH_NE | BRANCH_LEZ |
BRANCH_LTZ | BRANCH_GEZ | BRANCH_GTZ |
JUMP | JUMP_R;
assign br_stall = (rs_d != 0) & br_inst &
((write_reg_e & ((reg_dst_addr_e == rs_d) |
(reg_dst_addr_e == rt_d) )) |
(aluormem_m & ((reg_dst_addr_m == rs_d) | //lw
(reg_dst_addr_m == rt_d) )));
assign branch_target = immed_extend_sl2_d + pc_plus_4_d;
assign jump_target = {pc_plus_4_d[31:28], inst_d[25:0], 2'b00};
assign jumpr_target = rd1_fwd;
wire regs_equal = (rd1_fwd == rd2_fwd);
wire reg_zero = (rd1_fwd == 0);
assign do_branch = ( (BRANCH_E & regs_equal) |
(BRANCH_NE & ~regs_equal) |
(BRANCH_LEZ & ( rd1_fwd[31] | reg_zero)) | // <= 0
(BRANCH_LTZ & rd1_fwd[31] ) | // < 0
(BRANCH_GEZ & ~rd1_fwd[31] ) | // >= 0
(BRANCH_GTZ & (~rd1_fwd[31] & ~reg_zero)) ); // > 0
assign link_d = JUMP | JUMP_R | BRANCH_GEZ | BRANCH_LTZ;
ffd #(168) pipe_reg_E(CLK, RESET | stall, RUN,
{ WRITE_REG, // 1/ write to register file
WRITE_MEM, // 1/ write data memory
MEM_PARTIAL, // 1/ memory byte- or halfword access
MEM_OPTYPE, // 2/ mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
ALUORMEM_WR, // 1/ write regfile from alu or from memory
MULTIPLY, // 1/ do multiplication and write hi&lo
link_d, // 1/ link
ALU_SRC_B, // 1/ ALU Operand B 0 - reg_2, 1 - immediate
ALU_OP, // 7/ ALU Operation select
REG_DST, // 2/ write destination in regfile (0 - rt, 1 - rd)
MFCOP_SEL, // 2/ mfrom coprocessor selector
rd1, //32/ regfile_out_1
rd2, //32/ regfile_out_2
rs_d, // 5/ RS
rt_d, // 5/ RT
inst_d[15:11], // 5/ RD
inst_d[10:06], // 5/ SHAMT
immed_extend_d, //32/ immediate
pc_plus_4_d }, //32/ pc plus 4
{ write_reg_e, // 1/ write to register file
write_mem_e, // 1/ write data memory
mem_partial_e, // 1/ memory byte- or halfword access
mem_optype_e, // 2/ mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
aluormem_e, // 1/ write regfile from alu or from memory
multiply_e, // 1/ do multiplication and write hi&lo
link_e, // 1/ link
alu_src_b_e, // 1/ ALU Operand B 0 - reg_2, 1 - immediate
alu_op_e, // 7/ ALU Operation select
reg_dst_e, // 2/ write destination in regfile (0 - rt, 1 - rd)
mfcop_sel_e, // 2/ mfrom coprocessor selector
src_a_e,
src_b_e,
rs_e,
rt_e,
rd_e,
shamt_e,
immed_extend_e,
pc_plus_4_e });
//---------------------------------------------------------------------------//
//------------------------EXECUTE STAGE--------------------------------------//
mux4 #(5) regfile_wr_addr_mux( reg_dst_e,
rt_e,
rd_e,
5'd31, //ra
5'd31, //ra
reg_dst_addr_e);
//forwarding mux's
wire [1:0] fwd_a = ((rs_e != 0) && (rs_e == reg_dst_addr_m) && write_reg_m) ? 2'b10 :
((rs_e != 0) && (rs_e == reg_dst_addr_w) && write_reg_w) ? 2'b01 :
2'b00;
wire [1:0] fwd_b = ((rt_e != 0) && (rt_e == reg_dst_addr_m) && write_reg_m) ? 2'b10 :
((rt_e != 0) && (rt_e == reg_dst_addr_w) && write_reg_w) ? 2'b01 :
2'b00;
//lw stall logic
assign lw_stall = aluormem_e & ((rs_d == rt_e) |
(rt_d == rt_e) );
mux4 fwd_src_a(fwd_a, src_a_e, //00 -- no forwarding
regfile_wdata, //01 -- forward from WB
aluout_m, //10 -- forward from MEM
src_a_e, //11 -- no forwarding
src_a_fwd_e );
mux4 fwd_src_b(fwd_b, src_b_e, //00 -- no forwarding
regfile_wdata, //01 -- forward from WB
aluout_m, //10 -- forward from MEM
src_b_e, //11 -- no forwarding
src_b_fwd_e );
//final alu muxes
mux2 alu_src_a_mux( link_e,
src_a_fwd_e,
pc_plus_4_e,
src_a );
mux4 alu_src_b_mux( {link_e, alu_src_b_e},
src_b_fwd_e, //00: forwarded src b
immed_extend_e, //01: immediate
32'd4, //10: 4 for ret_addr calculation
32'd4, //11: 4 for ret_addr calculation
src_b );
alu alu(alu_op_e, src_a, src_b, shamt_e, aluout_e, alu_zero);
wire [63:0] product_e = src_a_fwd_e * src_b_fwd_e;
ffd #( 64) hi_lo_reg(CLK, RESET, multiply_e & RUN, product_e, {hi_e, lo_e});
mux4 aluout_mux( mfcop_sel_e,
aluout_e,
hi_e, //MFHI
lo_e, //MFLO
32'hXXXXXXXX, //MFC0
aluout_mux_e );
ffd #( 75) pipe_reg_M(CLK, RESET, RUN,
{ write_reg_e, // 1/ write to register file
write_mem_e, // 1/ write data memory
mem_partial_e, // 1/ memory byte- or halfword access
mem_optype_e, // 2/ mem op: 00-ubyte, 01-uhalf, 10-sb, 11-sh
aluormem_e, // 1/ write regfile from alu or from memory
aluout_mux_e, //32/ ALU result
src_b_fwd_e, //32/ regfile data B
reg_dst_addr_e }, // 5/ destination reg addr
{ write_reg_m,
write_mem_m,
mem_partial_m,
mem_optype_m,
aluormem_m,
aluout_m,
src_b_m,
reg_dst_addr_m });
//---------------------------------------------------------------------------//
//------------------------MEMORY STAGE---------------------------------------//
assign data_mem_we = write_mem_m;
assign data_mem_addr = aluout_m[31:2];
store_reorder st_reorder_unit( .LO_ADDR ( aluout_m[1:0] ),
.DATA_IN ( src_b_m ),
.PARTIAL ( mem_partial_m ),
.OP_TYPE ( mem_optype_m ),
.BYTE_EN ( data_mem_be ),
.DATA_OUT( data_mem_wdata ));
load_reorder ld_reorder_unit( .LO_ADDR ( aluout_m[1:0] ),
.DATA_IN ( data_mem_rdata ),
.PARTIAL ( mem_partial_m ),
.OP_TYPE ( mem_optype_m ),
.DATA_OUT( mem_reordered_m));
ffd #( 71) pipe_reg_W(CLK, RESET, RUN,
{ write_reg_m, // 1/ write to register file
aluormem_m, // 1/ write regfile from alu or from memory
aluout_m, //32/ alu result
mem_reordered_m, //32/ memory data
reg_dst_addr_m}, // 5/ destination register
{ write_reg_w, // 1/ write to register file
aluormem_w, // 1/ write regfile from alu or from memory
aluout_w, //32/ alu result
mem_reordered_w, //32/ memory data
reg_dst_addr_w} ); // 5/ destination register
//---------------------------------------------------------------------------//
//-----------------------WRITEBACK STAGE-------------------------------------//
mux2 regfile_wr_data_mux( aluormem_w,
aluout_w, //0: ALU out
mem_reordered_w, //1: MEM out
regfile_wdata);
//---------------------------------------------------------------------------//
endmodule
|
/*
*
* Copyright (c) 2011-2012 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// Top-level module that uses the unoptimized mining core and Virtual Wire
// external interface.
`timescale 1ns/1ps
module fpgaminer_top (
input MAIN_CLK
);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 0 will completely
// unroll the calculations, resulting in 128 rounds and a large, but
// fast design.
//
// A setting of 1 will result in 64 rounds, with half the size and
// half the speed. 2 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
localparam LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
localparam LOOP_LOG2 = 0;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
hashing_pll # (
.INPUT_FREQUENCY (`MAIN_CLK_FREQUENCY),
.DIVIDE_BY (`MAIN_CLK_DIVIDE),
.MULTIPLY_BY (`MAIN_CLK_MULTIPLY)
) pll_blk (
.rx_clk (MAIN_CLK),
.tx_hash_clk (hash_clk)
);
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
virtual_wire # (.OUTPUT_WIDTH(256), .INSTANCE_ID("STAT")) midstate_vw_blk (.clk (hash_clk), .rx_data (), .tx_data (midstate_vw));
virtual_wire # (.OUTPUT_WIDTH(256), .INSTANCE_ID("DAT2")) data2_vw_blk (.clk (hash_clk), .rx_data (), .tx_data (data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
virtual_wire # (.INPUT_WIDTH(32), .INSTANCE_ID("GNON")) golden_nonce_vw_blk (.clk (hash_clk), .rx_data (golden_nonce), .tx_data ());
virtual_wire # (.INPUT_WIDTH(32), .INSTANCE_ID("NONC")) nonce_vw_blk (.clk (hash_clk), .rx_data (nonce), .tx_data ());
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
assign cnt_next = (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next = feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvpwrvgnd (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVPWRVGND_PP_BLACKBOX_V
|
//Jun.30.2004 NOP_DISABLE BUG FIX
`include "define.h"
module pc_module(clock,sync_reset,pc_commandD1,PCC,imm,ea_reg_source,takenD2,
takenD3 ,branchQQ,jumpQ,NOP_Signal,control_state,IMMD1, PCCDD);
input clock;
input sync_reset;
input [31:0] ea_reg_source;
input [2:0] pc_commandD1;
input takenD2;
input [25:0] imm;
input [25:0] IMMD1;
`ifdef RAM4K
output [11:0] PCC;
`else
output [25:0] PCC;
`endif
input takenD3;
input branchQQ,jumpQ;
input NOP_Signal;
input [7:0] control_state;
reg [2:0] pc_commandD2,pc_commandD3;
`ifdef RAM4K
reg [11:0] PC;
reg [11:0] pcimm1D1,pcimm2D1;
reg [15:0] immD1;//
reg [11:0] pcimm1D2,pcimm2D2,pcimm2D3;
reg [11:0] save_pc;
wire [11:0] PCC;
output [11:0] PCCDD;
reg [11:0] PCCD,PCCDD;
`else
reg [25:0] PC;
reg [25:0] pcimm1D1,pcimm2D1;
reg [15:0] immD1;//
reg [25:0] pcimm1D2,pcimm2D2,pcimm2D3;
reg [25:0] save_pc;
wire [25:0] PCC;
output [25:0] PCCDD;
reg [25:0] PCCD,PCCDD;
`endif
reg takenD4;
reg branchQQQtakenD4;
//combination
always@(posedge clock) PCCD<=PCC;
always@(posedge clock) PCCDD<=PCCD;
always @(posedge clock) begin
pc_commandD2 <=pc_commandD1;
end
//
always @(posedge clock) begin
if (NOP_Signal) pc_commandD3<=3'b000;//Jun.30.2004
else pc_commandD3 <=pc_commandD2;
end
always @(IMMD1 ) begin
pcimm1D1={IMMD1,2'b00};//Jul.7.2004 {imm[23:0],2'b00};//+{PC[25:2],2'b00};
end
`ifdef RAM4K
always @(posedge clock) begin
pcimm2D1<={PC[11:2],2'b00};
end
`else
always @(posedge clock) begin
pcimm2D1<={PC[25:2],2'b00};
end
`endif
always @(posedge clock) begin
pcimm1D2<=pcimm1D1;
end
always @(posedge clock) begin
pcimm2D2<={{8 {immD1[15]}},immD1[15:0],2'b00}+pcimm2D1;//Jul.14.2004
end
always @(posedge clock) begin
pcimm2D3<=pcimm2D2;
end
always @(posedge clock) begin
immD1<=imm[15:0];//Jul.14.2004
end
always @(posedge clock) begin
if (control_state==8'b00_000_010) save_pc<=PCCDD;
end
always @(posedge clock) begin
if (sync_reset) PC<=26'h0_00_0000_0000;
else if (branchQQQtakenD4) PC<=pcimm2D3+4;//NOP
else if (jumpQ && !NOP_Signal) PC<=pcimm1D1+4;
else if (pc_commandD3==`PC_REG) PC<=ea_reg_source[25:0]+4;
else if (control_state[2:0]==3'b110) PC<=save_pc+4;//mul/div
else case(pc_commandD1)
`PC_INC: PC<=PC+4;
default: PC<=PC+4;
endcase
end
always @(posedge clock) begin
if (sync_reset) takenD4<=1'b0;
else takenD4<=takenD3;
end
always @(posedge clock) begin
if (sync_reset) branchQQQtakenD4<=1'b0;
else branchQQQtakenD4<=branchQQ && takenD3;
end
assign PCC= branchQQQtakenD4 ? pcimm2D3 :
jumpQ && !NOP_Signal ? pcimm1D1 :
pc_commandD3==`PC_REG ? ea_reg_source[25:0] :
control_state[2:0] ==3'b110 ? save_pc:PC;//Jun.27.2004
endmodule |
// DEFINES
`define BITS 32 // Bit width of the operands
module syn2(clock,
reset,
in1,
in2,
in3,
in4,
in5,
out_1,
out_2,
out_3,
out_4
);
// SIGNAL DECLARATIONS
input clock;
input reset;
input [`BITS-1:0] in1;
input [`BITS-1:0] in2;
input [`BITS-1:0] in3;
input [`BITS-1:0] in4;
input [`BITS-1:0] in5;
output [`BITS-1:0] out_1;
output [`BITS-1:0] out_2;
output [`BITS-1:0] out_3;
output [`BITS-1:0] out_4;
wire [`BITS-1:0] x1;
wire [`BITS-1:0] x2;
wire [`BITS-1:0] x3;
wire [`BITS-1:0] x4;
wire [`BITS-1:0] add1;
wire [`BITS-1:0] add2;
wire [`BITS-1:0] add3;
wire [`BITS-1:0] add4;
wire [`BITS-1:0] add5;
reg [`BITS-1:0] reg1;
reg [`BITS-1:0] reg2;
reg [`BITS-1:0] reg3;
reg [`BITS-1:0] reg4;
reg [`BITS-1:0] reg5;
reg [`BITS-1:0] reg6;
wire [`BITS-1:0] out_1;
wire [`BITS-1:0] out_2;
wire [`BITS-1:0] out_3;
wire [`BITS-1:0] out_4;
// ASSIGN STATEMENTS
//assign add1 = reg1 + in4;
wire [7:0] add1_control;
fpu_add add1_add
(
.clk(clock),
.opa(reg6),
.opb(in4),
.out(add1),
.control(add1_control)
);
//assign x1 = x3 * in1;
wire [7:0] x1_control;
fpu_mul x1_mul
(
.clk(clock),
.opa(x3),
.opb(in1),
.out(x1),
.control(x1_control)
);
//assign add2 = add5 + add1;
wire [7:0] add2_control;
fpu_add add2_add
(
.clk(clock),
.opa(add5),
.opb(add1),
.out(add2),
.control(add2_control)
);
//assign x2 = x1 * add2;
wire [7:0] x2_control;
fpu_mul x2_mul
(
.clk(clock),
.opa(x1),
.opb(add2),
.out(x2),
.control(x2_control)
);
//assign add3 = in1 + reg1;
wire [7:0] add3_control;
fpu_add add3_add
(
.clk(clock),
.opa(in1),
.opb(reg6),
.out(add3),
.control(add3_control)
);
//assign x3 = in3 * in1;
wire [7:0] x3_control;
fpu_mul x3_mul
(
.clk(clock),
.opa(in3),
.opb(in1),
.out(x3),
.control(x3_control)
);
//assign add4 = in5 + in3;
wire [7:0] add4_control;
fpu_add add4_add
(
.clk(clock),
.opa(in5),
.opb(in3),
.out(add4),
.control(add4_control)
);
//assign x4 = in5 * in4;
wire [7:0] x4_control;
fpu_mul x4_mul
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(x4),
.control(x4_control)
);
//assign add5 = in5 + in4;
wire [7:0] add5_control;
fpu_add add5_add
(
.clk(clock),
.opa(in5),
.opb(in4),
.out(add5),
.control(add5_control)
);
assign out_1 = x2;
assign out_2 = add3;
assign out_3 = add4;
assign out_4 = x4;
always @(posedge clock)
begin
reg1 <= in2;
reg2 <= reg1;
reg3 <= reg2;
reg4 <= reg3;
reg5 <= reg4;
reg6 <= reg5;
end
endmodule
module fpu_mul(
clk,
//rmode,
opa, opb, out,
control
/*
inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero
*/
);
input clk;
//input [1:0] rmode;
input [31:0] opa, opb;
output [31:0] out;
output [7:0] control;
/*
output inf, snan, qnan;
output ine;
output overflow, underflow;
output zero;
output div_by_zero;
*/
////////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [2:0] fpu_op;
reg zero;
reg [31:0] opa_r, opb_r; // Input operand registers
reg [31:0] out; // Output register
reg div_by_zero; // Divide by zero output register
wire signa, signb; // alias to opX sign
wire sign_fasu; // sign output
wire [26:0] fracta, fractb; // Fraction Outputs from EQU block
wire [7:0] exp_fasu; // Exponent output from EQU block
reg [7:0] exp_r; // Exponent output (registerd)
wire [26:0] fract_out_d; // fraction output
wire co; // carry output
reg [27:0] fract_out_q; // fraction output (registerd)
wire [30:0] out_d; // Intermediate final result output
wire overflow_d, underflow_d;// Overflow/Underflow Indicators
reg overflow, underflow; // Output registers for Overflow & Underflow
reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN
reg ine; // Output Registers for INE
reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode
rmode_r3;
reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration
fpu_op_r3;
wire mul_inf, div_inf;
wire mul_00, div_00;
/*
parameter INF = 31'h7f800000;
parameter QNAN = 31'h7fc00001;
parameter SNAN = 31'h7f800001;
*/
wire [1:0] rmode;
assign rmode = 2'b00;
wire [30:0] INF;
assign INF = 31'h7f800000;
wire [30:0] QNAN;
assign QNAN = 31'h7fc00001;
wire [30:0] SNAN;
assign SNAN = 31'h7f800001;
// start output_reg
reg [31:0] out_o1;
reg inf_o1, snan_o1, qnan_o1;
reg ine_o1;
reg overflow_o1, underflow_o1;
reg zero_o1;
reg div_by_zero_o1;
// end output_reg
wire [7:0] contorl;
assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero};
////////////////////////////////////////////////////////////////////////
//
// Input Registers
//
always @(posedge clk) begin
fpu_op[2:0] <= 3'b010;
end
always @(posedge clk)
opa_r <= opa;
always @(posedge clk)
opb_r <= opb;
always @(posedge clk)
rmode_r1 <= rmode;
always @(posedge clk)
rmode_r2 <= rmode_r1;
always @(posedge clk)
rmode_r3 <= rmode_r2;
always @(posedge clk)
fpu_op_r1 <= fpu_op;
always @(posedge clk)
fpu_op_r2 <= fpu_op_r1;
always @(posedge clk)
fpu_op_r3 <= fpu_op_r2;
////////////////////////////////////////////////////////////////////////
//
// Exceptions block
//
wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan;
wire opa_00, opb_00;
wire opa_inf, opb_inf;
wire opa_dn, opb_dn;
except u0( .clk(clk),
.opa(opa_r[30:0]), .opb(opb_r[30:0]),
.inf(inf_d), .ind(ind_d),
.qnan(qnan_d), .snan(snan_d),
.opa_nan(opa_nan), .opb_nan(opb_nan),
.opa_00(opa_00), .opb_00(opb_00),
.opa_inf(opa_inf), .opb_inf(opb_inf),
.opa_dn(opa_dn), .opb_dn(opb_dn)
);
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize block
// - Adjusts the numbers to equal exponents and sorts them
// - determine result sign
// - determine actual operation to perform (add or sub)
//
wire nan_sign_d, result_zero_sign_d;
reg sign_fasu_r;
wire [7:0] exp_mul;
wire sign_mul;
reg sign_mul_r;
wire [23:0] fracta_mul, fractb_mul;
wire inf_mul;
reg inf_mul_r;
wire [1:0] exp_ovf;
reg [1:0] exp_ovf_r;
wire sign_exe;
reg sign_exe_r;
wire [2:0] underflow_fmul_d;
pre_norm_fmul u2(
.clk(clk),
.fpu_op(fpu_op_r1),
.opa(opa_r), .opb(opb_r),
.fracta(fracta_mul),
.fractb(fractb_mul),
.exp_out(exp_mul), // FMUL exponent output (registered)
.sign(sign_mul), // FMUL sign output (registered)
.sign_exe(sign_exe), // FMUL exception sign output (registered)
.inf(inf_mul), // FMUL inf output (registered)
.exp_ovf(exp_ovf), // FMUL exponnent overflow output (registered)
.underflow(underflow_fmul_d)
);
always @(posedge clk)
sign_mul_r <= sign_mul;
always @(posedge clk)
sign_exe_r <= sign_exe;
always @(posedge clk)
inf_mul_r <= inf_mul;
always @(posedge clk)
exp_ovf_r <= exp_ovf;
////////////////////////////////////////////////////////////////////////
//
// Mul
//
wire [47:0] prod;
mul_r2 u5(.clk(clk), .opa(fracta_mul), .opb(fractb_mul), .prod(prod));
////////////////////////////////////////////////////////////////////////
//
// Normalize Result
//
wire ine_d;
reg [47:0] fract_denorm;
wire [47:0] fract_div;
wire sign_d;
reg sign;
reg [30:0] opa_r1;
reg [47:0] fract_i2f;
reg opas_r1, opas_r2;
wire f2i_out_sign;
always @(posedge clk) // Exponent must be once cycle delayed
exp_r <= exp_mul;
always @(posedge clk)
opa_r1 <= opa_r[30:0];
//always @(fpu_op_r3 or prod)
always @(prod)
fract_denorm = prod;
always @(posedge clk)
opas_r1 <= opa_r[31];
always @(posedge clk)
opas_r2 <= opas_r1;
assign sign_d = sign_mul;
always @(posedge clk)
sign <= (rmode_r2==2'h3) ? !sign_d : sign_d;
wire or_result;
assign or_result = mul_00 | div_00;
post_norm u4(
//.clk(clk), // System Clock
.fpu_op(fpu_op_r3), // Floating Point Operation
.opas(opas_r2), // OPA Sign
.sign(sign), // Sign of the result
.rmode(rmode_r3), // Rounding mode
.fract_in(fract_denorm), // Fraction Input
.exp_in(exp_r), // Exponent Input
.exp_ovf(exp_ovf_r), // Exponent Overflow
.opa_dn(opa_dn), // Operand A Denormalized
.opb_dn(opb_dn), // Operand A Denormalized
.rem_00(1'b0), // Diveide Remainder is zero
.div_opa_ldz(5'b00000), // Divide opa leading zeros count
// .output_zero(mul_00 | div_00), // Force output to Zero
.output_zero(or_result), // Force output to Zero
.out(out_d), // Normalized output (un-registered)
.ine(ine_d), // Result Inexact output (un-registered)
.overflow(overflow_d), // Overflow output (un-registered)
.underflow(underflow_d), // Underflow output (un-registered)
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
);
////////////////////////////////////////////////////////////////////////
//
// FPU Outputs
//
wire [30:0] out_fixed;
wire output_zero_fasu;
wire output_zero_fdiv;
wire output_zero_fmul;
reg inf_mul2;
wire overflow_fasu;
wire overflow_fmul;
wire overflow_fdiv;
wire inf_fmul;
wire sign_mul_final;
wire out_d_00;
wire sign_div_final;
wire ine_mul, ine_mula, ine_div, ine_fasu;
wire underflow_fasu, underflow_fmul, underflow_fdiv;
wire underflow_fmul1;
reg [2:0] underflow_fmul_r;
reg opa_nan_r;
always @(posedge clk)
inf_mul2 <= exp_mul == 8'hff;
// Force pre-set values for non numerical output
assign mul_inf = (fpu_op_r3==3'b010) & (inf_mul_r | inf_mul2) & (rmode_r3==2'h0);
assign div_inf = (fpu_op_r3==3'b011) & (opb_00 | opa_inf);
assign mul_00 = (fpu_op_r3==3'b010) & (opa_00 | opb_00);
assign div_00 = (fpu_op_r3==3'b011) & (opa_00 | opb_inf);
assign out_fixed =
( (qnan_d | snan_d) |
(opa_inf & opb_00)|
(opb_inf & opa_00 )
) ? QNAN : INF;
always @(posedge clk)
out_o1[30:0] <= (mul_inf | div_inf | inf_d | snan_d | qnan_d) ? out_fixed : out_d;
assign out_d_00 = !(|out_d);
assign sign_mul_final = (sign_exe_r & ((opa_00 & opb_inf) | (opb_00 & opa_inf))) ? !sign_mul_r : sign_mul_r;
assign sign_div_final = (sign_exe_r & (opa_inf & opb_inf)) ? !sign_mul_r : sign_mul_r | (opa_00 & opb_00);
always @(posedge clk)
// out_o1[31] <= !(snan_d | qnan_d) ? sign_mul_final : nan_sign_d ;
out_o1[31] <= !(snan_d | qnan_d) & sign_mul_final;
// Exception Outputs
assign ine_mula = ((inf_mul_r | inf_mul2 | opa_inf | opb_inf) & (rmode_r3==2'h1) &
!((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3[1]);
assign ine_mul = (ine_mula | ine_d | inf_fmul | out_d_00 | overflow_d | underflow_d) &
!opa_00 & !opb_00 & !(snan_d | qnan_d | inf_d);
always @(posedge clk)
ine_o1 <= ine_mul;
assign overflow_fmul = !inf_d & (inf_mul_r | inf_mul2 | overflow_d) & !(snan_d | qnan_d);
always @(posedge clk)
overflow_o1 <= overflow_fmul;
always @(posedge clk)
underflow_fmul_r <= underflow_fmul_d;
wire out_d_compare1;
assign out_d_compare1 = (out_d[30:23]==8'b0);
wire out_d_compare2;
assign out_d_compare2 = (out_d[22:0]==23'b0);
/*
assign underflow_fmul1 = underflow_fmul_r[0] |
(underflow_fmul_r[1] & underflow_d ) |
((opa_dn | opb_dn) & out_d_00 & (prod!=0) & sign) |
(underflow_fmul_r[2] & ((out_d[30:23]==8'b0) | (out_d[22:0]==23'b0)));
*/
assign underflow_fmul1 = underflow_fmul_r[0] |
(underflow_fmul_r[1] & underflow_d ) |
((opa_dn | opb_dn) & out_d_00 & (prod!=48'b0) & sign) |
(underflow_fmul_r[2] & (out_d_compare1 | out_d_compare2));
assign underflow_fmul = underflow_fmul1 & !(snan_d | qnan_d | inf_mul_r);
/*
always @(posedge clk)
begin
underflow_o1 <= 1'b0;
snan_o1 <= 1'b0;
qnan_o1 <= 1'b0;
inf_fmul <= 1'b0;
inf_o1 <= 1'b0;
zero_o1 <= 1'b0;
opa_nan_r <= 1'b0;
div_by_zero_o1 <= 1'b0;
end
assign output_zero_fmul = 1'b0;
*/
always @(posedge clk)
underflow_o1 <= underflow_fmul;
always @(posedge clk)
snan_o1 <= snan_d;
// Status Outputs
always @(posedge clk)
qnan_o1 <= ( snan_d | qnan_d |
(((opa_inf & opb_00) | (opb_inf & opa_00 )) & fpu_op_r3==3'b010)
);
assign inf_fmul = (((inf_mul_r | inf_mul2) & (rmode_r3==2'h0)) | opa_inf | opb_inf) &
!((opa_inf & opb_00) | (opb_inf & opa_00 )) &
fpu_op_r3==3'b010;
always @(posedge clk)
/*
inf_o1 <= fpu_op_r3[2] ? 1'b0 :
(!(qnan_d | snan_d) &
( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul)
);
*/
inf_o1 <= !fpu_op_r3[2] & (!(qnan_d | snan_d) &
( ((&out_d[30:23]) & !(|out_d[22:0]) & !(opb_00 & fpu_op_r3==3'b011)) | inf_fmul)
);
assign output_zero_fmul = (out_d_00 | opa_00 | opb_00) &
!(inf_mul_r | inf_mul2 | opa_inf | opb_inf | snan_d | qnan_d) &
!(opa_inf & opb_00) & !(opb_inf & opa_00);
always @(posedge clk)
zero_o1 <= output_zero_fmul;
always @(posedge clk)
opa_nan_r <= (!opa_nan) & (fpu_op_r2==3'b011) ;
always @(posedge clk)
div_by_zero_o1 <= opa_nan_r & !opa_00 & !opa_inf & opb_00;
// output register
always @(posedge clk)
begin
qnan <= qnan_o1;
out <= out_o1;
inf <= inf_o1;
snan <= snan_o1;
//qnan <= qnan_o1;
ine <= ine_o1;
overflow <= overflow_o1;
underflow <= underflow_o1;
zero <= zero_o1;
div_by_zero <= div_by_zero_o1;
end
endmodule
//---------------------------------------------------------------------------------
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other special number
//
always @(posedge clk)
expa_ff <= &expa;
always @(posedge clk)
expb_ff <= &expb;
always @(posedge clk)
infa_f_r <= !(|fracta);
always @(posedge clk)
infb_f_r <= !(|fractb);
always @(posedge clk)
qnan_r_a <= fracta[22];
always @(posedge clk)
snan_r_a <= !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= fractb[22];
always @(posedge clk)
snan_r_b <= !fractb[22] & |fractb[21:0];
always @(posedge clk)
ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= !(|expa);
always @(posedge clk)
expb_00 <= !(|expb);
always @(posedge clk)
fracta_00 <= !(|fracta);
always @(posedge clk)
fractb_00 <= !(|fractb);
always @(posedge clk)
opa_00 <= expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= expa_00;
always @(posedge clk)
opb_dn <= expb_00;
endmodule
//---------------------------------------------------------------------------------
module pre_norm_fmul(clk, fpu_op, opa, opb, fracta, fractb, exp_out, sign,
sign_exe, inf, exp_ovf, underflow);
input clk;
input [2:0] fpu_op;
input [31:0] opa, opb;
output [23:0] fracta, fractb;
output [7:0] exp_out;
output sign, sign_exe;
output inf;
output [1:0] exp_ovf;
output [2:0] underflow;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
reg [7:0] exp_out;
wire signa, signb;
reg sign, sign_d;
reg sign_exe;
reg inf;
wire [1:0] exp_ovf_d;
reg [1:0] exp_ovf;
wire [7:0] expa, expb;
wire [7:0] exp_tmp1, exp_tmp2;
wire co1, co2;
wire expa_dn, expb_dn;
wire [7:0] exp_out_a;
wire opa_00, opb_00, fracta_00, fractb_00;
wire [7:0] exp_tmp3, exp_tmp4, exp_tmp5;
wire [2:0] underflow_d;
reg [2:0] underflow;
wire op_div;
wire [7:0] exp_out_mul, exp_out_div;
assign op_div = (fpu_op == 3'b011);
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign signa = opa[31];
assign signb = opb[31];
assign expa = opa[30:23];
assign expb = opb[30:23];
////////////////////////////////////////////////////////////////////////
//
// Calculate Exponenet
//
assign expa_dn = !(|expa);
assign expb_dn = !(|expb);
assign opa_00 = !(|opa[30:0]);
assign opb_00 = !(|opb[30:0]);
assign fracta_00 = !(|opa[22:0]);
assign fractb_00 = !(|opb[22:0]);
assign fracta[22:0] = opa[22:0];
assign fractb[22:0] = opb[22:0];
assign fracta[23:23] = !expa_dn;
assign fractb[23:23] = !expb_dn;
//assign fracta = {!expa_dn,opa[22:0]}; // Recover hidden bit
//assign fractb = {!expb_dn,opb[22:0]}; // Recover hidden bit
assign {co1,exp_tmp1} = op_div ? ({1'b0,expa[7:0]} - {1'b0,expb[7:0]}) : ({1'b0,expa[7:0]} + {1'b0,expb[7:0]});
assign {co2,exp_tmp2} = op_div ? ({co1,exp_tmp1} + 9'h07f) : ({co1,exp_tmp1} - 9'h07f);
assign exp_tmp3 = exp_tmp2 + 8'h01;
assign exp_tmp4 = 8'h7f - exp_tmp1;
assign exp_tmp5 = op_div ? (exp_tmp4+8'h01) : (exp_tmp4-8'h01);
always@(posedge clk)
exp_out <= op_div ? exp_out_div : exp_out_mul;
assign exp_out_div = (expa_dn | expb_dn) ? (co2 ? exp_tmp5 : exp_tmp3 ) : co2 ? exp_tmp4 : exp_tmp2;
assign exp_out_mul = exp_ovf_d[1] ? exp_out_a : (expa_dn | expb_dn) ? exp_tmp3 : exp_tmp2;
assign exp_out_a = (expa_dn | expb_dn) ? exp_tmp5 : exp_tmp4;
assign exp_ovf_d[0] = op_div ? (expa[7] & !expb[7]) : (co2 & expa[7] & expb[7]);
assign exp_ovf_d[1] = op_div ? co2 : ((!expa[7] & !expb[7] & exp_tmp2[7]) | co2);
always @(posedge clk)
exp_ovf <= #1 exp_ovf_d;
assign underflow_d[0] = (exp_tmp1 < 8'h7f) & !co1 & !(opa_00 | opb_00 | expa_dn | expb_dn);
assign underflow_d[1] = ((expa[7] | expb[7]) & !opa_00 & !opb_00) |
(expa_dn & !fracta_00) | (expb_dn & !fractb_00);
assign underflow_d[2] = !opa_00 & !opb_00 & (exp_tmp1 == 8'h7f);
always @(posedge clk)
underflow <= underflow_d;
always @(posedge clk)
inf <= op_div ? (expb_dn & !expa[7]) : ({co1,exp_tmp1} > 9'h17e) ;
////////////////////////////////////////////////////////////////////////
//
// Determine sign for the output
//
// sign: 0=Posetive Number; 1=Negative Number
always @(signa or signb)
case({signa, signb}) // synopsys full_case parallel_case
2'b00: sign_d = 0;
2'b01: sign_d = 1;
2'b10: sign_d = 1;
2'b11: sign_d = 0;
endcase
always @(posedge clk)
sign <= sign_d;
always @(posedge clk)
sign_exe <= signa & signb;
endmodule
//----------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////
//
// Multiply
//
module mul_r2(clk, opa, opb, prod);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk)
prod1 <= #1 opa * opb;
always @(posedge clk)
prod <= #1 prod1;
endmodule
//----------------------------------------------------------------------------
module post_norm( fpu_op, opas, sign, rmode, fract_in, exp_in, exp_ovf,
opa_dn, opb_dn, rem_00, div_opa_ldz, output_zero, out,
ine, overflow, underflow, f2i_out_sign);
input [2:0] fpu_op;
input opas;
input sign;
input [1:0] rmode;
input [47:0] fract_in;
input [7:0] exp_in;
input [1:0] exp_ovf;
input opa_dn, opb_dn;
input rem_00;
input [4:0] div_opa_ldz;
input output_zero;
output [30:0] out;
output ine;
output overflow, underflow;
output f2i_out_sign;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [22:0] fract_out;
wire [7:0] exp_out;
wire [30:0] out;
wire exp_out1_co, overflow, underflow;
wire [22:0] fract_out_final;
reg [22:0] fract_out_rnd;
wire [8:0] exp_next_mi;
wire dn;
wire exp_rnd_adj;
wire [7:0] exp_out_final;
reg [7:0] exp_out_rnd;
wire op_dn;
wire op_mul;
wire op_div;
wire op_i2f;
wire op_f2i;
//reg [5:0] fi_ldz;
wire [5:0] fi_ldz;
wire g, r, s;
wire round, round2, round2a, round2_fasu, round2_fmul;
wire [7:0] exp_out_rnd0, exp_out_rnd1, exp_out_rnd2, exp_out_rnd2a;
wire [22:0] fract_out_rnd0, fract_out_rnd1, fract_out_rnd2, fract_out_rnd2a;
wire exp_rnd_adj0, exp_rnd_adj2a;
wire r_sign;
wire ovf0, ovf1;
wire [23:0] fract_out_pl1;
wire [7:0] exp_out_pl1, exp_out_mi1;
wire exp_out_00, exp_out_fe, exp_out_ff, exp_in_00, exp_in_ff;
wire exp_out_final_ff, fract_out_7fffff;
wire [24:0] fract_trunc;
wire [7:0] exp_out1;
wire grs_sel;
wire fract_out_00, fract_in_00;
wire shft_co;
wire [8:0] exp_in_pl1, exp_in_mi1;
wire [47:0] fract_in_shftr;
wire [47:0] fract_in_shftl;
// for block shifter
wire [47:0] fract_in_shftr_1;
wire [47:0] fract_in_shftl_1;
// end for block shifter
wire [7:0] exp_div;
wire [7:0] shft2;
wire [7:0] exp_out1_mi1;
wire div_dn;
wire div_nr;
wire grs_sel_div;
wire div_inf;
wire [6:0] fi_ldz_2a;
wire [7:0] fi_ldz_2;
wire [7:0] div_shft1, div_shft2, div_shft3, div_shft4;
wire div_shft1_co;
wire [8:0] div_exp1;
wire [7:0] div_exp2, div_exp3;
wire left_right, lr_mul, lr_div;
wire [7:0] shift_right, shftr_mul, shftr_div;
wire [7:0] shift_left, shftl_mul, shftl_div;
wire [7:0] fasu_shift;
wire [7:0] exp_fix_div;
wire [7:0] exp_fix_diva, exp_fix_divb;
wire [5:0] fi_ldz_mi1;
wire [5:0] fi_ldz_mi22;
wire exp_zero;
wire [6:0] ldz_all;
wire [7:0] ldz_dif;
wire [8:0] div_scht1a;
wire [7:0] f2i_shft;
wire [55:0] exp_f2i_1;
wire f2i_zero, f2i_max;
wire [7:0] f2i_emin;
wire [7:0] conv_shft;
wire [7:0] exp_i2f, exp_f2i, conv_exp;
wire round2_f2i;
assign op_mul = fpu_op[2:0]==3'b010;
assign op_div = fpu_op[2:0]==3'b011;
assign op_i2f = fpu_op[2:0]==3'b100;
assign op_f2i = fpu_op[2:0]==3'b101;
assign op_dn = opa_dn | opb_dn;
pri_encoder u6(
.fract_in (fract_in),
.fi_ldz (fi_ldz)
);
// ---------------------------------------------------------------------
// Normalize
wire exp_in_80;
wire rmode_00, rmode_01, rmode_10, rmode_11;
// Misc common signals
assign exp_in_ff = &exp_in;
assign exp_in_00 = !(|exp_in);
assign exp_in_80 = exp_in[7] & !(|exp_in[6:0]);
assign exp_out_ff = &exp_out;
assign exp_out_00 = !(|exp_out);
assign exp_out_fe = &exp_out[7:1] & !exp_out[0];
assign exp_out_final_ff = &exp_out_final;
assign fract_out_7fffff = &fract_out;
assign fract_out_00 = !(|fract_out);
assign fract_in_00 = !(|fract_in);
assign rmode_00 = (rmode==2'b00);
assign rmode_01 = (rmode==2'b01);
assign rmode_10 = (rmode==2'b10);
assign rmode_11 = (rmode==2'b11);
// Fasu Output will be denormalized ...
assign dn = !op_mul & !op_div & (exp_in_00 | (exp_next_mi[8] & !fract_in[47]) );
// ---------------------------------------------------------------------
// Fraction Normalization
wire[7:0] f2i_emax;
assign f2i_emax = 8'h9d;
//parameter f2i_emax = 8'h9d;
// Incremented fraction for rounding
assign fract_out_pl1 = {1'b0, fract_out} + 24'h000001;
// Special Signals for f2i
assign f2i_emin = rmode_00 ? 8'h7e : 8'h7f;
assign f2i_zero = (!opas & (exp_in<f2i_emin)) | (opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & (fract_in_00 | !rmode_11));
assign f2i_max = (!opas & (exp_in>f2i_emax)) | (opas & (exp_in<f2i_emin) & !fract_in_00 & rmode_11);
// Calculate various shifting options
assign {shft_co,shftr_mul} = (!exp_ovf[1] & exp_in_00) ? {1'b0, exp_out} : exp_in_mi1 ;
assign {div_shft1_co, div_shft1} = exp_in_00 ? {1'b0, div_opa_ldz} : div_scht1a;
assign div_scht1a = {1'b0, exp_in}-{4'b0, div_opa_ldz}; // 9 bits - includes carry out
assign div_shft2 = exp_in+8'h02;
assign div_shft3 = {3'b0, div_opa_ldz}+exp_in;
assign div_shft4 = {3'b0, div_opa_ldz}-exp_in;
assign div_dn = op_dn & div_shft1_co;
assign div_nr = op_dn & exp_ovf[1] & !(|fract_in[46:23]) & (div_shft3>8'h16);
assign f2i_shft = exp_in-8'h7d;
// Select shifting direction
assign left_right = op_div ? lr_div : op_mul ? lr_mul :1'b1;
assign lr_div = (op_dn & !exp_ovf[1] & exp_ovf[0]) ? 1'b1 :
(op_dn & exp_ovf[1]) ? 1'b0 :
(op_dn & div_shft1_co) ? 1'b0 :
(op_dn & exp_out_00) ? 1'b1 :
(!op_dn & exp_out_00 & !exp_ovf[1]) ? 1'b1 :
exp_ovf[1] ? 1'b0 :
1'b1;
assign lr_mul = (shft_co | (!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00) )) ? 1'b1 :
( exp_ovf[1] | exp_in_00 ) ? 1'b0 :
1'b1;
// Select Left and Right shift value
assign fasu_shift = (dn | exp_out_00) ? (exp_in_00 ? 8'h02 : exp_in_pl1[7:0]) : {2'h0, fi_ldz};
assign shift_right = op_div ? shftr_div : shftr_mul;
assign conv_shft = op_f2i ? f2i_shft : {2'h0, fi_ldz};
assign shift_left = op_div ? shftl_div : op_mul ? shftl_mul : (op_f2i | op_i2f) ? conv_shft : fasu_shift;
assign shftl_mul = (shft_co |
(!exp_ovf[1] & exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00))) ? exp_in_pl1[7:0] : {2'h0, fi_ldz};
assign shftl_div = ( op_dn & exp_out_00 & !(!exp_ovf[1] & exp_ovf[0])) ? div_shft1[7:0] :
(!op_dn & exp_out_00 & !exp_ovf[1]) ? exp_in[7:0] :
{2'h0, fi_ldz};
assign shftr_div = (op_dn & exp_ovf[1]) ? div_shft3 :
(op_dn & div_shft1_co) ? div_shft4 : div_shft2;
// Do the actual shifting
//assign fract_in_shftr = (|shift_right[7:6]) ? 0 : fract_in>>shift_right[5:0];
//assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 0 : fract_in<<shift_left[5:0];
b_right_shifter u1(
.shift_in (fract_in),
.shift_value (shift_right[5:0]),
.shift_out (fract_in_shftr_1)
);
assign fract_in_shftr = (|shift_right[7:6]) ? 48'b0 : fract_in_shftr_1; // fract_in>>shift_right[5:0];
b_left_shifter u7(
.shift_in (fract_in),
.shift_value (shift_left[5:0]),
.shift_out (fract_in_shftl_1)
);
assign fract_in_shftl = (|shift_left[7:6] | (f2i_zero & op_f2i)) ? 48'b0 : fract_in_shftl_1; // fract_in<<shift_left[5:0];
// Chose final fraction output
assign {fract_out,fract_trunc} = left_right ? fract_in_shftl : fract_in_shftr;
// ---------------------------------------------------------------------
// Exponent Normalization
assign fi_ldz_mi1 = fi_ldz - 6'h01;
assign fi_ldz_mi22 = fi_ldz - 6'd22;
assign exp_out_pl1 = exp_out + 8'h01;
assign exp_out_mi1 = exp_out - 8'h01;
assign exp_in_pl1 = {1'b0, exp_in} + 9'd1; // 9 bits - includes carry out
assign exp_in_mi1 = {1'b0, exp_in} - 9'd1; // 9 bits - includes carry out
assign exp_out1_mi1 = exp_out1 - 8'h01;
assign exp_next_mi = exp_in_pl1 - {3'b0, fi_ldz_mi1}; // 9 bits - includes carry out
assign exp_fix_diva = exp_in - {2'b0, fi_ldz_mi22};
assign exp_fix_divb = exp_in - {2'b0, fi_ldz_mi1};
//assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul & (!exp_rnd_adj2a | !rmode[1])) | (op_mul & exp_out1_co);
assign exp_zero = (exp_ovf[1] & !exp_ovf[0] & op_mul ) | (op_mul & exp_out1_co);
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
assign f2i_out_sign = !opas ? ((exp_in<f2i_emin) ? 1'b0 : (exp_in>f2i_emax) ? 1'b0 : opas) :
((exp_in<f2i_emin) ? 1'b0 : (exp_in>f2i_emax) ? 1'b1 : opas);
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 8'h00) : (8'h9e-{2'b0, fi_ldz});
//assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
b_left_shifter_new u3(
.shift_in ({{8{fract_in[47]}}, fract_in }),
.shift_value (f2i_shft[5:0]),
.shift_out (exp_f2i_1)
);
assign exp_f2i = f2i_zero ? 8'h00 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
assign exp_out = op_div ? exp_div : (op_f2i | op_i2f) ? conv_exp : exp_zero ? 8'h0 : dn ? {6'h0, fract_in[47:46]} : exp_out1;
assign ldz_all = {2'b0, div_opa_ldz} + {1'b0, fi_ldz};
assign ldz_dif = fi_ldz_2 - {3'b0, div_opa_ldz};
assign fi_ldz_2a = 7'd23 - {1'b0,fi_ldz};
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
assign div_exp1 = exp_in_mi1 + {1'b0, fi_ldz_2}; // 9 bits - includes carry out
assign div_exp2 = exp_in_pl1[7:0] - {1'b0, ldz_all};
assign div_exp3 = exp_in + ldz_dif;
assign exp_div =(opa_dn & opb_dn)? div_exp3 : opb_dn? div_exp1[7:0] :
(opa_dn & !( (exp_in[4:0]<div_opa_ldz) | (div_exp2>8'hfe) )) ? div_exp2 :
(opa_dn | (exp_in_00 & !exp_ovf[1]) ) ? 8'h00 :
exp_out1_mi1;
assign div_inf = opb_dn & !opa_dn & (div_exp1[7:0] < 8'h7f);
// ---------------------------------------------------------------------
// Round
// Extract rounding (GRS) bits
assign grs_sel_div = op_div & (exp_ovf[1] | div_dn | exp_out1_co | exp_out_00);
assign g = grs_sel_div ? fract_out[0] : fract_out[0];
assign r = grs_sel_div ? (fract_trunc[24] & !div_nr) : fract_trunc[24];
assign s = grs_sel_div ? |fract_trunc[24:0] : (|fract_trunc[23:0] | (fract_trunc[24] & op_div));
// Round to nearest even
assign round = (g & r) | (r & s) ;
assign {exp_rnd_adj0, fract_out_rnd0} = round ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd0 = exp_rnd_adj0 ? exp_out_pl1 : exp_out;
assign ovf0 = exp_out_final_ff & !rmode_01 & !op_f2i;
// round to zero
assign fract_out_rnd1 = (exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out;
assign exp_fix_div = (fi_ldz>6'd22) ? exp_fix_diva : exp_fix_divb;
assign exp_out_rnd1 = (g & r & s & exp_in_ff) ? (op_div ? exp_fix_div : exp_next_mi[7:0]) : (exp_out_ff & !op_f2i) ? exp_in : exp_out;
assign ovf1 = exp_out_ff & !dn;
// round to +inf (UP) and -inf (DOWN)
assign r_sign = sign;
assign round2a = !exp_out_fe | !fract_out_7fffff | (exp_out_fe & fract_out_7fffff);
assign round2_fasu = ((r | s) & !r_sign) & (!exp_out[7] | (exp_out[7] & round2a));
assign round2_fmul = !r_sign &
(
(exp_ovf[1] & !fract_in_00 &
( ((!exp_out1_co | op_dn) & (r | s | (!rem_00 & op_div) )) | fract_out_00 | (!op_dn & !op_div))
) |
(
(r | s | (!rem_00 & op_div)) & (
(!exp_ovf[1] & (exp_in_80 | !exp_ovf[0])) | op_div |
( exp_ovf[1] & !exp_ovf[0] & exp_out1_co)
)
)
);
//assign round2_f2i = rmode_10 & (( |fract_in[23:0] & !opas & (exp_in<8'h80 )) | (|fract_trunc));
wire temp_fract_in;
assign temp_fract_in = |fract_in[23:0];
assign round2_f2i = rmode_10 & (( temp_fract_in & !opas & (exp_in<8'h80 )) | (|fract_trunc));
assign round2 = (op_mul | op_div) ? round2_fmul : op_f2i ? round2_f2i : round2_fasu;
assign {exp_rnd_adj2a, fract_out_rnd2a} = round2 ? fract_out_pl1 : {1'b0, fract_out};
assign exp_out_rnd2a = exp_rnd_adj2a ? ((exp_ovf[1] & op_mul) ? exp_out_mi1 : exp_out_pl1) : exp_out;
assign fract_out_rnd2 = (r_sign & exp_out_ff & !op_div & !dn & !op_f2i) ? 23'h7fffff : fract_out_rnd2a;
assign exp_out_rnd2 = (r_sign & exp_out_ff & !op_f2i) ? 8'hfe : exp_out_rnd2a;
// Choose rounding mode
always @(rmode or exp_out_rnd0 or exp_out_rnd1 or exp_out_rnd2)
case(rmode) // synopsys full_case parallel_case
2'b00: exp_out_rnd = exp_out_rnd0;
2'b01: exp_out_rnd = exp_out_rnd1;
2'b10: exp_out_rnd = exp_out_rnd2;
2'b11: exp_out_rnd = exp_out_rnd2;
endcase
always @(rmode or fract_out_rnd0 or fract_out_rnd1 or fract_out_rnd2)
case(rmode) // synopsys full_case parallel_case
2'b00: fract_out_rnd = fract_out_rnd0;
2'b01: fract_out_rnd = fract_out_rnd1;
2'b10: fract_out_rnd = fract_out_rnd2;
2'b11: fract_out_rnd = fract_out_rnd2;
endcase
// ---------------------------------------------------------------------
// Final Output Mux
// Fix Output for denormalized and special numbers
wire max_num, inf_out;
assign max_num = ( !rmode_00 & (op_mul | op_div ) & (
( exp_ovf[1] & exp_ovf[0]) |
(!exp_ovf[1] & !exp_ovf[0] & exp_in_ff & (fi_ldz_2<8'd24) & (exp_out!=8'hfe) )
)
) |
( op_div & (
( rmode_01 & ( div_inf |
(exp_out_ff & !exp_ovf[1] ) |
(exp_ovf[1] & exp_ovf[0] )
)
) |
( rmode[1] & !exp_ovf[1] & (
( exp_ovf[0] & exp_in_ff & r_sign & fract_in[47]
) |
( r_sign & (
(fract_in[47] & div_inf) |
(exp_in[7] & !exp_out_rnd[7] & !exp_in_80 & exp_out!=8'h7f ) |
(exp_in[7] & exp_out_rnd[7] & r_sign & exp_out_ff & op_dn &
div_exp1>9'h0fe )
)
) |
( exp_in_00 & r_sign & (
div_inf |
(r_sign & exp_out_ff & fi_ldz_2<8'h18)
)
)
)
)
)
);
assign inf_out = (rmode[1] & (op_mul | op_div) & !r_sign & ( (exp_in_ff & !op_div) |
(exp_ovf[1] & exp_ovf[0] & (exp_in_00 | exp_in[7]) )
)
) | (div_inf & op_div & (
rmode_00 |
(rmode[1] & !exp_in_ff & !exp_ovf[1] & !exp_ovf[0] & !r_sign ) |
(rmode[1] & !exp_ovf[1] & exp_ovf[0] & exp_in_00 & !r_sign)
)
) | (op_div & rmode[1] & exp_in_ff & op_dn & !r_sign & (fi_ldz_2 < 8'd24) & (exp_out_rnd!=8'hfe) );
assign fract_out_final = (inf_out | ovf0 | output_zero ) ? 23'h000000 :
(max_num | (f2i_max & op_f2i) ) ? 23'h7fffff :
fract_out_rnd;
assign exp_out_final = ((op_div & exp_ovf[1] & !exp_ovf[0]) | output_zero ) ? 8'h00 :
((op_div & exp_ovf[1] & exp_ovf[0] & rmode_00) | inf_out | (f2i_max & op_f2i) ) ? 8'hff :
max_num ? 8'hfe :
exp_out_rnd;
// ---------------------------------------------------------------------
// Pack Result
assign out = {exp_out_final, fract_out_final};
// ---------------------------------------------------------------------
// Exceptions
wire underflow_fmul;
wire overflow_fdiv;
wire undeflow_div;
wire z;
assign z = shft_co | ( exp_ovf[1] | exp_in_00) |
(!exp_ovf[1] & !exp_in_00 & (exp_out1_co | exp_out_00));
assign underflow_fmul = ( (|fract_trunc) & z & !exp_in_ff ) |
(fract_out_00 & !fract_in_00 & exp_ovf[1]);
assign undeflow_div = !(exp_ovf[1] & exp_ovf[0] & rmode_00) & !inf_out & !max_num & exp_out_final!=8'hff & (
((|fract_trunc) & !opb_dn & (
( op_dn & !exp_ovf[1] & exp_ovf[0]) |
( op_dn & exp_ovf[1]) |
( op_dn & div_shft1_co) |
exp_out_00 |
exp_ovf[1]
)
) |
( exp_ovf[1] & !exp_ovf[0] & (
( op_dn & exp_in>8'h16 & fi_ldz<6'd23) |
( op_dn & exp_in<8'd23 & fi_ldz<6'd23 & !rem_00) |
( !op_dn & (exp_in[7]==exp_div[7]) & !rem_00) |
( !op_dn & exp_in_00 & (exp_div[7:1]==7'h7f) ) |
( !op_dn & exp_in<8'h7f & exp_in>8'h20 )
)
) |
(!exp_ovf[1] & !exp_ovf[0] & (
( op_dn & fi_ldz<6'd23 & exp_out_00) |
( exp_in_00 & !rem_00) |
( !op_dn & ldz_all<7'd23 & exp_in==8'h01 & exp_out_00 & !rem_00)
)
)
);
assign underflow = op_div ? undeflow_div : op_mul ? underflow_fmul : (!fract_in[47] & exp_out1_co) & !dn;
assign overflow_fdiv = inf_out |
(!rmode_00 & max_num) |
(exp_in[7] & op_dn & exp_out_ff) |
(exp_ovf[0] & (exp_ovf[1] | exp_out_ff) );
assign overflow = op_div ? overflow_fdiv : (ovf0 | ovf1);
wire f2i_ine;
assign f2i_ine = (f2i_zero & !fract_in_00 & !opas) |
(|fract_trunc) |
(f2i_zero & (exp_in<8'h80) & opas & !fract_in_00) |
(f2i_max & rmode_11 & (exp_in<8'h80));
assign ine = op_f2i ? f2i_ine :
op_i2f ? (|fract_trunc) :
((r & !dn) | (s & !dn) | max_num | (op_div & !rem_00));
endmodule
//-------------------------------------------------------------------------------------
module pri_encoder ( fract_in, fi_ldz );
input [47:0] fract_in;
output [5:0] fi_ldz;
reg [5:0] fi_ldz_r0;
assign fi_ldz = fi_ldz_r0;
always @(fract_in)
begin
if (fract_in[47:47] == 1'b1)
fi_ldz_r0 = 6'd1;
else if (fract_in[47:46] == 2'b01)
fi_ldz_r0 = 6'd2;
else if (fract_in[47:45] == 3'b001)
fi_ldz_r0 = 6'd3;
else if (fract_in[47:44] == 4'b0001)
fi_ldz_r0 = 6'd4;
else if (fract_in[47:43] == 5'b00001)
fi_ldz_r0 = 6'd5;
else if (fract_in[47:42] == 6'b000001)
fi_ldz_r0 = 6'd6;
else if (fract_in[47:41] == 7'b0000001)
fi_ldz_r0 = 6'd7;
else if (fract_in[47:40] == 8'b00000001)
fi_ldz_r0 = 6'd8;
else if (fract_in[47:39] == 9'b000000001)
fi_ldz_r0 = 6'd9;
else if (fract_in[47:38] == 10'b0000000001)
fi_ldz_r0 = 6'd10;
else if (fract_in[47:37] == 11'b00000000001)
fi_ldz_r0 = 6'd11;
else if (fract_in[47:36] == 12'b000000000001)
fi_ldz_r0 = 6'd12;
else if (fract_in[47:35] == 13'b0000000000001)
fi_ldz_r0 = 6'd13;
else if (fract_in[47:34] == 14'b00000000000001)
fi_ldz_r0 = 6'd14;
else if (fract_in[47:33] == 15'b000000000000001)
fi_ldz_r0 = 6'd15;
else if (fract_in[47:32] == 16'b0000000000000001)
fi_ldz_r0 = 6'd16;
else if (fract_in[47:31] == 17'b00000000000000001)
fi_ldz_r0 = 6'd17;
else if (fract_in[47:30] == 18'b000000000000000001)
fi_ldz_r0 = 6'd18;
else if (fract_in[47:29] == 19'b0000000000000000001)
fi_ldz_r0 = 6'd19;
else if (fract_in[47:28] == 20'b00000000000000000001)
fi_ldz_r0 = 6'd20;
else if (fract_in[47:27] == 21'b000000000000000000001)
fi_ldz_r0 = 6'd21;
else if (fract_in[47:26] == 22'b0000000000000000000001)
fi_ldz_r0 = 6'd22;
else if (fract_in[47:25] == 23'b00000000000000000000001)
fi_ldz_r0 = 6'd23;
else if (fract_in[47:24] == 24'b000000000000000000000001)
fi_ldz_r0 = 6'd24;
else if (fract_in[47:23] == 25'b0000000000000000000000001)
fi_ldz_r0 = 6'd25;
else if (fract_in[47:22] == 26'b00000000000000000000000001)
fi_ldz_r0 = 6'd26;
else if (fract_in[47:21] == 27'b000000000000000000000000001)
fi_ldz_r0 = 6'd27;
else if (fract_in[47:20] == 28'b0000000000000000000000000001)
fi_ldz_r0 = 6'd28;
else if (fract_in[47:19] == 29'b00000000000000000000000000001)
fi_ldz_r0 = 6'd29;
else if (fract_in[47:18] == 30'b000000000000000000000000000001)
fi_ldz_r0 = 6'd30;
else if (fract_in[47:17] == 31'b0000000000000000000000000000001)
fi_ldz_r0 = 6'd31;
else if (fract_in[47:16] == 32'b00000000000000000000000000000001)
fi_ldz_r0 = 6'd32;
else if (fract_in[47:15] == 33'b000000000000000000000000000000001)
fi_ldz_r0 = 6'd33;
else if (fract_in[47:14] == 34'b0000000000000000000000000000000001)
fi_ldz_r0 = 6'd34;
else if (fract_in[47:13] == 35'b00000000000000000000000000000000001)
fi_ldz_r0 = 6'd35;
else if (fract_in[47:12] == 36'b000000000000000000000000000000000001)
fi_ldz_r0 = 6'd36;
else if (fract_in[47:11] == 37'b0000000000000000000000000000000000001)
fi_ldz_r0 = 6'd37;
else if (fract_in[47:10] == 38'b00000000000000000000000000000000000001)
fi_ldz_r0 = 6'd38;
else if (fract_in[47:9] == 39'b000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd39;
else if (fract_in[47:8] == 40'b0000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd40;
else if (fract_in[47:7] == 41'b00000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd41;
else if (fract_in[47:6] == 42'b000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd42;
else if (fract_in[47:5] == 43'b0000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd43;
else if (fract_in[47:4] == 44'b00000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd44;
else if (fract_in[47:3] == 45'b000000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd45;
else if (fract_in[47:2] == 46'b0000000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd46;
else if (fract_in[47:1] == 47'b00000000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd47;
else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000001)
fi_ldz_r0 = 6'd48;
else if (fract_in[47:0] == 48'b000000000000000000000000000000000000000000000000)
fi_ldz_r0 = 6'd48;
end
endmodule
module b_right_shifter (
shift_in,
shift_value,
shift_out
);
input [47:0] shift_in;
input [5:0] shift_value;
output [47:0] shift_out;
reg [47:0] shift_out;
always @(shift_value)
begin
case (shift_value)
6'b000000: shift_out = shift_in;
6'b000001: shift_out = shift_in >> 1;
6'b000010: shift_out = shift_in >> 2;
6'b000011: shift_out = shift_in >> 3;
6'b000100: shift_out = shift_in >> 4;
6'b000101: shift_out = shift_in >> 5;
6'b000110: shift_out = shift_in >> 6;
6'b000111: shift_out = shift_in >> 7;
6'b001000: shift_out = shift_in >> 8;
6'b001001: shift_out = shift_in >> 9;
6'b001010: shift_out = shift_in >> 10;
6'b001011: shift_out = shift_in >> 11;
6'b001100: shift_out = shift_in >> 12;
6'b001101: shift_out = shift_in >> 13;
6'b001110: shift_out = shift_in >> 14;
6'b001111: shift_out = shift_in >> 15;
6'b010000: shift_out = shift_in >> 16;
6'b010001: shift_out = shift_in >> 17;
6'b010010: shift_out = shift_in >> 18;
6'b010011: shift_out = shift_in >> 19;
6'b010100: shift_out = shift_in >> 20;
6'b010101: shift_out = shift_in >> 21;
6'b010110: shift_out = shift_in >> 22;
6'b010111: shift_out = shift_in >> 23;
6'b011000: shift_out = shift_in >> 24;
6'b011001: shift_out = shift_in >> 25;
6'b011010: shift_out = shift_in >> 26;
6'b011011: shift_out = shift_in >> 27;
6'b011100: shift_out = shift_in >> 28;
6'b011101: shift_out = shift_in >> 29;
6'b011110: shift_out = shift_in >> 30;
6'b011111: shift_out = shift_in >> 31;
6'b100000: shift_out = shift_in >> 32;
6'b100001: shift_out = shift_in >> 33;
6'b100010: shift_out = shift_in >> 34;
6'b100011: shift_out = shift_in >> 35;
6'b100100: shift_out = shift_in >> 36;
6'b100101: shift_out = shift_in >> 37;
6'b100110: shift_out = shift_in >> 38;
6'b100111: shift_out = shift_in >> 39;
6'b101000: shift_out = shift_in >> 40;
6'b101001: shift_out = shift_in >> 41;
6'b101010: shift_out = shift_in >> 42;
6'b101011: shift_out = shift_in >> 43;
6'b101100: shift_out = shift_in >> 44;
6'b101101: shift_out = shift_in >> 45;
6'b101110: shift_out = shift_in >> 46;
6'b101111: shift_out = shift_in >> 47;
6'b110000: shift_out = shift_in >> 48;
endcase
end
//assign shift_out = shift_in >> shift_value;
endmodule
module b_left_shifter (
shift_in,
shift_value,
shift_out
);
input [47:0] shift_in;
input [5:0] shift_value;
output [47:0] shift_out;
reg [47:0] shift_out;
always @(shift_value)
begin
case (shift_value)
6'b000000: shift_out = shift_in;
6'b000001: shift_out = shift_in << 1;
6'b000010: shift_out = shift_in << 2;
6'b000011: shift_out = shift_in << 3;
6'b000100: shift_out = shift_in << 4;
6'b000101: shift_out = shift_in << 5;
6'b000110: shift_out = shift_in << 6;
6'b000111: shift_out = shift_in << 7;
6'b001000: shift_out = shift_in << 8;
6'b001001: shift_out = shift_in << 9;
6'b001010: shift_out = shift_in << 10;
6'b001011: shift_out = shift_in << 11;
6'b001100: shift_out = shift_in << 12;
6'b001101: shift_out = shift_in << 13;
6'b001110: shift_out = shift_in << 14;
6'b001111: shift_out = shift_in << 15;
6'b010000: shift_out = shift_in << 16;
6'b010001: shift_out = shift_in << 17;
6'b010010: shift_out = shift_in << 18;
6'b010011: shift_out = shift_in << 19;
6'b010100: shift_out = shift_in << 20;
6'b010101: shift_out = shift_in << 21;
6'b010110: shift_out = shift_in << 22;
6'b010111: shift_out = shift_in << 23;
6'b011000: shift_out = shift_in << 24;
6'b011001: shift_out = shift_in << 25;
6'b011010: shift_out = shift_in << 26;
6'b011011: shift_out = shift_in << 27;
6'b011100: shift_out = shift_in << 28;
6'b011101: shift_out = shift_in << 29;
6'b011110: shift_out = shift_in << 30;
6'b011111: shift_out = shift_in << 31;
6'b100000: shift_out = shift_in << 32;
6'b100001: shift_out = shift_in << 33;
6'b100010: shift_out = shift_in << 34;
6'b100011: shift_out = shift_in << 35;
6'b100100: shift_out = shift_in << 36;
6'b100101: shift_out = shift_in << 37;
6'b100110: shift_out = shift_in << 38;
6'b100111: shift_out = shift_in << 39;
6'b101000: shift_out = shift_in << 40;
6'b101001: shift_out = shift_in << 41;
6'b101010: shift_out = shift_in << 42;
6'b101011: shift_out = shift_in << 43;
6'b101100: shift_out = shift_in << 44;
6'b101101: shift_out = shift_in << 45;
6'b101110: shift_out = shift_in << 46;
6'b101111: shift_out = shift_in << 47;
6'b110000: shift_out = shift_in << 48;
endcase
end
endmodule
module b_left_shifter_new (
shift_in,
shift_value,
shift_out
);
input [55:0] shift_in;
input [5:0] shift_value;
output [55:0] shift_out;
reg [47:0] shift_out;
always @(shift_value)
begin
case (shift_value)
6'b000000: shift_out = shift_in;
6'b000001: shift_out = shift_in << 1;
6'b000010: shift_out = shift_in << 2;
6'b000011: shift_out = shift_in << 3;
6'b000100: shift_out = shift_in << 4;
6'b000101: shift_out = shift_in << 5;
6'b000110: shift_out = shift_in << 6;
6'b000111: shift_out = shift_in << 7;
6'b001000: shift_out = shift_in << 8;
6'b001001: shift_out = shift_in << 9;
6'b001010: shift_out = shift_in << 10;
6'b001011: shift_out = shift_in << 11;
6'b001100: shift_out = shift_in << 12;
6'b001101: shift_out = shift_in << 13;
6'b001110: shift_out = shift_in << 14;
6'b001111: shift_out = shift_in << 15;
6'b010000: shift_out = shift_in << 16;
6'b010001: shift_out = shift_in << 17;
6'b010010: shift_out = shift_in << 18;
6'b010011: shift_out = shift_in << 19;
6'b010100: shift_out = shift_in << 20;
6'b010101: shift_out = shift_in << 21;
6'b010110: shift_out = shift_in << 22;
6'b010111: shift_out = shift_in << 23;
6'b011000: shift_out = shift_in << 24;
6'b011001: shift_out = shift_in << 25;
6'b011010: shift_out = shift_in << 26;
6'b011011: shift_out = shift_in << 27;
6'b011100: shift_out = shift_in << 28;
6'b011101: shift_out = shift_in << 29;
6'b011110: shift_out = shift_in << 30;
6'b011111: shift_out = shift_in << 31;
6'b100000: shift_out = shift_in << 32;
6'b100001: shift_out = shift_in << 33;
6'b100010: shift_out = shift_in << 34;
6'b100011: shift_out = shift_in << 35;
6'b100100: shift_out = shift_in << 36;
6'b100101: shift_out = shift_in << 37;
6'b100110: shift_out = shift_in << 38;
6'b100111: shift_out = shift_in << 39;
6'b101000: shift_out = shift_in << 40;
6'b101001: shift_out = shift_in << 41;
6'b101010: shift_out = shift_in << 42;
6'b101011: shift_out = shift_in << 43;
6'b101100: shift_out = shift_in << 44;
6'b101101: shift_out = shift_in << 45;
6'b101110: shift_out = shift_in << 46;
6'b101111: shift_out = shift_in << 47;
6'b110000: shift_out = shift_in << 48;
6'b110001: shift_out = shift_in << 49;
6'b110010: shift_out = shift_in << 50;
6'b110011: shift_out = shift_in << 51;
6'b110100: shift_out = shift_in << 52;
6'b110101: shift_out = shift_in << 53;
6'b110110: shift_out = shift_in << 54;
6'b110111: shift_out = shift_in << 55;
6'b111000: shift_out = shift_in << 56;
endcase
end
endmodule
module fpu_add( clk,
//rmode,
opa, opb, out,
control
//inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero
);
input clk;
//input [1:0] rmode;
//input [2:0] fpu_op;
input [31:0] opa, opb;
output [31:0] out;
/*
output inf, snan, qnan;
output ine;
output overflow, underflow;
output zero;
output div_by_zero;
*/
output [7:0] control;
/*
parameter INF = 31'h7f800000;
parameter QNAN = 31'h7fc00001;
parameter SNAN = 31'h7f800001;
*/
wire [30:0] INF;
assign INF = 31'h7f800000;
wire [30:0] QNAN;
assign QNAN = 31'h7fc00001;
wire [30:0] SNAN;
assign SNAN = 31'h7f800001;
////////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [2:0] fpu_op;
reg zero;
reg [31:0] opa_r, opb_r; // Input operand registers
reg [31:0] out; // Output register
reg div_by_zero; // Divide by zero output register
// wire signa, signb; // alias to opX sign
wire sign_fasu; // sign output
wire [26:0] fracta, fractb; // Fraction Outputs from EQU block
wire [7:0] exp_fasu; // Exponent output from EQU block
reg [7:0] exp_r; // Exponent output (registerd)
wire [26:0] fract_out_d; // fraction output
// wire co; // carry output
reg [27:0] fract_out_q; // fraction output (registerd)
wire [30:0] out_d; // Intermediate final result output
wire overflow_d, underflow_d;// Overflow/Underflow Indicators
reg overflow, underflow; // Output registers for Overflow & Underflow
reg inf, snan, qnan; // Output Registers for INF, SNAN and QNAN
reg ine; // Output Registers for INE
reg [1:0] rmode_r1, rmode_r2, // Pipeline registers for rounding mode
rmode_r3;
reg [2:0] fpu_op_r1, fpu_op_r2, // Pipeline registers for fp opration
fpu_op_r3;
// wire mul_inf, div_inf;
// wire mul_00, div_00;
// start output_reg
reg [31:0] out_o1;
reg inf_o1, snan_o1, qnan_o1;
reg ine_o1;
reg overflow_o1, underflow_o1;
reg zero_o1;
reg div_by_zero_o1;
// end output_reg
wire [7:0] contorl;
assign control = {inf, snan, qnan, ine, overflow, underflow, zero, div_by_zero};
wire [1:0] rmode;
assign rmode= 2'b00;
always@(posedge clk)
begin
fpu_op[2:0] <= 3'b000;
end
////////////////////////////////////////////////////////////////////////
//
// Input Registers
//
always @(posedge clk)
opa_r <= opa;
always @(posedge clk)
opb_r <= opb;
always @(posedge clk)
rmode_r1 <= rmode;
always @(posedge clk)
rmode_r2 <= rmode_r1;
always @(posedge clk)
rmode_r3 <= rmode_r2;
always @(posedge clk)
fpu_op_r1 <= fpu_op;
always @(posedge clk)
fpu_op_r2 <= fpu_op_r1;
always @(posedge clk)
fpu_op_r3 <= fpu_op_r2;
////////////////////////////////////////////////////////////////////////
//
// Exceptions block
//
wire inf_d, ind_d, qnan_d, snan_d, opa_nan, opb_nan;
wire opa_00, opb_00;
wire opa_inf, opb_inf;
wire opa_dn, opb_dn;
except u0( .clk(clk),
.opa(opa_r), .opb(opb_r),
.inf(inf_d), .ind(ind_d),
.qnan(qnan_d), .snan(snan_d),
.opa_nan(opa_nan), .opb_nan(opb_nan),
.opa_00(opa_00), .opb_00(opb_00),
.opa_inf(opa_inf), .opb_inf(opb_inf),
.opa_dn(opa_dn), .opb_dn(opb_dn)
);
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize block
// - Adjusts the numbers to equal exponents and sorts them
// - determine result sign
// - determine actual operation to perform (add or sub)
//
wire nan_sign_d, result_zero_sign_d;
reg sign_fasu_r;
wire fasu_op;
wire add_input;
assign add_input=!fpu_op_r1[0];
pre_norm u1(.clk(clk), // System Clock
.rmode(rmode_r2), // Roundin Mode
// .add(!fpu_op_r1[0]), // Add/Sub Input
.add(add_input),
.opa(opa_r), .opb(opb_r), // Registered OP Inputs
.opa_nan(opa_nan), // OpA is a NAN indicator
.opb_nan(opb_nan), // OpB is a NAN indicator
.fracta_out(fracta), // Equalized and sorted fraction
.fractb_out(fractb), // outputs (Registered)
.exp_dn_out(exp_fasu), // Selected exponent output (registered);
.sign(sign_fasu), // Encoded output Sign (registered)
.nan_sign(nan_sign_d), // Output Sign for NANs (registered)
.result_zero_sign(result_zero_sign_d), // Output Sign for zero result (registered)
.fasu_op(fasu_op) // Actual fasu operation output (registered)
);
always @(posedge clk)
sign_fasu_r <= #1 sign_fasu;
wire co_d;
////////////////////////////////////////////////////////////////////////
//
// Add/Sub
//
add_sub27 u3(
.add(fasu_op), // Add/Sub
.opa(fracta), // Fraction A input
.opb(fractb), // Fraction B Input
.sum(fract_out_d), // SUM output
.co(co_d) ); // Carry Output
always @(posedge clk)
fract_out_q <= #1 {co_d, fract_out_d};
////////////////////////////////////////////////////////////////////////
//
// Normalize Result
//
wire ine_d;
//reg [47:0] fract_denorm;
wire [47:0] fract_denorm;
wire sign_d;
reg sign;
reg [30:0] opa_r1;
reg [47:0] fract_i2f;
reg opas_r1, opas_r2;
wire f2i_out_sign;
always @(posedge clk) // Exponent must be once cycle delayed
exp_r <= #1 exp_fasu;
always @(posedge clk)
opa_r1 <= #1 opa_r[30:0];
//always @(fpu_op_r3 or fract_out_q)
assign fract_denorm = {fract_out_q, 20'h0};
always @(posedge clk)
opas_r1 <= #1 opa_r[31];
always @(posedge clk)
opas_r2 <= #1 opas_r1;
assign sign_d = sign_fasu;
always @(posedge clk)
sign <= #1 (rmode_r2==2'h3) ? !sign_d : sign_d;
post_norm u4(
//.clk(clk), // System Clock
.fpu_op(fpu_op_r3), // Floating Point Operation
.opas(opas_r2), // OPA Sign
.sign(sign), // Sign of the result
.rmode(rmode_r3), // Rounding mode
.fract_in(fract_denorm), // Fraction Input
.exp_in(exp_r), // Exponent Input
.exp_ovf(2'b00), // Exponent Overflow
.opa_dn(opa_dn), // Operand A Denormalized
.opb_dn(opb_dn), // Operand A Denormalized
.rem_00(1'b0), // Diveide Remainder is zero
.div_opa_ldz(5'b00000), // Divide opa leading zeros count
.output_zero(1'b0), // Force output to Zero
.out(out_d), // Normalized output (un-registered)
.ine(ine_d), // Result Inexact output (un-registered)
.overflow(overflow_d), // Overflow output (un-registered)
.underflow(underflow_d), // Underflow output (un-registered)
.f2i_out_sign(f2i_out_sign) // F2I Output Sign
);
////////////////////////////////////////////////////////////////////////
//
// FPU Outputs
//
reg fasu_op_r1, fasu_op_r2;
wire [30:0] out_fixed;
wire output_zero_fasu;
wire overflow_fasu;
wire out_d_00;
wire ine_fasu;
wire underflow_fasu;
reg opa_nan_r;
always @(posedge clk)
fasu_op_r1 <= #1 fasu_op;
always @(posedge clk)
fasu_op_r2 <= #1 fasu_op_r1;
// Force pre-set values for non numerical output
assign out_fixed = ( (qnan_d | snan_d) |
(ind_d & !fasu_op_r2) ) ? QNAN : INF;
always @(posedge clk)
out_o1[30:0] <= #1 (inf_d | snan_d | qnan_d) ? out_fixed : out_d;
assign out_d_00 = !(|out_d);
always @(posedge clk)
out_o1[31] <= #1 (snan_d | qnan_d | ind_d) ? nan_sign_d :
output_zero_fasu ? result_zero_sign_d :
sign_fasu_r;
assign ine_fasu = (ine_d | overflow_d | underflow_d) & !(snan_d | qnan_d | inf_d);
always @(posedge clk)
ine_o1 <= #1 ine_fasu ;
assign overflow_fasu = overflow_d & !(snan_d | qnan_d | inf_d);
always @(posedge clk)
overflow_o1 <= #1 overflow_fasu ;
assign underflow_fasu = underflow_d & !(inf_d | snan_d | qnan_d);
always @(posedge clk)
underflow_o1 <= #1 underflow_fasu ;
always @(posedge clk)
snan_o1 <= #1 snan_d;
// Status Outputs
always @(posedge clk)
qnan_o1 <= #1 ( snan_d | qnan_d | (ind_d & !fasu_op_r2) );
always @(posedge clk)
inf_o1 <= #1 (!(qnan_d | snan_d) & (( (&out_d[30:23]) & !(|out_d[22:0] ) ) | (inf_d & !(ind_d & !fasu_op_r2) & !fpu_op_r3[1]) ));
assign output_zero_fasu = out_d_00 & !(inf_d | snan_d | qnan_d);
always @(posedge clk)
zero_o1 <= #1 output_zero_fasu ;
always @(posedge clk)
opa_nan_r <= #1 !opa_nan & fpu_op_r2==3'b011;
always @(posedge clk)
div_by_zero_o1 <= #1 1'b0;
// output register
always @(posedge clk)
begin
qnan <= #1 qnan_o1;
out <= #1 out_o1;
inf <= #1 inf_o1;
snan <= #1 snan_o1;
//qnan <= #1 qnan_o1;
ine <= #1 ine_o1;
overflow <= #1 overflow_o1;
underflow <= #1 underflow_o1;
zero <= #1 zero_o1;
div_by_zero <= #1 div_by_zero_o1;
end
endmodule
//---------------------------------------------------------------------------------
module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out,
fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign,
fasu_op);
input clk;
input [1:0] rmode;
input add;
input [31:0] opa, opb;
input opa_nan, opb_nan;
output [26:0] fracta_out, fractb_out;
output [7:0] exp_dn_out;
output sign;
output nan_sign, result_zero_sign;
output fasu_op; // Operation Output
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire signa, signb; // alias to opX sign
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
wire expa_lt_expb; // expa is larger than expb indicator
wire fractb_lt_fracta; // fractb is larger than fracta indicator
reg [7:0] exp_dn_out; // de normalized exponent output
wire [7:0] exp_small, exp_large;
wire [7:0] exp_diff; // Numeric difference of the two exponents
wire [22:0] adj_op; // Fraction adjustment: input
wire [26:0] adj_op_tmp;
wire [26:0] adj_op_out; // Fraction adjustment: output
wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing
wire [26:0] fracta_s, fractb_s; // Fraction Sorting out
reg [26:0] fracta_out, fractb_out; // Fraction Output
reg sign, sign_d; // Sign Output
reg add_d; // operation (add/sub)
reg fasu_op; // operation (add/sub) register
wire expa_dn, expb_dn;
reg sticky;
reg result_zero_sign;
reg add_r, signa_r, signb_r;
wire [4:0] exp_diff_sft;
wire exp_lt_27;
wire op_dn;
wire [26:0] adj_op_out_sft;
reg fracta_lt_fractb, fracta_eq_fractb;
wire nan_sign1;
reg nan_sign;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign signa = opa[31];
assign signb = opb[31];
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize exponents (and fractions)
//
assign expa_lt_expb = expa > expb; // expa is larger than expb
// ---------------------------------------------------------------------
// Normalize
assign expa_dn = !(|expa); // opa denormalized
assign expb_dn = !(|expb); // opb denormalized
// ---------------------------------------------------------------------
// Calculate the difference between the smaller and larger exponent
wire [7:0] exp_diff1, exp_diff1a, exp_diff2;
assign exp_small = expa_lt_expb ? expb : expa;
assign exp_large = expa_lt_expb ? expa : expb;
assign exp_diff1 = exp_large - exp_small;
assign exp_diff1a = exp_diff1-8'h01;
assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1;
assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2;
always @(posedge clk) // If numbers are equal we should return zero
exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large;
// ---------------------------------------------------------------------
// Adjust the smaller fraction
assign op_dn = expa_lt_expb ? expb_dn : expa_dn;
assign adj_op = expa_lt_expb ? fractb : fracta;
wire temp1;
assign temp1 = ~op_dn;
//assign adj_op_tmp[26:0] = {~op_dn, adj_op, 3'b000}; // recover hidden bit (op_dn)
assign adj_op_tmp[26:0] = {temp1, adj_op, 3'b000}; // recover hidden bit (op_dn)
// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right
assign exp_lt_27 = exp_diff > 8'd27;
assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0];
//assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft;
b_right_shifter_new u7(
.shift_in(adj_op_tmp),
.shift_value(exp_diff_sft),
.shift_out(adj_op_out_sft)
);
wire temp2;
assign temp2 = adj_op_out_sft[0] | sticky;
//assign adj_op_out[26:0] = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky };
assign adj_op_out[26:0] = {adj_op_out_sft[26:1], temp2 };
// ---------------------------------------------------------------------
// Get truncated portion (sticky bit)
always @(exp_diff_sft or adj_op_tmp)
case(exp_diff_sft) // synopsys full_case parallel_case
5'd00: sticky = 1'h0;
5'd01: sticky = adj_op_tmp[0];
5'd02: sticky = |adj_op_tmp[01:0];
5'd03: sticky = |adj_op_tmp[02:0];
5'd04: sticky = |adj_op_tmp[03:0];
5'd05: sticky = |adj_op_tmp[04:0];
5'd06: sticky = |adj_op_tmp[05:0];
5'd07: sticky = |adj_op_tmp[06:0];
5'd08: sticky = |adj_op_tmp[07:0];
5'd09: sticky = |adj_op_tmp[08:0];
5'd10: sticky = |adj_op_tmp[09:0];
5'd11: sticky = |adj_op_tmp[10:0];
5'd12: sticky = |adj_op_tmp[11:0];
5'd13: sticky = |adj_op_tmp[12:0];
5'd14: sticky = |adj_op_tmp[13:0];
5'd15: sticky = |adj_op_tmp[14:0];
5'd16: sticky = |adj_op_tmp[15:0];
5'd17: sticky = |adj_op_tmp[16:0];
5'd18: sticky = |adj_op_tmp[17:0];
5'd19: sticky = |adj_op_tmp[18:0];
5'd20: sticky = |adj_op_tmp[19:0];
5'd21: sticky = |adj_op_tmp[20:0];
5'd22: sticky = |adj_op_tmp[21:0];
5'd23: sticky = |adj_op_tmp[22:0];
5'd24: sticky = |adj_op_tmp[23:0];
5'd25: sticky = |adj_op_tmp[24:0];
5'd26: sticky = |adj_op_tmp[25:0];
5'd27: sticky = |adj_op_tmp[26:0];
endcase
// ---------------------------------------------------------------------
// Select operands for add/sub (recover hidden bit)
assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out;
assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0};
// ---------------------------------------------------------------------
// Sort operands (for sub only)
assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta
assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n;
assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n;
always @(posedge clk)
fracta_out <= #1 fracta_s;
always @(posedge clk)
fractb_out <= #1 fractb_s;
// ---------------------------------------------------------------------
// Determine sign for the output
// sign: 0=Positive Number; 1=Negative Number
always @(signa or signb or add or fractb_lt_fracta)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b001: sign_d = 0;
3'b011: sign_d = fractb_lt_fracta;
3'b101: sign_d = !fractb_lt_fracta;
3'b111: sign_d = 1;
// Sub
3'b000: sign_d = fractb_lt_fracta;
3'b010: sign_d = 0;
3'b100: sign_d = 1;
3'b110: sign_d = !fractb_lt_fracta;
endcase
always @(posedge clk)
sign <= #1 sign_d;
// Fix sign for ZERO result
always @(posedge clk)
signa_r <= #1 signa;
always @(posedge clk)
signb_r <= #1 signb;
always @(posedge clk)
add_r <= #1 add;
always @(posedge clk)
result_zero_sign <= #1 ( add_r & signa_r & signb_r) |
(!add_r & signa_r & !signb_r) |
( add_r & (signa_r | signb_r) & (rmode==3)) |
(!add_r & (signa_r == signb_r) & (rmode==3));
// Fix sign for NAN result
always @(posedge clk)
fracta_lt_fractb <= #1 fracta < fractb;
always @(posedge clk)
fracta_eq_fractb <= #1 fracta == fractb;
assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r;
always @(posedge clk)
nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r;
////////////////////////////////////////////////////////////////////////
//
// Decode Add/Sub operation
//
// add: 1=Add; 0=Subtract
always @(signa or signb or add)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b001: add_d = 1;
3'b011: add_d = 0;
3'b101: add_d = 0;
3'b111: add_d = 1;
// Sub
3'b000: add_d = 0;
3'b010: add_d = 1;
3'b100: add_d = 1;
3'b110: add_d = 0;
endcase
always @(posedge clk)
fasu_op <= #1 add_d;
endmodule
module b_right_shifter_new (
shift_in,
shift_value,
shift_out
);
input [26:0] shift_in;
input [4:0] shift_value;
output [26:0] shift_out;
reg [47:0] shift_out;
always @(shift_value)
begin
case (shift_value)
5'b00000: shift_out = shift_in;
5'b00001: shift_out = shift_in >> 1;
5'b00010: shift_out = shift_in >> 2;
5'b00011: shift_out = shift_in >> 3;
5'b00100: shift_out = shift_in >> 4;
5'b00101: shift_out = shift_in >> 5;
5'b00110: shift_out = shift_in >> 6;
5'b00111: shift_out = shift_in >> 7;
5'b01000: shift_out = shift_in >> 8;
5'b01001: shift_out = shift_in >> 9;
5'b01010: shift_out = shift_in >> 10;
5'b01011: shift_out = shift_in >> 11;
5'b01100: shift_out = shift_in >> 12;
5'b01101: shift_out = shift_in >> 13;
5'b01110: shift_out = shift_in >> 14;
5'b01111: shift_out = shift_in >> 15;
5'b10000: shift_out = shift_in >> 16;
5'b10001: shift_out = shift_in >> 17;
5'b10010: shift_out = shift_in >> 18;
5'b10011: shift_out = shift_in >> 19;
5'b10100: shift_out = shift_in >> 20;
5'b10101: shift_out = shift_in >> 21;
5'b10110: shift_out = shift_in >> 22;
5'b10111: shift_out = shift_in >> 23;
5'b11000: shift_out = shift_in >> 24;
5'b11001: shift_out = shift_in >> 25;
5'b11010: shift_out = shift_in >> 26;
5'b11011: shift_out = shift_in >> 27;
endcase
end
endmodule
//----------------------------------------------------------------------------
////////////////////////////////////////////////////////////////////////
//
// Add/Sub
//
module add_sub27(add, opa, opb, sum, co);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_clgen.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [3:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [3:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {4{1'b0}};
assign cnt_one = cnt == {{3{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {4{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{3{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_4_V
`define SKY130_FD_SC_LS__INV_4_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_4_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:45:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_transform_0_0/system_vga_transform_0_0_stub.v
// Design : system_vga_transform_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_transform,Vivado 2016.4" *)
module system_vga_transform_0_0(clk, enable, x_addr_in, y_addr_in, rot_m00,
rot_m01, rot_m10, rot_m11, t_x, t_y, x_addr_out, y_addr_out)
/* synthesis syn_black_box black_box_pad_pin="clk,enable,x_addr_in[9:0],y_addr_in[9:0],rot_m00[15:0],rot_m01[15:0],rot_m10[15:0],rot_m11[15:0],t_x[9:0],t_y[9:0],x_addr_out[9:0],y_addr_out[9:0]" */;
input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
parameter rst_value = 0;
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
generate if (rst_value == 0)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
endgenerate
generate if (rst_value == 1)
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b1;
else
din_s1 <= din;
end
endgenerate
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate if (rst_value == 0)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
generate if (rst_value == 1)
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b1}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
module paddle_control(
input clock, reset, enable, rotary_event, rotary_right,
input [4:0] speed,
input [5:0] radius,
input middle,
output reg [9:0] paddle_x, paddle_y
);
localparam PD_H = 8;
localparam MAXX = 320;
localparam MAXY = 480;
localparam LEFT = 160;
localparam TOP = 0;
reg [9:0] next_x, next_y;
always @(*)
begin
if (middle)
paddle_y = TOP+MAXY/2-PD_H;
else
paddle_y = TOP+MAXY-PD_H;
end
always @(posedge clock)
begin
if (reset) begin
paddle_x <= LEFT + MAXX/2;
end else begin
paddle_x <= next_x;
end
end
always @(*)
begin
if (enable && rotary_event) begin
if (rotary_right) begin
if (paddle_x + radius + speed < LEFT + MAXX)
next_x = paddle_x + radius + speed;
else
next_x = LEFT + MAXX - radius;
end else begin
if (paddle_x > LEFT + radius + speed)
next_x = paddle_x - radius - speed;
else
next_x = LEFT + radius;
end
end else begin
if (paddle_x + radius >= LEFT + MAXX)
next_x = LEFT + MAXX - radius;
else if (paddle_x < LEFT + radius)
next_x = LEFT + radius;
else
next_x = paddle_x;
end
end
endmodule
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Claire Xenia Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module hx8kdemo (
input clk,
output ser_tx,
input ser_rx,
output [7:0] leds,
output flash_csb,
output flash_clk,
inout flash_io0,
inout flash_io1,
inout flash_io2,
inout flash_io3,
output debug_ser_tx,
output debug_ser_rx,
output debug_flash_csb,
output debug_flash_clk,
output debug_flash_io0,
output debug_flash_io1,
output debug_flash_io2,
output debug_flash_io3
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire flash_io0_oe, flash_io0_do, flash_io0_di;
wire flash_io1_oe, flash_io1_do, flash_io1_di;
wire flash_io2_oe, flash_io2_do, flash_io2_di;
wire flash_io3_oe, flash_io3_do, flash_io3_di;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 0)
) flash_io_buf [3:0] (
.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
);
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign leds = gpio;
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= gpio;
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc soc (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
assign debug_ser_tx = ser_tx;
assign debug_ser_rx = ser_rx;
assign debug_flash_csb = flash_csb;
assign debug_flash_clk = flash_clk;
assign debug_flash_io0 = flash_io0_di;
assign debug_flash_io1 = flash_io1_di;
assign debug_flash_io2 = flash_io2_di;
assign debug_flash_io3 = flash_io3_di;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module conbus_arb5(
input sys_clk,
input sys_rst,
input [4:0] req,
output [2:0] gnt
);
reg [2:0] state;
reg [2:0] next_state;
assign gnt = state;
always @(posedge sys_clk) begin
if(sys_rst)
state <= 3'd0;
else
state <= next_state;
end
always @(*) begin
next_state = state;
case(state)
3'd0: begin
if(~req[0]) begin
if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
end
end
3'd1: begin
if(~req[1]) begin
if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
end
end
3'd2: begin
if(~req[2]) begin
if(req[3]) next_state = 3'd3;
else if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
end
end
3'd3: begin
if(~req[3]) begin
if(req[4]) next_state = 3'd4;
else if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
end
end
3'd4: begin
if(~req[4]) begin
if(req[0]) next_state = 3'd0;
else if(req[1]) next_state = 3'd1;
else if(req[2]) next_state = 3'd2;
else if(req[3]) next_state = 3'd3;
end
end
endcase
end
endmodule
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module vita_tx_chain
#(parameter BASE=0,
parameter FIFOSIZE=10,
parameter POST_ENGINE_FIFOSIZE=10,
parameter REPORT_ERROR=0,
parameter DO_FLOW_CONTROL=0,
parameter PROT_ENG_FLAGS=0,
parameter USE_TRANS_HEADER=0,
parameter DSP_NUMBER=0)
(input clk, input reset,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
input [63:0] vita_time,
input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
output [31:0] sample, input strobe,
output underrun, output run, output clear_o,
output [31:0] debug);
localparam MAXCHAN = 1;
localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
wire [FIFOWIDTH-1:0] tx1_data;
wire tx1_src_rdy, tx1_dst_rdy;
wire [31:0] streamid, message;
wire trigger, sent;
wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
wire error, packet_consumed, ack;
wire [31:0] error_code;
wire clear_seqnum;
wire [31:0] current_seqnum;
wire clear, flush;
assign clear_o = clear;
assign underrun = error;
assign message = error_code;
setting_reg #(.my_addr(BASE+0), .width(1)) sr
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(flush),.changed(clear));
setting_reg #(.my_addr(BASE+2), .at_reset(0)) sr_streamid
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(streamid),.changed(clear_seqnum));
//flush control - full rate vacuum of input until flush cleared
wire tx_dst_rdy_int, tx_src_rdy_int;
wire [35:0] tx_data_int;
valve36 flusher_valve
(.clk(clk), .reset(reset), .clear(clear & flush), .shutoff(flush),
.data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
.data_o(tx_data_int), .src_rdy_o(tx_src_rdy_int), .dst_rdy_i(tx_dst_rdy_int));
wire [35:0] tx_data_int1;
wire tx_src_rdy_int1, tx_dst_rdy_int1;
generate
if (FIFOSIZE==0) begin
assign tx_data_int1 = tx_data_int;
assign tx_src_rdy_int1 = tx_src_rdy_int;
assign tx_dst_rdy_int = tx_dst_rdy_int1;
end
else begin
wire [FIFOSIZE-1:0] access_adr, access_len;
wire access_we, access_stb, access_ok, access_done, access_skip_read;
wire [35:0] dsp_to_buf, buf_to_dsp;
wire [35:0] tx_data_int0;
wire tx_src_rdy_int0, tx_dst_rdy_int0;
double_buffer #(.BUF_SIZE(FIFOSIZE)) db
(.clk(clk),.reset(reset),.clear(clear),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
.data_i(tx_data_int), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
.data_o(tx_data_int0), .src_rdy_o(tx_src_rdy_int0), .dst_rdy_i(tx_dst_rdy_int0));
vita_tx_engine_glue #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+1), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_tx
(.clock(clk),.reset(reset),.clear(clear),
.set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data),
.set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering(
.clk(clk), .reset(reset), .clear(clear),
.datain(tx_data_int0), .src_rdy_i(tx_src_rdy_int0), .dst_rdy_o(tx_dst_rdy_int0),
.dataout(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1));
end
endgenerate
vita_tx_deframer #(.BASE(BASE),
.MAXCHAN(MAXCHAN),
.USE_TRANS_HEADER(USE_TRANS_HEADER))
vita_tx_deframer
(.clk(clk), .reset(reset), .clear(clear), .clear_seqnum(clear_seqnum),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.data_i(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1),
.sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
.current_seqnum(current_seqnum),
.debug(debug_vtd) );
vita_tx_control #(.BASE(BASE), .WIDTH(32*MAXCHAN)) vita_tx_control
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code),
.sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
.sample(sample), .run(run), .strobe(strobe), .packet_consumed(packet_consumed),
.debug(debug_vtc) );
wire [35:0] flow_data, err_data_int;
wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int;
gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt
(.clk(clk), .reset(reset), .clear(clear),
.trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(),
.streamid(streamid), .vita_time(vita_time), .message(32'd0),
.seqnum(current_seqnum),
.data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy));
trigger_context_pkt #(.BASE(BASE)) trigger_context_pkt
(.clk(clk), .reset(reset), .clear(clear),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.packet_consumed(packet_consumed), .trigger(trigger));
gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt
(.clk(clk), .reset(reset), .clear(clear),
.trigger((error|ack) & (REPORT_ERROR==1)), .sent(),
.streamid(streamid), .vita_time(vita_time), .message(message),
.seqnum(current_seqnum),
.data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int));
assign debug = debug_vtc | debug_vtd;
fifo36_mux #(.prio(1)) mux_err_and_flow // Priority to err messages
(.clk(clk), .reset(reset), .clear(0), // Don't clear this or it could get clogged
.data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int),
.data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy),
.data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
endmodule // vita_tx_chain
|
module control (
start,
clk,
rst,
data,
data_out,
parameter_Block
parameter_Block2
);
input wire start;
input wire clk;
input wire rst;
input wire [63:0] data;
input wire [31:0] parameter_Block;
input wire [63:0] parameter_Block2;
output reg [63:0]data_out;
reg [7:0] bmRequestType ;
reg [7:0] bRequest ;
reg [11:0] count;
reg local;
reg global;
reg specific;
reg [7:0] debug_Unit_ID;
reg [7:0] interface_ID;
reg [15:0] wValue;
reg [15:0] wIndex;
reg [15:0] wLength;
reg [63:0] address;
reg [63:0] dato;
reg [3:0]state,next_state;
parameter [3:0]
IDLE = 4'b0001,
RECEIVE = 4'b0010,
SET = 4'b0011,
GET = 4'b0100,
DATA = 4'b0101,
HANDSHAKE = 4'b0110,
SETUP_TOKEN = 4'b0111,
OUT_TOKEN = 4'b1000,
IN_TOKEN = 4'b1001,
ACK_TOKEN = 4'b1010;
always @(posedge clk)
begin
case (state)
IDLE :
begin
if (start== 0 ) next_state = IDLE;
else
begin
next_state = RECEIVE;
bmRequestType = data [63:55];
bRequest = data [55:47];
wValue = data [48:33];
wIndex = data [32:16];
wLength = data [15:0];
end
end
RECEIVE :
begin
if (bmRequestType == 8'b00100001 )
begin
next_state = SET;
end
if (bmRequestType == 8'b00100001 )
begin
next_state = GET;
end
end
SET :
begin
if (bRequest == 8'h01 )//Set_config_data
begin
next_state = SET_CONFIG_DATA;
/*
if (wIndex[15:8] == 0)
begin
if (wValue[7:0] == 8'h00 ) // global DBclass
begin
global = 1 ;
ext_state = GET;
end
if (wValue[7:0] == 8'h01 ) // global vendor
begin
//Si lector este tamaño lo define usted
global = 1 ;
end
if (wValue[7:0] == 8'h02 ) // local DBclass
begin
local = 1 ;
//ask for inter face
end
if (wValue[7:0] == 8'h03 ) // local vendor
begin
//ask for inter face
//Si lector este tamaño lo define usted
//this is the espace to selec your own
local = 1 ;
end
end
if (wIndex[15:8] == 0)
begin
if (wValue[7:0] == 8'h00 )// specific DBclass
begin
specific = 1 ;
debug_Unit_ID = wIndex[15:8] ;
interface_ID = wIndex[7:0] ;
end
if (wValue[7:0] == 8'h01 ) // specific vendor
begin
//Si lector este tamaño lo define usted
debug_Unit_ID = wIndex[15:8] ;
interface_ID = wIndex[7:0] ;
specific = 1 ;
end */
end
end
if (bRequest == 8'h02 )//set_config_data_single
begin
next_state = SET_CONFIG_DATA_SINGLE;
end
if (bRequest == 8'h03 )//set_config_address
begin
next_state = SET_CONFIG_ADDRESS;
end
if (bRequest == 8'h04 )//set_alt_stack
begin
next_state = SET_ALT_STACK;
end
if (bRequest == 8'h05 )//set_operating_mode
begin
// this is for allow the trace ,dfx,ect modes
next_state = SET_OPERATING_MODE;
end
if (bRequest == 8'h06 )//set_trace
begin
next_state = SET_TRACE ;
// this is for allow the trace ,dfx,ect modes
end
if (bRequest == 8'h09 )//set_buffer
begin
next_state = SET_BUFFER ;
end
if (bRequest == 8'h0A )//set_rest
begin
next_state = SET_RESET;
end
end
GET :
begin
if (bRequest == 8'h81 ) //get_config data
begin
next_state = GET_CONFIG;
end
if (bRequest == 8'h82 ) //get_config data single
begin
next_state = GET_CONFIG_SINGLE;
end
if (bRequest == 8'h83 ) // get_config address
begin
next_state = GET_CONFIG_ADDRESS;
end
if (bRequest == 8'h84 ) // get_alt stack
begin
next_state = GET_ALT_STACK;
end
if (bRequest == 8'h85 ) //get oprating mode
begin
next_state = GET_OPERATION_MODE;
end
if (bRequest == 8'h86 ) //get_trace
begin
//this is no able
next_state = GET_TRACE;
end
if (bRequest == 8'h87 ) //get_INFO
begin
/*
bit support_capability
0 set_config data single
1 set config data
2 get config data
3 set config address
4 get config address
5 set alt stack
6 get alt stack
7 set operating mode
8 get operating mode
9 set trace configuration
10 get trace configuration
11 set buffer
12 get buffer
13 set reset
14-28 reseved set = 0
29 disable automatic mode
30 self generate control
31 slow control
*/
next_state = GET_INFO ;
end
if (bRequest == 8'h88 ) //get_error
begin
/*0x00: No error
0x01: Not ready
0x02: Wrong state
0x03: Insufficient Power Available
0x04: Max Power Violation
0x05: Operating-mode unavailable
0x06: Out of range
0x07: Invalid unit
0x08: Invalid control
0x09: Invalid Request
0x0A: Permission denied
0x0B-0xFE: reserved
0xFF: Unknown*/
end
if (bRequest == 8'h89 ) //get_buffer
begin
end
end
SET_CONFIG_DATA_SINGLE :
begin
end
SET_ALT_STACK :
begin
end
SET_OPERATING_MODE :
begin
end
SET_TRACE :
begin
end
SET_BUFFER :
begin
end
SET_RESET :
begin
end
GET_CONFIG :
begin
end
GET_CONFIG_SINGLE :
begin
end
GET_CONFIG_ADDRESS :
begin
end
GET_ALT_STACK :
begin
end
GET_OPERATION_MODE :
begin
end
GET_TRACE :
begin
end
GET_INFO :
begin
end
endcase
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:17:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: FxP_ABS_Function
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Fixed Point Absolute Value Function
//
// Input Data in Fixed Point Two's Complement Format
// Output Data is positive value integer
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module FxP_ABS_Function
#(
parameter DATA_WIDTH = 16
)
(
// Data Signals
input [DATA_WIDTH-1:0] DATA_IN,
output [DATA_WIDTH-1:0] DATA_ABS
);
//
// Two's Complement Absolute Function
//
// If the sign-bit (MSB) is high, then
// DATA_ABS = ~DATA_IN + 1'b1
// Else
// DATA_ABS = DATA_IN
//
assign DATA_ABS = DATA_IN[DATA_WIDTH-1] ? ~DATA_IN + 1'b1 : DATA_IN;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: tx_data_pipeline.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_data_fifo takes 0-bit aligned packet data and
// puts each DW into one of N FIFOs where N = (C_DATA_WIDTH/32).
//
// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
// its corresponding fifo contains the last dword of data for the current
// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
// and read by the READY signal.
//
// The write interface (WR_TX) differs slightly from the read interface because it
// produces a READY signal and consumes a VALID signal. VALID is asserted when an
// entire packet has been packed into a FIFO.
//
// TODO:
// - Make sure that the synthesis tool is removing the other three start
// flag wires (and modifying the width of the FIFOs)
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD = 256 // BYTES
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR TX DATA
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_VALID,
input WR_TX_DATA_START_FLAG,
input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_WORD_VALID,
input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_FLAGS,
output WR_TX_DATA_READY,
// Interface: RD TX DATA
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
output RD_TX_DATA_PACKET_VALID
);
localparam C_FIFO_OUTPUT_DEPTH = 1;
localparam C_INPUT_DEPTH = C_PIPELINE_INPUT != 0 ? 1 : 0;
localparam C_OUTPUT_DEPTH = C_PIPELINE_OUTPUT != 0 ? 1 : 0;
localparam C_MAXPACKET_LINES = (C_MAX_PAYLOAD*8)/C_DATA_WIDTH;
localparam C_FIFO_DEPTH = C_MAXPACKET_LINES*C_DEPTH_PACKETS;
localparam C_FIFO_DATA_WIDTH = 32;
localparam C_REGISTER_WIDTH = C_FIFO_DATA_WIDTH + 2;
localparam C_FIFO_WIDTH = C_FIFO_DATA_WIDTH + 2; // Data, end flag and start flag
localparam C_NUM_FIFOS = (C_DATA_WIDTH/32);
genvar i;
wire RST;
wire [C_FIFO_DATA_WIDTH-1:0] wWrTxData[C_NUM_FIFOS-1:0];
wire [C_NUM_FIFOS-1:0] wWrTxDataValid;
wire [C_NUM_FIFOS-1:0] wWrTxDataReady;
wire [C_NUM_FIFOS-1:0] wWrTxDataStartFlags;
wire [C_NUM_FIFOS-1:0] wWrTxDataEndFlags;
wire [C_NUM_FIFOS-1:0] _wRdTxDataStartFlags;
wire [C_FIFO_DATA_WIDTH-1:0] wRdTxData[C_NUM_FIFOS-1:0];
wire [C_NUM_FIFOS-1:0] wRdTxDataValid;
wire [C_NUM_FIFOS-1:0] wRdTxDataReady;
wire [C_NUM_FIFOS-1:0] wRdTxDataStartFlags;
wire [C_NUM_FIFOS-1:0] wRdTxDataEndFlags;
wire wRdTxDataPacketValid;
wire wWrTxEndFlagValid;
wire wWrTxEndFlagReady;
wire wRdTxEndFlagValid;
wire wRdTxEndFlagReady;
wire wPacketDecrement;
wire wPacketIncrement;
reg [clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter;
/*AUTOINPUT*/
/*AUTOWIRE*/
///*AUTOOUTPUT*/
assign RST = RST_IN;
assign wWrTxEndFlagValid = (wWrTxDataEndFlags & wWrTxDataValid) != {C_NUM_FIFOS{1'b0}};
assign wWrTxEndFlagReady = rPacketCounter != C_DEPTH_PACKETS;// Designed a small bit of latency here to help timing...
assign wPacketIncrement = wWrTxEndFlagValid & wWrTxEndFlagReady;
assign wPacketDecrement = wRdTxEndFlagValid & wRdTxEndFlagReady;
assign WR_TX_DATA_READY = wWrTxEndFlagReady;
assign wRdTxEndFlagValid = rPacketCounter != 0;
assign wRdTxEndFlagReady = (wRdTxDataReady & wRdTxDataEndFlags & wRdTxDataValid) != {C_NUM_FIFOS{1'b0}};
assign wRdTxDataPacketValid = rPacketCounter != 0;
assign RD_TX_DATA_START_FLAG = _wRdTxDataStartFlags[0];
always @(*) begin
_rPacketCounter = rPacketCounter;
if(wPacketIncrement & wPacketDecrement) begin
_rPacketCounter = rPacketCounter + 0;
end else if(wPacketIncrement) begin
_rPacketCounter = rPacketCounter + 1;
end else if(wPacketDecrement) begin
_rPacketCounter = rPacketCounter - 1;
end
end // always @ (*)
always @(posedge CLK) begin
if(RST_IN) begin
rPacketCounter <= #1 0;
end else begin
rPacketCounter <= #1 _rPacketCounter;
end
end
generate
for( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 ) begin : gen_regs_fifos
pipeline
#(
.C_DEPTH (C_INPUT_DEPTH),
.C_USE_MEMORY (0),
.C_WIDTH (C_REGISTER_WIDTH)
/*AUTOINSTPARAM*/)
input_pipeline_inst_
(
// Outputs
.WR_DATA_READY (),
.RD_DATA ({wWrTxData[i], wWrTxDataEndFlags[i],wWrTxDataStartFlags[i]}),
.RD_DATA_VALID (wWrTxDataValid[i]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA ({WR_TX_DATA[C_FIFO_DATA_WIDTH*i +: C_FIFO_DATA_WIDTH],
WR_TX_DATA_END_FLAGS[i], (i == 0) ? WR_TX_DATA_START_FLAG: 1'b0}),
.WR_DATA_VALID (WR_TX_DATA_VALID & WR_TX_DATA_WORD_VALID[i]),
.RD_DATA_READY (wWrTxDataReady[i]));
fifo
#(
// Parameters
.C_WIDTH (C_FIFO_WIDTH),
.C_DEPTH (C_FIFO_DEPTH),
.C_DELAY (0)
/*AUTOINSTPARAM*/)
fifo_inst_
(
// Outputs
.RD_DATA ({wRdTxData[i], wRdTxDataStartFlags[i], wRdTxDataEndFlags[i]}),
.WR_READY (wWrTxDataReady[i]),
.RD_VALID (wRdTxDataValid[i]),
// Inputs
.WR_DATA ({wWrTxData[i], wWrTxDataStartFlags[i], wWrTxDataEndFlags[i]}),
.WR_VALID (wWrTxDataValid[i]),
.RD_READY (wRdTxDataReady[i]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_FIFO_OUTPUT_DEPTH),
.C_USE_MEMORY (0),
.C_WIDTH (C_FIFO_WIDTH)
/*AUTOINSTPARAM*/)
fifo_pipeline_inst_
(
// Outputs
.WR_DATA_READY (wRdTxDataReady[i]),
.RD_DATA ({RD_TX_DATA[i*32 +: 32],
_wRdTxDataStartFlags[i],
RD_TX_DATA_END_FLAGS[i]}),
.RD_DATA_VALID (RD_TX_DATA_WORD_VALID[i]),
// Inputs
.WR_DATA ({wRdTxData[i],
wRdTxDataStartFlags[i],
wRdTxDataEndFlags[i]}),
.WR_DATA_VALID (wRdTxDataValid[i]),
.RD_DATA_READY (RD_TX_DATA_WORD_READY[i]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end // for ( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 )
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_auto_pc_3 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.i (O.4)
// \ \ Description :
// / /
// /__/ /\ Filename : PLLE2_BASE.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 12/09/09 - Initial version
// 03/23/10 - Change CLKFBOUT_MULT default from 1 to 5.
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE2_BASE (
CLKFBOUT,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 5;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE2_ADV #(
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.REF_JITTER1(REF_JITTER1)
)
plle2_adv_1 (
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
`endcelldefine
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
Each channel can use the full range of the DAC as they do not
get summed in the real chip.
Operator data is summed up without adding extra bits. This is
the case of real YM3438, which was used on Megadrive 2 models.
*/
// YM2610
// ADPCM inputs
// Full OP resolution
// No PCM
// 4 OP channels
// ADPCM-A input is added for the time assigned to FM channel 0_10 (i.e. 3)
module jt10_acc(
input clk,
input clk_en /* synthesis direct_enable */,
input signed [13:0] op_result,
input [ 1:0] rl,
input zero,
input s1_enters,
input s2_enters,
input s3_enters,
input s4_enters,
input [2:0] cur_ch,
input [1:0] cur_op,
input [2:0] alg,
input signed [15:0] adpcmA_l,
input signed [15:0] adpcmA_r,
input signed [15:0] adpcmB_l,
input signed [15:0] adpcmB_r,
// combined output
output signed [15:0] left,
output signed [15:0] right
);
reg sum_en;
always @(*) begin
case ( alg )
default: sum_en = s4_enters;
3'd4: sum_en = s2_enters | s4_enters;
3'd5,3'd6: sum_en = ~s1_enters;
3'd7: sum_en = 1'b1;
endcase
end
wire left_en = rl[1];
wire right_en= rl[0];
wire signed [15:0] opext = { {2{op_result[13]}}, op_result };
reg signed [15:0] acc_input_l, acc_input_r;
reg acc_en_l, acc_en_r;
// YM2610 mode:
// uses channels 0 and 4 for ADPCM data, throwing away FM data for those channels
// reference: YM2610 Application Notes.
always @(*)
case( {cur_op,cur_ch} )
{2'd0,3'd0}: begin // ADPCM-A:
acc_input_l = (adpcmA_l <<< 2) + (adpcmA_l <<< 1);
acc_input_r = (adpcmA_r <<< 2) + (adpcmA_r <<< 1);
`ifndef NOMIX
acc_en_l = 1'b1;
acc_en_r = 1'b1;
`else
acc_en_l = 1'b0;
acc_en_r = 1'b0;
`endif
end
{2'd0,3'd4}: begin // ADPCM-B:
acc_input_l = adpcmB_l >>> 1; // Operator width is 14 bit, ADPCM-B is 16 bit
acc_input_r = adpcmB_r >>> 1; // accumulator width per input channel is 14 bit
`ifndef NOMIX
acc_en_l = 1'b1;
acc_en_r = 1'b1;
`else
acc_en_l = 1'b0;
acc_en_r = 1'b0;
`endif
end
default: begin
// Note by Jose Tejada:
// I don't think we should divide down the FM output
// but someone was looking at the balance of the different
// channels and made this arrangement
// I suppose ADPCM-A would saturate if taken up a factor of 8 instead of 4
// I'll leave it as it is but I think it is worth revisiting this:
acc_input_l = opext >>> 1;
acc_input_r = opext >>> 1;
acc_en_l = sum_en & left_en;
acc_en_r = sum_en & right_en;
end
endcase
// Continuous output
jt12_single_acc #(.win(16),.wout(16)) u_left(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input_l ),
.sum_en ( acc_en_l ),
.zero ( zero ),
.snd ( left )
);
jt12_single_acc #(.win(16),.wout(16)) u_right(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input_r ),
.sum_en ( acc_en_r ),
.zero ( zero ),
.snd ( right )
);
`ifdef SIMULATION
// Dump each channel independently
// It dumps values in decimal, left and right
integer f0,f1,f2,f4,f5,f6;
reg signed [15:0] sum_l[7], sum_r[7];
initial begin
f0=$fopen("fm0.raw","w");
f1=$fopen("fm1.raw","w");
f2=$fopen("fm2.raw","w");
f4=$fopen("fm4.raw","w");
f5=$fopen("fm5.raw","w");
f6=$fopen("fm6.raw","w");
end
always @(posedge clk) begin
if(cur_op==2'b0) begin
sum_l[cur_ch] <= acc_en_l ? acc_input_l : 16'd0;
sum_r[cur_ch] <= acc_en_r ? acc_input_r : 16'd0;
end else begin
sum_l[cur_ch] <= sum_l[cur_ch] + (acc_en_l ? acc_input_l : 16'd0);
sum_r[cur_ch] <= sum_r[cur_ch] + (acc_en_r ? acc_input_r : 16'd0);
end
end
always @(posedge zero) begin
$fwrite(f0,"%d,%d\n", sum_l[0], sum_r[0]);
$fwrite(f1,"%d,%d\n", sum_l[1], sum_r[1]);
$fwrite(f2,"%d,%d\n", sum_l[2], sum_r[2]);
$fwrite(f4,"%d,%d\n", sum_l[4], sum_r[4]);
$fwrite(f5,"%d,%d\n", sum_l[5], sum_r[5]);
$fwrite(f6,"%d,%d\n", sum_l[6], sum_r[6]);
end
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
// Very simple test for interface pathclearing
`ifdef VCS
`define UNSUPPORTED_MOD_IN_GENS
`endif
`ifdef VERILATOR
`define UNSUPPORTED_MOD_IN_GENS
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itopa();
ifc #(2) itopb();
sub #(1) ca (.isub(itopa),
.i_value(4));
sub #(2) cb (.isub(itopb),
.i_value(5));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (itopa.MODE != 1) $stop;
if (itopb.MODE != 2) $stop;
end
if (cyc==20) begin
if (itopa.get_value() != 4) $stop;
if (itopb.get_value() != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
#(parameter MODE = 0)
(
ifc.out_modport isub,
input integer i_value
);
`ifdef UNSUPPORTED_MOD_IN_GENS
always @* isub.value = i_value;
`else
generate if (MODE == 1) begin
always @* isub.valuea = i_value;
end
else if (MODE == 2) begin
always @* isub.valueb = i_value;
end
endgenerate
`endif
endmodule
interface ifc;
parameter MODE = 0;
// Modports under generates not supported by all commercial simulators
`ifdef UNSUPPORTED_MOD_IN_GENS
integer value;
modport out_modport (output value);
function integer get_value(); return value; endfunction
`else
generate if (MODE == 0) begin
integer valuea;
modport out_modport (output valuea);
function integer get_valuea(); return valuea; endfunction
end
else begin
integer valueb;
modport out_modport (output valueb);
function integer get_valueb(); return valueb; endfunction
end
endgenerate
`endif
endinterface
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
// Copyright (c) 2000 Stephen Williams ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// This tests DFF-like behavior. The clocked always block acts like a
// DFF, and if the -Fsynth flag to ivl is used, actually generates an
// LPM_FF device.
module main () ;
reg clk;
reg D, Q;
always #10 clk = ~clk;
always @(posedge clk) Q = D;
initial begin
clk = 0;
D = 0;
@(negedge clk)
if (Q !== 1'b0)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 1;
@(negedge clk)
if (Q !== 1'b1)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 'bx;
@(negedge clk)
if (Q !== 1'bx)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
D = 'bz;
@(negedge clk)
if (Q !== 1'bz)
begin
$display("FAILED: %b !== %b", Q, D);
$finish;
end
$display("PASSED");
$finish;
end // initial begin
endmodule
|