text
stringlengths 992
1.04M
|
|---|
`timescale 1ns/10ps
module top;
reg pass;
reg [80*8:1] str;
reg [63:0] a, b, c;
real r;
integer code;
initial begin
pass = 1'b1;
// Check that a failing match stops the matching process.
str = "2 3";
code = $sscanf(str, "%b%d", a, b);
if (code !== 0) begin
$display("FAILED(mb) to stop matching found %d", code);
pass = 1'b0;
end
str = "8 3";
code = $sscanf(str, "%o%d", a, b);
if (code !== 0) begin
$display("FAILED(mo) to stop matching found %d", code);
pass = 1'b0;
end
str = "g 3";
code = $sscanf(str, "%h%d", a, b);
if (code !== 0) begin
$display("FAILED(mh) to stop matching found %d", code);
pass = 1'b0;
end
str = "g 3";
code = $sscanf(str, "%x%d", a, b);
if (code !== 0) begin
$display("FAILED(mx) to stop matching found %d", code);
pass = 1'b0;
end
str = "a 3";
code = $sscanf(str, "%d%d", a, b);
if (code !== 0) begin
$display("FAILED(md) to stop matching found %d", code);
pass = 1'b0;
end
// Check parsing all the binary values (%b).
str = "01_?xzXZ";
code = $sscanf(str, "%b", a);
if (code !== 1) begin
$display("FAILED(b) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'b01xxzxz) begin
$display("FAILED(b) argument value, expected 01xxzxz, got %b", a);
pass = 1'b0;
end
// Check that a leaading underscore is invalid.
a = 'bx;
str = "_01_?xzXZ";
code = $sscanf(str, "%b", a);
if (code !== 0) begin
$display("FAILED(bi) to parse zero argument found %d", code);
pass = 1'b0;
end
if (a !== 'bx) begin
$display("FAILED(bi) argument value, expected x, got %b", a);
pass = 1'b0;
end
// Check parsing all the octal values (%o).
str = "01234567_xzXZ?";
code = $sscanf(str, "%o", a);
if (code !== 1) begin
$display("FAILED(o) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 64'o01234567xzxzx) begin
$display("FAILED(o) argument value, expected 01234567xzxzx, got %o", a);
pass = 1'b0;
end
// Check that a leaading underscore is invalid.
a = 'bx;
str = "_01234567_xzXZ?";
code = $sscanf(str, "%o", a);
if (code !== 0) begin
$display("FAILED(oi) to parse zero argument found %d", code);
pass = 1'b0;
end
if (a !== 'ox) begin
$display("FAILED(oi) argument value, expected x, got %o", a);
pass = 1'b0;
end
// Check parsing all the decimal values (%d).
str = "+01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d1) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'd0123456789) begin
$display("FAILED(d1) argument value, expected 0123456789, got %d", a);
pass = 1'b0;
end
str = "01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d2) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'd0123456789) begin
$display("FAILED(d2) argument value, expected 0123456789, got %d", a);
pass = 1'b0;
end
str = "-01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d3) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== -'d0123456789) begin
$display("FAILED(d3) argument value, expected -0123456789, got %d", a);
pass = 1'b0;
end
str = "x";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d4) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(d4) argument value, expected x, got %d", a);
pass = 1'b0;
end
str = "X";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d5) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(d5) argument value, expected x, got %d", a);
pass = 1'b0;
end
str = "z";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d6) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'dz) begin
$display("FAILED(d6) argument value, expected z, got %d", a);
pass = 1'b0;
end
str = "Z";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d7) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'dz) begin
$display("FAILED(d7) argument value, expected z, got %d", a);
pass = 1'b0;
end
str = "?";
code = $sscanf(str, "%d", a);
if (code !== 1) begin
$display("FAILED(d8) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(d8) argument value, expected x, got %d", a);
pass = 1'b0;
end
// A plus or minus must have a digit after to match.
a = 'bx;
str = "-q";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(d9) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(d9) argument value, expected x, got %d", a);
pass = 1'b0;
end
a = 'bx;
str = "+q";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(d0) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(d0) argument value, expected x, got %d", a);
pass = 1'b0;
end
// Check that a leaading underscore is invalid.
a = 'dx;
str = "_01234_56789";
code = $sscanf(str, "%d", a);
if (code !== 0) begin
$display("FAILED(di) to parse zero argument found %d", code);
pass = 1'b0;
end
if (a !== 'dx) begin
$display("FAILED(di) argument value, expected x, got %d", a);
pass = 1'b0;
end
// Check parsing all the hex values (both %h and %x).
str = "0123456789_xzXZ?";
code = $sscanf(str, "%h", a);
if (code !== 1) begin
$display("FAILED(h1) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 64'h0123456789xzxzx) begin
$display("FAILED(h1) argument value, expected 0123456789xzxzx, got %h", a);
pass = 1'b0;
end
str = "aA_bB_cC_dD_eE_fF";
code = $sscanf(str, "%h", a);
if (code !== 1) begin
$display("FAILED(h2) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 64'haabbccddeeff) begin
$display("FAILED(h2) argument value, expected aabbccddeeff, got %h", a);
pass = 1'b0;
end
str = "0123456789_xzXZ?";
code = $sscanf(str, "%x", a);
if (code !== 1) begin
$display("FAILED(h3) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 64'h0123456789xzxzx) begin
$display("FAILED(h3) argument value, expected 0123456789xzxzx, got %h", a);
pass = 1'b0;
end
str = "aA_bB_cC_dD_eE_fF";
code = $sscanf(str, "%x", a);
if (code !== 1) begin
$display("FAILED(h4) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 64'haabbccddeeff) begin
$display("FAILED(h4) argument value, expected aabbccddeeff, got %h", a);
pass = 1'b0;
end
// Check that a leaading underscore is invalid.
a = 'dx;
str = "_0123456789_xzXZ?";
code = $sscanf(str, "%h", a);
if (code !== 0) begin
$display("FAILED(hi) to parse zero argument found %d", code);
pass = 1'b0;
end
if (a !== 'hx) begin
$display("FAILED(hi) argument value, expected x, got %h", a);
pass = 1'b0;
end
// Check parsing real values %f.
str = "+0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f1) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(f1) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f2) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(f2) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "-0123456789";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f3) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != -123456789.0) begin
$display("FAILED(f3) argument value, expected -123456789.0, got %f", r);
pass = 1'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f4) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f4) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f5) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f5) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f6) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f6) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f7) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(f7) argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
str = ".2";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f8) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(f8) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f9) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(f9) argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
str = "2.e-1";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f10) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(f10) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f11) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f11) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f12) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f12) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%f", r);
if (code !== 0) begin
$display("FAILED(f13) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(f13) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
str = "1e5000";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(f14) argument value, expected inf, got %f", r);
pass = 1'b0;
end
str = "-1e5000";
code = $sscanf(str, "%f", r);
if (code !== 1) begin
$display("FAILED(f14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(f14) argument value, expected -inf, got %f", r);
pass = 1'b0;
end
// Check parsing real values %e.
str = "+0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e1) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(e1) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e2) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(e2) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "-0123456789";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e3) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != -123456789.0) begin
$display("FAILED(e3) argument value, expected -123456789.0, got %f", r);
pass = 1'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e4) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e4) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e5) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e5) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e6) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e6) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e7) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(e7) argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
str = ".2";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e8) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(e8) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e9) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(e9) argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
str = "2.e-1";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e10) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(e10) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e11) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e11) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e12) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e12) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%e", r);
if (code !== 0) begin
$display("FAILED(e13) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(e13) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
str = "1e5000";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(e14) argument value, expected inf, got %f", r);
pass = 1'b0;
end
str = "-1e5000";
code = $sscanf(str, "%e", r);
if (code !== 1) begin
$display("FAILED(e14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(e14) argument value, expected -inf, got %f", r);
pass = 1'b0;
end
// Check parsing real values %g.
str = "+0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g1) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(g1) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g2) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.0) begin
$display("FAILED(g2) argument value, expected 123456789.0, got %f", r);
pass = 1'b0;
end
str = "-0123456789";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g3) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != -123456789.0) begin
$display("FAILED(g3) argument value, expected -123456789.0, got %f", r);
pass = 1'b0;
end
// A plus or minus must have a digit after to match.
r = 1.0;
str = "-q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g4) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g4) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "+q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g5) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g5) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "q";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g6) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g6) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
// Check starting/trailing decimal point.
str = "2.";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g7) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(g7) argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
str = ".2";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g8) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(g8) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check with an exponent.
str = "2.e1";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g9) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(g9) argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
str = "2.e-1";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g10) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 0.2) begin
$display("FAILED(g10) argument value, expected 0.2, got %f", r);
pass = 1'b0;
end
// Check failing exponent cases.
r = 1.0;
str = "2.ea";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g11) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g11) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e+a";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g12) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g12) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
r = 1.0;
str = "2.e-a";
code = $sscanf(str, "%g", r);
if (code !== 0) begin
$display("FAILED(g13) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0) begin
$display("FAILED(g13) argument value, expected 1.0, got %f", r);
pass = 1'b0;
end
str = "1e5000";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != 1.0/0.0) begin
$display("FAILED(g14) argument value, expected inf, got %f", r);
pass = 1'b0;
end
str = "-1e5000";
code = $sscanf(str, "%g", r);
if (code !== 1) begin
$display("FAILED(g14) to parse one arguments found %d", code);
pass = 1'b0;
end
if (r != -1.0/0.0) begin
$display("FAILED(g14) argument value, expected -inf, got %f", r);
pass = 1'b0;
end
// Check parsing time values (%t).
// The %t format uses the real code to parse the number so all the
// corner cases are tested above.
str = "+012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t1) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.25) begin
$display("FAILED(t1) argument value, expected 123456789.25, got %f", r);
pass = 1'b0;
end
str = "012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t2) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 123456789.25) begin
$display("FAILED(t2) argument value, expected 123456789.25, got %f", r);
pass = 1'b0;
end
str = "-012345678925";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t3) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != -123456789.25) begin
$display("FAILED(t3) argument value, expected -123456789.25, got %f", r);
pass = 1'b0;
end
// Check using different scaling and rounding.
$timeformat(-9, 3, "ns", 20);
str = "10.125";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t4) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 10.125) begin
$display("FAILED(t4) argument value, expected 10.125, got %f", r);
pass = 1'b0;
end
str = "10.0625";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t5) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 10.063) begin
$display("FAILED(t5) argument value, expected 10.063, got %f", r);
pass = 1'b0;
end
str = "10.03125";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t6) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 10.031) begin
$display("FAILED(t6) argument value, expected 10.031, got %f", r);
pass = 1'b0;
end
$timeformat(-9, 1, "ns", 20);
str = "10.543";
code = $sscanf(str, "%t", r);
if (code !== 1) begin
$display("FAILED(t7) to parse one argument found %d", code);
pass = 1'b0;
end
if (r != 10.5) begin
$display("FAILED(t7) argument value, expected 10.5, got %f", r);
pass = 1'b0;
end
// Check parsing a single character (%c).
str = "t";
code = $sscanf(str, "%c", a);
if (code !== 1) begin
$display("FAILED(c) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== 116) begin // t has an ASCII code of 116
$display("FAILED(c) argument value, expected t, got %c", a);
pass = 1'b0;
end
// Check parsing a string value (%s).
str = "hi ho";
code = $sscanf(str, "%s %s", a, b);
if (code !== 2) begin
$display("FAILED(s) to parse two arguments found %d", code);
pass = 1'b0;
end
if (a !== "hi") begin
$display("FAILED(s) first argument value, expected hi, got %s", a);
pass = 1'b0;
end
if (b !== "ho") begin
$display("FAILED(s) second argument value, expected ho, got %s", b);
pass = 1'b0;
end
// Check an empty %s match.
a = "skip";
str = " ";
code = $sscanf(str, "%s", a);
if (code !== 0) begin
$display("FAILED(ep) to parse zero arguments found %d", code);
pass = 1'b0;
end
if (a !== "skip") begin
$display("FAILED(ep) first argument value, expected skip, got %s", a);
pass = 1'b0;
end
// Check an empty %s second match.
b = "skip";
str = "one ";
code = $sscanf(str, "%s %s", a, b);
if (code !== 1) begin
$display("FAILED(es) to parse one arguments found %d", code);
pass = 1'b0;
end
if (a !== "one") begin
$display("FAILED(es) first argument value, expected one, got %s", a);
pass = 1'b0;
end
if (b !== "skip") begin
$display("FAILED(es) second argument value, expected skip, got %s", a);
pass = 1'b0;
end
// Check parsing 2 state unformatted binary values (%u).
// Check parsing 4 state unformatted binary values (%z).
// Check geting the current module (%m).
code = $sscanf(" ", "%m", a);
if (code !== 1) begin
$display("FAILED(m) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== "top") begin
$display("FAILED(m) first argument value, expected top, got %s", a);
pass = 1'b0;
end
// Check a string using a width.
str = "helloworld";
code = $sscanf(str, "%5s %s", a, b);
if (code !== 2) begin
$display("FAILED(sw) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== "hello") begin
$display("FAILED(sw) first argument value, expected hello, got %s", a);
pass = 1'b0;
end
if (b !== "world") begin
$display("FAILED(sw) second argument value, expected world, got %s", b);
pass = 1'b0;
end
// Check a binary using a width.
str = "01101001";
code = $sscanf(str, "%4b %b", a, b);
if (code !== 2) begin
$display("FAILED(bw) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'b0110) begin
$display("FAILED(bw) first argument value, expected 'b0110, got %b", a);
pass = 1'b0;
end
if (b !== 'b1001) begin
$display("FAILED(bw) second argument value, expected 'b1001, got %b", b);
pass = 1'b0;
end
// Check an octal using a width.
str = "234567";
code = $sscanf(str, "%3o %o", a, b);
if (code !== 2) begin
$display("FAILED(ow) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'o234) begin
$display("FAILED(ow) first argument value, expected 'o234, got %o", a);
pass = 1'b0;
end
if (b !== 'o567) begin
$display("FAILED(ow) second argument value, expected 'o567, got %o", b);
pass = 1'b0;
end
// Check a hex using a width.
str = "89abcdef";
code = $sscanf(str, "%4h %h", a, b);
if (code !== 2) begin
$display("FAILED(hw) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'h89ab) begin
$display("FAILED(hw) first argument value, expected 'h89ab, got %h", a);
pass = 1'b0;
end
if (b !== 'hcdef) begin
$display("FAILED(hw) second argument value, expected 'hcdef, got %h", b);
pass = 1'b0;
end
// Check a decimal using a width.
str = "23456789";
code = $sscanf(str, "%4d %d", a, b);
if (code !== 2) begin
$display("FAILED(dw) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(dw) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (b !== 'd6789) begin
$display("FAILED(dw) second argument value, expected 'd6789, got %d", b);
pass = 1'b0;
end
// Check a real using a width.
str = "-2.2566789";
code = $sscanf(str, "%6f %d", r, a);
if (code !== 2) begin
$display("FAILED(fw1) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != -2.256) begin
$display("FAILED(fw1) first argument value, expected 2.256, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(fw1) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6f %d", r, a);
if (code !== 2) begin
$display("FAILED(fw2) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(fw2) first argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(fw2) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "-2.2566789";
code = $sscanf(str, "%6e %d", r, a);
if (code !== 2) begin
$display("FAILED(ew1) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != -2.256) begin
$display("FAILED(ew1) first argument value, expected 2.256, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(ew1) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6e %d", r, a);
if (code !== 2) begin
$display("FAILED(ew2) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(ew2) first argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(ew2) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "-2.2566789";
code = $sscanf(str, "%6g %d", r, a);
if (code !== 2) begin
$display("FAILED(gw1) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != -2.256) begin
$display("FAILED(gw1) first argument value, expected 2.256, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(gw1) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6g %d", r, a);
if (code !== 2) begin
$display("FAILED(gw2) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(gw2) first argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(gw2) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
// Check a time using a width.
$timeformat(-9, 3, "ns", 20);
str = "-2.2566789";
code = $sscanf(str, "%6t %d", r, a);
if (code !== 2) begin
$display("FAILED(tw1) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != -2.256) begin
$display("FAILED(tw1) first argument value, expected 2.256, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(tw1) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
str = "+2.e+16789";
code = $sscanf(str, "%6t %d", r, a);
if (code !== 2) begin
$display("FAILED(tw2) to parse two argument found %d", code);
pass = 1'b0;
end
if (r != 20.0) begin
$display("FAILED(tw2) first argument value, expected 20.0, got %f", r);
pass = 1'b0;
end
if (a !== 'd6789) begin
$display("FAILED(tw2) second argument value, expected 'd6789, got %d", a);
pass = 1'b0;
end
// Check a suppressed string.
str = "hello bad world";
code = $sscanf(str, "%s %*s %s", a, b);
if (code !== 2) begin
$display("FAILED(ss) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== "hello") begin
$display("FAILED(sw) first argument value, expected hello, got %s", a);
pass = 1'b0;
end
if (b !== "world") begin
$display("FAILED(sw) second argument value, expected world, got %s", b);
pass = 1'b0;
end
// Check a suppressed binary.
str = "0110 xxz 1001";
code = $sscanf(str, "%b %*b %b", a, b);
if (code !== 2) begin
$display("FAILED(bs) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'b0110) begin
$display("FAILED(bs) first argument value, expected 'b0110, got %b", a);
pass = 1'b0;
end
if (b !== 'b1001) begin
$display("FAILED(bs) second argument value, expected 'b1001, got %b", b);
pass = 1'b0;
end
// Check a suppressed octal.
str = "234 xxz 567";
code = $sscanf(str, "%o %*o %o", a, b);
if (code !== 2) begin
$display("FAILED(os) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'o234) begin
$display("FAILED(os) first argument value, expected 'o234, got %o", a);
pass = 1'b0;
end
if (b !== 'o567) begin
$display("FAILED(os) second argument value, expected 'o567, got %o", b);
pass = 1'b0;
end
// Check a suppressed hex.
str = "89ab xz CDEF";
code = $sscanf(str, "%h %*h %h", a, b);
if (code !== 2) begin
$display("FAILED(hs) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'h89ab) begin
$display("FAILED(hs) first argument value, expected 'h89ab, got %h", a);
pass = 1'b0;
end
if (b !== 'hcdef) begin
$display("FAILED(hs) second argument value, expected 'hcdef, got %h", b);
pass = 1'b0;
end
// Check a suppressed decimal.
str = "2345 x 6789";
code = $sscanf(str, "%d %*d %d", a, b);
if (code !== 2) begin
$display("FAILED(ds) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(ds) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (b !== 'd6789) begin
$display("FAILED(ds) second argument value, expected 'd6789, got %d", b);
pass = 1'b0;
end
// Check a suppressed real.
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*f %f", a, r);
if (code !== 2) begin
$display("FAILED(fs) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(fs) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(fs) second argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*e %e", a, r);
if (code !== 2) begin
$display("FAILED(es) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(es) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(es) second argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*g %g", a, r);
if (code !== 2) begin
$display("FAILED(gs) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(gs) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(gs) second argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
// Check a suppressed time.
str = "2345 1.0 2.0";
code = $sscanf(str, "%d %*t %t", a, r);
if (code !== 2) begin
$display("FAILED(ts) to parse two argument found %d", code);
pass = 1'b0;
end
if (a !== 'd2345) begin
$display("FAILED(ts) first argument value, expected 'd2345, got %d", a);
pass = 1'b0;
end
if (r != 2.0) begin
$display("FAILED(ts) second argument value, expected 2.0, got %f", r);
pass = 1'b0;
end
// Check matching normal characters. Also check %%.
str = "test% str";
code = $sscanf(str, "test%% %s", a);
if (code !== 1) begin
$display("FAILED(nc) to parse one argument found %d", code);
pass = 1'b0;
end
if (a !== "str") begin
$display("FAILED(nc) first argument value, expected str, got %s", a);
pass = 1'b0;
end
// Check different spacing issues, tab, leading space, extra space, etc.
str = " one \t\n two ";
code = $sscanf(str, "%s %s", a, b);
if (code !== 2) begin
$display("FAILED(sp) to parse two arguments found %d", code);
pass = 1'b0;
end
if (a !== "one") begin
$display("FAILED(sp) first argument value, expected one, got %s", a);
pass = 1'b0;
end
if (b !== "two") begin
$display("FAILED(sp) second argument value, expected two, got %s", b);
pass = 1'b0;
end
// Check for a failing match.
a = 'bx;
b = 'bx;
str = "BAD";
code = $sscanf(str, "GOOD %s %s", a, b);
if (code !== 0) begin
$display("FAILED(fl) to parse bad match arguments found %d", code);
pass = 1'b0;
end
if (a !== 'bx) begin
$display("FAILED(fl) first argument value, expected 'bx, got %b", a);
pass = 1'b0;
end
if (b !== 'bx) begin
$display("FAILED(fl) second argument value, expected 'bx, got %b", b);
pass = 1'b0;
end
b = 'bx;
str = "a ";
// Check a failing character match at EOF.
code = $sscanf(str, "%s %c", a, b);
if (code !== 1) begin
$display("FAILED(fle) character at end, expected one found %d", code);
pass = 1'b0;
end
if (a !== "a") begin
$display("FAILED(fle) first argument value, expected a, got %s", a);
pass = 1'b0;
end
if (b !== 'bx) begin
$display("FAILED(fle) second argument value, expected 'bx, got %b", b);
pass = 1'b0;
end
// Check for no match.
a = 'bx;
b = 'bx;
str = "";
code = $sscanf(str, "GOOD %s %s", a, b);
if (code !== -1) begin
$display("FAILED(no) to parse no match arguments found %d", code);
pass = 1'b0;
end
if (a !== 'bx) begin
$display("FAILED(no) first argument value, expected 'bx, got %s", a);
pass = 1'b0;
end
if (b !== 'bx) begin
$display("FAILED(no) second argument value, expected 'bx, got %s", b);
pass = 1'b0;
end
// Check for an undefined conversion string.
a = 'bx;
str = "foo";
code = $sscanf(str, 'bx, a);
if (code !== -1) begin
$display("FAILED(udef) to parse undefined string returned %d", code);
pass = 1'b0;
end
if (a !== 'bx) begin
$display("FAILED(udef) first argument value, expected 'bx, got %s", a);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream RAM switch
*/
module axis_ram_switch #
(
// FIFO depth in words (each virtual FIFO)
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter FIFO_DEPTH = 4096,
// Command FIFO depth (each virtual FIFO)
// Rounded up to nearest power of 2
parameter CMD_FIFO_DEPTH = 32,
// Speedup factor (internal data width scaling factor)
// Speedup of 0 scales internal width to provide maximum bandwidth
parameter SPEEDUP = 0,
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of input AXI stream interfaces in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// input tid signal width
parameter S_ID_WIDTH = 8,
// output tid signal width
parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
// output tdest signal width
parameter M_DEST_WIDTH = 1,
// input tdest signal width
// must be wide enough to uniquely address outputs
parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(M_COUNT),
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames marked bad
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
parameter DROP_WHEN_FULL = 0,
// Output interface routing base tdest selection
// Concatenate M_COUNT S_DEST_WIDTH sized constants
// Port selected if M_BASE <= tdest <= M_TOP
// set to zero for default routing with tdest MSBs as port index
parameter M_BASE = 0,
// Output interface routing top tdest selection
// Concatenate M_COUNT S_DEST_WIDTH sized constants
// Port selected if M_BASE <= tdest <= M_TOP
// set to zero to inherit from M_BASE
parameter M_TOP = 0,
// Interface connection control
// M_COUNT concatenated fields of S_COUNT bits
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
// Update tid with routing information
parameter UPDATE_TID = 0,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 1,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1,
// RAM read data output pipeline stages
parameter RAM_PIPELINE = 2
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*S_DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
input wire [M_COUNT-1:0] m_axis_tready,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*M_ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*M_DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire [S_COUNT-1:0] status_overflow,
output wire [S_COUNT-1:0] status_bad_frame,
output wire [S_COUNT-1:0] status_good_frame
);
parameter CL_S_COUNT = $clog2(S_COUNT);
parameter CL_M_COUNT = $clog2(M_COUNT);
parameter S_ID_WIDTH_INT = S_ID_WIDTH > 0 ? S_ID_WIDTH : 1;
parameter M_DEST_WIDTH_INT = M_DEST_WIDTH > 0 ? M_DEST_WIDTH : 1;
// force keep width to 1 when disabled
parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
// bus word sizes (must be identical)
parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT;
parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT;
// total data and keep widths
parameter MIN_DATA_WIDTH = (M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT ? M_DATA_WIDTH : S_DATA_WIDTH);
parameter MIN_KEEP_WIDTH = (M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT);
// speedup factor
parameter M_TOTAL_DATA_WIDTH = M_DATA_WIDTH*M_COUNT;
parameter S_TOTAL_DATA_WIDTH = S_DATA_WIDTH*S_COUNT;
parameter SPEEDUP_INT = SPEEDUP > 0 ? SPEEDUP : (M_TOTAL_DATA_WIDTH > S_TOTAL_DATA_WIDTH ? (M_TOTAL_DATA_WIDTH / MIN_DATA_WIDTH) : (S_TOTAL_DATA_WIDTH / MIN_DATA_WIDTH));
parameter DATA_WIDTH = MIN_DATA_WIDTH*SPEEDUP_INT;
parameter KEEP_WIDTH = MIN_KEEP_WIDTH*SPEEDUP_INT;
parameter ADDR_WIDTH = $clog2(FIFO_DEPTH/KEEP_WIDTH);
parameter RAM_ADDR_WIDTH = $clog2(S_COUNT*FIFO_DEPTH/KEEP_WIDTH);
parameter CMD_ADDR_WIDTH = $clog2(CMD_FIFO_DEPTH);
integer i, j;
// check configuration
initial begin
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
$error("Error: input data width not evenly divisble (instance %m)");
$finish;
end
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
$error("Error: output data width not evenly divisble (instance %m)");
$finish;
end
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
if (S_DEST_WIDTH < CL_M_COUNT) begin
$error("Error: S_DEST_WIDTH too small for port count (instance %m)");
$finish;
end
if (UPDATE_TID) begin
if (!ID_ENABLE) begin
$error("Error: UPDATE_TID set requires ID_ENABLE set (instance %m)");
$finish;
end
if (M_ID_WIDTH < CL_S_COUNT) begin
$error("Error: M_ID_WIDTH too small for port count (instance %m)");
$finish;
end
end
if (M_BASE == 0) begin
// M_BASE is zero, route with tdest as port index
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, i << (S_DEST_WIDTH-CL_M_COUNT), ((i+1) << (S_DEST_WIDTH-CL_M_COUNT))-1, M_CONNECT[i*S_COUNT +: S_COUNT]);
end
end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end
for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = i+1; j < M_COUNT; j = j + 1) begin
if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] == M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]) begin
$display("%d: %08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH]);
$display("%d: %08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH]);
$error("Error: ranges overlap (instance %m)");
$finish;
end
end
end
end else begin
$display("Addressing configuration for axis_switch instance %m");
for (i = 0; i < M_COUNT; i = i + 1) begin
$display("%d: %08x-%08x (connect mask %b)", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_CONNECT[i*S_COUNT +: S_COUNT]);
end
for (i = 0; i < M_COUNT; i = i + 1) begin
if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] > M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin
$error("Error: invalid range (instance %m)");
$finish;
end
end
for (i = 0; i < M_COUNT; i = i + 1) begin
for (j = i+1; j < M_COUNT; j = j + 1) begin
if (M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH] && M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH] <= M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]) begin
$display("%d: %08x-%08x", i, M_BASE[i*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[i*S_DEST_WIDTH +: S_DEST_WIDTH]);
$display("%d: %08x-%08x", j, M_BASE[j*S_DEST_WIDTH +: S_DEST_WIDTH], M_TOP[j*S_DEST_WIDTH +: S_DEST_WIDTH]);
$error("Error: ranges overlap (instance %m)");
$finish;
end
end
end
end
end
// Shared RAM
reg [DATA_WIDTH-1:0] mem[(2**RAM_ADDR_WIDTH)-1:0];
reg [DATA_WIDTH-1:0] mem_read_data_reg[RAM_PIPELINE-1:0];
reg [M_COUNT-1:0] mem_read_data_valid_reg[RAM_PIPELINE-1:0];
wire [S_COUNT*DATA_WIDTH-1:0] port_ram_wr_data;
wire [S_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_wr_addr;
wire [S_COUNT-1:0] port_ram_wr_en;
wire [S_COUNT-1:0] port_ram_wr_ack;
wire [M_COUNT*RAM_ADDR_WIDTH-1:0] port_ram_rd_addr;
wire [M_COUNT-1:0] port_ram_rd_en;
wire [M_COUNT-1:0] port_ram_rd_ack;
wire [M_COUNT*DATA_WIDTH-1:0] port_ram_rd_data;
wire [M_COUNT-1:0] port_ram_rd_data_valid;
assign port_ram_rd_data = {M_COUNT{mem_read_data_reg[RAM_PIPELINE-1]}};
assign port_ram_rd_data_valid = mem_read_data_valid_reg[RAM_PIPELINE-1];
wire [CL_S_COUNT-1:0] ram_wr_sel;
wire ram_wr_en;
wire [CL_M_COUNT-1:0] ram_rd_sel;
wire ram_rd_en;
generate
if (S_COUNT > 1) begin
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ram_write_arb_inst (
.clk(clk),
.rst(rst),
.request(port_ram_wr_en & ~port_ram_wr_ack),
.acknowledge({S_COUNT{1'b0}}),
.grant(port_ram_wr_ack),
.grant_valid(ram_wr_en),
.grant_encoded(ram_wr_sel)
);
end else begin
assign ram_wr_en = port_ram_wr_en;
assign port_ram_wr_ack = port_ram_wr_en;
assign ram_wr_sel = 0;
end
endgenerate
always @(posedge clk) begin
if (ram_wr_en) begin
mem[port_ram_wr_addr[ram_wr_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]] <= port_ram_wr_data[ram_wr_sel*DATA_WIDTH +: DATA_WIDTH];
end
end
generate
if (M_COUNT > 1) begin
arbiter #(
.PORTS(M_COUNT),
.ARB_TYPE_ROUND_ROBIN(1),
.ARB_BLOCK(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ram_read_arb_inst (
.clk(clk),
.rst(rst),
.request(port_ram_rd_en & ~port_ram_rd_ack),
.acknowledge({M_COUNT{1'b0}}),
.grant(port_ram_rd_ack),
.grant_valid(ram_rd_en),
.grant_encoded(ram_rd_sel)
);
end else begin
assign ram_rd_en = port_ram_rd_en;
assign port_ram_rd_ack = port_ram_rd_en;
assign ram_rd_sel = 0;
end
endgenerate
integer s;
always @(posedge clk) begin
mem_read_data_valid_reg[0] <= 0;
for (s = RAM_PIPELINE-1; s > 0; s = s - 1) begin
mem_read_data_reg[s] <= mem_read_data_reg[s-1];
mem_read_data_valid_reg[s] <= mem_read_data_valid_reg[s-1];
end
if (ram_rd_en) begin
mem_read_data_reg[0] <= mem[port_ram_rd_addr[ram_rd_sel*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]];
mem_read_data_valid_reg[0] <= 1 << ram_rd_sel;
end
if (rst) begin
mem_read_data_valid_reg[0] <= 0;
for (s = 0; s < RAM_PIPELINE; s = s + 1) begin
mem_read_data_valid_reg[s] <= 0;
end
end
end
// Interconnect
wire [S_COUNT*RAM_ADDR_WIDTH-1:0] int_cmd_addr;
wire [S_COUNT*ADDR_WIDTH-1:0] int_cmd_len;
wire [S_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_id;
wire [S_COUNT*KEEP_WIDTH-1:0] int_cmd_tkeep;
wire [S_COUNT*S_ID_WIDTH-1:0] int_cmd_tid;
wire [S_COUNT*S_DEST_WIDTH-1:0] int_cmd_tdest;
wire [S_COUNT*USER_WIDTH-1:0] int_cmd_tuser;
wire [S_COUNT*M_COUNT-1:0] int_cmd_valid;
wire [M_COUNT*S_COUNT-1:0] int_cmd_ready;
wire [M_COUNT*CMD_ADDR_WIDTH-1:0] int_cmd_status_id;
wire [M_COUNT*S_COUNT-1:0] int_cmd_status_valid;
wire [S_COUNT*M_COUNT-1:0] int_cmd_status_ready;
generate
genvar m, n;
for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
wire [DATA_WIDTH-1:0] port_axis_tdata;
wire [KEEP_WIDTH-1:0] port_axis_tkeep;
wire port_axis_tvalid;
wire port_axis_tready;
wire port_axis_tlast;
wire [S_ID_WIDTH-1:0] port_axis_tid;
wire [S_DEST_WIDTH-1:0] port_axis_tdest;
wire [USER_WIDTH-1:0] port_axis_tuser;
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE && S_ID_WIDTH > 0),
.ID_WIDTH(S_ID_WIDTH_INT),
.DEST_ENABLE(1),
.DEST_WIDTH(S_DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata[S_DATA_WIDTH*m +: S_DATA_WIDTH]),
.s_axis_tkeep(s_axis_tkeep[S_KEEP_WIDTH*m +: S_KEEP_WIDTH]),
.s_axis_tvalid(s_axis_tvalid[m]),
.s_axis_tready(s_axis_tready[m]),
.s_axis_tlast(s_axis_tlast[m]),
.s_axis_tid(s_axis_tid[S_ID_WIDTH*m +: S_ID_WIDTH_INT]),
.s_axis_tdest(s_axis_tdest[S_DEST_WIDTH*m +: S_DEST_WIDTH]),
.s_axis_tuser(s_axis_tuser[USER_WIDTH*m +: USER_WIDTH]),
// AXI output
.m_axis_tdata(port_axis_tdata),
.m_axis_tkeep(port_axis_tkeep),
.m_axis_tvalid(port_axis_tvalid),
.m_axis_tready(port_axis_tready),
.m_axis_tlast(port_axis_tlast),
.m_axis_tid(port_axis_tid),
.m_axis_tdest(port_axis_tdest),
.m_axis_tuser(port_axis_tuser)
);
// decoding
reg [CL_M_COUNT-1:0] select_reg = 0, select_next;
reg drop_reg = 1'b0, drop_next;
reg select_valid_reg = 1'b0, select_valid_next;
integer k;
always @* begin
select_next = select_reg;
drop_next = drop_reg && !(port_axis_tvalid && port_axis_tready && port_axis_tlast);
select_valid_next = select_valid_reg && !(port_axis_tvalid && port_axis_tready && port_axis_tlast);
if (port_axis_tvalid && !select_valid_reg && !drop_reg) begin
select_next = 0;
select_valid_next = 1'b0;
drop_next = 1'b1;
for (k = 0; k < M_COUNT; k = k + 1) begin
if (M_BASE == 0) begin
if (M_COUNT == 1) begin
// M_BASE is zero with only one output port, ignore tdest
select_next = 0;
select_valid_next = 1'b1;
drop_next = 1'b0;
end else begin
// M_BASE is zero, route with $clog2(M_COUNT) MSBs of tdest as port index
if (port_axis_tdest[S_DEST_WIDTH-CL_M_COUNT +: CL_M_COUNT] == k && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end
end else if (M_TOP == 0) begin
// M_TOP is zero, assume equal to M_BASE
if (port_axis_tdest == M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end else begin
if (port_axis_tdest >= M_BASE[k*S_DEST_WIDTH +: S_DEST_WIDTH] && port_axis_tdest <= M_TOP[k*S_DEST_WIDTH +: S_DEST_WIDTH] && (M_CONNECT & (1 << (m+k*S_COUNT)))) begin
select_next = k;
select_valid_next = 1'b1;
drop_next = 1'b0;
end
end
end
end
end
always @(posedge clk) begin
select_reg <= select_next;
drop_reg <= drop_next;
select_valid_reg <= select_valid_next;
if (rst) begin
select_valid_reg <= 1'b0;
end
end
// status arbitration
wire [M_COUNT-1:0] request;
wire [M_COUNT-1:0] acknowledge;
wire [M_COUNT-1:0] grant;
wire grant_valid;
wire [CL_M_COUNT-1:0] grant_encoded;
arbiter #(
.PORTS(M_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
cmd_status_arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
// mux
wire [CMD_ADDR_WIDTH-1:0] cmd_status_id_mux = int_cmd_status_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH];
wire cmd_status_valid_mux = int_cmd_status_valid[grant_encoded*S_COUNT+m] && grant_valid;
wire cmd_status_ready_mux;
assign int_cmd_status_ready[m*M_COUNT +: M_COUNT] = (grant_valid && cmd_status_ready_mux) << grant_encoded;
for (n = 0; n < M_COUNT; n = n + 1) begin
assign request[n] = int_cmd_status_valid[m+n*S_COUNT] && !grant[n];
assign acknowledge[n] = grant[n] && int_cmd_status_valid[m+n*S_COUNT] && cmd_status_ready_mux;
end
reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next;
reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH-1:0] len_reg = {ADDR_WIDTH{1'b0}}, len_next;
// full when first MSB different but rest same
wire full = wr_ptr_cur_reg == (rd_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
// empty when pointers match exactly
wire empty = wr_ptr_reg == rd_ptr_reg;
// overflow within packet
wire full_wr = wr_ptr_cur_reg == (wr_ptr_reg ^ {1'b1, {ADDR_WIDTH{1'b0}}});
reg drop_frame_reg = 1'b0, drop_frame_next;
reg overflow_reg = 1'b0, overflow_next;
reg bad_frame_reg = 1'b0, bad_frame_next;
reg good_frame_reg = 1'b0, good_frame_next;
reg [DATA_WIDTH-1:0] ram_wr_data_reg = {DATA_WIDTH{1'b0}}, ram_wr_data_next;
reg [ADDR_WIDTH-1:0] ram_wr_addr_reg = {ADDR_WIDTH{1'b0}}, ram_wr_addr_next;
reg ram_wr_en_reg = 1'b0, ram_wr_en_next;
wire ram_wr_ack;
reg [2**CMD_ADDR_WIDTH-1:0] cmd_table_active = 0;
reg [2**CMD_ADDR_WIDTH-1:0] cmd_table_commit = 0;
reg [RAM_ADDR_WIDTH+1-1:0] cmd_table_addr_start[2**CMD_ADDR_WIDTH-1:0];
reg [RAM_ADDR_WIDTH+1-1:0] cmd_table_addr_end[2**CMD_ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] cmd_table_len[2**CMD_ADDR_WIDTH-1:0];
reg [CL_M_COUNT-1:0] cmd_table_select[2**CMD_ADDR_WIDTH-1:0];
reg [KEEP_WIDTH-1:0] cmd_table_tkeep[2**CMD_ADDR_WIDTH-1:0];
reg [S_ID_WIDTH-1:0] cmd_table_tid[2**CMD_ADDR_WIDTH-1:0];
reg [S_DEST_WIDTH-1:0] cmd_table_tdest[2**CMD_ADDR_WIDTH-1:0];
reg [USER_WIDTH-1:0] cmd_table_tuser[2**CMD_ADDR_WIDTH-1:0];
reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_start_ptr_reg = 0;
reg [RAM_ADDR_WIDTH+1-1:0] cmd_table_start_addr_start;
reg [RAM_ADDR_WIDTH+1-1:0] cmd_table_start_addr_end;
reg [ADDR_WIDTH-1:0] cmd_table_start_len;
reg [CL_M_COUNT-1:0] cmd_table_start_select;
reg [KEEP_WIDTH-1:0] cmd_table_start_tkeep;
reg [S_ID_WIDTH-1:0] cmd_table_start_tid;
reg [S_DEST_WIDTH-1:0] cmd_table_start_tdest;
reg [USER_WIDTH-1:0] cmd_table_start_tuser;
reg cmd_table_start_en;
reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_read_ptr_reg = 0;
reg cmd_table_read_en;
reg [CMD_ADDR_WIDTH-1:0] cmd_table_commit_ptr;
reg cmd_table_commit_en;
reg [CMD_ADDR_WIDTH+1-1:0] cmd_table_finish_ptr_reg = 0;
reg cmd_table_finish_en;
reg [RAM_ADDR_WIDTH-1:0] cmd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, cmd_addr_next;
reg [ADDR_WIDTH-1:0] cmd_len_reg = {ADDR_WIDTH{1'b0}}, cmd_len_next;
reg [CMD_ADDR_WIDTH-1:0] cmd_id_reg = {CMD_ADDR_WIDTH{1'b0}}, cmd_id_next;
reg [KEEP_WIDTH-1:0] cmd_tkeep_reg = {KEEP_WIDTH{1'b0}}, cmd_tkeep_next;
reg [S_ID_WIDTH-1:0] cmd_tid_reg = {S_ID_WIDTH_INT{1'b0}}, cmd_tid_next;
reg [S_DEST_WIDTH-1:0] cmd_tdest_reg = {S_DEST_WIDTH{1'b0}}, cmd_tdest_next;
reg [USER_WIDTH-1:0] cmd_tuser_reg = {USER_WIDTH{1'b0}}, cmd_tuser_next;
reg [M_COUNT-1:0] cmd_valid_reg = 0, cmd_valid_next;
reg cmd_status_ready_reg = 1'b0, cmd_status_ready_next;
wire [M_COUNT-1:0] port_cmd_ready;
for (n = 0; n < M_COUNT; n = n + 1) begin
assign port_cmd_ready[n] = int_cmd_ready[m+n*S_COUNT];
end
assign port_axis_tready = (select_valid_reg && (!ram_wr_en_reg || ram_wr_ack) && (!full || full_wr || DROP_WHEN_FULL) && ($unsigned(cmd_table_start_ptr_reg - cmd_table_finish_ptr_reg) < 2**CMD_ADDR_WIDTH)) || drop_reg;
assign port_ram_wr_data[m*DATA_WIDTH +: DATA_WIDTH] = ram_wr_data_reg;
assign port_ram_wr_addr[m*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = ram_wr_addr_reg[ADDR_WIDTH-1:0] | (m << ADDR_WIDTH);
assign port_ram_wr_en[m] = ram_wr_en_reg;
assign ram_wr_ack = port_ram_wr_ack[m];
assign int_cmd_addr[m*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = cmd_addr_reg[ADDR_WIDTH-1:0] | (m << ADDR_WIDTH);
assign int_cmd_len[m*ADDR_WIDTH +: ADDR_WIDTH] = cmd_len_reg;
assign int_cmd_id[m*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_id_reg;
assign int_cmd_tkeep[m*KEEP_WIDTH +: KEEP_WIDTH] = cmd_tkeep_reg;
assign int_cmd_tid[m*S_ID_WIDTH +: S_ID_WIDTH_INT] = cmd_tid_reg;
assign int_cmd_tdest[m*S_DEST_WIDTH +: S_DEST_WIDTH] = cmd_tdest_reg;
assign int_cmd_tuser[m*USER_WIDTH +: USER_WIDTH] = cmd_tuser_reg;
assign int_cmd_valid[m*M_COUNT +: M_COUNT] = cmd_valid_reg;
assign cmd_status_ready_mux = cmd_status_ready_reg;
assign status_overflow[m] = overflow_reg;
assign status_bad_frame[m] = bad_frame_reg;
assign status_good_frame[m] = good_frame_reg;
always @* begin
wr_ptr_next = wr_ptr_reg;
wr_ptr_cur_next = wr_ptr_cur_reg;
rd_ptr_next = rd_ptr_reg;
len_next = len_reg;
drop_frame_next = drop_frame_reg;
overflow_next = 1'b0;
bad_frame_next = 1'b0;
good_frame_next = 1'b0;
ram_wr_data_next = ram_wr_data_reg;
ram_wr_addr_next = ram_wr_addr_reg;
ram_wr_en_next = ram_wr_en_reg && !ram_wr_ack;
cmd_table_start_addr_start = wr_ptr_reg;
cmd_table_start_addr_end = wr_ptr_cur_reg + 1;
cmd_table_start_len = len_reg;
cmd_table_start_select = select_reg;
cmd_table_start_tkeep = S_KEEP_ENABLE ? port_axis_tkeep : 1'b1;
cmd_table_start_tid = port_axis_tid;
cmd_table_start_tdest = port_axis_tdest;
cmd_table_start_tuser = port_axis_tuser;
cmd_table_start_en = 1'b0;
cmd_table_read_en = 1'b0;
cmd_table_commit_ptr = 0;
cmd_table_commit_en = 1'b0;
cmd_table_finish_en = 1'b0;
cmd_addr_next = cmd_addr_reg;
cmd_len_next = cmd_len_reg;
cmd_id_next = cmd_id_reg;
cmd_tkeep_next = cmd_tkeep_reg;
cmd_tid_next = cmd_tid_reg;
cmd_tdest_next = cmd_tdest_reg;
cmd_tuser_next = cmd_tuser_reg;
cmd_valid_next = cmd_valid_reg;
cmd_status_ready_next = 1'b0;
// issue memory writes and commands
if (port_axis_tready && port_axis_tvalid && select_valid_reg && !drop_reg) begin
if (full || full_wr || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_next = 1'b1;
if (port_axis_tlast) begin
// end of frame, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
drop_frame_next = 1'b0;
overflow_next = 1'b1;
end
end else begin
wr_ptr_cur_next = wr_ptr_cur_reg + 1;
len_next = len_reg + 1;
// issue write operation
ram_wr_data_next = port_axis_tdata;
ram_wr_addr_next = wr_ptr_cur_reg;
ram_wr_en_next = 1'b1;
if (port_axis_tlast) begin
// end of frame
len_next = 0;
if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(port_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin
// bad packet, reset write pointer
wr_ptr_cur_next = wr_ptr_reg;
bad_frame_next = 1'b1;
end else begin
// good packet, update write pointer
wr_ptr_next = wr_ptr_cur_reg + 1;
good_frame_next = 1'b1;
cmd_table_start_addr_start = wr_ptr_reg;
cmd_table_start_addr_end = wr_ptr_cur_reg + 1;
cmd_table_start_len = len_reg;
cmd_table_start_select = select_reg;
cmd_table_start_tkeep = port_axis_tkeep;
cmd_table_start_tid = port_axis_tid;
cmd_table_start_tdest = port_axis_tdest;
cmd_table_start_tuser = port_axis_tuser;
cmd_table_start_en = 1'b1;
end
end
end
end
// read
cmd_valid_next = cmd_valid_reg & ~port_cmd_ready;
if (!cmd_valid_reg && cmd_table_active[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]] && cmd_table_read_ptr_reg != cmd_table_start_ptr_reg && (!ram_wr_en_reg || ram_wr_ack)) begin
cmd_table_read_en = 1'b1;
cmd_addr_next = cmd_table_addr_start[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_len_next = cmd_table_len[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_id_next = cmd_table_read_ptr_reg;
cmd_tkeep_next = cmd_table_tkeep[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_tid_next = cmd_table_tid[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_tdest_next = cmd_table_tdest[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_tuser_next = cmd_table_tuser[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_valid_next = 1 << cmd_table_select[cmd_table_read_ptr_reg[CMD_ADDR_WIDTH-1:0]];
end
// commit
if (cmd_status_valid_mux) begin
cmd_status_ready_next = 1'b1;
cmd_table_commit_ptr = cmd_status_id_mux;
cmd_table_commit_en = 1'b1;
end
// clean-up
if (cmd_table_active[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]] && cmd_table_commit[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]] && cmd_table_finish_ptr_reg != cmd_table_start_ptr_reg) begin
// update read pointer
rd_ptr_next = cmd_table_addr_end[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]];
cmd_table_finish_en = 1'b1;
end
end
always @(posedge clk) begin
wr_ptr_reg <= wr_ptr_next;
wr_ptr_cur_reg <= wr_ptr_cur_next;
rd_ptr_reg <= rd_ptr_next;
len_reg <= len_next;
drop_frame_reg <= drop_frame_next;
overflow_reg <= overflow_next;
bad_frame_reg <= bad_frame_next;
good_frame_reg <= good_frame_next;
ram_wr_data_reg <= ram_wr_data_next;
ram_wr_addr_reg <= ram_wr_addr_next;
ram_wr_en_reg <= ram_wr_en_next;
cmd_addr_reg <= cmd_addr_next;
cmd_len_reg <= cmd_len_next;
cmd_id_reg <= cmd_id_next;
cmd_tkeep_reg <= cmd_tkeep_next;
cmd_tid_reg <= cmd_tid_next;
cmd_tdest_reg <= cmd_tdest_next;
cmd_tuser_reg <= cmd_tuser_next;
cmd_valid_reg <= cmd_valid_next;
cmd_status_ready_reg <= cmd_status_ready_next;
if (cmd_table_start_en) begin
cmd_table_start_ptr_reg <= cmd_table_start_ptr_reg + 1;
cmd_table_active[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= 1'b1;
cmd_table_commit[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= 1'b0;
cmd_table_addr_start[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_addr_start;
cmd_table_addr_end[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_addr_end;
cmd_table_len[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_len;
cmd_table_select[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_select;
cmd_table_tkeep[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_tkeep;
cmd_table_tid[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_tid;
cmd_table_tdest[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_tdest;
cmd_table_tuser[cmd_table_start_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= cmd_table_start_tuser;
end
if (cmd_table_read_en) begin
cmd_table_read_ptr_reg <= cmd_table_read_ptr_reg + 1;
end
if (cmd_table_commit_en) begin
cmd_table_commit[cmd_table_commit_ptr] <= 1'b1;
end
if (cmd_table_finish_en) begin
cmd_table_finish_ptr_reg <= cmd_table_finish_ptr_reg + 1;
cmd_table_active[cmd_table_finish_ptr_reg[CMD_ADDR_WIDTH-1:0]] <= 1'b0;
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}};
rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}};
len_reg <= {ADDR_WIDTH{1'b0}};
drop_frame_reg <= 1'b0;
overflow_reg <= 1'b0;
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
ram_wr_en_reg <= 1'b0;
cmd_valid_reg <= 1'b0;
cmd_status_ready_reg <= 1'b0;
cmd_table_start_ptr_reg <= 0;
cmd_table_read_ptr_reg <= 0;
cmd_table_finish_ptr_reg <= 0;
end
end
end // s_ifaces
for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
// command arbitration
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
cmd_arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
// mux
reg [RAM_ADDR_WIDTH-1:0] cmd_addr_mux;
reg [ADDR_WIDTH-1:0] cmd_len_mux;
reg [CMD_ADDR_WIDTH-1:0] cmd_id_mux;
reg [KEEP_WIDTH-1:0] cmd_tkeep_mux;
reg [M_ID_WIDTH-1:0] cmd_tid_mux;
reg [M_DEST_WIDTH-1:0] cmd_tdest_mux;
reg [USER_WIDTH-1:0] cmd_tuser_mux;
reg cmd_valid_mux;
wire cmd_ready_mux;
always @* begin
cmd_addr_mux = int_cmd_addr[grant_encoded*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH];
cmd_len_mux = int_cmd_len[grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
cmd_id_mux = int_cmd_id[grant_encoded*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH];
cmd_tkeep_mux = int_cmd_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
cmd_tid_mux = int_cmd_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
if (UPDATE_TID && S_COUNT > 1) begin
cmd_tid_mux[M_ID_WIDTH-1:M_ID_WIDTH-CL_S_COUNT] = grant_encoded;
end
cmd_tdest_mux = int_cmd_tdest[grant_encoded*S_DEST_WIDTH +: S_DEST_WIDTH];
cmd_tuser_mux = int_cmd_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
cmd_valid_mux = int_cmd_valid[grant_encoded*M_COUNT+n] && grant_valid;
end
assign int_cmd_ready[n*S_COUNT +: S_COUNT] = (grant_valid && cmd_ready_mux) << grant_encoded;
for (m = 0; m < S_COUNT; m = m + 1) begin
assign request[m] = int_cmd_valid[m*M_COUNT+n] && !grant[m];
assign acknowledge[m] = grant[m] && int_cmd_valid[m*M_COUNT+n] && cmd_ready_mux;
end
reg [RAM_ADDR_WIDTH-1:0] rd_ptr_reg = {RAM_ADDR_WIDTH-1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH-1:0] len_reg = {ADDR_WIDTH{1'b0}}, len_next;
reg [CL_S_COUNT-1:0] src_reg = 0, src_next;
reg [CMD_ADDR_WIDTH-1:0] id_reg = 0, id_next;
reg [KEEP_WIDTH-1:0] last_cycle_tkeep_reg = {KEEP_WIDTH{1'b0}}, last_cycle_tkeep_next;
reg [M_ID_WIDTH-1:0] tid_reg = {M_ID_WIDTH{1'b0}}, tid_next;
reg [M_DEST_WIDTH-1:0] tdest_reg = {M_DEST_WIDTH_INT{1'b0}}, tdest_next;
reg [USER_WIDTH-1:0] tuser_reg = {USER_WIDTH{1'b0}}, tuser_next;
reg [DATA_WIDTH-1:0] out_axis_tdata_reg = {DATA_WIDTH{1'b0}}, out_axis_tdata_next;
reg [KEEP_WIDTH-1:0] out_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, out_axis_tkeep_next;
reg out_axis_tvalid_reg = 1'b0, out_axis_tvalid_next;
wire out_axis_tready;
reg out_axis_tlast_reg = 1'b0, out_axis_tlast_next;
reg [M_ID_WIDTH-1:0] out_axis_tid_reg = {M_ID_WIDTH{1'b0}}, out_axis_tid_next;
reg [M_DEST_WIDTH-1:0] out_axis_tdest_reg = {M_DEST_WIDTH_INT{1'b0}}, out_axis_tdest_next;
reg [USER_WIDTH-1:0] out_axis_tuser_reg = {USER_WIDTH{1'b0}}, out_axis_tuser_next;
reg [RAM_ADDR_WIDTH-1:0] ram_rd_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, ram_rd_addr_next;
reg ram_rd_en_reg = 1'b0, ram_rd_en_next;
wire ram_rd_ack;
wire [DATA_WIDTH-1:0] ram_rd_data;
wire ram_rd_data_valid;
reg cmd_valid_reg = 1'b0, cmd_valid_next;
reg [CMD_ADDR_WIDTH-1:0] cmd_status_id_reg = {CMD_ADDR_WIDTH{1'b0}}, cmd_status_id_next;
reg [S_COUNT-1:0] cmd_status_valid_reg = 0, cmd_status_valid_next;
wire [S_COUNT-1:0] port_cmd_status_ready;
for (m = 0; m < S_COUNT; m = m + 1) begin
assign port_cmd_status_ready[m] = int_cmd_status_ready[m*M_COUNT+n];
end
reg [DATA_WIDTH-1:0] out_fifo_tdata[31:0];
reg [KEEP_WIDTH-1:0] out_fifo_tkeep[31:0];
reg out_fifo_tlast[31:0];
reg [M_ID_WIDTH-1:0] out_fifo_tid[31:0];
reg [M_DEST_WIDTH-1:0] out_fifo_tdest[31:0];
reg [USER_WIDTH-1:0] out_fifo_tuser[31:0];
reg [5:0] out_fifo_data_wr_ptr_reg = 0;
reg [DATA_WIDTH-1:0] out_fifo_data_wr_tdata;
reg out_fifo_data_wr_en;
reg [5:0] out_fifo_ctrl_wr_ptr_reg = 0;
reg [KEEP_WIDTH-1:0] out_fifo_ctrl_wr_tkeep;
reg out_fifo_ctrl_wr_tlast;
reg [M_ID_WIDTH-1:0] out_fifo_ctrl_wr_tid;
reg [M_DEST_WIDTH-1:0] out_fifo_ctrl_wr_tdest;
reg [USER_WIDTH-1:0] out_fifo_ctrl_wr_tuser;
reg out_fifo_ctrl_wr_en;
reg [5:0] out_fifo_rd_ptr_reg = 0;
reg out_fifo_rd_en;
assign port_ram_rd_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH] = ram_rd_addr_reg;
assign port_ram_rd_en[n] = ram_rd_en_reg;
assign ram_rd_ack = port_ram_rd_ack[n];
assign ram_rd_data = port_ram_rd_data[n*DATA_WIDTH +: DATA_WIDTH];
assign ram_rd_data_valid = port_ram_rd_data_valid[n];
assign cmd_ready_mux = !cmd_valid_reg;
assign int_cmd_status_id[n*CMD_ADDR_WIDTH +: CMD_ADDR_WIDTH] = cmd_status_id_reg;
assign int_cmd_status_valid[n*S_COUNT +: S_COUNT] = cmd_status_valid_reg;
always @* begin
rd_ptr_next = rd_ptr_reg;
len_next = len_reg;
src_next = src_reg;
id_next = id_reg;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
tid_next = tid_reg;
tdest_next = tdest_reg;
tuser_next = tuser_reg;
out_axis_tdata_next = out_axis_tdata_reg;
out_axis_tkeep_next = out_axis_tkeep_reg;
out_axis_tvalid_next = out_axis_tvalid_reg && !out_axis_tready;
out_axis_tlast_next = out_axis_tlast_reg;
out_axis_tid_next = out_axis_tid_reg;
out_axis_tdest_next = out_axis_tdest_reg;
out_axis_tuser_next = out_axis_tuser_reg;
ram_rd_addr_next = ram_rd_addr_reg;
ram_rd_en_next = ram_rd_en_reg && !ram_rd_ack;
cmd_valid_next = cmd_valid_reg;
cmd_status_id_next = cmd_status_id_reg;
cmd_status_valid_next = cmd_status_valid_reg & ~port_cmd_status_ready;
out_fifo_data_wr_tdata = ram_rd_data;
out_fifo_data_wr_en = 1'b0;
out_fifo_ctrl_wr_tkeep = len_reg == 0 ? last_cycle_tkeep_reg : {KEEP_WIDTH{1'b1}};
out_fifo_ctrl_wr_tlast = len_reg == 0;
out_fifo_ctrl_wr_tid = tid_reg;
out_fifo_ctrl_wr_tdest = tdest_reg;
out_fifo_ctrl_wr_tuser = tuser_reg;
out_fifo_ctrl_wr_en = 1'b0;
out_fifo_rd_en = 1'b0;
// receive commands
if (!cmd_valid_reg && cmd_valid_mux) begin
cmd_valid_next = 1'b1;
rd_ptr_next = cmd_addr_mux;
len_next = cmd_len_mux;
last_cycle_tkeep_next = cmd_tkeep_mux;
id_next = cmd_id_mux;
tid_next = cmd_tid_mux;
tdest_next = cmd_tdest_mux;
tuser_next = cmd_tuser_mux;
src_next = grant_encoded;
end
// process commands and issue memory reads
if (cmd_valid_reg && !cmd_status_valid_next && (!ram_rd_en_reg || ram_rd_ack) && ($unsigned(out_fifo_ctrl_wr_ptr_reg - out_fifo_rd_ptr_reg) < 32)) begin
// update counters
rd_ptr_next[ADDR_WIDTH-1:0] = rd_ptr_reg[ADDR_WIDTH-1:0] + 1;
len_next = len_reg - 1;
// issue memory read
ram_rd_addr_next = rd_ptr_reg;
ram_rd_en_next = 1'b1;
// write output control FIFO
out_fifo_ctrl_wr_tkeep = len_reg == 0 ? last_cycle_tkeep_reg : {KEEP_WIDTH{1'b1}};
out_fifo_ctrl_wr_tlast = len_reg == 0;
out_fifo_ctrl_wr_tid = tid_reg;
out_fifo_ctrl_wr_tdest = tdest_reg;
out_fifo_ctrl_wr_tuser = tuser_reg;
out_fifo_ctrl_wr_en = 1'b1;
if (len_reg == 0) begin
// indicate operation complete
cmd_status_id_next = id_reg;
cmd_status_valid_next = 1 << src_reg;
cmd_valid_next = 1'b0;
end
end
// write RAM read data to output data FIFO
if (ram_rd_data_valid) begin
out_fifo_data_wr_tdata = ram_rd_data;
out_fifo_data_wr_en = 1'b1;
end
// generate output AXI stream data from control and data FIFOs
if ((out_axis_tready || !out_axis_tvalid_reg) && (out_fifo_rd_ptr_reg != out_fifo_ctrl_wr_ptr_reg) && (out_fifo_rd_ptr_reg != out_fifo_data_wr_ptr_reg)) begin
out_fifo_rd_en = 1'b1;
out_axis_tdata_next = out_fifo_tdata[out_fifo_rd_ptr_reg[4:0]];
out_axis_tkeep_next = out_fifo_tkeep[out_fifo_rd_ptr_reg[4:0]];
out_axis_tvalid_next = 1'b1;
out_axis_tlast_next = out_fifo_tlast[out_fifo_rd_ptr_reg[4:0]];
out_axis_tid_next = out_fifo_tid[out_fifo_rd_ptr_reg[4:0]];
out_axis_tdest_next = out_fifo_tdest[out_fifo_rd_ptr_reg[4:0]];
out_axis_tuser_next = out_fifo_tuser[out_fifo_rd_ptr_reg[4:0]];
end
end
always @(posedge clk) begin
rd_ptr_reg <= rd_ptr_next;
len_reg <= len_next;
src_reg <= src_next;
id_reg <= id_next;
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
tid_reg <= tid_next;
tdest_reg <= tdest_next;
tuser_reg <= tuser_next;
out_axis_tdata_reg <= out_axis_tdata_next;
out_axis_tkeep_reg <= out_axis_tkeep_next;
out_axis_tvalid_reg <= out_axis_tvalid_next;
out_axis_tlast_reg <= out_axis_tlast_next;
out_axis_tid_reg <= out_axis_tid_next;
out_axis_tdest_reg <= out_axis_tdest_next;
out_axis_tuser_reg <= out_axis_tuser_next;
ram_rd_addr_reg <= ram_rd_addr_next;
ram_rd_en_reg <= ram_rd_en_next;
cmd_valid_reg <= cmd_valid_next;
cmd_status_id_reg <= cmd_status_id_next;
cmd_status_valid_reg <= cmd_status_valid_next;
if (out_fifo_data_wr_en) begin
out_fifo_data_wr_ptr_reg <= out_fifo_data_wr_ptr_reg + 1;
out_fifo_tdata[out_fifo_data_wr_ptr_reg[4:0]] <= out_fifo_data_wr_tdata;
end
if (out_fifo_ctrl_wr_en) begin
out_fifo_ctrl_wr_ptr_reg <= out_fifo_ctrl_wr_ptr_reg + 1;
out_fifo_tkeep[out_fifo_ctrl_wr_ptr_reg[4:0]] <= out_fifo_ctrl_wr_tkeep;
out_fifo_tlast[out_fifo_ctrl_wr_ptr_reg[4:0]] <= out_fifo_ctrl_wr_tlast;
out_fifo_tid[out_fifo_ctrl_wr_ptr_reg[4:0]] <= out_fifo_ctrl_wr_tid;
out_fifo_tdest[out_fifo_ctrl_wr_ptr_reg[4:0]] <= out_fifo_ctrl_wr_tdest;
out_fifo_tuser[out_fifo_ctrl_wr_ptr_reg[4:0]] <= out_fifo_ctrl_wr_tuser;
end
if (out_fifo_rd_en) begin
out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
end
if (rst) begin
len_reg <= 0;
out_axis_tvalid_reg <= 1'b0;
ram_rd_en_reg <= 1'b0;
cmd_valid_reg <= 1'b0;
cmd_status_valid_reg <= 0;
out_fifo_data_wr_ptr_reg <= 0;
out_fifo_ctrl_wr_ptr_reg <= 0;
out_fifo_rd_ptr_reg <= 0;
end
end
axis_adapter #(
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(M_ID_WIDTH),
.DEST_ENABLE(M_DEST_WIDTH > 0),
.DEST_WIDTH(M_DEST_WIDTH_INT),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(out_axis_tdata_reg),
.s_axis_tkeep(out_axis_tkeep_reg),
.s_axis_tvalid(out_axis_tvalid_reg),
.s_axis_tready(out_axis_tready),
.s_axis_tlast(out_axis_tlast_reg),
.s_axis_tid(out_axis_tid_reg),
.s_axis_tdest(out_axis_tdest_reg),
.s_axis_tuser(out_axis_tuser_reg),
// AXI output
.m_axis_tdata(m_axis_tdata[M_DATA_WIDTH*n +: M_DATA_WIDTH]),
.m_axis_tkeep(m_axis_tkeep[M_KEEP_WIDTH*n +: M_KEEP_WIDTH]),
.m_axis_tvalid(m_axis_tvalid[n]),
.m_axis_tready(m_axis_tready[n]),
.m_axis_tlast(m_axis_tlast[n]),
.m_axis_tid(m_axis_tid[M_ID_WIDTH*n +: M_ID_WIDTH]),
.m_axis_tdest(m_axis_tdest[M_DEST_WIDTH*n +: M_DEST_WIDTH_INT]),
.m_axis_tuser(m_axis_tuser[USER_WIDTH*n +: USER_WIDTH])
);
end // m_ifaces
endgenerate
endmodule
`resetall
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [3:0] datai = crc[3:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [3:0] datao; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.datao (datao[3:0]),
// Inputs
.clk (clk),
.datai (datai[3:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, datao};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3db7bc8bfe61f983
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input logic clk,
input logic [3:0] datai,
output logic [3:0] datao
);
genvar i;
parameter SIZE = 4;
logic [SIZE:1][3:0] delay;
always_ff @(posedge clk) begin
delay[1][3:0] <= datai;
end
generate
for (i = 2; i < (SIZE+1); i++) begin
always_ff @(posedge clk) begin
delay[i][3:0] <= delay[i-1][3:0];
end
end
endgenerate
always_comb datao = delay[SIZE][3:0];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Juan Jos� Rojas Salazar
//
// Create Date: 08/01/2016 03:34:00 PM
// Design Name:
// Module Name: DESNORMALIZADOR_DESLINEALIZADOR
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESNORMALIZADOR_DESLINEALIZADOR(
input wire CLK,
input wire [31:0] I,
input wire [31:0] V,
input wire RST_EX_FF,
input wire Begin_FSM_I,
//input wire Begin_FSM_V,
output wire ACK_I,
//output wire ACK_V,
// output wire U_F,
// output wire O_F,
output wire [31:0] RESULT_I
//output wire [31:0] RESULT_V
);
// wire ACK_EX;
wire ACK_FF;
wire [31:0] FLOATING;
I_DESNORM_FIXED_TO_FLOAT DESNORM_I_FIXED_FLOAT(
.CLK(CLK), //system clock
.F(I), //VALOR BINARIO EN COMA FIJA
.RST_FF(RST_EX_FF), //system reset
.Begin_FSM_FF(Begin_FSM_I), //INICIA LA CONVERSION
.ACK_FF(ACK_FF), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(FLOATING) //RESULTADO FINAL
);
DESLINEALIZADOR #(.P(32)) DESLINEALIZADOR_FLOAT (
.CLK(CLK), //system clock
.T(FLOATING), //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
//.T(I), //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
.RST_EX(RST_EX_FF), //system reset
.Begin_FSM_EX(ACK_FF), //INICIA EL CALCULO
//.Begin_FSM_EX(Begin_FSM_I), //INICIA EL CALCULO
.ACK_EX(ACK_I), //INDICA QUE EL CALCULO FUE REALIZADO
.O_FX(), //BANDERA DE OVER FLOW X
.O_FY(), //BANDERA DE OVER FLOW X
.O_FZ(), //BANDERA DE OVER FLOW X
.U_FX(), //BANDERA DE UNDER FLOW Y
.U_FY(), //BANDERA DE UNDER FLOW Y
.U_FZ(), //BANDERA DE UNDER FLOW Y
.RESULT(RESULT_I) //RESULTADO FINAL
);
/*V_DESNORM_FIXED_TO_FLOAT DESNORM_V_FIXED_FLOAT(
.CLK(CLK), //system clock
.F(V), //VALOR BINARIO EN COMA FIJA
.RST_FF(RST_EX_FF), //system reset
.Begin_FSM_FF(Begin_FSM_V), //INICIA LA CONVERSION
.ACK_FF(ACK_V), //INDICA QUE LA CONVERSION FUE REALIZADA
.RESULT(RESULT_V) //RESULTADO FINAL
);*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
integer p_i;
reg [7*8:1] p_str;
initial begin
if ($test$plusargs("PLUS")!==1) $stop;
if ($test$plusargs("PLUSNOT")!==0) $stop;
if ($test$plusargs("PL")!==1) $stop;
//if ($test$plusargs("")!==1) $stop; // Simulators differ in this answer
if ($test$plusargs("NOTTHERE")!==0) $stop;
p_i = 10;
if ($value$plusargs("NOTTHERE%d", p_i)!==0) $stop;
if (p_i !== 10) $stop;
if ($value$plusargs("INT=%d", p_i)!==1) $stop;
if (p_i !== 32'd1234) $stop;
if ($value$plusargs("INT=%H", p_i)!==1) $stop; // tests uppercase % also
if (p_i !== 32'h1234) $stop;
if ($value$plusargs("INT=%o", p_i)!==1) $stop;
if (p_i !== 32'o1234) $stop;
if ($value$plusargs("IN%s", p_str)!==1) $stop;
$display("str='%s'",p_str);
if (p_str !== "T=1234") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_SYMBOL_V
`define SKY130_FD_SC_LP__XOR3_SYMBOL_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: init_mem_pattern_ctr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/24 00:08:32 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel has a small FSM to control the operation of
// memc_traffic_gen module.It first fill up the memory with a selected
// DATA pattern and then starts the memory testing state.
//Reference:
//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6"
// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during
// memory testing phase.
// 1.3 1-4-2012 Fixed end address logic if defined END_ADDRESS == 0x0FFFFFFF.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_init_mem_pattern_ctr #
(
parameter SIMULATION = "FALSE",
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6
parameter MEM_TYPE = "DDR3",//DDR3,DDR2, QDR2PLUS,
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
// "R_W_INSTR_MODE" - Random Read/Write commands will be generated.
parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option.
parameter nCK_PER_CLK = 4,
parameter BL_WIDTH = 10,
parameter NUM_DQ_PINS = 4, // Total number of memory dq pins in the design.
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available
// commands pattern.
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00000fff,
parameter ADDR_WIDTH = 30,
parameter DWIDTH = 32,
parameter CMD_SEED_VALUE = 32'h12345678,
parameter DATA_SEED_VALUE = 32'hca345675,
parameter DATA_MODE = 4'b0010,
parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE"
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory
// signals. It overwrites the TST_MEM_INSTR_MODE setting.
// Traffic Generator will onlywrite to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input single_write_button,
input single_read_button,
input slow_write_read_button,
input single_operation, // tie this signal to '1' if want to do single operation
input memc_cmd_en_i,
input memc_wr_en_i,
input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode.
// 1: enable exteral VIO to control the data_mode pattern
input [3:0] vio_instr_mode_value, // "0000" = Fixed
// "0001" = bram; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0111" = Single Step
// and address mode pattern during runtime.
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [1:0] vio_bl_mode_value,
input vio_data_mask_gen,
input [2:0] vio_fixed_instr_value,
input [BL_WIDTH - 1:0] vio_fixed_bl_value, // valid range is: from 1 to 64.
input memc_init_done_i,
input cmp_error,
output reg run_traffic_o,
// runtime parameter
output [31:0] start_addr_o, // define the start of address
output [31:0] end_addr_o,
output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
output [31:0] data_seed_o,
output reg load_seed_o, //
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output
// "001" = fixed address from the fixed_addr input
// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "011" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
output reg [3:0] instr_mode_o, // "0000" = Fixed
// "0001" = bram; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0111" = Single Step
// "1111" = Debug Read Only, bypass memory initialization
output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
output reg [3:0] data_mode_o, // "00" = bram;
// "01" = fixed data from the fixed_data input
// "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR
// "11" = sequential using the addrs as the starting data pattern
output reg mode_load_o,
// fixed pattern inputs interface
output reg [BL_WIDTH-1:0] fixed_bl_o, // range from 1 to 64
output reg [2:0] fixed_instr_o, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
output reg mem_pattern_init_done_o
);
//FSM State Defination
parameter IDLE = 8'b00000001,
INIT_MEM_WRITE = 8'b00000010,
INIT_MEM_READ = 8'b00000100,
TEST_MEM = 8'b00001000,
SINGLE_STEP_WRITE = 8'b00010000, //0x10
SINGLE_STEP_READ = 8'b00100000, //0x20
CMP_ERROR = 8'b01000000,
SINGLE_CMD_WAIT = 8'b10000000;
localparam BRAM_ADDR = 3'b000;
localparam FIXED_ADDR = 3'b001;
localparam PRBS_ADDR = 3'b010;
localparam SEQUENTIAL_ADDR = 3'b011;
localparam BRAM_INSTR_MODE = 4'b0000;
localparam FIXED_INSTR_MODE = 4'b0001;
localparam R_W_INSTR_MODE = 4'b0010;
localparam RP_WP_INSTR_MODE = 4'b0011;
localparam R_RP_W_WP_INSTR_MODE = 4'b0100;
localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101;
localparam BRAM_BL_MODE = 2'b00;
localparam FIXED_BL_MODE = 2'b01;
localparam PRBS_BL_MODE = 2'b10;
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
// type fixed instruction
localparam RD_INSTR = 3'b001;
localparam RDP_INSTR = 3'b011;
localparam WR_INSTR = 3'b000;
localparam WRP_INSTR = 3'b010;
localparam REFRESH_INSTR = 3'b100;
localparam NOP_WR_INSTR = 3'b101;
//(* FSM_ENCODING="USER" *) reg [6:0] STATE = current_state;
reg [7:0] current_state;
reg [7:0] next_state;
reg memc_init_done_reg;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [31:0] end_boundary_addr;
reg memc_cmd_en_r;
reg lower_end_matched;
reg end_addr_reached;
reg run_traffic;
reg bram_mode_enable;
reg [31:0] current_address;
reg [BL_WIDTH-1:0] fix_bl_value;
reg [3:0] data_mode_sel;
reg [1:0] bl_mode_sel;
reg [2:0] addr_mode;
reg [10:0] INC_COUNTS;
wire [3:0] test_mem_instr_mode;
reg pre_instr_switch;
reg switch_instr;
reg memc_wr_en_r;
reg mode_load_d1,mode_load_d2,mode_load_pulse;
reg mode_load_d3,mode_load_d4,mode_load_d5;
always @ (posedge clk_i) begin
mode_load_d1 <= #TCQ mode_load_o;
mode_load_d2 <= #TCQ mode_load_d1;
mode_load_d3 <= #TCQ mode_load_d2;
mode_load_d4 <= #TCQ mode_load_d3;
mode_load_d5 <= #TCQ mode_load_d4;
end
always @ (posedge clk_i)
mode_load_pulse <= #TCQ mode_load_d4 & ~mode_load_d5;
always @ (TST_MEM_INSTR_MODE, EYE_TEST)
if ((TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || TST_MEM_INSTR_MODE == "R_W_INSTR_MODE" ||
TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" || TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" ||
TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" || TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE" )
&& (EYE_TEST == "TRUE"))
begin: Warning_Message1
$display("Invalid Parameter setting! When EYE_TEST is set to TRUE, only WRITE commands can be generated.");
$stop;
end
else
begin: NoWarning_Message1
end
always @ (TST_MEM_INSTR_MODE)
if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "SPARTAN6")
begin
$display("Error ! Not supported test instruction mode in Spartan 6");
$stop;
end
else
begin
// dummy
end
always @ (vio_fixed_bl_value,vio_data_mode_value)
if (vio_fixed_bl_value[6:0] > 7'd64 && FAMILY == "SPARTAN6")
begin
$display("Error ! Maximum User Burst Length is 64");
$display("Change a smaller burst size");
$stop;
end
else if ((vio_data_mode_value == 4'h6 || vio_data_mode_value == 4'h5) && FAMILY == "VIRTEX6")
begin
$display("Data DQ bus Walking 1's test.");
$display("A single DQ bit is set to 1 and walk through entire DQ bus to test ");
$display("if each DQ bit can be set to 0 or 1 ");
if (NUM_DQ_PINS == 8)begin
$display("Warning ! Fixed Burst Length in this mode is forced to 64");
$display("to ensure '1' always appear on DQ0 of each beginning User Burst");
end
else begin
$display("Warning ! Fixed Burst Length in this mode is forced to equal to NUM_DQ_PINS");
$display("to ensure '1' always appear on DQ0 of each beginning User Burst");
end
end
else
begin// dummy
end
always @ (data_mode_o)
if (data_mode_o == 4'h7 && FAMILY == "SPARTAN6")
begin
$display("Error ! Hammer PRBS is not support in MCB-like interface");
$display("Set value to 4'h8 for Psuedo PRBS");
$stop;
end
else
begin
// dummy
end
//always @ (vio_data_mode_value,TST_MEM_INSTR_MODE)
//if (TST_MEM_INSTR_MODE != "FIXED_INSTR_R_MODE" &&
// vio_data_mode_value == 4'b1000)
//begin
//$display("Error ! The selected PRBS data pattern has to run together with FIXED_INSTR_R_MODE");
//$display("Set the TST_MEM_INSTR_MODE = FIXED_INSTR_R_MODE and addr_mode to sequential mode");
//$stop;
//end
assign test_mem_instr_mode = (vio_instr_mode_value[3:2] == 2'b11) ? 4'b1111:
(vio_instr_mode_value[3:2] == 2'b10) ? 4'b1011:
(TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000:
(TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" ||
TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001:
(TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010:
(TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101:
4'b0010;
always @ (posedge clk_i)
begin
if (data_mode_o == 4)
begin
fix_bl_value[4:0] <= 5'd8;//Simple_Data_MODE;
fix_bl_value[BL_WIDTH-1:5] <= 'b0;
end
else if (data_mode_o == 5 || data_mode_o == 6 )
if (MEM_TYPE == "RLD3" && vio_modify_enable)
fix_bl_value <= vio_fixed_bl_value;
else
if (NUM_DQ_PINS == 8)
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else
fix_bl_value <= NUM_DQ_PINS;//Waling 1's or 0's;
else if (data_mode_o == 8)
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else if (vio_modify_enable == 1'b1)
if (vio_fixed_bl_value == 0) // not valid value;
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
else begin
fix_bl_value <= vio_fixed_bl_value;
end
else
begin
fix_bl_value[6:0] <= 7'b1000000;
fix_bl_value[BL_WIDTH-1:7] <= 'b0;
end
end
generate
if (FAMILY == "SPARTAN6" )
begin : INC_COUNTS_S
always @ (posedge clk_i)
INC_COUNTS <= (DWIDTH/8);
end
else // VIRTEX 6
begin : INC_COUNTS_V
always @ (posedge clk_i)
if (MEM_TYPE == "QDR2PLUS")
INC_COUNTS <= 1;// Each address is associated with 4 words in QDR2.
else
INC_COUNTS <= MEM_BURST_LEN;
end
endgenerate
// In V6, each write command in MEM_BLEN = 8, TG writes 8 words of DQ width data to the accessed location.
// For MEM_BLEN = 4, TG writes 4 words of DQ width data to the accessed location.
reg Cout_b;
always @ (posedge clk_i)
begin
if (rst_i)
current_address <= BEGIN_ADDRESS;
else if (memc_wr_en_r && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE"))
|| (memc_wr_en_r && (current_state == IDLE && PORT_MODE == "RD_MODE")) )
// ** current_address stops incrementing when reaching the beginning of last END_ADDRESS write burst.
{Cout_b,current_address} <= current_address + INC_COUNTS;
else
current_address <= current_address;
end
always @ (posedge clk_i)
begin
if (rst_i)
AC3_G_E3 <= 1'b0;
else if (current_address[29:24] >= end_boundary_addr[29:24])
AC3_G_E3 <= 1'b1;
else
AC3_G_E3 <= AC3_G_E3;
if (rst_i)
AC2_G_E2 <= 1'b0;
else if (current_address[23:16] >= end_boundary_addr[23:16])
AC2_G_E2 <= AC3_G_E3;
else
AC2_G_E2 <= AC2_G_E2;
if (rst_i)
AC1_G_E1 <= 1'b0;
else if (current_address[15:8] >= end_boundary_addr[15:8] )
AC1_G_E1 <= AC2_G_E2 & AC3_G_E3;
else
AC1_G_E1 <= AC1_G_E1;
end
always @(posedge clk_i)
begin
if (rst_i)
upper_end_matched <= 1'b0;
else if (memc_cmd_en_i)
upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1;
else
upper_end_matched <= upper_end_matched;
end
//synthesis translate_off
always @ (fix_bl_value)
if(fix_bl_value * MEM_BURST_LEN > END_ADDRESS)
begin
$display("Error ! User Burst Size goes beyond END Address");
$display("decrease vio_fixed_bl_value or increase END Address range");
$stop;
end
else
begin
// dummy
end
always @ (vio_data_mode_value, vio_data_mask_gen)
if(vio_data_mode_value != 4'b0010 && vio_data_mask_gen)
begin
$display("Error ! Data Mask Generation only supported in Data Mode = Address as Data");
$stop;
end
else
begin
// dummy
end
//synthesis translate_on
reg COuta;
always @(posedge clk_i)
begin
// **end_boundary_addr defination is the beginning address of the last write burst of END_ADDRESS
{COuta,end_boundary_addr} <= (END_ADDRESS[31:0] - {{32-BL_WIDTH{1'b0}} ,fix_bl_value } +1) ;
end
always @(posedge clk_i)
begin
if ((current_address[7:4] >= END_ADDRESS[7:4]) && MEM_TYPE == "QDR2PLUS")
lower_end_matched <= 1'b1;
else if ((current_address[7:0] >= end_boundary_addr[7:0]) && MEM_TYPE != "QDR2PLUS")
lower_end_matched <= 1'b1;
else
lower_end_matched <= 1'b0;
end
always @(posedge clk_i)
begin
if (rst_i)
pre_instr_switch <= 1'b0;
else if (current_address[7:0] >= end_boundary_addr[7:0] ) // V6 send a seed address to memc_flow_ctr
pre_instr_switch <= 1'b1;
end
always @(posedge clk_i)
begin
//if (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6" && MEM_TYPE == "QDR2PLUS")
// end_addr_reached <= 1'b1;
if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) ||
(upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) ||
(upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") ||
(upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6"))
end_addr_reached <= 1'b1;
else
end_addr_reached <= 1'b0;
end
always @(posedge clk_i)
begin
if ((upper_end_matched && pre_instr_switch && FAMILY == "VIRTEX6"))
switch_instr <= 1'b1;
else
switch_instr <= 1'b0;
end
always @ (posedge clk_i)
begin
memc_wr_en_r <= memc_wr_en_i;
memc_init_done_reg <= memc_init_done_i;
end
always @ (posedge clk_i)
run_traffic_o <= run_traffic;
always @ (posedge clk_i)
begin
if (rst_i)
current_state <= 5'b00001;
else
current_state <= next_state;
end
assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS;
assign end_addr_o = END_ADDRESS;
assign cmd_seed_o = CMD_SEED_VALUE;
assign data_seed_o = DATA_SEED_VALUE;
//
always @ (posedge clk_i)
begin
if (rst_i)
mem_pattern_init_done_o <= 1'b0;
else if (current_address >= end_boundary_addr )
mem_pattern_init_done_o <= 1'b1;
end
reg [3:0] syn1_vio_data_mode_value;
reg [2:0] syn1_vio_addr_mode_value;
always @ (posedge clk_i)
begin
if (rst_i) begin
syn1_vio_data_mode_value <= 4'b0011;
syn1_vio_addr_mode_value <= 3'b011;
end
else if (vio_modify_enable == 1'b1) begin
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE;
end
else if (vio_modify_enable == 1'b1) begin
data_mode_sel <= syn1_vio_data_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i )
bl_mode_sel <= FIXED_BL_MODE;
else if (test_mem_instr_mode[3])
bl_mode_sel <= 2'b11;
else if (vio_modify_enable == 1'b1) begin
bl_mode_sel <= vio_bl_mode_value;
end
end
always @ (posedge clk_i)
begin
// whenever vio_instr_mode_value[3] == 1'b1, TG expects reading back phy calibration data pattern
// which is: 0xFF, 0x00, 0xAA,0x55, 0x55, 0xAA, 0x99 and 0x66.
if (vio_modify_enable)
if (vio_instr_mode_value == 4'h7)
data_mode_o <= 4'h1; // fixed data input
else
data_mode_o <= (test_mem_instr_mode[3]) ? 4'b1000: data_mode_sel;
else
data_mode_o <= DATA_MODE;
addr_mode_o <= (test_mem_instr_mode[3]) ? 3'b000: addr_mode ;
// assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero
// user wants to have bram interface.
if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1)
bram_mode_enable <= 1'b1;
else
bram_mode_enable <= 1'b0;
end
reg single_write_r1,single_write_r2,single_read_r1,single_read_r2;
reg single_instr_run_trarric;
reg slow_write_read_button_r1,slow_write_read_button_r2;
reg toggle_start_stop_write_read;
wire int_single_wr,int_single_rd;
reg [8:0] write_read_counter;
always @ (posedge clk_i)
begin
if (rst_i) begin
write_read_counter <= 'b0;
slow_write_read_button_r1 <= 1'b0;
slow_write_read_button_r2 <= 1'b0;
toggle_start_stop_write_read <= 1'b0;
end
else begin
write_read_counter <= write_read_counter + 1;
slow_write_read_button_r1 <= slow_write_read_button;
slow_write_read_button_r2 <= slow_write_read_button_r1;
if (~slow_write_read_button_r2 && slow_write_read_button_r1)
toggle_start_stop_write_read <= ~toggle_start_stop_write_read;
end
end
assign int_single_wr = write_read_counter[8];
assign int_single_rd = ~write_read_counter[8];
always @ (posedge clk_i)
begin
if (rst_i)
begin
single_write_r1 <= 1'b0;
single_write_r2 <= 1'b0;
single_read_r1 <= 1'b0;
single_read_r2 <= 1'b0;
end
else begin
single_write_r1 <= single_write_button | (int_single_wr & toggle_start_stop_write_read);
single_write_r2 <= single_write_r1 ;
single_read_r1 <= single_read_button | (int_single_rd & toggle_start_stop_write_read);
single_read_r2 <= single_read_r1 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i)
single_instr_run_trarric <= 1'b0;
else if ((single_write_r1 && ~single_write_r2) || (single_read_r1 && ~single_read_r2))
single_instr_run_trarric <= 1'b1;
else if (mode_load_o)
single_instr_run_trarric <= 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i)
run_traffic <= 1'b0;
else if ((current_state == SINGLE_CMD_WAIT ) || (current_state == SINGLE_STEP_WRITE ) || (current_state == SINGLE_STEP_READ ))
run_traffic <= single_instr_run_trarric;
else if ((current_state == SINGLE_CMD_WAIT ) )
run_traffic <= 1'b0;
else if ( (current_state != IDLE))
run_traffic <= 1'b1;
else
run_traffic <= 1'b0;
end
always @ (*)
begin
load_seed_o = 1'b0;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = 'b0;
else
instr_mode_o = FIXED_INSTR_MODE;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
bl_mode_o = 'b0;
else
bl_mode_o = FIXED_BL_MODE;
if (vio_modify_enable)
if (vio_instr_mode_value == 7)
fixed_bl_o = 10'd1;
else if (data_mode_o[2:0] == 3'b111)
if (FAMILY == "VIRTEX6")
fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256.
else
fixed_bl_o = 10'd64;
else
if (FAMILY == "VIRTEX6")
fixed_bl_o = vio_fixed_bl_value;
// PRBS mode
else if (data_mode_o[3:0] == 4'b1000 && FAMILY == "SPARTAN6")
fixed_bl_o = 10'd64; //
else
fixed_bl_o = fix_bl_value;
else
fixed_bl_o = fix_bl_value;
// fixed_bl_o = 10'd64;
// fixed_bl_o = 10'd256; // for 8 taps PRBS, this has to be set to 256.
mode_load_o = 1'b0;
// run_traffic = 1'b0;
next_state = IDLE;
if (PORT_MODE == "RD_MODE")
fixed_instr_o = RD_INSTR;
else //if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
fixed_instr_o = WR_INSTR;
case(current_state)
IDLE:
begin
if(memc_init_done_reg ) //rdp_rdy_i comes from read_data path
begin
if (vio_instr_mode_value == 4'h7 && single_write_r1 && ~single_write_r2)
begin
next_state = SINGLE_STEP_WRITE;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else if (vio_instr_mode_value == 4'h7 && single_read_r1 && ~single_read_r2)
begin
next_state = SINGLE_STEP_READ;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else if ((PORT_MODE == "WR_MODE" || (PORT_MODE == "BI_MODE" && test_mem_instr_mode[3:2] != 2'b11)) &&
vio_instr_mode_value != 4'h7 ) // normal test mode
begin
next_state = INIT_MEM_WRITE;
mode_load_o = 1'b1;
// run_traffic = 1'b0;
load_seed_o = 1'b1;
end
else if ((PORT_MODE == "RD_MODE" && end_addr_reached || (test_mem_instr_mode == 4'b1111)) &&
vio_instr_mode_value != 4'h7 )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
// run_traffic = 1'b1;
load_seed_o = 1'b1;
end
else
begin
next_state = IDLE;
// run_traffic = 1'b0;
load_seed_o = 1'b0;
end
end
else
begin
next_state = IDLE;
// run_traffic = 1'b0;
load_seed_o = 1'b0;
end
end
SINGLE_CMD_WAIT: begin
if (single_operation&& single_read_r1 && ~single_read_r2)
next_state = SINGLE_STEP_READ;
else
next_state = SINGLE_CMD_WAIT;
fixed_instr_o = RD_INSTR;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
end
SINGLE_STEP_WRITE: begin
// run_traffic = single_instr_run_trarric;
if (memc_cmd_en_i)
next_state = IDLE;
else
next_state = SINGLE_STEP_WRITE;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
fixed_instr_o = WR_INSTR;
end
SINGLE_STEP_READ: begin //0x20
// run_traffic = single_instr_run_trarric;
if (single_operation)
next_state = SINGLE_CMD_WAIT;
else if (memc_cmd_en_i)
next_state = IDLE;
else
next_state = SINGLE_STEP_READ;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
// run_traffic = 1'b1;
addr_mode = FIXED_ADDR;
bl_mode_o = FIXED_BL_MODE;
fixed_instr_o = RD_INSTR;
end
INIT_MEM_WRITE: begin
if (end_addr_reached && EYE_TEST == "FALSE" )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
// run_traffic = 1'b1;
end
else
begin
next_state = INIT_MEM_WRITE;
// run_traffic = 1'b1;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
if (EYE_TEST == "TRUE")
addr_mode = FIXED_ADDR;
else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
if (switch_instr && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE")
fixed_instr_o = RD_INSTR;
else
fixed_instr_o = WR_INSTR;
end
end
INIT_MEM_READ: begin
if (end_addr_reached )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
end
else
begin
next_state = INIT_MEM_READ;
// run_traffic = 1'b0;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
end
end
TEST_MEM: begin
if (single_operation)
next_state = SINGLE_CMD_WAIT;
else if (cmp_error)
next_state = TEST_MEM;//CMP_ERROR;
else
next_state = TEST_MEM;
// run_traffic = 1'b1;
if (vio_modify_enable)
fixed_instr_o = vio_fixed_instr_value;
else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
fixed_instr_o = WR_INSTR;
else if (PORT_MODE == "BI_MODE" && ( TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" ||
TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE"))
fixed_instr_o = RD_INSTR;
else if (PORT_MODE == "RD_MODE")
fixed_instr_o = RD_INSTR;
else //if( PORT_MODE == "WR_MODE")
fixed_instr_o = WR_INSTR;
if ((data_mode_o == 3'b111) && FAMILY == "VIRTEX6")
fixed_bl_o = 10'd256;
else if ((FAMILY == "SPARTAN6"))
fixed_bl_o = 10'd64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o = fix_bl_value;
if (data_mode_o == 3'b111)
bl_mode_o = FIXED_BL_MODE;
else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
bl_mode_o = FIXED_BL_MODE;
else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110)
// simplify the downstream logic, data_mode is forced to FIXED_BL_MODE
// if data_mode is set to Walking 1's or Walking 0's.
bl_mode_o = FIXED_BL_MODE;
else
bl_mode_o = bl_mode_sel ;
/* if (TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
addr_mode = SEQUENTIAL_ADDR;
else if (data_mode_o == 4'b0101 || data_mode_o == 4'b0110)
// simplify the downstream logic, addr_mode is forced to SEQUENTIAL
// if data_mode is set to Walking 1's or Walking 0's.
// This ensure the starting burst address always in in the beginning
// of burst_length address for the number of DQ pins.And to ensure the
// DQ0 always asserts at the beginning of each user burst.
addr_mode = SEQUENTIAL_ADDR;
else if (bl_mode_o == PRBS_BL_MODE)
addr_mode = PRBS_ADDR;
else
addr_mode = 3'b010;*/
addr_mode = vio_addr_mode_value;
if (vio_modify_enable )
instr_mode_o = vio_instr_mode_value;
else if (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_EYE_MODE" && FAMILY == "VIRTEX6")
instr_mode_o = FIXED_INSTR_MODE;
else if(PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE != "FIXED_INSTR_R_EYE_MODE")
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;
else
instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
else //if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin
instr_mode_o = FIXED_INSTR_MODE;
end
CMP_ERROR:
begin
next_state = CMP_ERROR;
bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
fixed_instr_o = RD_INSTR;
addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR;
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;//
else
instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
// run_traffic = 1'b1; // ?? keep it running or stop if error happened
end
default:
begin
next_state = IDLE;
//run_traffic = 1'b0;
end
endcase
end
endmodule
|
// soc_system_master_secure.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2014.12.29.10:20:53
`timescale 1 ps / 1 ps
module soc_system_master_secure #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset), // resetrequest.reset
.source_ready (1'b1), // (terminated)
.mgmt_valid (), // (terminated)
.mgmt_channel (), // (terminated)
.mgmt_data (), // (terminated)
.jtag_tck (1'b0), // (terminated)
.jtag_tms (1'b0), // (terminated)
.jtag_tdi (1'b0), // (terminated)
.jtag_tdo (), // (terminated)
.jtag_ena (1'b0), // (terminated)
.jtag_usr1 (1'b0), // (terminated)
.jtag_clr (1'b0), // (terminated)
.jtag_clrn (1'b0), // (terminated)
.jtag_state_tlr (1'b0), // (terminated)
.jtag_state_rti (1'b0), // (terminated)
.jtag_state_sdrs (1'b0), // (terminated)
.jtag_state_cdr (1'b0), // (terminated)
.jtag_state_sdr (1'b0), // (terminated)
.jtag_state_e1dr (1'b0), // (terminated)
.jtag_state_pdr (1'b0), // (terminated)
.jtag_state_e2dr (1'b0), // (terminated)
.jtag_state_udr (1'b0), // (terminated)
.jtag_state_sirs (1'b0), // (terminated)
.jtag_state_cir (1'b0), // (terminated)
.jtag_state_sir (1'b0), // (terminated)
.jtag_state_e1ir (1'b0), // (terminated)
.jtag_state_pir (1'b0), // (terminated)
.jtag_state_e2ir (1'b0), // (terminated)
.jtag_state_uir (1'b0), // (terminated)
.jtag_ir_in (3'b000), // (terminated)
.jtag_irq (), // (terminated)
.jtag_ir_out () // (terminated)
);
soc_system_master_secure_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.out_data (timing_adt_out_data), // out.data
.out_valid (timing_adt_out_valid), // .valid
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_master_secure_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (b2p_out_packets_stream_data), // in.data
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_ready (b2p_out_packets_stream_ready), // .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_channel (b2p_out_packets_stream_channel), // .channel
.out_data (b2p_adapter_out_data), // out.data
.out_valid (b2p_adapter_out_valid), // .valid
.out_ready (b2p_adapter_out_ready), // .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_master_secure_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_data (transacto_out_stream_data), // in.data
.in_valid (transacto_out_stream_valid), // .valid
.in_ready (transacto_out_stream_ready), // .ready
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_data (p2b_adapter_out_data), // out.data
.out_valid (p2b_adapter_out_valid), // .valid
.out_ready (p2b_adapter_out_ready), // .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// Wishbone arbiter, burst-compatible ////
/// ////
/// Simple round-robin arbiter for multiple Wishbone masters ////
/// ////
/// Olof Kindgren, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module wb_arbiter
#(parameter dw = 32,
parameter aw = 32,
parameter num_masters = 2)
(
input wb_clk_i,
input wb_rst_i,
// Wishbone Master Interface
input [num_masters*aw-1:0] wbm_adr_i,
input [num_masters*dw-1:0] wbm_dat_i,
input [num_masters*4-1:0] wbm_sel_i,
input [num_masters-1:0] wbm_we_i,
input [num_masters-1:0] wbm_cyc_i,
input [num_masters-1:0] wbm_stb_i,
input [num_masters*3-1:0] wbm_cti_i,
input [num_masters*2-1:0] wbm_bte_i,
output [num_masters*dw-1:0] wbm_dat_o,
output [num_masters-1:0] wbm_ack_o,
output [num_masters-1:0] wbm_err_o,
output [num_masters-1:0] wbm_rty_o,
// Wishbone Slave interface
output [aw-1:0] wbs_adr_o,
output [dw-1:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
output [2:0] wbs_cti_o,
output [1:0] wbs_bte_o,
input [dw-1:0] wbs_dat_i,
input wbs_ack_i,
input wbs_err_i,
input wbs_rty_i);
`include "verilog_utils.vh"
///////////////////////////////////////////////////////////////////////////////
// Parameters
///////////////////////////////////////////////////////////////////////////////
localparam master_sel_bits = num_masters > 1 ? `clog2(num_masters) : 1;
wire [num_masters-1:0] grant;
wire [master_sel_bits-1:0] master_sel;
wire active;
arbiter
#(.NUM_PORTS (num_masters))
arbiter0
(.clk (wb_clk_i),
.rst (wb_rst_i),
.request (wbm_cyc_i),
.grant (grant),
.select (master_sel),
.active (active));
//Mux active master
assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
assign wbs_we_o = wbm_we_i [master_sel];
assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
assign wbs_stb_o = wbm_stb_i[master_sel];
assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
assign wbm_dat_o = {num_masters{wbs_dat_i}};
assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
assign wbm_err_o = ((wbs_err_i & active) << master_sel);
assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
endmodule // wb_arbiter
|
//////////////////////////////////////////////////////////////////////////////////
// Completion for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Completion
// Module Name: Completion
// File Name: Completion.v
//
// Version: v1.0.0
//
// Description: Reports completion of an operation
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Completion
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 1
)
(
iClock ,
iReset ,
iSrcOpcode ,
iSrcTargetID ,
iSrcSourceID ,
iSrcAddress ,
iSrcLength ,
iSrcCmdValid ,
oSrcCmdReady ,
iSrcWriteData ,
iSrcWriteValid ,
iSrcWriteLast ,
oSrcWriteReady ,
oDstOpcode ,
oDstTargetID ,
oDstSourceID ,
oDstAddress ,
oDstLength ,
oDstCmdValid ,
iDstCmdReady ,
oDstWriteData ,
oDstWriteValid ,
oDstWriteLast ,
iDstWriteReady
);
input iClock ;
input iReset ;
// Master side
input [5:0] iSrcOpcode ;
input [4:0] iSrcTargetID ;
input [4:0] iSrcSourceID ;
input [AddressWidth - 1:0] iSrcAddress ;
input [InnerIFLengthWidth - 1:0] iSrcLength ;
input iSrcCmdValid ;
output oSrcCmdReady ;
input [DataWidth - 1:0] iSrcWriteData ;
input iSrcWriteValid ;
input iSrcWriteLast ;
output oSrcWriteReady ;
// Slave side
output [5:0] oDstOpcode ;
output [4:0] oDstTargetID ;
output [4:0] oDstSourceID ;
output [AddressWidth - 1:0] oDstAddress ;
output [InnerIFLengthWidth - 1:0] oDstLength ;
output oDstCmdValid ;
input iDstCmdReady ;
output [DataWidth - 1:0] oDstWriteData ;
output oDstWriteValid ;
output oDstWriteLast ;
input iDstWriteReady ;
wire wDataChReady ;
CompletionCommandChannel
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.ThisID (ThisID )
)
Inst_CompletionCommandChannel
(
.iClock (iClock ),
.iReset (iReset ),
.iSrcOpcode (iSrcOpcode ),
.iSrcTargetID (iSrcTargetID ),
.iSrcSourceID (iSrcSourceID ),
.iSrcAddress (iSrcAddress ),
.iSrcLength (iSrcLength ),
.iSrcCmdValid (iSrcCmdValid ),
.oSrcCmdReady (oSrcCmdReady ),
.oDstOpcode (oDstOpcode ),
.oDstTargetID (oDstTargetID ),
.oDstSourceID (oDstSourceID ),
.oDstAddress (oDstAddress ),
.oDstLength (oDstLength ),
.oDstCmdValid (oDstCmdValid ),
.iDstCmdReady (iDstCmdReady ),
.iSrcValidCond (wDataChReady )
);
CompletionDataChannel
#
(
.DataWidth (DataWidth ),
.InnerIFLengthWidth (InnerIFLengthWidth ),
.ThisID (ThisID )
)
Inst_CompletionDataChannel
(
.iClock (iClock ),
.iReset (iReset ),
.iSrcLength (iSrcLength ),
.iSrcTargetID (iSrcTargetID ),
.iSrcValid (iSrcCmdValid && oSrcCmdReady ),
.oSrcReady (wDataChReady ),
.iSrcWriteData (iSrcWriteData ),
.iSrcWriteValid (iSrcWriteValid ),
.iSrcWriteLast (iSrcWriteLast ),
.oSrcWriteReady (oSrcWriteReady ),
.oDstWriteData (oDstWriteData ),
.oDstWriteValid (oDstWriteValid ),
.oDstWriteLast (oDstWriteLast ),
.iDstWriteReady (iDstWriteReady )
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_M_V
`define SKY130_FD_SC_LP__AND3_M_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_m (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_M_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:27 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_cfg_fe1.v,v 1.8 2005/12/14 15:43:45 lutscher Exp $
// $Date: 2005/12/14 15:43:45 $
// $Log: rs_cfg_fe1.v,v $
// Revision 1.8 2005/12/14 15:43:45 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1
//
// Generated module rs_cfg_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire test_i,
input wire [13:0] addr_i,
input wire trans_start,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output reg usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output reg [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output reg usr_rw_test_rd_p_o,
output reg usr_rw_test_wr_p_o,
output reg [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i
);
// Module parameters:
parameter sync = 0;
parameter cgtransp = 0;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire int_upd_r_p;
wire int_upd_rw_p;
wire tie0_1;
wire u6_sync_generic_i_trans_start_p;
wire u7_sync_rst_i_int_rst_n;
wire u8_ccgc_iwr_clk;
wire u8_ccgc_iwr_clk_en;
wire u9_ccgc_ishdw_clk;
wire u9_ccgc_ishdw_clk_en;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign tie0_1 = `tie0_1_c;
/*
Generator information:
used package Micronas::Reg is version 1.16
this module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [7:0] sha_r_test_shdw;
reg [31:0] REG_0C;
wire [5:0] mvstop_shdw;
reg [31:0] REG_10;
reg [31:0] REG_14;
wire [31:0] sha_rw2_shdw;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
reg [31:0] REG_28;
reg int_upd_rw;
reg int_upd_r;
wire wr_p;
wire rd_p;
reg int_trans_done;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg rd_done_p;
reg wr_done_p;
reg fwd_txn;
wire [1:0] fwd_decode_vec;
wire [1:0] fwd_done_vec;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign Cvbsdetect_par_o = REG_04[0];
assign mvstop_shdw = REG_0C[10:5];
assign mvstart_par_o = REG_0C[4:0];
assign sha_rw2_shdw = REG_14;
assign wd_16_test_par_o = REG_18[15:0];
assign wd_16_test2_par_o = REG_1C[7:0];
assign usr_rw_test_par_o = wr_data_i[14:11];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
/*
clock enable signals
*/
assign u8_ccgc_iwr_clk_en = wr_p; // write-clock enable
assign u9_ccgc_ishdw_clk_en = int_upd_rw | int_upd_r; // shadow-clock enable
// write txn start pulse
assign wr_p = ~rd_wr_i & u6_sync_generic_i_trans_start_p;
// read txn start pulse
assign rd_p = rd_wr_i & u6_sync_generic_i_trans_start_p;
/*
generate txn done signals
*/
assign fwd_done_vec = {usr_r_test_trans_done_p_i, usr_rw_test_trans_done_p_i}; // ack for forwarded txns
assign trans_done_p = ((wr_done_p | rd_done_p) & ~fwd_txn) | ((fwd_done_vec != 0) & fwd_txn);
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
wr_done_p <= 0;
rd_done_p <= 0;
end
else begin
wr_done_p <= wr_p;
rd_done_p <= rd_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
write process
*/
always @(posedge u8_ccgc_iwr_clk or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
REG_0C[10:5] <= 'hc;
REG_0C[4:0] <= 'h7;
REG_14 <= 'h0;
REG_18[15:0] <= 'ha;
REG_1C[7:0] <= 'hff;
end
else begin
case (iaddr)
`REG_0C_OFFS: begin
REG_0C[10:5] <= wr_data_i[10:5];
REG_0C[4:0] <= wr_data_i[4:0];
end
`REG_14_OFFS: begin
REG_14 <= wr_data_i;
end
`REG_18_OFFS: begin
REG_18[15:0] <= wr_data_i[15:0];
end
`REG_1C_OFFS: begin
REG_1C[7:0] <= wr_data_i[7:0];
end
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
REG_04[0] <= 'h0;
end
else begin
if (Cvbsdetect_set_p_i)
REG_04[0] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS)
REG_04[0] <= REG_04[0] & ~wr_data_i[0];
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_08_OFFS) & rd_wr_i, (iaddr == `REG_10_OFFS)};
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
end
else begin
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
if (u6_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_r_test_rd_p_o <= fwd_decode_vec[1] & rd_wr_i;
usr_rw_test_rd_p_o <= fwd_decode_vec[0] & rd_wr_i;
usr_rw_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_rw'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n)
int_upd_rw <= 1;
else
int_upd_rw <= (int_upd_rw_p & upd_rw_en_i) | upd_rw_force_i;
end
// shadow process
always @(posedge u9_ccgc_ishdw_clk) begin
if (int_upd_rw) begin
mvstop_par_o <= mvstop_shdw;
sha_rw2_par_o <= sha_rw2_shdw;
end
end
/*
shadowing for update signal 'upd_r'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u7_sync_rst_i_int_rst_n) begin
if (~u7_sync_rst_i_int_rst_n)
int_upd_r <= 1;
else
int_upd_r <= (int_upd_r_p & upd_r_en_i) | upd_r_force_i;
end
// shadow process
always @(posedge u9_ccgc_ishdw_clk) begin
if (int_upd_r) begin
sha_r_test_shdw <= sha_r_test_par_i;
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @(REG_04 or REG_0C or REG_18 or iaddr or mvstop_shdw or sha_r_test_shdw or sha_rw2_shdw or usr_r_test_par_i or usr_rw_test_par_i or ycdetect_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_04_OFFS : begin
mux_rd_data[0] <= REG_04[0];
end
`REG_08_OFFS : begin
mux_rd_data[1] <= ycdetect_par_i;
mux_rd_data[2] <= usr_r_test_par_i;
mux_rd_data[10:3] <= sha_r_test_shdw;
end
`REG_0C_OFFS : begin
mux_rd_data[4:0] <= REG_0C[4:0];
mux_rd_data[10:5] <= mvstop_shdw;
end
`REG_10_OFFS : begin
mux_rd_data[14:11] <= usr_rw_test_par_i;
end
`REG_14_OFFS : begin
mux_rd_data <= sha_rw2_shdw;
end
`REG_18_OFFS : begin
mux_rd_data[15:0] <= REG_18[15:0];
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert property(p_pos_pulse_check(Cvbsdetect_set_p_i));
assert property(p_pos_pulse_check(usr_r_test_trans_done_p_i));
assert property(p_pos_pulse_check(usr_rw_test_trans_done_p_i));
p_fwd_done_expected: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> fwd_txn
);
p_fwd_done_onehot: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> onehot(fwd_done_vec)
);
p_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_f20) disable iff (~u7_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [1:0] vec); // not built-in to SV yet
integer i,j;
begin
j = 0;
for (i=0; i<2; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
`endif
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for u10_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u10_sync_generic_i ( // Synchronizer for update-signal upd_rw
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_rw_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_rw_i)
);
// End of Generated Instance Port Map for u10_sync_generic_i
// Generated Instance Port Map for u11_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u11_sync_generic_i ( // Synchronizer for update-signal upd_r
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_r_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_r_i)
);
// End of Generated Instance Port Map for u11_sync_generic_i
// Generated Instance Port Map for u6_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(0)
) u6_sync_generic_i ( // Synchronizer for trans_done signal
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u6_sync_generic_i_trans_start_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(trans_start)
);
// End of Generated Instance Port Map for u6_sync_generic_i
// Generated Instance Port Map for u7_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u7_sync_rst_i ( // Reset synchronizer
.clk_r(clk_f20),
.rst_i(res_f20_n_i),
.rst_o(u7_sync_rst_i_int_rst_n)
);
// End of Generated Instance Port Map for u7_sync_rst_i
// Generated Instance Port Map for u8_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u8_ccgc_i ( // Clock-gating cell for write-clock
.clk_i(clk_f20),
.clk_o(u8_ccgc_iwr_clk),
.enable_i(u8_ccgc_iwr_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u8_ccgc_i
// Generated Instance Port Map for u9_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u9_ccgc_i ( // Clock-gating cell for shadow-clock
.clk_i(clk_f20),
.clk_o(u9_ccgc_ishdw_clk),
.enable_i(u9_ccgc_ishdw_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u9_ccgc_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Titor - Preshift - Prepares signals for input into the butterfly unit
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_PRESHIFT
`else
`define INC_PRESHIFT
`timescale 1 ns / 100 ps
// This module handles most of the messy junk that goes into the butterfly unit
// There are some nasty things still in it but the non-recyclables are here
module Preshift (
boperand,
bamount,
btype,
bopcode,
immediate,
reg1,
reg2,
reg3,
shift_I,
shift_IR,
shift_type,
swapshift,
amount,
enable
);
`include "definition/Definition.v"
output reg [WORD-1:0] boperand; // the argument to be shifted or swapped by the butterfly unit
output reg [WORD-1:0] bamount; // the amount or control bits by which to shift in the butterfly unit
output reg [WORD-1:0] btype; // whether to do a shift or swap type operation
output reg [WORD-1:0] bopcode; // what type of swap or shift operation
input [WORD-1:0] immediate; // the immedaite value in the instruction
input [WORD-1:0] reg1; // reg1
input [WORD-1:0] reg2; // reg2
input [WORD-1:0] reg3; // reg3
input [WORD-1:0] shift_I; // the instruction-immediate value
input [WIDTH_SHIFT_IR-1:0] shift_IR; // the instruction flag indicating if a shift is controlled by an imm or reg value
input [WIDTH_SHIFT_TYPE-1:0] shift_type; // the instruction code indicating the kind of shift/rotate
input swapshift; // choose between swap or shift operations
input [WORD-1:0] amount; // the control path value dictating a swap
input enable; // if false just pass reg2 through this and the butterfly unit unharmed
always @(*) begin
if(enable) begin
case(swapshift)
PS_SWAP: begin
boperand <= reg1 | immediate;
bamount <= amount;
btype <= PS_SWAP;
bopcode <= 0;
end
PS_SHIFT: begin
boperand <= reg2;
case(shift_IR)
IMM: bamount <= shift_I;
REG: bamount <= reg3;
default bamount <= 0;
endcase
btype <= PS_SHIFT;
bopcode <= shift_type;
end
default: begin
boperand <= 0;
bamount <= 0;
btype <= 0;
bopcode <= 0;
end
endcase
end
else begin
boperand <= reg2;
bamount <= 0;
btype <= PS_SWAP;
bopcode <= 0;
end
end
endmodule
`endif
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_8_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter PO_TAP_DLY = 2 // # of PO fine taps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output po_dly_req,
output po_dly_load,
output [5:0] po_dec_dly_cnt,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
input prech_done,
input tg_err,
input tg_timer_done,
input po_dly_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
// Stage 2 calibration inputs/outputs
// Upto 3 coarse delay taps and 22 fine delay taps
// used during write calibration
// Inc Phaser_Out coarse delay line
(* keep = "true", max_fanout = 3 *) output reg dqs_po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_po_en_stg2_c,
// Inc/dec Phaser_Out fine delay line
output reg dqs_wcal_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_wcal_po_en_stg2_f,
output wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
localparam PO_DLY_CNT = 16/PO_TAP_DLY;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 5'h0;
localparam CAL2_READ_WAIT = 5'h1;
localparam CAL2_DETECT_MATCH = 5'h2;
localparam CAL2_CORSE_INC = 5'h3;
localparam CAL2_CORSE_INC_WAIT = 5'h4;
localparam CAL2_FINE_INC = 5'h5;
localparam CAL2_FINE_INC_WAIT = 5'h6;
localparam CAL2_NEXT_DQS = 5'h7;
localparam CAL2_DONE = 5'h8;
localparam CAL2_ERR = 5'h9;
localparam CAL2_DQSFOUND = 5'hA;
localparam CAL2_DQSFOUND_WAIT = 5'hB;
localparam CAL2_DEC_TAPS = 5'hC;
localparam CAL2_CORSE_DEC = 5'hD;
localparam CAL2_CORSE_DEC_WAIT = 5'hE;
localparam CAL2_FINE_DEC = 5'hF;
localparam CAL2_FINE_DEC_WAIT = 5'h10;
localparam CAL2_READS = 5'h11;
localparam CAL2_PREWAIT_PO_DLY = 5'h12;
localparam CAL2_PO_DLY = 5'h13;
localparam CAL2_PREWAIT_READS = 5'h14;
localparam CAL2_READS_WAIT = 5'h15;
localparam CAL2_WAIT_ERR_DETECT = 5'h16;
localparam CAL2_CALC_PO_DLY = 5'h17;
localparam CAL2_DEC_PO_DLY = 5'h18;
localparam CAL2_DQ_IDEL_DEC = 5'h19;
localparam CAL2_WRLVL_WAIT = 5'h1A;
localparam CAL2_IFIFO_RESET = 5'h1B;
integer i,j,k,l,m;
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt;
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt;
(* keep = "true", max_fanout = 10 *) reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] retry_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_done_r2;
reg cal2_done_r3;
reg cal2_prech_req_r;
reg [4:0] cal2_state_r;
reg [4:0] cal2_state_r1;
reg [3*DQS_WIDTH-1:0] cal2_corse_cnt;
reg [5:0] cal2_fine_cnt [0:DQS_WIDTH-1];
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg [2:0] cal2_rd_cnt;
reg [PO_DLY_CNT:0] cal2_pass_fail;
reg [4:0] stable_pass_cnt;
reg [4:0] pass_start_index;
reg restart_stable_cnt;
reg [4:0] stable_pass_cnt1;
reg [4:0] pass_start_index1;
reg restart_stable_cnt1;
reg [DQS_WIDTH-1:0] no_po_fine_taps_left;
reg cal2_read_req;
reg cal2_po_dly_req;
reg cal2_po_dly_load;
reg [4:0] cal2_po_dly_cnt;
reg [5:0] po_dec_cnt;
reg po_dec_done;
reg cal2_if_reset;
reg [2:0] dec_cnt;
reg dec_taps;
reg dqsfound_again;
reg dqs_po_stg2_c_incdec_r;
reg dqs_po_en_stg2_c_r;
reg dqs_wcal_po_stg2_f_incdec_r;
reg dqs_wcal_po_en_stg2_f_r;
reg [5:0] fine_inc_cnt;
reg [5:0] fine_dec_cnt;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [3:0] cnt_rden_wait_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg rden_wait_r;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt;
assign dbg_phy_wrcal[0] = pat_data_match_r;
assign dbg_phy_wrcal[5:1] = cal2_state_r[4:0];
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = stable_pass_cnt;
assign dbg_phy_wrcal[22+:5] = cal2_po_dly_cnt;
assign dbg_phy_wrcal[27] = cal2_read_req;
assign dbg_phy_wrcal[28+:5] = pass_start_index;
assign dbg_phy_wrcal[33+:PO_DLY_CNT+1] = cal2_pass_fail;
assign dbg_phy_wrcal[54] = restart_stable_cnt;
assign dbg_phy_wrcal[55+:5] = stable_pass_cnt1;
assign dbg_phy_wrcal[60] = |no_po_fine_taps_left;
assign dbg_phy_wrcal[61+:5] = pass_start_index1;
assign dbg_phy_wrcal[66+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[71] = early1_data;
assign dbg_phy_wrcal[72] = early2_data;
assign dqsfound_retry = dqsfound_again;
assign po_dly_req = cal2_po_dly_req;
assign po_dly_load = cal2_po_dly_load;
assign wrcal_read_req = cal2_read_req;
assign phy_if_reset = cal2_if_reset;
assign po_dec_dly_cnt = po_dec_cnt;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
po_coarse_tap_cnt <= #TCQ {3*DQS_WIDTH{1'b0}};
po_fine_tap_cnt <= #TCQ {6*DQS_WIDTH{1'b0}};
end else if (cal2_done_r && ~cal2_done_r1) begin
for (i = 0; i < DQS_WIDTH; i = i + 1) begin
po_coarse_tap_cnt[3*i+:3] <= #TCQ
(cal2_corse_cnt[3*i+:3] + wl_po_coarse_cnt_w[i]);
po_fine_tap_cnt[6*i+:6] <= #TCQ
(cal2_fine_cnt[i] + wl_po_fine_cnt_w[i]);
end
end
end
always @(posedge clk) begin
if (rst)
no_po_fine_taps_left <= #TCQ {DQS_WIDTH{1'b0}};
else if ((PRE_REV3ES == "ON") && (cal2_state_r == CAL2_NEXT_DQS) &&
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
for (k = 0; k < DQS_WIDTH; k = k + 1) begin
if ((cal2_fine_cnt[k] + wl_po_fine_cnt_w[k]) > 'd43)
no_po_fine_taps_left[k] <= #TCQ 1'b1;
else
no_po_fine_taps_left[k] <= #TCQ 1'b0;
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
//{sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
//{sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
//{sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
//{sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],mux_rd_fall1_r[rd_i]};
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
//if (wrcal_start && (cal2_state_r == CAL2_READ_WAIT)) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
rd_active_posedge_r <= #TCQ phy_rddata_en & ~rd_active_r;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Generic counter to force wait after read_en is issued
// Have to re-visit this logic based on IN_FIFO timing
always @(posedge clk)
if (rst || ((cal2_state_r == CAL2_READ_WAIT)
&& (cnt_rden_wait_r == 'b1)))
cnt_rden_wait_r <= #TCQ 'b0;
else if (rd_active_posedge_r)
cnt_rden_wait_r <= #TCQ RDEN_WAIT_CNT;
else if (cnt_rden_wait_r > 'b1)
cnt_rden_wait_r <= #TCQ cnt_rden_wait_r - 1;
always @(posedge clk)
if (rst || (cnt_rden_wait_r == 'b1))
rden_wait_r <= #TCQ 1'b0;
else if (cal2_state_r != CAL2_READ_WAIT)
rden_wait_r <= #TCQ 1'b1;
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume_r3 <= #TCQ wrcal_pat_resume_r2;
end
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
assign wrcal_pat_resume = wrcal_pat_resume_r3;
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write calibration
dqs_po_stg2_c_incdec_r <= #TCQ 1'b0;
dqs_po_en_stg2_c_r <= #TCQ 1'b0;
// Inc Phaser_Out coarse delay during write calibration
end else if (cal2_state_r == CAL2_CORSE_INC) begin
dqs_po_stg2_c_incdec_r <= #TCQ 1'b1;
dqs_po_en_stg2_c_r <= #TCQ 1'b1;
end else if (cal2_state_r == CAL2_CORSE_DEC) begin
dqs_po_stg2_c_incdec_r <= #TCQ 1'b0;
dqs_po_en_stg2_c_r <= #TCQ 1'b1;
end else begin
dqs_po_stg2_c_incdec_r <= #TCQ 1'b0;
dqs_po_en_stg2_c_r <= #TCQ 1'b0;
end
end
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
dqs_wcal_po_stg2_f_incdec_r <= #TCQ 1'b0;
dqs_wcal_po_en_stg2_f_r <= #TCQ 1'b0;
// Inc Fine delay line
end else if (cal2_state_r == CAL2_FINE_INC) begin
dqs_wcal_po_stg2_f_incdec_r <= #TCQ 1'b1;
dqs_wcal_po_en_stg2_f_r <= #TCQ 1'b1;
end else if (cal2_state_r == CAL2_FINE_DEC) begin
dqs_wcal_po_stg2_f_incdec_r <= #TCQ 1'b0;
dqs_wcal_po_en_stg2_f_r <= #TCQ 1'b1;
end else begin
dqs_wcal_po_stg2_f_incdec_r <= #TCQ 1'b0;
dqs_wcal_po_en_stg2_f_r <= #TCQ 1'b0;
end
end // always @ (posedge clk)
// registering for timing
always @(posedge clk) begin
dqs_po_stg2_c_incdec <= #TCQ dqs_po_stg2_c_incdec_r;
dqs_po_en_stg2_c <= #TCQ dqs_po_en_stg2_c_r;
dqs_wcal_po_stg2_f_incdec <= #TCQ dqs_wcal_po_stg2_f_incdec_r;
dqs_wcal_po_en_stg2_f <= #TCQ dqs_wcal_po_en_stg2_f_r;
end // always @ (posdege clk)
/* // This counter used to implement settling time for
// Phaser_Out fine delay line after final_val
// loaded for different DQSs
always @(posedge clk) begin
if (rst || ((wrcal_regl_dqs_cnt == DQS_WIDTH-1)
&& (wrcal_done_cnt == 4'd1)))
wrcal_done_cnt <= #TCQ 'b0;
else if ((cal2_done_r && ~cal2_done_r1)
|| (wrcal_done_cnt == 4'd1))
wrcal_done_cnt <= #TCQ 4'b1010;
else if (wrcal_done_cnt > 'b0)
wrcal_done_cnt <= #TCQ wrcal_done_cnt - 1;
end
always @(posedge clk) begin
if (rst || (wrcal_done_cnt == 4'd0))
wrcal_regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
else if (cal2_done_r && (wrcal_regl_dqs_cnt != DQS_WIDTH-1)
&& (wrcal_done_cnt == 4'd1))
wrcal_regl_dqs_cnt <= #TCQ wrcal_regl_dqs_cnt + 1;
else
wrcal_regl_dqs_cnt <= #TCQ wrcal_regl_dqs_cnt;
end
// Load Phaser_OUT register with final delay value.
// For multi-rank systems same value used for all
// ranks from single Phaser_OUT register.
always @(posedge clk) begin
if (rst || (wrcal_done_cnt == 4'd0)) begin
dqs_po_stg2_load <= #TCQ 'b0;
dqs_po_stg2_reg_l <= #TCQ 'b0;
end else if (cal2_done_r && (wrcal_regl_dqs_cnt <= DQS_WIDTH-1)
&& (wrcal_done_cnt == 4'd2)) begin
dqs_po_stg2_load <= #TCQ 'b1;
dqs_po_stg2_reg_l <= #TCQ {(cal2_corse_cnt[3*wrcal_regl_dqs_cnt+:3] + wl_po_coarse_cnt[3*wrcal_regl_dqs_cnt+:3]),
wl_po_fine_cnt[6*wrcal_regl_dqs_cnt+:6]};
end else begin
dqs_po_stg2_load <= #TCQ 'b0;
dqs_po_stg2_reg_l <= #TCQ 'b0;
end
end */
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_CORSE_INC_WAIT) ||
(cal2_state_r == CAL2_PREWAIT_PO_DLY) ||
(cal2_state_r == CAL2_PREWAIT_READS) ||
(cal2_state_r == CAL2_CALC_PO_DLY) ||
(cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
retry_cnt <= #TCQ 'd0;
else if (dqsfound_again)
retry_cnt <= #TCQ retry_cnt + 1;
end
always @(posedge clk) begin
if (rst || ~dqsfound_retry_done)
dec_taps <= #TCQ 1'b0;
else if (dqsfound_again)
dec_taps <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst ||
((cal2_rd_cnt == 'd0) && ~rd_active_r3 && rd_active_r4 &&
(cal2_state_r == CAL2_READS)) ||
(cal2_state_r == CAL2_PREWAIT_PO_DLY))
cal2_rd_cnt <= #TCQ NUM_READS;
else if (~rd_active_r3 && rd_active_r4 &&
(cal2_rd_cnt > 'd0) && (cal2_state_r == CAL2_READS))
cal2_rd_cnt <= #TCQ cal2_rd_cnt - 1;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
cal2_corse_cnt <= #TCQ {3*DQS_WIDTH{1'b0}};
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
cal2_fine_cnt[l] <= #TCQ {6{1'b0}};
end
dec_cnt <= #TCQ 'd0;
fine_dec_cnt <= #TCQ 'd0;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
dqsfound_again <= #TCQ 1'b0;
cal2_read_req <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_po_dly_cnt <= #TCQ 'd0;
cal2_po_dly_req <= #TCQ 1'b0;
cal2_po_dly_load <= #TCQ 1'b0;
po_dec_cnt <= #TCQ 'd0;
po_dec_done <= #TCQ 1'b0;
cal2_pass_fail <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
restart_stable_cnt <= #TCQ 1'b1;
pass_start_index <= #TCQ 'd0;
stable_pass_cnt1 <= #TCQ 'd0;
restart_stable_cnt1 <= #TCQ 1'b1;
pass_start_index1 <= #TCQ 'd0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
CAL2_CORSE_INC: begin
cal2_state_r <= #TCQ CAL2_CORSE_INC_WAIT;
cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3] <=
#TCQ cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3] + 1;
end
CAL2_CORSE_INC_WAIT: begin
// Add 1 memory clock cycle of delay to DQS and DQ
// 1 memory clock cycle of delay is obtained by
// adding 3 coarse delay taps and 22 fine delay taps
if (tap_inc_wait_cnt == 'd4) begin
if (cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3] == COARSE_CNT) begin
cal2_state_r <= #TCQ CAL2_FINE_INC;
if (|wl_po_coarse_cnt_w[wrcal_dqs_cnt_r]) begin
cal2_fine_cnt[wrcal_dqs_cnt_r] <= #TCQ (FINE_CNT - 2);
fine_inc_cnt <= #TCQ (FINE_CNT - 2);
end else begin
cal2_fine_cnt[wrcal_dqs_cnt_r] <= #TCQ FINE_CNT;
fine_inc_cnt <= #TCQ FINE_CNT;
end
end else begin
cal2_state_r <= #TCQ CAL2_CORSE_INC;
end
end
end
CAL2_FINE_INC: begin
cal2_state_r <= #TCQ CAL2_FINE_INC_WAIT;
fine_inc_cnt <= #TCQ fine_inc_cnt - 1;
end
CAL2_FINE_INC_WAIT: begin
if (fine_inc_cnt == 'd0) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end else begin
cal2_state_r <= #TCQ CAL2_FINE_INC;
// wrcal_pat_resume_r only asserted once per DQS since we do
// not forsee using more than a clock cycle of delay in this
// stage of calibration.
wrcal_pat_resume_r <= #TCQ 1'b0;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
// Addded state CAL2_WAIT_ERR_DETECT and param PRE_REV3ES
// Delays all POs in the PHY by the same amount
if ((PRE_REV3ES == "ON") && ~(|no_po_fine_taps_left)) begin
temp_wrcal_done <= #TCQ 1'b1;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_WAIT_ERR_DETECT;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// Addded state CAL2_WAIT_ERR_DETECT and param PRE_REV3ES
// Multiple non-back-to-back reads issued to ensure reliable
// data capture
CAL2_WAIT_ERR_DETECT: begin
if (tg_err || tg_timer_done) begin
if (tg_err) begin
cal2_pass_fail[1*cal2_po_dly_cnt] <= #TCQ 1'b1;
if (stable_pass_cnt < 'd3) begin
stable_pass_cnt <= #TCQ 'd0;
restart_stable_cnt <= #TCQ 1'b1;
end else begin
stable_pass_cnt <= #TCQ stable_pass_cnt;
restart_stable_cnt <= #TCQ 1'b0;
end
if (stable_pass_cnt1 < 'd3) begin
stable_pass_cnt1 <= #TCQ 'd0;
restart_stable_cnt1 <= #TCQ 1'b1;
end else begin
stable_pass_cnt1 <= #TCQ stable_pass_cnt1;
restart_stable_cnt1 <= #TCQ 1'b0;
end
end else begin
cal2_pass_fail[1*cal2_po_dly_cnt] <= #TCQ 1'b0;
if (restart_stable_cnt) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if (stable_pass_cnt == 'd0)
pass_start_index <= #TCQ cal2_po_dly_cnt;
end
if (restart_stable_cnt1 && ~restart_stable_cnt) begin
stable_pass_cnt1 <= #TCQ stable_pass_cnt1 + 1;
if (stable_pass_cnt1 == 'd0)
pass_start_index1 <= #TCQ cal2_po_dly_cnt;
end
end
temp_wrcal_done <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
if (cal2_po_dly_cnt < PO_DLY_CNT) begin
cal2_state_r <= #TCQ CAL2_PREWAIT_PO_DLY;
cal2_po_dly_load <= #TCQ 1'b1;
end else if (~po_dec_done) begin
wrcal_pat_err <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_CALC_PO_DLY;
end else begin
if (tg_err)
cal2_state_r <= #TCQ CAL2_ERR;
else
cal2_state_r <= #TCQ CAL2_DONE;
end
end
end
CAL2_READS: begin
cal2_if_reset <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
if (pat_data_match_valid_r) begin
if (pat_data_match_r) begin
// No data errors during multiple reads for current byte
if (cal2_rd_cnt > 'd0) begin
cal2_read_req <= #TCQ 1'b1;
if (~rd_active_r3 && rd_active_r4)
cal2_state_r <= #TCQ CAL2_PREWAIT_READS;
// No data errors during multiple reads for all bytes
end else if (wrcal_dqs_cnt_r == DQS_WIDTH-1) begin
cal2_read_req <= #TCQ 1'b0;
if (~rd_active_r3 && rd_active_r4 && (cal2_rd_cnt == 'd0)) begin
if (~po_dec_done)
cal2_state_r <= #TCQ CAL2_WAIT_ERR_DETECT;
else
cal2_state_r <= #TCQ CAL2_DONE;
temp_wrcal_done <= #TCQ 1'b1;
end
// No data errors during multiple reads for current byte
// Proceed to next byte
end else if (cal2_rd_cnt == 'd0) begin
cal2_read_req <= #TCQ 1'b0;
if (~rd_active_r3 && rd_active_r4) begin
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_PREWAIT_READS;
end
end
// Data errors found during multiple reads for current byte
// Delay outputs using Phaser_Out and redo reads
end else begin
cal2_read_req <= #TCQ 1'b0;
cal2_pass_fail[1*cal2_po_dly_cnt] <= #TCQ 1'b1;
if (stable_pass_cnt < 'd3) begin
stable_pass_cnt <= #TCQ 'd0;
restart_stable_cnt <= #TCQ 1'b1;
end else begin
stable_pass_cnt <= #TCQ stable_pass_cnt;
restart_stable_cnt <= #TCQ 1'b0;
end
if (stable_pass_cnt1 < 'd3) begin
stable_pass_cnt1 <= #TCQ 'd0;
restart_stable_cnt1 <= #TCQ 1'b1;
end else begin
stable_pass_cnt1 <= #TCQ stable_pass_cnt1;
restart_stable_cnt1 <= #TCQ 1'b0;
end
if (cal2_po_dly_cnt < PO_DLY_CNT) begin
cal2_state_r <= #TCQ CAL2_PREWAIT_PO_DLY;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_po_dly_load <= #TCQ 1'b1;
end else if (~po_dec_done) begin
cal2_state_r <= #TCQ CAL2_CALC_PO_DLY;
wrcal_dqs_cnt_r <= #TCQ 'd0;
end else begin
cal2_state_r <= #TCQ CAL2_ERR;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r;
end
end
end
end
CAL2_PREWAIT_PO_DLY: begin
cal2_if_reset <= #TCQ 1'b1;
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_PO_DLY;
cal2_po_dly_load <= #TCQ 1'b0;
end
end
CAL2_PO_DLY: begin
cal2_if_reset <= #TCQ 1'b0;
if (po_dly_done) begin
cal2_po_dly_req <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_PREWAIT_READS;
wrcal_act_req <= #TCQ 1'b1;
//cal2_state_r <= #TCQ CAL2_WAIT_ERR_DETECT;
cal2_po_dly_cnt <= #TCQ cal2_po_dly_cnt + 1;
end else begin
cal2_po_dly_req <= #TCQ 1'b1;
end
end
CAL2_PREWAIT_READS: begin
cal2_read_req <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
if (pat_data_match_valid_r && ~pat_data_match_r && ~po_dly_done &&
(cal2_po_dly_cnt < PO_DLY_CNT))
cal2_state_r <= #TCQ CAL2_PREWAIT_PO_DLY;
else if (tap_inc_wait_cnt == 'd4)
cal2_state_r <= #TCQ CAL2_READS_WAIT;
end
CAL2_READS_WAIT: begin
//cal2_if_reset <= #TCQ 1'b0;
cal2_read_req <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READS;
end
CAL2_CALC_PO_DLY: begin
cal2_if_reset <= #TCQ 1'b1;
if (tap_inc_wait_cnt == 'd15) begin
if ((stable_pass_cnt >= 'd3) || (stable_pass_cnt1 >= 'd3)) begin
cal2_state_r <= #TCQ CAL2_DEC_PO_DLY;
if (stable_pass_cnt > stable_pass_cnt1)
po_dec_cnt <= #TCQ 16 - (PO_TAP_DLY *
(pass_start_index + (stable_pass_cnt/2)));
else
po_dec_cnt <= #TCQ 16 - (PO_TAP_DLY *
(pass_start_index1 + (stable_pass_cnt1/2)));
end else begin
cal2_state_r <= #TCQ CAL2_ERR;
end
end
end
CAL2_DEC_PO_DLY: begin
cal2_if_reset <= #TCQ 1'b0;
if (po_dly_done) begin
po_dec_done <= #TCQ 1'b1;
cal2_po_dly_req <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_PREWAIT_READS;
wrcal_act_req <= #TCQ 1'b1;
end else
cal2_po_dly_req <= #TCQ 1'b1;
end
// Finished with read enable calibration
CAL2_DONE: begin
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
//if ((retry_cnt == 'd3) ||
// ((PRE_REV3ES == "ON") && (cal2_po_dly_cnt > PO_DLY_CNT-1))) begin
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
//end else begin
// wrcal_pat_err <= #TCQ 1'b0;
// cal2_state_r <= #TCQ CAL2_DQSFOUND;
//end
end
// Retry DQSFOUND calibration
CAL2_DQSFOUND: begin
dqsfound_again <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_DQSFOUND_WAIT;
end
CAL2_DQSFOUND_WAIT: begin
dqsfound_again <= #TCQ 1'b0;
if (dqsfound_retry_done && ~(dec_taps || dqsfound_again)) begin
cal2_state_r <= #TCQ CAL2_DEC_TAPS;
end
end
CAL2_DEC_TAPS: begin
dec_cnt <= #TCQ cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3];
cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3] <= #TCQ 3'd0;
if (cal2_corse_cnt[3*wrcal_dqs_cnt_r+:3] == 3'd0)
cal2_state_r <= #TCQ CAL2_FINE_DEC_WAIT;
else
cal2_state_r <= #TCQ CAL2_CORSE_DEC;
end
CAL2_CORSE_DEC: begin
cal2_state_r <= #TCQ CAL2_CORSE_DEC_WAIT;
dec_cnt <= #TCQ dec_cnt - 1;
end
CAL2_CORSE_DEC_WAIT: begin
if (dec_cnt == 'd0) begin
cal2_state_r <= #TCQ CAL2_FINE_DEC;
fine_dec_cnt <= #TCQ cal2_fine_cnt[wrcal_dqs_cnt_r];
cal2_fine_cnt[wrcal_dqs_cnt_r] <= #TCQ 6'd0;
end else
cal2_state_r <= #TCQ CAL2_CORSE_DEC;
end
CAL2_FINE_DEC: begin
cal2_state_r <= #TCQ CAL2_FINE_DEC_WAIT;
fine_dec_cnt <= #TCQ fine_dec_cnt -1;
end
CAL2_FINE_DEC_WAIT: begin
if ((fine_dec_cnt == 'd0) && (wrcal_dqs_cnt_r == 'd0))
cal2_state_r <= #TCQ CAL2_IDLE;
else if ((fine_dec_cnt == 'd0) && (wrcal_dqs_cnt_r > 'd0)) begin
cal2_state_r <= #TCQ CAL2_DEC_TAPS;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r - 1;
end else
cal2_state_r <= #TCQ CAL2_FINE_DEC;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst) begin
cal2_done_r1 <= #TCQ 1'b0;
cal2_done_r2 <= #TCQ 1'b0;
cal2_done_r3 <= #TCQ 1'b0;
end else begin
cal2_done_r1 <= #TCQ cal2_done_r;
cal2_done_r2 <= #TCQ cal2_done_r1;
cal2_done_r3 <= #TCQ cal2_done_r2;
end // else: !if(rst)
always @(posedge clk)
if (rst)
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ddr_wr_stream_fifo.v when simulating
// the core, ddr_wr_stream_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ddr_wr_stream_fifo(
s_aclk,
s_aresetn,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata
);
input s_aclk;
input s_aresetn;
input s_axis_tvalid;
output s_axis_tready;
input [511 : 0] s_axis_tdata;
output m_axis_tvalid;
input m_axis_tready;
output [511 : 0] m_axis_tdata;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(512),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(64),
.C_AXIS_TSTRB_WIDTH(64),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(512),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(2),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(1),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.S_ACLK(s_aclk),
.S_ARESETN(s_aresetn),
.S_AXIS_TVALID(s_axis_tvalid),
.S_AXIS_TREADY(s_axis_tready),
.S_AXIS_TDATA(s_axis_tdata),
.M_AXIS_TVALID(m_axis_tvalid),
.M_AXIS_TREADY(m_axis_tready),
.M_AXIS_TDATA(m_axis_tdata),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.DIN(),
.WR_EN(),
.RD_EN(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.DOUT(),
.FULL(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.EMPTY(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 15:21:33 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_A, FSM_selector_C, Exp_module_Overflow_flag_A,
n286, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308,
n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330,
n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352,
n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374,
n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429,
n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440,
n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462,
n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,
n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484,
n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, Sgf_operation_n109, Sgf_operation_n108,
Sgf_operation_n107, Sgf_operation_n106, Sgf_operation_n105,
Sgf_operation_n104, Sgf_operation_n103, Sgf_operation_n102,
Sgf_operation_n101, Sgf_operation_n100, Sgf_operation_n99,
Sgf_operation_n98, Sgf_operation_n97, Sgf_operation_n96,
Sgf_operation_n95, Sgf_operation_n94, Sgf_operation_n93,
Sgf_operation_n92, Sgf_operation_n91, Sgf_operation_n90,
Sgf_operation_n89, Sgf_operation_n88, Sgf_operation_n87,
Sgf_operation_n86, Sgf_operation_n85, Sgf_operation_n84,
Sgf_operation_n83, Sgf_operation_n82, Sgf_operation_n81,
Sgf_operation_n80, Sgf_operation_n79, Sgf_operation_n78,
Sgf_operation_n77, Sgf_operation_n76, Sgf_operation_n75,
Sgf_operation_n74, Sgf_operation_n73, Sgf_operation_n72,
Sgf_operation_n71, Sgf_operation_n70, Sgf_operation_n69,
Sgf_operation_n68, Sgf_operation_n67, Sgf_operation_n66,
Sgf_operation_n65, Sgf_operation_n64, Sgf_operation_n63,
Sgf_operation_n62, Sgf_operation_n61, Sgf_operation_n60,
Sgf_operation_n59, Sgf_operation_n58, Sgf_operation_n57,
Sgf_operation_n56, Sgf_operation_n55, Sgf_operation_n54,
Sgf_operation_n53, Sgf_operation_n52, Sgf_operation_n51,
Sgf_operation_n50, Sgf_operation_n49, Sgf_operation_n48,
Sgf_operation_n47, Sgf_operation_n46, Sgf_operation_n45,
Sgf_operation_n44, Sgf_operation_n43, Sgf_operation_n42,
Sgf_operation_n41, Sgf_operation_n40, Sgf_operation_n39,
Sgf_operation_n38, Sgf_operation_n37, Sgf_operation_n36,
Sgf_operation_n35, Sgf_operation_n34, Sgf_operation_n33,
Sgf_operation_n32, Sgf_operation_n31, Sgf_operation_n30,
Sgf_operation_n29, Sgf_operation_n28, Sgf_operation_n27,
Sgf_operation_n26, Sgf_operation_n25, Sgf_operation_n24,
Sgf_operation_n23, Sgf_operation_n22, Sgf_operation_n21,
Sgf_operation_n20, Sgf_operation_n19, Sgf_operation_n18,
Sgf_operation_n17, Sgf_operation_n16, Sgf_operation_n15,
Sgf_operation_n14, Sgf_operation_n13, Sgf_operation_n12,
Sgf_operation_n11, Sgf_operation_n10, Sgf_operation_n9,
Sgf_operation_n8, Sgf_operation_n7, Sgf_operation_n6,
Sgf_operation_n5, Sgf_operation_n4, Sgf_operation_n3,
DP_OP_31J39_122_605_n42, DP_OP_31J39_122_605_n28,
DP_OP_31J39_122_605_n27, DP_OP_31J39_122_605_n26,
DP_OP_31J39_122_605_n25, DP_OP_31J39_122_605_n24,
DP_OP_31J39_122_605_n23, DP_OP_31J39_122_605_n22,
DP_OP_31J39_122_605_n21, DP_OP_31J39_122_605_n20,
DP_OP_31J39_122_605_n19, DP_OP_31J39_122_605_n18,
DP_OP_31J39_122_605_n12, DP_OP_31J39_122_605_n11,
DP_OP_31J39_122_605_n10, DP_OP_31J39_122_605_n9,
DP_OP_31J39_122_605_n8, DP_OP_31J39_122_605_n7,
DP_OP_31J39_122_605_n6, DP_OP_31J39_122_605_n5,
DP_OP_31J39_122_605_n4, DP_OP_31J39_122_605_n3,
DP_OP_31J39_122_605_n2, DP_OP_31J39_122_605_n1,
Sgf_operation_mult_x_1_n4405, Sgf_operation_mult_x_1_n4404,
Sgf_operation_mult_x_1_n4403, Sgf_operation_mult_x_1_n4402,
Sgf_operation_mult_x_1_n4401, Sgf_operation_mult_x_1_n4399,
Sgf_operation_mult_x_1_n4398, Sgf_operation_mult_x_1_n4397,
Sgf_operation_mult_x_1_n4396, Sgf_operation_mult_x_1_n4395,
Sgf_operation_mult_x_1_n4394, Sgf_operation_mult_x_1_n4393,
Sgf_operation_mult_x_1_n4392, Sgf_operation_mult_x_1_n4391,
Sgf_operation_mult_x_1_n4390, Sgf_operation_mult_x_1_n4389,
Sgf_operation_mult_x_1_n4388, Sgf_operation_mult_x_1_n4387,
Sgf_operation_mult_x_1_n4386, Sgf_operation_mult_x_1_n4385,
Sgf_operation_mult_x_1_n4384, Sgf_operation_mult_x_1_n4383,
Sgf_operation_mult_x_1_n4382, Sgf_operation_mult_x_1_n4381,
Sgf_operation_mult_x_1_n4380, Sgf_operation_mult_x_1_n4379,
Sgf_operation_mult_x_1_n4378, Sgf_operation_mult_x_1_n4377,
Sgf_operation_mult_x_1_n4376, Sgf_operation_mult_x_1_n4375,
Sgf_operation_mult_x_1_n4374, Sgf_operation_mult_x_1_n4373,
Sgf_operation_mult_x_1_n4372, Sgf_operation_mult_x_1_n4371,
Sgf_operation_mult_x_1_n4370, Sgf_operation_mult_x_1_n4369,
Sgf_operation_mult_x_1_n4368, Sgf_operation_mult_x_1_n4367,
Sgf_operation_mult_x_1_n4366, Sgf_operation_mult_x_1_n4365,
Sgf_operation_mult_x_1_n4364, Sgf_operation_mult_x_1_n4363,
Sgf_operation_mult_x_1_n4362, Sgf_operation_mult_x_1_n4361,
Sgf_operation_mult_x_1_n4360, Sgf_operation_mult_x_1_n4352,
Sgf_operation_mult_x_1_n4351, Sgf_operation_mult_x_1_n4350,
Sgf_operation_mult_x_1_n4349, Sgf_operation_mult_x_1_n4348,
Sgf_operation_mult_x_1_n4347, Sgf_operation_mult_x_1_n4346,
Sgf_operation_mult_x_1_n4345, Sgf_operation_mult_x_1_n4344,
Sgf_operation_mult_x_1_n4343, Sgf_operation_mult_x_1_n4342,
Sgf_operation_mult_x_1_n4340, Sgf_operation_mult_x_1_n4339,
Sgf_operation_mult_x_1_n4338, Sgf_operation_mult_x_1_n4337,
Sgf_operation_mult_x_1_n4336, Sgf_operation_mult_x_1_n4335,
Sgf_operation_mult_x_1_n4334, Sgf_operation_mult_x_1_n4333,
Sgf_operation_mult_x_1_n4332, Sgf_operation_mult_x_1_n4331,
Sgf_operation_mult_x_1_n4330, Sgf_operation_mult_x_1_n4329,
Sgf_operation_mult_x_1_n4328, Sgf_operation_mult_x_1_n4327,
Sgf_operation_mult_x_1_n4326, Sgf_operation_mult_x_1_n4325,
Sgf_operation_mult_x_1_n4324, Sgf_operation_mult_x_1_n4323,
Sgf_operation_mult_x_1_n4322, Sgf_operation_mult_x_1_n4321,
Sgf_operation_mult_x_1_n4320, Sgf_operation_mult_x_1_n4319,
Sgf_operation_mult_x_1_n4318, Sgf_operation_mult_x_1_n4317,
Sgf_operation_mult_x_1_n4316, Sgf_operation_mult_x_1_n4315,
Sgf_operation_mult_x_1_n4314, Sgf_operation_mult_x_1_n4313,
Sgf_operation_mult_x_1_n4312, Sgf_operation_mult_x_1_n4311,
Sgf_operation_mult_x_1_n4310, Sgf_operation_mult_x_1_n4309,
Sgf_operation_mult_x_1_n4308, Sgf_operation_mult_x_1_n4307,
Sgf_operation_mult_x_1_n4306, Sgf_operation_mult_x_1_n4305,
Sgf_operation_mult_x_1_n4304, Sgf_operation_mult_x_1_n4299,
Sgf_operation_mult_x_1_n4298, Sgf_operation_mult_x_1_n4297,
Sgf_operation_mult_x_1_n4296, Sgf_operation_mult_x_1_n4295,
Sgf_operation_mult_x_1_n4294, Sgf_operation_mult_x_1_n4293,
Sgf_operation_mult_x_1_n4292, Sgf_operation_mult_x_1_n4291,
Sgf_operation_mult_x_1_n4290, Sgf_operation_mult_x_1_n4289,
Sgf_operation_mult_x_1_n4288, Sgf_operation_mult_x_1_n4287,
Sgf_operation_mult_x_1_n4286, Sgf_operation_mult_x_1_n4285,
Sgf_operation_mult_x_1_n4284, Sgf_operation_mult_x_1_n4283,
Sgf_operation_mult_x_1_n4282, Sgf_operation_mult_x_1_n4281,
Sgf_operation_mult_x_1_n4280, Sgf_operation_mult_x_1_n4279,
Sgf_operation_mult_x_1_n4278, Sgf_operation_mult_x_1_n4277,
Sgf_operation_mult_x_1_n4276, Sgf_operation_mult_x_1_n4275,
Sgf_operation_mult_x_1_n4274, Sgf_operation_mult_x_1_n4273,
Sgf_operation_mult_x_1_n4272, Sgf_operation_mult_x_1_n4271,
Sgf_operation_mult_x_1_n4270, Sgf_operation_mult_x_1_n4269,
Sgf_operation_mult_x_1_n4268, Sgf_operation_mult_x_1_n4267,
Sgf_operation_mult_x_1_n4266, Sgf_operation_mult_x_1_n4265,
Sgf_operation_mult_x_1_n4264, Sgf_operation_mult_x_1_n4263,
Sgf_operation_mult_x_1_n4262, Sgf_operation_mult_x_1_n4261,
Sgf_operation_mult_x_1_n4260, Sgf_operation_mult_x_1_n4259,
Sgf_operation_mult_x_1_n4258, Sgf_operation_mult_x_1_n4257,
Sgf_operation_mult_x_1_n4256, Sgf_operation_mult_x_1_n4255,
Sgf_operation_mult_x_1_n4254, Sgf_operation_mult_x_1_n4253,
Sgf_operation_mult_x_1_n4252, Sgf_operation_mult_x_1_n4251,
Sgf_operation_mult_x_1_n4250, Sgf_operation_mult_x_1_n4249,
Sgf_operation_mult_x_1_n4248, Sgf_operation_mult_x_1_n4240,
Sgf_operation_mult_x_1_n4239, Sgf_operation_mult_x_1_n4238,
Sgf_operation_mult_x_1_n4237, Sgf_operation_mult_x_1_n4236,
Sgf_operation_mult_x_1_n4235, Sgf_operation_mult_x_1_n4234,
Sgf_operation_mult_x_1_n4233, Sgf_operation_mult_x_1_n4232,
Sgf_operation_mult_x_1_n4231, Sgf_operation_mult_x_1_n4230,
Sgf_operation_mult_x_1_n4228, Sgf_operation_mult_x_1_n4227,
Sgf_operation_mult_x_1_n4226, Sgf_operation_mult_x_1_n4225,
Sgf_operation_mult_x_1_n4224, Sgf_operation_mult_x_1_n4222,
Sgf_operation_mult_x_1_n4221, Sgf_operation_mult_x_1_n4220,
Sgf_operation_mult_x_1_n4219, Sgf_operation_mult_x_1_n4218,
Sgf_operation_mult_x_1_n4217, Sgf_operation_mult_x_1_n4216,
Sgf_operation_mult_x_1_n4215, Sgf_operation_mult_x_1_n4214,
Sgf_operation_mult_x_1_n4213, Sgf_operation_mult_x_1_n4212,
Sgf_operation_mult_x_1_n4211, Sgf_operation_mult_x_1_n4210,
Sgf_operation_mult_x_1_n4209, Sgf_operation_mult_x_1_n4208,
Sgf_operation_mult_x_1_n4207, Sgf_operation_mult_x_1_n4206,
Sgf_operation_mult_x_1_n4205, Sgf_operation_mult_x_1_n4204,
Sgf_operation_mult_x_1_n4203, Sgf_operation_mult_x_1_n4202,
Sgf_operation_mult_x_1_n4201, Sgf_operation_mult_x_1_n4200,
Sgf_operation_mult_x_1_n4199, Sgf_operation_mult_x_1_n4198,
Sgf_operation_mult_x_1_n4197, Sgf_operation_mult_x_1_n4196,
Sgf_operation_mult_x_1_n4195, Sgf_operation_mult_x_1_n4194,
Sgf_operation_mult_x_1_n4193, Sgf_operation_mult_x_1_n4192,
Sgf_operation_mult_x_1_n4187, Sgf_operation_mult_x_1_n4186,
Sgf_operation_mult_x_1_n4185, Sgf_operation_mult_x_1_n4184,
Sgf_operation_mult_x_1_n4183, Sgf_operation_mult_x_1_n4182,
Sgf_operation_mult_x_1_n4181, Sgf_operation_mult_x_1_n4180,
Sgf_operation_mult_x_1_n4179, Sgf_operation_mult_x_1_n4178,
Sgf_operation_mult_x_1_n4177, Sgf_operation_mult_x_1_n4176,
Sgf_operation_mult_x_1_n4175, Sgf_operation_mult_x_1_n4174,
Sgf_operation_mult_x_1_n4173, Sgf_operation_mult_x_1_n4172,
Sgf_operation_mult_x_1_n4171, Sgf_operation_mult_x_1_n4170,
Sgf_operation_mult_x_1_n4169, Sgf_operation_mult_x_1_n4168,
Sgf_operation_mult_x_1_n4167, Sgf_operation_mult_x_1_n4166,
Sgf_operation_mult_x_1_n4165, Sgf_operation_mult_x_1_n4164,
Sgf_operation_mult_x_1_n4163, Sgf_operation_mult_x_1_n4162,
Sgf_operation_mult_x_1_n4161, Sgf_operation_mult_x_1_n4160,
Sgf_operation_mult_x_1_n4159, Sgf_operation_mult_x_1_n4158,
Sgf_operation_mult_x_1_n4157, Sgf_operation_mult_x_1_n4156,
Sgf_operation_mult_x_1_n4155, Sgf_operation_mult_x_1_n4154,
Sgf_operation_mult_x_1_n4153, Sgf_operation_mult_x_1_n4152,
Sgf_operation_mult_x_1_n4151, Sgf_operation_mult_x_1_n4150,
Sgf_operation_mult_x_1_n4149, Sgf_operation_mult_x_1_n4148,
Sgf_operation_mult_x_1_n4147, Sgf_operation_mult_x_1_n4146,
Sgf_operation_mult_x_1_n4145, Sgf_operation_mult_x_1_n4144,
Sgf_operation_mult_x_1_n4143, Sgf_operation_mult_x_1_n4142,
Sgf_operation_mult_x_1_n4141, Sgf_operation_mult_x_1_n4140,
Sgf_operation_mult_x_1_n4139, Sgf_operation_mult_x_1_n4138,
Sgf_operation_mult_x_1_n4137, Sgf_operation_mult_x_1_n4136,
Sgf_operation_mult_x_1_n4128, Sgf_operation_mult_x_1_n4127,
Sgf_operation_mult_x_1_n4126, Sgf_operation_mult_x_1_n4125,
Sgf_operation_mult_x_1_n4124, Sgf_operation_mult_x_1_n4123,
Sgf_operation_mult_x_1_n4122, Sgf_operation_mult_x_1_n4121,
Sgf_operation_mult_x_1_n4120, Sgf_operation_mult_x_1_n4119,
Sgf_operation_mult_x_1_n4118, Sgf_operation_mult_x_1_n4117,
Sgf_operation_mult_x_1_n4116, Sgf_operation_mult_x_1_n4115,
Sgf_operation_mult_x_1_n4114, Sgf_operation_mult_x_1_n4113,
Sgf_operation_mult_x_1_n4112, Sgf_operation_mult_x_1_n4110,
Sgf_operation_mult_x_1_n4109, Sgf_operation_mult_x_1_n4108,
Sgf_operation_mult_x_1_n4107, Sgf_operation_mult_x_1_n4106,
Sgf_operation_mult_x_1_n4105, Sgf_operation_mult_x_1_n4104,
Sgf_operation_mult_x_1_n4103, Sgf_operation_mult_x_1_n4102,
Sgf_operation_mult_x_1_n4101, Sgf_operation_mult_x_1_n4100,
Sgf_operation_mult_x_1_n4099, Sgf_operation_mult_x_1_n4098,
Sgf_operation_mult_x_1_n4097, Sgf_operation_mult_x_1_n4096,
Sgf_operation_mult_x_1_n4095, Sgf_operation_mult_x_1_n4094,
Sgf_operation_mult_x_1_n4093, Sgf_operation_mult_x_1_n4092,
Sgf_operation_mult_x_1_n4091, Sgf_operation_mult_x_1_n4090,
Sgf_operation_mult_x_1_n4089, Sgf_operation_mult_x_1_n4088,
Sgf_operation_mult_x_1_n4087, Sgf_operation_mult_x_1_n4086,
Sgf_operation_mult_x_1_n4085, Sgf_operation_mult_x_1_n4084,
Sgf_operation_mult_x_1_n4083, Sgf_operation_mult_x_1_n4082,
Sgf_operation_mult_x_1_n4081, Sgf_operation_mult_x_1_n4080,
Sgf_operation_mult_x_1_n4075, Sgf_operation_mult_x_1_n4074,
Sgf_operation_mult_x_1_n4073, Sgf_operation_mult_x_1_n4072,
Sgf_operation_mult_x_1_n4071, Sgf_operation_mult_x_1_n4070,
Sgf_operation_mult_x_1_n4069, Sgf_operation_mult_x_1_n4068,
Sgf_operation_mult_x_1_n4067, Sgf_operation_mult_x_1_n4066,
Sgf_operation_mult_x_1_n4065, Sgf_operation_mult_x_1_n4064,
Sgf_operation_mult_x_1_n4063, Sgf_operation_mult_x_1_n4062,
Sgf_operation_mult_x_1_n4061, Sgf_operation_mult_x_1_n4060,
Sgf_operation_mult_x_1_n4059, Sgf_operation_mult_x_1_n4058,
Sgf_operation_mult_x_1_n4057, Sgf_operation_mult_x_1_n4056,
Sgf_operation_mult_x_1_n4055, Sgf_operation_mult_x_1_n4054,
Sgf_operation_mult_x_1_n4053, Sgf_operation_mult_x_1_n4052,
Sgf_operation_mult_x_1_n4051, Sgf_operation_mult_x_1_n4050,
Sgf_operation_mult_x_1_n4049, Sgf_operation_mult_x_1_n4048,
Sgf_operation_mult_x_1_n4047, Sgf_operation_mult_x_1_n4046,
Sgf_operation_mult_x_1_n4045, Sgf_operation_mult_x_1_n4044,
Sgf_operation_mult_x_1_n4043, Sgf_operation_mult_x_1_n4042,
Sgf_operation_mult_x_1_n4041, Sgf_operation_mult_x_1_n4040,
Sgf_operation_mult_x_1_n4039, Sgf_operation_mult_x_1_n4038,
Sgf_operation_mult_x_1_n4037, Sgf_operation_mult_x_1_n4036,
Sgf_operation_mult_x_1_n4035, Sgf_operation_mult_x_1_n4034,
Sgf_operation_mult_x_1_n4033, Sgf_operation_mult_x_1_n4032,
Sgf_operation_mult_x_1_n4031, Sgf_operation_mult_x_1_n4030,
Sgf_operation_mult_x_1_n4029, Sgf_operation_mult_x_1_n4028,
Sgf_operation_mult_x_1_n4027, Sgf_operation_mult_x_1_n4026,
Sgf_operation_mult_x_1_n4024, Sgf_operation_mult_x_1_n4016,
Sgf_operation_mult_x_1_n4015, Sgf_operation_mult_x_1_n4014,
Sgf_operation_mult_x_1_n4013, Sgf_operation_mult_x_1_n4012,
Sgf_operation_mult_x_1_n4011, Sgf_operation_mult_x_1_n4010,
Sgf_operation_mult_x_1_n4009, Sgf_operation_mult_x_1_n4008,
Sgf_operation_mult_x_1_n4007, Sgf_operation_mult_x_1_n4006,
Sgf_operation_mult_x_1_n4005, Sgf_operation_mult_x_1_n4004,
Sgf_operation_mult_x_1_n4003, Sgf_operation_mult_x_1_n4002,
Sgf_operation_mult_x_1_n4001, Sgf_operation_mult_x_1_n4000,
Sgf_operation_mult_x_1_n3999, Sgf_operation_mult_x_1_n3998,
Sgf_operation_mult_x_1_n3997, Sgf_operation_mult_x_1_n3996,
Sgf_operation_mult_x_1_n3995, Sgf_operation_mult_x_1_n3994,
Sgf_operation_mult_x_1_n3993, Sgf_operation_mult_x_1_n3992,
Sgf_operation_mult_x_1_n3991, Sgf_operation_mult_x_1_n3990,
Sgf_operation_mult_x_1_n3989, Sgf_operation_mult_x_1_n3988,
Sgf_operation_mult_x_1_n3987, Sgf_operation_mult_x_1_n3986,
Sgf_operation_mult_x_1_n3985, Sgf_operation_mult_x_1_n3984,
Sgf_operation_mult_x_1_n3983, Sgf_operation_mult_x_1_n3982,
Sgf_operation_mult_x_1_n3981, Sgf_operation_mult_x_1_n3980,
Sgf_operation_mult_x_1_n3979, Sgf_operation_mult_x_1_n3978,
Sgf_operation_mult_x_1_n3977, Sgf_operation_mult_x_1_n3976,
Sgf_operation_mult_x_1_n3975, Sgf_operation_mult_x_1_n3974,
Sgf_operation_mult_x_1_n3973, Sgf_operation_mult_x_1_n3972,
Sgf_operation_mult_x_1_n3971, Sgf_operation_mult_x_1_n3970,
Sgf_operation_mult_x_1_n3969, Sgf_operation_mult_x_1_n3968,
Sgf_operation_mult_x_1_n3963, Sgf_operation_mult_x_1_n3962,
Sgf_operation_mult_x_1_n3961, Sgf_operation_mult_x_1_n3960,
Sgf_operation_mult_x_1_n3959, Sgf_operation_mult_x_1_n3958,
Sgf_operation_mult_x_1_n3957, Sgf_operation_mult_x_1_n3956,
Sgf_operation_mult_x_1_n3955, Sgf_operation_mult_x_1_n3954,
Sgf_operation_mult_x_1_n3953, Sgf_operation_mult_x_1_n3952,
Sgf_operation_mult_x_1_n3951, Sgf_operation_mult_x_1_n3950,
Sgf_operation_mult_x_1_n3949, Sgf_operation_mult_x_1_n3948,
Sgf_operation_mult_x_1_n3947, Sgf_operation_mult_x_1_n3946,
Sgf_operation_mult_x_1_n3945, Sgf_operation_mult_x_1_n3944,
Sgf_operation_mult_x_1_n3943, Sgf_operation_mult_x_1_n3942,
Sgf_operation_mult_x_1_n3941, Sgf_operation_mult_x_1_n3940,
Sgf_operation_mult_x_1_n3939, Sgf_operation_mult_x_1_n3938,
Sgf_operation_mult_x_1_n3937, Sgf_operation_mult_x_1_n3936,
Sgf_operation_mult_x_1_n3935, Sgf_operation_mult_x_1_n3934,
Sgf_operation_mult_x_1_n3933, Sgf_operation_mult_x_1_n3932,
Sgf_operation_mult_x_1_n3931, Sgf_operation_mult_x_1_n3930,
Sgf_operation_mult_x_1_n3929, Sgf_operation_mult_x_1_n3928,
Sgf_operation_mult_x_1_n3927, Sgf_operation_mult_x_1_n3926,
Sgf_operation_mult_x_1_n3925, Sgf_operation_mult_x_1_n3924,
Sgf_operation_mult_x_1_n3923, Sgf_operation_mult_x_1_n3922,
Sgf_operation_mult_x_1_n3921, Sgf_operation_mult_x_1_n3920,
Sgf_operation_mult_x_1_n3919, Sgf_operation_mult_x_1_n3918,
Sgf_operation_mult_x_1_n3917, Sgf_operation_mult_x_1_n3916,
Sgf_operation_mult_x_1_n3915, Sgf_operation_mult_x_1_n3914,
Sgf_operation_mult_x_1_n3904, Sgf_operation_mult_x_1_n3903,
Sgf_operation_mult_x_1_n3902, Sgf_operation_mult_x_1_n3901,
Sgf_operation_mult_x_1_n3900, Sgf_operation_mult_x_1_n3899,
Sgf_operation_mult_x_1_n3898, Sgf_operation_mult_x_1_n3897,
Sgf_operation_mult_x_1_n3896, Sgf_operation_mult_x_1_n3895,
Sgf_operation_mult_x_1_n3894, Sgf_operation_mult_x_1_n3893,
Sgf_operation_mult_x_1_n3892, Sgf_operation_mult_x_1_n3891,
Sgf_operation_mult_x_1_n3890, Sgf_operation_mult_x_1_n3889,
Sgf_operation_mult_x_1_n3888, Sgf_operation_mult_x_1_n3887,
Sgf_operation_mult_x_1_n3886, Sgf_operation_mult_x_1_n3885,
Sgf_operation_mult_x_1_n3884, Sgf_operation_mult_x_1_n3883,
Sgf_operation_mult_x_1_n3882, Sgf_operation_mult_x_1_n3881,
Sgf_operation_mult_x_1_n3880, Sgf_operation_mult_x_1_n3879,
Sgf_operation_mult_x_1_n3878, Sgf_operation_mult_x_1_n3877,
Sgf_operation_mult_x_1_n3876, Sgf_operation_mult_x_1_n3875,
Sgf_operation_mult_x_1_n3874, Sgf_operation_mult_x_1_n3873,
Sgf_operation_mult_x_1_n3872, Sgf_operation_mult_x_1_n3871,
Sgf_operation_mult_x_1_n3870, Sgf_operation_mult_x_1_n3869,
Sgf_operation_mult_x_1_n3868, Sgf_operation_mult_x_1_n3867,
Sgf_operation_mult_x_1_n3866, Sgf_operation_mult_x_1_n3865,
Sgf_operation_mult_x_1_n3864, Sgf_operation_mult_x_1_n3863,
Sgf_operation_mult_x_1_n3862, Sgf_operation_mult_x_1_n3861,
Sgf_operation_mult_x_1_n3860, Sgf_operation_mult_x_1_n3859,
Sgf_operation_mult_x_1_n3858, Sgf_operation_mult_x_1_n3857,
Sgf_operation_mult_x_1_n3856, Sgf_operation_mult_x_1_n3851,
Sgf_operation_mult_x_1_n3850, Sgf_operation_mult_x_1_n3849,
Sgf_operation_mult_x_1_n3848, Sgf_operation_mult_x_1_n3847,
Sgf_operation_mult_x_1_n3846, Sgf_operation_mult_x_1_n3845,
Sgf_operation_mult_x_1_n3844, Sgf_operation_mult_x_1_n3843,
Sgf_operation_mult_x_1_n3842, Sgf_operation_mult_x_1_n3841,
Sgf_operation_mult_x_1_n3839, Sgf_operation_mult_x_1_n3838,
Sgf_operation_mult_x_1_n3837, Sgf_operation_mult_x_1_n3836,
Sgf_operation_mult_x_1_n3835, Sgf_operation_mult_x_1_n3834,
Sgf_operation_mult_x_1_n3833, Sgf_operation_mult_x_1_n3832,
Sgf_operation_mult_x_1_n3831, Sgf_operation_mult_x_1_n3830,
Sgf_operation_mult_x_1_n3829, Sgf_operation_mult_x_1_n3828,
Sgf_operation_mult_x_1_n3827, Sgf_operation_mult_x_1_n3826,
Sgf_operation_mult_x_1_n3825, Sgf_operation_mult_x_1_n3824,
Sgf_operation_mult_x_1_n3823, Sgf_operation_mult_x_1_n3822,
Sgf_operation_mult_x_1_n3821, Sgf_operation_mult_x_1_n3820,
Sgf_operation_mult_x_1_n3819, Sgf_operation_mult_x_1_n3818,
Sgf_operation_mult_x_1_n3817, Sgf_operation_mult_x_1_n3816,
Sgf_operation_mult_x_1_n3815, Sgf_operation_mult_x_1_n3814,
Sgf_operation_mult_x_1_n3813, Sgf_operation_mult_x_1_n3812,
Sgf_operation_mult_x_1_n3811, Sgf_operation_mult_x_1_n3810,
Sgf_operation_mult_x_1_n3809, Sgf_operation_mult_x_1_n3808,
Sgf_operation_mult_x_1_n3807, Sgf_operation_mult_x_1_n3806,
Sgf_operation_mult_x_1_n3805, Sgf_operation_mult_x_1_n3804,
Sgf_operation_mult_x_1_n3803, Sgf_operation_mult_x_1_n3802,
Sgf_operation_mult_x_1_n3793, Sgf_operation_mult_x_1_n3792,
Sgf_operation_mult_x_1_n3791, Sgf_operation_mult_x_1_n3790,
Sgf_operation_mult_x_1_n3789, Sgf_operation_mult_x_1_n3788,
Sgf_operation_mult_x_1_n3787, Sgf_operation_mult_x_1_n3786,
Sgf_operation_mult_x_1_n3785, Sgf_operation_mult_x_1_n3784,
Sgf_operation_mult_x_1_n3783, Sgf_operation_mult_x_1_n3782,
Sgf_operation_mult_x_1_n3781, Sgf_operation_mult_x_1_n3780,
Sgf_operation_mult_x_1_n3779, Sgf_operation_mult_x_1_n3778,
Sgf_operation_mult_x_1_n3777, Sgf_operation_mult_x_1_n3776,
Sgf_operation_mult_x_1_n3775, Sgf_operation_mult_x_1_n3774,
Sgf_operation_mult_x_1_n3773, Sgf_operation_mult_x_1_n3772,
Sgf_operation_mult_x_1_n3771, Sgf_operation_mult_x_1_n3770,
Sgf_operation_mult_x_1_n3769, Sgf_operation_mult_x_1_n3768,
Sgf_operation_mult_x_1_n3767, Sgf_operation_mult_x_1_n3766,
Sgf_operation_mult_x_1_n3765, Sgf_operation_mult_x_1_n3764,
Sgf_operation_mult_x_1_n3763, Sgf_operation_mult_x_1_n3762,
Sgf_operation_mult_x_1_n3761, Sgf_operation_mult_x_1_n3760,
Sgf_operation_mult_x_1_n3759, Sgf_operation_mult_x_1_n3758,
Sgf_operation_mult_x_1_n3757, Sgf_operation_mult_x_1_n3756,
Sgf_operation_mult_x_1_n3755, Sgf_operation_mult_x_1_n3754,
Sgf_operation_mult_x_1_n3753, Sgf_operation_mult_x_1_n3752,
Sgf_operation_mult_x_1_n3751, Sgf_operation_mult_x_1_n3750,
Sgf_operation_mult_x_1_n3749, Sgf_operation_mult_x_1_n3748,
Sgf_operation_mult_x_1_n3747, Sgf_operation_mult_x_1_n3746,
Sgf_operation_mult_x_1_n3745, Sgf_operation_mult_x_1_n3740,
Sgf_operation_mult_x_1_n3739, Sgf_operation_mult_x_1_n3738,
Sgf_operation_mult_x_1_n3737, Sgf_operation_mult_x_1_n3736,
Sgf_operation_mult_x_1_n3735, Sgf_operation_mult_x_1_n3734,
Sgf_operation_mult_x_1_n3733, Sgf_operation_mult_x_1_n3732,
Sgf_operation_mult_x_1_n3731, Sgf_operation_mult_x_1_n3730,
Sgf_operation_mult_x_1_n3728, Sgf_operation_mult_x_1_n3727,
Sgf_operation_mult_x_1_n3726, Sgf_operation_mult_x_1_n3725,
Sgf_operation_mult_x_1_n3724, Sgf_operation_mult_x_1_n3723,
Sgf_operation_mult_x_1_n3722, Sgf_operation_mult_x_1_n3721,
Sgf_operation_mult_x_1_n3720, Sgf_operation_mult_x_1_n3719,
Sgf_operation_mult_x_1_n3718, Sgf_operation_mult_x_1_n3717,
Sgf_operation_mult_x_1_n3716, Sgf_operation_mult_x_1_n3715,
Sgf_operation_mult_x_1_n3714, Sgf_operation_mult_x_1_n3713,
Sgf_operation_mult_x_1_n3712, Sgf_operation_mult_x_1_n3711,
Sgf_operation_mult_x_1_n3710, Sgf_operation_mult_x_1_n3709,
Sgf_operation_mult_x_1_n3708, Sgf_operation_mult_x_1_n3707,
Sgf_operation_mult_x_1_n3706, Sgf_operation_mult_x_1_n3705,
Sgf_operation_mult_x_1_n3704, Sgf_operation_mult_x_1_n3703,
Sgf_operation_mult_x_1_n3702, Sgf_operation_mult_x_1_n3701,
Sgf_operation_mult_x_1_n3700, Sgf_operation_mult_x_1_n3699,
Sgf_operation_mult_x_1_n3698, Sgf_operation_mult_x_1_n3697,
Sgf_operation_mult_x_1_n3696, Sgf_operation_mult_x_1_n3695,
Sgf_operation_mult_x_1_n3693, Sgf_operation_mult_x_1_n3692,
Sgf_operation_mult_x_1_n3691, Sgf_operation_mult_x_1_n3682,
Sgf_operation_mult_x_1_n3681, Sgf_operation_mult_x_1_n3680,
Sgf_operation_mult_x_1_n3679, Sgf_operation_mult_x_1_n3678,
Sgf_operation_mult_x_1_n3677, Sgf_operation_mult_x_1_n3676,
Sgf_operation_mult_x_1_n3675, Sgf_operation_mult_x_1_n3674,
Sgf_operation_mult_x_1_n3673, Sgf_operation_mult_x_1_n3672,
Sgf_operation_mult_x_1_n3671, Sgf_operation_mult_x_1_n3670,
Sgf_operation_mult_x_1_n3669, Sgf_operation_mult_x_1_n3668,
Sgf_operation_mult_x_1_n3667, Sgf_operation_mult_x_1_n3666,
Sgf_operation_mult_x_1_n3665, Sgf_operation_mult_x_1_n3664,
Sgf_operation_mult_x_1_n3663, Sgf_operation_mult_x_1_n3662,
Sgf_operation_mult_x_1_n3661, Sgf_operation_mult_x_1_n3660,
Sgf_operation_mult_x_1_n3659, Sgf_operation_mult_x_1_n3658,
Sgf_operation_mult_x_1_n3657, Sgf_operation_mult_x_1_n3656,
Sgf_operation_mult_x_1_n3655, Sgf_operation_mult_x_1_n3654,
Sgf_operation_mult_x_1_n3653, Sgf_operation_mult_x_1_n3652,
Sgf_operation_mult_x_1_n3651, Sgf_operation_mult_x_1_n3650,
Sgf_operation_mult_x_1_n3649, Sgf_operation_mult_x_1_n3648,
Sgf_operation_mult_x_1_n3647, Sgf_operation_mult_x_1_n3646,
Sgf_operation_mult_x_1_n3645, Sgf_operation_mult_x_1_n3644,
Sgf_operation_mult_x_1_n3643, Sgf_operation_mult_x_1_n3642,
Sgf_operation_mult_x_1_n3641, Sgf_operation_mult_x_1_n3640,
Sgf_operation_mult_x_1_n3639, Sgf_operation_mult_x_1_n3638,
Sgf_operation_mult_x_1_n3637, Sgf_operation_mult_x_1_n3636,
Sgf_operation_mult_x_1_n3635, Sgf_operation_mult_x_1_n3634,
Sgf_operation_mult_x_1_n3629, Sgf_operation_mult_x_1_n3628,
Sgf_operation_mult_x_1_n3627, Sgf_operation_mult_x_1_n3626,
Sgf_operation_mult_x_1_n3625, Sgf_operation_mult_x_1_n3624,
Sgf_operation_mult_x_1_n3623, Sgf_operation_mult_x_1_n3622,
Sgf_operation_mult_x_1_n3621, Sgf_operation_mult_x_1_n3620,
Sgf_operation_mult_x_1_n3619, Sgf_operation_mult_x_1_n3618,
Sgf_operation_mult_x_1_n3617, Sgf_operation_mult_x_1_n3616,
Sgf_operation_mult_x_1_n3615, Sgf_operation_mult_x_1_n3614,
Sgf_operation_mult_x_1_n3613, Sgf_operation_mult_x_1_n3612,
Sgf_operation_mult_x_1_n3611, Sgf_operation_mult_x_1_n3610,
Sgf_operation_mult_x_1_n3609, Sgf_operation_mult_x_1_n3608,
Sgf_operation_mult_x_1_n3606, Sgf_operation_mult_x_1_n3605,
Sgf_operation_mult_x_1_n3604, Sgf_operation_mult_x_1_n3602,
Sgf_operation_mult_x_1_n3601, Sgf_operation_mult_x_1_n3600,
Sgf_operation_mult_x_1_n3599, Sgf_operation_mult_x_1_n3598,
Sgf_operation_mult_x_1_n3597, Sgf_operation_mult_x_1_n3596,
Sgf_operation_mult_x_1_n3595, Sgf_operation_mult_x_1_n3594,
Sgf_operation_mult_x_1_n3593, Sgf_operation_mult_x_1_n3592,
Sgf_operation_mult_x_1_n3591, Sgf_operation_mult_x_1_n3590,
Sgf_operation_mult_x_1_n3589, Sgf_operation_mult_x_1_n3588,
Sgf_operation_mult_x_1_n3587, Sgf_operation_mult_x_1_n3586,
Sgf_operation_mult_x_1_n3585, Sgf_operation_mult_x_1_n3584,
Sgf_operation_mult_x_1_n3582, Sgf_operation_mult_x_1_n3581,
Sgf_operation_mult_x_1_n3580, Sgf_operation_mult_x_1_n3571,
Sgf_operation_mult_x_1_n3570, Sgf_operation_mult_x_1_n3569,
Sgf_operation_mult_x_1_n3568, Sgf_operation_mult_x_1_n3567,
Sgf_operation_mult_x_1_n3566, Sgf_operation_mult_x_1_n3565,
Sgf_operation_mult_x_1_n3564, Sgf_operation_mult_x_1_n3561,
Sgf_operation_mult_x_1_n3560, Sgf_operation_mult_x_1_n3559,
Sgf_operation_mult_x_1_n3558, Sgf_operation_mult_x_1_n3557,
Sgf_operation_mult_x_1_n3555, Sgf_operation_mult_x_1_n3554,
Sgf_operation_mult_x_1_n3553, Sgf_operation_mult_x_1_n3552,
Sgf_operation_mult_x_1_n3551, Sgf_operation_mult_x_1_n3549,
Sgf_operation_mult_x_1_n3548, Sgf_operation_mult_x_1_n3547,
Sgf_operation_mult_x_1_n3546, Sgf_operation_mult_x_1_n3545,
Sgf_operation_mult_x_1_n3544, Sgf_operation_mult_x_1_n3543,
Sgf_operation_mult_x_1_n3542, Sgf_operation_mult_x_1_n3541,
Sgf_operation_mult_x_1_n3540, Sgf_operation_mult_x_1_n3539,
Sgf_operation_mult_x_1_n3538, Sgf_operation_mult_x_1_n3537,
Sgf_operation_mult_x_1_n3536, Sgf_operation_mult_x_1_n3535,
Sgf_operation_mult_x_1_n3534, Sgf_operation_mult_x_1_n3533,
Sgf_operation_mult_x_1_n3532, Sgf_operation_mult_x_1_n3531,
Sgf_operation_mult_x_1_n3530, Sgf_operation_mult_x_1_n3529,
Sgf_operation_mult_x_1_n3528, Sgf_operation_mult_x_1_n3527,
Sgf_operation_mult_x_1_n3526, Sgf_operation_mult_x_1_n3525,
Sgf_operation_mult_x_1_n3524, Sgf_operation_mult_x_1_n3523,
Sgf_operation_mult_x_1_n3518, Sgf_operation_mult_x_1_n3517,
Sgf_operation_mult_x_1_n3516, Sgf_operation_mult_x_1_n3515,
Sgf_operation_mult_x_1_n3514, Sgf_operation_mult_x_1_n3513,
Sgf_operation_mult_x_1_n3512, Sgf_operation_mult_x_1_n3511,
Sgf_operation_mult_x_1_n3510, Sgf_operation_mult_x_1_n3509,
Sgf_operation_mult_x_1_n3508, Sgf_operation_mult_x_1_n3507,
Sgf_operation_mult_x_1_n3506, Sgf_operation_mult_x_1_n3505,
Sgf_operation_mult_x_1_n3503, Sgf_operation_mult_x_1_n3502,
Sgf_operation_mult_x_1_n3501, Sgf_operation_mult_x_1_n3500,
Sgf_operation_mult_x_1_n3499, Sgf_operation_mult_x_1_n3498,
Sgf_operation_mult_x_1_n3496, Sgf_operation_mult_x_1_n3495,
Sgf_operation_mult_x_1_n3494, Sgf_operation_mult_x_1_n3492,
Sgf_operation_mult_x_1_n3491, Sgf_operation_mult_x_1_n3490,
Sgf_operation_mult_x_1_n3489, Sgf_operation_mult_x_1_n3488,
Sgf_operation_mult_x_1_n3486, Sgf_operation_mult_x_1_n3485,
Sgf_operation_mult_x_1_n3484, Sgf_operation_mult_x_1_n3483,
Sgf_operation_mult_x_1_n3482, Sgf_operation_mult_x_1_n3481,
Sgf_operation_mult_x_1_n3480, Sgf_operation_mult_x_1_n3479,
Sgf_operation_mult_x_1_n3478, Sgf_operation_mult_x_1_n3477,
Sgf_operation_mult_x_1_n3476, Sgf_operation_mult_x_1_n3475,
Sgf_operation_mult_x_1_n3474, Sgf_operation_mult_x_1_n3472,
Sgf_operation_mult_x_1_n3471, Sgf_operation_mult_x_1_n3470,
Sgf_operation_mult_x_1_n3467, Sgf_operation_mult_x_1_n3466,
Sgf_operation_mult_x_1_n3465, Sgf_operation_mult_x_1_n3464,
Sgf_operation_mult_x_1_n3463, Sgf_operation_mult_x_1_n3462,
Sgf_operation_mult_x_1_n3461, Sgf_operation_mult_x_1_n3460,
Sgf_operation_mult_x_1_n3458, Sgf_operation_mult_x_1_n3457,
Sgf_operation_mult_x_1_n3455, Sgf_operation_mult_x_1_n3454,
Sgf_operation_mult_x_1_n3453, Sgf_operation_mult_x_1_n3452,
Sgf_operation_mult_x_1_n3451, Sgf_operation_mult_x_1_n3450,
Sgf_operation_mult_x_1_n3449, Sgf_operation_mult_x_1_n3446,
Sgf_operation_mult_x_1_n3445, Sgf_operation_mult_x_1_n3443,
Sgf_operation_mult_x_1_n3442, Sgf_operation_mult_x_1_n3441,
Sgf_operation_mult_x_1_n3439, Sgf_operation_mult_x_1_n3438,
Sgf_operation_mult_x_1_n3437, Sgf_operation_mult_x_1_n3435,
Sgf_operation_mult_x_1_n3434, Sgf_operation_mult_x_1_n3433,
Sgf_operation_mult_x_1_n2757, Sgf_operation_mult_x_1_n2754,
Sgf_operation_mult_x_1_n2752, Sgf_operation_mult_x_1_n2751,
Sgf_operation_mult_x_1_n2750, Sgf_operation_mult_x_1_n2749,
Sgf_operation_mult_x_1_n2747, Sgf_operation_mult_x_1_n2746,
Sgf_operation_mult_x_1_n2745, Sgf_operation_mult_x_1_n2744,
Sgf_operation_mult_x_1_n2742, Sgf_operation_mult_x_1_n2741,
Sgf_operation_mult_x_1_n2740, Sgf_operation_mult_x_1_n2737,
Sgf_operation_mult_x_1_n2735, Sgf_operation_mult_x_1_n2734,
Sgf_operation_mult_x_1_n2733, Sgf_operation_mult_x_1_n2730,
Sgf_operation_mult_x_1_n2729, Sgf_operation_mult_x_1_n2728,
Sgf_operation_mult_x_1_n2727, Sgf_operation_mult_x_1_n2726,
Sgf_operation_mult_x_1_n2724, Sgf_operation_mult_x_1_n2723,
Sgf_operation_mult_x_1_n2722, Sgf_operation_mult_x_1_n2721,
Sgf_operation_mult_x_1_n2720, Sgf_operation_mult_x_1_n2719,
Sgf_operation_mult_x_1_n2718, Sgf_operation_mult_x_1_n2716,
Sgf_operation_mult_x_1_n2715, Sgf_operation_mult_x_1_n2714,
Sgf_operation_mult_x_1_n2713, Sgf_operation_mult_x_1_n2712,
Sgf_operation_mult_x_1_n2711, Sgf_operation_mult_x_1_n2710,
Sgf_operation_mult_x_1_n2708, Sgf_operation_mult_x_1_n2707,
Sgf_operation_mult_x_1_n2706, Sgf_operation_mult_x_1_n2705,
Sgf_operation_mult_x_1_n2704, Sgf_operation_mult_x_1_n2703,
Sgf_operation_mult_x_1_n2702, Sgf_operation_mult_x_1_n2700,
Sgf_operation_mult_x_1_n2699, Sgf_operation_mult_x_1_n2698,
Sgf_operation_mult_x_1_n2697, Sgf_operation_mult_x_1_n2696,
Sgf_operation_mult_x_1_n2695, Sgf_operation_mult_x_1_n2692,
Sgf_operation_mult_x_1_n2690, Sgf_operation_mult_x_1_n2689,
Sgf_operation_mult_x_1_n2688, Sgf_operation_mult_x_1_n2687,
Sgf_operation_mult_x_1_n2686, Sgf_operation_mult_x_1_n2685,
Sgf_operation_mult_x_1_n2682, Sgf_operation_mult_x_1_n2681,
Sgf_operation_mult_x_1_n2680, Sgf_operation_mult_x_1_n2679,
Sgf_operation_mult_x_1_n2678, Sgf_operation_mult_x_1_n2677,
Sgf_operation_mult_x_1_n2676, Sgf_operation_mult_x_1_n2675,
Sgf_operation_mult_x_1_n2673, Sgf_operation_mult_x_1_n2672,
Sgf_operation_mult_x_1_n2671, Sgf_operation_mult_x_1_n2670,
Sgf_operation_mult_x_1_n2669, Sgf_operation_mult_x_1_n2668,
Sgf_operation_mult_x_1_n2667, Sgf_operation_mult_x_1_n2666,
Sgf_operation_mult_x_1_n2665, Sgf_operation_mult_x_1_n2664,
Sgf_operation_mult_x_1_n2662, Sgf_operation_mult_x_1_n2661,
Sgf_operation_mult_x_1_n2660, Sgf_operation_mult_x_1_n2659,
Sgf_operation_mult_x_1_n2658, Sgf_operation_mult_x_1_n2657,
Sgf_operation_mult_x_1_n2656, Sgf_operation_mult_x_1_n2655,
Sgf_operation_mult_x_1_n2654, Sgf_operation_mult_x_1_n2653,
Sgf_operation_mult_x_1_n2651, Sgf_operation_mult_x_1_n2650,
Sgf_operation_mult_x_1_n2649, Sgf_operation_mult_x_1_n2648,
Sgf_operation_mult_x_1_n2647, Sgf_operation_mult_x_1_n2646,
Sgf_operation_mult_x_1_n2645, Sgf_operation_mult_x_1_n2644,
Sgf_operation_mult_x_1_n2643, Sgf_operation_mult_x_1_n2642,
Sgf_operation_mult_x_1_n2640, Sgf_operation_mult_x_1_n2639,
Sgf_operation_mult_x_1_n2638, Sgf_operation_mult_x_1_n2637,
Sgf_operation_mult_x_1_n2636, Sgf_operation_mult_x_1_n2635,
Sgf_operation_mult_x_1_n2634, Sgf_operation_mult_x_1_n2633,
Sgf_operation_mult_x_1_n2632, Sgf_operation_mult_x_1_n2629,
Sgf_operation_mult_x_1_n2627, Sgf_operation_mult_x_1_n2626,
Sgf_operation_mult_x_1_n2625, Sgf_operation_mult_x_1_n2624,
Sgf_operation_mult_x_1_n2623, Sgf_operation_mult_x_1_n2622,
Sgf_operation_mult_x_1_n2621, Sgf_operation_mult_x_1_n2620,
Sgf_operation_mult_x_1_n2619, Sgf_operation_mult_x_1_n2616,
Sgf_operation_mult_x_1_n2615, Sgf_operation_mult_x_1_n2614,
Sgf_operation_mult_x_1_n2613, Sgf_operation_mult_x_1_n2612,
Sgf_operation_mult_x_1_n2611, Sgf_operation_mult_x_1_n2610,
Sgf_operation_mult_x_1_n2609, Sgf_operation_mult_x_1_n2608,
Sgf_operation_mult_x_1_n2607, Sgf_operation_mult_x_1_n2606,
Sgf_operation_mult_x_1_n2604, Sgf_operation_mult_x_1_n2603,
Sgf_operation_mult_x_1_n2602, Sgf_operation_mult_x_1_n2601,
Sgf_operation_mult_x_1_n2600, Sgf_operation_mult_x_1_n2599,
Sgf_operation_mult_x_1_n2598, Sgf_operation_mult_x_1_n2597,
Sgf_operation_mult_x_1_n2596, Sgf_operation_mult_x_1_n2595,
Sgf_operation_mult_x_1_n2594, Sgf_operation_mult_x_1_n2593,
Sgf_operation_mult_x_1_n2592, Sgf_operation_mult_x_1_n2590,
Sgf_operation_mult_x_1_n2589, Sgf_operation_mult_x_1_n2588,
Sgf_operation_mult_x_1_n2587, Sgf_operation_mult_x_1_n2586,
Sgf_operation_mult_x_1_n2585, Sgf_operation_mult_x_1_n2584,
Sgf_operation_mult_x_1_n2583, Sgf_operation_mult_x_1_n2582,
Sgf_operation_mult_x_1_n2581, Sgf_operation_mult_x_1_n2580,
Sgf_operation_mult_x_1_n2579, Sgf_operation_mult_x_1_n2578,
Sgf_operation_mult_x_1_n2576, Sgf_operation_mult_x_1_n2575,
Sgf_operation_mult_x_1_n2574, Sgf_operation_mult_x_1_n2573,
Sgf_operation_mult_x_1_n2572, Sgf_operation_mult_x_1_n2571,
Sgf_operation_mult_x_1_n2570, Sgf_operation_mult_x_1_n2569,
Sgf_operation_mult_x_1_n2568, Sgf_operation_mult_x_1_n2567,
Sgf_operation_mult_x_1_n2566, Sgf_operation_mult_x_1_n2565,
Sgf_operation_mult_x_1_n2564, Sgf_operation_mult_x_1_n2562,
Sgf_operation_mult_x_1_n2561, Sgf_operation_mult_x_1_n2560,
Sgf_operation_mult_x_1_n2559, Sgf_operation_mult_x_1_n2558,
Sgf_operation_mult_x_1_n2557, Sgf_operation_mult_x_1_n2556,
Sgf_operation_mult_x_1_n2555, Sgf_operation_mult_x_1_n2554,
Sgf_operation_mult_x_1_n2553, Sgf_operation_mult_x_1_n2552,
Sgf_operation_mult_x_1_n2551, Sgf_operation_mult_x_1_n2548,
Sgf_operation_mult_x_1_n2546, Sgf_operation_mult_x_1_n2545,
Sgf_operation_mult_x_1_n2544, Sgf_operation_mult_x_1_n2543,
Sgf_operation_mult_x_1_n2542, Sgf_operation_mult_x_1_n2541,
Sgf_operation_mult_x_1_n2540, Sgf_operation_mult_x_1_n2539,
Sgf_operation_mult_x_1_n2538, Sgf_operation_mult_x_1_n2537,
Sgf_operation_mult_x_1_n2536, Sgf_operation_mult_x_1_n2535,
Sgf_operation_mult_x_1_n2532, Sgf_operation_mult_x_1_n2531,
Sgf_operation_mult_x_1_n2530, Sgf_operation_mult_x_1_n2529,
Sgf_operation_mult_x_1_n2528, Sgf_operation_mult_x_1_n2527,
Sgf_operation_mult_x_1_n2526, Sgf_operation_mult_x_1_n2525,
Sgf_operation_mult_x_1_n2524, Sgf_operation_mult_x_1_n2523,
Sgf_operation_mult_x_1_n2522, Sgf_operation_mult_x_1_n2521,
Sgf_operation_mult_x_1_n2520, Sgf_operation_mult_x_1_n2519,
Sgf_operation_mult_x_1_n2517, Sgf_operation_mult_x_1_n2516,
Sgf_operation_mult_x_1_n2515, Sgf_operation_mult_x_1_n2514,
Sgf_operation_mult_x_1_n2513, Sgf_operation_mult_x_1_n2512,
Sgf_operation_mult_x_1_n2511, Sgf_operation_mult_x_1_n2510,
Sgf_operation_mult_x_1_n2509, Sgf_operation_mult_x_1_n2508,
Sgf_operation_mult_x_1_n2507, Sgf_operation_mult_x_1_n2506,
Sgf_operation_mult_x_1_n2505, Sgf_operation_mult_x_1_n2504,
Sgf_operation_mult_x_1_n2503, Sgf_operation_mult_x_1_n2502,
Sgf_operation_mult_x_1_n2500, Sgf_operation_mult_x_1_n2499,
Sgf_operation_mult_x_1_n2498, Sgf_operation_mult_x_1_n2497,
Sgf_operation_mult_x_1_n2496, Sgf_operation_mult_x_1_n2495,
Sgf_operation_mult_x_1_n2494, Sgf_operation_mult_x_1_n2493,
Sgf_operation_mult_x_1_n2492, Sgf_operation_mult_x_1_n2491,
Sgf_operation_mult_x_1_n2490, Sgf_operation_mult_x_1_n2489,
Sgf_operation_mult_x_1_n2488, Sgf_operation_mult_x_1_n2487,
Sgf_operation_mult_x_1_n2486, Sgf_operation_mult_x_1_n2485,
Sgf_operation_mult_x_1_n2483, Sgf_operation_mult_x_1_n2482,
Sgf_operation_mult_x_1_n2481, Sgf_operation_mult_x_1_n2480,
Sgf_operation_mult_x_1_n2479, Sgf_operation_mult_x_1_n2478,
Sgf_operation_mult_x_1_n2477, Sgf_operation_mult_x_1_n2476,
Sgf_operation_mult_x_1_n2475, Sgf_operation_mult_x_1_n2474,
Sgf_operation_mult_x_1_n2473, Sgf_operation_mult_x_1_n2472,
Sgf_operation_mult_x_1_n2471, Sgf_operation_mult_x_1_n2470,
Sgf_operation_mult_x_1_n2469, Sgf_operation_mult_x_1_n2468,
Sgf_operation_mult_x_1_n2466, Sgf_operation_mult_x_1_n2465,
Sgf_operation_mult_x_1_n2464, Sgf_operation_mult_x_1_n2463,
Sgf_operation_mult_x_1_n2462, Sgf_operation_mult_x_1_n2461,
Sgf_operation_mult_x_1_n2460, Sgf_operation_mult_x_1_n2459,
Sgf_operation_mult_x_1_n2458, Sgf_operation_mult_x_1_n2457,
Sgf_operation_mult_x_1_n2456, Sgf_operation_mult_x_1_n2455,
Sgf_operation_mult_x_1_n2454, Sgf_operation_mult_x_1_n2453,
Sgf_operation_mult_x_1_n2452, Sgf_operation_mult_x_1_n2449,
Sgf_operation_mult_x_1_n2447, Sgf_operation_mult_x_1_n2446,
Sgf_operation_mult_x_1_n2445, Sgf_operation_mult_x_1_n2444,
Sgf_operation_mult_x_1_n2443, Sgf_operation_mult_x_1_n2442,
Sgf_operation_mult_x_1_n2441, Sgf_operation_mult_x_1_n2440,
Sgf_operation_mult_x_1_n2439, Sgf_operation_mult_x_1_n2438,
Sgf_operation_mult_x_1_n2437, Sgf_operation_mult_x_1_n2436,
Sgf_operation_mult_x_1_n2435, Sgf_operation_mult_x_1_n2434,
Sgf_operation_mult_x_1_n2433, Sgf_operation_mult_x_1_n2430,
Sgf_operation_mult_x_1_n2429, Sgf_operation_mult_x_1_n2428,
Sgf_operation_mult_x_1_n2427, Sgf_operation_mult_x_1_n2426,
Sgf_operation_mult_x_1_n2425, Sgf_operation_mult_x_1_n2424,
Sgf_operation_mult_x_1_n2423, Sgf_operation_mult_x_1_n2422,
Sgf_operation_mult_x_1_n2421, Sgf_operation_mult_x_1_n2420,
Sgf_operation_mult_x_1_n2419, Sgf_operation_mult_x_1_n2418,
Sgf_operation_mult_x_1_n2417, Sgf_operation_mult_x_1_n2416,
Sgf_operation_mult_x_1_n2415, Sgf_operation_mult_x_1_n2414,
Sgf_operation_mult_x_1_n2412, Sgf_operation_mult_x_1_n2411,
Sgf_operation_mult_x_1_n2410, Sgf_operation_mult_x_1_n2409,
Sgf_operation_mult_x_1_n2408, Sgf_operation_mult_x_1_n2407,
Sgf_operation_mult_x_1_n2406, Sgf_operation_mult_x_1_n2405,
Sgf_operation_mult_x_1_n2404, Sgf_operation_mult_x_1_n2403,
Sgf_operation_mult_x_1_n2402, Sgf_operation_mult_x_1_n2401,
Sgf_operation_mult_x_1_n2400, Sgf_operation_mult_x_1_n2399,
Sgf_operation_mult_x_1_n2398, Sgf_operation_mult_x_1_n2397,
Sgf_operation_mult_x_1_n2396, Sgf_operation_mult_x_1_n2395,
Sgf_operation_mult_x_1_n2394, Sgf_operation_mult_x_1_n2392,
Sgf_operation_mult_x_1_n2391, Sgf_operation_mult_x_1_n2390,
Sgf_operation_mult_x_1_n2389, Sgf_operation_mult_x_1_n2388,
Sgf_operation_mult_x_1_n2387, Sgf_operation_mult_x_1_n2386,
Sgf_operation_mult_x_1_n2385, Sgf_operation_mult_x_1_n2384,
Sgf_operation_mult_x_1_n2383, Sgf_operation_mult_x_1_n2382,
Sgf_operation_mult_x_1_n2381, Sgf_operation_mult_x_1_n2380,
Sgf_operation_mult_x_1_n2379, Sgf_operation_mult_x_1_n2378,
Sgf_operation_mult_x_1_n2377, Sgf_operation_mult_x_1_n2376,
Sgf_operation_mult_x_1_n2375, Sgf_operation_mult_x_1_n2374,
Sgf_operation_mult_x_1_n2372, Sgf_operation_mult_x_1_n2371,
Sgf_operation_mult_x_1_n2370, Sgf_operation_mult_x_1_n2369,
Sgf_operation_mult_x_1_n2368, Sgf_operation_mult_x_1_n2367,
Sgf_operation_mult_x_1_n2366, Sgf_operation_mult_x_1_n2365,
Sgf_operation_mult_x_1_n2364, Sgf_operation_mult_x_1_n2363,
Sgf_operation_mult_x_1_n2362, Sgf_operation_mult_x_1_n2361,
Sgf_operation_mult_x_1_n2360, Sgf_operation_mult_x_1_n2359,
Sgf_operation_mult_x_1_n2358, Sgf_operation_mult_x_1_n2357,
Sgf_operation_mult_x_1_n2356, Sgf_operation_mult_x_1_n2355,
Sgf_operation_mult_x_1_n2354, Sgf_operation_mult_x_1_n2352,
Sgf_operation_mult_x_1_n2351, Sgf_operation_mult_x_1_n2350,
Sgf_operation_mult_x_1_n2349, Sgf_operation_mult_x_1_n2348,
Sgf_operation_mult_x_1_n2347, Sgf_operation_mult_x_1_n2346,
Sgf_operation_mult_x_1_n2345, Sgf_operation_mult_x_1_n2344,
Sgf_operation_mult_x_1_n2343, Sgf_operation_mult_x_1_n2342,
Sgf_operation_mult_x_1_n2341, Sgf_operation_mult_x_1_n2340,
Sgf_operation_mult_x_1_n2339, Sgf_operation_mult_x_1_n2338,
Sgf_operation_mult_x_1_n2337, Sgf_operation_mult_x_1_n2336,
Sgf_operation_mult_x_1_n2335, Sgf_operation_mult_x_1_n2332,
Sgf_operation_mult_x_1_n2330, Sgf_operation_mult_x_1_n2329,
Sgf_operation_mult_x_1_n2328, Sgf_operation_mult_x_1_n2327,
Sgf_operation_mult_x_1_n2326, Sgf_operation_mult_x_1_n2325,
Sgf_operation_mult_x_1_n2324, Sgf_operation_mult_x_1_n2323,
Sgf_operation_mult_x_1_n2322, Sgf_operation_mult_x_1_n2321,
Sgf_operation_mult_x_1_n2320, Sgf_operation_mult_x_1_n2319,
Sgf_operation_mult_x_1_n2318, Sgf_operation_mult_x_1_n2317,
Sgf_operation_mult_x_1_n2316, Sgf_operation_mult_x_1_n2315,
Sgf_operation_mult_x_1_n2314, Sgf_operation_mult_x_1_n2313,
Sgf_operation_mult_x_1_n2310, Sgf_operation_mult_x_1_n2309,
Sgf_operation_mult_x_1_n2308, Sgf_operation_mult_x_1_n2307,
Sgf_operation_mult_x_1_n2306, Sgf_operation_mult_x_1_n2305,
Sgf_operation_mult_x_1_n2304, Sgf_operation_mult_x_1_n2303,
Sgf_operation_mult_x_1_n2302, Sgf_operation_mult_x_1_n2301,
Sgf_operation_mult_x_1_n2300, Sgf_operation_mult_x_1_n2299,
Sgf_operation_mult_x_1_n2298, Sgf_operation_mult_x_1_n2297,
Sgf_operation_mult_x_1_n2296, Sgf_operation_mult_x_1_n2295,
Sgf_operation_mult_x_1_n2294, Sgf_operation_mult_x_1_n2293,
Sgf_operation_mult_x_1_n2292, Sgf_operation_mult_x_1_n2291,
Sgf_operation_mult_x_1_n2289, Sgf_operation_mult_x_1_n2288,
Sgf_operation_mult_x_1_n2287, Sgf_operation_mult_x_1_n2286,
Sgf_operation_mult_x_1_n2285, Sgf_operation_mult_x_1_n2284,
Sgf_operation_mult_x_1_n2283, Sgf_operation_mult_x_1_n2282,
Sgf_operation_mult_x_1_n2281, Sgf_operation_mult_x_1_n2280,
Sgf_operation_mult_x_1_n2279, Sgf_operation_mult_x_1_n2278,
Sgf_operation_mult_x_1_n2277, Sgf_operation_mult_x_1_n2276,
Sgf_operation_mult_x_1_n2275, Sgf_operation_mult_x_1_n2274,
Sgf_operation_mult_x_1_n2273, Sgf_operation_mult_x_1_n2272,
Sgf_operation_mult_x_1_n2271, Sgf_operation_mult_x_1_n2270,
Sgf_operation_mult_x_1_n2269, Sgf_operation_mult_x_1_n2268,
Sgf_operation_mult_x_1_n2266, Sgf_operation_mult_x_1_n2265,
Sgf_operation_mult_x_1_n2264, Sgf_operation_mult_x_1_n2263,
Sgf_operation_mult_x_1_n2262, Sgf_operation_mult_x_1_n2261,
Sgf_operation_mult_x_1_n2260, Sgf_operation_mult_x_1_n2259,
Sgf_operation_mult_x_1_n2258, Sgf_operation_mult_x_1_n2257,
Sgf_operation_mult_x_1_n2256, Sgf_operation_mult_x_1_n2255,
Sgf_operation_mult_x_1_n2254, Sgf_operation_mult_x_1_n2253,
Sgf_operation_mult_x_1_n2252, Sgf_operation_mult_x_1_n2251,
Sgf_operation_mult_x_1_n2250, Sgf_operation_mult_x_1_n2249,
Sgf_operation_mult_x_1_n2248, Sgf_operation_mult_x_1_n2247,
Sgf_operation_mult_x_1_n2246, Sgf_operation_mult_x_1_n2245,
Sgf_operation_mult_x_1_n2243, Sgf_operation_mult_x_1_n2242,
Sgf_operation_mult_x_1_n2241, Sgf_operation_mult_x_1_n2240,
Sgf_operation_mult_x_1_n2239, Sgf_operation_mult_x_1_n2238,
Sgf_operation_mult_x_1_n2237, Sgf_operation_mult_x_1_n2236,
Sgf_operation_mult_x_1_n2235, Sgf_operation_mult_x_1_n2234,
Sgf_operation_mult_x_1_n2233, Sgf_operation_mult_x_1_n2232,
Sgf_operation_mult_x_1_n2231, Sgf_operation_mult_x_1_n2230,
Sgf_operation_mult_x_1_n2229, Sgf_operation_mult_x_1_n2228,
Sgf_operation_mult_x_1_n2227, Sgf_operation_mult_x_1_n2226,
Sgf_operation_mult_x_1_n2225, Sgf_operation_mult_x_1_n2224,
Sgf_operation_mult_x_1_n2223, Sgf_operation_mult_x_1_n2222,
Sgf_operation_mult_x_1_n2220, Sgf_operation_mult_x_1_n2219,
Sgf_operation_mult_x_1_n2218, Sgf_operation_mult_x_1_n2217,
Sgf_operation_mult_x_1_n2216, Sgf_operation_mult_x_1_n2215,
Sgf_operation_mult_x_1_n2214, Sgf_operation_mult_x_1_n2213,
Sgf_operation_mult_x_1_n2212, Sgf_operation_mult_x_1_n2211,
Sgf_operation_mult_x_1_n2210, Sgf_operation_mult_x_1_n2209,
Sgf_operation_mult_x_1_n2208, Sgf_operation_mult_x_1_n2207,
Sgf_operation_mult_x_1_n2206, Sgf_operation_mult_x_1_n2205,
Sgf_operation_mult_x_1_n2204, Sgf_operation_mult_x_1_n2203,
Sgf_operation_mult_x_1_n2202, Sgf_operation_mult_x_1_n2201,
Sgf_operation_mult_x_1_n2200, Sgf_operation_mult_x_1_n2197,
Sgf_operation_mult_x_1_n2195, Sgf_operation_mult_x_1_n2194,
Sgf_operation_mult_x_1_n2193, Sgf_operation_mult_x_1_n2192,
Sgf_operation_mult_x_1_n2191, Sgf_operation_mult_x_1_n2190,
Sgf_operation_mult_x_1_n2189, Sgf_operation_mult_x_1_n2188,
Sgf_operation_mult_x_1_n2187, Sgf_operation_mult_x_1_n2186,
Sgf_operation_mult_x_1_n2185, Sgf_operation_mult_x_1_n2184,
Sgf_operation_mult_x_1_n2183, Sgf_operation_mult_x_1_n2182,
Sgf_operation_mult_x_1_n2181, Sgf_operation_mult_x_1_n2180,
Sgf_operation_mult_x_1_n2179, Sgf_operation_mult_x_1_n2178,
Sgf_operation_mult_x_1_n2177, Sgf_operation_mult_x_1_n2176,
Sgf_operation_mult_x_1_n2175, Sgf_operation_mult_x_1_n2172,
Sgf_operation_mult_x_1_n2171, Sgf_operation_mult_x_1_n2170,
Sgf_operation_mult_x_1_n2169, Sgf_operation_mult_x_1_n2168,
Sgf_operation_mult_x_1_n2167, Sgf_operation_mult_x_1_n2166,
Sgf_operation_mult_x_1_n2165, Sgf_operation_mult_x_1_n2164,
Sgf_operation_mult_x_1_n2163, Sgf_operation_mult_x_1_n2162,
Sgf_operation_mult_x_1_n2161, Sgf_operation_mult_x_1_n2160,
Sgf_operation_mult_x_1_n2159, Sgf_operation_mult_x_1_n2158,
Sgf_operation_mult_x_1_n2157, Sgf_operation_mult_x_1_n2156,
Sgf_operation_mult_x_1_n2155, Sgf_operation_mult_x_1_n2154,
Sgf_operation_mult_x_1_n2153, Sgf_operation_mult_x_1_n2152,
Sgf_operation_mult_x_1_n2151, Sgf_operation_mult_x_1_n2150,
Sgf_operation_mult_x_1_n2148, Sgf_operation_mult_x_1_n2147,
Sgf_operation_mult_x_1_n2146, Sgf_operation_mult_x_1_n2145,
Sgf_operation_mult_x_1_n2144, Sgf_operation_mult_x_1_n2143,
Sgf_operation_mult_x_1_n2142, Sgf_operation_mult_x_1_n2141,
Sgf_operation_mult_x_1_n2140, Sgf_operation_mult_x_1_n2139,
Sgf_operation_mult_x_1_n2138, Sgf_operation_mult_x_1_n2137,
Sgf_operation_mult_x_1_n2136, Sgf_operation_mult_x_1_n2135,
Sgf_operation_mult_x_1_n2134, Sgf_operation_mult_x_1_n2133,
Sgf_operation_mult_x_1_n2132, Sgf_operation_mult_x_1_n2131,
Sgf_operation_mult_x_1_n2130, Sgf_operation_mult_x_1_n2129,
Sgf_operation_mult_x_1_n2128, Sgf_operation_mult_x_1_n2127,
Sgf_operation_mult_x_1_n2126, Sgf_operation_mult_x_1_n2125,
Sgf_operation_mult_x_1_n2124, Sgf_operation_mult_x_1_n2123,
Sgf_operation_mult_x_1_n2122, Sgf_operation_mult_x_1_n2121,
Sgf_operation_mult_x_1_n2120, Sgf_operation_mult_x_1_n2119,
Sgf_operation_mult_x_1_n2118, Sgf_operation_mult_x_1_n2117,
Sgf_operation_mult_x_1_n2116, Sgf_operation_mult_x_1_n2115,
Sgf_operation_mult_x_1_n2114, Sgf_operation_mult_x_1_n2113,
Sgf_operation_mult_x_1_n2112, Sgf_operation_mult_x_1_n2111,
Sgf_operation_mult_x_1_n2110, Sgf_operation_mult_x_1_n2109,
Sgf_operation_mult_x_1_n2108, Sgf_operation_mult_x_1_n2107,
Sgf_operation_mult_x_1_n2106, Sgf_operation_mult_x_1_n2105,
Sgf_operation_mult_x_1_n2104, Sgf_operation_mult_x_1_n2103,
Sgf_operation_mult_x_1_n2102, Sgf_operation_mult_x_1_n2101,
Sgf_operation_mult_x_1_n2100, Sgf_operation_mult_x_1_n2099,
Sgf_operation_mult_x_1_n2098, Sgf_operation_mult_x_1_n2097,
Sgf_operation_mult_x_1_n2096, Sgf_operation_mult_x_1_n2095,
Sgf_operation_mult_x_1_n2094, Sgf_operation_mult_x_1_n2093,
Sgf_operation_mult_x_1_n2092, Sgf_operation_mult_x_1_n2091,
Sgf_operation_mult_x_1_n2090, Sgf_operation_mult_x_1_n2089,
Sgf_operation_mult_x_1_n2088, Sgf_operation_mult_x_1_n2087,
Sgf_operation_mult_x_1_n2086, Sgf_operation_mult_x_1_n2085,
Sgf_operation_mult_x_1_n2084, Sgf_operation_mult_x_1_n2083,
Sgf_operation_mult_x_1_n2082, Sgf_operation_mult_x_1_n2081,
Sgf_operation_mult_x_1_n2080, Sgf_operation_mult_x_1_n2079,
Sgf_operation_mult_x_1_n2078, Sgf_operation_mult_x_1_n2077,
Sgf_operation_mult_x_1_n2076, Sgf_operation_mult_x_1_n2075,
Sgf_operation_mult_x_1_n2074, Sgf_operation_mult_x_1_n2073,
Sgf_operation_mult_x_1_n2072, Sgf_operation_mult_x_1_n2071,
Sgf_operation_mult_x_1_n2070, Sgf_operation_mult_x_1_n2069,
Sgf_operation_mult_x_1_n2068, Sgf_operation_mult_x_1_n2067,
Sgf_operation_mult_x_1_n2066, Sgf_operation_mult_x_1_n2065,
Sgf_operation_mult_x_1_n2064, Sgf_operation_mult_x_1_n2063,
Sgf_operation_mult_x_1_n2062, Sgf_operation_mult_x_1_n2061,
Sgf_operation_mult_x_1_n2060, Sgf_operation_mult_x_1_n2059,
Sgf_operation_mult_x_1_n2058, Sgf_operation_mult_x_1_n2057,
Sgf_operation_mult_x_1_n2056, Sgf_operation_mult_x_1_n2055,
Sgf_operation_mult_x_1_n2054, Sgf_operation_mult_x_1_n2053,
Sgf_operation_mult_x_1_n2052, Sgf_operation_mult_x_1_n2051,
Sgf_operation_mult_x_1_n2050, Sgf_operation_mult_x_1_n2049,
Sgf_operation_mult_x_1_n2048, Sgf_operation_mult_x_1_n2047,
Sgf_operation_mult_x_1_n2046, Sgf_operation_mult_x_1_n2045,
Sgf_operation_mult_x_1_n2044, Sgf_operation_mult_x_1_n2043,
Sgf_operation_mult_x_1_n2042, Sgf_operation_mult_x_1_n2041,
Sgf_operation_mult_x_1_n2040, Sgf_operation_mult_x_1_n2039,
Sgf_operation_mult_x_1_n2038, Sgf_operation_mult_x_1_n2037,
Sgf_operation_mult_x_1_n2036, Sgf_operation_mult_x_1_n2035,
Sgf_operation_mult_x_1_n2034, Sgf_operation_mult_x_1_n2033,
Sgf_operation_mult_x_1_n2032, Sgf_operation_mult_x_1_n2031,
Sgf_operation_mult_x_1_n2030, Sgf_operation_mult_x_1_n2029,
Sgf_operation_mult_x_1_n2028, Sgf_operation_mult_x_1_n2027,
Sgf_operation_mult_x_1_n2026, Sgf_operation_mult_x_1_n2025,
Sgf_operation_mult_x_1_n2024, Sgf_operation_mult_x_1_n2023,
Sgf_operation_mult_x_1_n2022, Sgf_operation_mult_x_1_n2021,
Sgf_operation_mult_x_1_n2020, Sgf_operation_mult_x_1_n2019,
Sgf_operation_mult_x_1_n2018, Sgf_operation_mult_x_1_n2017,
Sgf_operation_mult_x_1_n2016, Sgf_operation_mult_x_1_n2015,
Sgf_operation_mult_x_1_n2014, Sgf_operation_mult_x_1_n2013,
Sgf_operation_mult_x_1_n2012, Sgf_operation_mult_x_1_n2011,
Sgf_operation_mult_x_1_n2010, Sgf_operation_mult_x_1_n2009,
Sgf_operation_mult_x_1_n2008, Sgf_operation_mult_x_1_n2007,
Sgf_operation_mult_x_1_n2006, Sgf_operation_mult_x_1_n2005,
Sgf_operation_mult_x_1_n2004, Sgf_operation_mult_x_1_n2003,
Sgf_operation_mult_x_1_n2002, Sgf_operation_mult_x_1_n2001,
Sgf_operation_mult_x_1_n2000, Sgf_operation_mult_x_1_n1999,
Sgf_operation_mult_x_1_n1998, Sgf_operation_mult_x_1_n1997,
Sgf_operation_mult_x_1_n1996, Sgf_operation_mult_x_1_n1995,
Sgf_operation_mult_x_1_n1994, Sgf_operation_mult_x_1_n1993,
Sgf_operation_mult_x_1_n1992, Sgf_operation_mult_x_1_n1991,
Sgf_operation_mult_x_1_n1990, Sgf_operation_mult_x_1_n1989,
Sgf_operation_mult_x_1_n1988, Sgf_operation_mult_x_1_n1987,
Sgf_operation_mult_x_1_n1986, Sgf_operation_mult_x_1_n1985,
Sgf_operation_mult_x_1_n1984, Sgf_operation_mult_x_1_n1983,
Sgf_operation_mult_x_1_n1982, Sgf_operation_mult_x_1_n1981,
Sgf_operation_mult_x_1_n1980, Sgf_operation_mult_x_1_n1979,
Sgf_operation_mult_x_1_n1978, Sgf_operation_mult_x_1_n1977,
Sgf_operation_mult_x_1_n1976, Sgf_operation_mult_x_1_n1975,
Sgf_operation_mult_x_1_n1974, Sgf_operation_mult_x_1_n1973,
Sgf_operation_mult_x_1_n1972, Sgf_operation_mult_x_1_n1971,
Sgf_operation_mult_x_1_n1970, Sgf_operation_mult_x_1_n1969,
Sgf_operation_mult_x_1_n1968, Sgf_operation_mult_x_1_n1967,
Sgf_operation_mult_x_1_n1966, Sgf_operation_mult_x_1_n1965,
Sgf_operation_mult_x_1_n1964, Sgf_operation_mult_x_1_n1963,
Sgf_operation_mult_x_1_n1962, Sgf_operation_mult_x_1_n1961,
Sgf_operation_mult_x_1_n1960, Sgf_operation_mult_x_1_n1959,
Sgf_operation_mult_x_1_n1958, Sgf_operation_mult_x_1_n1957,
Sgf_operation_mult_x_1_n1956, Sgf_operation_mult_x_1_n1955,
Sgf_operation_mult_x_1_n1954, Sgf_operation_mult_x_1_n1953,
Sgf_operation_mult_x_1_n1952, Sgf_operation_mult_x_1_n1951,
Sgf_operation_mult_x_1_n1950, Sgf_operation_mult_x_1_n1949,
Sgf_operation_mult_x_1_n1948, Sgf_operation_mult_x_1_n1947,
Sgf_operation_mult_x_1_n1946, Sgf_operation_mult_x_1_n1945,
Sgf_operation_mult_x_1_n1944, Sgf_operation_mult_x_1_n1943,
Sgf_operation_mult_x_1_n1942, Sgf_operation_mult_x_1_n1941,
Sgf_operation_mult_x_1_n1940, Sgf_operation_mult_x_1_n1939,
Sgf_operation_mult_x_1_n1938, Sgf_operation_mult_x_1_n1937,
Sgf_operation_mult_x_1_n1936, Sgf_operation_mult_x_1_n1935,
Sgf_operation_mult_x_1_n1934, Sgf_operation_mult_x_1_n1933,
Sgf_operation_mult_x_1_n1930, Sgf_operation_mult_x_1_n1929,
Sgf_operation_mult_x_1_n1928, Sgf_operation_mult_x_1_n1927,
Sgf_operation_mult_x_1_n1926, Sgf_operation_mult_x_1_n1925,
Sgf_operation_mult_x_1_n1924, Sgf_operation_mult_x_1_n1923,
Sgf_operation_mult_x_1_n1922, Sgf_operation_mult_x_1_n1921,
Sgf_operation_mult_x_1_n1920, Sgf_operation_mult_x_1_n1919,
Sgf_operation_mult_x_1_n1918, Sgf_operation_mult_x_1_n1917,
Sgf_operation_mult_x_1_n1916, Sgf_operation_mult_x_1_n1915,
Sgf_operation_mult_x_1_n1914, Sgf_operation_mult_x_1_n1913,
Sgf_operation_mult_x_1_n1912, Sgf_operation_mult_x_1_n1911,
Sgf_operation_mult_x_1_n1910, Sgf_operation_mult_x_1_n1909,
Sgf_operation_mult_x_1_n1908, Sgf_operation_mult_x_1_n1905,
Sgf_operation_mult_x_1_n1904, Sgf_operation_mult_x_1_n1903,
Sgf_operation_mult_x_1_n1902, Sgf_operation_mult_x_1_n1901,
Sgf_operation_mult_x_1_n1900, Sgf_operation_mult_x_1_n1899,
Sgf_operation_mult_x_1_n1898, Sgf_operation_mult_x_1_n1897,
Sgf_operation_mult_x_1_n1896, Sgf_operation_mult_x_1_n1895,
Sgf_operation_mult_x_1_n1894, Sgf_operation_mult_x_1_n1893,
Sgf_operation_mult_x_1_n1892, Sgf_operation_mult_x_1_n1891,
Sgf_operation_mult_x_1_n1890, Sgf_operation_mult_x_1_n1889,
Sgf_operation_mult_x_1_n1888, Sgf_operation_mult_x_1_n1887,
Sgf_operation_mult_x_1_n1886, Sgf_operation_mult_x_1_n1885,
Sgf_operation_mult_x_1_n1884, Sgf_operation_mult_x_1_n1883,
Sgf_operation_mult_x_1_n1882, Sgf_operation_mult_x_1_n1881,
Sgf_operation_mult_x_1_n1880, Sgf_operation_mult_x_1_n1879,
Sgf_operation_mult_x_1_n1878, Sgf_operation_mult_x_1_n1877,
Sgf_operation_mult_x_1_n1876, Sgf_operation_mult_x_1_n1875,
Sgf_operation_mult_x_1_n1874, Sgf_operation_mult_x_1_n1873,
Sgf_operation_mult_x_1_n1872, Sgf_operation_mult_x_1_n1871,
Sgf_operation_mult_x_1_n1870, Sgf_operation_mult_x_1_n1869,
Sgf_operation_mult_x_1_n1868, Sgf_operation_mult_x_1_n1867,
Sgf_operation_mult_x_1_n1866, Sgf_operation_mult_x_1_n1865,
Sgf_operation_mult_x_1_n1864, Sgf_operation_mult_x_1_n1863,
Sgf_operation_mult_x_1_n1862, Sgf_operation_mult_x_1_n1861,
Sgf_operation_mult_x_1_n1860, Sgf_operation_mult_x_1_n1859,
Sgf_operation_mult_x_1_n1858, Sgf_operation_mult_x_1_n1857,
Sgf_operation_mult_x_1_n1856, Sgf_operation_mult_x_1_n1855,
Sgf_operation_mult_x_1_n1854, Sgf_operation_mult_x_1_n1853,
Sgf_operation_mult_x_1_n1852, Sgf_operation_mult_x_1_n1851,
Sgf_operation_mult_x_1_n1850, Sgf_operation_mult_x_1_n1849,
Sgf_operation_mult_x_1_n1848, Sgf_operation_mult_x_1_n1847,
Sgf_operation_mult_x_1_n1846, Sgf_operation_mult_x_1_n1845,
Sgf_operation_mult_x_1_n1844, Sgf_operation_mult_x_1_n1843,
Sgf_operation_mult_x_1_n1842, Sgf_operation_mult_x_1_n1841,
Sgf_operation_mult_x_1_n1840, Sgf_operation_mult_x_1_n1839,
Sgf_operation_mult_x_1_n1838, Sgf_operation_mult_x_1_n1836,
Sgf_operation_mult_x_1_n1835, Sgf_operation_mult_x_1_n1834,
Sgf_operation_mult_x_1_n1833, Sgf_operation_mult_x_1_n1832,
Sgf_operation_mult_x_1_n1831, Sgf_operation_mult_x_1_n1830,
Sgf_operation_mult_x_1_n1829, Sgf_operation_mult_x_1_n1828,
Sgf_operation_mult_x_1_n1827, Sgf_operation_mult_x_1_n1826,
Sgf_operation_mult_x_1_n1825, Sgf_operation_mult_x_1_n1824,
Sgf_operation_mult_x_1_n1823, Sgf_operation_mult_x_1_n1822,
Sgf_operation_mult_x_1_n1821, Sgf_operation_mult_x_1_n1820,
Sgf_operation_mult_x_1_n1819, Sgf_operation_mult_x_1_n1818,
Sgf_operation_mult_x_1_n1817, Sgf_operation_mult_x_1_n1816,
Sgf_operation_mult_x_1_n1815, Sgf_operation_mult_x_1_n1814,
Sgf_operation_mult_x_1_n1813, Sgf_operation_mult_x_1_n1812,
Sgf_operation_mult_x_1_n1811, Sgf_operation_mult_x_1_n1810,
Sgf_operation_mult_x_1_n1809, Sgf_operation_mult_x_1_n1808,
Sgf_operation_mult_x_1_n1807, Sgf_operation_mult_x_1_n1806,
Sgf_operation_mult_x_1_n1805, Sgf_operation_mult_x_1_n1804,
Sgf_operation_mult_x_1_n1803, Sgf_operation_mult_x_1_n1802,
Sgf_operation_mult_x_1_n1801, Sgf_operation_mult_x_1_n1800,
Sgf_operation_mult_x_1_n1799, Sgf_operation_mult_x_1_n1798,
Sgf_operation_mult_x_1_n1797, Sgf_operation_mult_x_1_n1796,
Sgf_operation_mult_x_1_n1795, Sgf_operation_mult_x_1_n1794,
Sgf_operation_mult_x_1_n1792, Sgf_operation_mult_x_1_n1791,
Sgf_operation_mult_x_1_n1790, Sgf_operation_mult_x_1_n1789,
Sgf_operation_mult_x_1_n1788, Sgf_operation_mult_x_1_n1787,
Sgf_operation_mult_x_1_n1786, Sgf_operation_mult_x_1_n1785,
Sgf_operation_mult_x_1_n1784, Sgf_operation_mult_x_1_n1783,
Sgf_operation_mult_x_1_n1782, Sgf_operation_mult_x_1_n1781,
Sgf_operation_mult_x_1_n1780, Sgf_operation_mult_x_1_n1779,
Sgf_operation_mult_x_1_n1778, Sgf_operation_mult_x_1_n1777,
Sgf_operation_mult_x_1_n1776, Sgf_operation_mult_x_1_n1775,
Sgf_operation_mult_x_1_n1774, Sgf_operation_mult_x_1_n1773,
Sgf_operation_mult_x_1_n1770, Sgf_operation_mult_x_1_n1769,
Sgf_operation_mult_x_1_n1768, Sgf_operation_mult_x_1_n1767,
Sgf_operation_mult_x_1_n1766, Sgf_operation_mult_x_1_n1765,
Sgf_operation_mult_x_1_n1764, Sgf_operation_mult_x_1_n1763,
Sgf_operation_mult_x_1_n1762, Sgf_operation_mult_x_1_n1761,
Sgf_operation_mult_x_1_n1760, Sgf_operation_mult_x_1_n1759,
Sgf_operation_mult_x_1_n1758, Sgf_operation_mult_x_1_n1757,
Sgf_operation_mult_x_1_n1756, Sgf_operation_mult_x_1_n1755,
Sgf_operation_mult_x_1_n1754, Sgf_operation_mult_x_1_n1753,
Sgf_operation_mult_x_1_n1752, Sgf_operation_mult_x_1_n1751,
Sgf_operation_mult_x_1_n1750, Sgf_operation_mult_x_1_n1749,
Sgf_operation_mult_x_1_n1748, Sgf_operation_mult_x_1_n1747,
Sgf_operation_mult_x_1_n1746, Sgf_operation_mult_x_1_n1745,
Sgf_operation_mult_x_1_n1744, Sgf_operation_mult_x_1_n1743,
Sgf_operation_mult_x_1_n1742, Sgf_operation_mult_x_1_n1741,
Sgf_operation_mult_x_1_n1740, Sgf_operation_mult_x_1_n1739,
Sgf_operation_mult_x_1_n1738, Sgf_operation_mult_x_1_n1737,
Sgf_operation_mult_x_1_n1736, Sgf_operation_mult_x_1_n1735,
Sgf_operation_mult_x_1_n1734, Sgf_operation_mult_x_1_n1733,
Sgf_operation_mult_x_1_n1732, Sgf_operation_mult_x_1_n1731,
Sgf_operation_mult_x_1_n1730, Sgf_operation_mult_x_1_n1729,
Sgf_operation_mult_x_1_n1728, Sgf_operation_mult_x_1_n1727,
Sgf_operation_mult_x_1_n1726, Sgf_operation_mult_x_1_n1725,
Sgf_operation_mult_x_1_n1724, Sgf_operation_mult_x_1_n1723,
Sgf_operation_mult_x_1_n1722, Sgf_operation_mult_x_1_n1721,
Sgf_operation_mult_x_1_n1720, Sgf_operation_mult_x_1_n1719,
Sgf_operation_mult_x_1_n1718, Sgf_operation_mult_x_1_n1717,
Sgf_operation_mult_x_1_n1716, Sgf_operation_mult_x_1_n1715,
Sgf_operation_mult_x_1_n1714, Sgf_operation_mult_x_1_n1713,
Sgf_operation_mult_x_1_n1712, Sgf_operation_mult_x_1_n1710,
Sgf_operation_mult_x_1_n1709, Sgf_operation_mult_x_1_n1708,
Sgf_operation_mult_x_1_n1707, Sgf_operation_mult_x_1_n1706,
Sgf_operation_mult_x_1_n1705, Sgf_operation_mult_x_1_n1704,
Sgf_operation_mult_x_1_n1703, Sgf_operation_mult_x_1_n1702,
Sgf_operation_mult_x_1_n1701, Sgf_operation_mult_x_1_n1700,
Sgf_operation_mult_x_1_n1699, Sgf_operation_mult_x_1_n1698,
Sgf_operation_mult_x_1_n1697, Sgf_operation_mult_x_1_n1696,
Sgf_operation_mult_x_1_n1695, Sgf_operation_mult_x_1_n1694,
Sgf_operation_mult_x_1_n1693, Sgf_operation_mult_x_1_n1692,
Sgf_operation_mult_x_1_n1691, Sgf_operation_mult_x_1_n1690,
Sgf_operation_mult_x_1_n1689, Sgf_operation_mult_x_1_n1688,
Sgf_operation_mult_x_1_n1687, Sgf_operation_mult_x_1_n1686,
Sgf_operation_mult_x_1_n1685, Sgf_operation_mult_x_1_n1684,
Sgf_operation_mult_x_1_n1683, Sgf_operation_mult_x_1_n1682,
Sgf_operation_mult_x_1_n1681, Sgf_operation_mult_x_1_n1680,
Sgf_operation_mult_x_1_n1679, Sgf_operation_mult_x_1_n1678,
Sgf_operation_mult_x_1_n1677, Sgf_operation_mult_x_1_n1676,
Sgf_operation_mult_x_1_n1675, Sgf_operation_mult_x_1_n1674,
Sgf_operation_mult_x_1_n1673, Sgf_operation_mult_x_1_n1671,
Sgf_operation_mult_x_1_n1670, Sgf_operation_mult_x_1_n1669,
Sgf_operation_mult_x_1_n1668, Sgf_operation_mult_x_1_n1667,
Sgf_operation_mult_x_1_n1666, Sgf_operation_mult_x_1_n1665,
Sgf_operation_mult_x_1_n1664, Sgf_operation_mult_x_1_n1663,
Sgf_operation_mult_x_1_n1662, Sgf_operation_mult_x_1_n1661,
Sgf_operation_mult_x_1_n1660, Sgf_operation_mult_x_1_n1659,
Sgf_operation_mult_x_1_n1658, Sgf_operation_mult_x_1_n1657,
Sgf_operation_mult_x_1_n1656, Sgf_operation_mult_x_1_n1655,
Sgf_operation_mult_x_1_n1652, Sgf_operation_mult_x_1_n1651,
Sgf_operation_mult_x_1_n1650, Sgf_operation_mult_x_1_n1649,
Sgf_operation_mult_x_1_n1648, Sgf_operation_mult_x_1_n1647,
Sgf_operation_mult_x_1_n1646, Sgf_operation_mult_x_1_n1645,
Sgf_operation_mult_x_1_n1644, Sgf_operation_mult_x_1_n1643,
Sgf_operation_mult_x_1_n1642, Sgf_operation_mult_x_1_n1641,
Sgf_operation_mult_x_1_n1640, Sgf_operation_mult_x_1_n1639,
Sgf_operation_mult_x_1_n1638, Sgf_operation_mult_x_1_n1637,
Sgf_operation_mult_x_1_n1636, Sgf_operation_mult_x_1_n1635,
Sgf_operation_mult_x_1_n1634, Sgf_operation_mult_x_1_n1633,
Sgf_operation_mult_x_1_n1632, Sgf_operation_mult_x_1_n1631,
Sgf_operation_mult_x_1_n1630, Sgf_operation_mult_x_1_n1629,
Sgf_operation_mult_x_1_n1628, Sgf_operation_mult_x_1_n1627,
Sgf_operation_mult_x_1_n1626, Sgf_operation_mult_x_1_n1625,
Sgf_operation_mult_x_1_n1624, Sgf_operation_mult_x_1_n1623,
Sgf_operation_mult_x_1_n1622, Sgf_operation_mult_x_1_n1621,
Sgf_operation_mult_x_1_n1620, Sgf_operation_mult_x_1_n1619,
Sgf_operation_mult_x_1_n1618, Sgf_operation_mult_x_1_n1617,
Sgf_operation_mult_x_1_n1616, Sgf_operation_mult_x_1_n1615,
Sgf_operation_mult_x_1_n1614, Sgf_operation_mult_x_1_n1613,
Sgf_operation_mult_x_1_n1612, Sgf_operation_mult_x_1_n1611,
Sgf_operation_mult_x_1_n1610, Sgf_operation_mult_x_1_n1609,
Sgf_operation_mult_x_1_n1608, Sgf_operation_mult_x_1_n1607,
Sgf_operation_mult_x_1_n1606, Sgf_operation_mult_x_1_n1605,
Sgf_operation_mult_x_1_n1604, Sgf_operation_mult_x_1_n1603,
Sgf_operation_mult_x_1_n1601, Sgf_operation_mult_x_1_n1600,
Sgf_operation_mult_x_1_n1599, Sgf_operation_mult_x_1_n1598,
Sgf_operation_mult_x_1_n1597, Sgf_operation_mult_x_1_n1596,
Sgf_operation_mult_x_1_n1595, Sgf_operation_mult_x_1_n1594,
Sgf_operation_mult_x_1_n1593, Sgf_operation_mult_x_1_n1592,
Sgf_operation_mult_x_1_n1591, Sgf_operation_mult_x_1_n1590,
Sgf_operation_mult_x_1_n1589, Sgf_operation_mult_x_1_n1588,
Sgf_operation_mult_x_1_n1587, Sgf_operation_mult_x_1_n1586,
Sgf_operation_mult_x_1_n1585, Sgf_operation_mult_x_1_n1584,
Sgf_operation_mult_x_1_n1583, Sgf_operation_mult_x_1_n1582,
Sgf_operation_mult_x_1_n1581, Sgf_operation_mult_x_1_n1580,
Sgf_operation_mult_x_1_n1579, Sgf_operation_mult_x_1_n1578,
Sgf_operation_mult_x_1_n1577, Sgf_operation_mult_x_1_n1576,
Sgf_operation_mult_x_1_n1575, Sgf_operation_mult_x_1_n1574,
Sgf_operation_mult_x_1_n1573, Sgf_operation_mult_x_1_n1572,
Sgf_operation_mult_x_1_n1571, Sgf_operation_mult_x_1_n1570,
Sgf_operation_mult_x_1_n1569, Sgf_operation_mult_x_1_n1568,
Sgf_operation_mult_x_1_n1567, Sgf_operation_mult_x_1_n1566,
Sgf_operation_mult_x_1_n1565, Sgf_operation_mult_x_1_n1564,
Sgf_operation_mult_x_1_n1563, Sgf_operation_mult_x_1_n1562,
Sgf_operation_mult_x_1_n1561, Sgf_operation_mult_x_1_n1560,
Sgf_operation_mult_x_1_n1559, Sgf_operation_mult_x_1_n1558,
Sgf_operation_mult_x_1_n1557, Sgf_operation_mult_x_1_n1556,
Sgf_operation_mult_x_1_n1553, Sgf_operation_mult_x_1_n1552,
Sgf_operation_mult_x_1_n1551, Sgf_operation_mult_x_1_n1550,
Sgf_operation_mult_x_1_n1549, Sgf_operation_mult_x_1_n1548,
Sgf_operation_mult_x_1_n1547, Sgf_operation_mult_x_1_n1546,
Sgf_operation_mult_x_1_n1545, Sgf_operation_mult_x_1_n1544,
Sgf_operation_mult_x_1_n1543, Sgf_operation_mult_x_1_n1542,
Sgf_operation_mult_x_1_n1541, Sgf_operation_mult_x_1_n1540,
Sgf_operation_mult_x_1_n1539, Sgf_operation_mult_x_1_n1538,
Sgf_operation_mult_x_1_n1537, Sgf_operation_mult_x_1_n1536,
Sgf_operation_mult_x_1_n1535, Sgf_operation_mult_x_1_n1534,
Sgf_operation_mult_x_1_n1533, Sgf_operation_mult_x_1_n1532,
Sgf_operation_mult_x_1_n1531, Sgf_operation_mult_x_1_n1530,
Sgf_operation_mult_x_1_n1529, Sgf_operation_mult_x_1_n1528,
Sgf_operation_mult_x_1_n1527, Sgf_operation_mult_x_1_n1526,
Sgf_operation_mult_x_1_n1525, Sgf_operation_mult_x_1_n1524,
Sgf_operation_mult_x_1_n1523, Sgf_operation_mult_x_1_n1522,
Sgf_operation_mult_x_1_n1521, Sgf_operation_mult_x_1_n1520,
Sgf_operation_mult_x_1_n1519, Sgf_operation_mult_x_1_n1518,
Sgf_operation_mult_x_1_n1517, Sgf_operation_mult_x_1_n1516,
Sgf_operation_mult_x_1_n1515, Sgf_operation_mult_x_1_n1514,
Sgf_operation_mult_x_1_n1513, Sgf_operation_mult_x_1_n1511,
Sgf_operation_mult_x_1_n1510, Sgf_operation_mult_x_1_n1509,
Sgf_operation_mult_x_1_n1508, Sgf_operation_mult_x_1_n1507,
Sgf_operation_mult_x_1_n1506, Sgf_operation_mult_x_1_n1505,
Sgf_operation_mult_x_1_n1504, Sgf_operation_mult_x_1_n1503,
Sgf_operation_mult_x_1_n1502, Sgf_operation_mult_x_1_n1501,
Sgf_operation_mult_x_1_n1500, Sgf_operation_mult_x_1_n1499,
Sgf_operation_mult_x_1_n1498, Sgf_operation_mult_x_1_n1497,
Sgf_operation_mult_x_1_n1496, Sgf_operation_mult_x_1_n1495,
Sgf_operation_mult_x_1_n1494, Sgf_operation_mult_x_1_n1493,
Sgf_operation_mult_x_1_n1492, Sgf_operation_mult_x_1_n1491,
Sgf_operation_mult_x_1_n1490, Sgf_operation_mult_x_1_n1489,
Sgf_operation_mult_x_1_n1488, Sgf_operation_mult_x_1_n1487,
Sgf_operation_mult_x_1_n1484, Sgf_operation_mult_x_1_n1483,
Sgf_operation_mult_x_1_n1482, Sgf_operation_mult_x_1_n1481,
Sgf_operation_mult_x_1_n1480, Sgf_operation_mult_x_1_n1479,
Sgf_operation_mult_x_1_n1478, Sgf_operation_mult_x_1_n1477,
Sgf_operation_mult_x_1_n1476, Sgf_operation_mult_x_1_n1475,
Sgf_operation_mult_x_1_n1474, Sgf_operation_mult_x_1_n1471,
Sgf_operation_mult_x_1_n1470, Sgf_operation_mult_x_1_n1469,
Sgf_operation_mult_x_1_n1468, Sgf_operation_mult_x_1_n1467,
Sgf_operation_mult_x_1_n1466, Sgf_operation_mult_x_1_n1465,
Sgf_operation_mult_x_1_n1464, Sgf_operation_mult_x_1_n1463,
Sgf_operation_mult_x_1_n1462, Sgf_operation_mult_x_1_n1461,
Sgf_operation_mult_x_1_n1460, Sgf_operation_mult_x_1_n1459,
Sgf_operation_mult_x_1_n1458, Sgf_operation_mult_x_1_n1457,
Sgf_operation_mult_x_1_n1456, Sgf_operation_mult_x_1_n1455,
Sgf_operation_mult_x_1_n1454, Sgf_operation_mult_x_1_n1453,
Sgf_operation_mult_x_1_n1452, Sgf_operation_mult_x_1_n1451,
Sgf_operation_mult_x_1_n1450, Sgf_operation_mult_x_1_n1449,
Sgf_operation_mult_x_1_n1448, Sgf_operation_mult_x_1_n1447,
Sgf_operation_mult_x_1_n1446, Sgf_operation_mult_x_1_n1445,
Sgf_operation_mult_x_1_n1444, Sgf_operation_mult_x_1_n1443,
Sgf_operation_mult_x_1_n1442, Sgf_operation_mult_x_1_n1441,
Sgf_operation_mult_x_1_n1440, Sgf_operation_mult_x_1_n1438,
Sgf_operation_mult_x_1_n1437, Sgf_operation_mult_x_1_n1436,
Sgf_operation_mult_x_1_n1435, Sgf_operation_mult_x_1_n1434,
Sgf_operation_mult_x_1_n1433, Sgf_operation_mult_x_1_n1432,
Sgf_operation_mult_x_1_n1431, Sgf_operation_mult_x_1_n1430,
Sgf_operation_mult_x_1_n1429, Sgf_operation_mult_x_1_n1428,
Sgf_operation_mult_x_1_n1427, Sgf_operation_mult_x_1_n1426,
Sgf_operation_mult_x_1_n1425, Sgf_operation_mult_x_1_n1424,
Sgf_operation_mult_x_1_n1423, Sgf_operation_mult_x_1_n1422,
Sgf_operation_mult_x_1_n1421, Sgf_operation_mult_x_1_n1420,
Sgf_operation_mult_x_1_n1417, Sgf_operation_mult_x_1_n1416,
Sgf_operation_mult_x_1_n1415, Sgf_operation_mult_x_1_n1414,
Sgf_operation_mult_x_1_n1413, Sgf_operation_mult_x_1_n1412,
Sgf_operation_mult_x_1_n1411, Sgf_operation_mult_x_1_n1410,
Sgf_operation_mult_x_1_n1407, Sgf_operation_mult_x_1_n1406,
Sgf_operation_mult_x_1_n1405, Sgf_operation_mult_x_1_n1404,
Sgf_operation_mult_x_1_n1403, Sgf_operation_mult_x_1_n1402,
Sgf_operation_mult_x_1_n1401, Sgf_operation_mult_x_1_n1400,
Sgf_operation_mult_x_1_n1399, Sgf_operation_mult_x_1_n1398,
Sgf_operation_mult_x_1_n1397, Sgf_operation_mult_x_1_n1396,
Sgf_operation_mult_x_1_n1395, Sgf_operation_mult_x_1_n1394,
Sgf_operation_mult_x_1_n1393, Sgf_operation_mult_x_1_n1392,
Sgf_operation_mult_x_1_n1391, Sgf_operation_mult_x_1_n1390,
Sgf_operation_mult_x_1_n1389, Sgf_operation_mult_x_1_n1388,
Sgf_operation_mult_x_1_n1387, Sgf_operation_mult_x_1_n1386,
Sgf_operation_mult_x_1_n1385, Sgf_operation_mult_x_1_n1383,
Sgf_operation_mult_x_1_n1382, Sgf_operation_mult_x_1_n1381,
Sgf_operation_mult_x_1_n1380, Sgf_operation_mult_x_1_n1379,
Sgf_operation_mult_x_1_n1378, Sgf_operation_mult_x_1_n1377,
Sgf_operation_mult_x_1_n1376, Sgf_operation_mult_x_1_n1375,
Sgf_operation_mult_x_1_n1374, Sgf_operation_mult_x_1_n1373,
Sgf_operation_mult_x_1_n1372, Sgf_operation_mult_x_1_n1371,
Sgf_operation_mult_x_1_n1368, Sgf_operation_mult_x_1_n1367,
Sgf_operation_mult_x_1_n1366, Sgf_operation_mult_x_1_n1365,
Sgf_operation_mult_x_1_n1364, Sgf_operation_mult_x_1_n1361,
Sgf_operation_mult_x_1_n1360, Sgf_operation_mult_x_1_n1359,
Sgf_operation_mult_x_1_n1358, Sgf_operation_mult_x_1_n1357,
Sgf_operation_mult_x_1_n1356, Sgf_operation_mult_x_1_n1355,
Sgf_operation_mult_x_1_n1354, Sgf_operation_mult_x_1_n1353,
Sgf_operation_mult_x_1_n1352, Sgf_operation_mult_x_1_n1351,
Sgf_operation_mult_x_1_n1350, Sgf_operation_mult_x_1_n1349,
Sgf_operation_mult_x_1_n1348, Sgf_operation_mult_x_1_n1346,
Sgf_operation_mult_x_1_n1345, Sgf_operation_mult_x_1_n1344,
Sgf_operation_mult_x_1_n1343, Sgf_operation_mult_x_1_n1342,
Sgf_operation_mult_x_1_n1341, Sgf_operation_mult_x_1_n1340, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n806, n807, n808, n809, n810, n811, n812, n813,
n814, n815, n816, n817, n818, n819, n820, n821, n822, n823, n824,
n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, n835,
n836, n837, n838, n839, n840, n841, n842, n843, n844, n845, n846,
n847, n848, n849, n850, n851, n852, n853, n854, n855, n856, n857,
n858, n859, n860, n861, n862, n863, n864, n865, n866, n867, n868,
n869, n870, n871, n872, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903,
n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913,
n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923,
n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933,
n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943,
n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953,
n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963,
n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973,
n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983,
n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993,
n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003,
n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013,
n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023,
n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033,
n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043,
n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053,
n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063,
n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073,
n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083,
n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093,
n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103,
n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113,
n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123,
n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133,
n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143,
n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153,
n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163,
n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173,
n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:1] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n608), .CK(clk), .RN(
n5171), .Q(Op_MY[63]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n601), .CK(clk), .RN(
n5164), .QN(n670) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n599), .CK(clk), .RN(
n5173), .QN(n669) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n598), .CK(clk), .RN(
n5168), .QN(n655) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n597), .CK(clk), .RN(
n5176), .QN(n648) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n592), .CK(clk), .RN(
n5175), .QN(n668) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n591), .CK(clk), .RN(
n5164), .QN(n652) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n421), .CK(clk), .RN(n5178),
.QN(n697) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n422), .CK(clk), .RN(n5163),
.Q(Add_result[50]), .QN(n5147) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n423), .CK(clk), .RN(n5174),
.Q(Add_result[49]), .QN(n5100) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n424), .CK(clk), .RN(n5170),
.Q(Add_result[48]), .QN(n5101) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n425), .CK(clk), .RN(n5179),
.Q(Add_result[47]), .QN(n5102) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n426), .CK(clk), .RN(n702),
.Q(Add_result[46]), .QN(n5103) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n427), .CK(clk), .RN(n701),
.Q(Add_result[45]), .QN(n5104) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n428), .CK(clk), .RN(n5170),
.Q(Add_result[44]), .QN(n5105) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n429), .CK(clk), .RN(n5179),
.Q(Add_result[43]), .QN(n5106) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n430), .CK(clk), .RN(n5164),
.Q(Add_result[42]), .QN(n5107) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n431), .CK(clk), .RN(n5173),
.Q(Add_result[41]), .QN(n5108) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n432), .CK(clk), .RN(n5164),
.Q(Add_result[40]), .QN(n5109) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n433), .CK(clk), .RN(n5175),
.Q(Add_result[39]), .QN(n5110) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n434), .CK(clk), .RN(n5173),
.Q(Add_result[38]), .QN(n5111) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n435), .CK(clk), .RN(n5172),
.Q(Add_result[37]), .QN(n5112) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n436), .CK(clk), .RN(n5178),
.Q(Add_result[36]), .QN(n5113) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n437), .CK(clk), .RN(n5163),
.Q(Add_result[35]), .QN(n5114) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n438), .CK(clk), .RN(n5180),
.Q(Add_result[34]), .QN(n5115) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n439), .CK(clk), .RN(n5174),
.Q(Add_result[33]), .QN(n5116) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n440), .CK(clk), .RN(n5178),
.Q(Add_result[32]), .QN(n5117) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n441), .CK(clk), .RN(n5177),
.Q(Add_result[31]), .QN(n5118) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n442), .CK(clk), .RN(n5177),
.Q(Add_result[30]), .QN(n5119) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n443), .CK(clk), .RN(n5177),
.Q(Add_result[29]), .QN(n5120) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n444), .CK(clk), .RN(n5177),
.Q(Add_result[28]), .QN(n5121) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n445), .CK(clk), .RN(n5177),
.Q(Add_result[27]), .QN(n5122) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n446), .CK(clk), .RN(n5177),
.Q(Add_result[26]), .QN(n5123) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n447), .CK(clk), .RN(n5177),
.Q(Add_result[25]), .QN(n5124) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n448), .CK(clk), .RN(n5177),
.Q(Add_result[24]), .QN(n5125) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n449), .CK(clk), .RN(n5177),
.Q(Add_result[23]), .QN(n5126) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n450), .CK(clk), .RN(n5177),
.Q(Add_result[22]), .QN(n5127) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n451), .CK(clk), .RN(n5177),
.Q(Add_result[21]), .QN(n5128) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n452), .CK(clk), .RN(n5177),
.Q(Add_result[20]), .QN(n5129) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n453), .CK(clk), .RN(n881),
.Q(Add_result[19]), .QN(n5130) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n454), .CK(clk), .RN(n881),
.Q(Add_result[18]), .QN(n5131) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n455), .CK(clk), .RN(n881),
.Q(Add_result[17]), .QN(n5132) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n456), .CK(clk), .RN(n5162),
.Q(Add_result[16]), .QN(n5133) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n457), .CK(clk), .RN(n5166),
.Q(Add_result[15]), .QN(n5134) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n458), .CK(clk), .RN(n5161),
.Q(Add_result[14]), .QN(n5135) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n459), .CK(clk), .RN(n5168),
.Q(Add_result[13]), .QN(n5136) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n460), .CK(clk), .RN(n5161),
.Q(Add_result[12]), .QN(n5137) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n461), .CK(clk), .RN(n5171),
.Q(Add_result[11]), .QN(n5138) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n462), .CK(clk), .RN(n5169),
.Q(Add_result[10]), .QN(n5139) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n463), .CK(clk), .RN(n5166),
.Q(Add_result[9]), .QN(n5140) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n464), .CK(clk), .RN(n5168),
.Q(Add_result[8]), .QN(n5141) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n465), .CK(clk), .RN(n5177),
.Q(Add_result[7]), .QN(n5142) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n466), .CK(clk), .RN(n5167),
.Q(Add_result[6]), .QN(n5143) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n467), .CK(clk), .RN(n5175),
.Q(Add_result[5]), .QN(n5144) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n468), .CK(clk), .RN(n5175),
.Q(Add_result[4]), .QN(n5145) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n469), .CK(clk), .RN(n5164),
.Q(Add_result[3]), .QN(n5146) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n470), .CK(clk), .RN(n5173),
.Q(Add_result[2]), .QN(n5097) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n471), .CK(clk), .RN(n5175),
.Q(Add_result[1]), .QN(n5098) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n420), .CK(clk), .RN(n5164),
.Q(Add_result[52]) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n419), .CK(clk), .RN(
n5164), .QN(n654) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n536), .CK(clk), .RN(
n5175), .QN(n656) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n535), .CK(clk), .RN(
n882), .QN(n649) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n532), .CK(clk), .RN(
n883), .QN(n653) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n531), .CK(clk), .RN(
n881), .QN(n647) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n530), .CK(clk), .RN(
n881), .QN(n646) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n528), .CK(clk), .RN(
n5170), .QN(n651) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n404), .CK(clk), .RN(n5162), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Exp_module_exp_result_m_Q_reg_9_ ( .D(n407), .CK(clk), .RN(n701),
.QN(n672) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n473), .CK(clk),
.RN(n5179), .Q(Sgf_normalized_result[52]), .QN(n5148) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n350),
.CK(clk), .RN(n5167), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n349),
.CK(clk), .RN(n5167), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n348),
.CK(clk), .RN(n5167), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n347),
.CK(clk), .RN(n5167), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n346),
.CK(clk), .RN(n5167), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n345),
.CK(clk), .RN(n5167), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n344),
.CK(clk), .RN(n5165), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n343),
.CK(clk), .RN(n5161), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n342),
.CK(clk), .RN(n5171), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n341),
.CK(clk), .RN(n5168), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n340),
.CK(clk), .RN(n5176), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n339),
.CK(clk), .RN(n5168), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n338),
.CK(clk), .RN(n5176), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n337),
.CK(clk), .RN(n5161), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n336),
.CK(clk), .RN(n5172), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n335),
.CK(clk), .RN(n5168), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n334),
.CK(clk), .RN(n5171), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n333),
.CK(clk), .RN(n5172), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n332),
.CK(clk), .RN(n5169), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n331),
.CK(clk), .RN(n5169), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n330),
.CK(clk), .RN(n5169), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n329),
.CK(clk), .RN(n5169), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n328),
.CK(clk), .RN(n5169), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n327),
.CK(clk), .RN(n5169), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n326),
.CK(clk), .RN(n5169), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n325),
.CK(clk), .RN(n5169), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n324),
.CK(clk), .RN(n5169), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n323),
.CK(clk), .RN(n5169), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n322),
.CK(clk), .RN(n5169), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n321),
.CK(clk), .RN(n5169), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n320),
.CK(clk), .RN(n5163), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n319),
.CK(clk), .RN(n5174), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n318),
.CK(clk), .RN(n702), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n317),
.CK(clk), .RN(n701), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n316),
.CK(clk), .RN(n5170), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n315),
.CK(clk), .RN(n5179), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n314),
.CK(clk), .RN(n5180), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n313),
.CK(clk), .RN(n5178), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n312),
.CK(clk), .RN(n5163), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n311),
.CK(clk), .RN(n5174), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n310),
.CK(clk), .RN(n5170), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n309),
.CK(clk), .RN(n702), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n308),
.CK(clk), .RN(n5172), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n307),
.CK(clk), .RN(n5176), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n306),
.CK(clk), .RN(n5161), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n305),
.CK(clk), .RN(n5166), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n304),
.CK(clk), .RN(n5161), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n303),
.CK(clk), .RN(n5166), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n302),
.CK(clk), .RN(n5171), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n301),
.CK(clk), .RN(n5166), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n300),
.CK(clk), .RN(n5165), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n299),
.CK(clk), .RN(n5165), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n298),
.CK(clk), .RN(n5165), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n297),
.CK(clk), .RN(n5165), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n296),
.CK(clk), .RN(n5171), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n295),
.CK(clk), .RN(n5166), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n294),
.CK(clk), .RN(n5168), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n293),
.CK(clk), .RN(n5166), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n292),
.CK(clk), .RN(n5161), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n291),
.CK(clk), .RN(n5171), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n290),
.CK(clk), .RN(n5166), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n289),
.CK(clk), .RN(n5176), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n288),
.CK(clk), .RN(n5168), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n286),
.CK(clk), .RN(n5161), .Q(final_result_ieee[63]), .QN(n5149) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_103_ ( .D(Sgf_operation_n6), .CK(clk),
.RN(n5155), .QN(n696) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_101_ ( .D(Sgf_operation_n8), .CK(clk),
.RN(n5156), .QN(n658) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_100_ ( .D(Sgf_operation_n9), .CK(clk),
.RN(n5156), .QN(n673) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_98_ ( .D(Sgf_operation_n11), .CK(clk),
.RN(n5159), .QN(n674) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_96_ ( .D(Sgf_operation_n13), .CK(clk),
.RN(n5160), .QN(n675) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_94_ ( .D(Sgf_operation_n15), .CK(clk),
.RN(Sgf_operation_n3), .QN(n676) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_92_ ( .D(Sgf_operation_n17), .CK(clk),
.RN(n5157), .QN(n677) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_90_ ( .D(Sgf_operation_n19), .CK(clk),
.RN(n5160), .QN(n678) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_88_ ( .D(Sgf_operation_n21), .CK(clk),
.RN(n5155), .QN(n679) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_86_ ( .D(Sgf_operation_n23), .CK(clk),
.RN(n5153), .QN(n680) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_85_ ( .D(Sgf_operation_n24), .CK(clk),
.RN(n5154), .QN(n659) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_84_ ( .D(Sgf_operation_n25), .CK(clk),
.RN(n5160), .QN(n681) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_83_ ( .D(Sgf_operation_n26), .CK(clk),
.RN(n5155), .QN(n660) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_82_ ( .D(Sgf_operation_n27), .CK(clk),
.RN(n5159), .QN(n682) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_81_ ( .D(Sgf_operation_n28), .CK(clk),
.RN(n5158), .QN(n661) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_80_ ( .D(Sgf_operation_n29), .CK(clk),
.RN(n5157), .QN(n683) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_78_ ( .D(Sgf_operation_n31), .CK(clk),
.RN(n5153), .QN(n684) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_76_ ( .D(Sgf_operation_n33), .CK(clk),
.RN(n5153), .QN(n685) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_74_ ( .D(Sgf_operation_n35), .CK(clk),
.RN(n5156), .QN(n686) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_72_ ( .D(Sgf_operation_n37), .CK(clk),
.RN(n5157), .QN(n687) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_70_ ( .D(Sgf_operation_n39), .CK(clk),
.RN(n5157), .QN(n688) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_68_ ( .D(Sgf_operation_n41), .CK(clk),
.RN(n5157), .QN(n689) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_66_ ( .D(Sgf_operation_n43), .CK(clk),
.RN(n5154), .QN(n650) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_65_ ( .D(Sgf_operation_n44), .CK(clk),
.RN(n5159), .QN(n662) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_64_ ( .D(Sgf_operation_n45), .CK(clk),
.RN(n5155), .QN(n690) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_63_ ( .D(Sgf_operation_n46), .CK(clk),
.RN(n5153), .QN(n663) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_62_ ( .D(Sgf_operation_n47), .CK(clk),
.RN(n5153), .QN(n691) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_61_ ( .D(Sgf_operation_n48), .CK(clk),
.RN(n5160), .QN(n664) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_60_ ( .D(Sgf_operation_n49), .CK(clk),
.RN(n5155), .QN(n692) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_59_ ( .D(Sgf_operation_n50), .CK(clk),
.RN(n5157), .QN(n665) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_58_ ( .D(Sgf_operation_n51), .CK(clk),
.RN(n5155), .QN(n693) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_57_ ( .D(Sgf_operation_n52), .CK(clk),
.RN(n5154), .QN(n666) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_56_ ( .D(Sgf_operation_n53), .CK(clk),
.RN(n5155), .QN(n694) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_55_ ( .D(Sgf_operation_n54), .CK(clk),
.RN(Sgf_operation_n3), .QN(n667) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_54_ ( .D(Sgf_operation_n55), .CK(clk),
.RN(n5155), .QN(n695) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_20_ ( .D(Sgf_operation_n89), .CK(clk),
.RN(n5154), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_19_ ( .D(Sgf_operation_n90), .CK(clk),
.RN(n5158), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_14_ ( .D(Sgf_operation_n95), .CK(clk),
.RN(n5159), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_11_ ( .D(Sgf_operation_n98), .CK(clk),
.RN(n5159), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_6_ ( .D(Sgf_operation_n103), .CK(clk),
.RN(n5158), .Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_4_ ( .D(Sgf_operation_n105), .CK(clk),
.RN(n5157), .Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_0_ ( .D(Sgf_operation_n109), .CK(clk),
.RN(n5156), .Q(P_Sgf[0]) );
CMPR32X2TS DP_OP_31J39_122_605_U13 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_31J39_122_605_n42), .C(DP_OP_31J39_122_605_n28), .CO(
DP_OP_31J39_122_605_n12), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_31J39_122_605_U12 ( .A(DP_OP_31J39_122_605_n27), .B(
S_Oper_A_exp[1]), .C(DP_OP_31J39_122_605_n12), .CO(
DP_OP_31J39_122_605_n11), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_31J39_122_605_U11 ( .A(DP_OP_31J39_122_605_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_31J39_122_605_n11), .CO(
DP_OP_31J39_122_605_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_31J39_122_605_U10 ( .A(DP_OP_31J39_122_605_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_31J39_122_605_n10), .CO(
DP_OP_31J39_122_605_n9), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_31J39_122_605_U9 ( .A(DP_OP_31J39_122_605_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_31J39_122_605_n9), .CO(
DP_OP_31J39_122_605_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_31J39_122_605_U8 ( .A(DP_OP_31J39_122_605_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_31J39_122_605_n8), .CO(
DP_OP_31J39_122_605_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_31J39_122_605_U7 ( .A(DP_OP_31J39_122_605_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_31J39_122_605_n7), .CO(
DP_OP_31J39_122_605_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_31J39_122_605_U6 ( .A(DP_OP_31J39_122_605_n21), .B(
S_Oper_A_exp[7]), .C(DP_OP_31J39_122_605_n6), .CO(
DP_OP_31J39_122_605_n5), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_31J39_122_605_U5 ( .A(DP_OP_31J39_122_605_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_31J39_122_605_n5), .CO(
DP_OP_31J39_122_605_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_31J39_122_605_U4 ( .A(DP_OP_31J39_122_605_n19), .B(
S_Oper_A_exp[9]), .C(DP_OP_31J39_122_605_n4), .CO(
DP_OP_31J39_122_605_n3), .S(Exp_module_Data_S[9]) );
CMPR32X2TS DP_OP_31J39_122_605_U3 ( .A(DP_OP_31J39_122_605_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_31J39_122_605_n3), .CO(
DP_OP_31J39_122_605_n2), .S(Exp_module_Data_S[10]) );
CMPR32X2TS DP_OP_31J39_122_605_U2 ( .A(DP_OP_31J39_122_605_n42), .B(
S_Oper_A_exp[11]), .C(DP_OP_31J39_122_605_n2), .CO(
DP_OP_31J39_122_605_n1), .S(Exp_module_Data_S[11]) );
CMPR42X1TS Sgf_operation_mult_x_1_U1926 ( .A(Sgf_operation_mult_x_1_n2754),
.B(Sgf_operation_mult_x_1_n4299), .C(Sgf_operation_mult_x_1_n2757),
.D(Sgf_operation_mult_x_1_n4405), .ICI(Sgf_operation_mult_x_1_n4352),
.S(Sgf_operation_mult_x_1_n2752), .ICO(Sgf_operation_mult_x_1_n2750),
.CO(Sgf_operation_mult_x_1_n2751) );
CMPR42X1TS Sgf_operation_mult_x_1_U1924 ( .A(Sgf_operation_mult_x_1_n2749),
.B(Sgf_operation_mult_x_1_n4298), .C(Sgf_operation_mult_x_1_n2750),
.D(Sgf_operation_mult_x_1_n4351), .ICI(Sgf_operation_mult_x_1_n4404),
.S(Sgf_operation_mult_x_1_n2747), .ICO(Sgf_operation_mult_x_1_n2745),
.CO(Sgf_operation_mult_x_1_n2746) );
CMPR42X1TS Sgf_operation_mult_x_1_U1919 ( .A(Sgf_operation_mult_x_1_n4349),
.B(Sgf_operation_mult_x_1_n2737), .C(Sgf_operation_mult_x_1_n4296),
.D(Sgf_operation_mult_x_1_n2740), .ICI(Sgf_operation_mult_x_1_n4402),
.S(Sgf_operation_mult_x_1_n2735), .ICO(Sgf_operation_mult_x_1_n2733),
.CO(Sgf_operation_mult_x_1_n2734) );
CMPR42X1TS Sgf_operation_mult_x_1_U1916 ( .A(Sgf_operation_mult_x_1_n4401),
.B(Sgf_operation_mult_x_1_n4295), .C(Sgf_operation_mult_x_1_n2730),
.D(Sgf_operation_mult_x_1_n4348), .ICI(Sgf_operation_mult_x_1_n2733),
.S(Sgf_operation_mult_x_1_n2728), .ICO(Sgf_operation_mult_x_1_n2726),
.CO(Sgf_operation_mult_x_1_n2727) );
CMPR42X1TS Sgf_operation_mult_x_1_U1913 ( .A(Sgf_operation_mult_x_1_n4347),
.B(Sgf_operation_mult_x_1_n4294), .C(Sgf_operation_mult_x_1_n2729),
.D(Sgf_operation_mult_x_1_n2723), .ICI(Sgf_operation_mult_x_1_n2726),
.S(Sgf_operation_mult_x_1_n2721), .ICO(Sgf_operation_mult_x_1_n2719),
.CO(Sgf_operation_mult_x_1_n2720) );
CMPR42X1TS Sgf_operation_mult_x_1_U1911 ( .A(Sgf_operation_mult_x_1_n2718),
.B(Sgf_operation_mult_x_1_n4187), .C(Sgf_operation_mult_x_1_n2724),
.D(Sgf_operation_mult_x_1_n4293), .ICI(Sgf_operation_mult_x_1_n4240),
.S(Sgf_operation_mult_x_1_n2716), .ICO(Sgf_operation_mult_x_1_n2714),
.CO(Sgf_operation_mult_x_1_n2715) );
CMPR42X1TS Sgf_operation_mult_x_1_U1910 ( .A(Sgf_operation_mult_x_1_n4399),
.B(Sgf_operation_mult_x_1_n2722), .C(Sgf_operation_mult_x_1_n2719),
.D(Sgf_operation_mult_x_1_n4346), .ICI(Sgf_operation_mult_x_1_n2716),
.S(Sgf_operation_mult_x_1_n2713), .ICO(Sgf_operation_mult_x_1_n2711),
.CO(Sgf_operation_mult_x_1_n2712) );
CMPR42X1TS Sgf_operation_mult_x_1_U1908 ( .A(Sgf_operation_mult_x_1_n2710),
.B(Sgf_operation_mult_x_1_n4186), .C(Sgf_operation_mult_x_1_n2714),
.D(Sgf_operation_mult_x_1_n4345), .ICI(Sgf_operation_mult_x_1_n4239),
.S(Sgf_operation_mult_x_1_n2708), .ICO(Sgf_operation_mult_x_1_n2706),
.CO(Sgf_operation_mult_x_1_n2707) );
CMPR42X1TS Sgf_operation_mult_x_1_U1907 ( .A(Sgf_operation_mult_x_1_n4292),
.B(Sgf_operation_mult_x_1_n2715), .C(Sgf_operation_mult_x_1_n4398),
.D(Sgf_operation_mult_x_1_n2711), .ICI(Sgf_operation_mult_x_1_n2708),
.S(Sgf_operation_mult_x_1_n2705), .ICO(Sgf_operation_mult_x_1_n2703),
.CO(Sgf_operation_mult_x_1_n2704) );
CMPR42X1TS Sgf_operation_mult_x_1_U1904 ( .A(Sgf_operation_mult_x_1_n4291),
.B(Sgf_operation_mult_x_1_n4238), .C(Sgf_operation_mult_x_1_n2707),
.D(Sgf_operation_mult_x_1_n2703), .ICI(Sgf_operation_mult_x_1_n2700),
.S(Sgf_operation_mult_x_1_n2697), .ICO(Sgf_operation_mult_x_1_n2695),
.CO(Sgf_operation_mult_x_1_n2696) );
CMPR42X1TS Sgf_operation_mult_x_1_U1901 ( .A(Sgf_operation_mult_x_1_n4237),
.B(Sgf_operation_mult_x_1_n2692), .C(Sgf_operation_mult_x_1_n4184),
.D(Sgf_operation_mult_x_1_n4343), .ICI(Sgf_operation_mult_x_1_n4396),
.S(Sgf_operation_mult_x_1_n2690), .ICO(Sgf_operation_mult_x_1_n2688),
.CO(Sgf_operation_mult_x_1_n2689) );
CMPR42X1TS Sgf_operation_mult_x_1_U1900 ( .A(Sgf_operation_mult_x_1_n2698),
.B(Sgf_operation_mult_x_1_n4290), .C(Sgf_operation_mult_x_1_n2699),
.D(Sgf_operation_mult_x_1_n2690), .ICI(Sgf_operation_mult_x_1_n2695),
.S(Sgf_operation_mult_x_1_n2687), .ICO(Sgf_operation_mult_x_1_n2685),
.CO(Sgf_operation_mult_x_1_n2686) );
CMPR42X1TS Sgf_operation_mult_x_1_U1897 ( .A(Sgf_operation_mult_x_1_n4289),
.B(Sgf_operation_mult_x_1_n4183), .C(Sgf_operation_mult_x_1_n4395),
.D(Sgf_operation_mult_x_1_n2682), .ICI(Sgf_operation_mult_x_1_n4342),
.S(Sgf_operation_mult_x_1_n2680), .ICO(Sgf_operation_mult_x_1_n2678),
.CO(Sgf_operation_mult_x_1_n2679) );
CMPR42X1TS Sgf_operation_mult_x_1_U1893 ( .A(Sgf_operation_mult_x_1_n4288),
.B(Sgf_operation_mult_x_1_n4235), .C(Sgf_operation_mult_x_1_n4182),
.D(Sgf_operation_mult_x_1_n2681), .ICI(Sgf_operation_mult_x_1_n4394),
.S(Sgf_operation_mult_x_1_n2670), .ICO(Sgf_operation_mult_x_1_n2668),
.CO(Sgf_operation_mult_x_1_n2669) );
CMPR42X1TS Sgf_operation_mult_x_1_U1890 ( .A(Sgf_operation_mult_x_1_n2664),
.B(Sgf_operation_mult_x_1_n4075), .C(Sgf_operation_mult_x_1_n2673),
.D(Sgf_operation_mult_x_1_n4181), .ICI(Sgf_operation_mult_x_1_n4128),
.S(Sgf_operation_mult_x_1_n2662), .ICO(Sgf_operation_mult_x_1_n2660),
.CO(Sgf_operation_mult_x_1_n2661) );
CMPR42X1TS Sgf_operation_mult_x_1_U1889 ( .A(Sgf_operation_mult_x_1_n4393),
.B(Sgf_operation_mult_x_1_n4287), .C(Sgf_operation_mult_x_1_n2671),
.D(Sgf_operation_mult_x_1_n2668), .ICI(Sgf_operation_mult_x_1_n2662),
.S(Sgf_operation_mult_x_1_n2659), .ICO(Sgf_operation_mult_x_1_n2657),
.CO(Sgf_operation_mult_x_1_n2658) );
CMPR42X1TS Sgf_operation_mult_x_1_U1888 ( .A(Sgf_operation_mult_x_1_n4340),
.B(Sgf_operation_mult_x_1_n4234), .C(Sgf_operation_mult_x_1_n2669),
.D(Sgf_operation_mult_x_1_n2665), .ICI(Sgf_operation_mult_x_1_n2659),
.S(Sgf_operation_mult_x_1_n2656), .ICO(Sgf_operation_mult_x_1_n2654),
.CO(Sgf_operation_mult_x_1_n2655) );
CMPR42X1TS Sgf_operation_mult_x_1_U1886 ( .A(Sgf_operation_mult_x_1_n2653),
.B(Sgf_operation_mult_x_1_n4074), .C(Sgf_operation_mult_x_1_n2660),
.D(Sgf_operation_mult_x_1_n4233), .ICI(Sgf_operation_mult_x_1_n4127),
.S(Sgf_operation_mult_x_1_n2651), .ICO(Sgf_operation_mult_x_1_n2649),
.CO(Sgf_operation_mult_x_1_n2650) );
CMPR42X1TS Sgf_operation_mult_x_1_U1885 ( .A(Sgf_operation_mult_x_1_n4339),
.B(Sgf_operation_mult_x_1_n4180), .C(Sgf_operation_mult_x_1_n2661),
.D(Sgf_operation_mult_x_1_n4392), .ICI(Sgf_operation_mult_x_1_n2657),
.S(Sgf_operation_mult_x_1_n2648), .ICO(Sgf_operation_mult_x_1_n2646),
.CO(Sgf_operation_mult_x_1_n2647) );
CMPR42X1TS Sgf_operation_mult_x_1_U1884 ( .A(Sgf_operation_mult_x_1_n4286),
.B(Sgf_operation_mult_x_1_n2651), .C(Sgf_operation_mult_x_1_n2658),
.D(Sgf_operation_mult_x_1_n2648), .ICI(Sgf_operation_mult_x_1_n2654),
.S(Sgf_operation_mult_x_1_n2645), .ICO(Sgf_operation_mult_x_1_n2643),
.CO(Sgf_operation_mult_x_1_n2644) );
CMPR42X1TS Sgf_operation_mult_x_1_U1881 ( .A(Sgf_operation_mult_x_1_n4232),
.B(Sgf_operation_mult_x_1_n4126), .C(Sgf_operation_mult_x_1_n4179),
.D(Sgf_operation_mult_x_1_n4338), .ICI(Sgf_operation_mult_x_1_n2650),
.S(Sgf_operation_mult_x_1_n2637), .ICO(Sgf_operation_mult_x_1_n2635),
.CO(Sgf_operation_mult_x_1_n2636) );
CMPR42X1TS Sgf_operation_mult_x_1_U1880 ( .A(Sgf_operation_mult_x_1_n2646),
.B(Sgf_operation_mult_x_1_n2640), .C(Sgf_operation_mult_x_1_n2647),
.D(Sgf_operation_mult_x_1_n2637), .ICI(Sgf_operation_mult_x_1_n2643),
.S(Sgf_operation_mult_x_1_n2634), .ICO(Sgf_operation_mult_x_1_n2632),
.CO(Sgf_operation_mult_x_1_n2633) );
CMPR42X1TS Sgf_operation_mult_x_1_U1877 ( .A(Sgf_operation_mult_x_1_n4125),
.B(Sgf_operation_mult_x_1_n2629), .C(Sgf_operation_mult_x_1_n4072),
.D(Sgf_operation_mult_x_1_n4337), .ICI(Sgf_operation_mult_x_1_n4390),
.S(Sgf_operation_mult_x_1_n2627), .ICO(Sgf_operation_mult_x_1_n2625),
.CO(Sgf_operation_mult_x_1_n2626) );
CMPR42X1TS Sgf_operation_mult_x_1_U1876 ( .A(Sgf_operation_mult_x_1_n4231),
.B(Sgf_operation_mult_x_1_n2638), .C(Sgf_operation_mult_x_1_n2635),
.D(Sgf_operation_mult_x_1_n4284), .ICI(Sgf_operation_mult_x_1_n4178),
.S(Sgf_operation_mult_x_1_n2624), .ICO(Sgf_operation_mult_x_1_n2622),
.CO(Sgf_operation_mult_x_1_n2623) );
CMPR42X1TS Sgf_operation_mult_x_1_U1872 ( .A(Sgf_operation_mult_x_1_n4177),
.B(Sgf_operation_mult_x_1_n4071), .C(Sgf_operation_mult_x_1_n4389),
.D(Sgf_operation_mult_x_1_n2616), .ICI(Sgf_operation_mult_x_1_n4336),
.S(Sgf_operation_mult_x_1_n2614), .ICO(Sgf_operation_mult_x_1_n2612),
.CO(Sgf_operation_mult_x_1_n2613) );
CMPR42X1TS Sgf_operation_mult_x_1_U1871 ( .A(Sgf_operation_mult_x_1_n4283),
.B(Sgf_operation_mult_x_1_n4124), .C(Sgf_operation_mult_x_1_n2625),
.D(Sgf_operation_mult_x_1_n4230), .ICI(Sgf_operation_mult_x_1_n2622),
.S(Sgf_operation_mult_x_1_n2611), .ICO(Sgf_operation_mult_x_1_n2609),
.CO(Sgf_operation_mult_x_1_n2610) );
CMPR42X1TS Sgf_operation_mult_x_1_U1870 ( .A(Sgf_operation_mult_x_1_n2626),
.B(Sgf_operation_mult_x_1_n2614), .C(Sgf_operation_mult_x_1_n2623),
.D(Sgf_operation_mult_x_1_n2611), .ICI(Sgf_operation_mult_x_1_n2619),
.S(Sgf_operation_mult_x_1_n2608), .ICO(Sgf_operation_mult_x_1_n2606),
.CO(Sgf_operation_mult_x_1_n2607) );
CMPR42X1TS Sgf_operation_mult_x_1_U1866 ( .A(Sgf_operation_mult_x_1_n4335),
.B(Sgf_operation_mult_x_1_n2612), .C(Sgf_operation_mult_x_1_n2603),
.D(Sgf_operation_mult_x_1_n4388), .ICI(Sgf_operation_mult_x_1_n4282),
.S(Sgf_operation_mult_x_1_n2598), .ICO(Sgf_operation_mult_x_1_n2596),
.CO(Sgf_operation_mult_x_1_n2597) );
CMPR42X1TS Sgf_operation_mult_x_1_U1865 ( .A(Sgf_operation_mult_x_1_n2613),
.B(Sgf_operation_mult_x_1_n2601), .C(Sgf_operation_mult_x_1_n2610),
.D(Sgf_operation_mult_x_1_n2598), .ICI(Sgf_operation_mult_x_1_n2606),
.S(Sgf_operation_mult_x_1_n2595), .ICO(Sgf_operation_mult_x_1_n2593),
.CO(Sgf_operation_mult_x_1_n2594) );
CMPR42X1TS Sgf_operation_mult_x_1_U1863 ( .A(Sgf_operation_mult_x_1_n2592),
.B(Sgf_operation_mult_x_1_n3963), .C(Sgf_operation_mult_x_1_n2604),
.D(Sgf_operation_mult_x_1_n4069), .ICI(Sgf_operation_mult_x_1_n4016),
.S(Sgf_operation_mult_x_1_n2590), .ICO(Sgf_operation_mult_x_1_n2588),
.CO(Sgf_operation_mult_x_1_n2589) );
CMPR42X1TS Sgf_operation_mult_x_1_U1861 ( .A(Sgf_operation_mult_x_1_n2599),
.B(Sgf_operation_mult_x_1_n4334), .C(Sgf_operation_mult_x_1_n4228),
.D(Sgf_operation_mult_x_1_n4122), .ICI(Sgf_operation_mult_x_1_n2600),
.S(Sgf_operation_mult_x_1_n2584), .ICO(Sgf_operation_mult_x_1_n2582),
.CO(Sgf_operation_mult_x_1_n2583) );
CMPR42X1TS Sgf_operation_mult_x_1_U1860 ( .A(Sgf_operation_mult_x_1_n2596),
.B(Sgf_operation_mult_x_1_n2587), .C(Sgf_operation_mult_x_1_n2597),
.D(Sgf_operation_mult_x_1_n2593), .ICI(Sgf_operation_mult_x_1_n2584),
.S(Sgf_operation_mult_x_1_n2581), .ICO(Sgf_operation_mult_x_1_n2579),
.CO(Sgf_operation_mult_x_1_n2580) );
CMPR42X1TS Sgf_operation_mult_x_1_U1858 ( .A(Sgf_operation_mult_x_1_n2578),
.B(Sgf_operation_mult_x_1_n3962), .C(Sgf_operation_mult_x_1_n2588),
.D(Sgf_operation_mult_x_1_n4121), .ICI(Sgf_operation_mult_x_1_n4015),
.S(Sgf_operation_mult_x_1_n2576), .ICO(Sgf_operation_mult_x_1_n2574),
.CO(Sgf_operation_mult_x_1_n2575) );
CMPR42X1TS Sgf_operation_mult_x_1_U1856 ( .A(Sgf_operation_mult_x_1_n2589),
.B(Sgf_operation_mult_x_1_n4174), .C(Sgf_operation_mult_x_1_n4386),
.D(Sgf_operation_mult_x_1_n2576), .ICI(Sgf_operation_mult_x_1_n2586),
.S(Sgf_operation_mult_x_1_n2570), .ICO(Sgf_operation_mult_x_1_n2568),
.CO(Sgf_operation_mult_x_1_n2569) );
CMPR42X1TS Sgf_operation_mult_x_1_U1855 ( .A(Sgf_operation_mult_x_1_n2582),
.B(Sgf_operation_mult_x_1_n2573), .C(Sgf_operation_mult_x_1_n2583),
.D(Sgf_operation_mult_x_1_n2579), .ICI(Sgf_operation_mult_x_1_n2570),
.S(Sgf_operation_mult_x_1_n2567), .ICO(Sgf_operation_mult_x_1_n2565),
.CO(Sgf_operation_mult_x_1_n2566) );
CMPR42X1TS Sgf_operation_mult_x_1_U1852 ( .A(Sgf_operation_mult_x_1_n4120),
.B(Sgf_operation_mult_x_1_n4385), .C(Sgf_operation_mult_x_1_n4067),
.D(Sgf_operation_mult_x_1_n4014), .ICI(Sgf_operation_mult_x_1_n2575),
.S(Sgf_operation_mult_x_1_n2559), .ICO(Sgf_operation_mult_x_1_n2557),
.CO(Sgf_operation_mult_x_1_n2558) );
CMPR42X1TS Sgf_operation_mult_x_1_U1847 ( .A(Sgf_operation_mult_x_1_n4013),
.B(Sgf_operation_mult_x_1_n2548), .C(Sgf_operation_mult_x_1_n3960),
.D(Sgf_operation_mult_x_1_n4225), .ICI(Sgf_operation_mult_x_1_n4172),
.S(Sgf_operation_mult_x_1_n2546), .ICO(Sgf_operation_mult_x_1_n2544),
.CO(Sgf_operation_mult_x_1_n2545) );
CMPR42X1TS Sgf_operation_mult_x_1_U1844 ( .A(Sgf_operation_mult_x_1_n2546),
.B(Sgf_operation_mult_x_1_n2543), .C(Sgf_operation_mult_x_1_n2555),
.D(Sgf_operation_mult_x_1_n2540), .ICI(Sgf_operation_mult_x_1_n2551),
.S(Sgf_operation_mult_x_1_n2537), .ICO(Sgf_operation_mult_x_1_n2535),
.CO(Sgf_operation_mult_x_1_n2536) );
CMPR42X1TS Sgf_operation_mult_x_1_U1841 ( .A(Sgf_operation_mult_x_1_n4065),
.B(Sgf_operation_mult_x_1_n3959), .C(Sgf_operation_mult_x_1_n4171),
.D(Sgf_operation_mult_x_1_n2532), .ICI(Sgf_operation_mult_x_1_n4118),
.S(Sgf_operation_mult_x_1_n2530), .ICO(Sgf_operation_mult_x_1_n2528),
.CO(Sgf_operation_mult_x_1_n2529) );
CMPR42X1TS Sgf_operation_mult_x_1_U1840 ( .A(Sgf_operation_mult_x_1_n4277),
.B(Sgf_operation_mult_x_1_n4012), .C(Sgf_operation_mult_x_1_n2544),
.D(Sgf_operation_mult_x_1_n4383), .ICI(Sgf_operation_mult_x_1_n2541),
.S(Sgf_operation_mult_x_1_n2527), .ICO(Sgf_operation_mult_x_1_n2525),
.CO(Sgf_operation_mult_x_1_n2526) );
CMPR42X1TS Sgf_operation_mult_x_1_U1838 ( .A(Sgf_operation_mult_x_1_n2542),
.B(Sgf_operation_mult_x_1_n2527), .C(Sgf_operation_mult_x_1_n2539),
.D(Sgf_operation_mult_x_1_n2535), .ICI(Sgf_operation_mult_x_1_n2524),
.S(Sgf_operation_mult_x_1_n2521), .ICO(Sgf_operation_mult_x_1_n2519),
.CO(Sgf_operation_mult_x_1_n2520) );
CMPR42X1TS Sgf_operation_mult_x_1_U1830 ( .A(Sgf_operation_mult_x_1_n2502),
.B(Sgf_operation_mult_x_1_n3851), .C(Sgf_operation_mult_x_1_n2517),
.D(Sgf_operation_mult_x_1_n3957), .ICI(Sgf_operation_mult_x_1_n3904),
.S(Sgf_operation_mult_x_1_n2500), .ICO(Sgf_operation_mult_x_1_n2498),
.CO(Sgf_operation_mult_x_1_n2499) );
CMPR42X1TS Sgf_operation_mult_x_1_U1829 ( .A(Sgf_operation_mult_x_1_n4275),
.B(Sgf_operation_mult_x_1_n4169), .C(Sgf_operation_mult_x_1_n4063),
.D(Sgf_operation_mult_x_1_n2515), .ICI(Sgf_operation_mult_x_1_n2509),
.S(Sgf_operation_mult_x_1_n2497), .ICO(Sgf_operation_mult_x_1_n2495),
.CO(Sgf_operation_mult_x_1_n2496) );
CMPR42X1TS Sgf_operation_mult_x_1_U1827 ( .A(Sgf_operation_mult_x_1_n4222),
.B(Sgf_operation_mult_x_1_n4116), .C(Sgf_operation_mult_x_1_n2513),
.D(Sgf_operation_mult_x_1_n2510), .ICI(Sgf_operation_mult_x_1_n2497),
.S(Sgf_operation_mult_x_1_n2491), .ICO(Sgf_operation_mult_x_1_n2489),
.CO(Sgf_operation_mult_x_1_n2490) );
CMPR42X1TS Sgf_operation_mult_x_1_U1826 ( .A(Sgf_operation_mult_x_1_n2506),
.B(Sgf_operation_mult_x_1_n2494), .C(Sgf_operation_mult_x_1_n2507),
.D(Sgf_operation_mult_x_1_n2503), .ICI(Sgf_operation_mult_x_1_n2491),
.S(Sgf_operation_mult_x_1_n2488), .ICO(Sgf_operation_mult_x_1_n2486),
.CO(Sgf_operation_mult_x_1_n2487) );
CMPR42X1TS Sgf_operation_mult_x_1_U1824 ( .A(Sgf_operation_mult_x_1_n2485),
.B(Sgf_operation_mult_x_1_n3850), .C(Sgf_operation_mult_x_1_n2498),
.D(Sgf_operation_mult_x_1_n4009), .ICI(Sgf_operation_mult_x_1_n3903),
.S(Sgf_operation_mult_x_1_n2483), .ICO(Sgf_operation_mult_x_1_n2481),
.CO(Sgf_operation_mult_x_1_n2482) );
CMPR42X1TS Sgf_operation_mult_x_1_U1822 ( .A(Sgf_operation_mult_x_1_n2495),
.B(Sgf_operation_mult_x_1_n2499), .C(Sgf_operation_mult_x_1_n4062),
.D(Sgf_operation_mult_x_1_n4168), .ICI(Sgf_operation_mult_x_1_n2496),
.S(Sgf_operation_mult_x_1_n2477), .ICO(Sgf_operation_mult_x_1_n2475),
.CO(Sgf_operation_mult_x_1_n2476) );
CMPR42X1TS Sgf_operation_mult_x_1_U1821 ( .A(Sgf_operation_mult_x_1_n4380),
.B(Sgf_operation_mult_x_1_n2483), .C(Sgf_operation_mult_x_1_n2492),
.D(Sgf_operation_mult_x_1_n2480), .ICI(Sgf_operation_mult_x_1_n2489),
.S(Sgf_operation_mult_x_1_n2474), .ICO(Sgf_operation_mult_x_1_n2472),
.CO(Sgf_operation_mult_x_1_n2473) );
CMPR42X1TS Sgf_operation_mult_x_1_U1820 ( .A(Sgf_operation_mult_x_1_n2493),
.B(Sgf_operation_mult_x_1_n2477), .C(Sgf_operation_mult_x_1_n2490),
.D(Sgf_operation_mult_x_1_n2474), .ICI(Sgf_operation_mult_x_1_n2486),
.S(Sgf_operation_mult_x_1_n2471), .ICO(Sgf_operation_mult_x_1_n2469),
.CO(Sgf_operation_mult_x_1_n2470) );
CMPR42X1TS Sgf_operation_mult_x_1_U1817 ( .A(Sgf_operation_mult_x_1_n4061),
.B(Sgf_operation_mult_x_1_n4273), .C(Sgf_operation_mult_x_1_n3902),
.D(Sgf_operation_mult_x_1_n3955), .ICI(Sgf_operation_mult_x_1_n2482),
.S(Sgf_operation_mult_x_1_n2463), .ICO(Sgf_operation_mult_x_1_n2461),
.CO(Sgf_operation_mult_x_1_n2462) );
CMPR42X1TS Sgf_operation_mult_x_1_U1816 ( .A(Sgf_operation_mult_x_1_n4379),
.B(Sgf_operation_mult_x_1_n4220), .C(Sgf_operation_mult_x_1_n4114),
.D(Sgf_operation_mult_x_1_n2478), .ICI(Sgf_operation_mult_x_1_n2466),
.S(Sgf_operation_mult_x_1_n2460), .ICO(Sgf_operation_mult_x_1_n2458),
.CO(Sgf_operation_mult_x_1_n2459) );
CMPR42X1TS Sgf_operation_mult_x_1_U1815 ( .A(Sgf_operation_mult_x_1_n4326),
.B(Sgf_operation_mult_x_1_n2475), .C(Sgf_operation_mult_x_1_n2479),
.D(Sgf_operation_mult_x_1_n2463), .ICI(Sgf_operation_mult_x_1_n2476),
.S(Sgf_operation_mult_x_1_n2457), .ICO(Sgf_operation_mult_x_1_n2455),
.CO(Sgf_operation_mult_x_1_n2456) );
CMPR42X1TS Sgf_operation_mult_x_1_U1814 ( .A(Sgf_operation_mult_x_1_n2472),
.B(Sgf_operation_mult_x_1_n2460), .C(Sgf_operation_mult_x_1_n2473),
.D(Sgf_operation_mult_x_1_n2457), .ICI(Sgf_operation_mult_x_1_n2469),
.S(Sgf_operation_mult_x_1_n2454), .ICO(Sgf_operation_mult_x_1_n2452),
.CO(Sgf_operation_mult_x_1_n2453) );
CMPR42X1TS Sgf_operation_mult_x_1_U1811 ( .A(Sgf_operation_mult_x_1_n3901),
.B(Sgf_operation_mult_x_1_n2449), .C(Sgf_operation_mult_x_1_n3848),
.D(Sgf_operation_mult_x_1_n4113), .ICI(Sgf_operation_mult_x_1_n4060),
.S(Sgf_operation_mult_x_1_n2447), .ICO(Sgf_operation_mult_x_1_n2445),
.CO(Sgf_operation_mult_x_1_n2446) );
CMPR42X1TS Sgf_operation_mult_x_1_U1810 ( .A(Sgf_operation_mult_x_1_n4007),
.B(Sgf_operation_mult_x_1_n4219), .C(Sgf_operation_mult_x_1_n4325),
.D(Sgf_operation_mult_x_1_n2464), .ICI(Sgf_operation_mult_x_1_n3954),
.S(Sgf_operation_mult_x_1_n2444), .ICO(Sgf_operation_mult_x_1_n2442),
.CO(Sgf_operation_mult_x_1_n2443) );
CMPR42X1TS Sgf_operation_mult_x_1_U1809 ( .A(Sgf_operation_mult_x_1_n2461),
.B(Sgf_operation_mult_x_1_n4166), .C(Sgf_operation_mult_x_1_n4272),
.D(Sgf_operation_mult_x_1_n4378), .ICI(Sgf_operation_mult_x_1_n2462),
.S(Sgf_operation_mult_x_1_n2441), .ICO(Sgf_operation_mult_x_1_n2439),
.CO(Sgf_operation_mult_x_1_n2440) );
CMPR42X1TS Sgf_operation_mult_x_1_U1808 ( .A(Sgf_operation_mult_x_1_n2458),
.B(Sgf_operation_mult_x_1_n2465), .C(Sgf_operation_mult_x_1_n2447),
.D(Sgf_operation_mult_x_1_n2444), .ICI(Sgf_operation_mult_x_1_n2459),
.S(Sgf_operation_mult_x_1_n2438), .ICO(Sgf_operation_mult_x_1_n2436),
.CO(Sgf_operation_mult_x_1_n2437) );
CMPR42X1TS Sgf_operation_mult_x_1_U1804 ( .A(Sgf_operation_mult_x_1_n3953),
.B(Sgf_operation_mult_x_1_n3847), .C(Sgf_operation_mult_x_1_n4059),
.D(Sgf_operation_mult_x_1_n2430), .ICI(Sgf_operation_mult_x_1_n4112),
.S(Sgf_operation_mult_x_1_n2428), .ICO(Sgf_operation_mult_x_1_n2426),
.CO(Sgf_operation_mult_x_1_n2427) );
CMPR42X1TS Sgf_operation_mult_x_1_U1803 ( .A(Sgf_operation_mult_x_1_n4165),
.B(Sgf_operation_mult_x_1_n3900), .C(Sgf_operation_mult_x_1_n2445),
.D(Sgf_operation_mult_x_1_n4271), .ICI(Sgf_operation_mult_x_1_n2442),
.S(Sgf_operation_mult_x_1_n2425), .ICO(Sgf_operation_mult_x_1_n2423),
.CO(Sgf_operation_mult_x_1_n2424) );
CMPR42X1TS Sgf_operation_mult_x_1_U1802 ( .A(Sgf_operation_mult_x_1_n4377),
.B(Sgf_operation_mult_x_1_n4218), .C(Sgf_operation_mult_x_1_n4006),
.D(Sgf_operation_mult_x_1_n4324), .ICI(Sgf_operation_mult_x_1_n2439),
.S(Sgf_operation_mult_x_1_n2422), .ICO(Sgf_operation_mult_x_1_n2420),
.CO(Sgf_operation_mult_x_1_n2421) );
CMPR42X1TS Sgf_operation_mult_x_1_U1800 ( .A(Sgf_operation_mult_x_1_n2425),
.B(Sgf_operation_mult_x_1_n2422), .C(Sgf_operation_mult_x_1_n2437),
.D(Sgf_operation_mult_x_1_n2419), .ICI(Sgf_operation_mult_x_1_n2433),
.S(Sgf_operation_mult_x_1_n2416), .ICO(Sgf_operation_mult_x_1_n2414),
.CO(Sgf_operation_mult_x_1_n2415) );
CMPR42X1TS Sgf_operation_mult_x_1_U1796 ( .A(Sgf_operation_mult_x_1_n3952),
.B(Sgf_operation_mult_x_1_n4217), .C(Sgf_operation_mult_x_1_n4323),
.D(Sgf_operation_mult_x_1_n2426), .ICI(Sgf_operation_mult_x_1_n4164),
.S(Sgf_operation_mult_x_1_n2406), .ICO(Sgf_operation_mult_x_1_n2404),
.CO(Sgf_operation_mult_x_1_n2405) );
CMPR42X1TS Sgf_operation_mult_x_1_U1794 ( .A(Sgf_operation_mult_x_1_n2420),
.B(Sgf_operation_mult_x_1_n2409), .C(Sgf_operation_mult_x_1_n2424),
.D(Sgf_operation_mult_x_1_n2406), .ICI(Sgf_operation_mult_x_1_n2417),
.S(Sgf_operation_mult_x_1_n2400), .ICO(Sgf_operation_mult_x_1_n2398),
.CO(Sgf_operation_mult_x_1_n2399) );
CMPR42X1TS Sgf_operation_mult_x_1_U1791 ( .A(Sgf_operation_mult_x_1_n2394),
.B(Sgf_operation_mult_x_1_n3740), .C(Sgf_operation_mult_x_1_n2412),
.D(Sgf_operation_mult_x_1_n3845), .ICI(Sgf_operation_mult_x_1_n3793),
.S(Sgf_operation_mult_x_1_n2392), .ICO(Sgf_operation_mult_x_1_n2390),
.CO(Sgf_operation_mult_x_1_n2391) );
CMPR42X1TS Sgf_operation_mult_x_1_U1787 ( .A(Sgf_operation_mult_x_1_n2408),
.B(Sgf_operation_mult_x_1_n2405), .C(Sgf_operation_mult_x_1_n2389),
.D(Sgf_operation_mult_x_1_n2386), .ICI(Sgf_operation_mult_x_1_n2402),
.S(Sgf_operation_mult_x_1_n2380), .ICO(Sgf_operation_mult_x_1_n2378),
.CO(Sgf_operation_mult_x_1_n2379) );
CMPR42X1TS Sgf_operation_mult_x_1_U1786 ( .A(Sgf_operation_mult_x_1_n2398),
.B(Sgf_operation_mult_x_1_n2383), .C(Sgf_operation_mult_x_1_n2399),
.D(Sgf_operation_mult_x_1_n2380), .ICI(Sgf_operation_mult_x_1_n2395),
.S(Sgf_operation_mult_x_1_n2377), .ICO(Sgf_operation_mult_x_1_n2375),
.CO(Sgf_operation_mult_x_1_n2376) );
CMPR42X1TS Sgf_operation_mult_x_1_U1784 ( .A(Sgf_operation_mult_x_1_n2374),
.B(Sgf_operation_mult_x_1_n3739), .C(Sgf_operation_mult_x_1_n2390),
.D(Sgf_operation_mult_x_1_n3897), .ICI(Sgf_operation_mult_x_1_n3792),
.S(Sgf_operation_mult_x_1_n2372), .ICO(Sgf_operation_mult_x_1_n2370),
.CO(Sgf_operation_mult_x_1_n2371) );
CMPR42X1TS Sgf_operation_mult_x_1_U1781 ( .A(Sgf_operation_mult_x_1_n2391),
.B(Sgf_operation_mult_x_1_n4374), .C(Sgf_operation_mult_x_1_n4268),
.D(Sgf_operation_mult_x_1_n2372), .ICI(Sgf_operation_mult_x_1_n2388),
.S(Sgf_operation_mult_x_1_n2363), .ICO(Sgf_operation_mult_x_1_n2361),
.CO(Sgf_operation_mult_x_1_n2362) );
CMPR42X1TS Sgf_operation_mult_x_1_U1779 ( .A(Sgf_operation_mult_x_1_n2378),
.B(Sgf_operation_mult_x_1_n2363), .C(Sgf_operation_mult_x_1_n2379),
.D(Sgf_operation_mult_x_1_n2360), .ICI(Sgf_operation_mult_x_1_n2375),
.S(Sgf_operation_mult_x_1_n2357), .ICO(Sgf_operation_mult_x_1_n2355),
.CO(Sgf_operation_mult_x_1_n2356) );
CMPR42X1TS Sgf_operation_mult_x_1_U1776 ( .A(Sgf_operation_mult_x_1_n3949),
.B(Sgf_operation_mult_x_1_n4161), .C(Sgf_operation_mult_x_1_n3843),
.D(Sgf_operation_mult_x_1_n3791), .ICI(Sgf_operation_mult_x_1_n2371),
.S(Sgf_operation_mult_x_1_n2349), .ICO(Sgf_operation_mult_x_1_n2347),
.CO(Sgf_operation_mult_x_1_n2348) );
CMPR42X1TS Sgf_operation_mult_x_1_U1775 ( .A(Sgf_operation_mult_x_1_n4373),
.B(Sgf_operation_mult_x_1_n4267), .C(Sgf_operation_mult_x_1_n4002),
.D(Sgf_operation_mult_x_1_n4108), .ICI(Sgf_operation_mult_x_1_n2352),
.S(Sgf_operation_mult_x_1_n2346), .ICO(Sgf_operation_mult_x_1_n2344),
.CO(Sgf_operation_mult_x_1_n2345) );
CMPR42X1TS Sgf_operation_mult_x_1_U1774 ( .A(Sgf_operation_mult_x_1_n2367),
.B(Sgf_operation_mult_x_1_n4320), .C(Sgf_operation_mult_x_1_n4214),
.D(Sgf_operation_mult_x_1_n2364), .ICI(Sgf_operation_mult_x_1_n2361),
.S(Sgf_operation_mult_x_1_n2343), .ICO(Sgf_operation_mult_x_1_n2341),
.CO(Sgf_operation_mult_x_1_n2342) );
CMPR42X1TS Sgf_operation_mult_x_1_U1773 ( .A(Sgf_operation_mult_x_1_n2368),
.B(Sgf_operation_mult_x_1_n2349), .C(Sgf_operation_mult_x_1_n2365),
.D(Sgf_operation_mult_x_1_n2346), .ICI(Sgf_operation_mult_x_1_n2362),
.S(Sgf_operation_mult_x_1_n2340), .ICO(Sgf_operation_mult_x_1_n2338),
.CO(Sgf_operation_mult_x_1_n2339) );
CMPR42X1TS Sgf_operation_mult_x_1_U1772 ( .A(Sgf_operation_mult_x_1_n2358),
.B(Sgf_operation_mult_x_1_n2343), .C(Sgf_operation_mult_x_1_n2359),
.D(Sgf_operation_mult_x_1_n2340), .ICI(Sgf_operation_mult_x_1_n2355),
.S(Sgf_operation_mult_x_1_n2337), .ICO(Sgf_operation_mult_x_1_n2335),
.CO(Sgf_operation_mult_x_1_n2336) );
CMPR42X1TS Sgf_operation_mult_x_1_U1769 ( .A(Sgf_operation_mult_x_1_n3790),
.B(Sgf_operation_mult_x_1_n2332), .C(Sgf_operation_mult_x_1_n3737),
.D(Sgf_operation_mult_x_1_n4001), .ICI(Sgf_operation_mult_x_1_n3948),
.S(Sgf_operation_mult_x_1_n2330), .ICO(Sgf_operation_mult_x_1_n2328),
.CO(Sgf_operation_mult_x_1_n2329) );
CMPR42X1TS Sgf_operation_mult_x_1_U1768 ( .A(Sgf_operation_mult_x_1_n3895),
.B(Sgf_operation_mult_x_1_n4107), .C(Sgf_operation_mult_x_1_n4213),
.D(Sgf_operation_mult_x_1_n4319), .ICI(Sgf_operation_mult_x_1_n3842),
.S(Sgf_operation_mult_x_1_n2327), .ICO(Sgf_operation_mult_x_1_n2325),
.CO(Sgf_operation_mult_x_1_n2326) );
CMPR42X1TS Sgf_operation_mult_x_1_U1767 ( .A(Sgf_operation_mult_x_1_n2350),
.B(Sgf_operation_mult_x_1_n2347), .C(Sgf_operation_mult_x_1_n4054),
.D(Sgf_operation_mult_x_1_n4160), .ICI(Sgf_operation_mult_x_1_n2348),
.S(Sgf_operation_mult_x_1_n2324), .ICO(Sgf_operation_mult_x_1_n2322),
.CO(Sgf_operation_mult_x_1_n2323) );
CMPR42X1TS Sgf_operation_mult_x_1_U1766 ( .A(Sgf_operation_mult_x_1_n4372),
.B(Sgf_operation_mult_x_1_n2344), .C(Sgf_operation_mult_x_1_n2351),
.D(Sgf_operation_mult_x_1_n2330), .ICI(Sgf_operation_mult_x_1_n2345),
.S(Sgf_operation_mult_x_1_n2321), .ICO(Sgf_operation_mult_x_1_n2319),
.CO(Sgf_operation_mult_x_1_n2320) );
CMPR42X1TS Sgf_operation_mult_x_1_U1765 ( .A(Sgf_operation_mult_x_1_n4266),
.B(Sgf_operation_mult_x_1_n2341), .C(Sgf_operation_mult_x_1_n2327),
.D(Sgf_operation_mult_x_1_n2324), .ICI(Sgf_operation_mult_x_1_n2338),
.S(Sgf_operation_mult_x_1_n2318), .ICO(Sgf_operation_mult_x_1_n2316),
.CO(Sgf_operation_mult_x_1_n2317) );
CMPR42X1TS Sgf_operation_mult_x_1_U1761 ( .A(Sgf_operation_mult_x_1_n3841),
.B(Sgf_operation_mult_x_1_n3736), .C(Sgf_operation_mult_x_1_n3947),
.D(Sgf_operation_mult_x_1_n2310), .ICI(Sgf_operation_mult_x_1_n3894),
.S(Sgf_operation_mult_x_1_n2308), .ICO(Sgf_operation_mult_x_1_n2306),
.CO(Sgf_operation_mult_x_1_n2307) );
CMPR42X1TS Sgf_operation_mult_x_1_U1760 ( .A(Sgf_operation_mult_x_1_n4053),
.B(Sgf_operation_mult_x_1_n3789), .C(Sgf_operation_mult_x_1_n2328),
.D(Sgf_operation_mult_x_1_n4371), .ICI(Sgf_operation_mult_x_1_n2325),
.S(Sgf_operation_mult_x_1_n2305), .ICO(Sgf_operation_mult_x_1_n2303),
.CO(Sgf_operation_mult_x_1_n2304) );
CMPR42X1TS Sgf_operation_mult_x_1_U1759 ( .A(Sgf_operation_mult_x_1_n4265),
.B(Sgf_operation_mult_x_1_n4159), .C(Sgf_operation_mult_x_1_n4000),
.D(Sgf_operation_mult_x_1_n4106), .ICI(Sgf_operation_mult_x_1_n2329),
.S(Sgf_operation_mult_x_1_n2302), .ICO(Sgf_operation_mult_x_1_n2300),
.CO(Sgf_operation_mult_x_1_n2301) );
CMPR42X1TS Sgf_operation_mult_x_1_U1758 ( .A(Sgf_operation_mult_x_1_n4318),
.B(Sgf_operation_mult_x_1_n4212), .C(Sgf_operation_mult_x_1_n2322),
.D(Sgf_operation_mult_x_1_n2308), .ICI(Sgf_operation_mult_x_1_n2302),
.S(Sgf_operation_mult_x_1_n2299), .ICO(Sgf_operation_mult_x_1_n2297),
.CO(Sgf_operation_mult_x_1_n2298) );
CMPR42X1TS Sgf_operation_mult_x_1_U1752 ( .A(Sgf_operation_mult_x_1_n3893),
.B(Sgf_operation_mult_x_1_n3788), .C(Sgf_operation_mult_x_1_n4317),
.D(Sgf_operation_mult_x_1_n4211), .ICI(Sgf_operation_mult_x_1_n4052),
.S(Sgf_operation_mult_x_1_n2283), .ICO(Sgf_operation_mult_x_1_n2281),
.CO(Sgf_operation_mult_x_1_n2282) );
CMPR42X1TS Sgf_operation_mult_x_1_U1751 ( .A(Sgf_operation_mult_x_1_n2306),
.B(Sgf_operation_mult_x_1_n2288), .C(Sgf_operation_mult_x_1_n3946),
.D(Sgf_operation_mult_x_1_n4158), .ICI(Sgf_operation_mult_x_1_n2307),
.S(Sgf_operation_mult_x_1_n2280), .ICO(Sgf_operation_mult_x_1_n2278),
.CO(Sgf_operation_mult_x_1_n2279) );
CMPR42X1TS Sgf_operation_mult_x_1_U1750 ( .A(Sgf_operation_mult_x_1_n4370),
.B(Sgf_operation_mult_x_1_n4264), .C(Sgf_operation_mult_x_1_n2300),
.D(Sgf_operation_mult_x_1_n2286), .ICI(Sgf_operation_mult_x_1_n2301),
.S(Sgf_operation_mult_x_1_n2277), .ICO(Sgf_operation_mult_x_1_n2275),
.CO(Sgf_operation_mult_x_1_n2276) );
CMPR42X1TS Sgf_operation_mult_x_1_U1749 ( .A(Sgf_operation_mult_x_1_n2297),
.B(Sgf_operation_mult_x_1_n2304), .C(Sgf_operation_mult_x_1_n2283),
.D(Sgf_operation_mult_x_1_n2294), .ICI(Sgf_operation_mult_x_1_n2298),
.S(Sgf_operation_mult_x_1_n2274), .ICO(Sgf_operation_mult_x_1_n2272),
.CO(Sgf_operation_mult_x_1_n2273) );
CMPR42X1TS Sgf_operation_mult_x_1_U1748 ( .A(Sgf_operation_mult_x_1_n2280),
.B(Sgf_operation_mult_x_1_n2277), .C(Sgf_operation_mult_x_1_n2295),
.D(Sgf_operation_mult_x_1_n2274), .ICI(Sgf_operation_mult_x_1_n2291),
.S(Sgf_operation_mult_x_1_n2271), .ICO(Sgf_operation_mult_x_1_n2269),
.CO(Sgf_operation_mult_x_1_n2270) );
CMPR42X1TS Sgf_operation_mult_x_1_U1746 ( .A(Sgf_operation_mult_x_1_n2268),
.B(Sgf_operation_mult_x_1_n3629), .C(Sgf_operation_mult_x_1_n2289),
.D(Sgf_operation_mult_x_1_n3734), .ICI(Sgf_operation_mult_x_1_n3682),
.S(Sgf_operation_mult_x_1_n2266), .ICO(Sgf_operation_mult_x_1_n2264),
.CO(Sgf_operation_mult_x_1_n2265) );
CMPR42X1TS Sgf_operation_mult_x_1_U1744 ( .A(Sgf_operation_mult_x_1_n4263),
.B(Sgf_operation_mult_x_1_n4157), .C(Sgf_operation_mult_x_1_n4104),
.D(Sgf_operation_mult_x_1_n3787), .ICI(Sgf_operation_mult_x_1_n2278),
.S(Sgf_operation_mult_x_1_n2260), .ICO(Sgf_operation_mult_x_1_n2258),
.CO(Sgf_operation_mult_x_1_n2259) );
CMPR42X1TS Sgf_operation_mult_x_1_U1743 ( .A(Sgf_operation_mult_x_1_n4369),
.B(Sgf_operation_mult_x_1_n2284), .C(Sgf_operation_mult_x_1_n3892),
.D(Sgf_operation_mult_x_1_n3998), .ICI(Sgf_operation_mult_x_1_n4210),
.S(Sgf_operation_mult_x_1_n2257), .ICO(Sgf_operation_mult_x_1_n2255),
.CO(Sgf_operation_mult_x_1_n2256) );
CMPR42X1TS Sgf_operation_mult_x_1_U1742 ( .A(Sgf_operation_mult_x_1_n2281),
.B(Sgf_operation_mult_x_1_n4316), .C(Sgf_operation_mult_x_1_n2285),
.D(Sgf_operation_mult_x_1_n2275), .ICI(Sgf_operation_mult_x_1_n2263),
.S(Sgf_operation_mult_x_1_n2254), .ICO(Sgf_operation_mult_x_1_n2252),
.CO(Sgf_operation_mult_x_1_n2253) );
CMPR42X1TS Sgf_operation_mult_x_1_U1740 ( .A(Sgf_operation_mult_x_1_n2272),
.B(Sgf_operation_mult_x_1_n2254), .C(Sgf_operation_mult_x_1_n2273),
.D(Sgf_operation_mult_x_1_n2251), .ICI(Sgf_operation_mult_x_1_n2269),
.S(Sgf_operation_mult_x_1_n2248), .ICO(Sgf_operation_mult_x_1_n2246),
.CO(Sgf_operation_mult_x_1_n2247) );
CMPR42X1TS Sgf_operation_mult_x_1_U1738 ( .A(Sgf_operation_mult_x_1_n2245),
.B(Sgf_operation_mult_x_1_n3628), .C(Sgf_operation_mult_x_1_n2264),
.D(Sgf_operation_mult_x_1_n3786), .ICI(Sgf_operation_mult_x_1_n3681),
.S(Sgf_operation_mult_x_1_n2243), .ICO(Sgf_operation_mult_x_1_n2241),
.CO(Sgf_operation_mult_x_1_n2242) );
CMPR42X1TS Sgf_operation_mult_x_1_U1735 ( .A(Sgf_operation_mult_x_1_n2261),
.B(Sgf_operation_mult_x_1_n2265), .C(Sgf_operation_mult_x_1_n4368),
.D(Sgf_operation_mult_x_1_n4262), .ICI(Sgf_operation_mult_x_1_n2262),
.S(Sgf_operation_mult_x_1_n2234), .ICO(Sgf_operation_mult_x_1_n2232),
.CO(Sgf_operation_mult_x_1_n2233) );
CMPR42X1TS Sgf_operation_mult_x_1_U1734 ( .A(Sgf_operation_mult_x_1_n4156),
.B(Sgf_operation_mult_x_1_n2243), .C(Sgf_operation_mult_x_1_n2255),
.D(Sgf_operation_mult_x_1_n2240), .ICI(Sgf_operation_mult_x_1_n2237),
.S(Sgf_operation_mult_x_1_n2231), .ICO(Sgf_operation_mult_x_1_n2229),
.CO(Sgf_operation_mult_x_1_n2230) );
CMPR42X1TS Sgf_operation_mult_x_1_U1732 ( .A(Sgf_operation_mult_x_1_n2249),
.B(Sgf_operation_mult_x_1_n2231), .C(Sgf_operation_mult_x_1_n2250),
.D(Sgf_operation_mult_x_1_n2228), .ICI(Sgf_operation_mult_x_1_n2246),
.S(Sgf_operation_mult_x_1_n2225), .ICO(Sgf_operation_mult_x_1_n2223),
.CO(Sgf_operation_mult_x_1_n2224) );
CMPR42X1TS Sgf_operation_mult_x_1_U1729 ( .A(Sgf_operation_mult_x_1_n3943),
.B(Sgf_operation_mult_x_1_n3732), .C(Sgf_operation_mult_x_1_n3680),
.D(Sgf_operation_mult_x_1_n4049), .ICI(Sgf_operation_mult_x_1_n2242),
.S(Sgf_operation_mult_x_1_n2217), .ICO(Sgf_operation_mult_x_1_n2215),
.CO(Sgf_operation_mult_x_1_n2216) );
CMPR42X1TS Sgf_operation_mult_x_1_U1728 ( .A(Sgf_operation_mult_x_1_n4367),
.B(Sgf_operation_mult_x_1_n4261), .C(Sgf_operation_mult_x_1_n3996),
.D(Sgf_operation_mult_x_1_n3890), .ICI(Sgf_operation_mult_x_1_n2220),
.S(Sgf_operation_mult_x_1_n2214), .ICO(Sgf_operation_mult_x_1_n2212),
.CO(Sgf_operation_mult_x_1_n2213) );
CMPR42X1TS Sgf_operation_mult_x_1_U1727 ( .A(Sgf_operation_mult_x_1_n4155),
.B(Sgf_operation_mult_x_1_n2238), .C(Sgf_operation_mult_x_1_n4102),
.D(Sgf_operation_mult_x_1_n4208), .ICI(Sgf_operation_mult_x_1_n2235),
.S(Sgf_operation_mult_x_1_n2211), .ICO(Sgf_operation_mult_x_1_n2209),
.CO(Sgf_operation_mult_x_1_n2210) );
CMPR42X1TS Sgf_operation_mult_x_1_U1726 ( .A(Sgf_operation_mult_x_1_n4314),
.B(Sgf_operation_mult_x_1_n2239), .C(Sgf_operation_mult_x_1_n2232),
.D(Sgf_operation_mult_x_1_n2217), .ICI(Sgf_operation_mult_x_1_n2214),
.S(Sgf_operation_mult_x_1_n2208), .ICO(Sgf_operation_mult_x_1_n2206),
.CO(Sgf_operation_mult_x_1_n2207) );
CMPR42X1TS Sgf_operation_mult_x_1_U1721 ( .A(Sgf_operation_mult_x_1_n3679),
.B(Sgf_operation_mult_x_1_n2197), .C(Sgf_operation_mult_x_1_n3626),
.D(Sgf_operation_mult_x_1_n3995), .ICI(Sgf_operation_mult_x_1_n3836),
.S(Sgf_operation_mult_x_1_n2195), .ICO(Sgf_operation_mult_x_1_n2193),
.CO(Sgf_operation_mult_x_1_n2194) );
CMPR42X1TS Sgf_operation_mult_x_1_U1720 ( .A(Sgf_operation_mult_x_1_n3784),
.B(Sgf_operation_mult_x_1_n3889), .C(Sgf_operation_mult_x_1_n4101),
.D(Sgf_operation_mult_x_1_n4207), .ICI(Sgf_operation_mult_x_1_n4048),
.S(Sgf_operation_mult_x_1_n2192), .ICO(Sgf_operation_mult_x_1_n2190),
.CO(Sgf_operation_mult_x_1_n2191) );
CMPR42X1TS Sgf_operation_mult_x_1_U1719 ( .A(Sgf_operation_mult_x_1_n4313),
.B(Sgf_operation_mult_x_1_n2218), .C(Sgf_operation_mult_x_1_n3942),
.D(Sgf_operation_mult_x_1_n3731), .ICI(Sgf_operation_mult_x_1_n2195),
.S(Sgf_operation_mult_x_1_n2189), .ICO(Sgf_operation_mult_x_1_n2187),
.CO(Sgf_operation_mult_x_1_n2188) );
CMPR42X1TS Sgf_operation_mult_x_1_U1718 ( .A(Sgf_operation_mult_x_1_n2215),
.B(Sgf_operation_mult_x_1_n4366), .C(Sgf_operation_mult_x_1_n4260),
.D(Sgf_operation_mult_x_1_n4154), .ICI(Sgf_operation_mult_x_1_n2209),
.S(Sgf_operation_mult_x_1_n2186), .ICO(Sgf_operation_mult_x_1_n2184),
.CO(Sgf_operation_mult_x_1_n2185) );
CMPR42X1TS Sgf_operation_mult_x_1_U1717 ( .A(Sgf_operation_mult_x_1_n2212),
.B(Sgf_operation_mult_x_1_n2219), .C(Sgf_operation_mult_x_1_n2216),
.D(Sgf_operation_mult_x_1_n2192), .ICI(Sgf_operation_mult_x_1_n2206),
.S(Sgf_operation_mult_x_1_n2183), .ICO(Sgf_operation_mult_x_1_n2181),
.CO(Sgf_operation_mult_x_1_n2182) );
CMPR42X1TS Sgf_operation_mult_x_1_U1716 ( .A(Sgf_operation_mult_x_1_n2213),
.B(Sgf_operation_mult_x_1_n2189), .C(Sgf_operation_mult_x_1_n2210),
.D(Sgf_operation_mult_x_1_n2186), .ICI(Sgf_operation_mult_x_1_n2207),
.S(Sgf_operation_mult_x_1_n2180), .ICO(Sgf_operation_mult_x_1_n2178),
.CO(Sgf_operation_mult_x_1_n2179) );
CMPR42X1TS Sgf_operation_mult_x_1_U1712 ( .A(Sgf_operation_mult_x_1_n3730),
.B(Sgf_operation_mult_x_1_n3625), .C(Sgf_operation_mult_x_1_n3835),
.D(Sgf_operation_mult_x_1_n2172), .ICI(Sgf_operation_mult_x_1_n3994),
.S(Sgf_operation_mult_x_1_n2170), .ICO(Sgf_operation_mult_x_1_n2168),
.CO(Sgf_operation_mult_x_1_n2169) );
CMPR42X1TS Sgf_operation_mult_x_1_U1711 ( .A(Sgf_operation_mult_x_1_n3941),
.B(Sgf_operation_mult_x_1_n3678), .C(Sgf_operation_mult_x_1_n2193),
.D(Sgf_operation_mult_x_1_n4365), .ICI(Sgf_operation_mult_x_1_n2190),
.S(Sgf_operation_mult_x_1_n2167), .ICO(Sgf_operation_mult_x_1_n2165),
.CO(Sgf_operation_mult_x_1_n2166) );
CMPR42X1TS Sgf_operation_mult_x_1_U1710 ( .A(Sgf_operation_mult_x_1_n4047),
.B(Sgf_operation_mult_x_1_n4153), .C(Sgf_operation_mult_x_1_n3783),
.D(Sgf_operation_mult_x_1_n3888), .ICI(Sgf_operation_mult_x_1_n2194),
.S(Sgf_operation_mult_x_1_n2164), .ICO(Sgf_operation_mult_x_1_n2162),
.CO(Sgf_operation_mult_x_1_n2163) );
CMPR42X1TS Sgf_operation_mult_x_1_U1709 ( .A(Sgf_operation_mult_x_1_n4259),
.B(Sgf_operation_mult_x_1_n4312), .C(Sgf_operation_mult_x_1_n4100),
.D(Sgf_operation_mult_x_1_n4206), .ICI(Sgf_operation_mult_x_1_n2187),
.S(Sgf_operation_mult_x_1_n2161), .ICO(Sgf_operation_mult_x_1_n2159),
.CO(Sgf_operation_mult_x_1_n2160) );
CMPR42X1TS Sgf_operation_mult_x_1_U1708 ( .A(Sgf_operation_mult_x_1_n2170),
.B(Sgf_operation_mult_x_1_n2184), .C(Sgf_operation_mult_x_1_n2191),
.D(Sgf_operation_mult_x_1_n2167), .ICI(Sgf_operation_mult_x_1_n2164),
.S(Sgf_operation_mult_x_1_n2158), .ICO(Sgf_operation_mult_x_1_n2156),
.CO(Sgf_operation_mult_x_1_n2157) );
CMPR42X1TS Sgf_operation_mult_x_1_U1707 ( .A(Sgf_operation_mult_x_1_n2188),
.B(Sgf_operation_mult_x_1_n2181), .C(Sgf_operation_mult_x_1_n2185),
.D(Sgf_operation_mult_x_1_n2161), .ICI(Sgf_operation_mult_x_1_n2182),
.S(Sgf_operation_mult_x_1_n2155), .ICO(Sgf_operation_mult_x_1_n2153),
.CO(Sgf_operation_mult_x_1_n2154) );
CMPR42X1TS Sgf_operation_mult_x_1_U1702 ( .A(Sgf_operation_mult_x_1_n3782),
.B(Sgf_operation_mult_x_1_n3624), .C(Sgf_operation_mult_x_1_n4311),
.D(Sgf_operation_mult_x_1_n4205), .ICI(Sgf_operation_mult_x_1_n3940),
.S(Sgf_operation_mult_x_1_n2142), .ICO(Sgf_operation_mult_x_1_n2140),
.CO(Sgf_operation_mult_x_1_n2141) );
CMPR42X1TS Sgf_operation_mult_x_1_U1701 ( .A(Sgf_operation_mult_x_1_n4099),
.B(Sgf_operation_mult_x_1_n2168), .C(Sgf_operation_mult_x_1_n2147),
.D(Sgf_operation_mult_x_1_n3834), .ICI(Sgf_operation_mult_x_1_n2169),
.S(Sgf_operation_mult_x_1_n2139), .ICO(Sgf_operation_mult_x_1_n2137),
.CO(Sgf_operation_mult_x_1_n2138) );
CMPR42X1TS Sgf_operation_mult_x_1_U1700 ( .A(Sgf_operation_mult_x_1_n4364),
.B(Sgf_operation_mult_x_1_n4046), .C(Sgf_operation_mult_x_1_n4152),
.D(Sgf_operation_mult_x_1_n2162), .ICI(Sgf_operation_mult_x_1_n2139),
.S(Sgf_operation_mult_x_1_n2136), .ICO(Sgf_operation_mult_x_1_n2134),
.CO(Sgf_operation_mult_x_1_n2135) );
CMPR42X1TS Sgf_operation_mult_x_1_U1699 ( .A(Sgf_operation_mult_x_1_n4258),
.B(Sgf_operation_mult_x_1_n2145), .C(Sgf_operation_mult_x_1_n2159),
.D(Sgf_operation_mult_x_1_n2166), .ICI(Sgf_operation_mult_x_1_n2163),
.S(Sgf_operation_mult_x_1_n2133), .ICO(Sgf_operation_mult_x_1_n2131),
.CO(Sgf_operation_mult_x_1_n2132) );
CMPR42X1TS Sgf_operation_mult_x_1_U1698 ( .A(Sgf_operation_mult_x_1_n2142),
.B(Sgf_operation_mult_x_1_n2156), .C(Sgf_operation_mult_x_1_n2160),
.D(Sgf_operation_mult_x_1_n2136), .ICI(Sgf_operation_mult_x_1_n2153),
.S(Sgf_operation_mult_x_1_n2130), .ICO(Sgf_operation_mult_x_1_n2128),
.CO(Sgf_operation_mult_x_1_n2129) );
CMPR42X1TS Sgf_operation_mult_x_1_U1696 ( .A(Sgf_operation_mult_x_1_n3467),
.B(Sgf_operation_mult_x_1_n3518), .C(Sgf_operation_mult_x_1_n2148),
.D(Sgf_operation_mult_x_1_n3623), .ICI(Sgf_operation_mult_x_1_n3571),
.S(Sgf_operation_mult_x_1_n2124), .ICO(Sgf_operation_mult_x_1_n2122),
.CO(Sgf_operation_mult_x_1_n2123) );
CMPR42X1TS Sgf_operation_mult_x_1_U1692 ( .A(Sgf_operation_mult_x_1_n2143),
.B(Sgf_operation_mult_x_1_n2140), .C(Sgf_operation_mult_x_1_n2137),
.D(Sgf_operation_mult_x_1_n4310), .ICI(Sgf_operation_mult_x_1_n2144),
.S(Sgf_operation_mult_x_1_n2112), .ICO(Sgf_operation_mult_x_1_n2110),
.CO(Sgf_operation_mult_x_1_n2111) );
CMPR42X1TS Sgf_operation_mult_x_1_U1690 ( .A(Sgf_operation_mult_x_1_n2115),
.B(Sgf_operation_mult_x_1_n2118), .C(Sgf_operation_mult_x_1_n2131),
.D(Sgf_operation_mult_x_1_n2112), .ICI(Sgf_operation_mult_x_1_n2132),
.S(Sgf_operation_mult_x_1_n2106), .ICO(Sgf_operation_mult_x_1_n2104),
.CO(Sgf_operation_mult_x_1_n2105) );
CMPR42X1TS Sgf_operation_mult_x_1_U1689 ( .A(Sgf_operation_mult_x_1_n2128),
.B(Sgf_operation_mult_x_1_n2109), .C(Sgf_operation_mult_x_1_n2129),
.D(Sgf_operation_mult_x_1_n2106), .ICI(Sgf_operation_mult_x_1_n2125),
.S(Sgf_operation_mult_x_1_n2103), .ICO(Sgf_operation_mult_x_1_n2101),
.CO(Sgf_operation_mult_x_1_n2102) );
CMPR42X1TS Sgf_operation_mult_x_1_U1688 ( .A(Sgf_operation_mult_x_1_n3466),
.B(Sgf_operation_mult_x_1_n3517), .C(Sgf_operation_mult_x_1_n2122),
.D(Sgf_operation_mult_x_1_n3675), .ICI(Sgf_operation_mult_x_1_n3570),
.S(Sgf_operation_mult_x_1_n2100), .ICO(Sgf_operation_mult_x_1_n2098),
.CO(Sgf_operation_mult_x_1_n2099) );
CMPR42X1TS Sgf_operation_mult_x_1_U1685 ( .A(Sgf_operation_mult_x_1_n4203),
.B(Sgf_operation_mult_x_1_n2119), .C(Sgf_operation_mult_x_1_n2123),
.D(Sgf_operation_mult_x_1_n4044), .ICI(Sgf_operation_mult_x_1_n2113),
.S(Sgf_operation_mult_x_1_n2091), .ICO(Sgf_operation_mult_x_1_n2089),
.CO(Sgf_operation_mult_x_1_n2090) );
CMPR42X1TS Sgf_operation_mult_x_1_U1684 ( .A(Sgf_operation_mult_x_1_n4256),
.B(Sgf_operation_mult_x_1_n4362), .C(Sgf_operation_mult_x_1_n4150),
.D(Sgf_operation_mult_x_1_n2100), .ICI(Sgf_operation_mult_x_1_n2094),
.S(Sgf_operation_mult_x_1_n2088), .ICO(Sgf_operation_mult_x_1_n2086),
.CO(Sgf_operation_mult_x_1_n2087) );
CMPR42X1TS Sgf_operation_mult_x_1_U1683 ( .A(Sgf_operation_mult_x_1_n2120),
.B(Sgf_operation_mult_x_1_n2110), .C(Sgf_operation_mult_x_1_n2097),
.D(Sgf_operation_mult_x_1_n2114), .ICI(Sgf_operation_mult_x_1_n2091),
.S(Sgf_operation_mult_x_1_n2085), .ICO(Sgf_operation_mult_x_1_n2083),
.CO(Sgf_operation_mult_x_1_n2084) );
CMPR42X1TS Sgf_operation_mult_x_1_U1682 ( .A(Sgf_operation_mult_x_1_n2117),
.B(Sgf_operation_mult_x_1_n2107), .C(Sgf_operation_mult_x_1_n2111),
.D(Sgf_operation_mult_x_1_n2104), .ICI(Sgf_operation_mult_x_1_n2088),
.S(Sgf_operation_mult_x_1_n2082), .ICO(Sgf_operation_mult_x_1_n2080),
.CO(Sgf_operation_mult_x_1_n2081) );
CMPR42X1TS Sgf_operation_mult_x_1_U1681 ( .A(Sgf_operation_mult_x_1_n2108),
.B(Sgf_operation_mult_x_1_n2085), .C(Sgf_operation_mult_x_1_n2105),
.D(Sgf_operation_mult_x_1_n2082), .ICI(Sgf_operation_mult_x_1_n2101),
.S(Sgf_operation_mult_x_1_n2079), .ICO(Sgf_operation_mult_x_1_n2077),
.CO(Sgf_operation_mult_x_1_n2078) );
CMPR42X1TS Sgf_operation_mult_x_1_U1678 ( .A(Sgf_operation_mult_x_1_n3621),
.B(Sgf_operation_mult_x_1_n4043), .C(Sgf_operation_mult_x_1_n4255),
.D(Sgf_operation_mult_x_1_n4149), .ICI(Sgf_operation_mult_x_1_n2095),
.S(Sgf_operation_mult_x_1_n2070), .ICO(Sgf_operation_mult_x_1_n2068),
.CO(Sgf_operation_mult_x_1_n2069) );
CMPR42X1TS Sgf_operation_mult_x_1_U1677 ( .A(Sgf_operation_mult_x_1_n3779),
.B(Sgf_operation_mult_x_1_n3884), .C(Sgf_operation_mult_x_1_n3990),
.D(Sgf_operation_mult_x_1_n4202), .ICI(Sgf_operation_mult_x_1_n2073),
.S(Sgf_operation_mult_x_1_n2067), .ICO(Sgf_operation_mult_x_1_n2065),
.CO(Sgf_operation_mult_x_1_n2066) );
CMPR42X1TS Sgf_operation_mult_x_1_U1676 ( .A(Sgf_operation_mult_x_1_n4308),
.B(Sgf_operation_mult_x_1_n2089), .C(Sgf_operation_mult_x_1_n2092),
.D(Sgf_operation_mult_x_1_n2076), .ICI(Sgf_operation_mult_x_1_n2090),
.S(Sgf_operation_mult_x_1_n2064), .ICO(Sgf_operation_mult_x_1_n2062),
.CO(Sgf_operation_mult_x_1_n2063) );
CMPR42X1TS Sgf_operation_mult_x_1_U1673 ( .A(Sgf_operation_mult_x_1_n2080),
.B(Sgf_operation_mult_x_1_n2084), .C(Sgf_operation_mult_x_1_n2081),
.D(Sgf_operation_mult_x_1_n2058), .ICI(Sgf_operation_mult_x_1_n2077),
.S(Sgf_operation_mult_x_1_n2055), .ICO(Sgf_operation_mult_x_1_n2053),
.CO(Sgf_operation_mult_x_1_n2054) );
CMPR42X1TS Sgf_operation_mult_x_1_U1671 ( .A(Sgf_operation_mult_x_1_n3883),
.B(Sgf_operation_mult_x_1_n4360), .C(Sgf_operation_mult_x_1_n3989),
.D(Sgf_operation_mult_x_1_n4307), .ICI(Sgf_operation_mult_x_1_n2068),
.S(Sgf_operation_mult_x_1_n2049), .ICO(Sgf_operation_mult_x_1_n2047),
.CO(Sgf_operation_mult_x_1_n2048) );
CMPR42X1TS Sgf_operation_mult_x_1_U1670 ( .A(Sgf_operation_mult_x_1_n4095),
.B(Sgf_operation_mult_x_1_n2074), .C(Sgf_operation_mult_x_1_n3936),
.D(Sgf_operation_mult_x_1_n3620), .ICI(Sgf_operation_mult_x_1_n2052),
.S(Sgf_operation_mult_x_1_n2046), .ICO(Sgf_operation_mult_x_1_n2044),
.CO(Sgf_operation_mult_x_1_n2045) );
CMPR42X1TS Sgf_operation_mult_x_1_U1669 ( .A(Sgf_operation_mult_x_1_n4201),
.B(Sgf_operation_mult_x_1_n3725), .C(Sgf_operation_mult_x_1_n3830),
.D(Sgf_operation_mult_x_1_n2071), .ICI(Sgf_operation_mult_x_1_n2075),
.S(Sgf_operation_mult_x_1_n2043), .ICO(Sgf_operation_mult_x_1_n2041),
.CO(Sgf_operation_mult_x_1_n2042) );
CMPR42X1TS Sgf_operation_mult_x_1_U1668 ( .A(Sgf_operation_mult_x_1_n4254),
.B(Sgf_operation_mult_x_1_n4042), .C(Sgf_operation_mult_x_1_n4148),
.D(Sgf_operation_mult_x_1_n2072), .ICI(Sgf_operation_mult_x_1_n2046),
.S(Sgf_operation_mult_x_1_n2040), .ICO(Sgf_operation_mult_x_1_n2038),
.CO(Sgf_operation_mult_x_1_n2039) );
CMPR42X1TS Sgf_operation_mult_x_1_U1667 ( .A(Sgf_operation_mult_x_1_n2065),
.B(Sgf_operation_mult_x_1_n2062), .C(Sgf_operation_mult_x_1_n2069),
.D(Sgf_operation_mult_x_1_n2049), .ICI(Sgf_operation_mult_x_1_n2063),
.S(Sgf_operation_mult_x_1_n2037), .ICO(Sgf_operation_mult_x_1_n2035),
.CO(Sgf_operation_mult_x_1_n2036) );
CMPR42X1TS Sgf_operation_mult_x_1_U1666 ( .A(Sgf_operation_mult_x_1_n2059),
.B(Sgf_operation_mult_x_1_n2043), .C(Sgf_operation_mult_x_1_n2066),
.D(Sgf_operation_mult_x_1_n2040), .ICI(Sgf_operation_mult_x_1_n2056),
.S(Sgf_operation_mult_x_1_n2034), .ICO(Sgf_operation_mult_x_1_n2032),
.CO(Sgf_operation_mult_x_1_n2033) );
CMPR42X1TS Sgf_operation_mult_x_1_U1665 ( .A(Sgf_operation_mult_x_1_n2060),
.B(Sgf_operation_mult_x_1_n2037), .C(Sgf_operation_mult_x_1_n2057),
.D(Sgf_operation_mult_x_1_n2034), .ICI(Sgf_operation_mult_x_1_n2053),
.S(Sgf_operation_mult_x_1_n2031), .ICO(Sgf_operation_mult_x_1_n2029),
.CO(Sgf_operation_mult_x_1_n2030) );
CMPR42X1TS Sgf_operation_mult_x_1_U1664 ( .A(n5152), .B(
Sgf_operation_mult_x_1_n3463), .C(Sgf_operation_mult_x_1_n3619), .D(
Sgf_operation_mult_x_1_n3514), .ICI(Sgf_operation_mult_x_1_n3829), .S(
Sgf_operation_mult_x_1_n2028), .ICO(Sgf_operation_mult_x_1_n2026),
.CO(Sgf_operation_mult_x_1_n2027) );
CMPR42X1TS Sgf_operation_mult_x_1_U1663 ( .A(Sgf_operation_mult_x_1_n3724),
.B(Sgf_operation_mult_x_1_n3567), .C(Sgf_operation_mult_x_1_n2050),
.D(Sgf_operation_mult_x_1_n4253), .ICI(Sgf_operation_mult_x_1_n2047),
.S(Sgf_operation_mult_x_1_n2025), .ICO(Sgf_operation_mult_x_1_n2023),
.CO(Sgf_operation_mult_x_1_n2024) );
CMPR42X1TS Sgf_operation_mult_x_1_U1660 ( .A(Sgf_operation_mult_x_1_n4200),
.B(Sgf_operation_mult_x_1_n4094), .C(Sgf_operation_mult_x_1_n3988),
.D(Sgf_operation_mult_x_1_n2044), .ICI(Sgf_operation_mult_x_1_n2042),
.S(Sgf_operation_mult_x_1_n2016), .ICO(Sgf_operation_mult_x_1_n2014),
.CO(Sgf_operation_mult_x_1_n2015) );
CMPR42X1TS Sgf_operation_mult_x_1_U1659 ( .A(Sgf_operation_mult_x_1_n2038),
.B(Sgf_operation_mult_x_1_n2048), .C(Sgf_operation_mult_x_1_n2025),
.D(Sgf_operation_mult_x_1_n2045), .ICI(Sgf_operation_mult_x_1_n2039),
.S(Sgf_operation_mult_x_1_n2013), .ICO(Sgf_operation_mult_x_1_n2011),
.CO(Sgf_operation_mult_x_1_n2012) );
CMPR42X1TS Sgf_operation_mult_x_1_U1658 ( .A(Sgf_operation_mult_x_1_n2022),
.B(Sgf_operation_mult_x_1_n2035), .C(Sgf_operation_mult_x_1_n2019),
.D(Sgf_operation_mult_x_1_n2016), .ICI(Sgf_operation_mult_x_1_n2032),
.S(Sgf_operation_mult_x_1_n2010), .ICO(Sgf_operation_mult_x_1_n2008),
.CO(Sgf_operation_mult_x_1_n2009) );
CMPR42X1TS Sgf_operation_mult_x_1_U1657 ( .A(Sgf_operation_mult_x_1_n2036),
.B(Sgf_operation_mult_x_1_n2013), .C(Sgf_operation_mult_x_1_n2033),
.D(Sgf_operation_mult_x_1_n2010), .ICI(Sgf_operation_mult_x_1_n2029),
.S(Sgf_operation_mult_x_1_n2007), .ICO(Sgf_operation_mult_x_1_n2005),
.CO(Sgf_operation_mult_x_1_n2006) );
CMPR42X1TS Sgf_operation_mult_x_1_U1655 ( .A(Sgf_operation_mult_x_1_n3881),
.B(Sgf_operation_mult_x_1_n3513), .C(Sgf_operation_mult_x_1_n4305),
.D(Sgf_operation_mult_x_1_n2026), .ICI(Sgf_operation_mult_x_1_n2027),
.S(Sgf_operation_mult_x_1_n2001), .ICO(Sgf_operation_mult_x_1_n1999),
.CO(Sgf_operation_mult_x_1_n2000) );
CMPR42X1TS Sgf_operation_mult_x_1_U1654 ( .A(Sgf_operation_mult_x_1_n3566),
.B(Sgf_operation_mult_x_1_n4199), .C(Sgf_operation_mult_x_1_n4093),
.D(Sgf_operation_mult_x_1_n3987), .ICI(Sgf_operation_mult_x_1_n2023),
.S(Sgf_operation_mult_x_1_n1998), .ICO(Sgf_operation_mult_x_1_n1996),
.CO(Sgf_operation_mult_x_1_n1997) );
CMPR42X1TS Sgf_operation_mult_x_1_U1653 ( .A(Sgf_operation_mult_x_1_n3723),
.B(Sgf_operation_mult_x_1_n3828), .C(Sgf_operation_mult_x_1_n3934),
.D(Sgf_operation_mult_x_1_n4040), .ICI(Sgf_operation_mult_x_1_n2001),
.S(Sgf_operation_mult_x_1_n1995), .ICO(Sgf_operation_mult_x_1_n1993),
.CO(Sgf_operation_mult_x_1_n1994) );
CMPR42X1TS Sgf_operation_mult_x_1_U1651 ( .A(Sgf_operation_mult_x_1_n2017),
.B(Sgf_operation_mult_x_1_n2014), .C(Sgf_operation_mult_x_1_n2024),
.D(Sgf_operation_mult_x_1_n2021), .ICI(Sgf_operation_mult_x_1_n2015),
.S(Sgf_operation_mult_x_1_n1989), .ICO(Sgf_operation_mult_x_1_n1987),
.CO(Sgf_operation_mult_x_1_n1988) );
CMPR42X1TS Sgf_operation_mult_x_1_U1650 ( .A(Sgf_operation_mult_x_1_n2018),
.B(Sgf_operation_mult_x_1_n2011), .C(Sgf_operation_mult_x_1_n1995),
.D(Sgf_operation_mult_x_1_n1992), .ICI(Sgf_operation_mult_x_1_n1989),
.S(Sgf_operation_mult_x_1_n1986), .ICO(Sgf_operation_mult_x_1_n1984),
.CO(Sgf_operation_mult_x_1_n1985) );
CMPR42X1TS Sgf_operation_mult_x_1_U1649 ( .A(Sgf_operation_mult_x_1_n2008),
.B(Sgf_operation_mult_x_1_n2012), .C(Sgf_operation_mult_x_1_n2009),
.D(Sgf_operation_mult_x_1_n1986), .ICI(Sgf_operation_mult_x_1_n2005),
.S(Sgf_operation_mult_x_1_n1983), .ICO(Sgf_operation_mult_x_1_n1981),
.CO(Sgf_operation_mult_x_1_n1982) );
CMPR42X1TS Sgf_operation_mult_x_1_U1647 ( .A(Sgf_operation_mult_x_1_n3617),
.B(Sgf_operation_mult_x_1_n4304), .C(Sgf_operation_mult_x_1_n3933),
.D(Sgf_operation_mult_x_1_n4251), .ICI(Sgf_operation_mult_x_1_n1996),
.S(Sgf_operation_mult_x_1_n1977), .ICO(Sgf_operation_mult_x_1_n1975),
.CO(Sgf_operation_mult_x_1_n1976) );
CMPR42X1TS Sgf_operation_mult_x_1_U1646 ( .A(Sgf_operation_mult_x_1_n4039),
.B(Sgf_operation_mult_x_1_n2002), .C(Sgf_operation_mult_x_1_n3880),
.D(Sgf_operation_mult_x_1_n1999), .ICI(Sgf_operation_mult_x_1_n1980),
.S(Sgf_operation_mult_x_1_n1974), .ICO(Sgf_operation_mult_x_1_n1972),
.CO(Sgf_operation_mult_x_1_n1973) );
CMPR42X1TS Sgf_operation_mult_x_1_U1643 ( .A(Sgf_operation_mult_x_1_n1993),
.B(Sgf_operation_mult_x_1_n1990), .C(Sgf_operation_mult_x_1_n1997),
.D(Sgf_operation_mult_x_1_n1977), .ICI(Sgf_operation_mult_x_1_n1991),
.S(Sgf_operation_mult_x_1_n1965), .ICO(Sgf_operation_mult_x_1_n1963),
.CO(Sgf_operation_mult_x_1_n1964) );
CMPR42X1TS Sgf_operation_mult_x_1_U1642 ( .A(Sgf_operation_mult_x_1_n1971),
.B(Sgf_operation_mult_x_1_n1987), .C(Sgf_operation_mult_x_1_n1994),
.D(Sgf_operation_mult_x_1_n1968), .ICI(Sgf_operation_mult_x_1_n1988),
.S(Sgf_operation_mult_x_1_n1962), .ICO(Sgf_operation_mult_x_1_n1960),
.CO(Sgf_operation_mult_x_1_n1961) );
CMPR42X1TS Sgf_operation_mult_x_1_U1640 ( .A(n5078), .B(n5151), .C(
Sgf_operation_mult_x_1_n3460), .D(Sgf_operation_mult_x_1_n3564), .ICI(
Sgf_operation_mult_x_1_n3774), .S(Sgf_operation_mult_x_1_n1956), .ICO(
Sgf_operation_mult_x_1_n1954), .CO(Sgf_operation_mult_x_1_n1955) );
CMPR42X1TS Sgf_operation_mult_x_1_U1637 ( .A(Sgf_operation_mult_x_1_n4091),
.B(Sgf_operation_mult_x_1_n3826), .C(Sgf_operation_mult_x_1_n1975),
.D(Sgf_operation_mult_x_1_n4250), .ICI(Sgf_operation_mult_x_1_n1972),
.S(Sgf_operation_mult_x_1_n1947), .ICO(Sgf_operation_mult_x_1_n1945),
.CO(Sgf_operation_mult_x_1_n1946) );
CMPR42X1TS Sgf_operation_mult_x_1_U1634 ( .A(Sgf_operation_mult_x_1_n1950),
.B(Sgf_operation_mult_x_1_n1963), .C(Sgf_operation_mult_x_1_n1947),
.D(Sgf_operation_mult_x_1_n1944), .ICI(Sgf_operation_mult_x_1_n1960),
.S(Sgf_operation_mult_x_1_n1938), .ICO(Sgf_operation_mult_x_1_n1936),
.CO(Sgf_operation_mult_x_1_n1937) );
CMPR42X1TS Sgf_operation_mult_x_1_U1630 ( .A(Sgf_operation_mult_x_1_n3720),
.B(Sgf_operation_mult_x_1_n3825), .C(Sgf_operation_mult_x_1_n3510),
.D(Sgf_operation_mult_x_1_n4249), .ICI(Sgf_operation_mult_x_1_n1955),
.S(Sgf_operation_mult_x_1_n1928), .ICO(Sgf_operation_mult_x_1_n1926),
.CO(Sgf_operation_mult_x_1_n1927) );
CMPR42X1TS Sgf_operation_mult_x_1_U1629 ( .A(Sgf_operation_mult_x_1_n3615),
.B(Sgf_operation_mult_x_1_n3931), .C(Sgf_operation_mult_x_1_n4143),
.D(Sgf_operation_mult_x_1_n4037), .ICI(Sgf_operation_mult_x_1_n1951),
.S(Sgf_operation_mult_x_1_n1925), .ICO(Sgf_operation_mult_x_1_n1923),
.CO(Sgf_operation_mult_x_1_n1924) );
CMPR42X1TS Sgf_operation_mult_x_1_U1628 ( .A(Sgf_operation_mult_x_1_n1930),
.B(Sgf_operation_mult_x_1_n3668), .C(Sgf_operation_mult_x_1_n3773),
.D(Sgf_operation_mult_x_1_n3984), .ICI(Sgf_operation_mult_x_1_n1952),
.S(Sgf_operation_mult_x_1_n1922), .ICO(Sgf_operation_mult_x_1_n1920),
.CO(Sgf_operation_mult_x_1_n1921) );
CMPR42X1TS Sgf_operation_mult_x_1_U1626 ( .A(Sgf_operation_mult_x_1_n1945),
.B(Sgf_operation_mult_x_1_n1928), .C(Sgf_operation_mult_x_1_n1942),
.D(Sgf_operation_mult_x_1_n1949), .ICI(Sgf_operation_mult_x_1_n1922),
.S(Sgf_operation_mult_x_1_n1916), .ICO(Sgf_operation_mult_x_1_n1914),
.CO(Sgf_operation_mult_x_1_n1915) );
CMPR42X1TS Sgf_operation_mult_x_1_U1621 ( .A(Sgf_operation_mult_x_1_n3772),
.B(Sgf_operation_mult_x_1_n3667), .C(Sgf_operation_mult_x_1_n4248),
.D(Sgf_operation_mult_x_1_n1929), .ICI(Sgf_operation_mult_x_1_n1923),
.S(Sgf_operation_mult_x_1_n1903), .ICO(Sgf_operation_mult_x_1_n1901),
.CO(Sgf_operation_mult_x_1_n1902) );
CMPR42X1TS Sgf_operation_mult_x_1_U1620 ( .A(Sgf_operation_mult_x_1_n3877),
.B(Sgf_operation_mult_x_1_n4195), .C(Sgf_operation_mult_x_1_n3824),
.D(Sgf_operation_mult_x_1_n3509), .ICI(Sgf_operation_mult_x_1_n1920),
.S(Sgf_operation_mult_x_1_n1900), .ICO(Sgf_operation_mult_x_1_n1898),
.CO(Sgf_operation_mult_x_1_n1899) );
CMPR42X1TS Sgf_operation_mult_x_1_U1618 ( .A(Sgf_operation_mult_x_1_n1905),
.B(Sgf_operation_mult_x_1_n1926), .C(Sgf_operation_mult_x_1_n4036),
.D(Sgf_operation_mult_x_1_n3930), .ICI(Sgf_operation_mult_x_1_n1927),
.S(Sgf_operation_mult_x_1_n1894), .ICO(Sgf_operation_mult_x_1_n1892),
.CO(Sgf_operation_mult_x_1_n1893) );
CMPR42X1TS Sgf_operation_mult_x_1_U1617 ( .A(Sgf_operation_mult_x_1_n1917),
.B(Sgf_operation_mult_x_1_n1903), .C(Sgf_operation_mult_x_1_n1924),
.D(Sgf_operation_mult_x_1_n1897), .ICI(Sgf_operation_mult_x_1_n1918),
.S(Sgf_operation_mult_x_1_n1891), .ICO(Sgf_operation_mult_x_1_n1889),
.CO(Sgf_operation_mult_x_1_n1890) );
CMPR42X1TS Sgf_operation_mult_x_1_U1615 ( .A(Sgf_operation_mult_x_1_n1911),
.B(Sgf_operation_mult_x_1_n1891), .C(Sgf_operation_mult_x_1_n1888),
.D(Sgf_operation_mult_x_1_n1912), .ICI(Sgf_operation_mult_x_1_n1908),
.S(Sgf_operation_mult_x_1_n1885), .ICO(Sgf_operation_mult_x_1_n1883),
.CO(Sgf_operation_mult_x_1_n1884) );
CMPR42X1TS Sgf_operation_mult_x_1_U1613 ( .A(Sgf_operation_mult_x_1_n3508),
.B(Sgf_operation_mult_x_1_n3613), .C(Sgf_operation_mult_x_1_n3718),
.D(Sgf_operation_mult_x_1_n1882), .ICI(Sgf_operation_mult_x_1_n1901),
.S(Sgf_operation_mult_x_1_n1880), .ICO(Sgf_operation_mult_x_1_n1878),
.CO(Sgf_operation_mult_x_1_n1879) );
CMPR42X1TS Sgf_operation_mult_x_1_U1612 ( .A(Sgf_operation_mult_x_1_n1904),
.B(Sgf_operation_mult_x_1_n4035), .C(Sgf_operation_mult_x_1_n3561),
.D(Sgf_operation_mult_x_1_n3666), .ICI(Sgf_operation_mult_x_1_n1898),
.S(Sgf_operation_mult_x_1_n1877), .ICO(Sgf_operation_mult_x_1_n1875),
.CO(Sgf_operation_mult_x_1_n1876) );
CMPR42X1TS Sgf_operation_mult_x_1_U1610 ( .A(Sgf_operation_mult_x_1_n4194),
.B(Sgf_operation_mult_x_1_n3876), .C(Sgf_operation_mult_x_1_n3982),
.D(Sgf_operation_mult_x_1_n4088), .ICI(Sgf_operation_mult_x_1_n1874),
.S(Sgf_operation_mult_x_1_n1871), .ICO(Sgf_operation_mult_x_1_n1869),
.CO(Sgf_operation_mult_x_1_n1870) );
CMPR42X1TS Sgf_operation_mult_x_1_U1609 ( .A(Sgf_operation_mult_x_1_n1902),
.B(Sgf_operation_mult_x_1_n1892), .C(Sgf_operation_mult_x_1_n1880),
.D(Sgf_operation_mult_x_1_n1896), .ICI(Sgf_operation_mult_x_1_n1889),
.S(Sgf_operation_mult_x_1_n1868), .ICO(Sgf_operation_mult_x_1_n1866),
.CO(Sgf_operation_mult_x_1_n1867) );
CMPR42X1TS Sgf_operation_mult_x_1_U1608 ( .A(Sgf_operation_mult_x_1_n1899),
.B(Sgf_operation_mult_x_1_n1877), .C(Sgf_operation_mult_x_1_n1893),
.D(Sgf_operation_mult_x_1_n1886), .ICI(Sgf_operation_mult_x_1_n1871),
.S(Sgf_operation_mult_x_1_n1865), .ICO(Sgf_operation_mult_x_1_n1863),
.CO(Sgf_operation_mult_x_1_n1864) );
CMPR42X1TS Sgf_operation_mult_x_1_U1607 ( .A(Sgf_operation_mult_x_1_n1890),
.B(Sgf_operation_mult_x_1_n1868), .C(Sgf_operation_mult_x_1_n1887),
.D(Sgf_operation_mult_x_1_n1865), .ICI(Sgf_operation_mult_x_1_n1883),
.S(Sgf_operation_mult_x_1_n1862), .ICO(Sgf_operation_mult_x_1_n1860),
.CO(Sgf_operation_mult_x_1_n1861) );
CMPR42X1TS Sgf_operation_mult_x_1_U1604 ( .A(Sgf_operation_mult_x_1_n3770),
.B(Sgf_operation_mult_x_1_n1881), .C(Sgf_operation_mult_x_1_n4193),
.D(Sgf_operation_mult_x_1_n4087), .ICI(Sgf_operation_mult_x_1_n1872),
.S(Sgf_operation_mult_x_1_n1855), .ICO(Sgf_operation_mult_x_1_n1853),
.CO(Sgf_operation_mult_x_1_n1854) );
CMPR42X1TS Sgf_operation_mult_x_1_U1603 ( .A(Sgf_operation_mult_x_1_n3981),
.B(Sgf_operation_mult_x_1_n3875), .C(Sgf_operation_mult_x_1_n1878),
.D(Sgf_operation_mult_x_1_n3612), .ICI(Sgf_operation_mult_x_1_n1879),
.S(Sgf_operation_mult_x_1_n1852), .ICO(Sgf_operation_mult_x_1_n1850),
.CO(Sgf_operation_mult_x_1_n1851) );
CMPR42X1TS Sgf_operation_mult_x_1_U1602 ( .A(Sgf_operation_mult_x_1_n4140),
.B(Sgf_operation_mult_x_1_n3822), .C(Sgf_operation_mult_x_1_n3928),
.D(Sgf_operation_mult_x_1_n1875), .ICI(Sgf_operation_mult_x_1_n1852),
.S(Sgf_operation_mult_x_1_n1849), .ICO(Sgf_operation_mult_x_1_n1847),
.CO(Sgf_operation_mult_x_1_n1848) );
CMPR42X1TS Sgf_operation_mult_x_1_U1599 ( .A(Sgf_operation_mult_x_1_n1846),
.B(Sgf_operation_mult_x_1_n1867), .C(Sgf_operation_mult_x_1_n1864),
.D(Sgf_operation_mult_x_1_n1843), .ICI(Sgf_operation_mult_x_1_n1860),
.S(Sgf_operation_mult_x_1_n1840), .ICO(Sgf_operation_mult_x_1_n1838),
.CO(Sgf_operation_mult_x_1_n1839) );
CMPR42X1TS Sgf_operation_mult_x_1_U1597 ( .A(Sgf_operation_mult_x_1_n1859),
.B(Sgf_operation_mult_x_1_n3611), .C(Sgf_operation_mult_x_1_n3716),
.D(Sgf_operation_mult_x_1_n3506), .ICI(Sgf_operation_mult_x_1_n3769),
.S(Sgf_operation_mult_x_1_n1835), .ICO(Sgf_operation_mult_x_1_n1833),
.CO(Sgf_operation_mult_x_1_n1834) );
CMPR42X1TS Sgf_operation_mult_x_1_U1596 ( .A(Sgf_operation_mult_x_1_n3458),
.B(Sgf_operation_mult_x_1_n4192), .C(Sgf_operation_mult_x_1_n4033),
.D(Sgf_operation_mult_x_1_n3821), .ICI(Sgf_operation_mult_x_1_n3874),
.S(Sgf_operation_mult_x_1_n1832), .ICO(Sgf_operation_mult_x_1_n1830),
.CO(Sgf_operation_mult_x_1_n1831) );
CMPR42X1TS Sgf_operation_mult_x_1_U1594 ( .A(Sgf_operation_mult_x_1_n1856),
.B(Sgf_operation_mult_x_1_n3664), .C(Sgf_operation_mult_x_1_n1850),
.D(Sgf_operation_mult_x_1_n4086), .ICI(Sgf_operation_mult_x_1_n1835),
.S(Sgf_operation_mult_x_1_n1826), .ICO(Sgf_operation_mult_x_1_n1824),
.CO(Sgf_operation_mult_x_1_n1825) );
CMPR42X1TS Sgf_operation_mult_x_1_U1593 ( .A(Sgf_operation_mult_x_1_n3980),
.B(Sgf_operation_mult_x_1_n1854), .C(Sgf_operation_mult_x_1_n1847),
.D(Sgf_operation_mult_x_1_n1832), .ICI(Sgf_operation_mult_x_1_n1829),
.S(Sgf_operation_mult_x_1_n1823), .ICO(Sgf_operation_mult_x_1_n1821),
.CO(Sgf_operation_mult_x_1_n1822) );
CMPR42X1TS Sgf_operation_mult_x_1_U1590 ( .A(n5080), .B(
Sgf_operation_mult_x_1_n3457), .C(Sgf_operation_mult_x_1_n1836), .D(
Sgf_operation_mult_x_1_n3663), .ICI(Sgf_operation_mult_x_1_n3558), .S(
Sgf_operation_mult_x_1_n1814), .ICO(Sgf_operation_mult_x_1_n1812),
.CO(Sgf_operation_mult_x_1_n1813) );
CMPR42X1TS Sgf_operation_mult_x_1_U1587 ( .A(Sgf_operation_mult_x_1_n1830),
.B(Sgf_operation_mult_x_1_n4138), .C(Sgf_operation_mult_x_1_n3820),
.D(Sgf_operation_mult_x_1_n1827), .ICI(Sgf_operation_mult_x_1_n1828),
.S(Sgf_operation_mult_x_1_n1805), .ICO(Sgf_operation_mult_x_1_n1803),
.CO(Sgf_operation_mult_x_1_n1804) );
CMPR42X1TS Sgf_operation_mult_x_1_U1586 ( .A(Sgf_operation_mult_x_1_n4032),
.B(Sgf_operation_mult_x_1_n3926), .C(Sgf_operation_mult_x_1_n1824),
.D(Sgf_operation_mult_x_1_n1831), .ICI(Sgf_operation_mult_x_1_n1811),
.S(Sgf_operation_mult_x_1_n1802), .ICO(Sgf_operation_mult_x_1_n1800),
.CO(Sgf_operation_mult_x_1_n1801) );
CMPR42X1TS Sgf_operation_mult_x_1_U1584 ( .A(Sgf_operation_mult_x_1_n1818),
.B(Sgf_operation_mult_x_1_n1822), .C(Sgf_operation_mult_x_1_n1819),
.D(Sgf_operation_mult_x_1_n1799), .ICI(Sgf_operation_mult_x_1_n1815),
.S(Sgf_operation_mult_x_1_n1796), .ICO(Sgf_operation_mult_x_1_n1794),
.CO(Sgf_operation_mult_x_1_n1795) );
CMPR42X1TS Sgf_operation_mult_x_1_U1581 ( .A(Sgf_operation_mult_x_1_n3609),
.B(Sgf_operation_mult_x_1_n3714), .C(Sgf_operation_mult_x_1_n4137),
.D(Sgf_operation_mult_x_1_n3925), .ICI(Sgf_operation_mult_x_1_n1813),
.S(Sgf_operation_mult_x_1_n1790), .ICO(Sgf_operation_mult_x_1_n1788),
.CO(Sgf_operation_mult_x_1_n1789) );
CMPR42X1TS Sgf_operation_mult_x_1_U1578 ( .A(Sgf_operation_mult_x_1_n4084),
.B(Sgf_operation_mult_x_1_n3767), .C(Sgf_operation_mult_x_1_n1790),
.D(Sgf_operation_mult_x_1_n1810), .ICI(Sgf_operation_mult_x_1_n1787),
.S(Sgf_operation_mult_x_1_n1781), .ICO(Sgf_operation_mult_x_1_n1779),
.CO(Sgf_operation_mult_x_1_n1780) );
CMPR42X1TS Sgf_operation_mult_x_1_U1577 ( .A(Sgf_operation_mult_x_1_n1807),
.B(Sgf_operation_mult_x_1_n1800), .C(Sgf_operation_mult_x_1_n1804),
.D(Sgf_operation_mult_x_1_n1784), .ICI(Sgf_operation_mult_x_1_n1797),
.S(Sgf_operation_mult_x_1_n1778), .ICO(Sgf_operation_mult_x_1_n1776),
.CO(Sgf_operation_mult_x_1_n1777) );
CMPR42X1TS Sgf_operation_mult_x_1_U1573 ( .A(Sgf_operation_mult_x_1_n3661),
.B(Sgf_operation_mult_x_1_n4136), .C(Sgf_operation_mult_x_1_n3871),
.D(Sgf_operation_mult_x_1_n4083), .ICI(Sgf_operation_mult_x_1_n1788),
.S(Sgf_operation_mult_x_1_n1768), .ICO(Sgf_operation_mult_x_1_n1766),
.CO(Sgf_operation_mult_x_1_n1767) );
CMPR42X1TS Sgf_operation_mult_x_1_U1570 ( .A(Sgf_operation_mult_x_1_n3924),
.B(Sgf_operation_mult_x_1_n3818), .C(Sgf_operation_mult_x_1_n1782),
.D(Sgf_operation_mult_x_1_n1768), .ICI(Sgf_operation_mult_x_1_n1765),
.S(Sgf_operation_mult_x_1_n1759), .ICO(Sgf_operation_mult_x_1_n1757),
.CO(Sgf_operation_mult_x_1_n1758) );
CMPR42X1TS Sgf_operation_mult_x_1_U1568 ( .A(Sgf_operation_mult_x_1_n1776),
.B(Sgf_operation_mult_x_1_n1759), .C(Sgf_operation_mult_x_1_n1777),
.D(Sgf_operation_mult_x_1_n1756), .ICI(Sgf_operation_mult_x_1_n1773),
.S(Sgf_operation_mult_x_1_n1753), .ICO(Sgf_operation_mult_x_1_n1751),
.CO(Sgf_operation_mult_x_1_n1752) );
CMPR42X1TS Sgf_operation_mult_x_1_U1566 ( .A(Sgf_operation_mult_x_1_n3502),
.B(Sgf_operation_mult_x_1_n3455), .C(Sgf_operation_mult_x_1_n1769),
.D(Sgf_operation_mult_x_1_n3923), .ICI(Sgf_operation_mult_x_1_n1766),
.S(Sgf_operation_mult_x_1_n1748), .ICO(Sgf_operation_mult_x_1_n1746),
.CO(Sgf_operation_mult_x_1_n1747) );
CMPR42X1TS Sgf_operation_mult_x_1_U1564 ( .A(Sgf_operation_mult_x_1_n4029),
.B(Sgf_operation_mult_x_1_n1750), .C(Sgf_operation_mult_x_1_n3870),
.D(Sgf_operation_mult_x_1_n4082), .ICI(Sgf_operation_mult_x_1_n1763),
.S(Sgf_operation_mult_x_1_n1742), .ICO(Sgf_operation_mult_x_1_n1740),
.CO(Sgf_operation_mult_x_1_n1741) );
CMPR42X1TS Sgf_operation_mult_x_1_U1563 ( .A(Sgf_operation_mult_x_1_n3976),
.B(Sgf_operation_mult_x_1_n3765), .C(Sgf_operation_mult_x_1_n1767),
.D(Sgf_operation_mult_x_1_n1748), .ICI(Sgf_operation_mult_x_1_n1757),
.S(Sgf_operation_mult_x_1_n1739), .ICO(Sgf_operation_mult_x_1_n1737),
.CO(Sgf_operation_mult_x_1_n1738) );
CMPR42X1TS Sgf_operation_mult_x_1_U1559 ( .A(Sgf_operation_mult_x_1_n1730),
.B(Sgf_operation_mult_x_1_n3554), .C(Sgf_operation_mult_x_1_n3659),
.D(Sgf_operation_mult_x_1_n4081), .ICI(Sgf_operation_mult_x_1_n3606),
.S(Sgf_operation_mult_x_1_n1729), .ICO(Sgf_operation_mult_x_1_n1727),
.CO(Sgf_operation_mult_x_1_n1728) );
CMPR42X1TS Sgf_operation_mult_x_1_U1558 ( .A(Sgf_operation_mult_x_1_n1749),
.B(Sgf_operation_mult_x_1_n3869), .C(Sgf_operation_mult_x_1_n3764),
.D(Sgf_operation_mult_x_1_n3501), .ICI(Sgf_operation_mult_x_1_n1743),
.S(Sgf_operation_mult_x_1_n1726), .ICO(Sgf_operation_mult_x_1_n1724),
.CO(Sgf_operation_mult_x_1_n1725) );
CMPR42X1TS Sgf_operation_mult_x_1_U1557 ( .A(Sgf_operation_mult_x_1_n3975),
.B(Sgf_operation_mult_x_1_n1746), .C(Sgf_operation_mult_x_1_n3816),
.D(Sgf_operation_mult_x_1_n4028), .ICI(Sgf_operation_mult_x_1_n3711),
.S(Sgf_operation_mult_x_1_n1723), .ICO(Sgf_operation_mult_x_1_n1721),
.CO(Sgf_operation_mult_x_1_n1722) );
CMPR42X1TS Sgf_operation_mult_x_1_U1556 ( .A(Sgf_operation_mult_x_1_n3922),
.B(Sgf_operation_mult_x_1_n1729), .C(Sgf_operation_mult_x_1_n1740),
.D(Sgf_operation_mult_x_1_n1747), .ICI(Sgf_operation_mult_x_1_n1726),
.S(Sgf_operation_mult_x_1_n1720), .ICO(Sgf_operation_mult_x_1_n1718),
.CO(Sgf_operation_mult_x_1_n1719) );
CMPR42X1TS Sgf_operation_mult_x_1_U1555 ( .A(Sgf_operation_mult_x_1_n1744),
.B(Sgf_operation_mult_x_1_n1737), .C(Sgf_operation_mult_x_1_n1741),
.D(Sgf_operation_mult_x_1_n1723), .ICI(Sgf_operation_mult_x_1_n1738),
.S(Sgf_operation_mult_x_1_n1717), .ICO(Sgf_operation_mult_x_1_n1715),
.CO(Sgf_operation_mult_x_1_n1716) );
CMPR42X1TS Sgf_operation_mult_x_1_U1554 ( .A(Sgf_operation_mult_x_1_n1734),
.B(Sgf_operation_mult_x_1_n1720), .C(Sgf_operation_mult_x_1_n1735),
.D(Sgf_operation_mult_x_1_n1717), .ICI(Sgf_operation_mult_x_1_n1731),
.S(Sgf_operation_mult_x_1_n1714), .ICO(Sgf_operation_mult_x_1_n1712),
.CO(Sgf_operation_mult_x_1_n1713) );
CMPR42X1TS Sgf_operation_mult_x_1_U1552 ( .A(Sgf_operation_mult_x_1_n1730),
.B(Sgf_operation_mult_x_1_n3605), .C(Sgf_operation_mult_x_1_n3500),
.D(Sgf_operation_mult_x_1_n3454), .ICI(Sgf_operation_mult_x_1_n3553),
.S(Sgf_operation_mult_x_1_n1709), .ICO(Sgf_operation_mult_x_1_n1707),
.CO(Sgf_operation_mult_x_1_n1708) );
CMPR42X1TS Sgf_operation_mult_x_1_U1551 ( .A(Sgf_operation_mult_x_1_n4080),
.B(Sgf_operation_mult_x_1_n3815), .C(Sgf_operation_mult_x_1_n3710),
.D(Sgf_operation_mult_x_1_n1727), .ICI(Sgf_operation_mult_x_1_n3868),
.S(Sgf_operation_mult_x_1_n1706), .ICO(Sgf_operation_mult_x_1_n1704),
.CO(Sgf_operation_mult_x_1_n1705) );
CMPR42X1TS Sgf_operation_mult_x_1_U1549 ( .A(Sgf_operation_mult_x_1_n3974),
.B(Sgf_operation_mult_x_1_n3763), .C(Sgf_operation_mult_x_1_n1709),
.D(Sgf_operation_mult_x_1_n1721), .ICI(Sgf_operation_mult_x_1_n1718),
.S(Sgf_operation_mult_x_1_n1700), .ICO(Sgf_operation_mult_x_1_n1698),
.CO(Sgf_operation_mult_x_1_n1699) );
CMPR42X1TS Sgf_operation_mult_x_1_U1548 ( .A(Sgf_operation_mult_x_1_n1725),
.B(Sgf_operation_mult_x_1_n1706), .C(Sgf_operation_mult_x_1_n1703),
.D(Sgf_operation_mult_x_1_n1722), .ICI(Sgf_operation_mult_x_1_n1719),
.S(Sgf_operation_mult_x_1_n1697), .ICO(Sgf_operation_mult_x_1_n1695),
.CO(Sgf_operation_mult_x_1_n1696) );
CMPR42X1TS Sgf_operation_mult_x_1_U1547 ( .A(Sgf_operation_mult_x_1_n1715),
.B(Sgf_operation_mult_x_1_n1700), .C(Sgf_operation_mult_x_1_n1697),
.D(Sgf_operation_mult_x_1_n1716), .ICI(Sgf_operation_mult_x_1_n1712),
.S(Sgf_operation_mult_x_1_n1694), .ICO(Sgf_operation_mult_x_1_n1692),
.CO(Sgf_operation_mult_x_1_n1693) );
CMPR42X1TS Sgf_operation_mult_x_1_U1544 ( .A(Sgf_operation_mult_x_1_n3762),
.B(Sgf_operation_mult_x_1_n1707), .C(Sgf_operation_mult_x_1_n1704),
.D(Sgf_operation_mult_x_1_n3709), .ICI(Sgf_operation_mult_x_1_n1691),
.S(Sgf_operation_mult_x_1_n1685), .ICO(Sgf_operation_mult_x_1_n1683),
.CO(Sgf_operation_mult_x_1_n1684) );
CMPR42X1TS Sgf_operation_mult_x_1_U1543 ( .A(Sgf_operation_mult_x_1_n4026),
.B(Sgf_operation_mult_x_1_n3814), .C(Sgf_operation_mult_x_1_n3920),
.D(Sgf_operation_mult_x_1_n1701), .ICI(Sgf_operation_mult_x_1_n1688),
.S(Sgf_operation_mult_x_1_n1682), .ICO(Sgf_operation_mult_x_1_n1680),
.CO(Sgf_operation_mult_x_1_n1681) );
CMPR42X1TS Sgf_operation_mult_x_1_U1538 ( .A(Sgf_operation_mult_x_1_n3452),
.B(Sgf_operation_mult_x_1_n1673), .C(Sgf_operation_mult_x_1_n3919),
.D(Sgf_operation_mult_x_1_n3813), .ICI(Sgf_operation_mult_x_1_n1686),
.S(Sgf_operation_mult_x_1_n1669), .ICO(Sgf_operation_mult_x_1_n1667),
.CO(Sgf_operation_mult_x_1_n1668) );
CMPR42X1TS Sgf_operation_mult_x_1_U1537 ( .A(Sgf_operation_mult_x_1_n3708),
.B(Sgf_operation_mult_x_1_n3551), .C(Sgf_operation_mult_x_1_n1671),
.D(Sgf_operation_mult_x_1_n1690), .ICI(Sgf_operation_mult_x_1_n3656),
.S(Sgf_operation_mult_x_1_n1666), .ICO(Sgf_operation_mult_x_1_n1664),
.CO(Sgf_operation_mult_x_1_n1665) );
CMPR42X1TS Sgf_operation_mult_x_1_U1536 ( .A(Sgf_operation_mult_x_1_n3972),
.B(Sgf_operation_mult_x_1_n3761), .C(Sgf_operation_mult_x_1_n3866),
.D(Sgf_operation_mult_x_1_n1683), .ICI(Sgf_operation_mult_x_1_n1687),
.S(Sgf_operation_mult_x_1_n1663), .ICO(Sgf_operation_mult_x_1_n1661),
.CO(Sgf_operation_mult_x_1_n1662) );
CMPR42X1TS Sgf_operation_mult_x_1_U1535 ( .A(Sgf_operation_mult_x_1_n1680),
.B(Sgf_operation_mult_x_1_n1669), .C(Sgf_operation_mult_x_1_n1684),
.D(Sgf_operation_mult_x_1_n1666), .ICI(Sgf_operation_mult_x_1_n1681),
.S(Sgf_operation_mult_x_1_n1660), .ICO(Sgf_operation_mult_x_1_n1658),
.CO(Sgf_operation_mult_x_1_n1659) );
CMPR42X1TS Sgf_operation_mult_x_1_U1531 ( .A(Sgf_operation_mult_x_1_n4024),
.B(Sgf_operation_mult_x_1_n3971), .C(Sgf_operation_mult_x_1_n3655),
.D(Sgf_operation_mult_x_1_n3498), .ICI(Sgf_operation_mult_x_1_n1664),
.S(Sgf_operation_mult_x_1_n1650), .ICO(Sgf_operation_mult_x_1_n1648),
.CO(Sgf_operation_mult_x_1_n1649) );
CMPR42X1TS Sgf_operation_mult_x_1_U1528 ( .A(Sgf_operation_mult_x_1_n1661),
.B(Sgf_operation_mult_x_1_n1650), .C(Sgf_operation_mult_x_1_n1647),
.D(Sgf_operation_mult_x_1_n1665), .ICI(Sgf_operation_mult_x_1_n1662),
.S(Sgf_operation_mult_x_1_n1641), .ICO(Sgf_operation_mult_x_1_n1639),
.CO(Sgf_operation_mult_x_1_n1640) );
CMPR42X1TS Sgf_operation_mult_x_1_U1525 ( .A(Sgf_operation_mult_x_1_n3451),
.B(Sgf_operation_mult_x_1_n3917), .C(Sgf_operation_mult_x_1_n3811),
.D(Sgf_operation_mult_x_1_n3601), .ICI(Sgf_operation_mult_x_1_n3864),
.S(Sgf_operation_mult_x_1_n1633), .ICO(Sgf_operation_mult_x_1_n1631),
.CO(Sgf_operation_mult_x_1_n1632) );
CMPR42X1TS Sgf_operation_mult_x_1_U1523 ( .A(Sgf_operation_mult_x_1_n1648),
.B(Sgf_operation_mult_x_1_n3654), .C(Sgf_operation_mult_x_1_n3759),
.D(Sgf_operation_mult_x_1_n3970), .ICI(Sgf_operation_mult_x_1_n1633),
.S(Sgf_operation_mult_x_1_n1627), .ICO(Sgf_operation_mult_x_1_n1625),
.CO(Sgf_operation_mult_x_1_n1626) );
CMPR42X1TS Sgf_operation_mult_x_1_U1522 ( .A(Sgf_operation_mult_x_1_n1642),
.B(Sgf_operation_mult_x_1_n1649), .C(Sgf_operation_mult_x_1_n1646),
.D(Sgf_operation_mult_x_1_n1630), .ICI(Sgf_operation_mult_x_1_n1639),
.S(Sgf_operation_mult_x_1_n1624), .ICO(Sgf_operation_mult_x_1_n1622),
.CO(Sgf_operation_mult_x_1_n1623) );
CMPR42X1TS Sgf_operation_mult_x_1_U1521 ( .A(Sgf_operation_mult_x_1_n1643),
.B(Sgf_operation_mult_x_1_n1627), .C(Sgf_operation_mult_x_1_n1640),
.D(Sgf_operation_mult_x_1_n1624), .ICI(Sgf_operation_mult_x_1_n1636),
.S(Sgf_operation_mult_x_1_n1621), .ICO(Sgf_operation_mult_x_1_n1619),
.CO(Sgf_operation_mult_x_1_n1620) );
CMPR42X1TS Sgf_operation_mult_x_1_U1519 ( .A(Sgf_operation_mult_x_1_n1618),
.B(Sgf_operation_mult_x_1_n3548), .C(Sgf_operation_mult_x_1_n3969),
.D(Sgf_operation_mult_x_1_n1634), .ICI(Sgf_operation_mult_x_1_n3496),
.S(Sgf_operation_mult_x_1_n1617), .ICO(Sgf_operation_mult_x_1_n1615),
.CO(Sgf_operation_mult_x_1_n1616) );
CMPR42X1TS Sgf_operation_mult_x_1_U1513 ( .A(Sgf_operation_mult_x_1_n1618),
.B(Sgf_operation_mult_x_1_n3495), .C(Sgf_operation_mult_x_1_n3450),
.D(Sgf_operation_mult_x_1_n3968), .ICI(Sgf_operation_mult_x_1_n3704),
.S(Sgf_operation_mult_x_1_n1600), .ICO(Sgf_operation_mult_x_1_n1598),
.CO(Sgf_operation_mult_x_1_n1599) );
CMPR42X1TS Sgf_operation_mult_x_1_U1512 ( .A(Sgf_operation_mult_x_1_n3599),
.B(Sgf_operation_mult_x_1_n3915), .C(Sgf_operation_mult_x_1_n3547),
.D(Sgf_operation_mult_x_1_n1615), .ICI(Sgf_operation_mult_x_1_n1616),
.S(Sgf_operation_mult_x_1_n1597), .ICO(Sgf_operation_mult_x_1_n1595),
.CO(Sgf_operation_mult_x_1_n1596) );
CMPR42X1TS Sgf_operation_mult_x_1_U1510 ( .A(Sgf_operation_mult_x_1_n1600),
.B(Sgf_operation_mult_x_1_n1609), .C(Sgf_operation_mult_x_1_n1613),
.D(Sgf_operation_mult_x_1_n1597), .ICI(Sgf_operation_mult_x_1_n1610),
.S(Sgf_operation_mult_x_1_n1591), .ICO(Sgf_operation_mult_x_1_n1589),
.CO(Sgf_operation_mult_x_1_n1590) );
CMPR42X1TS Sgf_operation_mult_x_1_U1509 ( .A(Sgf_operation_mult_x_1_n1606),
.B(Sgf_operation_mult_x_1_n1594), .C(Sgf_operation_mult_x_1_n1607),
.D(Sgf_operation_mult_x_1_n1591), .ICI(Sgf_operation_mult_x_1_n1603),
.S(Sgf_operation_mult_x_1_n1588), .ICO(Sgf_operation_mult_x_1_n1586),
.CO(Sgf_operation_mult_x_1_n1587) );
CMPR42X1TS Sgf_operation_mult_x_1_U1508 ( .A(n5079), .B(
Sgf_operation_mult_x_1_n3449), .C(Sgf_operation_mult_x_1_n1601), .D(
Sgf_operation_mult_x_1_n3651), .ICI(Sgf_operation_mult_x_1_n3546), .S(
Sgf_operation_mult_x_1_n1585), .ICO(Sgf_operation_mult_x_1_n1570),
.CO(Sgf_operation_mult_x_1_n1584) );
CMPR42X1TS Sgf_operation_mult_x_1_U1507 ( .A(Sgf_operation_mult_x_1_n3861),
.B(Sgf_operation_mult_x_1_n3756), .C(Sgf_operation_mult_x_1_n1598),
.D(Sgf_operation_mult_x_1_n3494), .ICI(Sgf_operation_mult_x_1_n1599),
.S(Sgf_operation_mult_x_1_n1583), .ICO(Sgf_operation_mult_x_1_n1581),
.CO(Sgf_operation_mult_x_1_n1582) );
CMPR42X1TS Sgf_operation_mult_x_1_U1506 ( .A(Sgf_operation_mult_x_1_n3914),
.B(Sgf_operation_mult_x_1_n3598), .C(Sgf_operation_mult_x_1_n3703),
.D(Sgf_operation_mult_x_1_n1595), .ICI(Sgf_operation_mult_x_1_n1583),
.S(Sgf_operation_mult_x_1_n1580), .ICO(Sgf_operation_mult_x_1_n1578),
.CO(Sgf_operation_mult_x_1_n1579) );
CMPR42X1TS Sgf_operation_mult_x_1_U1504 ( .A(Sgf_operation_mult_x_1_n1589),
.B(Sgf_operation_mult_x_1_n1580), .C(Sgf_operation_mult_x_1_n1590),
.D(Sgf_operation_mult_x_1_n1577), .ICI(Sgf_operation_mult_x_1_n1586),
.S(Sgf_operation_mult_x_1_n1574), .ICO(Sgf_operation_mult_x_1_n1572),
.CO(Sgf_operation_mult_x_1_n1573) );
CMPR42X1TS Sgf_operation_mult_x_1_U1499 ( .A(Sgf_operation_mult_x_1_n3545),
.B(Sgf_operation_mult_x_1_n1584), .C(Sgf_operation_mult_x_1_n1582),
.D(Sgf_operation_mult_x_1_n1567), .ICI(Sgf_operation_mult_x_1_n1575),
.S(Sgf_operation_mult_x_1_n1561), .ICO(Sgf_operation_mult_x_1_n1559),
.CO(Sgf_operation_mult_x_1_n1560) );
CMPR42X1TS Sgf_operation_mult_x_1_U1494 ( .A(Sgf_operation_mult_x_1_n3544),
.B(Sgf_operation_mult_x_1_n3649), .C(Sgf_operation_mult_x_1_n1553),
.D(Sgf_operation_mult_x_1_n1565), .ICI(Sgf_operation_mult_x_1_n3806),
.S(Sgf_operation_mult_x_1_n1548), .ICO(Sgf_operation_mult_x_1_n1546),
.CO(Sgf_operation_mult_x_1_n1547) );
CMPR42X1TS Sgf_operation_mult_x_1_U1493 ( .A(Sgf_operation_mult_x_1_n3701),
.B(Sgf_operation_mult_x_1_n1562), .C(Sgf_operation_mult_x_1_n1566),
.D(Sgf_operation_mult_x_1_n1551), .ICI(Sgf_operation_mult_x_1_n1548),
.S(Sgf_operation_mult_x_1_n1545), .ICO(Sgf_operation_mult_x_1_n1543),
.CO(Sgf_operation_mult_x_1_n1544) );
CMPR42X1TS Sgf_operation_mult_x_1_U1489 ( .A(Sgf_operation_mult_x_1_n3805),
.B(Sgf_operation_mult_x_1_n3491), .C(Sgf_operation_mult_x_1_n3543),
.D(Sgf_operation_mult_x_1_n3648), .ICI(Sgf_operation_mult_x_1_n1549),
.S(Sgf_operation_mult_x_1_n1534), .ICO(Sgf_operation_mult_x_1_n1532),
.CO(Sgf_operation_mult_x_1_n1533) );
CMPR42X1TS Sgf_operation_mult_x_1_U1487 ( .A(Sgf_operation_mult_x_1_n1543),
.B(Sgf_operation_mult_x_1_n1534), .C(Sgf_operation_mult_x_1_n1544),
.D(Sgf_operation_mult_x_1_n1531), .ICI(Sgf_operation_mult_x_1_n1540),
.S(Sgf_operation_mult_x_1_n1528), .ICO(Sgf_operation_mult_x_1_n1526),
.CO(Sgf_operation_mult_x_1_n1527) );
CMPR42X1TS Sgf_operation_mult_x_1_U1485 ( .A(Sgf_operation_mult_x_1_n1525),
.B(Sgf_operation_mult_x_1_n3857), .C(Sgf_operation_mult_x_1_n3752),
.D(Sgf_operation_mult_x_1_n3542), .ICI(Sgf_operation_mult_x_1_n1538),
.S(Sgf_operation_mult_x_1_n1524), .ICO(Sgf_operation_mult_x_1_n1522),
.CO(Sgf_operation_mult_x_1_n1523) );
CMPR42X1TS Sgf_operation_mult_x_1_U1484 ( .A(Sgf_operation_mult_x_1_n3647),
.B(Sgf_operation_mult_x_1_n3804), .C(Sgf_operation_mult_x_1_n3594),
.D(Sgf_operation_mult_x_1_n3699), .ICI(Sgf_operation_mult_x_1_n1535),
.S(Sgf_operation_mult_x_1_n1521), .ICO(Sgf_operation_mult_x_1_n1519),
.CO(Sgf_operation_mult_x_1_n1520) );
CMPR42X1TS Sgf_operation_mult_x_1_U1480 ( .A(Sgf_operation_mult_x_1_n1525),
.B(Sgf_operation_mult_x_1_n3446), .C(Sgf_operation_mult_x_1_n3856),
.D(Sgf_operation_mult_x_1_n3803), .ICI(Sgf_operation_mult_x_1_n3489),
.S(Sgf_operation_mult_x_1_n1510), .ICO(Sgf_operation_mult_x_1_n1508),
.CO(Sgf_operation_mult_x_1_n1509) );
CMPR42X1TS Sgf_operation_mult_x_1_U1476 ( .A(n5085), .B(
Sgf_operation_mult_x_1_n1511), .C(Sgf_operation_mult_x_1_n3445), .D(
Sgf_operation_mult_x_1_n3750), .ICI(Sgf_operation_mult_x_1_n3540), .S(
Sgf_operation_mult_x_1_n1498), .ICO(Sgf_operation_mult_x_1_n1496),
.CO(Sgf_operation_mult_x_1_n1497) );
CMPR42X1TS Sgf_operation_mult_x_1_U1475 ( .A(Sgf_operation_mult_x_1_n3645),
.B(Sgf_operation_mult_x_1_n1508), .C(Sgf_operation_mult_x_1_n3488),
.D(Sgf_operation_mult_x_1_n3592), .ICI(Sgf_operation_mult_x_1_n1505),
.S(Sgf_operation_mult_x_1_n1495), .ICO(Sgf_operation_mult_x_1_n1493),
.CO(Sgf_operation_mult_x_1_n1494) );
CMPR42X1TS Sgf_operation_mult_x_1_U1474 ( .A(Sgf_operation_mult_x_1_n3802),
.B(Sgf_operation_mult_x_1_n3697), .C(Sgf_operation_mult_x_1_n1509),
.D(Sgf_operation_mult_x_1_n1498), .ICI(Sgf_operation_mult_x_1_n1506),
.S(Sgf_operation_mult_x_1_n1492), .ICO(Sgf_operation_mult_x_1_n1490),
.CO(Sgf_operation_mult_x_1_n1491) );
CMPR42X1TS Sgf_operation_mult_x_1_U1473 ( .A(Sgf_operation_mult_x_1_n1502),
.B(Sgf_operation_mult_x_1_n1495), .C(Sgf_operation_mult_x_1_n1492),
.D(Sgf_operation_mult_x_1_n1503), .ICI(Sgf_operation_mult_x_1_n1499),
.S(Sgf_operation_mult_x_1_n1489), .ICO(Sgf_operation_mult_x_1_n1487),
.CO(Sgf_operation_mult_x_1_n1488) );
CMPR42X1TS Sgf_operation_mult_x_1_U1470 ( .A(Sgf_operation_mult_x_1_n1496),
.B(Sgf_operation_mult_x_1_n3696), .C(Sgf_operation_mult_x_1_n3591),
.D(Sgf_operation_mult_x_1_n3644), .ICI(Sgf_operation_mult_x_1_n1484),
.S(Sgf_operation_mult_x_1_n1482), .ICO(Sgf_operation_mult_x_1_n1480),
.CO(Sgf_operation_mult_x_1_n1481) );
CMPR42X1TS Sgf_operation_mult_x_1_U1469 ( .A(Sgf_operation_mult_x_1_n3749),
.B(Sgf_operation_mult_x_1_n3539), .C(Sgf_operation_mult_x_1_n1497),
.D(Sgf_operation_mult_x_1_n1493), .ICI(Sgf_operation_mult_x_1_n1490),
.S(Sgf_operation_mult_x_1_n1479), .ICO(Sgf_operation_mult_x_1_n1477),
.CO(Sgf_operation_mult_x_1_n1478) );
CMPR42X1TS Sgf_operation_mult_x_1_U1468 ( .A(Sgf_operation_mult_x_1_n1494),
.B(Sgf_operation_mult_x_1_n1482), .C(Sgf_operation_mult_x_1_n1491),
.D(Sgf_operation_mult_x_1_n1479), .ICI(Sgf_operation_mult_x_1_n1487),
.S(Sgf_operation_mult_x_1_n1476), .ICO(Sgf_operation_mult_x_1_n1474),
.CO(Sgf_operation_mult_x_1_n1475) );
CMPR42X1TS Sgf_operation_mult_x_1_U1465 ( .A(Sgf_operation_mult_x_1_n3643),
.B(Sgf_operation_mult_x_1_n3538), .C(Sgf_operation_mult_x_1_n3748),
.D(Sgf_operation_mult_x_1_n1471), .ICI(Sgf_operation_mult_x_1_n3590),
.S(Sgf_operation_mult_x_1_n1469), .ICO(Sgf_operation_mult_x_1_n1467),
.CO(Sgf_operation_mult_x_1_n1468) );
CMPR42X1TS Sgf_operation_mult_x_1_U1464 ( .A(Sgf_operation_mult_x_1_n1480),
.B(Sgf_operation_mult_x_1_n1483), .C(Sgf_operation_mult_x_1_n3695),
.D(Sgf_operation_mult_x_1_n3486), .ICI(Sgf_operation_mult_x_1_n1477),
.S(Sgf_operation_mult_x_1_n1466), .ICO(Sgf_operation_mult_x_1_n1464),
.CO(Sgf_operation_mult_x_1_n1465) );
CMPR42X1TS Sgf_operation_mult_x_1_U1463 ( .A(Sgf_operation_mult_x_1_n1481),
.B(Sgf_operation_mult_x_1_n1469), .C(Sgf_operation_mult_x_1_n1466),
.D(Sgf_operation_mult_x_1_n1478), .ICI(Sgf_operation_mult_x_1_n1474),
.S(Sgf_operation_mult_x_1_n1463), .ICO(Sgf_operation_mult_x_1_n1461),
.CO(Sgf_operation_mult_x_1_n1462) );
CMPR42X1TS Sgf_operation_mult_x_1_U1461 ( .A(Sgf_operation_mult_x_1_n3589),
.B(Sgf_operation_mult_x_1_n3485), .C(Sgf_operation_mult_x_1_n3443),
.D(Sgf_operation_mult_x_1_n1470), .ICI(Sgf_operation_mult_x_1_n3537),
.S(Sgf_operation_mult_x_1_n1458), .ICO(Sgf_operation_mult_x_1_n1456),
.CO(Sgf_operation_mult_x_1_n1457) );
CMPR42X1TS Sgf_operation_mult_x_1_U1460 ( .A(Sgf_operation_mult_x_1_n1460),
.B(Sgf_operation_mult_x_1_n1467), .C(Sgf_operation_mult_x_1_n3642),
.D(Sgf_operation_mult_x_1_n3747), .ICI(Sgf_operation_mult_x_1_n1468),
.S(Sgf_operation_mult_x_1_n1455), .ICO(Sgf_operation_mult_x_1_n1453),
.CO(Sgf_operation_mult_x_1_n1454) );
CMPR42X1TS Sgf_operation_mult_x_1_U1457 ( .A(Sgf_operation_mult_x_1_n1449),
.B(Sgf_operation_mult_x_1_n3746), .C(Sgf_operation_mult_x_1_n3641),
.D(Sgf_operation_mult_x_1_n3536), .ICI(Sgf_operation_mult_x_1_n3588),
.S(Sgf_operation_mult_x_1_n1448), .ICO(Sgf_operation_mult_x_1_n1446),
.CO(Sgf_operation_mult_x_1_n1447) );
CMPR42X1TS Sgf_operation_mult_x_1_U1455 ( .A(Sgf_operation_mult_x_1_n1453),
.B(Sgf_operation_mult_x_1_n1457), .C(Sgf_operation_mult_x_1_n1454),
.D(Sgf_operation_mult_x_1_n1445), .ICI(Sgf_operation_mult_x_1_n1450),
.S(Sgf_operation_mult_x_1_n1442), .ICO(Sgf_operation_mult_x_1_n1440),
.CO(Sgf_operation_mult_x_1_n1441) );
CMPR42X1TS Sgf_operation_mult_x_1_U1453 ( .A(Sgf_operation_mult_x_1_n1449),
.B(Sgf_operation_mult_x_1_n3745), .C(Sgf_operation_mult_x_1_n3692),
.D(Sgf_operation_mult_x_1_n3587), .ICI(Sgf_operation_mult_x_1_n3535),
.S(Sgf_operation_mult_x_1_n1437), .ICO(Sgf_operation_mult_x_1_n1435),
.CO(Sgf_operation_mult_x_1_n1436) );
CMPR42X1TS Sgf_operation_mult_x_1_U1449 ( .A(Sgf_operation_mult_x_1_n1435),
.B(Sgf_operation_mult_x_1_n3482), .C(Sgf_operation_mult_x_1_n3691),
.D(Sgf_operation_mult_x_1_n3586), .ICI(Sgf_operation_mult_x_1_n1436),
.S(Sgf_operation_mult_x_1_n1425), .ICO(Sgf_operation_mult_x_1_n1423),
.CO(Sgf_operation_mult_x_1_n1424) );
CMPR42X1TS Sgf_operation_mult_x_1_U1448 ( .A(Sgf_operation_mult_x_1_n1432),
.B(Sgf_operation_mult_x_1_n1428), .C(Sgf_operation_mult_x_1_n1433),
.D(Sgf_operation_mult_x_1_n1425), .ICI(Sgf_operation_mult_x_1_n1429),
.S(Sgf_operation_mult_x_1_n1422), .ICO(Sgf_operation_mult_x_1_n1420),
.CO(Sgf_operation_mult_x_1_n1421) );
CMPR42X1TS Sgf_operation_mult_x_1_U1445 ( .A(Sgf_operation_mult_x_1_n3585),
.B(Sgf_operation_mult_x_1_n3481), .C(Sgf_operation_mult_x_1_n3533),
.D(Sgf_operation_mult_x_1_n3638), .ICI(Sgf_operation_mult_x_1_n1427),
.S(Sgf_operation_mult_x_1_n1415), .ICO(Sgf_operation_mult_x_1_n1413),
.CO(Sgf_operation_mult_x_1_n1414) );
CMPR42X1TS Sgf_operation_mult_x_1_U1441 ( .A(Sgf_operation_mult_x_1_n3532),
.B(Sgf_operation_mult_x_1_n3637), .C(Sgf_operation_mult_x_1_n1407),
.D(Sgf_operation_mult_x_1_n1416), .ICI(Sgf_operation_mult_x_1_n3480),
.S(Sgf_operation_mult_x_1_n1405), .ICO(Sgf_operation_mult_x_1_n1403),
.CO(Sgf_operation_mult_x_1_n1404) );
CMPR42X1TS Sgf_operation_mult_x_1_U1438 ( .A(Sgf_operation_mult_x_1_n3479),
.B(Sgf_operation_mult_x_1_n3439), .C(Sgf_operation_mult_x_1_n1406),
.D(Sgf_operation_mult_x_1_n1399), .ICI(Sgf_operation_mult_x_1_n1403),
.S(Sgf_operation_mult_x_1_n1397), .ICO(Sgf_operation_mult_x_1_n1395),
.CO(Sgf_operation_mult_x_1_n1396) );
CMPR42X1TS Sgf_operation_mult_x_1_U1437 ( .A(Sgf_operation_mult_x_1_n3636),
.B(Sgf_operation_mult_x_1_n3531), .C(Sgf_operation_mult_x_1_n1404),
.D(Sgf_operation_mult_x_1_n1397), .ICI(Sgf_operation_mult_x_1_n1400),
.S(Sgf_operation_mult_x_1_n1394), .ICO(Sgf_operation_mult_x_1_n1392),
.CO(Sgf_operation_mult_x_1_n1393) );
CMPR42X1TS Sgf_operation_mult_x_1_U1435 ( .A(Sgf_operation_mult_x_1_n1391),
.B(Sgf_operation_mult_x_1_n3635), .C(Sgf_operation_mult_x_1_n3530),
.D(Sgf_operation_mult_x_1_n1398), .ICI(Sgf_operation_mult_x_1_n3478),
.S(Sgf_operation_mult_x_1_n1390), .ICO(Sgf_operation_mult_x_1_n1388),
.CO(Sgf_operation_mult_x_1_n1389) );
CMPR42X1TS Sgf_operation_mult_x_1_U1434 ( .A(Sgf_operation_mult_x_1_n3582),
.B(Sgf_operation_mult_x_1_n1395), .C(Sgf_operation_mult_x_1_n1396),
.D(Sgf_operation_mult_x_1_n1390), .ICI(Sgf_operation_mult_x_1_n1392),
.S(Sgf_operation_mult_x_1_n1387), .ICO(Sgf_operation_mult_x_1_n1385),
.CO(Sgf_operation_mult_x_1_n1386) );
CMPR42X1TS Sgf_operation_mult_x_1_U1432 ( .A(Sgf_operation_mult_x_1_n1391),
.B(Sgf_operation_mult_x_1_n3634), .C(Sgf_operation_mult_x_1_n3581),
.D(Sgf_operation_mult_x_1_n3477), .ICI(Sgf_operation_mult_x_1_n3529),
.S(Sgf_operation_mult_x_1_n1382), .ICO(Sgf_operation_mult_x_1_n1380),
.CO(Sgf_operation_mult_x_1_n1381) );
CMPR42X1TS Sgf_operation_mult_x_1_U1430 ( .A(n5091), .B(
Sgf_operation_mult_x_1_n1383), .C(Sgf_operation_mult_x_1_n3437), .D(
Sgf_operation_mult_x_1_n3528), .ICI(Sgf_operation_mult_x_1_n1380), .S(
Sgf_operation_mult_x_1_n1376), .ICO(Sgf_operation_mult_x_1_n1374),
.CO(Sgf_operation_mult_x_1_n1375) );
CMPR42X1TS Sgf_operation_mult_x_1_U1421 ( .A(Sgf_operation_mult_x_1_n3435),
.B(Sgf_operation_mult_x_1_n1360), .C(Sgf_operation_mult_x_1_n1356),
.D(Sgf_operation_mult_x_1_n3525), .ICI(Sgf_operation_mult_x_1_n1357),
.S(Sgf_operation_mult_x_1_n1354), .ICO(Sgf_operation_mult_x_1_n1352),
.CO(Sgf_operation_mult_x_1_n1353) );
CMPR42X1TS Sgf_operation_mult_x_1_U1417 ( .A(Sgf_operation_mult_x_1_n1351),
.B(Sgf_operation_mult_x_1_n3523), .C(Sgf_operation_mult_x_1_n3471),
.D(Sgf_operation_mult_x_1_n3434), .ICI(Sgf_operation_mult_x_1_n1348),
.S(Sgf_operation_mult_x_1_n1345), .ICO(Sgf_operation_mult_x_1_n1343),
.CO(Sgf_operation_mult_x_1_n1344) );
CMPR42X1TS Sgf_operation_mult_x_1_U1416 ( .A(n5093), .B(
Sgf_operation_mult_x_1_n1346), .C(Sgf_operation_mult_x_1_n3433), .D(
Sgf_operation_mult_x_1_n1343), .ICI(Sgf_operation_mult_x_1_n3470), .S(
Sgf_operation_mult_x_1_n1342), .ICO(Sgf_operation_mult_x_1_n1340),
.CO(Sgf_operation_mult_x_1_n1341) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n417), .CK(clk), .RN(n5162), .Q(
FSM_selector_B[1]), .QN(n5088) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n606), .CK(clk), .RN(n5158), .Q(
FS_Module_state_reg[0]), .QN(n5073) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n604), .CK(clk), .RN(n5153), .Q(
FS_Module_state_reg[2]), .QN(n5072) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n539), .CK(clk), .RN(
n5170), .Q(Op_MX[0]), .QN(n5071) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n607), .CK(clk), .RN(
Sgf_operation_n3), .Q(FS_Module_state_reg[3]), .QN(n5070) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n605), .CK(clk), .RN(
Sgf_operation_n3), .Q(n5150), .QN(n5181) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n474), .CK(clk),
.RN(n5168), .Q(zero_flag), .QN(n5099) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n418), .CK(clk), .RN(n5162), .Q(
FSM_selector_B[0]), .QN(n5089) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n589), .CK(clk), .RN(
n5175), .Q(Op_MX[50]), .QN(n5094) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n586), .CK(clk), .RN(
n5171), .Q(Op_MX[47]), .QN(n5093) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n583), .CK(clk), .RN(
n701), .Q(Op_MX[44]), .QN(n5092) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n580), .CK(clk), .RN(
n5169), .Q(Op_MX[41]), .QN(n5091) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n553), .CK(clk), .RN(
n5164), .Q(Op_MX[14]), .QN(n5082) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n577), .CK(clk), .RN(
n881), .Q(Op_MX[38]), .QN(n5090) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n574), .CK(clk), .RN(
n5174), .Q(Op_MX[35]), .QN(n5087) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n571), .CK(clk), .RN(
n5170), .Q(Op_MX[32]), .QN(n5086) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n568), .CK(clk), .RN(
n5179), .Q(Op_MX[29]), .QN(n5085) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n565), .CK(clk), .RN(
n702), .Q(Op_MX[26]), .QN(n5084) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n562), .CK(clk), .RN(
n883), .Q(Op_MX[23]), .QN(n5079) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n559), .CK(clk), .RN(
n883), .Q(Op_MX[20]), .QN(n5081) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n556), .CK(clk), .RN(
n883), .Q(Op_MX[17]), .QN(n5077) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n550), .CK(clk), .RN(
n5161), .Q(Op_MX[11]), .QN(n5080) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n547), .CK(clk), .RN(
n5161), .Q(Op_MX[8]), .QN(n5083) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n544), .CK(clk), .RN(
n5172), .Q(Op_MX[5]), .QN(n5078) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n351), .CK(clk), .RN(n5167),
.Q(underflow_flag), .QN(n5096) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n5180), .Q(FSM_selector_C),
.QN(n5074) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n472), .CK(clk), .RN(n5173),
.QN(n5182) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n590), .CK(clk), .RN(
n5175), .Q(Op_MX[51]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n477), .CK(clk), .RN(
n5162), .Q(Op_MY[2]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n479), .CK(clk), .RN(
n5162), .Q(Op_MY[4]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n491), .CK(clk), .RN(
n5171), .Q(Op_MY[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n493), .CK(clk), .RN(
n5172), .Q(Op_MY[18]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n497), .CK(clk), .RN(
n5170), .Q(Op_MY[22]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n500), .CK(clk), .RN(
n701), .Q(Op_MY[25]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n505), .CK(clk), .RN(
n5179), .Q(Op_MY[30]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n507), .CK(clk), .RN(
n5170), .Q(Op_MY[32]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n512), .CK(clk), .RN(
n701), .Q(Op_MY[37]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n515), .CK(clk), .RN(
n5163), .Q(Op_MY[40]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n521), .CK(clk), .RN(
n5180), .Q(Op_MY[46]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n523), .CK(clk), .RN(
n702), .Q(Op_MY[48]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n524), .CK(clk), .RN(
n5177), .Q(Op_MY[49]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n526), .CK(clk), .RN(
n5167), .Q(Op_MY[51]), .QN(n758) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n572), .CK(clk), .RN(
n5163), .Q(Op_MX[33]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n543), .CK(clk), .RN(
n5172), .Q(Op_MX[4]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n555), .CK(clk), .RN(
n883), .Q(Op_MX[16]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n561), .CK(clk), .RN(
n883), .Q(Op_MX[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n576), .CK(clk), .RN(
n701), .Q(Op_MX[37]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n540), .CK(clk), .RN(
n5178), .Q(Op_MX[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n355), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n358), .CK(clk),
.RN(n5172), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n359), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n360), .CK(clk),
.RN(n5172), .Q(Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n361), .CK(clk),
.RN(n5171), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n362), .CK(clk),
.RN(n5165), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n363), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n364), .CK(clk),
.RN(n5165), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n365), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n366), .CK(clk),
.RN(n5171), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n367), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n369), .CK(clk),
.RN(n5170), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n370), .CK(clk),
.RN(n5179), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n371), .CK(clk),
.RN(n5169), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n372), .CK(clk),
.RN(n5162), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n373), .CK(clk),
.RN(n5177), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n374), .CK(clk),
.RN(n883), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n375), .CK(clk),
.RN(n5162), .Q(Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n376), .CK(clk),
.RN(n5179), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n377), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n378), .CK(clk),
.RN(n5172), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n379), .CK(clk),
.RN(n5176), .Q(Sgf_normalized_result[27]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n380), .CK(clk),
.RN(n5171), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n381), .CK(clk),
.RN(n5165), .Q(Sgf_normalized_result[29]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n383), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[31]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n384), .CK(clk),
.RN(n5171), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n385), .CK(clk),
.RN(n5166), .Q(Sgf_normalized_result[33]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n386), .CK(clk),
.RN(n5176), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n387), .CK(clk),
.RN(n5161), .Q(Sgf_normalized_result[35]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n388), .CK(clk),
.RN(n5176), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n389), .CK(clk),
.RN(n5168), .Q(Sgf_normalized_result[37]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n390), .CK(clk),
.RN(n5168), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n391), .CK(clk),
.RN(n5168), .Q(Sgf_normalized_result[39]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n392), .CK(clk),
.RN(n5175), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n393), .CK(clk),
.RN(n5164), .Q(Sgf_normalized_result[41]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n394), .CK(clk),
.RN(n5173), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n396), .CK(clk),
.RN(n5175), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n397), .CK(clk),
.RN(n5164), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n398), .CK(clk),
.RN(n5173), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n399), .CK(clk),
.RN(n5175), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n400), .CK(clk),
.RN(n5164), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n401), .CK(clk),
.RN(n5173), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n402), .CK(clk),
.RN(n5175), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n403), .CK(clk),
.RN(n5164), .Q(Sgf_normalized_result[51]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n356), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n357), .CK(clk),
.RN(n5161), .Q(Sgf_normalized_result[5]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n476), .CK(clk), .RN(
n5162), .Q(Op_MY[1]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n498), .CK(clk), .RN(
n5163), .Q(Op_MY[23]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n502), .CK(clk), .RN(
n5163), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n501), .CK(clk), .RN(
n5180), .Q(Op_MY[26]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n484), .CK(clk), .RN(
n5166), .Q(Op_MY[9]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n483), .CK(clk), .RN(
n5168), .Q(Op_MY[8]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n510), .CK(clk), .RN(
n5178), .Q(Op_MY[35]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n480), .CK(clk), .RN(
n5162), .Q(Op_MY[5]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n511), .CK(clk), .RN(
n5174), .Q(Op_MY[36]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n514), .CK(clk), .RN(
n5179), .Q(Op_MY[39]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n519), .CK(clk), .RN(
n5170), .Q(Op_MY[44]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n520), .CK(clk), .RN(
n5179), .Q(Op_MY[45]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_102_ ( .D(Sgf_operation_n7), .CK(clk),
.RN(n5159), .Q(P_Sgf[102]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_53_ ( .D(Sgf_operation_n56), .CK(clk),
.RN(n5157), .Q(P_Sgf[53]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_67_ ( .D(Sgf_operation_n42), .CK(clk),
.RN(n5154), .Q(P_Sgf[67]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_69_ ( .D(Sgf_operation_n40), .CK(clk),
.RN(n5156), .Q(P_Sgf[69]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_71_ ( .D(Sgf_operation_n38), .CK(clk),
.RN(n5158), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_73_ ( .D(Sgf_operation_n36), .CK(clk),
.RN(n5160), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_75_ ( .D(Sgf_operation_n34), .CK(clk),
.RN(n5160), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_77_ ( .D(Sgf_operation_n32), .CK(clk),
.RN(n5156), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_79_ ( .D(Sgf_operation_n30), .CK(clk),
.RN(n5153), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_87_ ( .D(Sgf_operation_n22), .CK(clk),
.RN(n5156), .Q(P_Sgf[87]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_89_ ( .D(Sgf_operation_n20), .CK(clk),
.RN(n5154), .Q(P_Sgf[89]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_91_ ( .D(Sgf_operation_n18), .CK(clk),
.RN(n5154), .Q(P_Sgf[91]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_93_ ( .D(Sgf_operation_n16), .CK(clk),
.RN(n5154), .Q(P_Sgf[93]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_95_ ( .D(Sgf_operation_n14), .CK(clk),
.RN(n5159), .Q(P_Sgf[95]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_97_ ( .D(Sgf_operation_n12), .CK(clk),
.RN(n5153), .Q(P_Sgf[97]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_99_ ( .D(Sgf_operation_n10), .CK(clk),
.RN(n5153), .Q(P_Sgf[99]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_105_ ( .D(Sgf_operation_n4), .CK(clk),
.RN(n5155), .Q(P_Sgf[105]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n600), .CK(clk), .RN(
n5164), .Q(Op_MX[61]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n368), .CK(clk),
.RN(n5165), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n382), .CK(clk),
.RN(n5161), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n395), .CK(clk),
.RN(n5173), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n533), .CK(clk), .RN(
n5170), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n527), .CK(clk), .RN(
n5179), .Q(Op_MY[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n537), .CK(clk), .RN(
n5175), .Q(Op_MY[62]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n406), .CK(clk), .RN(n5178),
.Q(exp_oper_result[10]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n408), .CK(clk), .RN(n5163),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n409), .CK(clk), .RN(n5174),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n410), .CK(clk), .RN(n702),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n411), .CK(clk), .RN(n701),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n412), .CK(clk), .RN(n5170),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n413), .CK(clk), .RN(n5179),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n414), .CK(clk), .RN(n5163),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n415), .CK(clk), .RN(n5162),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n416), .CK(clk), .RN(n5162),
.Q(exp_oper_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n352), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n353), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n405), .CK(clk), .RN(n5180),
.Q(exp_oper_result[11]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n594), .CK(clk), .RN(
n5173), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n595), .CK(clk), .RN(
n5164), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n596), .CK(clk), .RN(
n5175), .Q(Op_MX[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n593), .CK(clk), .RN(
n5173), .Q(Op_MX[54]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_23_ ( .D(Sgf_operation_n86), .CK(clk),
.RN(n5157), .Q(P_Sgf[23]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_31_ ( .D(Sgf_operation_n78), .CK(clk),
.RN(n5155), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_45_ ( .D(Sgf_operation_n64), .CK(clk),
.RN(n5153), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_47_ ( .D(Sgf_operation_n62), .CK(clk),
.RN(n5155), .Q(P_Sgf[47]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n548), .CK(clk), .RN(
n5166), .Q(Op_MX[9]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n563), .CK(clk), .RN(
n5175), .Q(Op_MX[24]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n564), .CK(clk), .RN(
n5173), .Q(Op_MX[25]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n569), .CK(clk), .RN(
n5178), .Q(Op_MX[30]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n570), .CK(clk), .RN(
n5180), .Q(Op_MX[31]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n584), .CK(clk), .RN(
n883), .Q(Op_MX[45]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n585), .CK(clk), .RN(
n883), .Q(Op_MX[46]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n545), .CK(clk), .RN(
n5161), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n546), .CK(clk), .RN(
n5171), .Q(Op_MX[7]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n557), .CK(clk), .RN(
n5173), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n558), .CK(clk), .RN(
n5164), .Q(Op_MX[19]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n566), .CK(clk), .RN(
n702), .Q(Op_MX[27]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n567), .CK(clk), .RN(
n5174), .Q(Op_MX[28]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n578), .CK(clk), .RN(
n882), .Q(Op_MX[39]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n579), .CK(clk), .RN(
n882), .Q(Op_MX[40]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_25_ ( .D(Sgf_operation_n84), .CK(clk),
.RN(n5159), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_46_ ( .D(Sgf_operation_n63), .CK(clk),
.RN(n5155), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_49_ ( .D(Sgf_operation_n60), .CK(clk),
.RN(n5153), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_28_ ( .D(Sgf_operation_n81), .CK(clk),
.RN(n5157), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_30_ ( .D(Sgf_operation_n79), .CK(clk),
.RN(n5157), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_104_ ( .D(Sgf_operation_n5), .CK(clk),
.RN(n5157), .Q(P_Sgf[104]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_3_ ( .D(Sgf_operation_n106), .CK(clk),
.RN(n5158), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_7_ ( .D(Sgf_operation_n102), .CK(clk),
.RN(n5154), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_8_ ( .D(Sgf_operation_n101), .CK(clk),
.RN(n5158), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_16_ ( .D(Sgf_operation_n93), .CK(clk),
.RN(n5160), .Q(P_Sgf[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n478), .CK(clk), .RN(
n5162), .Q(Op_MY[3]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n492), .CK(clk), .RN(
n5165), .Q(Op_MY[17]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n489), .CK(clk), .RN(
n5168), .Q(Op_MY[14]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n517), .CK(clk), .RN(
n5178), .Q(Op_MY[42]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n516), .CK(clk), .RN(
n5174), .Q(Op_MY[41]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n508), .CK(clk), .RN(
n5179), .Q(Op_MY[33]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n494), .CK(clk), .RN(
n5180), .Q(Op_MY[19]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n486), .CK(clk), .RN(
n5165), .Q(Op_MY[11]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n522), .CK(clk), .RN(
n701), .Q(Op_MY[47]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n506), .CK(clk), .RN(
n5170), .Q(Op_MY[31]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n504), .CK(clk), .RN(
n702), .Q(Op_MY[29]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n499), .CK(clk), .RN(
n5178), .Q(Op_MY[24]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n496), .CK(clk), .RN(
n5174), .Q(Op_MY[21]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n490), .CK(clk), .RN(
n5176), .Q(Op_MY[15]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n488), .CK(clk), .RN(
n5168), .Q(Op_MY[13]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n485), .CK(clk), .RN(
n5161), .Q(Op_MY[10]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n482), .CK(clk), .RN(
n5161), .Q(Op_MY[7]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n513), .CK(clk), .RN(
n5170), .Q(Op_MY[38]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n509), .CK(clk), .RN(
n701), .Q(Op_MY[34]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n503), .CK(clk), .RN(
n5179), .Q(Op_MY[28]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n495), .CK(clk), .RN(
n702), .Q(Op_MY[20]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n487), .CK(clk), .RN(
n5176), .Q(Op_MY[12]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n481), .CK(clk), .RN(
n5162), .Q(Op_MY[6]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n518), .CK(clk), .RN(
n702), .Q(Op_MY[43]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n575), .CK(clk), .RN(
n701), .Q(Op_MX[36]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n560), .CK(clk), .RN(
n5164), .Q(Op_MX[21]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n554), .CK(clk), .RN(
n5175), .Q(Op_MX[15]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n542), .CK(clk), .RN(
n5172), .Q(Op_MX[3]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n573), .CK(clk), .RN(
n5179), .Q(Op_MX[34]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n552), .CK(clk), .RN(
n5176), .Q(Op_MX[13]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n534), .CK(clk), .RN(
n5170), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n529), .CK(clk), .RN(
n5167), .Q(Op_MY[54]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n475), .CK(clk), .RN(
n5162), .Q(Op_MY[0]), .QN(n5075) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n581), .CK(clk), .RN(
n5179), .Q(Op_MX[42]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n587), .CK(clk), .RN(
n5162), .Q(Op_MX[48]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n582), .CK(clk), .RN(
n883), .Q(Op_MX[43]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_24_ ( .D(Sgf_operation_n85), .CK(clk),
.RN(n5153), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_44_ ( .D(Sgf_operation_n65), .CK(clk),
.RN(n5154), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_42_ ( .D(Sgf_operation_n67), .CK(clk),
.RN(n5160), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_37_ ( .D(Sgf_operation_n72), .CK(clk),
.RN(n5156), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_26_ ( .D(Sgf_operation_n83), .CK(clk),
.RN(n5154), .Q(P_Sgf[26]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n551), .CK(clk), .RN(
n5168), .Q(Op_MX[12]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_51_ ( .D(Sgf_operation_n58), .CK(clk),
.RN(n5157), .Q(P_Sgf[51]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_48_ ( .D(Sgf_operation_n61), .CK(clk),
.RN(n5154), .Q(P_Sgf[48]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_40_ ( .D(Sgf_operation_n69), .CK(clk),
.RN(n5160), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_38_ ( .D(Sgf_operation_n71), .CK(clk),
.RN(n5155), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_27_ ( .D(Sgf_operation_n82), .CK(clk),
.RN(n5158), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_50_ ( .D(Sgf_operation_n59), .CK(clk),
.RN(n5156), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_41_ ( .D(Sgf_operation_n68), .CK(clk),
.RN(n5160), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_36_ ( .D(Sgf_operation_n73), .CK(clk),
.RN(n5155), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_52_ ( .D(Sgf_operation_n57), .CK(clk),
.RN(n5154), .Q(P_Sgf[52]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_39_ ( .D(Sgf_operation_n70), .CK(clk),
.RN(n5155), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_29_ ( .D(Sgf_operation_n80), .CK(clk),
.RN(n5159), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_34_ ( .D(Sgf_operation_n75), .CK(clk),
.RN(n5155), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_32_ ( .D(Sgf_operation_n77), .CK(clk),
.RN(n5156), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_18_ ( .D(Sgf_operation_n91), .CK(clk),
.RN(n5158), .Q(P_Sgf[18]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n538), .CK(clk), .RN(
n5180), .Q(Op_MX[63]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_35_ ( .D(Sgf_operation_n74), .CK(clk),
.RN(n5153), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_33_ ( .D(Sgf_operation_n76), .CK(clk),
.RN(n5154), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_21_ ( .D(Sgf_operation_n88), .CK(clk),
.RN(n5159), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_13_ ( .D(Sgf_operation_n96), .CK(clk),
.RN(n5153), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_12_ ( .D(Sgf_operation_n97), .CK(clk),
.RN(n5158), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_5_ ( .D(Sgf_operation_n104), .CK(clk),
.RN(n5157), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_1_ ( .D(Sgf_operation_n108), .CK(clk),
.RN(n5157), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_22_ ( .D(Sgf_operation_n87), .CK(clk),
.RN(n5157), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_17_ ( .D(Sgf_operation_n92), .CK(clk),
.RN(n5160), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_15_ ( .D(Sgf_operation_n94), .CK(clk),
.RN(n5153), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_10_ ( .D(Sgf_operation_n99), .CK(clk),
.RN(n5153), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_9_ ( .D(Sgf_operation_n100), .CK(clk),
.RN(n5158), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_2_ ( .D(Sgf_operation_n107), .CK(clk),
.RN(n5159), .Q(P_Sgf[2]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n549), .CK(clk), .RN(
n5171), .Q(Op_MX[10]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n588), .CK(clk), .RN(
n881), .Q(Op_MX[49]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_43_ ( .D(Sgf_operation_n66), .CK(clk),
.RN(n5156), .Q(P_Sgf[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n354), .CK(clk),
.RN(n5167), .Q(Sgf_normalized_result[2]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n525), .CK(clk), .RN(
n882), .Q(Op_MY[50]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n541), .CK(clk), .RN(
n5171), .Q(Op_MX[2]), .QN(n5076) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n5173), .Q(FSM_selector_A),
.QN(n5095) );
OAI32X4TS U640 ( .A0(n5181), .A1(FS_Module_state_reg[3]), .A2(n5072), .B0(
n3056), .B1(n5181), .Y(n4954) );
ADDHXLTS U641 ( .A(Sgf_normalized_result[38]), .B(n5027), .CO(n5029), .S(
n5026) );
ADDHXLTS U642 ( .A(Sgf_normalized_result[37]), .B(n5025), .CO(n5027), .S(
n5024) );
ADDHXLTS U643 ( .A(Sgf_normalized_result[36]), .B(n5023), .CO(n5025), .S(
n5022) );
ADDHXLTS U644 ( .A(Sgf_normalized_result[35]), .B(n5021), .CO(n5023), .S(
n5020) );
ADDHXLTS U645 ( .A(Sgf_normalized_result[34]), .B(n5019), .CO(n5021), .S(
n5018) );
ADDHXLTS U646 ( .A(Sgf_normalized_result[33]), .B(n5017), .CO(n5019), .S(
n5016) );
ADDHXLTS U647 ( .A(Sgf_normalized_result[31]), .B(n5013), .CO(n5015), .S(
n5012) );
ADDHXLTS U648 ( .A(Sgf_normalized_result[30]), .B(n5011), .CO(n5013), .S(
n5010) );
ADDHXLTS U649 ( .A(Sgf_normalized_result[29]), .B(n5009), .CO(n5011), .S(
n5008) );
ADDHXLTS U650 ( .A(Sgf_normalized_result[28]), .B(n5007), .CO(n5009), .S(
n5006) );
ADDHXLTS U651 ( .A(Sgf_normalized_result[27]), .B(n5005), .CO(n5007), .S(
n5004) );
ADDHXLTS U652 ( .A(Sgf_normalized_result[26]), .B(n5003), .CO(n5005), .S(
n5002) );
NAND2X1TS U653 ( .A(Sgf_operation_mult_x_1_n1515), .B(
Sgf_operation_mult_x_1_n1527), .Y(n4673) );
ADDHXLTS U654 ( .A(Sgf_normalized_result[25]), .B(n5001), .CO(n5003), .S(
n5000) );
AOI21X1TS U655 ( .A0(n4679), .A1(n4683), .B0(n4265), .Y(n4670) );
ADDHXLTS U656 ( .A(Sgf_normalized_result[24]), .B(n4999), .CO(n5001), .S(
n4998) );
ADDHXLTS U657 ( .A(Sgf_normalized_result[23]), .B(n4997), .CO(n4999), .S(
n4996) );
ADDHXLTS U658 ( .A(Sgf_normalized_result[22]), .B(n4995), .CO(n4997), .S(
n4994) );
ADDHXLTS U659 ( .A(Sgf_normalized_result[14]), .B(n4978), .CO(n4980), .S(
n4977) );
CLKINVX6TS U660 ( .A(n986), .Y(n2945) );
CLKINVX6TS U661 ( .A(n1022), .Y(n3909) );
CMPR32X2TS U662 ( .A(n4113), .B(n4112), .C(n4111), .CO(n4179), .S(n4178) );
CLKINVX6TS U663 ( .A(n4057), .Y(n956) );
AOI222X1TS U664 ( .A0(n3595), .A1(n4126), .B0(n3616), .B1(n4125), .C0(n3615),
.C1(n4124), .Y(n3357) );
AOI222X1TS U665 ( .A0(n3732), .A1(n4126), .B0(n3743), .B1(n4125), .C0(n3742),
.C1(n4124), .Y(n3075) );
BUFX4TS U666 ( .A(n934), .Y(n4057) );
INVX4TS U667 ( .A(n1379), .Y(n4086) );
AOI222X1TS U668 ( .A0(n3773), .A1(n4126), .B0(n3779), .B1(n4125), .C0(n3764),
.C1(n4124), .Y(n3417) );
BUFX3TS U669 ( .A(n901), .Y(n1724) );
AOI222X1TS U670 ( .A0(n3850), .A1(n4126), .B0(n4035), .B1(n4125), .C0(n4034),
.C1(n4124), .Y(n4037) );
AOI222X1TS U671 ( .A0(n3788), .A1(n4126), .B0(n3810), .B1(n4125), .C0(n3803),
.C1(n4124), .Y(n3157) );
BUFX3TS U672 ( .A(n3203), .Y(n3300) );
INVX2TS U673 ( .A(n900), .Y(n2007) );
CLKINVX6TS U674 ( .A(n1128), .Y(n4062) );
CLKBUFX2TS U675 ( .A(n5094), .Y(n1128) );
OR2X1TS U676 ( .A(n3008), .B(n3020), .Y(n1491) );
NOR2XLTS U677 ( .A(n2147), .B(n889), .Y(n890) );
NOR2XLTS U678 ( .A(n1289), .B(n788), .Y(n789) );
OAI21XLTS U679 ( .A0(n2007), .A1(n867), .B0(n1808), .Y(n871) );
OAI21XLTS U680 ( .A0(n892), .A1(n891), .B0(n890), .Y(n893) );
OAI21XLTS U681 ( .A0(n1587), .A1(n1374), .B0(n1584), .Y(n1378) );
OAI21XLTS U682 ( .A0(n1045), .A1(n1044), .B0(n1043), .Y(n1046) );
OAI21XLTS U683 ( .A0(n3949), .A1(n3798), .B0(n2505), .Y(n2506) );
OAI21XLTS U684 ( .A0(n3949), .A1(n3745), .B0(n2765), .Y(n2766) );
OAI21XLTS U685 ( .A0(n630), .A1(n3829), .B0(n3816), .Y(n3817) );
OAI21XLTS U686 ( .A0(n3949), .A1(n3675), .B0(n2063), .Y(n2064) );
OAI21XLTS U687 ( .A0(n4120), .A1(n3531), .B0(n1296), .Y(n1298) );
OAI21XLTS U688 ( .A0(n3232), .A1(n3798), .B0(n1802), .Y(n1803) );
OAI21XLTS U689 ( .A0(n2945), .A1(n2796), .B0(n2263), .Y(n2264) );
OAI21XLTS U690 ( .A0(n642), .A1(n3556), .B0(n1696), .Y(n1697) );
OAI21XLTS U691 ( .A0(n3969), .A1(n3580), .B0(n1863), .Y(n1864) );
OAI21XLTS U692 ( .A0(n3232), .A1(n3675), .B0(n1966), .Y(n1967) );
OAI21XLTS U693 ( .A0(n2973), .A1(n3661), .B0(n1906), .Y(n1907) );
OAI21XLTS U694 ( .A0(n642), .A1(n3475), .B0(n1656), .Y(n1657) );
OAI21XLTS U695 ( .A0(n3940), .A1(n3576), .B0(n2456), .Y(n2457) );
OAI21XLTS U696 ( .A0(n3949), .A1(n3544), .B0(n2251), .Y(n2252) );
OAI21XLTS U697 ( .A0(n4046), .A1(n3813), .B0(n2352), .Y(n2353) );
OAI21XLTS U698 ( .A0(n956), .A1(n3829), .B0(n2599), .Y(n2600) );
OAI21XLTS U699 ( .A0(n956), .A1(n3798), .B0(n2686), .Y(n2687) );
OAI21XLTS U700 ( .A0(n2973), .A1(n3592), .B0(n2119), .Y(n2120) );
OAI21XLTS U701 ( .A0(n2692), .A1(n4060), .B0(n2805), .Y(n2806) );
OAI21XLTS U702 ( .A0(n633), .A1(n3487), .B0(n3486), .Y(n3488) );
OR2X1TS U703 ( .A(n2956), .B(n2950), .Y(n1138) );
OR2X1TS U704 ( .A(n3199), .B(n3184), .Y(n1052) );
OAI21XLTS U705 ( .A0(n2967), .A1(n4169), .B0(n1960), .Y(n1961) );
OAI21XLTS U706 ( .A0(n639), .A1(n3833), .B0(n2366), .Y(n2367) );
OAI21XLTS U707 ( .A0(n639), .A1(n4038), .B0(n2202), .Y(n2203) );
OAI21XLTS U708 ( .A0(n2952), .A1(n2796), .B0(n1556), .Y(n1557) );
OAI21XLTS U709 ( .A0(n625), .A1(n3745), .B0(n1633), .Y(n1634) );
OAI21XLTS U710 ( .A0(n627), .A1(n3766), .B0(n1994), .Y(n1995) );
OAI21XLTS U711 ( .A0(n628), .A1(n3691), .B0(n2714), .Y(n2715) );
OAI21XLTS U712 ( .A0(n3909), .A1(n3640), .B0(n1791), .Y(n1792) );
OR2X1TS U713 ( .A(n2942), .B(n3233), .Y(n990) );
OAI21XLTS U714 ( .A0(n628), .A1(n1484), .B0(n1355), .Y(n1356) );
OAI21XLTS U715 ( .A0(n4421), .A1(n4417), .B0(n4422), .Y(n4233) );
OAI21XLTS U716 ( .A0(n4411), .A1(n4455), .B0(n4412), .Y(n4229) );
OAI21XLTS U717 ( .A0(n4747), .A1(n4252), .B0(n4251), .Y(n4253) );
OAI21XLTS U718 ( .A0(n2952), .A1(n3556), .B0(n1253), .Y(n1254) );
OAI21XLTS U719 ( .A0(n628), .A1(n3215), .B0(n1238), .Y(n1239) );
OAI21XLTS U720 ( .A0(n3925), .A1(n4060), .B0(n1093), .Y(n1094) );
OAI21XLTS U721 ( .A0(n956), .A1(n1174), .B0(n1436), .Y(n1074) );
OAI21XLTS U722 ( .A0(n4322), .A1(n4328), .B0(n4323), .Y(n4217) );
OAI21XLTS U723 ( .A0(n628), .A1(n3192), .B0(n1087), .Y(n1088) );
AOI21X1TS U724 ( .A0(n4240), .A1(n4303), .B0(n4239), .Y(n4743) );
OR2X1TS U725 ( .A(Sgf_operation_mult_x_1_n1588), .B(
Sgf_operation_mult_x_1_n1604), .Y(n4715) );
OAI21XLTS U726 ( .A0(n4395), .A1(n4391), .B0(n4392), .Y(n4355) );
OAI21XLTS U727 ( .A0(n4597), .A1(n4593), .B0(n4594), .Y(n4591) );
OAI21XLTS U728 ( .A0(n4741), .A1(n4681), .B0(n4680), .Y(n4685) );
OAI21XLTS U729 ( .A0(n4848), .A1(n4844), .B0(n4845), .Y(n4842) );
OAI21XLTS U730 ( .A0(n4821), .A1(n4817), .B0(n4818), .Y(n4815) );
OAI21XLTS U731 ( .A0(n4741), .A1(n4732), .B0(n4738), .Y(n4736) );
ADDHXLTS U732 ( .A(Sgf_normalized_result[13]), .B(n4976), .CO(n4978), .S(
n4975) );
ADDHXLTS U733 ( .A(Sgf_normalized_result[32]), .B(n5015), .CO(n5017), .S(
n5014) );
ADDHXLTS U734 ( .A(Sgf_normalized_result[52]), .B(n5059), .CO(n5061), .S(
n5057) );
ADDHX1TS U735 ( .A(Sgf_normalized_result[44]), .B(n5039), .CO(n5041), .S(
n5038) );
CLKMX2X2TS U736 ( .A(P_Sgf[89]), .B(n4650), .S0(n4652), .Y(Sgf_operation_n20) );
ADDHX1TS U737 ( .A(Sgf_normalized_result[43]), .B(n5037), .CO(n5039), .S(
n5036) );
CLKMX2X2TS U738 ( .A(n746), .B(n4653), .S0(n4895), .Y(Sgf_operation_n21) );
CLKMX2X2TS U739 ( .A(P_Sgf[87]), .B(n4655), .S0(n4895), .Y(Sgf_operation_n22) );
AO22XLTS U740 ( .A0(n5060), .A1(Add_result[40]), .B0(n703), .B1(n5030), .Y(
n432) );
CLKMX2X2TS U741 ( .A(n745), .B(n4658), .S0(n4875), .Y(Sgf_operation_n23) );
CLKMX2X2TS U742 ( .A(n734), .B(n4757), .S0(n4645), .Y(Sgf_operation_n39) );
CLKMX2X2TS U743 ( .A(P_Sgf[69]), .B(n4763), .S0(n4895), .Y(Sgf_operation_n40) );
CLKMX2X2TS U744 ( .A(n744), .B(n4660), .S0(n4875), .Y(Sgf_operation_n24) );
CLKMX2X2TS U745 ( .A(n733), .B(n4770), .S0(n4776), .Y(Sgf_operation_n41) );
AOI21X2TS U746 ( .A0(n4669), .A1(n4267), .B0(n4266), .Y(n4667) );
INVX1TS U747 ( .A(n4695), .Y(n4698) );
OAI21X1TS U748 ( .A0(n4575), .A1(n4566), .B0(n4565), .Y(n4571) );
OAI21X1TS U749 ( .A0(n4575), .A1(n4574), .B0(n4573), .Y(n4579) );
INVX1TS U750 ( .A(n4689), .Y(n4691) );
NAND2XLTS U751 ( .A(n4674), .B(n4673), .Y(n4675) );
OR2X2TS U752 ( .A(Sgf_operation_mult_x_1_n1574), .B(
Sgf_operation_mult_x_1_n1587), .Y(n4710) );
NAND2XLTS U753 ( .A(n4683), .B(n4682), .Y(n4684) );
OR2X2TS U754 ( .A(Sgf_operation_mult_x_1_n1638), .B(
Sgf_operation_mult_x_1_n1656), .Y(n4734) );
OR2X2TS U755 ( .A(Sgf_operation_mult_x_1_n1605), .B(
Sgf_operation_mult_x_1_n1620), .Y(n4723) );
OR2X2TS U756 ( .A(Sgf_operation_mult_x_1_n1621), .B(
Sgf_operation_mult_x_1_n1637), .Y(n4728) );
NOR2X1TS U757 ( .A(n4566), .B(n4567), .Y(n4202) );
OAI21X1TS U758 ( .A0(n635), .A1(n3544), .B0(n2550), .Y(n2551) );
OAI21X1TS U759 ( .A0(n629), .A1(n3514), .B0(n2440), .Y(n2441) );
OAI21X1TS U760 ( .A0(n956), .A1(n3725), .B0(n2760), .Y(n2762) );
OAI21X1TS U761 ( .A0(n626), .A1(n2665), .B0(n1325), .Y(n1326) );
OAI21X1TS U762 ( .A0(n630), .A1(n3592), .B0(n3559), .Y(n3560) );
OAI21X1TS U763 ( .A0(n626), .A1(n3640), .B0(n2047), .Y(n2048) );
OAI21X1TS U764 ( .A0(n627), .A1(n3691), .B0(n2740), .Y(n2741) );
OAI21X1TS U765 ( .A0(n956), .A1(n3752), .B0(n2792), .Y(n2793) );
OAI21X1TS U766 ( .A0(n634), .A1(n3544), .B0(n1453), .Y(n1454) );
OAI21X1TS U767 ( .A0(n632), .A1(n2757), .B0(n1366), .Y(n1367) );
OAI21X1TS U768 ( .A0(n630), .A1(n3661), .B0(n3644), .Y(n3645) );
OAI21X1TS U769 ( .A0(n627), .A1(n1984), .B0(n1520), .Y(n1521) );
OAI21X1TS U770 ( .A0(n633), .A1(n3544), .B0(n3543), .Y(n3545) );
OAI21X1TS U771 ( .A0(n625), .A1(n2665), .B0(n1446), .Y(n1447) );
OAI21X1TS U772 ( .A0(n625), .A1(n2757), .B0(n2509), .Y(n2510) );
OAI21X1TS U773 ( .A0(n956), .A1(n3766), .B0(n2790), .Y(n2791) );
OAI21X1TS U774 ( .A0(n632), .A1(n3691), .B0(n2632), .Y(n2633) );
OAI21X1TS U775 ( .A0(n626), .A1(n3140), .B0(n2463), .Y(n2464) );
OAI21X1TS U776 ( .A0(n630), .A1(n3628), .B0(n2521), .Y(n2522) );
OAI21X1TS U777 ( .A0(n631), .A1(n3514), .B0(n3511), .Y(n3512) );
OAI21X1TS U778 ( .A0(n629), .A1(n3487), .B0(n3484), .Y(n3485) );
OAI21X1TS U779 ( .A0(n634), .A1(n3619), .B0(n2564), .Y(n2565) );
OAI21X1TS U780 ( .A0(n635), .A1(n3514), .B0(n2221), .Y(n2222) );
OAI21X1TS U781 ( .A0(n625), .A1(n3679), .B0(n2460), .Y(n2461) );
OAI21X1TS U782 ( .A0(n632), .A1(n2734), .B0(n2733), .Y(n2735) );
OAI21X1TS U783 ( .A0(n630), .A1(n3619), .B0(n3596), .Y(n3597) );
OAI21X1TS U784 ( .A0(n631), .A1(n3607), .B0(n2311), .Y(n2312) );
OAI21X1TS U785 ( .A0(n628), .A1(n3706), .B0(n2625), .Y(n2626) );
OAI21X1TS U786 ( .A0(n627), .A1(n3715), .B0(n2753), .Y(n2754) );
OAI21X1TS U787 ( .A0(n634), .A1(n3592), .B0(n3562), .Y(n3563) );
OAI21X1TS U788 ( .A0(n628), .A1(n3661), .B0(n2696), .Y(n2697) );
OAI21X1TS U789 ( .A0(n629), .A1(n3628), .B0(n2239), .Y(n2240) );
OAI21X1TS U790 ( .A0(n632), .A1(n1484), .B0(n1264), .Y(n1265) );
OAI21X1TS U791 ( .A0(n627), .A1(n1070), .B0(n1010), .Y(n1011) );
OAI21X1TS U792 ( .A0(n628), .A1(n4056), .B0(n996), .Y(n997) );
OAI21X1TS U793 ( .A0(n626), .A1(n3576), .B0(n1255), .Y(n1256) );
OAI21X1TS U794 ( .A0(n630), .A1(n3514), .B0(n3506), .Y(n3507) );
OAI21X1TS U795 ( .A0(n956), .A1(n3864), .B0(n2702), .Y(n2703) );
OAI21X1TS U796 ( .A0(n632), .A1(n3833), .B0(n2637), .Y(n2638) );
OAI21X1TS U797 ( .A0(n635), .A1(n3661), .B0(n2231), .Y(n2232) );
OAI21X1TS U798 ( .A0(n628), .A1(n2665), .B0(n1259), .Y(n1260) );
OAI21X1TS U799 ( .A0(n631), .A1(n3487), .B0(n3480), .Y(n3481) );
OAI21X1TS U800 ( .A0(n631), .A1(n3628), .B0(n1485), .Y(n1487) );
OAI21X1TS U801 ( .A0(n2952), .A1(n3679), .B0(n1861), .Y(n1862) );
OAI21X1TS U802 ( .A0(n627), .A1(n1484), .B0(n1329), .Y(n1330) );
OAI21X1TS U803 ( .A0(n634), .A1(n3514), .B0(n3509), .Y(n3510) );
OAI21X1TS U804 ( .A0(n626), .A1(n3745), .B0(n1745), .Y(n1746) );
OAI21X1TS U805 ( .A0(n628), .A1(n1174), .B0(n1172), .Y(n1173) );
OAI21X1TS U806 ( .A0(n627), .A1(n3215), .B0(n1183), .Y(n1184) );
OAI21X1TS U807 ( .A0(n625), .A1(n3514), .B0(n1170), .Y(n1171) );
OAI21X1TS U808 ( .A0(n626), .A1(n3514), .B0(n1130), .Y(n1131) );
OAI21X1TS U809 ( .A0(n634), .A1(n3475), .B0(n3456), .Y(n3457) );
OAI21X1TS U810 ( .A0(n632), .A1(n3215), .B0(n1149), .Y(n1150) );
OAI21X1TS U811 ( .A0(n630), .A1(n3281), .B0(n1141), .Y(n1142) );
OAI21X1TS U812 ( .A0(n635), .A1(n3628), .B0(n3625), .Y(n3626) );
OAI21X1TS U813 ( .A0(n626), .A1(n3337), .B0(n1179), .Y(n1180) );
OAI21X1TS U814 ( .A0(n632), .A1(n2649), .B0(n2571), .Y(n2572) );
OAI21X1TS U815 ( .A0(n627), .A1(n1174), .B0(n1132), .Y(n1133) );
OAI21X1TS U816 ( .A0(n625), .A1(n3503), .B0(n1114), .Y(n1115) );
OAI21X1TS U817 ( .A0(n630), .A1(n3487), .B0(n3478), .Y(n3479) );
OAI21X1TS U818 ( .A0(n632), .A1(n2665), .B0(n1188), .Y(n1189) );
OAI21X1TS U819 ( .A0(n626), .A1(n3317), .B0(n1040), .Y(n1041) );
OAI21X1TS U820 ( .A0(n632), .A1(n3544), .B0(n1083), .Y(n1084) );
OAI21X1TS U821 ( .A0(n631), .A1(n3475), .B0(n3458), .Y(n3459) );
OAI21X1TS U822 ( .A0(n627), .A1(n1611), .B0(n1257), .Y(n1258) );
OAI21X1TS U823 ( .A0(n634), .A1(n3487), .B0(n1236), .Y(n1237) );
OAI21X1TS U824 ( .A0(n625), .A1(n3556), .B0(n1226), .Y(n1227) );
OAI21X1TS U825 ( .A0(n627), .A1(n3192), .B0(n1066), .Y(n1067) );
OAI21X1TS U826 ( .A0(n625), .A1(n4060), .B0(n1055), .Y(n1056) );
OAI21X1TS U827 ( .A0(n628), .A1(n1070), .B0(n1069), .Y(n1071) );
OAI21X1TS U828 ( .A0(n626), .A1(n4060), .B0(n1007), .Y(n1008) );
OAI21X1TS U829 ( .A0(n632), .A1(n3192), .B0(n1016), .Y(n1017) );
OAI21X1TS U830 ( .A0(n635), .A1(n3475), .B0(n3460), .Y(n3461) );
OAI21X1TS U831 ( .A0(n627), .A1(n2649), .B0(n2648), .Y(n2650) );
OAI21X1TS U832 ( .A0(n634), .A1(n3675), .B0(n3666), .Y(n3667) );
OAI21X1TS U833 ( .A0(n630), .A1(n3544), .B0(n3536), .Y(n3537) );
OAI21X1TS U834 ( .A0(n629), .A1(n3675), .B0(n3672), .Y(n3673) );
OAI21X1TS U835 ( .A0(n626), .A1(n3702), .B0(n1689), .Y(n1690) );
OAI21X1TS U836 ( .A0(n956), .A1(n3955), .B0(n2670), .Y(n2671) );
OAI21X1TS U837 ( .A0(n635), .A1(n3487), .B0(n3482), .Y(n3483) );
OAI21X1TS U838 ( .A0(n635), .A1(n3607), .B0(n1650), .Y(n1651) );
OAI21X1TS U839 ( .A0(n629), .A1(n4060), .B0(n3462), .Y(n3463) );
OAI21X1TS U840 ( .A0(n625), .A1(n3576), .B0(n1276), .Y(n1277) );
OAI21X1TS U841 ( .A0(n956), .A1(n4096), .B0(n2651), .Y(n2652) );
OAI21X1TS U842 ( .A0(n633), .A1(n4060), .B0(n3466), .Y(n3467) );
OAI21X1TS U843 ( .A0(n3232), .A1(n3619), .B0(n1683), .Y(n1684) );
OAI21X1TS U844 ( .A0(n3909), .A1(n3702), .B0(n1591), .Y(n1592) );
OAI21X1TS U845 ( .A0(n2973), .A1(n3619), .B0(n1839), .Y(n1840) );
OAI21X1TS U846 ( .A0(n3232), .A1(n2757), .B0(n2049), .Y(n2050) );
OAI21X1TS U847 ( .A0(n2973), .A1(n3675), .B0(n1694), .Y(n1695) );
OAI21X1TS U848 ( .A0(n2945), .A1(n3675), .B0(n2655), .Y(n2656) );
OAI21X1TS U849 ( .A0(n3232), .A1(n3725), .B0(n1902), .Y(n1903) );
OAI21X1TS U850 ( .A0(n3870), .A1(n3640), .B0(n2155), .Y(n2156) );
CLKINVX6TS U851 ( .A(n1102), .Y(n2952) );
OAI21X1TS U852 ( .A0(n3870), .A1(n3475), .B0(n3469), .Y(n3470) );
OAI21X1TS U853 ( .A0(n2945), .A1(n2757), .B0(n2525), .Y(n2526) );
OAI21X1TS U854 ( .A0(n2692), .A1(n3544), .B0(n1933), .Y(n1934) );
OAI21X1TS U855 ( .A0(n3909), .A1(n3691), .B0(n2356), .Y(n2357) );
OAI21X1TS U856 ( .A0(n3232), .A1(n3514), .B0(n2362), .Y(n2363) );
OAI21X1TS U857 ( .A0(n3909), .A1(n3745), .B0(n1892), .Y(n1893) );
OAI21X1TS U858 ( .A0(n636), .A1(n3487), .B0(n2483), .Y(n2484) );
OAI21X1TS U859 ( .A0(n3249), .A1(n3531), .B0(n2720), .Y(n2721) );
OAI21X1TS U860 ( .A0(n3949), .A1(n4060), .B0(n854), .Y(n855) );
OAI21X1TS U861 ( .A0(n3969), .A1(n3210), .B0(n2225), .Y(n2226) );
OAI21X1TS U862 ( .A0(n3249), .A1(n3619), .B0(n2267), .Y(n2268) );
OAI21X1TS U863 ( .A0(n3960), .A1(n3337), .B0(n1904), .Y(n1905) );
OAI21X1TS U864 ( .A0(n3249), .A1(n3475), .B0(n2601), .Y(n2602) );
CLKINVX6TS U865 ( .A(n1834), .Y(n2692) );
OAI21X1TS U866 ( .A0(n3949), .A1(n3487), .B0(n2749), .Y(n2750) );
OAI21X1TS U867 ( .A0(n3940), .A1(n3531), .B0(n3274), .Y(n3275) );
INVX4TS U868 ( .A(n1727), .Y(n3266) );
INVX4TS U869 ( .A(n2154), .Y(n3870) );
OAI21X1TS U870 ( .A0(n3988), .A1(n3210), .B0(n1783), .Y(n1784) );
INVX4TS U871 ( .A(n1419), .Y(n3662) );
INVX4TS U872 ( .A(n1294), .Y(n4120) );
OAI21X1TS U873 ( .A0(n1349), .A1(n806), .B0(n805), .Y(n900) );
OAI21XLTS U874 ( .A0(n645), .A1(n3122), .B0(n3121), .Y(n3123) );
OAI21X1TS U875 ( .A0(n829), .A1(n886), .B0(n892), .Y(n830) );
OAI21XLTS U876 ( .A0(n645), .A1(n4038), .B0(n4037), .Y(n4040) );
CLKINVX6TS U877 ( .A(n4954), .Y(n2822) );
INVX4TS U878 ( .A(n5069), .Y(n5063) );
OR2X2TS U879 ( .A(n3229), .B(n3888), .Y(n1214) );
OR2X2TS U880 ( .A(n3893), .B(n2981), .Y(n2975) );
OR2X2TS U881 ( .A(n2962), .B(n3787), .Y(n1481) );
OR2X2TS U882 ( .A(n2981), .B(n3857), .Y(n2978) );
OR2X2TS U883 ( .A(n2946), .B(n2942), .Y(n1004) );
OR2X2TS U884 ( .A(n3222), .B(n3848), .Y(n1232) );
OR2X2TS U885 ( .A(n2968), .B(n3883), .Y(n1647) );
OR2X2TS U886 ( .A(n2954), .B(n3201), .Y(n1099) );
OR2X2TS U887 ( .A(n3262), .B(n3893), .Y(n2151) );
OR2X2TS U888 ( .A(n3233), .B(n4072), .Y(n993) );
OR2X2TS U889 ( .A(n3024), .B(n3272), .Y(n1828) );
OR2X2TS U890 ( .A(n3015), .B(n3899), .Y(n1773) );
OR2X2TS U891 ( .A(n3872), .B(n3247), .Y(n2278) );
OR2X2TS U892 ( .A(n3247), .B(n3866), .Y(n2281) );
OR2X2TS U893 ( .A(n3866), .B(n3262), .Y(n2148) );
BUFX6TS U894 ( .A(n5075), .Y(n4137) );
CLKMX2X2TS U895 ( .A(P_Sgf[105]), .B(n4273), .S0(n4892), .Y(Sgf_operation_n4) );
CLKMX2X2TS U896 ( .A(P_Sgf[104]), .B(n4614), .S0(n4776), .Y(Sgf_operation_n5) );
CLKMX2X2TS U897 ( .A(n719), .B(n4618), .S0(n4652), .Y(Sgf_operation_n6) );
AFHCINX2TS U898 ( .CIN(n4615), .B(n4616), .A(n4617), .S(n4618), .CO(n4611)
);
CLKMX2X2TS U899 ( .A(P_Sgf[102]), .B(n4622), .S0(n4652), .Y(Sgf_operation_n7) );
CLKMX2X2TS U900 ( .A(n753), .B(n4625), .S0(n4645), .Y(Sgf_operation_n8) );
AFHCONX2TS U901 ( .A(n4621), .B(n4620), .CI(n4619), .CON(n4615), .S(n4622)
);
CLKMX2X2TS U902 ( .A(n752), .B(n4627), .S0(n4776), .Y(Sgf_operation_n9) );
AFHCINX2TS U903 ( .CIN(n4623), .B(Sgf_operation_mult_x_1_n1341), .A(n4624),
.S(n4625), .CO(n4619) );
AO22X1TS U904 ( .A0(n5062), .A1(n5061), .B0(n5060), .B1(n707), .Y(n419) );
CLKMX2X2TS U905 ( .A(P_Sgf[99]), .B(n4629), .S0(n4895), .Y(Sgf_operation_n10) );
AFHCONX2TS U906 ( .A(Sgf_operation_mult_x_1_n1344), .B(
Sgf_operation_mult_x_1_n1342), .CI(n4626), .CON(n4623), .S(n4627) );
AFHCINX2TS U907 ( .CIN(n4628), .B(Sgf_operation_mult_x_1_n1349), .A(
Sgf_operation_mult_x_1_n1345), .S(n4629), .CO(n4626) );
CLKMX2X2TS U908 ( .A(n751), .B(n4631), .S0(n4895), .Y(Sgf_operation_n11) );
AO22X1TS U909 ( .A0(n5055), .A1(n5054), .B0(n5053), .B1(n716), .Y(n421) );
AO22X1TS U910 ( .A0(n5051), .A1(Add_result[50]), .B0(n703), .B1(n5050), .Y(
n422) );
CLKMX2X2TS U911 ( .A(P_Sgf[97]), .B(n4633), .S0(n4645), .Y(Sgf_operation_n12) );
ADDHXLTS U912 ( .A(Sgf_normalized_result[51]), .B(n5056), .CO(n5059), .S(
n5054) );
CLKMX2X2TS U913 ( .A(n750), .B(n4635), .S0(n4652), .Y(Sgf_operation_n13) );
AO22X1TS U914 ( .A0(n5051), .A1(Add_result[49]), .B0(n703), .B1(n5048), .Y(
n423) );
AO22X1TS U915 ( .A0(n5051), .A1(Add_result[48]), .B0(n703), .B1(n5046), .Y(
n424) );
CLKMX2X2TS U916 ( .A(P_Sgf[95]), .B(n4637), .S0(n4776), .Y(Sgf_operation_n14) );
CLKMX2X2TS U917 ( .A(n749), .B(n4639), .S0(n4645), .Y(Sgf_operation_n15) );
AO22X1TS U918 ( .A0(n5051), .A1(Add_result[47]), .B0(n703), .B1(n5044), .Y(
n425) );
CLKMX2X2TS U919 ( .A(P_Sgf[93]), .B(n4641), .S0(n4652), .Y(Sgf_operation_n16) );
AO22X1TS U920 ( .A0(n5051), .A1(Add_result[46]), .B0(n703), .B1(n5042), .Y(
n426) );
CLKMX2X2TS U921 ( .A(n748), .B(n4643), .S0(n4652), .Y(Sgf_operation_n17) );
AO22X1TS U922 ( .A0(n5051), .A1(Add_result[45]), .B0(n703), .B1(n5040), .Y(
n427) );
ADDHX1TS U923 ( .A(Sgf_normalized_result[46]), .B(n5043), .CO(n5045), .S(
n5042) );
ADDHX1TS U924 ( .A(Sgf_normalized_result[45]), .B(n5041), .CO(n5043), .S(
n5040) );
CLKMX2X2TS U925 ( .A(P_Sgf[91]), .B(n4646), .S0(n4895), .Y(Sgf_operation_n18) );
AO22X1TS U926 ( .A0(n5060), .A1(Add_result[44]), .B0(n703), .B1(n5038), .Y(
n428) );
CLKMX2X2TS U927 ( .A(n747), .B(n4648), .S0(n4645), .Y(Sgf_operation_n19) );
AO22X1TS U928 ( .A0(n5060), .A1(Add_result[43]), .B0(n703), .B1(n5036), .Y(
n429) );
AO22X1TS U929 ( .A0(n5060), .A1(Add_result[42]), .B0(n703), .B1(n5034), .Y(
n430) );
AO22X1TS U930 ( .A0(n5060), .A1(Add_result[41]), .B0(n5062), .B1(n5032), .Y(
n431) );
ADDHX1TS U931 ( .A(Sgf_normalized_result[41]), .B(n5033), .CO(n5035), .S(
n5032) );
ADDHX1TS U932 ( .A(Sgf_normalized_result[40]), .B(n5031), .CO(n5033), .S(
n5030) );
ADDHX1TS U933 ( .A(Sgf_normalized_result[39]), .B(n5029), .CO(n5031), .S(
n5028) );
OAI21X1TS U934 ( .A0(n4762), .A1(n4758), .B0(n4759), .Y(n4756) );
OAI21X1TS U935 ( .A0(n4790), .A1(n4786), .B0(n4787), .Y(n4784) );
OAI21X1TS U936 ( .A0(n4764), .A1(n4771), .B0(n4772), .Y(n4769) );
OAI21X1TS U937 ( .A0(n4717), .A1(n4700), .B0(n4699), .Y(n4705) );
OAI21X1TS U938 ( .A0(n4792), .A1(n4799), .B0(n4800), .Y(n4797) );
OAI21X1TS U939 ( .A0(n4741), .A1(n4671), .B0(n4670), .Y(n4676) );
OAI21X1TS U940 ( .A0(n4741), .A1(n4688), .B0(n4687), .Y(n4693) );
OAI21X1TS U941 ( .A0(n4823), .A1(n4830), .B0(n4831), .Y(n4828) );
OAI21X1TS U942 ( .A0(n4458), .A1(n4454), .B0(n4455), .Y(n4415) );
OAI21X1TS U943 ( .A0(n4452), .A1(n4443), .B0(n4449), .Y(n4447) );
OAI21X1TS U944 ( .A0(n4432), .A1(n4431), .B0(n4430), .Y(n4437) );
OAI21X2TS U945 ( .A0(n4743), .A1(n4256), .B0(n4255), .Y(n4669) );
NOR2X1TS U946 ( .A(n4671), .B(n4672), .Y(n4267) );
OAI21X1TS U947 ( .A0(n4366), .A1(n4362), .B0(n4363), .Y(n4337) );
OAI21X2TS U948 ( .A0(n4408), .A1(n4232), .B0(n4231), .Y(n4303) );
INVX1TS U949 ( .A(n4678), .Y(n4681) );
INVX1TS U950 ( .A(n4679), .Y(n4680) );
OAI21X1TS U951 ( .A0(n4597), .A1(n4343), .B0(n4342), .Y(n4347) );
OAI21X1TS U952 ( .A0(n4585), .A1(n4581), .B0(n4582), .Y(n4547) );
OAI21X1TS U953 ( .A0(n4699), .A1(n4701), .B0(n4702), .Y(n4263) );
OAI21X1TS U954 ( .A0(n4780), .A1(n4787), .B0(n4781), .Y(n4247) );
OAI21X1TS U955 ( .A0(n4811), .A1(n4818), .B0(n4812), .Y(n4243) );
AOI21X1TS U956 ( .A0(n4734), .A1(n4258), .B0(n4257), .Y(n4719) );
OAI21X1TS U957 ( .A0(n4368), .A1(n4210), .B0(n4209), .Y(n4211) );
OAI21X1TS U958 ( .A0(n4838), .A1(n4845), .B0(n4839), .Y(n4241) );
OAI21X1TS U959 ( .A0(n4752), .A1(n4759), .B0(n4753), .Y(n4249) );
OAI21X1TS U960 ( .A0(n4870), .A1(n4877), .B0(n4871), .Y(n4235) );
INVX1TS U961 ( .A(n4672), .Y(n4674) );
NOR2X1TS U962 ( .A(n4210), .B(n4369), .Y(n4212) );
OAI21X1TS U963 ( .A0(n4565), .A1(n4567), .B0(n4568), .Y(n4201) );
OR2X2TS U964 ( .A(Sgf_operation_mult_x_1_n1528), .B(
Sgf_operation_mult_x_1_n1541), .Y(n4683) );
OAI21X1TS U965 ( .A0(n4351), .A1(n4392), .B0(n4352), .Y(n4213) );
OAI21X1TS U966 ( .A0(n4543), .A1(n4582), .B0(n4544), .Y(n4203) );
OAI21X1TS U967 ( .A0(n4490), .A1(n4191), .B0(n4190), .Y(n4494) );
OAI21X1TS U968 ( .A0(n2952), .A1(n3576), .B0(n1426), .Y(n1427) );
OAI21X1TS U969 ( .A0(n2952), .A1(n4060), .B0(n1103), .Y(n1104) );
OAI21X1TS U970 ( .A0(n2952), .A1(n3514), .B0(n1192), .Y(n1193) );
OAI21X1TS U971 ( .A0(n956), .A1(n1611), .B0(n1609), .Y(n1167) );
OAI21X1TS U972 ( .A0(n956), .A1(n3576), .B0(n3217), .Y(n3218) );
OAI21X1TS U973 ( .A0(n956), .A1(n3679), .B0(n3254), .Y(n3255) );
OAI21X1TS U974 ( .A0(n956), .A1(n1070), .B0(n957), .Y(n958) );
OAI21X1TS U975 ( .A0(n956), .A1(n3628), .B0(n3241), .Y(n3242) );
OAI21X1TS U976 ( .A0(n956), .A1(n3531), .B0(n3194), .Y(n3195) );
OAI21X1TS U977 ( .A0(n956), .A1(n1984), .B0(n1736), .Y(n1275) );
OAI21X1TS U978 ( .A0(n2952), .A1(n3503), .B0(n1107), .Y(n1108) );
OAI21X1TS U979 ( .A0(n3909), .A1(n4060), .B0(n1023), .Y(n1024) );
OAI21X1TS U980 ( .A0(n2945), .A1(n2665), .B0(n1335), .Y(n1336) );
OAI21X1TS U981 ( .A0(n2945), .A1(n4060), .B0(n987), .Y(n988) );
OAI21X1TS U982 ( .A0(n2973), .A1(n3487), .B0(n1685), .Y(n1686) );
OAI21X1TS U983 ( .A0(n3232), .A1(n4060), .B0(n1251), .Y(n1252) );
OAI21X1TS U984 ( .A0(n3914), .A1(n3514), .B0(n1168), .Y(n1169) );
OAI21X1TS U985 ( .A0(n3909), .A1(n3576), .B0(n1242), .Y(n1243) );
OAI21X1TS U986 ( .A0(n3208), .A1(n3514), .B0(n1240), .Y(n1241) );
OAI21X1TS U987 ( .A0(n2973), .A1(n4060), .B0(n1283), .Y(n1284) );
OAI21X1TS U988 ( .A0(n2945), .A1(n3503), .B0(n1072), .Y(n1073) );
OAI21X1TS U989 ( .A0(n2945), .A1(n3640), .B0(n1641), .Y(n1642) );
OAI21X1TS U990 ( .A0(n3909), .A1(n3514), .B0(n1109), .Y(n1110) );
OAI21X1TS U991 ( .A0(n3914), .A1(n2665), .B0(n2017), .Y(n2018) );
OAI21X1TS U992 ( .A0(n2945), .A1(n3556), .B0(n1175), .Y(n1176) );
OAI21X1TS U993 ( .A0(n3237), .A1(n3317), .B0(n1030), .Y(n1031) );
OAI21X1TS U994 ( .A0(n3266), .A1(n4060), .B0(n3060), .Y(n3061) );
OAI21X1TS U995 ( .A0(n2945), .A1(n3576), .B0(n1222), .Y(n1223) );
OAI21X1TS U996 ( .A0(n3237), .A1(n3337), .B0(n1111), .Y(n1112) );
OAI21X1TS U997 ( .A0(n3909), .A1(n2665), .B0(n1368), .Y(n1369) );
OAI21X1TS U998 ( .A0(n3925), .A1(n3556), .B0(n1270), .Y(n1271) );
OAI21X1TS U999 ( .A0(n3914), .A1(n3503), .B0(n1089), .Y(n1090) );
OAI21X1TS U1000 ( .A0(n3925), .A1(n3514), .B0(n1190), .Y(n1191) );
OAI21X1TS U1001 ( .A0(n2967), .A1(n3487), .B0(n1287), .Y(n1288) );
OAI21X1TS U1002 ( .A0(n2945), .A1(n3210), .B0(n1105), .Y(n1106) );
OAI21X1TS U1003 ( .A0(n3232), .A1(n3487), .B0(n1342), .Y(n1343) );
OAI21X1TS U1004 ( .A0(n3208), .A1(n3544), .B0(n1344), .Y(n1346) );
OAI21X1TS U1005 ( .A0(n3909), .A1(n3556), .B0(n1181), .Y(n1182) );
OAI21X1TS U1006 ( .A0(n3909), .A1(n3503), .B0(n1085), .Y(n1086) );
OAI21X1TS U1007 ( .A0(n3208), .A1(n3487), .B0(n1177), .Y(n1178) );
OAI21X1TS U1008 ( .A0(n3237), .A1(n3281), .B0(n3187), .Y(n3188) );
BUFX4TS U1009 ( .A(n1113), .Y(n625) );
OAI21X1TS U1010 ( .A0(n4057), .A1(n3192), .B0(n3191), .Y(n3193) );
OAI21X1TS U1011 ( .A0(n4057), .A1(n3215), .B0(n3214), .Y(n3216) );
INVX4TS U1012 ( .A(n1079), .Y(n3914) );
BUFX4TS U1013 ( .A(n1039), .Y(n626) );
BUFX4TS U1014 ( .A(n1009), .Y(n627) );
OAI21X1TS U1015 ( .A0(n4057), .A1(n1984), .B0(n1285), .Y(n1286) );
BUFX4TS U1016 ( .A(n1068), .Y(n628) );
BUFX4TS U1017 ( .A(n1980), .Y(n629) );
BUFX4TS U1018 ( .A(n2218), .Y(n630) );
INVX4TS U1019 ( .A(n1063), .Y(n3925) );
OAI21X1TS U1020 ( .A0(n4057), .A1(n3675), .B0(n3064), .Y(n3065) );
INVX4TS U1021 ( .A(n1029), .Y(n3237) );
INVX4TS U1022 ( .A(n953), .Y(n4046) );
OAI21X1TS U1023 ( .A0(n4057), .A1(n1174), .B0(n1035), .Y(n1036) );
INVX4TS U1024 ( .A(n1162), .Y(n2961) );
BUFX4TS U1025 ( .A(n2183), .Y(n631) );
BUFX4TS U1026 ( .A(n974), .Y(n632) );
OAI21X1TS U1027 ( .A0(n4057), .A1(n2665), .B0(n1154), .Y(n1155) );
BUFX4TS U1028 ( .A(n3464), .Y(n633) );
BUFX4TS U1029 ( .A(n2306), .Y(n634) );
OAI21X1TS U1030 ( .A0(n4057), .A1(n1484), .B0(n1197), .Y(n1198) );
INVX4TS U1031 ( .A(n1126), .Y(n3208) );
INVX4TS U1032 ( .A(n1207), .Y(n2967) );
BUFX4TS U1033 ( .A(n2080), .Y(n635) );
BUFX4TS U1034 ( .A(n1691), .Y(n636) );
INVX4TS U1035 ( .A(n1708), .Y(n3978) );
INVX4TS U1036 ( .A(n1533), .Y(n3969) );
XNOR2X1TS U1037 ( .A(n2976), .B(n1726), .Y(n1727) );
INVX4TS U1038 ( .A(n2010), .Y(n3940) );
INVX4TS U1039 ( .A(n864), .Y(n3988) );
XNOR2X1TS U1040 ( .A(n991), .B(n985), .Y(n986) );
BUFX4TS U1041 ( .A(n2067), .Y(n637) );
BUFX4TS U1042 ( .A(n2419), .Y(n638) );
BUFX4TS U1043 ( .A(n1793), .Y(n639) );
BUFX4TS U1044 ( .A(n1996), .Y(n640) );
INVX4TS U1045 ( .A(n819), .Y(n3960) );
BUFX4TS U1046 ( .A(n1850), .Y(n641) );
INVX4TS U1047 ( .A(n835), .Y(n3249) );
INVX4TS U1048 ( .A(n1406), .Y(n3002) );
INVX4TS U1049 ( .A(n872), .Y(n3310) );
INVX4TS U1050 ( .A(n1601), .Y(n3288) );
XNOR2X1TS U1051 ( .A(n1021), .B(n1020), .Y(n1022) );
BUFX4TS U1052 ( .A(n1559), .Y(n642) );
INVX4TS U1053 ( .A(n1352), .Y(n4155) );
BUFX4TS U1054 ( .A(n2329), .Y(n643) );
BUFX4TS U1055 ( .A(n1613), .Y(n644) );
OAI21X1TS U1056 ( .A0(n938), .A1(n943), .B0(n758), .Y(n930) );
OAI21XLTS U1057 ( .A0(n4142), .A1(n3531), .B0(n1304), .Y(n1305) );
NOR2X1TS U1058 ( .A(n887), .B(n896), .Y(n899) );
OAI21X1TS U1059 ( .A0(n897), .A1(n896), .B0(n895), .Y(n898) );
INVX4TS U1060 ( .A(n1303), .Y(n4142) );
INVX3TS U1061 ( .A(n4041), .Y(n3035) );
AOI222X1TS U1062 ( .A0(n3659), .A1(n3929), .B0(n3650), .B1(n3928), .C0(n3649), .C1(n3893), .Y(n3652) );
AOI222X1TS U1063 ( .A0(n4106), .A1(n3953), .B0(n3900), .B1(n3952), .C0(n4104), .C1(n3008), .Y(n2035) );
AOI222X1TS U1064 ( .A0(n3901), .A1(n2645), .B0(n4105), .B1(n2644), .C0(n4104), .C1(n3229), .Y(n2275) );
AOI222X1TS U1065 ( .A0(n4106), .A1(n3943), .B0(n4098), .B1(n3942), .C0(n4104), .C1(n3024), .Y(n2795) );
AOI222X1TS U1066 ( .A0(n3729), .A1(n3963), .B0(n3728), .B1(n3962), .C0(n3739), .C1(n3015), .Y(n2163) );
AOI222X1TS U1067 ( .A0(n3750), .A1(n3916), .B0(n3728), .B1(n3849), .C0(n3748), .C1(n3848), .Y(n3730) );
AOI222X1TS U1068 ( .A0(n3473), .A1(n3929), .B0(n3472), .B1(n3928), .C0(n3468), .C1(n3893), .Y(n3466) );
AOI222X1TS U1069 ( .A0(n3584), .A1(n3982), .B0(n3583), .B1(n3981), .C0(n3582), .C1(n3034), .Y(n1853) );
AOI222X1TS U1070 ( .A0(n3696), .A1(n2474), .B0(n3704), .B1(n2473), .C0(n3721), .C1(n2962), .Y(n1806) );
AOI222X1TS U1071 ( .A0(n3473), .A1(n3982), .B0(n3279), .B1(n3981), .C0(n3471), .C1(n3034), .Y(n1952) );
AOI222X1TS U1072 ( .A0(n4106), .A1(n3958), .B0(n3900), .B1(n3957), .C0(n3894), .C1(n3899), .Y(n3902) );
AOI222X1TS U1073 ( .A0(n3651), .A1(n2643), .B0(n3650), .B1(n2429), .C0(n3657), .C1(n2981), .Y(n1906) );
AOI222X1TS U1074 ( .A0(n3696), .A1(n3918), .B0(n3712), .B1(n3917), .C0(n3721), .C1(n2950), .Y(n1461) );
AOI222X1TS U1075 ( .A0(n3901), .A1(n2584), .B0(n4105), .B1(n2583), .C0(n4104), .C1(n2968), .Y(n2346) );
AOI222X1TS U1076 ( .A0(n1452), .A1(n2645), .B0(n3542), .B1(n2644), .C0(n3546), .C1(n3229), .Y(n2427) );
AOI222X1TS U1077 ( .A0(n3689), .A1(n3916), .B0(n2746), .B1(n3849), .C0(n3687), .C1(n3848), .Y(n1678) );
AOI222X1TS U1078 ( .A0(n3554), .A1(n3972), .B0(n3553), .B1(n3971), .C0(n3552), .C1(n3012), .Y(n2354) );
AOI222X1TS U1079 ( .A0(n3901), .A1(n3885), .B0(n4105), .B1(n3884), .C0(n4104), .C1(n3883), .Y(n3886) );
AOI222X1TS U1080 ( .A0(n3773), .A1(n2474), .B0(n3758), .B1(n2473), .C0(n3772), .C1(n2584), .Y(n1855) );
AOI222X1TS U1081 ( .A0(n1452), .A1(n3992), .B0(n3553), .B1(n3991), .C0(n3552), .C1(n3031), .Y(n2259) );
AOI222X1TS U1082 ( .A0(n3713), .A1(n2643), .B0(n3704), .B1(n2429), .C0(n2751), .C1(n2981), .Y(n1958) );
AOI222X1TS U1083 ( .A0(n3659), .A1(n3997), .B0(n3658), .B1(n3996), .C0(n3657), .C1(n3808), .Y(n2099) );
AOI222X1TS U1084 ( .A0(n3529), .A1(n2397), .B0(n3528), .B1(n2396), .C0(n3527), .C1(n3294), .Y(n1768) );
AOI222X1TS U1085 ( .A0(n3805), .A1(n2729), .B0(n3151), .B1(n700), .C0(n3156),
.C1(n4069), .Y(n2352) );
AOI222X1TS U1086 ( .A0(n3561), .A1(n3986), .B0(n3583), .B1(n3985), .C0(n3574), .C1(n3301), .Y(n1923) );
AOI222X1TS U1087 ( .A0(n3561), .A1(n3958), .B0(n3578), .B1(n3957), .C0(n3582), .C1(n3899), .Y(n3579) );
BUFX4TS U1088 ( .A(n4070), .Y(n3295) );
AOI222X1TS U1089 ( .A0(n3590), .A1(n3953), .B0(n3578), .B1(n3952), .C0(n3588), .C1(n3008), .Y(n2070) );
AOI222X1TS U1090 ( .A0(n3689), .A1(n2645), .B0(n3688), .B1(n2644), .C0(n3681), .C1(n3229), .Y(n1966) );
AOI222X1TS U1091 ( .A0(n1452), .A1(n3976), .B0(n3553), .B1(n3975), .C0(n3552), .C1(n3278), .Y(n2091) );
AOI222X1TS U1092 ( .A0(n3590), .A1(n3976), .B0(n3583), .B1(n3975), .C0(n3574), .C1(n3278), .Y(n2083) );
AOI222X1TS U1093 ( .A0(n3723), .A1(n3916), .B0(n3712), .B1(n3849), .C0(n3721), .C1(n3848), .Y(n3694) );
AOI222X1TS U1094 ( .A0(n3590), .A1(n3963), .B0(n3578), .B1(n3962), .C0(n3582), .C1(n3015), .Y(n2033) );
AOI222X1TS U1095 ( .A0(n3554), .A1(n3963), .B0(n3534), .B1(n3962), .C0(n3552), .C1(n3015), .Y(n2404) );
AOI222X1TS U1096 ( .A0(n3473), .A1(n3997), .B0(n3279), .B1(n3996), .C0(n3468), .C1(n3808), .Y(n1656) );
AOI222X1TS U1097 ( .A0(n3811), .A1(n3953), .B0(n3810), .B1(n3952), .C0(n3809), .C1(n3008), .Y(n1919) );
AOI222X1TS U1098 ( .A0(n3590), .A1(n3972), .B0(n3583), .B1(n3971), .C0(n3574), .C1(n3012), .Y(n2402) );
AOI222X1TS U1099 ( .A0(n3732), .A1(n3992), .B0(n3743), .B1(n3991), .C0(n3742), .C1(n3031), .Y(n2386) );
AOI222X1TS U1100 ( .A0(n3732), .A1(n2474), .B0(n3749), .B1(n2473), .C0(n3742), .C1(n2962), .Y(n1884) );
AOI222X1TS U1101 ( .A0(n3729), .A1(n3918), .B0(n3728), .B1(n3917), .C0(n3739), .C1(n2950), .Y(n2680) );
AOI222X1TS U1102 ( .A0(n3713), .A1(n2645), .B0(n3704), .B1(n2644), .C0(n2751), .C1(n3229), .Y(n1902) );
AOI222X1TS U1103 ( .A0(n3723), .A1(n2584), .B0(n3704), .B1(n2583), .C0(n2751), .C1(n2968), .Y(n1846) );
AOI222X1TS U1104 ( .A0(n3561), .A1(n3967), .B0(n3583), .B1(n3966), .C0(n3574), .C1(n3017), .Y(n1863) );
AOI222X1TS U1105 ( .A0(n3820), .A1(n2729), .B0(n3129), .B1(n2728), .C0(n3841), .C1(n3235), .Y(n2406) );
AOI222X1TS U1106 ( .A0(n3590), .A1(n3947), .B0(n3578), .B1(n3946), .C0(n3574), .C1(n3020), .Y(n2595) );
AOI222X1TS U1107 ( .A0(n3554), .A1(n2474), .B0(n3542), .B1(n2473), .C0(n3546), .C1(n2962), .Y(n2210) );
AOI222X1TS U1108 ( .A0(n1452), .A1(n3986), .B0(n3553), .B1(n3985), .C0(n3552), .C1(n3301), .Y(n2031) );
AOI222X1TS U1109 ( .A0(n3494), .A1(n3980), .B0(n3500), .B1(n3308), .C0(n3499), .C1(n3307), .Y(n3309) );
AOI222X1TS U1110 ( .A0(n3561), .A1(n3916), .B0(n3578), .B1(n3849), .C0(n3582), .C1(n3848), .Y(n3559) );
AOI222X1TS U1111 ( .A0(n4036), .A1(n3958), .B0(n4035), .B1(n3957), .C0(n4034), .C1(n3899), .Y(n2200) );
AOI222X1TS U1112 ( .A0(n1452), .A1(n3967), .B0(n3553), .B1(n3966), .C0(n3552), .C1(n3017), .Y(n2123) );
AOI222X1TS U1113 ( .A0(n3732), .A1(n2584), .B0(n3749), .B1(n2583), .C0(n3742), .C1(n2968), .Y(n1974) );
AOI222X1TS U1114 ( .A0(n4106), .A1(n2729), .B0(n4098), .B1(Op_MY[50]), .C0(
n4104), .C1(n4069), .Y(n2085) );
AOI222X1TS U1115 ( .A0(n3811), .A1(n3918), .B0(n3151), .B1(n3917), .C0(n3156), .C1(n2950), .Y(n2558) );
AOI222X1TS U1116 ( .A0(n3750), .A1(n3885), .B0(n3749), .B1(n3884), .C0(n3748), .C1(n3883), .Y(n2192) );
AOI222X1TS U1117 ( .A0(n3811), .A1(n3943), .B0(n3151), .B1(n3942), .C0(n3809), .C1(n3024), .Y(n2781) );
AOI222X1TS U1118 ( .A0(n3561), .A1(n3943), .B0(n3578), .B1(n3942), .C0(n3588), .C1(n3024), .Y(n2700) );
AOI222X1TS U1119 ( .A0(n3554), .A1(n3980), .B0(n3553), .B1(n3308), .C0(n3552), .C1(n3307), .Y(n1499) );
AOI222X1TS U1120 ( .A0(n3494), .A1(n3992), .B0(n3500), .B1(n3991), .C0(n3499), .C1(n3031), .Y(n2438) );
AOI222X1TS U1121 ( .A0(n3554), .A1(n3958), .B0(n3534), .B1(n3957), .C0(n3552), .C1(n3899), .Y(n1904) );
AOI222X1TS U1122 ( .A0(n3561), .A1(n2474), .B0(n3589), .B1(n2473), .C0(n3588), .C1(n2962), .Y(n2378) );
AOI222X1TS U1123 ( .A0(n3788), .A1(n3958), .B0(n3810), .B1(n3957), .C0(n3809), .C1(n3899), .Y(n1988) );
AOI222X1TS U1124 ( .A0(n3683), .A1(n3929), .B0(n3688), .B1(n3928), .C0(n3681), .C1(n3893), .Y(n3674) );
AOI222X1TS U1125 ( .A0(n3683), .A1(n3958), .B0(n2746), .B1(n3957), .C0(n3687), .C1(n3899), .Y(n1857) );
AOI222X1TS U1126 ( .A0(n3632), .A1(n3967), .B0(n3631), .B1(n3966), .C0(n3636), .C1(n3017), .Y(n2101) );
AOI222X1TS U1127 ( .A0(n3529), .A1(n4115), .B0(n3522), .B1(n4114), .C0(n3527), .C1(n3717), .Y(n1652) );
AOI222X1TS U1128 ( .A0(n3805), .A1(n2643), .B0(n3804), .B1(n2429), .C0(n3156), .C1(n2981), .Y(n2430) );
AOI222X1TS U1129 ( .A0(n3473), .A1(n3943), .B0(n4052), .B1(n3942), .C0(n4054), .C1(n3024), .Y(n2805) );
AOI222X1TS U1130 ( .A0(n3683), .A1(n3953), .B0(n2746), .B1(n3952), .C0(n3681), .C1(n3008), .Y(n1692) );
AOI222X1TS U1131 ( .A0(n3805), .A1(n3929), .B0(n3804), .B1(n3928), .C0(n3156), .C1(n3893), .Y(n3797) );
AOI222X1TS U1132 ( .A0(n3805), .A1(n2645), .B0(n3804), .B1(n2644), .C0(n3156), .C1(n3229), .Y(n1802) );
AOI222X1TS U1133 ( .A0(n3780), .A1(n2584), .B0(n3758), .B1(n2583), .C0(n3778), .C1(n2645), .Y(n2074) );
AOI222X1TS U1134 ( .A0(n2695), .A1(n3992), .B0(n3658), .B1(n3991), .C0(n2755), .C1(n3031), .Y(n2690) );
AOI222X1TS U1135 ( .A0(n3529), .A1(n4084), .B0(n3528), .B1(n4083), .C0(n3527), .C1(n3297), .Y(n1456) );
AOI222X1TS U1136 ( .A0(n3811), .A1(n2474), .B0(n3804), .B1(n2473), .C0(n3156), .C1(n2962), .Y(n1700) );
AOI222X1TS U1137 ( .A0(n3729), .A1(n2643), .B0(n3749), .B1(n2429), .C0(n3748), .C1(n2981), .Y(n1675) );
AOI222X1TS U1138 ( .A0(n3723), .A1(n3967), .B0(n3722), .B1(n3966), .C0(n2751), .C1(n3017), .Y(n2374) );
AOI222X1TS U1139 ( .A0(n3529), .A1(n4153), .B0(n3522), .B1(n4152), .C0(n3527), .C1(n4080), .Y(n1353) );
AOI222X1TS U1140 ( .A0(n3501), .A1(n3938), .B0(n2767), .B1(n3936), .C0(n2785), .C1(n3272), .Y(n2768) );
AOI222X1TS U1141 ( .A0(n3651), .A1(n3947), .B0(n3643), .B1(n3946), .C0(n2755), .C1(n3020), .Y(n2562) );
AOI222X1TS U1142 ( .A0(n3651), .A1(n3967), .B0(n3658), .B1(n3966), .C0(n3657), .C1(n3017), .Y(n1658) );
AOI222X1TS U1143 ( .A0(n4106), .A1(n3916), .B0(n3900), .B1(n3849), .C0(n4104), .C1(n3848), .Y(n2629) );
AOI222X1TS U1144 ( .A0(n2695), .A1(n3980), .B0(n3658), .B1(n3308), .C0(n2755), .C1(n3307), .Y(n2726) );
AOI222X1TS U1145 ( .A0(n3651), .A1(n3953), .B0(n3643), .B1(n3952), .C0(n3649), .C1(n3008), .Y(n1497) );
AOI222X1TS U1146 ( .A0(n3696), .A1(n3929), .B0(n3704), .B1(n3928), .C0(n3708), .C1(n3893), .Y(n3705) );
OR3X4TS U1147 ( .A(underflow_flag), .B(overflow_flag), .C(n5063), .Y(n885)
);
AOI222X1TS U1148 ( .A0(n3750), .A1(n3943), .B0(n3728), .B1(n3942), .C0(n3739), .C1(n3024), .Y(n2807) );
AOI222X1TS U1149 ( .A0(n3696), .A1(n3958), .B0(n3712), .B1(n3957), .C0(n3708), .C1(n3899), .Y(n3714) );
AOI222X1TS U1150 ( .A0(n3659), .A1(n3986), .B0(n3658), .B1(n3985), .C0(n3649), .C1(n3301), .Y(n2587) );
BUFX6TS U1151 ( .A(n2853), .Y(n2914) );
AOI222X1TS U1152 ( .A0(n3820), .A1(n2645), .B0(n3835), .B1(n2644), .C0(n3827), .C1(n2643), .Y(n2646) );
AOI222X1TS U1153 ( .A0(n3683), .A1(n3947), .B0(n2746), .B1(n3946), .C0(n3687), .C1(n3020), .Y(n2063) );
AOI222X1TS U1154 ( .A0(n1452), .A1(n2643), .B0(n3542), .B1(n2429), .C0(n3546), .C1(n2981), .Y(n2327) );
AOI222X1TS U1155 ( .A0(n3732), .A1(n2729), .B0(n3749), .B1(n700), .C0(n3742),
.C1(n4069), .Y(n2710) );
AOI222X1TS U1156 ( .A0(n3473), .A1(n3976), .B0(n3279), .B1(n3975), .C0(n3471), .C1(n3278), .Y(n3280) );
AOI222X1TS U1157 ( .A0(n3659), .A1(n3982), .B0(n3658), .B1(n3981), .C0(n3649), .C1(n3034), .Y(n2556) );
AOI222X1TS U1158 ( .A0(n3651), .A1(n3958), .B0(n3643), .B1(n3957), .C0(n3657), .C1(n3899), .Y(n1668) );
AOI222X1TS U1159 ( .A0(n3659), .A1(n3916), .B0(n3643), .B1(n3849), .C0(n2755), .C1(n3848), .Y(n3644) );
AOI222X1TS U1160 ( .A0(n3554), .A1(n3997), .B0(n3553), .B1(n3996), .C0(n3546), .C1(n3808), .Y(n1696) );
AOI222X1TS U1161 ( .A0(n3651), .A1(n3963), .B0(n3643), .B1(n3962), .C0(n3657), .C1(n3015), .Y(n1796) );
AOI222X1TS U1162 ( .A0(n3473), .A1(n3972), .B0(n3279), .B1(n3971), .C0(n3471), .C1(n3012), .Y(n1794) );
AOI222X1TS U1163 ( .A0(n3651), .A1(n3972), .B0(n3658), .B1(n3971), .C0(n3649), .C1(n3012), .Y(n1970) );
AOI222X1TS U1164 ( .A0(n3811), .A1(n3859), .B0(n3804), .B1(n3858), .C0(n3809), .C1(n3857), .Y(n3795) );
AOI222X1TS U1165 ( .A0(n3750), .A1(n2645), .B0(n3749), .B1(n2644), .C0(n3748), .C1(n3229), .Y(n1908) );
AOI222X1TS U1166 ( .A0(n3561), .A1(n3890), .B0(n3589), .B1(n3889), .C0(n3574), .C1(n3888), .Y(n3566) );
AOI222X1TS U1167 ( .A0(n3998), .A1(n2729), .B0(n4165), .B1(n700), .C0(n4163),
.C1(n3235), .Y(n2442) );
AOI222X1TS U1168 ( .A0(n3501), .A1(n3933), .B0(n3489), .B1(n3932), .C0(n2785), .C1(n3872), .Y(n2786) );
AOI222X1TS U1169 ( .A0(n3713), .A1(n3963), .B0(n3712), .B1(n3962), .C0(n3708), .C1(n3015), .Y(n2763) );
AOI222X1TS U1170 ( .A0(n3729), .A1(n3947), .B0(n3728), .B1(n3946), .C0(n3739), .C1(n3020), .Y(n2765) );
AOI222X1TS U1171 ( .A0(n3683), .A1(n3963), .B0(n2746), .B1(n3962), .C0(n3687), .C1(n3015), .Y(n1937) );
AOI222X1TS U1172 ( .A0(n3729), .A1(n3958), .B0(n3728), .B1(n3957), .C0(n3742), .C1(n3899), .Y(n2533) );
AOI222X1TS U1173 ( .A0(n3561), .A1(n2645), .B0(n3589), .B1(n2644), .C0(n3574), .C1(n3229), .Y(n2487) );
AOI222X1TS U1174 ( .A0(n3901), .A1(n2474), .B0(n4105), .B1(n2473), .C0(n4104), .C1(n2962), .Y(n2471) );
AOI222X1TS U1175 ( .A0(n3689), .A1(n3967), .B0(n3682), .B1(n3966), .C0(n3681), .C1(n3017), .Y(n2340) );
AOI222X1TS U1176 ( .A0(n3590), .A1(n3997), .B0(n3583), .B1(n3996), .C0(n3582), .C1(n3808), .Y(n3585) );
AOI222X1TS U1177 ( .A0(n3729), .A1(n3953), .B0(n3728), .B1(n3952), .C0(n3748), .C1(n3008), .Y(n2668) );
AOI222X1TS U1178 ( .A0(n3723), .A1(n3976), .B0(n3722), .B1(n3975), .C0(n3708), .C1(n3278), .Y(n2336) );
AOI222X1TS U1179 ( .A0(n3901), .A1(n3918), .B0(n4098), .B1(n3917), .C0(n4104), .C1(n2950), .Y(n1556) );
AOI222X1TS U1180 ( .A0(n3651), .A1(n3976), .B0(n3658), .B1(n3975), .C0(n3657), .C1(n3278), .Y(n2249) );
AOI222X1TS U1181 ( .A0(n3723), .A1(n3943), .B0(n3712), .B1(n3942), .C0(n3708), .C1(n3024), .Y(n1917) );
AOI222X1TS U1182 ( .A0(n3659), .A1(n2474), .B0(n3650), .B1(n2473), .C0(n3649), .C1(n2962), .Y(n1737) );
AOI222X1TS U1183 ( .A0(n3683), .A1(n3943), .B0(n2746), .B1(n3942), .C0(n3681), .C1(n3024), .Y(n2718) );
AOI222X1TS U1184 ( .A0(n3811), .A1(n3916), .B0(n3810), .B1(n3849), .C0(n3156), .C1(n3848), .Y(n3785) );
BUFX3TS U1185 ( .A(n1484), .Y(n3122) );
BUFX4TS U1186 ( .A(n1163), .Y(n3465) );
BUFX4TS U1187 ( .A(n3074), .Y(n645) );
OAI21X1TS U1188 ( .A0(n1388), .A1(n802), .B0(n801), .Y(n803) );
BUFX3TS U1189 ( .A(n3215), .Y(n3580) );
NOR2X2TS U1190 ( .A(FSM_selector_C), .B(n4955), .Y(n2812) );
NAND2X4TS U1191 ( .A(n759), .B(n2987), .Y(n3069) );
OAI21X1TS U1192 ( .A0(n1043), .A1(n919), .B0(n918), .Y(n920) );
BUFX3TS U1193 ( .A(n2734), .Y(n3076) );
NAND2BXLTS U1194 ( .AN(n4272), .B(n4271), .Y(n4657) );
OAI21X1TS U1195 ( .A0(n2986), .A1(n790), .B0(n789), .Y(n791) );
BUFX3TS U1196 ( .A(n3706), .Y(n3715) );
BUFX3TS U1197 ( .A(n4056), .Y(n3281) );
BUFX3TS U1198 ( .A(n3679), .Y(n3140) );
BUFX4TS U1199 ( .A(n883), .Y(n881) );
NOR2X1TS U1200 ( .A(n1050), .B(n917), .Y(n918) );
NOR2X1TS U1201 ( .A(n1134), .B(n913), .Y(n914) );
NOR2X1TS U1202 ( .A(n989), .B(n925), .Y(n926) );
NOR2X1TS U1203 ( .A(n1212), .B(n903), .Y(n904) );
NOR2X1TS U1204 ( .A(n1477), .B(n907), .Y(n908) );
NOR2X1TS U1205 ( .A(n1827), .B(n825), .Y(n826) );
NOR2X1TS U1206 ( .A(n796), .B(n795), .Y(n797) );
NOR2X1TS U1207 ( .A(n1390), .B(n800), .Y(n801) );
NOR2X1TS U1208 ( .A(n1772), .B(n813), .Y(n814) );
NOR2X1TS U1209 ( .A(n1511), .B(n809), .Y(n810) );
NAND3XLTS U1210 ( .A(n4270), .B(n5150), .C(n707), .Y(n4271) );
OR2X2TS U1211 ( .A(n4960), .B(Sgf_normalized_result[5]), .Y(n4962) );
OR2X2TS U1212 ( .A(n3888), .B(n2968), .Y(n1644) );
CLKAND2X4TS U1213 ( .A(n4019), .B(n4018), .Y(n4609) );
OR2X2TS U1214 ( .A(n3857), .B(n3229), .Y(n1279) );
NOR2XLTS U1215 ( .A(n4906), .B(n5070), .Y(n884) );
OR2X2TS U1216 ( .A(n3848), .B(n2956), .Y(n1135) );
OR2X2TS U1217 ( .A(n2950), .B(n2954), .Y(n1096) );
OR2X2TS U1218 ( .A(n3883), .B(n2962), .Y(n1478) );
OR2X2TS U1219 ( .A(n3201), .B(n3199), .Y(n1076) );
OR2X2TS U1220 ( .A(n3787), .B(n3222), .Y(n1229) );
OR2X2TS U1221 ( .A(n3184), .B(n2946), .Y(n1019) );
AND2X4TS U1222 ( .A(n4272), .B(n5181), .Y(DP_OP_31J39_122_605_n42) );
OR2X2TS U1223 ( .A(n4958), .B(Sgf_normalized_result[4]), .Y(n4960) );
NOR2XLTS U1224 ( .A(n5073), .B(FS_Module_state_reg[2]), .Y(n4019) );
OAI21X2TS U1225 ( .A0(n4311), .A1(n4216), .B0(n4215), .Y(n4315) );
ADDHX1TS U1226 ( .A(Sgf_normalized_result[42]), .B(n5035), .CO(n5037), .S(
n5034) );
INVX2TS U1227 ( .A(n4738), .Y(n4258) );
OAI21X1TS U1228 ( .A0(n4670), .A1(n4672), .B0(n4673), .Y(n4266) );
OAI21X1TS U1229 ( .A0(n1724), .A1(n933), .B0(n932), .Y(n934) );
OAI21X2TS U1230 ( .A0(n4528), .A1(n4198), .B0(n4197), .Y(n4549) );
AO22X1TS U1231 ( .A0(n5058), .A1(n5057), .B0(n5060), .B1(Add_result[52]),
.Y(n420) );
OAI21XLTS U1232 ( .A0(n4137), .A1(n3580), .B0(n3171), .Y(n3172) );
AOI21X1TS U1233 ( .A0(n1414), .A1(n1387), .B0(n1386), .Y(n1598) );
ADDHXLTS U1234 ( .A(n3400), .B(n3399), .CO(n3143), .S(n3411) );
OAI21XLTS U1235 ( .A0(n3069), .A1(n3140), .B0(n3135), .Y(n3136) );
CLKINVX6TS U1236 ( .A(n850), .Y(n3949) );
ADDHXLTS U1237 ( .A(n3420), .B(n3419), .CO(n3079), .S(n3431) );
OAI21XLTS U1238 ( .A0(n3069), .A1(n3076), .B0(n3070), .Y(n3071) );
AOI21X2TS U1239 ( .A0(n1245), .A1(n911), .B0(n910), .Y(n1158) );
NAND2X1TS U1240 ( .A(n1058), .B(n921), .Y(n923) );
OAI21XLTS U1241 ( .A0(n645), .A1(n3158), .B0(n3157), .Y(n3159) );
OAI21XLTS U1242 ( .A0(n4142), .A1(n3845), .B0(n3445), .Y(n3446) );
OAI21XLTS U1243 ( .A0(n3988), .A1(n4038), .B0(n1624), .Y(n1625) );
AOI21X1TS U1244 ( .A0(n900), .A1(n899), .B0(n898), .Y(n901) );
OAI21XLTS U1245 ( .A0(n4137), .A1(n3281), .B0(n3104), .Y(n3105) );
OAI21X1TS U1246 ( .A0(n2007), .A1(n887), .B0(n897), .Y(n1492) );
NAND2X1TS U1247 ( .A(n1512), .B(n1515), .Y(n811) );
NAND2X1TS U1248 ( .A(n1828), .B(n1831), .Y(n827) );
OAI21XLTS U1249 ( .A0(n3310), .A1(n3580), .B0(n3112), .Y(n3113) );
AOI222X1TS U1250 ( .A0(n3584), .A1(n3980), .B0(n3583), .B1(n3308), .C0(n3574), .C1(n3307), .Y(n3112) );
CLKAND2X2TS U1251 ( .A(n4048), .B(n3012), .Y(n3013) );
CLKAND2X2TS U1252 ( .A(n3295), .B(n3866), .Y(n3246) );
NAND2X1TS U1253 ( .A(n990), .B(n993), .Y(n927) );
OAI21XLTS U1254 ( .A0(n645), .A1(n3580), .B0(n3173), .Y(n3174) );
AOI222X1TS U1255 ( .A0(n3584), .A1(n4126), .B0(n3583), .B1(n4125), .C0(n3574), .C1(n4124), .Y(n3173) );
OAI21XLTS U1256 ( .A0(n3978), .A1(n3833), .B0(n3146), .Y(n3147) );
AOI222X1TS U1257 ( .A0(n3665), .A1(n4126), .B0(n3682), .B1(n4125), .C0(n3677), .C1(n4124), .Y(n3139) );
ADDHXLTS U1258 ( .A(n3404), .B(n3403), .CO(n3399), .S(n3414) );
OAI21XLTS U1259 ( .A0(n4120), .A1(n3661), .B0(n3381), .Y(n3382) );
OAI21XLTS U1260 ( .A0(n4137), .A1(n3715), .B0(n770), .Y(n771) );
AOI21X1TS U1261 ( .A0(n793), .A1(n792), .B0(n791), .Y(n1349) );
INVX2TS U1262 ( .A(n790), .Y(n793) );
OR2X1TS U1263 ( .A(n3717), .B(n3297), .Y(n1416) );
CLKAND2X2TS U1264 ( .A(n4048), .B(n3008), .Y(n820) );
CLKAND2X2TS U1265 ( .A(n4048), .B(n3024), .Y(n3019) );
OAI21XLTS U1266 ( .A0(n3069), .A1(n3770), .B0(n780), .Y(n781) );
OR2X1TS U1267 ( .A(n3720), .B(n3717), .Y(n1413) );
OAI21XLTS U1268 ( .A0(n4155), .A1(n3556), .B0(n3095), .Y(n3096) );
OAI21XLTS U1269 ( .A0(n4120), .A1(n3782), .B0(n3421), .Y(n3422) );
OAI21XLTS U1270 ( .A0(n3914), .A1(n3845), .B0(n1894), .Y(n1895) );
OAI21XLTS U1271 ( .A0(n3914), .A1(n3576), .B0(n1347), .Y(n1348) );
OAI21X1TS U1272 ( .A0(n1724), .A1(n942), .B0(n941), .Y(n952) );
OAI21XLTS U1273 ( .A0(n3069), .A1(n4038), .B0(n4029), .Y(n4030) );
OAI21XLTS U1274 ( .A0(n4137), .A1(n3833), .B0(n762), .Y(n763) );
XNOR2X1TS U1275 ( .A(n1378), .B(n1377), .Y(n1379) );
OAI21XLTS U1276 ( .A0(n4155), .A1(n3845), .B0(n3162), .Y(n3163) );
OAI21XLTS U1277 ( .A0(n4120), .A1(n3845), .B0(n3441), .Y(n3442) );
OAI21XLTS U1278 ( .A0(n4155), .A1(n3782), .B0(n3080), .Y(n3081) );
OAI21XLTS U1279 ( .A0(n3069), .A1(n3580), .B0(n3169), .Y(n3170) );
OR2X1TS U1280 ( .A(n3020), .B(n3024), .Y(n1494) );
NAND2X1TS U1281 ( .A(n1809), .B(n869), .Y(n861) );
NAND2X1TS U1282 ( .A(n2278), .B(n2281), .Y(n886) );
NAND2X1TS U1283 ( .A(n1585), .B(n1376), .Y(n798) );
NAND2X1TS U1284 ( .A(n1644), .B(n1647), .Y(n1199) );
OAI21XLTS U1285 ( .A0(n645), .A1(n3281), .B0(n3106), .Y(n3107) );
AOI222X1TS U1286 ( .A0(n3455), .A1(n4126), .B0(n3279), .B1(n4125), .C0(n3471), .C1(n4124), .Y(n3106) );
OAI21XLTS U1287 ( .A0(n4057), .A1(n3752), .B0(n3268), .Y(n3269) );
CLKINVX6TS U1288 ( .A(n1250), .Y(n3232) );
OAI21XLTS U1289 ( .A0(n4120), .A1(n3503), .B0(n3321), .Y(n3322) );
OAI21XLTS U1290 ( .A0(n3237), .A1(n4169), .B0(n1758), .Y(n1759) );
OAI21XLTS U1291 ( .A0(n2961), .A1(n3829), .B0(n1762), .Y(n1763) );
OAI21XLTS U1292 ( .A0(n2961), .A1(n3864), .B0(n2475), .Y(n2476) );
OAI21XLTS U1293 ( .A0(n4120), .A1(n3556), .B0(n3341), .Y(n3342) );
OAI21XLTS U1294 ( .A0(n4137), .A1(n3122), .B0(n3119), .Y(n3120) );
OAI21X2TS U1295 ( .A0(n860), .A1(n811), .B0(n810), .Y(n1543) );
NAND2X1TS U1296 ( .A(n1773), .B(n1776), .Y(n815) );
NAND2X1TS U1297 ( .A(n2148), .B(n2151), .Y(n891) );
NOR2X1TS U1298 ( .A(n1525), .B(n815), .Y(n817) );
NOR2X1TS U1299 ( .A(n886), .B(n891), .Y(n894) );
NAND2X1TS U1300 ( .A(n1403), .B(n1392), .Y(n802) );
OAI21X2TS U1301 ( .A0(n1210), .A1(n905), .B0(n904), .Y(n1245) );
NAND2X1TS U1302 ( .A(n1096), .B(n1099), .Y(n1044) );
NAND2X1TS U1303 ( .A(n1413), .B(n1416), .Y(n1370) );
ADDHXLTS U1304 ( .A(n3424), .B(n3423), .CO(n3419), .S(n3434) );
OAI21XLTS U1305 ( .A0(n4137), .A1(n3076), .B0(n3072), .Y(n3073) );
OAI21XLTS U1306 ( .A0(n3237), .A1(n2796), .B0(n2288), .Y(n2289) );
OAI21XLTS U1307 ( .A0(n2961), .A1(n3782), .B0(n1855), .Y(n1856) );
OAI21XLTS U1308 ( .A0(n3237), .A1(n3880), .B0(n2243), .Y(n2244) );
OAI21XLTS U1309 ( .A0(n2961), .A1(n3752), .B0(n1884), .Y(n1885) );
OAI21XLTS U1310 ( .A0(n3237), .A1(n3845), .B0(n2370), .Y(n2371) );
OAI21XLTS U1311 ( .A0(n633), .A1(n3661), .B0(n3652), .Y(n3654) );
OAI21XLTS U1312 ( .A0(n2952), .A1(n3766), .B0(n1804), .Y(n1805) );
OAI21XLTS U1313 ( .A0(n627), .A1(n4038), .B0(n2639), .Y(n2640) );
AOI222X1TS U1314 ( .A0(n4031), .A1(n2728), .B0(n4027), .B1(n2752), .C0(n3873), .C1(n4072), .Y(n2639) );
OAI21XLTS U1315 ( .A0(n2961), .A1(n3675), .B0(n2078), .Y(n2079) );
OAI21XLTS U1316 ( .A0(n3237), .A1(n3813), .B0(n2255), .Y(n2256) );
CLKAND2X2TS U1317 ( .A(n3295), .B(n3289), .Y(n3290) );
OAI21XLTS U1318 ( .A0(n2961), .A1(n3661), .B0(n1737), .Y(n1738) );
OAI21XLTS U1319 ( .A0(n3237), .A1(n3782), .B0(n2179), .Y(n2180) );
AO21XLTS U1320 ( .A0(n3151), .A1(n4047), .B0(n3805), .Y(n2570) );
AOI222X1TS U1321 ( .A0(n3494), .A1(n3947), .B0(n2767), .B1(n3946), .C0(n2785), .C1(n3020), .Y(n2749) );
OAI21XLTS U1322 ( .A0(n628), .A1(n2734), .B0(n2434), .Y(n2435) );
OAI21XLTS U1323 ( .A0(n2961), .A1(n3628), .B0(n2027), .Y(n2028) );
AOI222X1TS U1324 ( .A0(n3632), .A1(n2474), .B0(n3637), .B1(n2473), .C0(n3630), .C1(n2962), .Y(n2027) );
OAI21XLTS U1325 ( .A0(n3237), .A1(n3076), .B0(n2233), .Y(n2234) );
OAI21XLTS U1326 ( .A0(n3237), .A1(n3725), .B0(n2605), .Y(n2606) );
XNOR2X1TS U1327 ( .A(n2149), .B(n834), .Y(n835) );
OAI21XLTS U1328 ( .A0(n3237), .A1(n3675), .B0(n2747), .Y(n2748) );
XNOR2X1TS U1329 ( .A(n2279), .B(n2009), .Y(n2010) );
OAI21XLTS U1330 ( .A0(n3237), .A1(n2757), .B0(n2493), .Y(n2494) );
OAI21X1TS U1331 ( .A0(n1724), .A1(n1159), .B0(n1158), .Y(n1230) );
OAI21X1TS U1332 ( .A0(n1724), .A1(n1001), .B0(n1000), .Y(n1021) );
ADDHXLTS U1333 ( .A(n3444), .B(n3443), .CO(n3439), .S(n3454) );
OAI21XLTS U1334 ( .A0(n4137), .A1(n3158), .B0(n3154), .Y(n3155) );
OAI21XLTS U1335 ( .A0(n2692), .A1(n3766), .B0(n2798), .Y(n2800) );
OAI21XLTS U1336 ( .A0(n2961), .A1(n4169), .B0(n1798), .Y(n1799) );
OAI21XLTS U1337 ( .A0(n4120), .A1(n3725), .B0(n3401), .Y(n3402) );
OAI21XLTS U1338 ( .A0(n626), .A1(n3955), .B0(n2265), .Y(n2266) );
OAI21XLTS U1339 ( .A0(n625), .A1(n3955), .B0(n2390), .Y(n2391) );
OAI21XLTS U1340 ( .A0(n633), .A1(n3798), .B0(n3797), .Y(n3799) );
OAI21XLTS U1341 ( .A0(n3870), .A1(n4096), .B0(n2773), .Y(n2774) );
OAI21XLTS U1342 ( .A0(n638), .A1(n2796), .B0(n2783), .Y(n2784) );
OAI21XLTS U1343 ( .A0(n645), .A1(n3715), .B0(n3397), .Y(n3398) );
NAND2X1TS U1344 ( .A(n1076), .B(n1052), .Y(n919) );
NOR2X1TS U1345 ( .A(n1044), .B(n919), .Y(n921) );
OAI21XLTS U1346 ( .A0(n2967), .A1(n3766), .B0(n2074), .Y(n2075) );
OAI21XLTS U1347 ( .A0(n645), .A1(n3770), .B0(n3417), .Y(n3418) );
OAI21XLTS U1348 ( .A0(n625), .A1(n3702), .B0(n1915), .Y(n1916) );
OAI21XLTS U1349 ( .A0(n2961), .A1(n2665), .B0(n2290), .Y(n2291) );
OAI21XLTS U1350 ( .A0(n2961), .A1(n3576), .B0(n2378), .Y(n2379) );
OAI21X1TS U1351 ( .A0(n1724), .A1(n1060), .B0(n1059), .Y(n1097) );
OAI21X1TS U1352 ( .A0(n1724), .A1(n983), .B0(n982), .Y(n991) );
NAND2X1TS U1353 ( .A(n998), .B(n981), .Y(n983) );
XNOR2X1TS U1354 ( .A(n1078), .B(n1077), .Y(n1079) );
OAI21X1TS U1355 ( .A0(n1724), .A1(n962), .B0(n961), .Y(n1028) );
OAI21XLTS U1356 ( .A0(n641), .A1(n3158), .B0(n1851), .Y(n1852) );
OAI21XLTS U1357 ( .A0(n636), .A1(n3813), .B0(n1919), .Y(n1920) );
OAI21XLTS U1358 ( .A0(n639), .A1(n3770), .B0(n1722), .Y(n1723) );
OAI21XLTS U1359 ( .A0(n635), .A1(n3864), .B0(n3855), .Y(n3856) );
OAI21XLTS U1360 ( .A0(n4086), .A1(n4169), .B0(n4085), .Y(n4087) );
OAI21XLTS U1361 ( .A0(n637), .A1(n3158), .B0(n2684), .Y(n2685) );
OAI21XLTS U1362 ( .A0(n642), .A1(n3752), .B0(n1781), .Y(n1782) );
OAI21XLTS U1363 ( .A0(n4137), .A1(n4038), .B0(n4032), .Y(n4033) );
OAI21XLTS U1364 ( .A0(n645), .A1(n3833), .B0(n3437), .Y(n3438) );
AOI222X1TS U1365 ( .A0(n4036), .A1(n4084), .B0(n3878), .B1(n4083), .C0(n4034), .C1(n3297), .Y(n1888) );
XNOR2X1TS U1366 ( .A(n952), .B(n951), .Y(n953) );
OAI21XLTS U1367 ( .A0(n642), .A1(n3845), .B0(n1397), .Y(n1398) );
OAI21XLTS U1368 ( .A0(n3002), .A1(n3880), .B0(n1407), .Y(n1409) );
OAI21XLTS U1369 ( .A0(n642), .A1(n4096), .B0(n2053), .Y(n2054) );
NOR2X1TS U1370 ( .A(n4746), .B(n4252), .Y(n4254) );
OR2X1TS U1371 ( .A(Sgf_operation_mult_x_1_n2377), .B(
Sgf_operation_mult_x_1_n2396), .Y(n4461) );
OR2X1TS U1372 ( .A(Sgf_operation_mult_x_1_n2337), .B(
Sgf_operation_mult_x_1_n2356), .Y(n4475) );
OR2X1TS U1373 ( .A(Sgf_operation_mult_x_1_n2315), .B(
Sgf_operation_mult_x_1_n2336), .Y(n4470) );
OR2X1TS U1374 ( .A(Sgf_operation_mult_x_1_n2553), .B(
Sgf_operation_mult_x_1_n2566), .Y(n4387) );
OR2X1TS U1375 ( .A(Sgf_operation_mult_x_1_n2567), .B(
Sgf_operation_mult_x_1_n2580), .Y(n4345) );
OR2X1TS U1376 ( .A(Sgf_operation_mult_x_1_n2667), .B(
Sgf_operation_mult_x_1_n2676), .Y(n4577) );
NAND2X1TS U1377 ( .A(n3893), .B(n2981), .Y(n1725) );
NAND2X1TS U1378 ( .A(n3888), .B(n2968), .Y(n1248) );
OR2X1TS U1379 ( .A(n3017), .B(n3015), .Y(n1548) );
OAI21XLTS U1380 ( .A0(n3288), .A1(n3556), .B0(n1741), .Y(n1742) );
OAI21XLTS U1381 ( .A0(n3249), .A1(n3725), .B0(n2059), .Y(n2060) );
OAI21XLTS U1382 ( .A0(n4142), .A1(n3503), .B0(n3324), .Y(n3325) );
OAI21XLTS U1383 ( .A0(n3288), .A1(n3592), .B0(n1670), .Y(n1671) );
OAI21XLTS U1384 ( .A0(n3662), .A1(n3556), .B0(n3555), .Y(n3558) );
OAI21XLTS U1385 ( .A0(n3069), .A1(n3122), .B0(n3117), .Y(n3118) );
NAND2X1TS U1386 ( .A(n3008), .B(n3020), .Y(n823) );
OR2X1TS U1387 ( .A(n3899), .B(n3008), .Y(n1776) );
NAND2X1TS U1388 ( .A(n1705), .B(n1548), .Y(n1525) );
NAND2X1TS U1389 ( .A(n1300), .B(n1291), .Y(n790) );
NAND2X1TS U1390 ( .A(n2975), .B(n2978), .Y(n1211) );
NAND2X1TS U1391 ( .A(n1279), .B(n1214), .Y(n905) );
NAND2X1TS U1392 ( .A(n3012), .B(n3017), .Y(n1704) );
OR2X1TS U1393 ( .A(n3012), .B(n3017), .Y(n1705) );
OAI21X1TS U1394 ( .A0(n2007), .A1(n1545), .B0(n1544), .Y(n1707) );
NAND2X1TS U1395 ( .A(n3307), .B(n3301), .Y(n1808) );
NOR2X1TS U1396 ( .A(n3307), .B(n3301), .Y(n867) );
OR2X1TS U1397 ( .A(n3301), .B(n3034), .Y(n869) );
NAND2X1TS U1398 ( .A(n3015), .B(n3899), .Y(n1531) );
OAI21XLTS U1399 ( .A0(n3662), .A1(n3503), .B0(n3502), .Y(n3505) );
OAI21XLTS U1400 ( .A0(n4142), .A1(n3475), .B0(n1340), .Y(n1341) );
OAI21XLTS U1401 ( .A0(n4120), .A1(n3475), .B0(n1333), .Y(n1334) );
OAI21XLTS U1402 ( .A0(n644), .A1(n3503), .B0(n3497), .Y(n3498) );
OAI21XLTS U1403 ( .A0(n4155), .A1(n3475), .B0(n1410), .Y(n1411) );
CLKAND2X2TS U1404 ( .A(n3295), .B(n4028), .Y(n2989) );
OAI21XLTS U1405 ( .A0(n3949), .A1(n3628), .B0(n2194), .Y(n2195) );
OAI21XLTS U1406 ( .A0(n4057), .A1(n3955), .B0(n3904), .Y(n3905) );
OAI21XLTS U1407 ( .A0(n4086), .A1(n3503), .B0(n1553), .Y(n1554) );
OAI21XLTS U1408 ( .A0(n3266), .A1(n3675), .B0(n2546), .Y(n2547) );
AOI222X1TS U1409 ( .A0(n3523), .A1(n3992), .B0(n3522), .B1(n3991), .C0(n3527), .C1(n3031), .Y(n2444) );
OAI21XLTS U1410 ( .A0(n644), .A1(n3475), .B0(n1614), .Y(n1615) );
CLKAND2X2TS U1411 ( .A(n3295), .B(n4080), .Y(n2994) );
OAI21XLTS U1412 ( .A0(n3662), .A1(n3475), .B0(n2161), .Y(n2162) );
OAI21XLTS U1413 ( .A0(n3288), .A1(n3503), .B0(n1766), .Y(n1767) );
AOI222X1TS U1414 ( .A0(n3617), .A1(n3958), .B0(n3605), .B1(n3957), .C0(n3615), .C1(n3899), .Y(n3606) );
CLKAND2X2TS U1415 ( .A(n3295), .B(n4090), .Y(n2992) );
OAI21XLTS U1416 ( .A0(n3249), .A1(n3640), .B0(n2477), .Y(n2478) );
OAI21XLTS U1417 ( .A0(n3288), .A1(n3475), .B0(n1927), .Y(n1928) );
OAI21XLTS U1418 ( .A0(n3960), .A1(n3580), .B0(n3579), .Y(n3581) );
CLKAND2X2TS U1419 ( .A(n3295), .B(n3717), .Y(n2996) );
OAI21XLTS U1420 ( .A0(n3949), .A1(n2665), .B0(n2417), .Y(n2418) );
AOI222X1TS U1421 ( .A0(n3523), .A1(n3980), .B0(n3522), .B1(n3308), .C0(n3527), .C1(n3307), .Y(n1582) );
CLKAND2X2TS U1422 ( .A(n3295), .B(n3720), .Y(n3026) );
OAI21XLTS U1423 ( .A0(n4057), .A1(n2796), .B0(n1935), .Y(n1936) );
OAI21XLTS U1424 ( .A0(n4086), .A1(n3475), .B0(n1567), .Y(n1568) );
OAI21XLTS U1425 ( .A0(n3266), .A1(n2757), .B0(n2514), .Y(n2515) );
CLKAND2X2TS U1426 ( .A(n3295), .B(n3297), .Y(n3003) );
OAI21XLTS U1427 ( .A0(n3940), .A1(n2665), .B0(n2173), .Y(n2174) );
CLKAND2X2TS U1428 ( .A(n3295), .B(n3294), .Y(n3296) );
CLKAND2X2TS U1429 ( .A(n3295), .B(n3877), .Y(n3286) );
OR2X1TS U1430 ( .A(n3272), .B(n3872), .Y(n1831) );
OAI21X1TS U1431 ( .A0(n2007), .A1(n847), .B0(n846), .Y(n1829) );
CLKAND2X2TS U1432 ( .A(n4048), .B(n3307), .Y(n3030) );
OAI21XLTS U1433 ( .A0(n3940), .A1(n3544), .B0(n2343), .Y(n2345) );
CLKAND2X2TS U1434 ( .A(n3295), .B(n3808), .Y(n3000) );
AOI222X1TS U1435 ( .A0(n3523), .A1(n3958), .B0(n3522), .B1(n3957), .C0(n3527), .C1(n3899), .Y(n1931) );
OAI21XLTS U1436 ( .A0(n633), .A1(n3619), .B0(n3600), .Y(n3601) );
OAI21XLTS U1437 ( .A0(n3988), .A1(n3281), .B0(n1580), .Y(n1581) );
AOI222X1TS U1438 ( .A0(n3465), .A1(n3986), .B0(n3279), .B1(n3985), .C0(n3471), .C1(n3301), .Y(n1580) );
OAI21XLTS U1439 ( .A0(n3249), .A1(n3592), .B0(n2247), .Y(n2248) );
CLKAND2X2TS U1440 ( .A(n4048), .B(n3034), .Y(n865) );
AOI222X1TS U1441 ( .A0(n3494), .A1(n3958), .B0(n3500), .B1(n3957), .C0(n3499), .C1(n3899), .Y(n877) );
CLKAND2X2TS U1442 ( .A(n4048), .B(n3301), .Y(n873) );
CLKAND2X2TS U1443 ( .A(n4048), .B(n3015), .Y(n3016) );
OAI21XLTS U1444 ( .A0(n3940), .A1(n3487), .B0(n2768), .Y(n2770) );
OAI21XLTS U1445 ( .A0(n3914), .A1(n2757), .B0(n2446), .Y(n2447) );
NOR2X1TS U1446 ( .A(n822), .B(n886), .Y(n831) );
NAND2X1TS U1447 ( .A(n3872), .B(n3247), .Y(n2008) );
OAI21X1TS U1448 ( .A0(n2007), .A1(n2006), .B0(n2005), .Y(n2279) );
OAI21X1TS U1449 ( .A0(n1724), .A1(n1211), .B0(n1210), .Y(n1281) );
OAI21X1TS U1450 ( .A0(n1724), .A1(n1247), .B0(n1246), .Y(n1645) );
OAI21X1TS U1451 ( .A0(n1724), .A1(n1204), .B0(n1203), .Y(n1479) );
OAI21X1TS U1452 ( .A0(n1724), .A1(n1123), .B0(n1122), .Y(n1136) );
NAND2X1TS U1453 ( .A(n1229), .B(n1232), .Y(n1116) );
NAND2X1TS U1454 ( .A(n3184), .B(n2946), .Y(n1018) );
OAI21XLTS U1455 ( .A0(n3249), .A1(n3880), .B0(n2400), .Y(n2401) );
AOI222X1TS U1456 ( .A0(n4036), .A1(n2743), .B0(n3878), .B1(n2742), .C0(n3867), .C1(n3247), .Y(n2400) );
OAI21XLTS U1457 ( .A0(n3960), .A1(n3158), .B0(n1988), .Y(n1989) );
OAI21XLTS U1458 ( .A0(n4142), .A1(n3640), .B0(n1338), .Y(n1339) );
OAI21XLTS U1459 ( .A0(n3288), .A1(n3691), .B0(n1844), .Y(n1845) );
OAI21XLTS U1460 ( .A0(n3662), .A1(n3661), .B0(n3660), .Y(n3664) );
OAI21XLTS U1461 ( .A0(n3002), .A1(n3725), .B0(n1539), .Y(n1541) );
OAI21XLTS U1462 ( .A0(n3310), .A1(n3076), .B0(n2216), .Y(n2217) );
OAI21XLTS U1463 ( .A0(n4086), .A1(n3691), .B0(n1507), .Y(n1508) );
OAI21XLTS U1464 ( .A0(n4120), .A1(n3640), .B0(n1439), .Y(n1440) );
OAI21XLTS U1465 ( .A0(n643), .A1(n3715), .B0(n2338), .Y(n2339) );
OAI21XLTS U1466 ( .A0(n644), .A1(n3661), .B0(n3655), .Y(n3656) );
OAI21XLTS U1467 ( .A0(n3949), .A1(n2757), .B0(n2562), .Y(n2563) );
OAI21XLTS U1468 ( .A0(n3002), .A1(n3556), .B0(n1562), .Y(n1563) );
OAI21XLTS U1469 ( .A0(n3266), .A1(n3725), .B0(n2422), .Y(n2423) );
OAI21XLTS U1470 ( .A0(n3969), .A1(n3076), .B0(n2350), .Y(n2351) );
AOI222X1TS U1471 ( .A0(n3732), .A1(n3967), .B0(n3743), .B1(n3966), .C0(n3748), .C1(n3017), .Y(n2350) );
OAI21XLTS U1472 ( .A0(n643), .A1(n3140), .B0(n2452), .Y(n2453) );
OAI21XLTS U1473 ( .A0(n636), .A1(n3766), .B0(n2315), .Y(n2316) );
AOI222X1TS U1474 ( .A0(n3773), .A1(n3953), .B0(n3768), .B1(n3952), .C0(n3778), .C1(n3963), .Y(n2315) );
OAI21XLTS U1475 ( .A0(n644), .A1(n3640), .B0(n1821), .Y(n1822) );
OAI21XLTS U1476 ( .A0(n3310), .A1(n3715), .B0(n2376), .Y(n2377) );
OAI21XLTS U1477 ( .A0(n4155), .A1(n3640), .B0(n1441), .Y(n1442) );
OAI21XLTS U1478 ( .A0(n3288), .A1(n3661), .B0(n1999), .Y(n2000) );
OAI21XLTS U1479 ( .A0(n639), .A1(n3076), .B0(n2535), .Y(n2536) );
OAI21XLTS U1480 ( .A0(n3960), .A1(n3770), .B0(n3769), .Y(n3771) );
OAI21XLTS U1481 ( .A0(n4142), .A1(n3619), .B0(n3365), .Y(n3366) );
AOI222X1TS U1482 ( .A0(n3617), .A1(n4151), .B0(n3616), .B1(n4140), .C0(n3615), .C1(n4139), .Y(n3365) );
OAI21XLTS U1483 ( .A0(n3662), .A1(n3640), .B0(n2360), .Y(n2361) );
OAI21XLTS U1484 ( .A0(n3988), .A1(n3715), .B0(n2133), .Y(n2134) );
OAI21XLTS U1485 ( .A0(n642), .A1(n3691), .B0(n3684), .Y(n3686) );
OAI21XLTS U1486 ( .A0(n3249), .A1(n3845), .B0(n2469), .Y(n2470) );
OAI21XLTS U1487 ( .A0(n4086), .A1(n3661), .B0(n1504), .Y(n1506) );
OAI21XLTS U1488 ( .A0(n3002), .A1(n3691), .B0(n1467), .Y(n1469) );
OAI21XLTS U1489 ( .A0(n3266), .A1(n3864), .B0(n2481), .Y(n2482) );
AOI222X1TS U1490 ( .A0(n4036), .A1(n3264), .B0(n3878), .B1(n3263), .C0(n3867), .C1(n3262), .Y(n2481) );
OAI21XLTS U1491 ( .A0(n3978), .A1(n3076), .B0(n2121), .Y(n2122) );
AOI222X1TS U1492 ( .A0(n3732), .A1(n3976), .B0(n3743), .B1(n3975), .C0(n3739), .C1(n3278), .Y(n2121) );
OAI21XLTS U1493 ( .A0(n3940), .A1(n3829), .B0(n2384), .Y(n2385) );
OAI21XLTS U1494 ( .A0(n3870), .A1(n3880), .B0(n3869), .Y(n3871) );
AOI222X1TS U1495 ( .A0(n4036), .A1(n3927), .B0(n3878), .B1(n3868), .C0(n3867), .C1(n3866), .Y(n3869) );
OAI21XLTS U1496 ( .A0(n640), .A1(n3691), .B0(n3690), .Y(n3693) );
OAI21XLTS U1497 ( .A0(n3969), .A1(n3770), .B0(n2105), .Y(n2106) );
OAI21XLTS U1498 ( .A0(n4142), .A1(n3592), .B0(n1400), .Y(n1401) );
OAI21XLTS U1499 ( .A0(n3288), .A1(n3640), .B0(n1976), .Y(n1977) );
OAI21XLTS U1500 ( .A0(n3662), .A1(n3619), .B0(n3618), .Y(n3621) );
AOI222X1TS U1501 ( .A0(n3617), .A1(n4166), .B0(n3616), .B1(n4164), .C0(n3615), .C1(n3720), .Y(n3618) );
OAI21XLTS U1502 ( .A0(n4120), .A1(n3592), .B0(n1607), .Y(n1608) );
OAI21XLTS U1503 ( .A0(n644), .A1(n3619), .B0(n3613), .Y(n3614) );
AOI222X1TS U1504 ( .A0(n3617), .A1(n4115), .B0(n3616), .B1(n4114), .C0(n3615), .C1(n3717), .Y(n3613) );
OAI21XLTS U1505 ( .A0(n3002), .A1(n3661), .B0(n1751), .Y(n1752) );
OAI21XLTS U1506 ( .A0(n4086), .A1(n3640), .B0(n1660), .Y(n1661) );
OAI21XLTS U1507 ( .A0(n3978), .A1(n3715), .B0(n2336), .Y(n2337) );
OAI21XLTS U1508 ( .A0(n3310), .A1(n3140), .B0(n2286), .Y(n2287) );
OAI21XLTS U1509 ( .A0(n3266), .A1(n3829), .B0(n2560), .Y(n2561) );
OAI21XLTS U1510 ( .A0(n638), .A1(n3813), .B0(n3806), .Y(n3807) );
OAI21XLTS U1511 ( .A0(n3249), .A1(n3813), .B0(n2744), .Y(n2745) );
OAI21XLTS U1512 ( .A0(n3988), .A1(n3140), .B0(n2495), .Y(n2496) );
OAI21XLTS U1513 ( .A0(n3960), .A1(n3076), .B0(n2533), .Y(n2534) );
OAI21XLTS U1514 ( .A0(n3208), .A1(n3955), .B0(n2358), .Y(n2359) );
OAI21XLTS U1515 ( .A0(n3232), .A1(n3864), .B0(n2485), .Y(n2486) );
OAI21XLTS U1516 ( .A0(n633), .A1(n3829), .B0(n3828), .Y(n3830) );
OAI21XLTS U1517 ( .A0(n3288), .A1(n3619), .B0(n2398), .Y(n2399) );
AOI222X1TS U1518 ( .A0(n3617), .A1(n2397), .B0(n3616), .B1(n2396), .C0(n3615), .C1(n3294), .Y(n2398) );
OAI21XLTS U1519 ( .A0(n639), .A1(n3140), .B0(n2537), .Y(n2538) );
OAI21XLTS U1520 ( .A0(n3960), .A1(n3715), .B0(n3714), .Y(n3716) );
OAI21XLTS U1521 ( .A0(n4142), .A1(n3556), .B0(n3345), .Y(n3346) );
OAI21XLTS U1522 ( .A0(n3662), .A1(n3592), .B0(n2708), .Y(n2709) );
OAI21XLTS U1523 ( .A0(n641), .A1(n3715), .B0(n2763), .Y(n2764) );
OAI21XLTS U1524 ( .A0(n3925), .A1(n3955), .B0(n3924), .Y(n3926) );
OAI21XLTS U1525 ( .A0(n2967), .A1(n3864), .B0(n2585), .Y(n2586) );
OAI21XLTS U1526 ( .A0(n638), .A1(n3766), .B0(n3765), .Y(n3767) );
OAI21XLTS U1527 ( .A0(n3978), .A1(n3140), .B0(n2641), .Y(n2642) );
AOI222X1TS U1528 ( .A0(n3665), .A1(n3976), .B0(n3682), .B1(n3975), .C0(n3677), .C1(n3278), .Y(n2641) );
OAI21XLTS U1529 ( .A0(n3266), .A1(n3798), .B0(n2775), .Y(n2776) );
OAI21XLTS U1530 ( .A0(n4086), .A1(n3619), .B0(n1743), .Y(n1744) );
AOI222X1TS U1531 ( .A0(n3617), .A1(n4084), .B0(n3616), .B1(n4083), .C0(n3615), .C1(n3297), .Y(n1743) );
OAI21XLTS U1532 ( .A0(n3002), .A1(n3640), .B0(n1913), .Y(n1914) );
OAI21XLTS U1533 ( .A0(n637), .A1(n3140), .B0(n2610), .Y(n2611) );
OAI21XLTS U1534 ( .A0(n2973), .A1(n3829), .B0(n2415), .Y(n2416) );
OAI21XLTS U1535 ( .A0(n3969), .A1(n3715), .B0(n2374), .Y(n2375) );
OAI21XLTS U1536 ( .A0(n3870), .A1(n3813), .B0(n3800), .Y(n3802) );
OAI21XLTS U1537 ( .A0(n640), .A1(n3640), .B0(n3639), .Y(n3642) );
OAI21XLTS U1538 ( .A0(n4120), .A1(n3691), .B0(n1471), .Y(n1472) );
OAI21XLTS U1539 ( .A0(n643), .A1(n3770), .B0(n2548), .Y(n2549) );
OAI21XLTS U1540 ( .A0(n644), .A1(n3725), .B0(n3718), .Y(n3719) );
OAI21XLTS U1541 ( .A0(n3288), .A1(n3752), .B0(n2364), .Y(n2365) );
OAI21XLTS U1542 ( .A0(n4142), .A1(n3691), .B0(n1363), .Y(n1364) );
OAI21XLTS U1543 ( .A0(n3662), .A1(n3725), .B0(n3724), .Y(n3727) );
OAI21XLTS U1544 ( .A0(n635), .A1(n3770), .B0(n2206), .Y(n2207) );
OAI21XLTS U1545 ( .A0(n3914), .A1(n3880), .B0(n1570), .Y(n1571) );
OAI21XLTS U1546 ( .A0(n626), .A1(n2796), .B0(n2261), .Y(n2262) );
OAI21XLTS U1547 ( .A0(n3870), .A1(n3725), .B0(n3709), .Y(n3711) );
OAI21XLTS U1548 ( .A0(n643), .A1(n3580), .B0(n2330), .Y(n2331) );
AOI222X1TS U1549 ( .A0(n3584), .A1(n3992), .B0(n3583), .B1(n3991), .C0(n3574), .C1(n3031), .Y(n2330) );
OAI21XLTS U1550 ( .A0(n640), .A1(n3556), .B0(n2089), .Y(n2090) );
OAI21XLTS U1551 ( .A0(n3940), .A1(n3675), .B0(n2212), .Y(n2213) );
OAI21XLTS U1552 ( .A0(n636), .A1(n2757), .B0(n1497), .Y(n1498) );
OAI21XLTS U1553 ( .A0(n633), .A1(n3745), .B0(n3737), .Y(n3738) );
OAI21XLTS U1554 ( .A0(n3208), .A1(n3829), .B0(n1664), .Y(n1665) );
OAI21XLTS U1555 ( .A0(n3232), .A1(n3782), .B0(n1819), .Y(n1820) );
AOI222X1TS U1556 ( .A0(n2424), .A1(n2645), .B0(n3758), .B1(n2644), .C0(n3778), .C1(n2643), .Y(n1819) );
AOI222X1TS U1557 ( .A0(n3632), .A1(n3976), .B0(n3631), .B1(n3975), .C0(n3636), .C1(n3278), .Y(n1760) );
AOI222X1TS U1558 ( .A0(n3617), .A1(n3980), .B0(n3616), .B1(n3308), .C0(n3615), .C1(n3307), .Y(n1714) );
OAI21XLTS U1559 ( .A0(n2692), .A1(n3140), .B0(n2718), .Y(n2719) );
OAI21XLTS U1560 ( .A0(n642), .A1(n3592), .B0(n3585), .Y(n3587) );
OAI21XLTS U1561 ( .A0(n3909), .A1(n2796), .B0(n1711), .Y(n1712) );
OAI21XLTS U1562 ( .A0(n628), .A1(n2623), .B0(n2608), .Y(n2609) );
OAI21XLTS U1563 ( .A0(n631), .A1(n3798), .B0(n3791), .Y(n3792) );
OAI21XLTS U1564 ( .A0(n3925), .A1(n4038), .B0(n1654), .Y(n1655) );
OAI21XLTS U1565 ( .A0(n2945), .A1(n3955), .B0(n2021), .Y(n2022) );
OAI21XLTS U1566 ( .A0(n638), .A1(n3702), .B0(n2309), .Y(n2310) );
OAI21XLTS U1567 ( .A0(n3002), .A1(n3592), .B0(n1443), .Y(n1445) );
OAI21XLTS U1568 ( .A0(n4086), .A1(n3556), .B0(n1437), .Y(n1438) );
OAI21XLTS U1569 ( .A0(n3266), .A1(n3745), .B0(n1728), .Y(n1729) );
AOI222X1TS U1570 ( .A0(n3617), .A1(n3992), .B0(n3616), .B1(n3991), .C0(n3615), .C1(n3031), .Y(n1811) );
OAI21XLTS U1571 ( .A0(n644), .A1(n3556), .B0(n3550), .Y(n3551) );
OAI21XLTS U1572 ( .A0(n3940), .A1(n3702), .B0(n2129), .Y(n2130) );
OAI21XLTS U1573 ( .A0(n636), .A1(n3679), .B0(n1692), .Y(n1693) );
OAI21XLTS U1574 ( .A0(n640), .A1(n3592), .B0(n3591), .Y(n3594) );
OAI21XLTS U1575 ( .A0(n630), .A1(n3864), .B0(n3851), .Y(n3852) );
OAI21XLTS U1576 ( .A0(n637), .A1(n3122), .B0(n1817), .Y(n1818) );
AOI222X1TS U1577 ( .A0(n3632), .A1(n3982), .B0(n3631), .B1(n3981), .C0(n3636), .C1(n3034), .Y(n1817) );
OAI21XLTS U1578 ( .A0(n3870), .A1(n3752), .B0(n3740), .Y(n3741) );
OAI21XLTS U1579 ( .A0(n3914), .A1(n2796), .B0(n1565), .Y(n1566) );
OAI21XLTS U1580 ( .A0(n2973), .A1(n3770), .B0(n1621), .Y(n1623) );
OAI21XLTS U1581 ( .A0(n629), .A1(n3756), .B0(n2029), .Y(n2030) );
OAI21XLTS U1582 ( .A0(n634), .A1(n3829), .B0(n3821), .Y(n3822) );
OAI21XLTS U1583 ( .A0(n636), .A1(n3702), .B0(n2672), .Y(n2673) );
AOI222X1TS U1584 ( .A0(n3713), .A1(n3953), .B0(n3712), .B1(n3952), .C0(n3721), .C1(n3008), .Y(n2672) );
OAI21XLTS U1585 ( .A0(n3870), .A1(n3782), .B0(n3761), .Y(n3763) );
OAI21XLTS U1586 ( .A0(n3310), .A1(n3122), .B0(n3097), .Y(n3098) );
AOI222X1TS U1587 ( .A0(n3632), .A1(n3980), .B0(n3631), .B1(n3308), .C0(n3636), .C1(n3307), .Y(n3097) );
AOI222X1TS U1588 ( .A0(n3632), .A1(n3992), .B0(n3631), .B1(n3991), .C0(n3636), .C1(n3031), .Y(n2573) );
OAI21XLTS U1589 ( .A0(n3969), .A1(n3140), .B0(n2340), .Y(n2341) );
OAI21XLTS U1590 ( .A0(n644), .A1(n3592), .B0(n1890), .Y(n1891) );
OAI21XLTS U1591 ( .A0(n3208), .A1(n2796), .B0(n2503), .Y(n2504) );
OAI21XLTS U1592 ( .A0(n642), .A1(n3640), .B0(n3633), .Y(n3635) );
AOI222X1TS U1593 ( .A0(n3632), .A1(n3997), .B0(n3631), .B1(n3996), .C0(n3630), .C1(n3808), .Y(n3633) );
OAI21XLTS U1594 ( .A0(n3232), .A1(n3829), .B0(n2646), .Y(n2647) );
OAI21XLTS U1595 ( .A0(n3249), .A1(n3782), .B0(n2738), .Y(n2739) );
OAI21XLTS U1596 ( .A0(n3249), .A1(n3752), .B0(n2139), .Y(n2140) );
OAI21XLTS U1597 ( .A0(n3988), .A1(n3122), .B0(n1865), .Y(n1866) );
AOI222X1TS U1598 ( .A0(n3632), .A1(n3986), .B0(n3631), .B1(n3985), .C0(n3636), .C1(n3301), .Y(n1865) );
OAI21XLTS U1599 ( .A0(n3949), .A1(n3702), .B0(n2676), .Y(n2677) );
AOI222X1TS U1600 ( .A0(n3713), .A1(n3947), .B0(n3712), .B1(n3946), .C0(n3721), .C1(n3020), .Y(n2676) );
OAI21XLTS U1601 ( .A0(n4086), .A1(n3592), .B0(n1616), .Y(n1617) );
OAI21XLTS U1602 ( .A0(n3266), .A1(n3766), .B0(n2612), .Y(n2613) );
OAI21XLTS U1603 ( .A0(n642), .A1(n3619), .B0(n3611), .Y(n3612) );
OAI21XLTS U1604 ( .A0(n3208), .A1(n3864), .B0(n1871), .Y(n1872) );
OAI21XLTS U1605 ( .A0(n633), .A1(n3782), .B0(n3759), .Y(n3760) );
OAI21XLTS U1606 ( .A0(n631), .A1(n3829), .B0(n3823), .Y(n3824) );
OAI21XLTS U1607 ( .A0(n3909), .A1(n3955), .B0(n3908), .Y(n3910) );
OAI21XLTS U1608 ( .A0(n638), .A1(n3745), .B0(n3744), .Y(n3747) );
OAI21XLTS U1609 ( .A0(n3002), .A1(n3619), .B0(n1604), .Y(n1606) );
AOI222X1TS U1610 ( .A0(n3617), .A1(n3990), .B0(n3598), .B1(n1912), .C0(n3615), .C1(n3289), .Y(n1604) );
OAI21XLTS U1611 ( .A0(n2967), .A1(n3829), .B0(n2298), .Y(n2299) );
AOI222X1TS U1612 ( .A0(n3831), .A1(n2584), .B0(n3835), .B1(n2583), .C0(n3841), .C1(n2645), .Y(n2298) );
OAI21XLTS U1613 ( .A0(n640), .A1(n3619), .B0(n2698), .Y(n2699) );
AOI222X1TS U1614 ( .A0(n3617), .A1(n4002), .B0(n3598), .B1(n4001), .C0(n3615), .C1(n3877), .Y(n2698) );
OAI21XLTS U1615 ( .A0(n3940), .A1(n3745), .B0(n2771), .Y(n2772) );
OAI21XLTS U1616 ( .A0(n3914), .A1(n3955), .B0(n3913), .Y(n3915) );
OAI21XLTS U1617 ( .A0(n3969), .A1(n3158), .B0(n2095), .Y(n2096) );
OAI21XLTS U1618 ( .A0(n643), .A1(n3076), .B0(n2386), .Y(n2387) );
OAI21XLTS U1619 ( .A0(n644), .A1(n3691), .B0(n1666), .Y(n1667) );
OAI21XLTS U1620 ( .A0(n3002), .A1(n3752), .B0(n1595), .Y(n1597) );
OAI21XLTS U1621 ( .A0(n4086), .A1(n3725), .B0(n1578), .Y(n1579) );
OAI21XLTS U1622 ( .A0(n3266), .A1(n3955), .B0(n2657), .Y(n2658) );
OAI21XLTS U1623 ( .A0(n3310), .A1(n3770), .B0(n2450), .Y(n2451) );
OAI21XLTS U1624 ( .A0(n3288), .A1(n3813), .B0(n1925), .Y(n1926) );
OAI21XLTS U1625 ( .A0(n4142), .A1(n3752), .B0(n1327), .Y(n1328) );
OAI21XLTS U1626 ( .A0(n3662), .A1(n3782), .B0(n3781), .Y(n3784) );
OR2X1TS U1627 ( .A(n3034), .B(n3278), .Y(n1512) );
OR2X1TS U1628 ( .A(n3278), .B(n3012), .Y(n1515) );
OAI21X1TS U1629 ( .A0(n2007), .A1(n861), .B0(n860), .Y(n1513) );
NOR2X2TS U1630 ( .A(n861), .B(n811), .Y(n1542) );
NOR2X2TS U1631 ( .A(n842), .B(n827), .Y(n2003) );
NOR2X1TS U1632 ( .A(n1370), .B(n798), .Y(n1387) );
NAND2X1TS U1633 ( .A(n1942), .B(n1945), .Y(n1389) );
OAI21X1TS U1634 ( .A0(n1371), .A1(n798), .B0(n797), .Y(n1386) );
NAND2X1TS U1635 ( .A(n1478), .B(n1481), .Y(n909) );
NAND2X1TS U1636 ( .A(n1135), .B(n1138), .Y(n915) );
NOR2X1TS U1637 ( .A(n965), .B(n963), .Y(n929) );
NOR2X2TS U1638 ( .A(n1211), .B(n905), .Y(n1244) );
NOR2X1TS U1639 ( .A(n1199), .B(n909), .Y(n911) );
OAI21XLTS U1640 ( .A0(n641), .A1(n3122), .B0(n2253), .Y(n2254) );
AOI222X1TS U1641 ( .A0(n3632), .A1(n3963), .B0(n2778), .B1(n3962), .C0(n3636), .C1(n3015), .Y(n2253) );
OAI21XLTS U1642 ( .A0(n3925), .A1(n3845), .B0(n1747), .Y(n1748) );
OAI21XLTS U1643 ( .A0(n627), .A1(n2623), .B0(n2622), .Y(n2624) );
OAI21XLTS U1644 ( .A0(n629), .A1(n3745), .B0(n2214), .Y(n2215) );
OAI21XLTS U1645 ( .A0(n634), .A1(n3798), .B0(n3789), .Y(n3790) );
NAND2X1TS U1646 ( .A(n3877), .B(n3289), .Y(n1599) );
OR2X1TS U1647 ( .A(n3031), .B(n3307), .Y(n1392) );
OR2X1TS U1648 ( .A(n3289), .B(n3808), .Y(n1945) );
OR2X1TS U1649 ( .A(n3877), .B(n3289), .Y(n1942) );
OAI21XLTS U1650 ( .A0(n635), .A1(n3745), .B0(n3735), .Y(n3736) );
OAI21XLTS U1651 ( .A0(n3249), .A1(n3691), .B0(n2467), .Y(n2468) );
OAI21XLTS U1652 ( .A0(n3960), .A1(n3122), .B0(n1972), .Y(n1973) );
AOI222X1TS U1653 ( .A0(n3638), .A1(n3958), .B0(n2778), .B1(n3957), .C0(n3636), .C1(n3899), .Y(n1972) );
OAI21XLTS U1654 ( .A0(n4155), .A1(n3503), .B0(n3110), .Y(n3111) );
OAI21XLTS U1655 ( .A0(n2692), .A1(n2757), .B0(n2241), .Y(n2242) );
AOI222X1TS U1656 ( .A0(n3659), .A1(n3943), .B0(n3643), .B1(n3942), .C0(n3657), .C1(n3024), .Y(n2241) );
OAI21XLTS U1657 ( .A0(n3909), .A1(n3880), .B0(n1900), .Y(n1901) );
AOI222X1TS U1658 ( .A0(n3617), .A1(n3972), .B0(n3616), .B1(n3971), .C0(n3615), .C1(n3012), .Y(n2317) );
OAI21XLTS U1659 ( .A0(n3208), .A1(n3798), .B0(n2015), .Y(n2016) );
OAI21XLTS U1660 ( .A0(n633), .A1(n3706), .B0(n3705), .Y(n3707) );
OAI21XLTS U1661 ( .A0(n631), .A1(n3756), .B0(n3755), .Y(n3757) );
OAI21XLTS U1662 ( .A0(n637), .A1(n3580), .B0(n1853), .Y(n1854) );
OAI21XLTS U1663 ( .A0(n640), .A1(n3531), .B0(n3530), .Y(n3533) );
AOI222X1TS U1664 ( .A0(n3529), .A1(n4002), .B0(n3528), .B1(n4001), .C0(n3527), .C1(n3877), .Y(n3530) );
OAI21XLTS U1665 ( .A0(n3870), .A1(n3691), .B0(n2296), .Y(n2297) );
OAI21XLTS U1666 ( .A0(n636), .A1(n3640), .B0(n2143), .Y(n2144) );
AOI222X1TS U1667 ( .A0(n3632), .A1(n3953), .B0(n2778), .B1(n3952), .C0(n2777), .C1(n3008), .Y(n2143) );
OAI21XLTS U1668 ( .A0(n2973), .A1(n3715), .B0(n1958), .Y(n1959) );
OAI21XLTS U1669 ( .A0(n632), .A1(n3955), .B0(n2512), .Y(n2513) );
AO21XLTS U1670 ( .A0(n4130), .A1(n4047), .B0(n4167), .Y(n2511) );
OAI21XLTS U1671 ( .A0(n626), .A1(n3875), .B0(n2171), .Y(n2172) );
OAI21XLTS U1672 ( .A0(n2692), .A1(n3628), .B0(n2779), .Y(n2780) );
OAI21XLTS U1673 ( .A0(n3909), .A1(n3829), .B0(n1956), .Y(n1957) );
OAI21XLTS U1674 ( .A0(n3002), .A1(n3531), .B0(n1448), .Y(n1449) );
AOI222X1TS U1675 ( .A0(n3529), .A1(n3990), .B0(n3528), .B1(n1912), .C0(n3527), .C1(n3289), .Y(n1448) );
OAI21XLTS U1676 ( .A0(n2945), .A1(n3880), .B0(n2204), .Y(n2205) );
OAI21XLTS U1677 ( .A0(n3925), .A1(n3813), .B0(n1681), .Y(n1682) );
OAI21XLTS U1678 ( .A0(n2967), .A1(n3752), .B0(n1974), .Y(n1975) );
AOI222X1TS U1679 ( .A0(n3617), .A1(n3963), .B0(n3605), .B1(n3962), .C0(n3615), .C1(n3015), .Y(n2087) );
OAI21XLTS U1680 ( .A0(n625), .A1(n2660), .B0(n2125), .Y(n2126) );
OAI21XLTS U1681 ( .A0(n629), .A1(n3702), .B0(n3701), .Y(n3703) );
OAI21XLTS U1682 ( .A0(n633), .A1(n3675), .B0(n3674), .Y(n3676) );
OAI21XLTS U1683 ( .A0(n642), .A1(n3531), .B0(n3524), .Y(n3526) );
OAI21XLTS U1684 ( .A0(n3208), .A1(n3766), .B0(n2045), .Y(n2046) );
OAI21XLTS U1685 ( .A0(n640), .A1(n3503), .B0(n1997), .Y(n1998) );
OAI21XLTS U1686 ( .A0(n3249), .A1(n3661), .B0(n2181), .Y(n2182) );
OAI21XLTS U1687 ( .A0(n628), .A1(n3880), .B0(n2618), .Y(n2619) );
OAI21XLTS U1688 ( .A0(n626), .A1(n3833), .B0(n2269), .Y(n2270) );
OAI21XLTS U1689 ( .A0(n635), .A1(n3702), .B0(n3699), .Y(n3700) );
OAI21XLTS U1690 ( .A0(n636), .A1(n2665), .B0(n2103), .Y(n2104) );
OAI21XLTS U1691 ( .A0(n3914), .A1(n3798), .B0(n1978), .Y(n1979) );
AOI222X1TS U1692 ( .A0(n3535), .A1(n3982), .B0(n3553), .B1(n3981), .C0(n3552), .C1(n3034), .Y(n2237) );
OAI21XLTS U1693 ( .A0(n632), .A1(n3896), .B0(n2519), .Y(n2520) );
AO21XLTS U1694 ( .A0(n4098), .A1(n4047), .B0(n4106), .Y(n2518) );
OAI21XLTS U1695 ( .A0(n3870), .A1(n3661), .B0(n2736), .Y(n2737) );
AOI222X1TS U1696 ( .A0(n3689), .A1(n2643), .B0(n3688), .B1(n2429), .C0(n3687), .C1(n2981), .Y(n1694) );
OAI21XLTS U1697 ( .A0(n640), .A1(n3475), .B0(n3474), .Y(n3477) );
OAI21XLTS U1698 ( .A0(n628), .A1(n3829), .B0(n2577), .Y(n2578) );
OAI21XLTS U1699 ( .A0(n631), .A1(n3702), .B0(n2184), .Y(n2185) );
OAI21XLTS U1700 ( .A0(n642), .A1(n3503), .B0(n3495), .Y(n3496) );
OAI21XLTS U1701 ( .A0(n2692), .A1(n2665), .B0(n2294), .Y(n2295) );
OAI21XLTS U1702 ( .A0(n3925), .A1(n3766), .B0(n1910), .Y(n1911) );
OAI21XLTS U1703 ( .A0(n3002), .A1(n3503), .B0(n1463), .Y(n1464) );
OAI21XLTS U1704 ( .A0(n2967), .A1(n3706), .B0(n1846), .Y(n1847) );
OAI21XLTS U1705 ( .A0(n2945), .A1(n3845), .B0(n2448), .Y(n2449) );
AOI222X1TS U1706 ( .A0(n3523), .A1(n3986), .B0(n3522), .B1(n3985), .C0(n3527), .C1(n3301), .Y(n1783) );
OAI21XLTS U1707 ( .A0(n4046), .A1(n3864), .B0(n2057), .Y(n2058) );
AOI222X1TS U1708 ( .A0(n4031), .A1(n2729), .B0(n4027), .B1(n700), .C0(n3873),
.C1(n4069), .Y(n2057) );
OAI21XLTS U1709 ( .A0(n641), .A1(n3580), .B0(n2033), .Y(n2034) );
OAI21XLTS U1710 ( .A0(n638), .A1(n3640), .B0(n2420), .Y(n2421) );
OAI21XLTS U1711 ( .A0(n4057), .A1(n3864), .B0(n1992), .Y(n1993) );
OAI21XLTS U1712 ( .A0(n3002), .A1(n3475), .B0(n1536), .Y(n1537) );
OAI21XLTS U1713 ( .A0(n3266), .A1(n3628), .B0(n2552), .Y(n2553) );
AOI222X1TS U1714 ( .A0(n3523), .A1(n3982), .B0(n3522), .B1(n3981), .C0(n3527), .C1(n3034), .Y(n2198) );
OAI21XLTS U1715 ( .A0(n632), .A1(n3864), .B0(n2531), .Y(n2532) );
AO21XLTS U1716 ( .A0(n4027), .A1(n4047), .B0(n4031), .Y(n2530) );
OAI21XLTS U1717 ( .A0(n3914), .A1(n3766), .B0(n1717), .Y(n1718) );
OAI21XLTS U1718 ( .A0(n626), .A1(n2649), .B0(n2388), .Y(n2389) );
OAI21XLTS U1719 ( .A0(n635), .A1(n3675), .B0(n3670), .Y(n3671) );
OAI21XLTS U1720 ( .A0(n638), .A1(n2665), .B0(n2581), .Y(n2582) );
AOI222X1TS U1721 ( .A0(n3617), .A1(n3933), .B0(n3616), .B1(n3932), .C0(n2663), .C1(n3872), .Y(n2581) );
OAI21XLTS U1722 ( .A0(n634), .A1(n3706), .B0(n3697), .Y(n3698) );
OAI21XLTS U1723 ( .A0(n2967), .A1(n3675), .B0(n2061), .Y(n2062) );
AOI222X1TS U1724 ( .A0(n3689), .A1(n2584), .B0(n3688), .B1(n2583), .C0(n3687), .C1(n2968), .Y(n2061) );
OAI21XLTS U1725 ( .A0(n2945), .A1(n3813), .B0(n2332), .Y(n2333) );
OAI21XLTS U1726 ( .A0(n3925), .A1(n3745), .B0(n1869), .Y(n1870) );
AOI222X1TS U1727 ( .A0(n3523), .A1(n3976), .B0(n3522), .B1(n3975), .C0(n3527), .C1(n3278), .Y(n1825) );
OAI21XLTS U1728 ( .A0(n627), .A1(n2660), .B0(n2659), .Y(n2662) );
OAI21XLTS U1729 ( .A0(n625), .A1(n3766), .B0(n2177), .Y(n2178) );
OAI21XLTS U1730 ( .A0(n638), .A1(n3576), .B0(n3575), .Y(n3577) );
OAI21XLTS U1731 ( .A0(n3310), .A1(n3281), .B0(n1739), .Y(n1740) );
AOI222X1TS U1732 ( .A0(n3465), .A1(n3980), .B0(n3279), .B1(n3308), .C0(n3471), .C1(n3307), .Y(n1739) );
AOI222X1TS U1733 ( .A0(n3494), .A1(n3976), .B0(n3500), .B1(n3975), .C0(n3499), .C1(n3278), .Y(n1968) );
OAI21XLTS U1734 ( .A0(n2973), .A1(n3628), .B0(n1950), .Y(n1951) );
AOI222X1TS U1735 ( .A0(n3632), .A1(n2643), .B0(n3637), .B1(n2429), .C0(n3630), .C1(n2981), .Y(n1950) );
OAI21XLTS U1736 ( .A0(n3870), .A1(n3619), .B0(n3602), .Y(n3604) );
AOI222X1TS U1737 ( .A0(n3617), .A1(n3927), .B0(n3616), .B1(n3868), .C0(n3609), .C1(n3866), .Y(n3602) );
OAI21XLTS U1738 ( .A0(n633), .A1(n3628), .B0(n3627), .Y(n3629) );
AOI222X1TS U1739 ( .A0(n3632), .A1(n3929), .B0(n3637), .B1(n3928), .C0(n3630), .C1(n3893), .Y(n3627) );
AOI222X1TS U1740 ( .A0(n3659), .A1(n2645), .B0(n3650), .B1(n2644), .C0(n3657), .C1(n3229), .Y(n2049) );
AOI222X1TS U1741 ( .A0(n3617), .A1(n2743), .B0(n3598), .B1(n2742), .C0(n3609), .C1(n3247), .Y(n2267) );
AOI222X1TS U1742 ( .A0(n3523), .A1(n3967), .B0(n3522), .B1(n3966), .C0(n3527), .C1(n3017), .Y(n2225) );
OAI21XLTS U1743 ( .A0(n643), .A1(n3281), .B0(n2372), .Y(n2373) );
AOI222X1TS U1744 ( .A0(n3455), .A1(n3992), .B0(n3279), .B1(n3991), .C0(n3471), .C1(n3031), .Y(n2372) );
OAI21XLTS U1745 ( .A0(n3208), .A1(n3702), .B0(n1789), .Y(n1790) );
OAI21XLTS U1746 ( .A0(n628), .A1(n3798), .B0(n2076), .Y(n2077) );
OAI21XLTS U1747 ( .A0(n3909), .A1(n3766), .B0(n1753), .Y(n1754) );
AOI222X1TS U1748 ( .A0(n3523), .A1(n3972), .B0(n3522), .B1(n3971), .C0(n3527), .C1(n3012), .Y(n2167) );
OAI21XLTS U1749 ( .A0(n636), .A1(n3544), .B0(n1898), .Y(n1899) );
OAI21XLTS U1750 ( .A0(n3914), .A1(n3745), .B0(n1734), .Y(n1735) );
OAI21XLTS U1751 ( .A0(n626), .A1(n3766), .B0(n1921), .Y(n1922) );
AO21XLTS U1752 ( .A0(n3129), .A1(n4047), .B0(n3831), .Y(n2636) );
OAI21XLTS U1753 ( .A0(n4057), .A1(n3845), .B0(n1800), .Y(n1801) );
OAI21XLTS U1754 ( .A0(n3266), .A1(n2665), .B0(n2145), .Y(n2146) );
AOI222X1TS U1755 ( .A0(n3617), .A1(n3264), .B0(n3598), .B1(n3263), .C0(n3609), .C1(n3262), .Y(n2145) );
OAI21XLTS U1756 ( .A0(n3208), .A1(n3675), .B0(n1842), .Y(n1843) );
AOI222X1TS U1757 ( .A0(n3523), .A1(n3963), .B0(n3522), .B1(n3962), .C0(n3527), .C1(n3015), .Y(n2302) );
OAI21XLTS U1758 ( .A0(n3925), .A1(n3702), .B0(n2113), .Y(n2114) );
OAI21XLTS U1759 ( .A0(n2967), .A1(n2757), .B0(n2037), .Y(n2038) );
AOI222X1TS U1760 ( .A0(n3651), .A1(n2584), .B0(n3650), .B1(n2583), .C0(n3657), .C1(n2968), .Y(n2037) );
AOI222X1TS U1761 ( .A0(n3632), .A1(n3859), .B0(n3637), .B1(n3858), .C0(n3630), .C1(n3857), .Y(n2239) );
OAI21XLTS U1762 ( .A0(n3232), .A1(n3628), .B0(n1636), .Y(n1637) );
AOI222X1TS U1763 ( .A0(n3632), .A1(n2645), .B0(n3637), .B1(n2644), .C0(n3630), .C1(n3229), .Y(n1636) );
CLKAND2X2TS U1764 ( .A(n4048), .B(n3031), .Y(n2998) );
OAI21XLTS U1765 ( .A0(n4057), .A1(n3798), .B0(n1730), .Y(n1731) );
OAI21XLTS U1766 ( .A0(n3266), .A1(n3576), .B0(n2159), .Y(n2160) );
OAI21XLTS U1767 ( .A0(n3925), .A1(n3691), .B0(n1877), .Y(n1878) );
AOI222X1TS U1768 ( .A0(n3523), .A1(n3947), .B0(n3273), .B1(n3946), .C0(n3518), .C1(n3020), .Y(n2208) );
OAI21XLTS U1769 ( .A0(n636), .A1(n3531), .B0(n1873), .Y(n1874) );
OAI21XLTS U1770 ( .A0(n3914), .A1(n3702), .B0(n1626), .Y(n1627) );
OAI21XLTS U1771 ( .A0(n628), .A1(n3756), .B0(n2425), .Y(n2426) );
OAI21XLTS U1772 ( .A0(n3870), .A1(n3592), .B0(n3572), .Y(n3573) );
OAI21XLTS U1773 ( .A0(n3249), .A1(n3556), .B0(n2165), .Y(n2166) );
OAI21XLTS U1774 ( .A0(n3208), .A1(n2757), .B0(n2043), .Y(n2044) );
OAI21XLTS U1775 ( .A0(n4046), .A1(n3782), .B0(n2025), .Y(n2026) );
AOI222X1TS U1776 ( .A0(n3773), .A1(n2729), .B0(n3758), .B1(Op_MY[50]), .C0(
n3778), .C1(n3235), .Y(n2025) );
OAI21XLTS U1777 ( .A0(n2967), .A1(n3628), .B0(n1672), .Y(n1673) );
OAI21XLTS U1778 ( .A0(n2945), .A1(n3745), .B0(n1896), .Y(n1897) );
OAI21XLTS U1779 ( .A0(n638), .A1(n3544), .B0(n2284), .Y(n2285) );
CLKAND2X2TS U1780 ( .A(n4048), .B(n3278), .Y(n3033) );
OAI21XLTS U1781 ( .A0(n3969), .A1(n3281), .B0(n2190), .Y(n2191) );
AOI222X1TS U1782 ( .A0(n3455), .A1(n3967), .B0(n3279), .B1(n3966), .C0(n3471), .C1(n3017), .Y(n2190) );
OAI21XLTS U1783 ( .A0(n3914), .A1(n3691), .B0(n2107), .Y(n2108) );
OAI21XLTS U1784 ( .A0(n638), .A1(n3531), .B0(n3519), .Y(n3520) );
OAI21XLTS U1785 ( .A0(n4057), .A1(n3766), .B0(n2454), .Y(n2455) );
OAI21XLTS U1786 ( .A0(n3266), .A1(n3544), .B0(n2704), .Y(n2705) );
OAI21XLTS U1787 ( .A0(n633), .A1(n3592), .B0(n3570), .Y(n3571) );
OAI21XLTS U1788 ( .A0(n2692), .A1(n3531), .B0(n2693), .Y(n2694) );
AOI222X1TS U1789 ( .A0(n3584), .A1(n2643), .B0(n3589), .B1(n2429), .C0(n3574), .C1(n2981), .Y(n2119) );
OAI21XLTS U1790 ( .A0(n3870), .A1(n3556), .B0(n3547), .Y(n3549) );
OAI21XLTS U1791 ( .A0(n632), .A1(n3756), .B0(n2409), .Y(n2410) );
AO21XLTS U1792 ( .A0(n3758), .A1(n4047), .B0(n2424), .Y(n2408) );
AOI222X1TS U1793 ( .A0(n3455), .A1(n3963), .B0(n3279), .B1(n3962), .C0(n3471), .C1(n3015), .Y(n2554) );
OAI21XLTS U1794 ( .A0(n3925), .A1(n2757), .B0(n2616), .Y(n2617) );
OAI21XLTS U1795 ( .A0(n2967), .A1(n3619), .B0(n2568), .Y(n2569) );
OAI21XLTS U1796 ( .A0(n634), .A1(n3628), .B0(n3623), .Y(n3624) );
OAI21XLTS U1797 ( .A0(n2945), .A1(n3702), .B0(n2432), .Y(n2433) );
OAI21XLTS U1798 ( .A0(n629), .A1(n3580), .B0(n3568), .Y(n3569) );
OAI21XLTS U1799 ( .A0(n627), .A1(n2734), .B0(n2724), .Y(n2725) );
CLKAND2X2TS U1800 ( .A(n4048), .B(n3017), .Y(n3010) );
OAI21XLTS U1801 ( .A0(n3960), .A1(n3281), .B0(n2394), .Y(n2395) );
AOI222X1TS U1802 ( .A0(n3455), .A1(n3958), .B0(n3279), .B1(n3957), .C0(n3471), .C1(n3899), .Y(n2394) );
OAI21XLTS U1803 ( .A0(n2692), .A1(n3487), .B0(n2566), .Y(n2567) );
OAI21XLTS U1804 ( .A0(n3208), .A1(n3628), .B0(n2540), .Y(n2541) );
OAI21XLTS U1805 ( .A0(n2952), .A1(n2757), .B0(n2756), .Y(n2759) );
AOI222X1TS U1806 ( .A0(n3651), .A1(n3918), .B0(n3643), .B1(n3917), .C0(n3657), .C1(n2950), .Y(n2756) );
OAI21XLTS U1807 ( .A0(n4046), .A1(n3752), .B0(n2710), .Y(n2711) );
OAI21XLTS U1808 ( .A0(n636), .A1(n4060), .B0(n2497), .Y(n2498) );
OAI21XLTS U1809 ( .A0(n3870), .A1(n3531), .B0(n3516), .Y(n3517) );
OAI21XLTS U1810 ( .A0(n2967), .A1(n3576), .B0(n2304), .Y(n2305) );
AOI222X1TS U1811 ( .A0(n3584), .A1(n2584), .B0(n3589), .B1(n2583), .C0(n3574), .C1(n2968), .Y(n2304) );
OAI21XLTS U1812 ( .A0(n629), .A1(n3544), .B0(n3540), .Y(n3541) );
CLKAND2X2TS U1813 ( .A(n4048), .B(n3899), .Y(n3005) );
OAI21XLTS U1814 ( .A0(n3925), .A1(n3628), .B0(n2235), .Y(n2236) );
OAI21XLTS U1815 ( .A0(n3870), .A1(n3503), .B0(n3490), .Y(n3492) );
AOI222X1TS U1816 ( .A0(n3723), .A1(n2729), .B0(n3704), .B1(n2728), .C0(n2751), .C1(n4069), .Y(n2730) );
OAI21XLTS U1817 ( .A0(n3208), .A1(n2665), .B0(n2380), .Y(n2381) );
OAI21XLTS U1818 ( .A0(n631), .A1(n3592), .B0(n3564), .Y(n3565) );
OAI21XLTS U1819 ( .A0(n3909), .A1(n2757), .B0(n2499), .Y(n2500) );
OAI21XLTS U1820 ( .A0(n3266), .A1(n3514), .B0(n3265), .Y(n3267) );
OAI21XLTS U1821 ( .A0(n633), .A1(n3514), .B0(n3513), .Y(n3515) );
CLKAND2X2TS U1822 ( .A(n4048), .B(n3272), .Y(n3023) );
OAI21XLTS U1823 ( .A0(n3208), .A1(n3576), .B0(n1815), .Y(n1816) );
OAI21XLTS U1824 ( .A0(n4057), .A1(n3725), .B0(n2392), .Y(n2393) );
OAI21XLTS U1825 ( .A0(n638), .A1(n4060), .B0(n2688), .Y(n2689) );
OAI21XLTS U1826 ( .A0(n3266), .A1(n3487), .B0(n2716), .Y(n2717) );
CLKINVX6TS U1827 ( .A(n1128), .Y(n3282) );
OAI21XLTS U1828 ( .A0(n3940), .A1(n4060), .B0(n3258), .Y(n3259) );
OAI21XLTS U1829 ( .A0(n3914), .A1(n3628), .B0(n2491), .Y(n2492) );
OAI21XLTS U1830 ( .A0(n2973), .A1(n3514), .B0(n2019), .Y(n2020) );
OAI21XLTS U1831 ( .A0(n626), .A1(n2757), .B0(n2313), .Y(n2314) );
CLKAND2X2TS U1832 ( .A(n4048), .B(n3020), .Y(n3007) );
OAI21XLTS U1833 ( .A0(n3925), .A1(n2665), .B0(n2229), .Y(n2230) );
OAI21XLTS U1834 ( .A0(n2967), .A1(n3544), .B0(n2368), .Y(n2369) );
AOI222X1TS U1835 ( .A0(n1452), .A1(n2584), .B0(n3542), .B1(n2583), .C0(n3546), .C1(n2968), .Y(n2368) );
CLKAND2X2TS U1836 ( .A(n3295), .B(n3247), .Y(n3062) );
CLKAND2X2TS U1837 ( .A(n4048), .B(n3872), .Y(n3028) );
OAI21XLTS U1838 ( .A0(n4046), .A1(n3675), .B0(n2620), .Y(n2621) );
AOI222X1TS U1839 ( .A0(n3683), .A1(n2729), .B0(n3688), .B1(Op_MY[50]), .C0(
n3677), .C1(n4069), .Y(n2620) );
AOI222X1TS U1840 ( .A0(n3523), .A1(n2645), .B0(n3528), .B1(n2644), .C0(n3521), .C1(n3229), .Y(n2362) );
OAI21XLTS U1841 ( .A0(n2967), .A1(n3514), .B0(n1488), .Y(n1489) );
OAI21XLTS U1842 ( .A0(n3925), .A1(n3576), .B0(n1450), .Y(n1451) );
INVX2TS U1843 ( .A(Sgf_operation_mult_x_1_n1570), .Y(
Sgf_operation_mult_x_1_n1571) );
OAI21XLTS U1844 ( .A0(n4046), .A1(n1984), .B0(n1428), .Y(n1429) );
AOI222X1TS U1845 ( .A0(n3659), .A1(n2729), .B0(n3650), .B1(n700), .C0(n3657),
.C1(n4069), .Y(n1428) );
OAI21XLTS U1846 ( .A0(n2961), .A1(n3514), .B0(n1358), .Y(n1359) );
CLKAND2X2TS U1847 ( .A(n3295), .B(n3262), .Y(n3250) );
OAI21XLTS U1848 ( .A0(n4046), .A1(n1484), .B0(n1268), .Y(n1269) );
AOI222X1TS U1849 ( .A0(n3622), .A1(n2729), .B0(n3637), .B1(n2728), .C0(n2777), .C1(n4069), .Y(n1268) );
CLKAND2X2TS U1850 ( .A(n3227), .B(n2981), .Y(n2982) );
AOI222X1TS U1851 ( .A0(n3465), .A1(n2645), .B0(n3472), .B1(n2644), .C0(n3468), .C1(n3229), .Y(n1251) );
OAI21XLTS U1852 ( .A0(n3237), .A1(n1611), .B0(n1266), .Y(n1267) );
CLKAND2X2TS U1853 ( .A(n3227), .B(n3857), .Y(n2971) );
OAI21XLTS U1854 ( .A0(n2961), .A1(n3487), .B0(n1224), .Y(n1225) );
CLKAND2X2TS U1855 ( .A(n3295), .B(n3893), .Y(n2984) );
CLKAND2X2TS U1856 ( .A(n3227), .B(n3229), .Y(n1217) );
OAI21XLTS U1857 ( .A0(n2967), .A1(n3475), .B0(n1208), .Y(n1209) );
AOI222X1TS U1858 ( .A0(n3473), .A1(n2584), .B0(n3472), .B1(n2583), .C0(n3468), .C1(n2968), .Y(n1208) );
CLKAND2X2TS U1859 ( .A(n3227), .B(n3888), .Y(n3228) );
NOR2X2TS U1860 ( .A(n1116), .B(n915), .Y(n1058) );
NAND2X1TS U1861 ( .A(n1019), .B(n1004), .Y(n978) );
OAI21X1TS U1862 ( .A0(n1724), .A1(n1049), .B0(n1048), .Y(n1078) );
NAND2X1TS U1863 ( .A(n1047), .B(n1117), .Y(n1049) );
NOR2X1TS U1864 ( .A(n1042), .B(n1044), .Y(n1047) );
NOR2X1TS U1865 ( .A(n4072), .B(n4069), .Y(n963) );
NOR2X1TS U1866 ( .A(n699), .B(n4069), .Y(n965) );
NAND2X1TS U1867 ( .A(n4028), .B(n4090), .Y(n2986) );
NAND2X1TS U1868 ( .A(n3808), .B(n3031), .Y(n1402) );
OAI21X1TS U1869 ( .A0(n1598), .A1(n1389), .B0(n1388), .Y(n1405) );
OAI21XLTS U1870 ( .A0(n638), .A1(n3875), .B0(n3874), .Y(n3876) );
AOI222X1TS U1871 ( .A0(n4036), .A1(n3933), .B0(n3878), .B1(n3932), .C0(n3873), .C1(n3872), .Y(n3874) );
OAI21XLTS U1872 ( .A0(n3978), .A1(n3770), .B0(n1875), .Y(n1876) );
OAI21XLTS U1873 ( .A0(n3266), .A1(n4096), .B0(n2141), .Y(n2142) );
AOI222X1TS U1874 ( .A0(n3805), .A1(n3963), .B0(n3810), .B1(n3962), .C0(n3156), .C1(n3015), .Y(n1851) );
OAI21XLTS U1875 ( .A0(n629), .A1(n2623), .B0(n1981), .Y(n1982) );
OAI21XLTS U1876 ( .A0(n642), .A1(n3725), .B0(n1523), .Y(n1524) );
AOI222X1TS U1877 ( .A0(n3713), .A1(n3997), .B0(n3722), .B1(n3996), .C0(n3708), .C1(n3808), .Y(n1523) );
OAI21XLTS U1878 ( .A0(n633), .A1(n3896), .B0(n3895), .Y(n3898) );
OAI21XLTS U1879 ( .A0(n3232), .A1(n4169), .B0(n1628), .Y(n1629) );
OAI21XLTS U1880 ( .A0(n638), .A1(n3845), .B0(n2706), .Y(n2707) );
OAI21XLTS U1881 ( .A0(n634), .A1(n4169), .B0(n2436), .Y(n2437) );
OAI21XLTS U1882 ( .A0(n629), .A1(n3864), .B0(n3860), .Y(n3861) );
OAI21XLTS U1883 ( .A0(n4155), .A1(n3619), .B0(n3177), .Y(n3178) );
OAI21XLTS U1884 ( .A0(n3310), .A1(n3158), .B0(n2382), .Y(n2383) );
OAI21XLTS U1885 ( .A0(n3002), .A1(n3782), .B0(n1639), .Y(n1640) );
OAI21XLTS U1886 ( .A0(n640), .A1(n3661), .B0(n2292), .Y(n2293) );
OAI21XLTS U1887 ( .A0(n2973), .A1(n3864), .B0(n2055), .Y(n2056) );
OAI21XLTS U1888 ( .A0(n3940), .A1(n3798), .B0(n2489), .Y(n2490) );
OAI21XLTS U1889 ( .A0(n635), .A1(n3896), .B0(n3891), .Y(n3892) );
OAI21XLTS U1890 ( .A0(n3870), .A1(n3845), .B0(n2788), .Y(n2789) );
OAI21XLTS U1891 ( .A0(n2692), .A1(n3158), .B0(n2781), .Y(n2782) );
OAI21XLTS U1892 ( .A0(n633), .A1(n3864), .B0(n3863), .Y(n3865) );
OAI21XLTS U1893 ( .A0(n631), .A1(n2623), .B0(n2227), .Y(n2228) );
OAI21XLTS U1894 ( .A0(n630), .A1(n4169), .B0(n2575), .Y(n2576) );
AOI222X1TS U1895 ( .A0(n3831), .A1(n3890), .B0(n3835), .B1(n3889), .C0(n3827), .C1(n3859), .Y(n2627) );
OAI21XLTS U1896 ( .A0(n4120), .A1(n3813), .B0(n1323), .Y(n1324) );
OAI21XLTS U1897 ( .A0(n644), .A1(n3845), .B0(n3839), .Y(n3840) );
OAI21XLTS U1898 ( .A0(n3288), .A1(n3880), .B0(n2065), .Y(n2066) );
AOI222X1TS U1899 ( .A0(n4036), .A1(n2397), .B0(n3878), .B1(n2396), .C0(n4034), .C1(n3294), .Y(n2065) );
OAI21XLTS U1900 ( .A0(n4142), .A1(n3813), .B0(n1331), .Y(n1332) );
OAI21XLTS U1901 ( .A0(n3662), .A1(n3845), .B0(n3844), .Y(n3847) );
OAI21XLTS U1902 ( .A0(n4137), .A1(n3770), .B0(n782), .Y(n783) );
NAND2X1TS U1903 ( .A(n3720), .B(n3717), .Y(n1350) );
OAI21XLTS U1904 ( .A0(n3949), .A1(n3864), .B0(n2722), .Y(n2723) );
OAI21XLTS U1905 ( .A0(n3978), .A1(n3158), .B0(n2614), .Y(n2615) );
OAI21XLTS U1906 ( .A0(n4155), .A1(n3691), .B0(n1509), .Y(n1510) );
OAI21XLTS U1907 ( .A0(n638), .A1(n3955), .B0(n3934), .Y(n3935) );
OAI21XLTS U1908 ( .A0(n641), .A1(n4038), .B0(n2051), .Y(n2052) );
OAI21XLTS U1909 ( .A0(n3249), .A1(n4169), .B0(n2682), .Y(n2683) );
OAI21XLTS U1910 ( .A0(n3988), .A1(n3158), .B0(n2257), .Y(n2258) );
OAI21XLTS U1911 ( .A0(n4155), .A1(n3725), .B0(n3144), .Y(n3145) );
OAI21XLTS U1912 ( .A0(n642), .A1(n3782), .B0(n3774), .Y(n3775) );
AOI222X1TS U1913 ( .A0(n3773), .A1(n3997), .B0(n3779), .B1(n3996), .C0(n3778), .C1(n4002), .Y(n3774) );
OAI21XLTS U1914 ( .A0(n3870), .A1(n4169), .B0(n2803), .Y(n2804) );
OAI21XLTS U1915 ( .A0(n3969), .A1(n3833), .B0(n2465), .Y(n2466) );
AOI222X1TS U1916 ( .A0(n3820), .A1(n3967), .B0(n3842), .B1(n3966), .C0(n3827), .C1(n3976), .Y(n2465) );
OAI21XLTS U1917 ( .A0(n636), .A1(n3875), .B0(n2013), .Y(n2014) );
OAI21XLTS U1918 ( .A0(n640), .A1(n3752), .B0(n3751), .Y(n3754) );
OAI21XLTS U1919 ( .A0(n640), .A1(n3782), .B0(n2334), .Y(n2335) );
OAI21XLTS U1920 ( .A0(n3969), .A1(n4038), .B0(n2131), .Y(n2132) );
OAI21XLTS U1921 ( .A0(n643), .A1(n3158), .B0(n2634), .Y(n2635) );
OAI21XLTS U1922 ( .A0(n3940), .A1(n3955), .B0(n3939), .Y(n3941) );
OAI21XLTS U1923 ( .A0(n644), .A1(n3752), .B0(n2039), .Y(n2040) );
OAI21XLTS U1924 ( .A0(n3988), .A1(n3833), .B0(n1755), .Y(n1756) );
OAI21XLTS U1925 ( .A0(n642), .A1(n3813), .B0(n3812), .Y(n3815) );
OAI21XLTS U1926 ( .A0(n3288), .A1(n3782), .B0(n1859), .Y(n1860) );
OAI21XLTS U1927 ( .A0(n4142), .A1(n3725), .B0(n3405), .Y(n3406) );
OAI21XLTS U1928 ( .A0(n3662), .A1(n3752), .B0(n2323), .Y(n2324) );
OAI21XLTS U1929 ( .A0(n640), .A1(n3725), .B0(n2072), .Y(n2073) );
OAI21XLTS U1930 ( .A0(n3940), .A1(n3880), .B0(n2196), .Y(n2197) );
OAI21XLTS U1931 ( .A0(n2973), .A1(n2623), .B0(n1475), .Y(n1476) );
OAI21XLTS U1932 ( .A0(n3662), .A1(n3691), .B0(n2169), .Y(n2170) );
OAI21XLTS U1933 ( .A0(n639), .A1(n3158), .B0(n2273), .Y(n2274) );
OAI21XLTS U1934 ( .A0(n3960), .A1(n3833), .B0(n3832), .Y(n3834) );
OAI21XLTS U1935 ( .A0(n4142), .A1(n3661), .B0(n3385), .Y(n3386) );
OAI21XLTS U1936 ( .A0(n2692), .A1(n3864), .B0(n2801), .Y(n2802) );
AOI222X1TS U1937 ( .A0(n4036), .A1(n3943), .B0(n4027), .B1(n3942), .C0(n3873), .C1(n3024), .Y(n2801) );
OAI21XLTS U1938 ( .A0(n3249), .A1(n4096), .B0(n2348), .Y(n2349) );
OAI21XLTS U1939 ( .A0(n3988), .A1(n3770), .B0(n1823), .Y(n1824) );
AOI222X1TS U1940 ( .A0(n3773), .A1(n3986), .B0(n3779), .B1(n3985), .C0(n3772), .C1(n3992), .Y(n1823) );
OAI21XLTS U1941 ( .A0(n3949), .A1(n3955), .B0(n3948), .Y(n3950) );
OAI21XLTS U1942 ( .A0(n3978), .A1(n4038), .B0(n1709), .Y(n1710) );
AOI222X1TS U1943 ( .A0(n4036), .A1(n3976), .B0(n4035), .B1(n3975), .C0(n4034), .C1(n3278), .Y(n1709) );
OAI21XLTS U1944 ( .A0(n4086), .A1(n3782), .B0(n1662), .Y(n1663) );
OAI21XLTS U1945 ( .A0(n3002), .A1(n3813), .B0(n1593), .Y(n1594) );
OAI21XLTS U1946 ( .A0(n3310), .A1(n3833), .B0(n2271), .Y(n2272) );
AOI222X1TS U1947 ( .A0(n4106), .A1(n3963), .B0(n3900), .B1(n3962), .C0(n4104), .C1(n3015), .Y(n2300) );
OAI21XLTS U1948 ( .A0(n4120), .A1(n3752), .B0(n1309), .Y(n1310) );
OAI21XLTS U1949 ( .A0(n643), .A1(n3833), .B0(n1964), .Y(n1965) );
OAI21XLTS U1950 ( .A0(n644), .A1(n3782), .B0(n3776), .Y(n3777) );
OAI21XLTS U1951 ( .A0(n3069), .A1(n3715), .B0(n768), .Y(n769) );
OAI21XLTS U1952 ( .A0(n640), .A1(n3813), .B0(n1948), .Y(n1949) );
AOI222X1TS U1953 ( .A0(n4036), .A1(n3986), .B0(n4035), .B1(n3985), .C0(n4034), .C1(n3301), .Y(n1624) );
AOI222X1TS U1954 ( .A0(n3998), .A1(n3958), .B0(n4130), .B1(n3957), .C0(n4163), .C1(n3967), .Y(n3959) );
AOI21X2TS U1955 ( .A0(n1543), .A1(n817), .B0(n816), .Y(n897) );
AOI21X1TS U1956 ( .A0(n2002), .A1(n894), .B0(n893), .Y(n895) );
NAND2X1TS U1957 ( .A(n1542), .B(n817), .Y(n887) );
NAND2X1TS U1958 ( .A(n2003), .B(n894), .Y(n896) );
NAND2X1TS U1959 ( .A(n1387), .B(n804), .Y(n806) );
AOI21X1TS U1960 ( .A0(n1386), .A1(n804), .B0(n803), .Y(n805) );
NOR2X1TS U1961 ( .A(n1389), .B(n802), .Y(n804) );
NAND2X1TS U1962 ( .A(n929), .B(n960), .Y(n937) );
NAND2X1TS U1963 ( .A(n1244), .B(n911), .Y(n1159) );
NAND2X1TS U1964 ( .A(n4080), .B(n3720), .Y(n1290) );
OR2X1TS U1965 ( .A(n4080), .B(n3720), .Y(n1291) );
NAND2X1TS U1966 ( .A(n4090), .B(n4080), .Y(n1299) );
OR2X1TS U1967 ( .A(n4090), .B(n4080), .Y(n1300) );
AOI21X1TS U1968 ( .A0(n1414), .A1(n1373), .B0(n1372), .Y(n1587) );
NOR2X1TS U1969 ( .A(n3297), .B(n3294), .Y(n1374) );
NAND2X1TS U1970 ( .A(n3297), .B(n3294), .Y(n1584) );
OR2X1TS U1971 ( .A(n3294), .B(n3877), .Y(n1376) );
NAND2X1TS U1972 ( .A(n3294), .B(n3877), .Y(n1375) );
ADDHXLTS U1973 ( .A(n3440), .B(n3439), .CO(n3161), .S(n3451) );
OAI21XLTS U1974 ( .A0(n3069), .A1(n3158), .B0(n3152), .Y(n3153) );
OAI21XLTS U1975 ( .A0(n4155), .A1(n3813), .B0(n1430), .Y(n1431) );
OAI21XLTS U1976 ( .A0(n645), .A1(n3076), .B0(n3075), .Y(n3077) );
OAI21XLTS U1977 ( .A0(n3002), .A1(n3845), .B0(n1882), .Y(n1883) );
OAI21XLTS U1978 ( .A0(n3310), .A1(n4038), .B0(n2597), .Y(n2598) );
OAI21XLTS U1979 ( .A0(n4086), .A1(n3813), .B0(n1770), .Y(n1771) );
OAI21XLTS U1980 ( .A0(n644), .A1(n3813), .B0(n1867), .Y(n1868) );
OAI21XLTS U1981 ( .A0(n643), .A1(n4038), .B0(n2544), .Y(n2545) );
OAI21XLTS U1982 ( .A0(n3662), .A1(n3813), .B0(n2245), .Y(n2246) );
OAI21XLTS U1983 ( .A0(n3288), .A1(n3845), .B0(n1962), .Y(n1963) );
OAI21XLTS U1984 ( .A0(n4142), .A1(n3782), .B0(n3425), .Y(n3426) );
OAI21XLTS U1985 ( .A0(n628), .A1(n2796), .B0(n2325), .Y(n2326) );
OAI21XLTS U1986 ( .A0(n627), .A1(n3896), .B0(n2501), .Y(n2502) );
OAI21XLTS U1987 ( .A0(n3208), .A1(n3076), .B0(n1990), .Y(n1991) );
OAI21XLTS U1988 ( .A0(n625), .A1(n2649), .B0(n2135), .Y(n2136) );
AOI222X1TS U1989 ( .A0(n3689), .A1(n3918), .B0(n2746), .B1(n3917), .C0(n3687), .C1(n2950), .Y(n1861) );
OAI21XLTS U1990 ( .A0(n639), .A1(n3281), .B0(n1794), .Y(n1795) );
AO21XLTS U1991 ( .A0(n3749), .A1(n4047), .B0(n3729), .Y(n2732) );
AOI222X1TS U1992 ( .A0(n3632), .A1(n3916), .B0(n2778), .B1(n3849), .C0(n3630), .C1(n3848), .Y(n2521) );
OAI21XLTS U1993 ( .A0(n632), .A1(n3706), .B0(n2528), .Y(n2529) );
AO21XLTS U1994 ( .A0(n3704), .A1(n4047), .B0(n3723), .Y(n2527) );
AOI222X1TS U1995 ( .A0(n3554), .A1(n3890), .B0(n3542), .B1(n3889), .C0(n3546), .C1(n3888), .Y(n2550) );
AOI222X1TS U1996 ( .A0(n3632), .A1(n3918), .B0(n2778), .B1(n3917), .C0(n2777), .C1(n2950), .Y(n2523) );
OAI21XLTS U1997 ( .A0(n625), .A1(n3640), .B0(n2137), .Y(n2138) );
OAI21XLTS U1998 ( .A0(n2952), .A1(n2665), .B0(n2664), .Y(n2667) );
OAI21XLTS U1999 ( .A0(n631), .A1(n3544), .B0(n3538), .Y(n3539) );
AO21XLTS U2000 ( .A0(n3688), .A1(n2729), .B0(n3689), .Y(n2631) );
AOI222X1TS U2001 ( .A0(n3465), .A1(n2643), .B0(n3472), .B1(n2429), .C0(n3468), .C1(n2981), .Y(n1283) );
OAI21XLTS U2002 ( .A0(n3237), .A1(n3122), .B0(n1318), .Y(n1319) );
AOI222X1TS U2003 ( .A0(n3554), .A1(n3916), .B0(n3534), .B1(n3849), .C0(n3546), .C1(n3848), .Y(n3536) );
AO21XLTS U2004 ( .A0(n3650), .A1(n4047), .B0(n3659), .Y(n1365) );
AOI222X1TS U2005 ( .A0(n3622), .A1(n700), .B0(n2778), .B1(n2752), .C0(n2777),
.C1(n4072), .Y(n1329) );
AOI222X1TS U2006 ( .A0(n3554), .A1(n3918), .B0(n3534), .B1(n3917), .C0(n2342), .C1(n2950), .Y(n1253) );
AO21XLTS U2007 ( .A0(n3637), .A1(n2729), .B0(n3622), .Y(n1263) );
OAI21XLTS U2008 ( .A0(n3914), .A1(n3556), .B0(n1194), .Y(n1195) );
AOI222X1TS U2009 ( .A0(n3610), .A1(n700), .B0(n3605), .B1(n2752), .C0(n2663),
.C1(n4072), .Y(n1257) );
OAI21XLTS U2010 ( .A0(n4046), .A1(n1611), .B0(n1185), .Y(n1186) );
AOI222X1TS U2011 ( .A0(n3610), .A1(n2729), .B0(n3598), .B1(n700), .C0(n2663),
.C1(n4069), .Y(n1185) );
AO21XLTS U2012 ( .A0(n3598), .A1(n2729), .B0(n3610), .Y(n1187) );
CLKAND2X2TS U2013 ( .A(n3227), .B(n2968), .Y(n2969) );
OAI21XLTS U2014 ( .A0(n2961), .A1(n3475), .B0(n1165), .Y(n1166) );
OAI21XLTS U2015 ( .A0(n3925), .A1(n3503), .B0(n1156), .Y(n1157) );
OAI21XLTS U2016 ( .A0(n3237), .A1(n3580), .B0(n3236), .Y(n3238) );
AOI222X1TS U2017 ( .A0(n3584), .A1(n2728), .B0(n3578), .B1(n2752), .C0(n3588), .C1(n4072), .Y(n1183) );
OAI21XLTS U2018 ( .A0(n4046), .A1(n3215), .B0(n1146), .Y(n1147) );
OAI21XLTS U2019 ( .A0(n3208), .A1(n3475), .B0(n1127), .Y(n1129) );
CLKAND2X2TS U2020 ( .A(n3227), .B(n3883), .Y(n2965) );
AOI222X1TS U2021 ( .A0(n3473), .A1(n3916), .B0(n3279), .B1(n3849), .C0(n3468), .C1(n3848), .Y(n1141) );
OAI21XLTS U2022 ( .A0(n4046), .A1(n1174), .B0(n1091), .Y(n1092) );
AOI222X1TS U2023 ( .A0(n3535), .A1(n2729), .B0(n3542), .B1(n2728), .C0(n2342), .C1(n4069), .Y(n1091) );
AOI222X1TS U2024 ( .A0(n3465), .A1(n3918), .B0(n4052), .B1(n3917), .C0(n4054), .C1(n2950), .Y(n1103) );
OAI21XLTS U2025 ( .A0(n4046), .A1(n3192), .B0(n1037), .Y(n1038) );
AOI222X1TS U2026 ( .A0(n3508), .A1(n2729), .B0(n3273), .B1(n700), .C0(n3518),
.C1(n4069), .Y(n1037) );
NAND2X2TS U2027 ( .A(n4028), .B(n4133), .Y(n2987) );
OAI21XLTS U2028 ( .A0(n3662), .A1(n3880), .B0(n2041), .Y(n2042) );
AOI222X1TS U2029 ( .A0(n4036), .A1(n4166), .B0(n4035), .B1(n4164), .C0(n4034), .C1(n3720), .Y(n2041) );
OAI21XLTS U2030 ( .A0(n3288), .A1(n4096), .B0(n1764), .Y(n1765) );
AOI222X1TS U2031 ( .A0(n4106), .A1(n3972), .B0(n3900), .B1(n3971), .C0(n4104), .C1(n3012), .Y(n1551) );
AOI222X1TS U2032 ( .A0(n4036), .A1(n3990), .B0(n3878), .B1(n1912), .C0(n4034), .C1(n3289), .Y(n1407) );
AOI222X1TS U2033 ( .A0(n3998), .A1(n3890), .B0(n3937), .B1(n3889), .C0(n4163), .C1(n3859), .Y(n2081) );
OAI21XLTS U2034 ( .A0(n639), .A1(n3715), .B0(n2593), .Y(n2594) );
OAI21XLTS U2035 ( .A0(n625), .A1(n3875), .B0(n1787), .Y(n1788) );
OAI21XLTS U2036 ( .A0(n629), .A1(n3896), .B0(n2117), .Y(n2118) );
OAI21XLTS U2037 ( .A0(n629), .A1(n3829), .B0(n3825), .Y(n3826) );
OAI21XLTS U2038 ( .A0(n635), .A1(n3829), .B0(n2627), .Y(n2628) );
OAI21XLTS U2039 ( .A0(n631), .A1(n3864), .B0(n3853), .Y(n3854) );
OAI21XLTS U2040 ( .A0(n640), .A1(n3880), .B0(n3879), .Y(n3882) );
AOI222X1TS U2041 ( .A0(n4036), .A1(n4002), .B0(n3878), .B1(n4001), .C0(n4034), .C1(n3877), .Y(n3879) );
OAI21XLTS U2042 ( .A0(n625), .A1(n2796), .B0(n1687), .Y(n1688) );
OAI21XLTS U2043 ( .A0(n635), .A1(n3798), .B0(n3793), .Y(n3794) );
OAI21XLTS U2044 ( .A0(n634), .A1(n3864), .B0(n2307), .Y(n2308) );
OAI21XLTS U2045 ( .A0(n629), .A1(n3798), .B0(n3795), .Y(n3796) );
OAI21XLTS U2046 ( .A0(n636), .A1(n2660), .B0(n1954), .Y(n1955) );
OAI21XLTS U2047 ( .A0(n641), .A1(n3833), .B0(n2678), .Y(n2679) );
OAI21X2TS U2048 ( .A0(n1158), .A1(n923), .B0(n922), .Y(n999) );
NOR2X1TS U2049 ( .A(n937), .B(n943), .Y(n931) );
NOR2X2TS U2050 ( .A(n1159), .B(n923), .Y(n998) );
OAI21XLTS U2051 ( .A0(n4142), .A1(n3880), .B0(n1316), .Y(n1317) );
AOI222X1TS U2052 ( .A0(n4036), .A1(n4151), .B0(n4035), .B1(n4140), .C0(n4034), .C1(n4139), .Y(n1316) );
OAI21XLTS U2053 ( .A0(n3288), .A1(n4169), .B0(n1602), .Y(n1603) );
OAI21XLTS U2054 ( .A0(n3662), .A1(n4096), .B0(n1423), .Y(n1424) );
OAI21XLTS U2055 ( .A0(n4086), .A1(n4096), .B0(n1572), .Y(n1574) );
OAI21XLTS U2056 ( .A0(n4155), .A1(n3880), .B0(n1465), .Y(n1466) );
AOI222X1TS U2057 ( .A0(n4036), .A1(n4153), .B0(n4035), .B1(n4152), .C0(n4034), .C1(n4080), .Y(n1465) );
OAI21XLTS U2058 ( .A0(n640), .A1(n4169), .B0(n4003), .Y(n4004) );
OAI21XLTS U2059 ( .A0(n644), .A1(n4096), .B0(n1588), .Y(n1589) );
OAI21XLTS U2060 ( .A0(n4120), .A1(n3880), .B0(n1314), .Y(n1315) );
AOI222X1TS U2061 ( .A0(n4036), .A1(n4162), .B0(n4035), .B1(n4118), .C0(n4034), .C1(n4090), .Y(n1314) );
OAI21XLTS U2062 ( .A0(n3069), .A1(n3833), .B0(n760), .Y(n761) );
OAI21XLTS U2063 ( .A0(n640), .A1(n4096), .B0(n2319), .Y(n2320) );
OAI21XLTS U2064 ( .A0(n644), .A1(n3880), .B0(n1749), .Y(n1750) );
AOI222X1TS U2065 ( .A0(n4036), .A1(n4115), .B0(n4035), .B1(n4114), .C0(n4034), .C1(n3717), .Y(n1749) );
OAI21XLTS U2066 ( .A0(n634), .A1(n3756), .B0(n1719), .Y(n1720) );
OAI21XLTS U2067 ( .A0(n629), .A1(n1611), .B0(n1610), .Y(n1612) );
OAI21XLTS U2068 ( .A0(n2952), .A1(n3122), .B0(n2523), .Y(n2524) );
AOI222X1TS U2069 ( .A0(n3590), .A1(n3918), .B0(n3578), .B1(n3917), .C0(n3588), .C1(n2950), .Y(n1426) );
AOI222X1TS U2070 ( .A0(n3473), .A1(n3859), .B0(n3472), .B1(n3858), .C0(n3468), .C1(n3857), .Y(n3462) );
OAI21XLTS U2071 ( .A0(n3914), .A1(n4060), .B0(n1080), .Y(n1081) );
AOI222X1TS U2072 ( .A0(n1235), .A1(n2729), .B0(n2767), .B1(Op_MY[50]), .C0(
n2785), .C1(n4069), .Y(n972) );
OAI21XLTS U2073 ( .A0(n632), .A1(n1070), .B0(n976), .Y(n977) );
AOI222X1TS U2074 ( .A0(n3465), .A1(n2729), .B0(n4052), .B1(n2728), .C0(n4054), .C1(n4069), .Y(n954) );
XNOR2X1TS U2075 ( .A(n1028), .B(n1027), .Y(n1029) );
CLKAND2X2TS U2076 ( .A(n4070), .B(n4069), .Y(n4071) );
CLKAND2X2TS U2077 ( .A(n4070), .B(n700), .Y(n4044) );
OAI21XLTS U2078 ( .A0(n4155), .A1(n4169), .B0(n4154), .Y(n4156) );
OAI21XLTS U2079 ( .A0(n4155), .A1(n4096), .B0(n4081), .Y(n4082) );
OAI21XLTS U2080 ( .A0(n644), .A1(n4169), .B0(n4116), .Y(n4117) );
OAI21XLTS U2081 ( .A0(n4142), .A1(n4169), .B0(n4141), .Y(n4143) );
OAI21XLTS U2082 ( .A0(n637), .A1(n4038), .B0(n1518), .Y(n1519) );
CLKINVX6TS U2083 ( .A(n5075), .Y(n4133) );
OAI21XLTS U2084 ( .A0(n4120), .A1(n4169), .B0(n4119), .Y(n4121) );
OAI21XLTS U2085 ( .A0(n4142), .A1(n4096), .B0(n4095), .Y(n4097) );
OAI21XLTS U2086 ( .A0(n3662), .A1(n4169), .B0(n4168), .Y(n4171) );
OAI21XLTS U2087 ( .A0(n4086), .A1(n3880), .B0(n1888), .Y(n1889) );
OAI21XLTS U2088 ( .A0(n642), .A1(n3880), .B0(n1560), .Y(n1561) );
OAI21XLTS U2089 ( .A0(n4046), .A1(n1070), .B0(n972), .Y(n973) );
OR2X1TS U2090 ( .A(Sgf_operation_mult_x_1_n2713), .B(
Sgf_operation_mult_x_1_n2720), .Y(n4507) );
CLKAND2X2TS U2091 ( .A(n4138), .B(n5152), .Y(n4282) );
OR2X1TS U2092 ( .A(Sgf_operation_mult_x_1_n2735), .B(
Sgf_operation_mult_x_1_n2741), .Y(n4512) );
OR2X1TS U2093 ( .A(Sgf_operation_mult_x_1_n2728), .B(
Sgf_operation_mult_x_1_n2734), .Y(n4515) );
OR2X1TS U2094 ( .A(Sgf_operation_mult_x_1_n2697), .B(
Sgf_operation_mult_x_1_n2704), .Y(n4536) );
OR2X1TS U2095 ( .A(n4147), .B(n4146), .Y(n4275) );
MX2X1TS U2096 ( .A(P_Sgf[33]), .B(n4396), .S0(n4895), .Y(Sgf_operation_n76)
);
MX2X1TS U2097 ( .A(P_Sgf[35]), .B(n4367), .S0(n4645), .Y(Sgf_operation_n74)
);
AO22XLTS U2098 ( .A0(n4609), .A1(Data_MX[63]), .B0(n4908), .B1(Op_MX[63]),
.Y(n538) );
MX2X1TS U2099 ( .A(P_Sgf[32]), .B(n4385), .S0(n4776), .Y(Sgf_operation_n77)
);
MX2X1TS U2100 ( .A(P_Sgf[34]), .B(n4356), .S0(n4652), .Y(Sgf_operation_n75)
);
MX2X1TS U2101 ( .A(P_Sgf[29]), .B(n4390), .S0(n4652), .Y(Sgf_operation_n80)
);
MX2X1TS U2102 ( .A(P_Sgf[39]), .B(n4361), .S0(n4895), .Y(Sgf_operation_n70)
);
MX2X1TS U2103 ( .A(P_Sgf[52]), .B(n4891), .S0(n4892), .Y(Sgf_operation_n57)
);
MX2X1TS U2104 ( .A(P_Sgf[36]), .B(n4338), .S0(n4892), .Y(Sgf_operation_n73)
);
MX2X1TS U2105 ( .A(P_Sgf[41]), .B(n4478), .S0(n4776), .Y(Sgf_operation_n68)
);
MX2X1TS U2106 ( .A(P_Sgf[43]), .B(n4453), .S0(n4645), .Y(Sgf_operation_n66)
);
MX2X1TS U2107 ( .A(P_Sgf[50]), .B(n4426), .S0(n4776), .Y(Sgf_operation_n59)
);
MX2X1TS U2108 ( .A(P_Sgf[27]), .B(n4592), .S0(n4776), .Y(Sgf_operation_n82)
);
MX2X1TS U2109 ( .A(P_Sgf[38]), .B(n4327), .S0(n4892), .Y(Sgf_operation_n71)
);
MX2X1TS U2110 ( .A(P_Sgf[40]), .B(n4467), .S0(n4895), .Y(Sgf_operation_n69)
);
MX2X1TS U2111 ( .A(P_Sgf[48]), .B(n4438), .S0(n4645), .Y(Sgf_operation_n61)
);
MX2X1TS U2112 ( .A(P_Sgf[51]), .B(n4407), .S0(n4645), .Y(Sgf_operation_n58)
);
MX2X1TS U2113 ( .A(P_Sgf[26]), .B(n4598), .S0(n4652), .Y(Sgf_operation_n83)
);
MX2X1TS U2114 ( .A(P_Sgf[37]), .B(n4332), .S0(n4892), .Y(Sgf_operation_n72)
);
MX2X1TS U2115 ( .A(P_Sgf[42]), .B(n4473), .S0(n4776), .Y(Sgf_operation_n67)
);
MX2X1TS U2116 ( .A(P_Sgf[44]), .B(n4448), .S0(n4652), .Y(Sgf_operation_n65)
);
MX2X1TS U2117 ( .A(P_Sgf[24]), .B(n4586), .S0(n4645), .Y(Sgf_operation_n85)
);
MX2X1TS U2118 ( .A(P_Sgf[30]), .B(n4375), .S0(n4652), .Y(Sgf_operation_n79)
);
MX2X1TS U2119 ( .A(P_Sgf[28]), .B(n4348), .S0(n4895), .Y(Sgf_operation_n81)
);
MX2X1TS U2120 ( .A(P_Sgf[49]), .B(n4310), .S0(n4892), .Y(Sgf_operation_n60)
);
MX2X1TS U2121 ( .A(P_Sgf[46]), .B(n4416), .S0(n4645), .Y(Sgf_operation_n63)
);
MX2X1TS U2122 ( .A(P_Sgf[25]), .B(n4548), .S0(n4776), .Y(Sgf_operation_n84)
);
MX2X1TS U2123 ( .A(P_Sgf[47]), .B(n4429), .S0(n4776), .Y(Sgf_operation_n62)
);
MX2X1TS U2124 ( .A(P_Sgf[45]), .B(n4459), .S0(n4652), .Y(Sgf_operation_n64)
);
MX2X1TS U2125 ( .A(P_Sgf[31]), .B(n4314), .S0(n4892), .Y(Sgf_operation_n78)
);
MX2X1TS U2126 ( .A(P_Sgf[23]), .B(n4608), .S0(n4645), .Y(Sgf_operation_n86)
);
MX2X1TS U2127 ( .A(P_Sgf[79]), .B(n4686), .S0(n4645), .Y(Sgf_operation_n30)
);
MX2X1TS U2128 ( .A(P_Sgf[77]), .B(n4706), .S0(n4776), .Y(Sgf_operation_n32)
);
MX2X1TS U2129 ( .A(P_Sgf[75]), .B(n4718), .S0(n4652), .Y(Sgf_operation_n34)
);
MX2X1TS U2130 ( .A(P_Sgf[73]), .B(n4731), .S0(n4645), .Y(Sgf_operation_n36)
);
MX2X1TS U2131 ( .A(P_Sgf[71]), .B(n4742), .S0(n4776), .Y(Sgf_operation_n38)
);
MX2X1TS U2132 ( .A(P_Sgf[67]), .B(n4777), .S0(n4652), .Y(Sgf_operation_n42)
);
MX2X1TS U2133 ( .A(P_Sgf[53]), .B(n4881), .S0(n4892), .Y(Sgf_operation_n56)
);
MX2X1TS U2134 ( .A(n720), .B(n4876), .S0(n4875), .Y(Sgf_operation_n55) );
MX2X1TS U2135 ( .A(n721), .B(n4862), .S0(n4875), .Y(Sgf_operation_n54) );
MX2X1TS U2136 ( .A(n722), .B(n4857), .S0(n4875), .Y(Sgf_operation_n53) );
MX2X1TS U2137 ( .A(n723), .B(n4849), .S0(n4875), .Y(Sgf_operation_n52) );
MX2X1TS U2138 ( .A(n724), .B(n4843), .S0(n4875), .Y(Sgf_operation_n51) );
MX2X1TS U2139 ( .A(n725), .B(n4835), .S0(n4875), .Y(Sgf_operation_n50) );
MX2X1TS U2140 ( .A(n726), .B(n4829), .S0(n4875), .Y(Sgf_operation_n49) );
MX2X1TS U2141 ( .A(n727), .B(n4822), .S0(n4875), .Y(Sgf_operation_n48) );
MX2X1TS U2142 ( .A(n728), .B(n4816), .S0(n4875), .Y(Sgf_operation_n47) );
MX2X1TS U2143 ( .A(n729), .B(n4804), .S0(n4875), .Y(Sgf_operation_n46) );
MX2X1TS U2144 ( .A(n730), .B(n4798), .S0(n4875), .Y(Sgf_operation_n45) );
MX2X1TS U2145 ( .A(n731), .B(n4791), .S0(n4875), .Y(Sgf_operation_n44) );
MX2X1TS U2146 ( .A(n732), .B(n4785), .S0(n4875), .Y(Sgf_operation_n43) );
MX2X1TS U2147 ( .A(n735), .B(n4737), .S0(n4652), .Y(Sgf_operation_n37) );
MX2X1TS U2148 ( .A(n736), .B(n4726), .S0(n4776), .Y(Sgf_operation_n35) );
MX2X1TS U2149 ( .A(n737), .B(n4713), .S0(n4645), .Y(Sgf_operation_n33) );
MX2X1TS U2150 ( .A(n738), .B(n4694), .S0(n4895), .Y(Sgf_operation_n31) );
MX2X1TS U2151 ( .A(n739), .B(n4677), .S0(n4875), .Y(Sgf_operation_n29) );
MX2X1TS U2152 ( .A(n740), .B(n4668), .S0(n4875), .Y(Sgf_operation_n28) );
MX2X1TS U2153 ( .A(n741), .B(n4666), .S0(n4875), .Y(Sgf_operation_n27) );
MX2X1TS U2154 ( .A(n742), .B(n4664), .S0(n4875), .Y(Sgf_operation_n26) );
MX2X1TS U2155 ( .A(n743), .B(n4662), .S0(n4875), .Y(Sgf_operation_n25) );
OR2X1TS U2156 ( .A(Op_MX[57]), .B(Op_MX[56]), .Y(n657) );
BUFX4TS U2157 ( .A(Op_MY[50]), .Y(n2728) );
OR2X1TS U2158 ( .A(Op_MX[55]), .B(Op_MX[54]), .Y(n671) );
INVX3TS U2159 ( .A(rst), .Y(Sgf_operation_n3) );
INVX2TS U2160 ( .A(n2728), .Y(n698) );
INVX2TS U2161 ( .A(n698), .Y(n699) );
CLKINVX6TS U2162 ( .A(n698), .Y(n700) );
OR2X4TS U2163 ( .A(FSM_selector_B[1]), .B(n5089), .Y(n4015) );
NAND2X2TS U2164 ( .A(n4903), .B(n4018), .Y(n882) );
NOR4X1TS U2165 ( .A(FS_Module_state_reg[2]), .B(n5150), .C(n5070), .D(n5073),
.Y(n858) );
BUFX4TS U2166 ( .A(n5178), .Y(n5169) );
BUFX4TS U2167 ( .A(n5173), .Y(n5167) );
BUFX4TS U2168 ( .A(n5173), .Y(n5177) );
BUFX4TS U2169 ( .A(Sgf_operation_n3), .Y(n5153) );
BUFX4TS U2170 ( .A(Sgf_operation_n3), .Y(n5155) );
BUFX4TS U2171 ( .A(Sgf_operation_n3), .Y(n5157) );
BUFX4TS U2172 ( .A(Sgf_operation_n3), .Y(n5154) );
NOR2X2TS U2173 ( .A(Sgf_operation_mult_x_1_n2747), .B(
Sgf_operation_mult_x_1_n2751), .Y(n4520) );
NOR2X2TS U2174 ( .A(n4178), .B(n4177), .Y(n4498) );
NOR2X2TS U2175 ( .A(Sgf_operation_mult_x_1_n2488), .B(
Sgf_operation_mult_x_1_n2504), .Y(n4391) );
NOR2X2TS U2176 ( .A(Sgf_operation_mult_x_1_n1733), .B(
Sgf_operation_mult_x_1_n1752), .Y(n4771) );
NOR2X2TS U2177 ( .A(Sgf_operation_mult_x_1_n2621), .B(
Sgf_operation_mult_x_1_n2633), .Y(n4581) );
NOR2X2TS U2178 ( .A(Sgf_operation_mult_x_1_n1910), .B(
Sgf_operation_mult_x_1_n1934), .Y(n4830) );
BUFX4TS U2179 ( .A(n5180), .Y(n5162) );
BUFX4TS U2180 ( .A(n882), .Y(n5175) );
BUFX3TS U2181 ( .A(n882), .Y(n883) );
BUFX4TS U2182 ( .A(n882), .Y(n5164) );
BUFX4TS U2183 ( .A(n882), .Y(n5173) );
NOR2X2TS U2184 ( .A(Sgf_operation_mult_x_1_n2202), .B(
Sgf_operation_mult_x_1_n2224), .Y(n4431) );
NOR2X2TS U2185 ( .A(Sgf_operation_mult_x_1_n2595), .B(
Sgf_operation_mult_x_1_n2607), .Y(n4593) );
NOR2X2TS U2186 ( .A(Sgf_operation_mult_x_1_n2454), .B(
Sgf_operation_mult_x_1_n2470), .Y(n4362) );
NOR2X2TS U2187 ( .A(Sgf_operation_mult_x_1_n1862), .B(
Sgf_operation_mult_x_1_n1884), .Y(n4817) );
NOR2X2TS U2188 ( .A(Sgf_operation_mult_x_1_n1817), .B(
Sgf_operation_mult_x_1_n1839), .Y(n4799) );
NOR2X2TS U2189 ( .A(Sgf_operation_mult_x_1_n1935), .B(
Sgf_operation_mult_x_1_n1958), .Y(n4838) );
NOR2X2TS U2190 ( .A(Sgf_operation_mult_x_1_n1983), .B(
Sgf_operation_mult_x_1_n2006), .Y(n4852) );
NOR2X2TS U2191 ( .A(Sgf_operation_mult_x_1_n1775), .B(
Sgf_operation_mult_x_1_n1795), .Y(n4786) );
NOR2X2TS U2192 ( .A(Sgf_operation_mult_x_1_n1694), .B(
Sgf_operation_mult_x_1_n1713), .Y(n4758) );
BUFX4TS U2193 ( .A(n5174), .Y(n5161) );
BUFX4TS U2194 ( .A(n5180), .Y(n5171) );
BUFX4TS U2195 ( .A(n702), .Y(n5166) );
BUFX4TS U2196 ( .A(n5163), .Y(n5168) );
BUFX3TS U2197 ( .A(n881), .Y(n701) );
BUFX3TS U2198 ( .A(n881), .Y(n702) );
BUFX4TS U2199 ( .A(n881), .Y(n5170) );
BUFX4TS U2200 ( .A(n881), .Y(n5179) );
CLKINVX6TS U2201 ( .A(n5055), .Y(n5051) );
CLKINVX6TS U2202 ( .A(n840), .Y(n3491) );
CLKINVX6TS U2203 ( .A(n1297), .Y(n3532) );
CLKINVX6TS U2204 ( .A(n1345), .Y(n3548) );
CLKINVX6TS U2205 ( .A(n1444), .Y(n3593) );
CLKINVX6TS U2206 ( .A(n1486), .Y(n3641) );
CLKINVX6TS U2207 ( .A(n1505), .Y(n3653) );
CLKINVX6TS U2208 ( .A(n1573), .Y(n3897) );
CLKINVX6TS U2209 ( .A(n1605), .Y(n3603) );
CLKINVX6TS U2210 ( .A(n1128), .Y(n3476) );
NOR3X2TS U2211 ( .A(n5072), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n4272) );
AOI222X1TS U2212 ( .A0(n3632), .A1(n3947), .B0(n2778), .B1(n3946), .C0(n2777), .C1(n3020), .Y(n2194) );
AOI222X1TS U2213 ( .A0(n3632), .A1(n3943), .B0(n2778), .B1(n3942), .C0(n2777), .C1(n3024), .Y(n2779) );
CLKINVX6TS U2214 ( .A(n3241), .Y(n2777) );
BUFX3TS U2215 ( .A(n2914), .Y(n2926) );
AOI222X1TS U2216 ( .A0(n3455), .A1(n3947), .B0(n4052), .B1(n3946), .C0(n4054), .C1(n3020), .Y(n854) );
AOI222X1TS U2217 ( .A0(n3455), .A1(n3953), .B0(n3279), .B1(n3952), .C0(n4054), .C1(n3008), .Y(n2497) );
CLKINVX6TS U2218 ( .A(n4059), .Y(n4054) );
AOI222X1TS U2219 ( .A0(n1452), .A1(n3947), .B0(n3534), .B1(n3946), .C0(n2342), .C1(n3020), .Y(n2251) );
AOI222X1TS U2220 ( .A0(n3535), .A1(n3943), .B0(n3534), .B1(n3942), .C0(n2342), .C1(n3024), .Y(n1933) );
AOI222X1TS U2221 ( .A0(n3554), .A1(n3953), .B0(n3534), .B1(n3952), .C0(n2342), .C1(n3008), .Y(n1898) );
CLKINVX6TS U2222 ( .A(n1436), .Y(n2342) );
AOI222X1TS U2223 ( .A0(n4036), .A1(n3938), .B0(n4027), .B1(n3936), .C0(n3873), .C1(n3272), .Y(n2196) );
CLKINVX6TS U2224 ( .A(n2702), .Y(n3873) );
BUFX4TS U2225 ( .A(n2931), .Y(n2903) );
BUFX4TS U2226 ( .A(n2931), .Y(n2913) );
BUFX4TS U2227 ( .A(n2931), .Y(n2910) );
AOI222X1TS U2228 ( .A0(n3617), .A1(n3938), .B0(n3605), .B1(n3936), .C0(n2663), .C1(n3272), .Y(n2173) );
CLKINVX6TS U2229 ( .A(n1609), .Y(n2663) );
BUFX6TS U2230 ( .A(n3203), .Y(n4075) );
AOI222X1TS U2231 ( .A0(n3494), .A1(n3943), .B0(n2767), .B1(n3942), .C0(n2785), .C1(n3024), .Y(n2566) );
CLKINVX6TS U2232 ( .A(n957), .Y(n2785) );
INVX4TS U2233 ( .A(n5051), .Y(n703) );
CLKINVX6TS U2234 ( .A(n885), .Y(n5068) );
CLKINVX6TS U2235 ( .A(n885), .Y(n5066) );
BUFX6TS U2236 ( .A(n2812), .Y(n2907) );
BUFX6TS U2237 ( .A(n2812), .Y(n2921) );
NOR3XLTS U2238 ( .A(Op_MY[49]), .B(Op_MY[54]), .C(n704), .Y(n4921) );
INVX2TS U2239 ( .A(n651), .Y(n704) );
INVX2TS U2240 ( .A(n656), .Y(n705) );
INVX2TS U2241 ( .A(n649), .Y(n706) );
NOR4X1TS U2242 ( .A(Op_MY[62]), .B(n705), .C(n706), .D(Op_MY[59]), .Y(n4923)
);
INVX2TS U2243 ( .A(n654), .Y(n707) );
INVX2TS U2244 ( .A(n672), .Y(n708) );
INVX2TS U2245 ( .A(n668), .Y(n709) );
INVX2TS U2246 ( .A(n652), .Y(n710) );
INVX2TS U2247 ( .A(n646), .Y(n711) );
INVX2TS U2248 ( .A(n653), .Y(n712) );
INVX2TS U2249 ( .A(n647), .Y(n713) );
BUFX6TS U2250 ( .A(n2853), .Y(n2920) );
INVX2TS U2251 ( .A(n648), .Y(n714) );
INVX2TS U2252 ( .A(n670), .Y(n715) );
INVX2TS U2253 ( .A(n697), .Y(n716) );
INVX2TS U2254 ( .A(n669), .Y(n717) );
INVX2TS U2255 ( .A(n655), .Y(n718) );
INVX2TS U2256 ( .A(n696), .Y(n719) );
INVX2TS U2257 ( .A(n695), .Y(n720) );
INVX2TS U2258 ( .A(n667), .Y(n721) );
INVX2TS U2259 ( .A(n694), .Y(n722) );
INVX2TS U2260 ( .A(n666), .Y(n723) );
INVX2TS U2261 ( .A(n693), .Y(n724) );
INVX2TS U2262 ( .A(n665), .Y(n725) );
INVX2TS U2263 ( .A(n692), .Y(n726) );
INVX2TS U2264 ( .A(n664), .Y(n727) );
INVX2TS U2265 ( .A(n691), .Y(n728) );
INVX2TS U2266 ( .A(n663), .Y(n729) );
INVX2TS U2267 ( .A(n690), .Y(n730) );
INVX2TS U2268 ( .A(n662), .Y(n731) );
INVX2TS U2269 ( .A(n650), .Y(n732) );
INVX2TS U2270 ( .A(n689), .Y(n733) );
INVX2TS U2271 ( .A(n688), .Y(n734) );
INVX2TS U2272 ( .A(n687), .Y(n735) );
INVX2TS U2273 ( .A(n686), .Y(n736) );
INVX2TS U2274 ( .A(n685), .Y(n737) );
INVX2TS U2275 ( .A(n684), .Y(n738) );
INVX2TS U2276 ( .A(n683), .Y(n739) );
INVX2TS U2277 ( .A(n661), .Y(n740) );
INVX2TS U2278 ( .A(n682), .Y(n741) );
INVX2TS U2279 ( .A(n660), .Y(n742) );
INVX2TS U2280 ( .A(n681), .Y(n743) );
INVX2TS U2281 ( .A(n659), .Y(n744) );
INVX2TS U2282 ( .A(n680), .Y(n745) );
INVX2TS U2283 ( .A(n679), .Y(n746) );
INVX2TS U2284 ( .A(n678), .Y(n747) );
INVX2TS U2285 ( .A(n677), .Y(n748) );
INVX2TS U2286 ( .A(n676), .Y(n749) );
INVX2TS U2287 ( .A(n675), .Y(n750) );
INVX2TS U2288 ( .A(n674), .Y(n751) );
INVX2TS U2289 ( .A(n673), .Y(n752) );
INVX2TS U2290 ( .A(n658), .Y(n753) );
NOR2X4TS U2291 ( .A(FS_Module_state_reg[3]), .B(n4906), .Y(n4951) );
INVX3TS U2292 ( .A(n885), .Y(n5064) );
NOR2X6TS U2293 ( .A(n4951), .B(n4892), .Y(n4894) );
BUFX6TS U2294 ( .A(n4657), .Y(n4892) );
BUFX6TS U2295 ( .A(n4892), .Y(n4776) );
BUFX4TS U2296 ( .A(n4892), .Y(n4895) );
BUFX6TS U2297 ( .A(n4892), .Y(n4645) );
BUFX6TS U2298 ( .A(n4892), .Y(n4652) );
XNOR2X2TS U2299 ( .A(Op_MX[12]), .B(Op_MX[13]), .Y(n1320) );
NOR4X1TS U2300 ( .A(Op_MX[13]), .B(Op_MX[10]), .C(Op_MX[7]), .D(Op_MX[4]),
.Y(n4933) );
XNOR2X2TS U2301 ( .A(Op_MX[33]), .B(Op_MX[34]), .Y(n1151) );
NOR4X1TS U2302 ( .A(Op_MX[34]), .B(Op_MX[31]), .C(Op_MX[28]), .D(Op_MX[22]),
.Y(n4935) );
XNOR2X2TS U2303 ( .A(Op_MX[42]), .B(Op_MX[43]), .Y(n1012) );
NOR4X1TS U2304 ( .A(Op_MX[43]), .B(Op_MX[25]), .C(Op_MX[19]), .D(Op_MX[16]),
.Y(n4934) );
XNOR2X2TS U2305 ( .A(Op_MX[48]), .B(Op_MX[49]), .Y(n851) );
NOR4X1TS U2306 ( .A(Op_MX[49]), .B(Op_MX[46]), .C(Op_MX[40]), .D(Op_MX[37]),
.Y(n4936) );
XNOR2X2TS U2307 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n1420) );
NOR4X1TS U2308 ( .A(Op_MX[12]), .B(Op_MX[9]), .C(Op_MX[6]), .D(Op_MX[3]),
.Y(n4929) );
XNOR2X2TS U2309 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n1618) );
NOR4X1TS U2310 ( .A(Op_MX[42]), .B(Op_MX[24]), .C(Op_MX[18]), .D(Op_MX[15]),
.Y(n4930) );
XNOR2X2TS U2311 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n1458) );
NOR4X1TS U2312 ( .A(Op_MX[33]), .B(Op_MX[30]), .C(Op_MX[27]), .D(Op_MX[21]),
.Y(n4931) );
XNOR2X2TS U2313 ( .A(Op_MX[36]), .B(Op_MX[37]), .Y(n1143) );
NOR4X1TS U2314 ( .A(Op_MX[48]), .B(Op_MX[45]), .C(Op_MX[39]), .D(Op_MX[36]),
.Y(n4932) );
BUFX6TS U2315 ( .A(Op_MY[43]), .Y(n3199) );
BUFX6TS U2316 ( .A(Op_MY[43]), .Y(n3912) );
NOR4X1TS U2317 ( .A(Op_MY[48]), .B(Op_MY[47]), .C(Op_MY[43]), .D(Op_MY[42]),
.Y(n4917) );
BUFX6TS U2318 ( .A(Op_MY[6]), .Y(n4166) );
NOR4X1TS U2319 ( .A(Op_MY[16]), .B(Op_MY[15]), .C(Op_MY[6]), .D(Op_MY[5]),
.Y(n4911) );
BUFX6TS U2320 ( .A(Op_MY[12]), .Y(n3997) );
NOR4X1TS U2321 ( .A(Op_MY[14]), .B(Op_MY[13]), .C(Op_MY[12]), .D(Op_MY[4]),
.Y(n4912) );
BUFX6TS U2322 ( .A(Op_MY[20]), .Y(n3963) );
NOR4X1TS U2323 ( .A(Op_MY[22]), .B(Op_MY[21]), .C(Op_MY[20]), .D(Op_MY[11]),
.Y(n4916) );
BUFX6TS U2324 ( .A(Op_MY[28]), .Y(n3927) );
NOR4X1TS U2325 ( .A(Op_MY[30]), .B(Op_MY[29]), .C(Op_MY[28]), .D(Op_MY[26]),
.Y(n4914) );
BUFX6TS U2326 ( .A(Op_MY[34]), .Y(n3890) );
NOR4X1TS U2327 ( .A(Op_MY[37]), .B(Op_MY[36]), .C(Op_MY[34]), .D(Op_MY[33]),
.Y(n4920) );
BUFX6TS U2328 ( .A(Op_MY[38]), .Y(n3819) );
NOR4X1TS U2329 ( .A(Op_MY[40]), .B(Op_MY[39]), .C(Op_MY[38]), .D(Op_MY[35]),
.Y(n4919) );
BUFX6TS U2330 ( .A(Op_MY[7]), .Y(n4115) );
NOR4X1TS U2331 ( .A(Op_MY[17]), .B(Op_MY[7]), .C(Op_MY[3]), .D(Op_MY[2]),
.Y(n4910) );
BUFX6TS U2332 ( .A(Op_MY[10]), .Y(n4002) );
NOR4X1TS U2333 ( .A(Op_MY[18]), .B(Op_MY[10]), .C(Op_MY[9]), .D(Op_MY[8]),
.Y(n4909) );
BUFX6TS U2334 ( .A(Op_MY[13]), .Y(n3992) );
BUFX6TS U2335 ( .A(Op_MY[15]), .Y(n3986) );
BUFX6TS U2336 ( .A(Op_MY[21]), .Y(n3958) );
BUFX6TS U2337 ( .A(Op_MY[24]), .Y(n3943) );
NOR4X1TS U2338 ( .A(Op_MY[25]), .B(Op_MY[24]), .C(Op_MY[23]), .D(Op_MY[19]),
.Y(n4915) );
BUFX6TS U2339 ( .A(Op_MY[29]), .Y(n3264) );
BUFX6TS U2340 ( .A(Op_MY[31]), .Y(n2643) );
NOR4X1TS U2341 ( .A(Op_MY[32]), .B(Op_MY[31]), .C(Op_MY[27]), .D(Op_MY[1]),
.Y(n4913) );
BUFX6TS U2342 ( .A(Op_MY[47]), .Y(n2654) );
BUFX6TS U2343 ( .A(Op_MY[11]), .Y(n3990) );
BUFX6TS U2344 ( .A(Op_MY[19]), .Y(n3967) );
BUFX6TS U2345 ( .A(Op_MY[33]), .Y(n2645) );
BUFX6TS U2346 ( .A(Op_MY[41]), .Y(n3923) );
NOR4X1TS U2347 ( .A(Op_MY[46]), .B(Op_MY[45]), .C(Op_MY[44]), .D(Op_MY[41]),
.Y(n4918) );
BUFX6TS U2348 ( .A(Op_MY[42]), .Y(n3918) );
BUFX6TS U2349 ( .A(Op_MY[14]), .Y(n3980) );
BUFX6TS U2350 ( .A(Op_MY[17]), .Y(n3976) );
BUFX6TS U2351 ( .A(Op_MY[3]), .Y(n4080) );
BUFX6TS U2352 ( .A(Op_MY[3]), .Y(n4151) );
XNOR2X2TS U2353 ( .A(Op_MX[39]), .B(Op_MX[40]), .Y(n1032) );
XNOR2X2TS U2354 ( .A(Op_MX[27]), .B(Op_MX[28]), .Y(n1272) );
XNOR2X2TS U2355 ( .A(Op_MX[18]), .B(Op_MX[19]), .Y(n1306) );
XNOR2X2TS U2356 ( .A(Op_MX[6]), .B(Op_MX[7]), .Y(n1311) );
XNOR2X2TS U2357 ( .A(Op_MX[45]), .B(Op_MX[46]), .Y(n836) );
XNOR2X2TS U2358 ( .A(Op_MX[30]), .B(Op_MX[31]), .Y(n1196) );
XNOR2X2TS U2359 ( .A(Op_MX[24]), .B(Op_MX[25]), .Y(n1360) );
XNOR2X2TS U2360 ( .A(Op_MX[9]), .B(Op_MX[10]), .Y(n1380) );
NOR4X1TS U2361 ( .A(P_Sgf[24]), .B(P_Sgf[27]), .C(P_Sgf[26]), .D(P_Sgf[23]),
.Y(n3041) );
NOR2XLTS U2362 ( .A(n657), .B(n671), .Y(n4944) );
NOR2X2TS U2363 ( .A(Sgf_operation_mult_x_1_n2248), .B(
Sgf_operation_mult_x_1_n2270), .Y(n4454) );
NOR2X2TS U2364 ( .A(Sgf_operation_mult_x_1_n2656), .B(
Sgf_operation_mult_x_1_n2666), .Y(n4567) );
NOR2X2TS U2365 ( .A(Sgf_operation_mult_x_1_n2471), .B(
Sgf_operation_mult_x_1_n2487), .Y(n4351) );
OAI22X2TS U2366 ( .A0(beg_FSM), .A1(n881), .B0(ack_FSM), .B1(n2936), .Y(
n4904) );
NOR2X2TS U2367 ( .A(Sgf_operation_mult_x_1_n1885), .B(
Sgf_operation_mult_x_1_n1909), .Y(n4824) );
NOR2X2TS U2368 ( .A(Sgf_operation_mult_x_1_n1676), .B(
Sgf_operation_mult_x_1_n1693), .Y(n4752) );
NOR2X2TS U2369 ( .A(Sgf_operation_mult_x_1_n1753), .B(
Sgf_operation_mult_x_1_n1774), .Y(n4780) );
NOR2X2TS U2370 ( .A(Sgf_operation_mult_x_1_n2608), .B(
Sgf_operation_mult_x_1_n2620), .Y(n4543) );
NOR2X2TS U2371 ( .A(Sgf_operation_mult_x_1_n2634), .B(
Sgf_operation_mult_x_1_n2644), .Y(n4603) );
NOR2X2TS U2372 ( .A(Sgf_operation_mult_x_1_n1959), .B(
Sgf_operation_mult_x_1_n1982), .Y(n4844) );
OAI21XLTS U2373 ( .A0(n4553), .A1(n4556), .B0(n4557), .Y(n4194) );
NOR2XLTS U2374 ( .A(n4556), .B(n4554), .Y(n4195) );
NOR2X2TS U2375 ( .A(Sgf_operation_mult_x_1_n2705), .B(
Sgf_operation_mult_x_1_n2712), .Y(n4556) );
OAI21XLTS U2376 ( .A0(n641), .A1(n3317), .B0(n1779), .Y(n1780) );
OAI21XLTS U2377 ( .A0(n637), .A1(n3317), .B0(n2109), .Y(n2110) );
OAI21XLTS U2378 ( .A0(n3969), .A1(n3317), .B0(n1534), .Y(n1535) );
OAI21XLTS U2379 ( .A0(n639), .A1(n3317), .B0(n2188), .Y(n2189) );
OAI21XLTS U2380 ( .A0(n3988), .A1(n3317), .B0(n3302), .Y(n3303) );
OAI21XLTS U2381 ( .A0(n643), .A1(n3317), .B0(n2438), .Y(n2439) );
OAI21XLTS U2382 ( .A0(n3960), .A1(n3317), .B0(n877), .Y(n878) );
OAI21XLTS U2383 ( .A0(n3069), .A1(n3317), .B0(n764), .Y(n765) );
OAI21XLTS U2384 ( .A0(n4137), .A1(n3317), .B0(n766), .Y(n767) );
OAI21XLTS U2385 ( .A0(n4480), .A1(n4499), .B0(n4481), .Y(n4181) );
NOR2XLTS U2386 ( .A(n4480), .B(n4498), .Y(n4182) );
NOR2X2TS U2387 ( .A(n4180), .B(n4179), .Y(n4480) );
NOR2X2TS U2388 ( .A(Sgf_operation_mult_x_1_n1714), .B(
Sgf_operation_mult_x_1_n1732), .Y(n4765) );
NOR2X2TS U2389 ( .A(Sgf_operation_mult_x_1_n1796), .B(
Sgf_operation_mult_x_1_n1816), .Y(n4793) );
NOR2X2TS U2390 ( .A(Sgf_operation_mult_x_1_n1840), .B(
Sgf_operation_mult_x_1_n1861), .Y(n4811) );
NOR2X2TS U2391 ( .A(Sgf_operation_mult_x_1_n2177), .B(
Sgf_operation_mult_x_1_n2201), .Y(n4433) );
NOR2X2TS U2392 ( .A(Sgf_operation_mult_x_1_n2397), .B(
Sgf_operation_mult_x_1_n2415), .Y(n4322) );
NOR2X2TS U2393 ( .A(Sgf_operation_mult_x_1_n2435), .B(
Sgf_operation_mult_x_1_n2453), .Y(n4333) );
NOR2X2TS U2394 ( .A(Sgf_operation_mult_x_1_n2505), .B(
Sgf_operation_mult_x_1_n2520), .Y(n4380) );
NOR2X2TS U2395 ( .A(Sgf_operation_mult_x_1_n2581), .B(
Sgf_operation_mult_x_1_n2594), .Y(n4587) );
OAI21XLTS U2396 ( .A0(n4522), .A1(n4519), .B0(n4523), .Y(n4187) );
NOR2XLTS U2397 ( .A(n4522), .B(n4520), .Y(n4188) );
NOR2X2TS U2398 ( .A(Sgf_operation_mult_x_1_n2742), .B(
Sgf_operation_mult_x_1_n2746), .Y(n4522) );
AOI222X1TS U2399 ( .A0(n4134), .A1(n4126), .B0(n4165), .B1(n4125), .C0(n3951), .C1(n4124), .Y(n4127) );
AOI222X1TS U2400 ( .A0(n4101), .A1(n4126), .B0(n4105), .B1(n4125), .C0(n2794), .C1(n4124), .Y(n4107) );
AOI222X1TS U2401 ( .A0(n2695), .A1(n4126), .B0(n3658), .B1(n4125), .C0(n2755), .C1(n4124), .Y(n3377) );
AOI222X1TS U2402 ( .A0(n1452), .A1(n4126), .B0(n3553), .B1(n4125), .C0(n3552), .C1(n4124), .Y(n3336) );
AOI222X1TS U2403 ( .A0(n3638), .A1(n4126), .B0(n3631), .B1(n4125), .C0(n3636), .C1(n4124), .Y(n3121) );
AOI222X1TS U2404 ( .A0(n3501), .A1(n4126), .B0(n3500), .B1(n4125), .C0(n3499), .C1(n4124), .Y(n3316) );
AOI222X1TS U2405 ( .A0(n3713), .A1(n4126), .B0(n3722), .B1(n4125), .C0(n2751), .C1(n4124), .Y(n3397) );
OAI21XLTS U2406 ( .A0(n637), .A1(n3607), .B0(n2068), .Y(n2069) );
OAI21XLTS U2407 ( .A0(n639), .A1(n3607), .B0(n2317), .Y(n2318) );
OAI21XLTS U2408 ( .A0(n3988), .A1(n3607), .B0(n1732), .Y(n1733) );
OAI21XLTS U2409 ( .A0(n641), .A1(n3607), .B0(n2087), .Y(n2088) );
OAI21XLTS U2410 ( .A0(n3978), .A1(n3607), .B0(n1813), .Y(n1814) );
OAI21XLTS U2411 ( .A0(n3310), .A1(n3607), .B0(n1714), .Y(n1715) );
OAI21XLTS U2412 ( .A0(n643), .A1(n3607), .B0(n1811), .Y(n1812) );
OAI21XLTS U2413 ( .A0(n3960), .A1(n3607), .B0(n3606), .Y(n3608) );
OAI21XLTS U2414 ( .A0(n3969), .A1(n3607), .B0(n1886), .Y(n1887) );
OAI21XLTS U2415 ( .A0(n645), .A1(n3607), .B0(n3357), .Y(n3358) );
OAI21XLTS U2416 ( .A0(n3069), .A1(n3607), .B0(n776), .Y(n777) );
OAI21XLTS U2417 ( .A0(n4137), .A1(n3607), .B0(n778), .Y(n779) );
OAI21XLTS U2418 ( .A0(n637), .A1(n3647), .B0(n2556), .Y(n2557) );
OAI21XLTS U2419 ( .A0(n631), .A1(n3647), .B0(n3646), .Y(n3648) );
OAI21XLTS U2420 ( .A0(n639), .A1(n3647), .B0(n1970), .Y(n1971) );
OAI21XLTS U2421 ( .A0(n641), .A1(n3647), .B0(n1796), .Y(n1797) );
OAI21XLTS U2422 ( .A0(n3978), .A1(n3647), .B0(n2249), .Y(n2250) );
OAI21XLTS U2423 ( .A0(n3960), .A1(n3647), .B0(n1668), .Y(n1669) );
OAI21XLTS U2424 ( .A0(n3988), .A1(n3647), .B0(n2587), .Y(n2588) );
OAI21XLTS U2425 ( .A0(n3969), .A1(n3647), .B0(n1658), .Y(n1659) );
OAI21XLTS U2426 ( .A0(n3310), .A1(n3647), .B0(n2726), .Y(n2727) );
OAI21XLTS U2427 ( .A0(n643), .A1(n3647), .B0(n2690), .Y(n2691) );
OAI21XLTS U2428 ( .A0(n645), .A1(n3647), .B0(n3377), .Y(n3378) );
OAI21XLTS U2429 ( .A0(n3069), .A1(n3647), .B0(n772), .Y(n773) );
OAI21XLTS U2430 ( .A0(n4137), .A1(n3647), .B0(n774), .Y(n775) );
OAI21XLTS U2431 ( .A0(n633), .A1(n4136), .B0(n3930), .Y(n3931) );
OAI21XLTS U2432 ( .A0(n635), .A1(n4136), .B0(n2081), .Y(n2082) );
OAI21XLTS U2433 ( .A0(n641), .A1(n4136), .B0(n3964), .Y(n3965) );
OAI21XLTS U2434 ( .A0(n3960), .A1(n4136), .B0(n3959), .Y(n3961) );
OAI21XLTS U2435 ( .A0(n639), .A1(n4136), .B0(n3973), .Y(n3974) );
OAI21XLTS U2436 ( .A0(n637), .A1(n4136), .B0(n3983), .Y(n3984) );
OAI21XLTS U2437 ( .A0(n3978), .A1(n4136), .B0(n3977), .Y(n3979) );
OAI21XLTS U2438 ( .A0(n3969), .A1(n4136), .B0(n3968), .Y(n3970) );
OAI21XLTS U2439 ( .A0(n3988), .A1(n4136), .B0(n3987), .Y(n3989) );
OAI21XLTS U2440 ( .A0(n643), .A1(n4136), .B0(n3993), .Y(n3994) );
OAI21XLTS U2441 ( .A0(n3310), .A1(n4136), .B0(n3164), .Y(n3165) );
OAI21XLTS U2442 ( .A0(n645), .A1(n4136), .B0(n4127), .Y(n4128) );
OAI21XLTS U2443 ( .A0(n3069), .A1(n4136), .B0(n4131), .Y(n4132) );
OAI21XLTS U2444 ( .A0(n3237), .A1(n3210), .B0(n3209), .Y(n3211) );
OAI21XLTS U2445 ( .A0(n639), .A1(n3210), .B0(n2167), .Y(n2168) );
OAI21XLTS U2446 ( .A0(n641), .A1(n3210), .B0(n2302), .Y(n2303) );
OAI21XLTS U2447 ( .A0(n637), .A1(n3210), .B0(n2198), .Y(n2199) );
OAI21XLTS U2448 ( .A0(n3978), .A1(n3210), .B0(n1825), .Y(n1826) );
OAI21XLTS U2449 ( .A0(n3310), .A1(n3210), .B0(n1582), .Y(n1583) );
OAI21XLTS U2450 ( .A0(n3960), .A1(n3210), .B0(n1931), .Y(n1932) );
OAI21XLTS U2451 ( .A0(n643), .A1(n3210), .B0(n2444), .Y(n2445) );
OAI21XLTS U2452 ( .A0(n645), .A1(n3210), .B0(n3091), .Y(n3092) );
OAI21XLTS U2453 ( .A0(n3069), .A1(n3210), .B0(n3087), .Y(n3088) );
OAI21XLTS U2454 ( .A0(n4137), .A1(n3210), .B0(n3089), .Y(n3090) );
OAI21XLTS U2455 ( .A0(n641), .A1(n3337), .B0(n2404), .Y(n2405) );
OAI21XLTS U2456 ( .A0(n3310), .A1(n3337), .B0(n1499), .Y(n1500) );
OAI21XLTS U2457 ( .A0(n637), .A1(n3337), .B0(n2237), .Y(n2238) );
OAI21XLTS U2458 ( .A0(n639), .A1(n3337), .B0(n2354), .Y(n2355) );
OAI21XLTS U2459 ( .A0(n3969), .A1(n3337), .B0(n2123), .Y(n2124) );
OAI21XLTS U2460 ( .A0(n643), .A1(n3337), .B0(n2259), .Y(n2260) );
OAI21XLTS U2461 ( .A0(n3988), .A1(n3337), .B0(n2031), .Y(n2032) );
OAI21XLTS U2462 ( .A0(n3978), .A1(n3337), .B0(n2091), .Y(n2092) );
OAI21XLTS U2463 ( .A0(n645), .A1(n3337), .B0(n3336), .Y(n3338) );
OAI21XLTS U2464 ( .A0(n3069), .A1(n3337), .B0(n784), .Y(n785) );
OAI21XLTS U2465 ( .A0(n4137), .A1(n3337), .B0(n786), .Y(n787) );
OAI21XLTS U2466 ( .A0(n631), .A1(n4108), .B0(n3886), .Y(n3887) );
OAI21XLTS U2467 ( .A0(n634), .A1(n4108), .B0(n2591), .Y(n2592) );
OAI21XLTS U2468 ( .A0(n639), .A1(n4108), .B0(n1551), .Y(n1552) );
OAI21XLTS U2469 ( .A0(n641), .A1(n4108), .B0(n2300), .Y(n2301) );
OAI21XLTS U2470 ( .A0(n3960), .A1(n4108), .B0(n3902), .Y(n3903) );
OAI21XLTS U2471 ( .A0(n637), .A1(n4108), .B0(n2479), .Y(n2480) );
OAI21XLTS U2472 ( .A0(n3969), .A1(n4108), .B0(n1785), .Y(n1786) );
OAI21XLTS U2473 ( .A0(n3978), .A1(n4108), .B0(n3082), .Y(n3083) );
OAI21XLTS U2474 ( .A0(n3310), .A1(n4108), .B0(n2093), .Y(n2094) );
OAI21XLTS U2475 ( .A0(n3988), .A1(n4108), .B0(n2111), .Y(n2112) );
OAI21XLTS U2476 ( .A0(n643), .A1(n4108), .B0(n2175), .Y(n2176) );
OAI21XLTS U2477 ( .A0(n645), .A1(n4108), .B0(n4107), .Y(n4110) );
OAI21XLTS U2478 ( .A0(n3069), .A1(n4108), .B0(n4099), .Y(n4100) );
OAI21XLTS U2479 ( .A0(n4137), .A1(n4108), .B0(n4102), .Y(n4103) );
CLKINVX6TS U2480 ( .A(n1384), .Y(n3837) );
CLKINVX6TS U2481 ( .A(n1408), .Y(n3881) );
CLKINVX6TS U2482 ( .A(n1468), .Y(n3692) );
CLKINVX6TS U2483 ( .A(n1622), .Y(n3762) );
CLKINVX6TS U2484 ( .A(n1576), .Y(n3801) );
CLKINVX6TS U2485 ( .A(n1540), .Y(n3710) );
CLKINVX6TS U2486 ( .A(n1596), .Y(n3753) );
CLKINVX6TS U2487 ( .A(n5055), .Y(n5060) );
BUFX6TS U2488 ( .A(Op_MY[45]), .Y(n3907) );
BUFX6TS U2489 ( .A(Op_MY[44]), .Y(n2508) );
BUFX6TS U2490 ( .A(Op_MY[39]), .Y(n3921) );
BUFX6TS U2491 ( .A(Op_MY[36]), .Y(n3885) );
BUFX6TS U2492 ( .A(Op_MY[5]), .Y(n4153) );
BUFX6TS U2493 ( .A(Op_MY[35]), .Y(n2584) );
BUFX6TS U2494 ( .A(Op_MY[8]), .Y(n4084) );
BUFX6TS U2495 ( .A(Op_MY[9]), .Y(n2397) );
BUFX6TS U2496 ( .A(Op_MY[26]), .Y(n3933) );
BUFX6TS U2497 ( .A(Op_MY[27]), .Y(n2743) );
BUFX6TS U2498 ( .A(Op_MY[23]), .Y(n3947) );
BUFX6TS U2499 ( .A(Op_MY[1]), .Y(n4139) );
AO22XLTS U2500 ( .A0(n4609), .A1(Data_MY[63]), .B0(n4908), .B1(Op_MY[63]),
.Y(n608) );
CLKINVX3TS U2501 ( .A(n4609), .Y(n4908) );
BUFX6TS U2502 ( .A(n875), .Y(n3494) );
BUFX6TS U2503 ( .A(n1295), .Y(n3523) );
AOI222X1TS U2504 ( .A0(n3843), .A1(n3916), .B0(n3842), .B1(n3849), .C0(n3841), .C1(n3819), .Y(n3816) );
AOI222X1TS U2505 ( .A0(n3820), .A1(n3918), .B0(n3129), .B1(n3917), .C0(n3841), .C1(n3916), .Y(n2516) );
AOI222X1TS U2506 ( .A0(n3843), .A1(n3943), .B0(n3129), .B1(n3942), .C0(n3827), .C1(n3953), .Y(n1835) );
AOI222X1TS U2507 ( .A0(n3843), .A1(n3953), .B0(n3842), .B1(n3952), .C0(n3827), .C1(n3963), .Y(n1954) );
AOI222X1TS U2508 ( .A0(n3820), .A1(n3929), .B0(n3835), .B1(n3928), .C0(n3827), .C1(n3927), .Y(n3828) );
AOI222X1TS U2509 ( .A0(n3843), .A1(n3997), .B0(n3842), .B1(n3996), .C0(n3841), .C1(n4002), .Y(n1397) );
AOI222X1TS U2510 ( .A0(n3843), .A1(n3963), .B0(n3842), .B1(n3962), .C0(n3827), .C1(n3972), .Y(n2678) );
AOI222X1TS U2511 ( .A0(n3820), .A1(n2643), .B0(n3835), .B1(n2429), .C0(n3827), .C1(n3264), .Y(n2415) );
AOI222X1TS U2512 ( .A0(n3843), .A1(n3972), .B0(n3842), .B1(n3971), .C0(n3841), .C1(n3982), .Y(n2366) );
AOI222X1TS U2513 ( .A0(n3831), .A1(n3958), .B0(n3842), .B1(n3957), .C0(n3128), .C1(n3967), .Y(n3832) );
AOI222X1TS U2514 ( .A0(n3820), .A1(n3947), .B0(n3129), .B1(n3946), .C0(n3841), .C1(n3958), .Y(n3130) );
AOI222X1TS U2515 ( .A0(n3843), .A1(n3982), .B0(n3842), .B1(n3981), .C0(n3827), .C1(n3980), .Y(n2542) );
AOI222X1TS U2516 ( .A0(n3820), .A1(n3986), .B0(n3842), .B1(n3985), .C0(n3128), .C1(n3992), .Y(n1755) );
AOI222X1TS U2517 ( .A0(n3831), .A1(n3992), .B0(n3842), .B1(n3991), .C0(n3128), .C1(n3990), .Y(n1964) );
AOI222X1TS U2518 ( .A0(n3820), .A1(n3976), .B0(n3842), .B1(n3975), .C0(n3128), .C1(n3986), .Y(n3146) );
AOI222X1TS U2519 ( .A0(n3843), .A1(n3980), .B0(n3842), .B1(n3308), .C0(n3128), .C1(n3997), .Y(n2271) );
AOI222X1TS U2520 ( .A0(n3901), .A1(n2643), .B0(n4105), .B1(n2429), .C0(n4104), .C1(n2981), .Y(n2127) );
AOI222X1TS U2521 ( .A0(n3901), .A1(n3982), .B0(n3900), .B1(n3981), .C0(n2794), .C1(n3034), .Y(n2479) );
AOI222X1TS U2522 ( .A0(n4106), .A1(n3967), .B0(n3900), .B1(n3966), .C0(n3894), .C1(n3017), .Y(n1785) );
AOI222X1TS U2523 ( .A0(n3901), .A1(n3976), .B0(n3900), .B1(n3975), .C0(n2794), .C1(n3278), .Y(n3082) );
AOI222X1TS U2524 ( .A0(n4101), .A1(n3947), .B0(n3900), .B1(n3946), .C0(n3894), .C1(n3020), .Y(n2589) );
AOI222X1TS U2525 ( .A0(n4101), .A1(n3980), .B0(n3900), .B1(n3308), .C0(n2794), .C1(n3307), .Y(n2093) );
AOI222X1TS U2526 ( .A0(n4101), .A1(n3997), .B0(n3900), .B1(n3996), .C0(n2794), .C1(n3808), .Y(n2053) );
AOI222X1TS U2527 ( .A0(n4101), .A1(n3986), .B0(n3900), .B1(n3985), .C0(n2794), .C1(n3301), .Y(n2111) );
AOI222X1TS U2528 ( .A0(n4101), .A1(n3992), .B0(n3900), .B1(n3991), .C0(n2794), .C1(n3031), .Y(n2175) );
AOI222X1TS U2529 ( .A0(n3998), .A1(n3929), .B0(n3937), .B1(n3928), .C0(n4163), .C1(n3927), .Y(n3930) );
AOI222X1TS U2530 ( .A0(n3998), .A1(n3916), .B0(n3937), .B1(n3849), .C0(n3995), .C1(n3819), .Y(n2575) );
AOI222X1TS U2531 ( .A0(n4167), .A1(n3918), .B0(n3937), .B1(n3917), .C0(n4163), .C1(n3916), .Y(n3919) );
AOI222X1TS U2532 ( .A0(n3998), .A1(n2645), .B0(n3937), .B1(n2644), .C0(n3995), .C1(n2643), .Y(n1628) );
AOI222X1TS U2533 ( .A0(n3998), .A1(n2474), .B0(n3937), .B1(n2473), .C0(n3995), .C1(n2584), .Y(n1798) );
AOI222X1TS U2534 ( .A0(n4167), .A1(n2584), .B0(n3937), .B1(n2583), .C0(n4163), .C1(n2645), .Y(n1960) );
AOI222X1TS U2535 ( .A0(n3998), .A1(n3943), .B0(n4130), .B1(n3942), .C0(n4163), .C1(n3953), .Y(n3944) );
AOI222X1TS U2536 ( .A0(n4167), .A1(n3953), .B0(n4130), .B1(n3952), .C0(n4163), .C1(n3963), .Y(n3954) );
AOI222X1TS U2537 ( .A0(n3998), .A1(n3963), .B0(n4130), .B1(n3962), .C0(n3995), .C1(n3972), .Y(n3964) );
AOI222X1TS U2538 ( .A0(n4167), .A1(n3997), .B0(n4130), .B1(n3996), .C0(n4163), .C1(n4002), .Y(n3999) );
AOI222X1TS U2539 ( .A0(n4167), .A1(n3972), .B0(n4130), .B1(n3971), .C0(n4163), .C1(n3982), .Y(n3973) );
AOI222X1TS U2540 ( .A0(n4167), .A1(n3982), .B0(n4130), .B1(n3981), .C0(n4163), .C1(n3980), .Y(n3983) );
AOI222X1TS U2541 ( .A0(n3998), .A1(n3976), .B0(n4130), .B1(n3975), .C0(n3951), .C1(n3986), .Y(n3977) );
AOI222X1TS U2542 ( .A0(n4134), .A1(n3967), .B0(n4130), .B1(n3966), .C0(n3951), .C1(n3976), .Y(n3968) );
AOI222X1TS U2543 ( .A0(n4134), .A1(n3947), .B0(n4130), .B1(n3946), .C0(n3951), .C1(n3958), .Y(n3948) );
AOI222X1TS U2544 ( .A0(n4134), .A1(n3986), .B0(n4130), .B1(n3985), .C0(n3951), .C1(n3992), .Y(n3987) );
AOI222X1TS U2545 ( .A0(n4134), .A1(n3992), .B0(n4130), .B1(n3991), .C0(n3951), .C1(n3990), .Y(n3993) );
AOI222X1TS U2546 ( .A0(n4134), .A1(n3980), .B0(n4130), .B1(n3308), .C0(n3951), .C1(n3997), .Y(n3164) );
AOI222X1TS U2547 ( .A0(n3632), .A1(n3972), .B0(n3631), .B1(n3971), .C0(n3636), .C1(n3012), .Y(n1939) );
BUFX6TS U2548 ( .A(n1635), .Y(n3638) );
BUFX6TS U2549 ( .A(n1635), .Y(n3632) );
AOI222X1TS U2550 ( .A0(n3683), .A1(n3972), .B0(n3682), .B1(n3971), .C0(n3681), .C1(n3012), .Y(n2537) );
AOI222X1TS U2551 ( .A0(n3683), .A1(n3982), .B0(n3682), .B1(n3981), .C0(n3681), .C1(n3034), .Y(n2610) );
AOI222X1TS U2552 ( .A0(n3689), .A1(n3997), .B0(n3682), .B1(n3996), .C0(n3681), .C1(n3808), .Y(n3684) );
AOI222X4TS U2553 ( .A0(n3689), .A1(n2474), .B0(n3688), .B1(n2473), .C0(n3681), .C1(n2962), .Y(n2078) );
AOI222X1TS U2554 ( .A0(n3689), .A1(n3986), .B0(n3682), .B1(n3985), .C0(n3681), .C1(n3301), .Y(n2495) );
AOI222X4TS U2555 ( .A0(n3665), .A1(n3980), .B0(n3682), .B1(n3308), .C0(n3681), .C1(n3307), .Y(n2286) );
AOI222X4TS U2556 ( .A0(n3665), .A1(n3992), .B0(n3682), .B1(n3991), .C0(n3681), .C1(n3031), .Y(n2452) );
AOI222X1TS U2557 ( .A0(n3696), .A1(n3972), .B0(n3722), .B1(n3971), .C0(n3708), .C1(n3012), .Y(n2593) );
AOI222X1TS U2558 ( .A0(n3696), .A1(n3982), .B0(n3722), .B1(n3981), .C0(n3721), .C1(n3034), .Y(n2223) );
AOI222X1TS U2559 ( .A0(n3723), .A1(n3986), .B0(n3722), .B1(n3985), .C0(n3708), .C1(n3301), .Y(n2133) );
AOI222X1TS U2560 ( .A0(n3696), .A1(n3992), .B0(n3722), .B1(n3991), .C0(n2751), .C1(n3031), .Y(n2338) );
AOI222X1TS U2561 ( .A0(n3696), .A1(n3980), .B0(n3722), .B1(n3308), .C0(n2751), .C1(n3307), .Y(n2376) );
AOI222X1TS U2562 ( .A0(n3805), .A1(n3997), .B0(n3810), .B1(n3996), .C0(n3809), .C1(n3808), .Y(n3812) );
AOI222X1TS U2563 ( .A0(n3811), .A1(n3972), .B0(n3810), .B1(n3971), .C0(n3809), .C1(n3012), .Y(n2273) );
AOI222X1TS U2564 ( .A0(n3805), .A1(n3982), .B0(n3810), .B1(n3981), .C0(n3809), .C1(n3034), .Y(n2684) );
AOI222X1TS U2565 ( .A0(n3811), .A1(n3947), .B0(n3151), .B1(n3946), .C0(n3156), .C1(n3020), .Y(n2505) );
AOI222X1TS U2566 ( .A0(n3788), .A1(n3967), .B0(n3810), .B1(n3966), .C0(n3803), .C1(n3017), .Y(n2095) );
AOI222X1TS U2567 ( .A0(n3788), .A1(n3976), .B0(n3810), .B1(n3975), .C0(n3803), .C1(n3278), .Y(n2614) );
AOI222X1TS U2568 ( .A0(n3788), .A1(n3986), .B0(n3810), .B1(n3985), .C0(n3803), .C1(n3301), .Y(n2257) );
AOI222X1TS U2569 ( .A0(n3788), .A1(n3992), .B0(n3810), .B1(n3991), .C0(n3803), .C1(n3031), .Y(n2634) );
AOI222X1TS U2570 ( .A0(n3788), .A1(n3980), .B0(n3810), .B1(n3308), .C0(n3803), .C1(n3307), .Y(n2382) );
AOI222X1TS U2571 ( .A0(n2424), .A1(n3972), .B0(n3779), .B1(n3971), .C0(n3772), .C1(n3982), .Y(n1722) );
AOI222X1TS U2572 ( .A0(n3780), .A1(n3890), .B0(n3758), .B1(n3889), .C0(n3772), .C1(n3859), .Y(n2206) );
AOI222X1TS U2573 ( .A0(n2424), .A1(n3943), .B0(n3768), .B1(n3942), .C0(n3772), .C1(n3953), .Y(n2798) );
AOI222X1TS U2574 ( .A0(n3780), .A1(n3929), .B0(n3758), .B1(n3928), .C0(n3772), .C1(n3927), .Y(n3759) );
AOI222X1TS U2575 ( .A0(n2424), .A1(n3918), .B0(n3768), .B1(n3917), .C0(n3772), .C1(n3916), .Y(n1804) );
AOI222X1TS U2576 ( .A0(n3780), .A1(n3982), .B0(n3779), .B1(n3981), .C0(n3778), .C1(n3980), .Y(n2321) );
AOI222X1TS U2577 ( .A0(n3780), .A1(n3963), .B0(n3768), .B1(n3962), .C0(n3778), .C1(n3972), .Y(n2411) );
AOI222X1TS U2578 ( .A0(n3780), .A1(n3916), .B0(n3768), .B1(n3849), .C0(n3778), .C1(n3819), .Y(n2219) );
AOI222X1TS U2579 ( .A0(n3780), .A1(n3976), .B0(n3779), .B1(n3975), .C0(n3772), .C1(n3986), .Y(n1875) );
AOI222X1TS U2580 ( .A0(n2424), .A1(n3947), .B0(n3768), .B1(n3946), .C0(n3778), .C1(n3958), .Y(n3179) );
AOI222X1TS U2581 ( .A0(n3773), .A1(n3980), .B0(n3779), .B1(n3308), .C0(n3764), .C1(n3997), .Y(n2450) );
AOI222X1TS U2582 ( .A0(n3780), .A1(n3992), .B0(n3779), .B1(n3991), .C0(n3764), .C1(n3990), .Y(n2548) );
AOI222X1TS U2583 ( .A0(n2424), .A1(n3958), .B0(n3768), .B1(n3957), .C0(n3764), .C1(n3967), .Y(n3769) );
AOI222X1TS U2584 ( .A0(n3773), .A1(n3967), .B0(n3779), .B1(n3966), .C0(n3764), .C1(n3976), .Y(n2105) );
AOI222X1TS U2585 ( .A0(n3750), .A1(n3997), .B0(n3743), .B1(n3996), .C0(n3739), .C1(n3808), .Y(n1781) );
AOI222X1TS U2586 ( .A0(n3750), .A1(n3982), .B0(n3743), .B1(n3981), .C0(n3748), .C1(n3034), .Y(n2157) );
AOI222X1TS U2587 ( .A0(n3750), .A1(n3972), .B0(n3743), .B1(n3971), .C0(n3739), .C1(n3012), .Y(n2535) );
AOI222X1TS U2588 ( .A0(n3750), .A1(n3986), .B0(n3743), .B1(n3985), .C0(n3748), .C1(n3301), .Y(n1929) );
AOI222X1TS U2589 ( .A0(n3732), .A1(n3980), .B0(n3743), .B1(n3308), .C0(n3739), .C1(n3307), .Y(n2216) );
AOI222X1TS U2590 ( .A0(n4036), .A1(n3972), .B0(n4035), .B1(n3971), .C0(n4034), .C1(n3012), .Y(n2202) );
BUFX6TS U2591 ( .A(n3850), .Y(n4036) );
AOI222X1TS U2592 ( .A0(n3617), .A1(n4153), .B0(n3616), .B1(n4152), .C0(n3615), .C1(n4080), .Y(n3177) );
AOI222X1TS U2593 ( .A0(n3617), .A1(n4162), .B0(n3616), .B1(n4118), .C0(n3615), .C1(n4090), .Y(n3361) );
BUFX6TS U2594 ( .A(n3595), .Y(n3617) );
AOI222X1TS U2595 ( .A0(n3529), .A1(n4166), .B0(n3522), .B1(n4164), .C0(n3527), .C1(n3720), .Y(n2186) );
AOI222X1TS U2596 ( .A0(n3529), .A1(n4162), .B0(n3522), .B1(n4118), .C0(n3527), .C1(n4090), .Y(n1296) );
AOI222X1TS U2597 ( .A0(n3529), .A1(n4151), .B0(n3522), .B1(n4140), .C0(n3527), .C1(n4139), .Y(n1304) );
AOI222X4TS U2598 ( .A0(n3529), .A1(n4126), .B0(n3522), .B1(n4125), .C0(n3518), .C1(n4124), .Y(n3091) );
CLKINVX6TS U2599 ( .A(n3194), .Y(n3518) );
CLKINVX6TS U2600 ( .A(n3194), .Y(n3527) );
CLKINVX6TS U2601 ( .A(n1573), .Y(n4109) );
CLKINVX6TS U2602 ( .A(n840), .Y(n3504) );
CLKINVX6TS U2603 ( .A(n1297), .Y(n3525) );
CLKINVX6TS U2604 ( .A(n1345), .Y(n3557) );
CLKINVX6TS U2605 ( .A(n1444), .Y(n3586) );
CLKINVX6TS U2606 ( .A(n1605), .Y(n3620) );
CLKINVX6TS U2607 ( .A(n1486), .Y(n3634) );
CLKINVX6TS U2608 ( .A(n1505), .Y(n3663) );
ADDHXLTS U2609 ( .A(Sgf_normalized_result[50]), .B(n5052), .CO(n5056), .S(
n5050) );
ADDHXLTS U2610 ( .A(Sgf_normalized_result[49]), .B(n5049), .CO(n5052), .S(
n5048) );
ADDHXLTS U2611 ( .A(Sgf_normalized_result[48]), .B(n5047), .CO(n5049), .S(
n5046) );
ADDHXLTS U2612 ( .A(Sgf_normalized_result[47]), .B(n5045), .CO(n5047), .S(
n5044) );
ADDHXLTS U2613 ( .A(Sgf_normalized_result[21]), .B(n4993), .CO(n4995), .S(
n4992) );
ADDHXLTS U2614 ( .A(Sgf_normalized_result[20]), .B(n4991), .CO(n4993), .S(
n4990) );
ADDHXLTS U2615 ( .A(Sgf_normalized_result[19]), .B(n4989), .CO(n4991), .S(
n4988) );
ADDHXLTS U2616 ( .A(Sgf_normalized_result[18]), .B(n4987), .CO(n4989), .S(
n4985) );
ADDHXLTS U2617 ( .A(Sgf_normalized_result[17]), .B(n4984), .CO(n4987), .S(
n4983) );
ADDHXLTS U2618 ( .A(Sgf_normalized_result[15]), .B(n4980), .CO(n4982), .S(
n4979) );
ADDHXLTS U2619 ( .A(Sgf_normalized_result[12]), .B(n4974), .CO(n4976), .S(
n4973) );
ADDHXLTS U2620 ( .A(Sgf_normalized_result[11]), .B(n4972), .CO(n4974), .S(
n4971) );
ADDHXLTS U2621 ( .A(Sgf_normalized_result[10]), .B(n4970), .CO(n4972), .S(
n4969) );
ADDHXLTS U2622 ( .A(Sgf_normalized_result[9]), .B(n4968), .CO(n4970), .S(
n4967) );
ADDHXLTS U2623 ( .A(Sgf_normalized_result[8]), .B(n4966), .CO(n4968), .S(
n4965) );
ADDHXLTS U2624 ( .A(Sgf_normalized_result[7]), .B(n4964), .CO(n4966), .S(
n4963) );
ADDHXLTS U2625 ( .A(Sgf_normalized_result[6]), .B(n4962), .CO(n4964), .S(
n4961) );
XNOR2X2TS U2626 ( .A(Op_MX[0]), .B(Op_MX[1]), .Y(n1473) );
BUFX6TS U2627 ( .A(n4657), .Y(n4875) );
ADDHXLTS U2628 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.CO(n4958), .S(n4956) );
BUFX6TS U2629 ( .A(Op_MY[51]), .Y(n2729) );
NOR4X1TS U2630 ( .A(Op_MY[51]), .B(n699), .C(Op_MY[0]), .D(Op_MY[52]), .Y(
n4922) );
BUFX6TS U2631 ( .A(Op_MY[49]), .Y(n3235) );
BUFX6TS U2632 ( .A(Op_MY[48]), .Y(n2713) );
BUFX6TS U2633 ( .A(Op_MY[46]), .Y(n2607) );
BUFX6TS U2634 ( .A(Op_MY[40]), .Y(n3916) );
BUFX6TS U2635 ( .A(Op_MY[37]), .Y(n2474) );
BUFX6TS U2636 ( .A(Op_MY[32]), .Y(n3859) );
BUFX6TS U2637 ( .A(Op_MY[30]), .Y(n3929) );
BUFX6TS U2638 ( .A(Op_MY[25]), .Y(n3938) );
BUFX6TS U2639 ( .A(Op_MY[22]), .Y(n3953) );
BUFX6TS U2640 ( .A(Op_MY[18]), .Y(n3972) );
BUFX6TS U2641 ( .A(Op_MY[16]), .Y(n3982) );
BUFX6TS U2642 ( .A(Op_MY[4]), .Y(n3720) );
BUFX6TS U2643 ( .A(Op_MY[4]), .Y(n4162) );
BUFX6TS U2644 ( .A(Op_MY[2]), .Y(n4090) );
BUFX6TS U2645 ( .A(Op_MY[2]), .Y(n4126) );
NOR2BX4TS U2646 ( .AN(n3300), .B(Op_MX[51]), .Y(n4070) );
NOR4X1TS U2647 ( .A(Op_MX[0]), .B(Op_MX[51]), .C(Op_MX[8]), .D(Op_MX[5]),
.Y(n4937) );
CLKBUFX2TS U2648 ( .A(Op_MX[2]), .Y(n754) );
XNOR2X1TS U2649 ( .A(n4128), .B(n754), .Y(n756) );
OR2X1TS U2650 ( .A(n4028), .B(n4090), .Y(n757) );
NAND2X1TS U2651 ( .A(n3301), .B(n3034), .Y(n868) );
INVX2TS U2652 ( .A(n887), .Y(n2001) );
NAND2X1TS U2653 ( .A(n3717), .B(n3297), .Y(n1415) );
NAND2X1TS U2654 ( .A(n3034), .B(n3278), .Y(n862) );
OR2X1TS U2655 ( .A(n3808), .B(n3031), .Y(n1403) );
OAI21X1TS U2656 ( .A0(n2007), .A1(n1530), .B0(n1529), .Y(n1774) );
OAI21XLTS U2657 ( .A0(n3069), .A1(n3281), .B0(n3102), .Y(n3103) );
NAND2X1TS U2658 ( .A(n1491), .B(n1494), .Y(n842) );
OAI21XLTS U2659 ( .A0(n4137), .A1(n3140), .B0(n3137), .Y(n3138) );
OAI21XLTS U2660 ( .A0(n645), .A1(n3140), .B0(n3139), .Y(n3141) );
OAI21XLTS U2661 ( .A0(n4120), .A1(n3619), .B0(n3361), .Y(n3362) );
OAI21XLTS U2662 ( .A0(n645), .A1(n3317), .B0(n3316), .Y(n3318) );
OAI21XLTS U2663 ( .A0(n3940), .A1(n3628), .B0(n2011), .Y(n2012) );
OAI21XLTS U2664 ( .A0(n3310), .A1(n3317), .B0(n3309), .Y(n3311) );
OAI21X1TS U2665 ( .A0(n2007), .A1(n833), .B0(n832), .Y(n2149) );
BUFX6TS U2666 ( .A(Op_MY[1]), .Y(n4028) );
INVX2TS U2667 ( .A(n1349), .Y(n1414) );
OAI21XLTS U2668 ( .A0(n4155), .A1(n3661), .B0(n3126), .Y(n3127) );
OAI21XLTS U2669 ( .A0(n642), .A1(n3661), .B0(n2099), .Y(n2100) );
OAI21XLTS U2670 ( .A0(n4155), .A1(n3592), .B0(n1630), .Y(n1631) );
OAI21XLTS U2671 ( .A0(n3940), .A1(n3766), .B0(n2579), .Y(n2580) );
OAI21XLTS U2672 ( .A0(n2973), .A1(n3798), .B0(n2430), .Y(n2431) );
OAI21XLTS U2673 ( .A0(n643), .A1(n3122), .B0(n2573), .Y(n2574) );
OAI21XLTS U2674 ( .A0(n3925), .A1(n2796), .B0(n2413), .Y(n2414) );
OAI21XLTS U2675 ( .A0(n2692), .A1(n3702), .B0(n1917), .Y(n1918) );
OAI21XLTS U2676 ( .A0(n3978), .A1(n3122), .B0(n1760), .Y(n1761) );
OAI21XLTS U2677 ( .A0(n2967), .A1(n3798), .B0(n1575), .Y(n1577) );
OAI21XLTS U2678 ( .A0(n2961), .A1(n3798), .B0(n1700), .Y(n1701) );
OAI21XLTS U2679 ( .A0(n2952), .A1(n3875), .B0(n2603), .Y(n2604) );
OAI21XLTS U2680 ( .A0(n638), .A1(n3679), .B0(n3678), .Y(n3680) );
OAI21XLTS U2681 ( .A0(n4046), .A1(n3955), .B0(n2442), .Y(n2443) );
OAI21XLTS U2682 ( .A0(n3940), .A1(n2757), .B0(n2097), .Y(n2098) );
OAI21XLTS U2683 ( .A0(n638), .A1(n2757), .B0(n2458), .Y(n2459) );
OAI21XLTS U2684 ( .A0(n3909), .A1(n3158), .B0(n1986), .Y(n1987) );
OAI21XLTS U2685 ( .A0(n634), .A1(n3745), .B0(n3733), .Y(n3734) );
OAI21XLTS U2686 ( .A0(n629), .A1(n3647), .B0(n2115), .Y(n2116) );
OAI21XLTS U2687 ( .A0(n631), .A1(n3675), .B0(n3668), .Y(n3669) );
OAI21XLTS U2688 ( .A0(n3978), .A1(n3317), .B0(n1968), .Y(n1969) );
OAI21XLTS U2689 ( .A0(n2945), .A1(n3766), .B0(n2023), .Y(n2024) );
OAI21XLTS U2690 ( .A0(n3949), .A1(n3531), .B0(n2208), .Y(n2209) );
OAI21XLTS U2691 ( .A0(n634), .A1(n1984), .B0(n1983), .Y(n1985) );
OAI21XLTS U2692 ( .A0(n641), .A1(n3281), .B0(n2554), .Y(n2555) );
OAI21XLTS U2693 ( .A0(n638), .A1(n3487), .B0(n2786), .Y(n2787) );
OAI21XLTS U2694 ( .A0(n3249), .A1(n3503), .B0(n839), .Y(n841) );
OAI21XLTS U2695 ( .A0(n4046), .A1(n3725), .B0(n2730), .Y(n2731) );
INVX2TS U2696 ( .A(n1724), .Y(n2976) );
OR2X1TS U2697 ( .A(n4028), .B(n4133), .Y(n759) );
OAI21XLTS U2698 ( .A0(n4155), .A1(n3752), .B0(n1432), .Y(n1433) );
OAI21XLTS U2699 ( .A0(n4086), .A1(n3752), .B0(n1702), .Y(n1703) );
OAI21XLTS U2700 ( .A0(n3949), .A1(n2796), .B0(n2589), .Y(n2590) );
OAI21XLTS U2701 ( .A0(n3940), .A1(n2796), .B0(n2674), .Y(n2675) );
OAI21XLTS U2702 ( .A0(n3288), .A1(n3725), .B0(n1848), .Y(n1849) );
OAI21XLTS U2703 ( .A0(n2692), .A1(n2660), .B0(n1835), .Y(n1836) );
OAI21XLTS U2704 ( .A0(n2952), .A1(n3955), .B0(n3919), .Y(n3920) );
NAND2X1TS U2705 ( .A(n998), .B(n940), .Y(n942) );
OAI21XLTS U2706 ( .A0(n4120), .A1(n4096), .B0(n4091), .Y(n4092) );
OAI21XLTS U2707 ( .A0(n3002), .A1(n4169), .B0(n1880), .Y(n1881) );
OAI21XLTS U2708 ( .A0(n3002), .A1(n4096), .B0(n1837), .Y(n1838) );
OAI21XLTS U2709 ( .A0(n4086), .A1(n3845), .B0(n1383), .Y(n1385) );
OAI21XLTS U2710 ( .A0(n640), .A1(n3845), .B0(n3836), .Y(n3838) );
CLKINVX6TS U2711 ( .A(n1282), .Y(n2973) );
NOR2X1TS U2712 ( .A(n4688), .B(n4689), .Y(n4678) );
OAI21XLTS U2713 ( .A0(n4057), .A1(n3487), .B0(n935), .Y(n936) );
OAI21XLTS U2714 ( .A0(n4057), .A1(n4056), .B0(n4055), .Y(n4058) );
OR2X1TS U2715 ( .A(n4160), .B(n4159), .Y(n4299) );
OR2X1TS U2716 ( .A(Sgf_operation_mult_x_1_n2687), .B(
Sgf_operation_mult_x_1_n2696), .Y(n4531) );
OR2X1TS U2717 ( .A(Sgf_operation_mult_x_1_n2537), .B(
Sgf_operation_mult_x_1_n2552), .Y(n4372) );
OR2X1TS U2718 ( .A(Sgf_operation_mult_x_1_n2357), .B(
Sgf_operation_mult_x_1_n2376), .Y(n4464) );
OR2X1TS U2719 ( .A(Sgf_operation_mult_x_1_n2271), .B(
Sgf_operation_mult_x_1_n2292), .Y(n4445) );
NAND2X1TS U2720 ( .A(n4678), .B(n4683), .Y(n4671) );
OAI21XLTS U2721 ( .A0(n627), .A1(n4075), .B0(n4074), .Y(n4076) );
OAI21XLTS U2722 ( .A0(n4502), .A1(n4498), .B0(n4499), .Y(n4484) );
OAI21XLTS U2723 ( .A0(n4555), .A1(n4505), .B0(n4504), .Y(n4509) );
ADDHXLTS U2724 ( .A(Sgf_normalized_result[16]), .B(n4982), .CO(n4984), .S(
n4981) );
OAI31X1TS U2725 ( .A0(n5150), .A1(n3057), .A2(n3056), .B0(n5074), .Y(n602)
);
OAI211XLTS U2726 ( .A0(n2903), .A1(n5137), .B0(n2871), .C0(n2870), .Y(n364)
);
OAI211XLTS U2727 ( .A0(n2931), .A1(n5109), .B0(n2930), .C0(n2929), .Y(n392)
);
CLKBUFX2TS U2728 ( .A(n5076), .Y(n5151) );
CLKINVX6TS U2729 ( .A(n5151), .Y(n5152) );
CLKBUFX2TS U2730 ( .A(n5083), .Y(n1408) );
CLKINVX6TS U2731 ( .A(n1408), .Y(n4094) );
XNOR2X2TS U2732 ( .A(n4094), .B(Op_MX[9]), .Y(n1381) );
CLKBUFX2TS U2733 ( .A(n5080), .Y(n1384) );
CLKINVX6TS U2734 ( .A(n1384), .Y(n2661) );
CLKXOR2X2TS U2735 ( .A(n2661), .B(Op_MX[10]), .Y(n1382) );
NAND2BX2TS U2736 ( .AN(n1381), .B(n1382), .Y(n2660) );
BUFX3TS U2737 ( .A(n2660), .Y(n3833) );
NOR2X2TS U2738 ( .A(n1382), .B(n1381), .Y(n1395) );
BUFX4TS U2739 ( .A(n1395), .Y(n3820) );
NOR2BX2TS U2740 ( .AN(n1381), .B(n1380), .Y(n1396) );
BUFX4TS U2741 ( .A(n1396), .Y(n3129) );
CLKINVX6TS U2742 ( .A(n4137), .Y(n4129) );
AOI22X1TS U2743 ( .A0(n3843), .A1(n4028), .B0(n3129), .B1(n4129), .Y(n760)
);
CLKINVX6TS U2744 ( .A(n1384), .Y(n3846) );
XOR2X1TS U2745 ( .A(n761), .B(n3846), .Y(n3436) );
NAND2X1TS U2746 ( .A(n3820), .B(n4133), .Y(n762) );
XOR2X1TS U2747 ( .A(n763), .B(n3846), .Y(n1638) );
OR2X1TS U2748 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
CLKBUFX2TS U2749 ( .A(n5092), .Y(n1297) );
CLKINVX6TS U2750 ( .A(n1297), .Y(n3344) );
XNOR2X2TS U2751 ( .A(n3344), .B(Op_MX[45]), .Y(n837) );
CLKBUFX2TS U2752 ( .A(n5093), .Y(n840) );
CLKINVX6TS U2753 ( .A(n840), .Y(n2769) );
CLKXOR2X2TS U2754 ( .A(n2769), .B(Op_MX[46]), .Y(n838) );
NAND2BX2TS U2755 ( .AN(n837), .B(n838), .Y(n1070) );
BUFX3TS U2756 ( .A(n1070), .Y(n3317) );
NOR2X2TS U2757 ( .A(n838), .B(n837), .Y(n875) );
BUFX4TS U2758 ( .A(n875), .Y(n1235) );
NOR2BX2TS U2759 ( .AN(n837), .B(n836), .Y(n876) );
BUFX4TS U2760 ( .A(n876), .Y(n2767) );
AOI22X1TS U2761 ( .A0(n1235), .A1(n4028), .B0(n2767), .B1(n4129), .Y(n764)
);
XOR2X1TS U2762 ( .A(n765), .B(n3504), .Y(n3315) );
NAND2X1TS U2763 ( .A(n1235), .B(n4133), .Y(n766) );
XOR2X1TS U2764 ( .A(n767), .B(n3504), .Y(n1455) );
CLKBUFX2TS U2765 ( .A(n5081), .Y(n1596) );
CLKINVX6TS U2766 ( .A(n1596), .Y(n3424) );
XNOR2X2TS U2767 ( .A(n3424), .B(Op_MX[21]), .Y(n1459) );
CLKBUFX2TS U2768 ( .A(n5079), .Y(n1540) );
CLKINVX6TS U2769 ( .A(n1540), .Y(n2761) );
CLKXOR2X2TS U2770 ( .A(n2761), .B(Op_MX[22]), .Y(n1460) );
NAND2BX2TS U2771 ( .AN(n1459), .B(n1460), .Y(n3706) );
NOR2X2TS U2772 ( .A(n1460), .B(n1459), .Y(n1538) );
BUFX4TS U2773 ( .A(n1538), .Y(n3696) );
NOR2BX2TS U2774 ( .AN(n1459), .B(n1458), .Y(n1522) );
BUFX4TS U2775 ( .A(n1522), .Y(n3704) );
AOI22X1TS U2776 ( .A0(n3723), .A1(n4028), .B0(n3704), .B1(n4129), .Y(n768)
);
CLKINVX6TS U2777 ( .A(n1540), .Y(n3726) );
XOR2X1TS U2778 ( .A(n769), .B(n3726), .Y(n3396) );
NAND2X1TS U2779 ( .A(n3696), .B(n4129), .Y(n770) );
XOR2X1TS U2780 ( .A(n771), .B(n3726), .Y(n1470) );
CLKBUFX2TS U2781 ( .A(n5084), .Y(n1468) );
CLKINVX6TS U2782 ( .A(n1468), .Y(n3404) );
XNOR2X2TS U2783 ( .A(n3404), .B(Op_MX[27]), .Y(n1273) );
CLKBUFX2TS U2784 ( .A(n5085), .Y(n1505) );
CLKINVX6TS U2785 ( .A(n1505), .Y(n2758) );
CLKXOR2X2TS U2786 ( .A(n2758), .B(Op_MX[28]), .Y(n1274) );
NAND2BX2TS U2787 ( .AN(n1273), .B(n1274), .Y(n1984) );
BUFX3TS U2788 ( .A(n1984), .Y(n3647) );
NOR2X2TS U2789 ( .A(n1274), .B(n1273), .Y(n1502) );
BUFX4TS U2790 ( .A(n1502), .Y(n2695) );
NOR2BX2TS U2791 ( .AN(n1273), .B(n1272), .Y(n1503) );
BUFX4TS U2792 ( .A(n1503), .Y(n3650) );
AOI22X1TS U2793 ( .A0(n2695), .A1(n4028), .B0(n3650), .B1(n4129), .Y(n772)
);
XOR2X1TS U2794 ( .A(n773), .B(n3663), .Y(n3376) );
NAND2X1TS U2795 ( .A(n2695), .B(n4133), .Y(n774) );
XOR2X1TS U2796 ( .A(n775), .B(n3663), .Y(n1501) );
CLKBUFX2TS U2797 ( .A(n5086), .Y(n1486) );
CLKINVX6TS U2798 ( .A(n1486), .Y(n3384) );
XNOR2X2TS U2799 ( .A(n3384), .B(Op_MX[33]), .Y(n1152) );
CLKBUFX2TS U2800 ( .A(n5087), .Y(n1605) );
CLKINVX6TS U2801 ( .A(n1605), .Y(n2666) );
CLKXOR2X2TS U2802 ( .A(n2666), .B(Op_MX[34]), .Y(n1153) );
NAND2BX2TS U2803 ( .AN(n1152), .B(n1153), .Y(n1611) );
BUFX3TS U2804 ( .A(n1611), .Y(n3607) );
NOR2X4TS U2805 ( .A(n1153), .B(n1152), .Y(n3595) );
BUFX4TS U2806 ( .A(n3595), .Y(n3610) );
NOR2BX2TS U2807 ( .AN(n1152), .B(n1151), .Y(n1713) );
BUFX4TS U2808 ( .A(n1713), .Y(n3598) );
AOI22X1TS U2809 ( .A0(n3610), .A1(n4028), .B0(n3598), .B1(n4129), .Y(n776)
);
XOR2X1TS U2810 ( .A(n777), .B(n3620), .Y(n3356) );
NAND2X1TS U2811 ( .A(n3610), .B(n4133), .Y(n778) );
XOR2X1TS U2812 ( .A(n779), .B(n3620), .Y(n1558) );
CLKBUFX2TS U2813 ( .A(n5082), .Y(n1576) );
CLKINVX6TS U2814 ( .A(n1576), .Y(n3444) );
XNOR2X2TS U2815 ( .A(n3444), .B(Op_MX[15]), .Y(n1619) );
CLKBUFX2TS U2816 ( .A(n5077), .Y(n1622) );
CLKINVX6TS U2817 ( .A(n1622), .Y(n2799) );
CLKXOR2X2TS U2818 ( .A(n2799), .B(Op_MX[16]), .Y(n1620) );
NAND2BX2TS U2819 ( .AN(n1619), .B(n1620), .Y(n3756) );
BUFX3TS U2820 ( .A(n3756), .Y(n3770) );
NOR2X2TS U2821 ( .A(n1620), .B(n1619), .Y(n1721) );
BUFX4TS U2822 ( .A(n1721), .Y(n2424) );
NOR2BX2TS U2823 ( .AN(n1619), .B(n1618), .Y(n1716) );
BUFX4TS U2824 ( .A(n1716), .Y(n3758) );
AOI22X1TS U2825 ( .A0(n3780), .A1(n4139), .B0(n3758), .B1(n4129), .Y(n780)
);
CLKINVX6TS U2826 ( .A(n1622), .Y(n3783) );
XOR2X1TS U2827 ( .A(n781), .B(n3783), .Y(n3416) );
NAND2X1TS U2828 ( .A(n2424), .B(n4133), .Y(n782) );
XOR2X1TS U2829 ( .A(n783), .B(n3783), .Y(n1590) );
CLKBUFX2TS U2830 ( .A(n5090), .Y(n1444) );
CLKINVX6TS U2831 ( .A(n1444), .Y(n3364) );
XNOR2X2TS U2832 ( .A(n3364), .B(Op_MX[39]), .Y(n1033) );
CLKBUFX2TS U2833 ( .A(n5091), .Y(n1345) );
CLKINVX6TS U2834 ( .A(n1345), .Y(n2344) );
CLKXOR2X2TS U2835 ( .A(n2344), .B(Op_MX[40]), .Y(n1034) );
NAND2BX2TS U2836 ( .AN(n1033), .B(n1034), .Y(n1174) );
BUFX3TS U2837 ( .A(n1174), .Y(n3337) );
NOR2X2TS U2838 ( .A(n1034), .B(n1033), .Y(n1434) );
BUFX4TS U2839 ( .A(n1434), .Y(n1452) );
NOR2BX2TS U2840 ( .AN(n1033), .B(n1032), .Y(n1435) );
BUFX4TS U2841 ( .A(n1435), .Y(n3542) );
AOI22X1TS U2842 ( .A0(n1452), .A1(n4028), .B0(n3542), .B1(n4129), .Y(n784)
);
XOR2X1TS U2843 ( .A(n785), .B(n3557), .Y(n3335) );
NAND2X1TS U2844 ( .A(n1452), .B(n4129), .Y(n786) );
XOR2X1TS U2845 ( .A(n787), .B(n3557), .Y(n1698) );
INVX2TS U2846 ( .A(n2987), .Y(n792) );
INVX2TS U2847 ( .A(n1299), .Y(n1289) );
INVX2TS U2848 ( .A(n1290), .Y(n788) );
BUFX6TS U2849 ( .A(Op_MY[5]), .Y(n3717) );
BUFX6TS U2850 ( .A(Op_MY[6]), .Y(n3297) );
BUFX6TS U2851 ( .A(Op_MY[7]), .Y(n3294) );
INVX2TS U2852 ( .A(n1374), .Y(n1585) );
BUFX6TS U2853 ( .A(Op_MY[8]), .Y(n3877) );
BUFX6TS U2854 ( .A(Op_MY[9]), .Y(n3289) );
BUFX6TS U2855 ( .A(Op_MY[10]), .Y(n3808) );
BUFX6TS U2856 ( .A(Op_MY[11]), .Y(n3031) );
BUFX6TS U2857 ( .A(Op_MY[12]), .Y(n3307) );
INVX2TS U2858 ( .A(n1350), .Y(n1412) );
INVX2TS U2859 ( .A(n1415), .Y(n794) );
NOR2X1TS U2860 ( .A(n1412), .B(n794), .Y(n1371) );
INVX2TS U2861 ( .A(n1584), .Y(n796) );
INVX2TS U2862 ( .A(n1375), .Y(n795) );
INVX2TS U2863 ( .A(n1599), .Y(n1941) );
NAND2X1TS U2864 ( .A(n3289), .B(n3808), .Y(n1944) );
INVX2TS U2865 ( .A(n1944), .Y(n799) );
NOR2X1TS U2866 ( .A(n1941), .B(n799), .Y(n1388) );
INVX2TS U2867 ( .A(n1402), .Y(n1390) );
NAND2X1TS U2868 ( .A(n3031), .B(n3307), .Y(n1391) );
INVX2TS U2869 ( .A(n1391), .Y(n800) );
BUFX6TS U2870 ( .A(Op_MY[13]), .Y(n3301) );
INVX2TS U2871 ( .A(n867), .Y(n1809) );
BUFX6TS U2872 ( .A(Op_MY[14]), .Y(n3034) );
BUFX6TS U2873 ( .A(Op_MY[15]), .Y(n3278) );
BUFX6TS U2874 ( .A(Op_MY[16]), .Y(n3012) );
BUFX6TS U2875 ( .A(Op_MY[17]), .Y(n3017) );
BUFX6TS U2876 ( .A(Op_MY[18]), .Y(n3015) );
BUFX6TS U2877 ( .A(Op_MY[19]), .Y(n3899) );
BUFX6TS U2878 ( .A(Op_MY[20]), .Y(n3008) );
INVX2TS U2879 ( .A(n1808), .Y(n808) );
INVX2TS U2880 ( .A(n868), .Y(n807) );
NOR2X1TS U2881 ( .A(n808), .B(n807), .Y(n860) );
INVX2TS U2882 ( .A(n862), .Y(n1511) );
NAND2X1TS U2883 ( .A(n3278), .B(n3012), .Y(n1514) );
INVX2TS U2884 ( .A(n1514), .Y(n809) );
INVX2TS U2885 ( .A(n1704), .Y(n1546) );
NAND2X1TS U2886 ( .A(n3017), .B(n3015), .Y(n1547) );
INVX2TS U2887 ( .A(n1547), .Y(n812) );
NOR2X1TS U2888 ( .A(n1546), .B(n812), .Y(n1526) );
INVX2TS U2889 ( .A(n1531), .Y(n1772) );
NAND2X1TS U2890 ( .A(n3899), .B(n3008), .Y(n1775) );
INVX2TS U2891 ( .A(n1775), .Y(n813) );
OAI21X1TS U2892 ( .A0(n1526), .A1(n815), .B0(n814), .Y(n816) );
BUFX6TS U2893 ( .A(Op_MY[21]), .Y(n3020) );
NAND2X1TS U2894 ( .A(n1491), .B(n823), .Y(n818) );
XNOR2X1TS U2895 ( .A(n1492), .B(n818), .Y(n819) );
XNOR2X4TS U2896 ( .A(n4062), .B(Op_MX[51]), .Y(n3203) );
BUFX4TS U2897 ( .A(n3203), .Y(n4042) );
AND2X2TS U2898 ( .A(n3300), .B(Op_MX[51]), .Y(n3230) );
INVX2TS U2899 ( .A(n3230), .Y(n4041) );
BUFX4TS U2900 ( .A(n4070), .Y(n4048) );
AOI21X1TS U2901 ( .A0(n3035), .A1(n3899), .B0(n820), .Y(n821) );
OAI21X1TS U2902 ( .A0(n3960), .A1(n3300), .B0(n821), .Y(n3261) );
INVX2TS U2903 ( .A(n3261), .Y(n857) );
BUFX6TS U2904 ( .A(Op_MY[22]), .Y(n3024) );
BUFX6TS U2905 ( .A(Op_MY[23]), .Y(n3272) );
BUFX6TS U2906 ( .A(Op_MY[24]), .Y(n3872) );
INVX2TS U2907 ( .A(n2003), .Y(n822) );
BUFX6TS U2908 ( .A(Op_MY[25]), .Y(n3247) );
BUFX6TS U2909 ( .A(Op_MY[26]), .Y(n3866) );
NAND2X1TS U2910 ( .A(n831), .B(n2001), .Y(n833) );
INVX2TS U2911 ( .A(n897), .Y(n2004) );
INVX2TS U2912 ( .A(n823), .Y(n1490) );
NAND2X1TS U2913 ( .A(n3020), .B(n3024), .Y(n1493) );
INVX2TS U2914 ( .A(n1493), .Y(n824) );
NOR2X1TS U2915 ( .A(n1490), .B(n824), .Y(n843) );
NAND2X1TS U2916 ( .A(n3024), .B(n3272), .Y(n848) );
INVX2TS U2917 ( .A(n848), .Y(n1827) );
NAND2X1TS U2918 ( .A(n3272), .B(n3872), .Y(n1830) );
INVX2TS U2919 ( .A(n1830), .Y(n825) );
OAI21X2TS U2920 ( .A0(n843), .A1(n827), .B0(n826), .Y(n2002) );
INVX2TS U2921 ( .A(n2002), .Y(n829) );
INVX2TS U2922 ( .A(n2008), .Y(n2277) );
NAND2X1TS U2923 ( .A(n3247), .B(n3866), .Y(n2280) );
INVX2TS U2924 ( .A(n2280), .Y(n828) );
NOR2X1TS U2925 ( .A(n2277), .B(n828), .Y(n892) );
AOI21X1TS U2926 ( .A0(n2004), .A1(n831), .B0(n830), .Y(n832) );
BUFX6TS U2927 ( .A(Op_MY[27]), .Y(n3262) );
NAND2X1TS U2928 ( .A(n3866), .B(n3262), .Y(n888) );
NAND2X1TS U2929 ( .A(n2148), .B(n888), .Y(n834) );
BUFX4TS U2930 ( .A(n1070), .Y(n3503) );
BUFX4TS U2931 ( .A(n875), .Y(n3501) );
BUFX4TS U2932 ( .A(n876), .Y(n3489) );
BUFX4TS U2933 ( .A(Op_MY[26]), .Y(n2742) );
NAND3X2TS U2934 ( .A(n838), .B(n837), .C(n836), .Y(n957) );
INVX4TS U2935 ( .A(n957), .Y(n3493) );
AOI222X1TS U2936 ( .A0(n3501), .A1(n2743), .B0(n3489), .B1(n2742), .C0(n3493), .C1(n3247), .Y(n839) );
XOR2X1TS U2937 ( .A(n841), .B(n3491), .Y(n856) );
INVX2TS U2938 ( .A(n842), .Y(n845) );
NAND2X1TS U2939 ( .A(n2001), .B(n845), .Y(n847) );
INVX2TS U2940 ( .A(n843), .Y(n844) );
AOI21X1TS U2941 ( .A0(n2004), .A1(n845), .B0(n844), .Y(n846) );
NAND2X1TS U2942 ( .A(n1828), .B(n848), .Y(n849) );
XNOR2X1TS U2943 ( .A(n1829), .B(n849), .Y(n850) );
XNOR2X2TS U2944 ( .A(n2769), .B(Op_MX[48]), .Y(n852) );
CLKXOR2X2TS U2945 ( .A(n4062), .B(Op_MX[49]), .Y(n853) );
NAND2BX2TS U2946 ( .AN(n852), .B(n853), .Y(n4056) );
BUFX4TS U2947 ( .A(n4056), .Y(n4060) );
NOR2X2TS U2948 ( .A(n853), .B(n852), .Y(n1163) );
NOR2BX2TS U2949 ( .AN(n852), .B(n851), .Y(n1164) );
BUFX4TS U2950 ( .A(n1164), .Y(n4052) );
BUFX4TS U2951 ( .A(Op_MY[22]), .Y(n3946) );
NAND3X2TS U2952 ( .A(n853), .B(n852), .C(n851), .Y(n4059) );
XOR2X1TS U2953 ( .A(n855), .B(n3282), .Y(n3022) );
CMPR32X2TS U2954 ( .A(n857), .B(n856), .C(n3022), .CO(
Sgf_operation_mult_x_1_n1651), .S(Sgf_operation_mult_x_1_n1652) );
NAND4X1TS U2955 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]),
.C(n5070), .D(n5181), .Y(n4905) );
NAND2BXLTS U2956 ( .AN(n4905), .B(P_Sgf[105]), .Y(n2810) );
NAND3X1TS U2957 ( .A(FS_Module_state_reg[0]), .B(n5150), .C(n5072), .Y(n4906) );
INVX2TS U2958 ( .A(n4951), .Y(n4949) );
CLKBUFX2TS U2959 ( .A(n858), .Y(n5055) );
NAND2X1TS U2960 ( .A(n4949), .B(n5051), .Y(n859) );
AO21XLTS U2961 ( .A0(FSM_selector_B[0]), .A1(n2810), .B0(n859), .Y(n418) );
NAND2X1TS U2962 ( .A(n1512), .B(n862), .Y(n863) );
XNOR2X1TS U2963 ( .A(n1513), .B(n863), .Y(n864) );
AOI21X1TS U2964 ( .A0(n3035), .A1(n3301), .B0(n865), .Y(n866) );
OAI21X1TS U2965 ( .A0(n3988), .A1(n3300), .B0(n866), .Y(n880) );
NAND2X1TS U2966 ( .A(n869), .B(n868), .Y(n870) );
XNOR2X1TS U2967 ( .A(n871), .B(n870), .Y(n872) );
AOI21X1TS U2968 ( .A0(n3035), .A1(n3307), .B0(n873), .Y(n874) );
OAI21X1TS U2969 ( .A0(n3310), .A1(n3300), .B0(n874), .Y(n3277) );
INVX2TS U2970 ( .A(n3277), .Y(n3285) );
BUFX4TS U2971 ( .A(n876), .Y(n3500) );
BUFX4TS U2972 ( .A(Op_MY[20]), .Y(n3957) );
CLKINVX6TS U2973 ( .A(n957), .Y(n3499) );
XOR2X1TS U2974 ( .A(n878), .B(n3504), .Y(n879) );
CMPR32X2TS U2975 ( .A(n880), .B(n3285), .C(n879), .CO(
Sgf_operation_mult_x_1_n1769), .S(Sgf_operation_mult_x_1_n1770) );
NOR2X2TS U2976 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n4903) );
NOR2X1TS U2977 ( .A(FS_Module_state_reg[3]), .B(n5150), .Y(n4018) );
BUFX3TS U2978 ( .A(n881), .Y(n5180) );
BUFX3TS U2979 ( .A(Sgf_operation_n3), .Y(n5156) );
BUFX3TS U2980 ( .A(n881), .Y(n5163) );
BUFX3TS U2981 ( .A(n881), .Y(n5165) );
BUFX3TS U2982 ( .A(n881), .Y(n5178) );
BUFX3TS U2983 ( .A(n5169), .Y(n5176) );
BUFX3TS U2984 ( .A(n881), .Y(n5174) );
BUFX3TS U2985 ( .A(n5177), .Y(n5172) );
BUFX3TS U2986 ( .A(Sgf_operation_n3), .Y(n5160) );
BUFX3TS U2987 ( .A(Sgf_operation_n3), .Y(n5159) );
BUFX3TS U2988 ( .A(Sgf_operation_n3), .Y(n5158) );
BUFX3TS U2989 ( .A(n884), .Y(n5069) );
AO22XLTS U2990 ( .A0(Sgf_normalized_result[0]), .A1(n5064), .B0(
final_result_ieee[0]), .B1(n5063), .Y(n350) );
AO22XLTS U2991 ( .A0(Sgf_normalized_result[45]), .A1(n5068), .B0(
final_result_ieee[45]), .B1(n5063), .Y(n305) );
AO22XLTS U2992 ( .A0(Sgf_normalized_result[47]), .A1(n5068), .B0(
final_result_ieee[47]), .B1(n5063), .Y(n303) );
AO22XLTS U2993 ( .A0(Sgf_normalized_result[44]), .A1(n5068), .B0(
final_result_ieee[44]), .B1(n5063), .Y(n306) );
AO22XLTS U2994 ( .A0(Sgf_normalized_result[46]), .A1(n5068), .B0(
final_result_ieee[46]), .B1(n5063), .Y(n304) );
AO22XLTS U2995 ( .A0(Sgf_normalized_result[41]), .A1(n5068), .B0(
final_result_ieee[41]), .B1(n5063), .Y(n309) );
AO22XLTS U2996 ( .A0(Sgf_normalized_result[51]), .A1(n5068), .B0(
final_result_ieee[51]), .B1(n5063), .Y(n299) );
AO22XLTS U2997 ( .A0(Sgf_normalized_result[48]), .A1(n5068), .B0(
final_result_ieee[48]), .B1(n5063), .Y(n302) );
AO22XLTS U2998 ( .A0(Sgf_normalized_result[42]), .A1(n5068), .B0(
final_result_ieee[42]), .B1(n5063), .Y(n308) );
AO22XLTS U2999 ( .A0(Sgf_normalized_result[49]), .A1(n5068), .B0(
final_result_ieee[49]), .B1(n5063), .Y(n301) );
AO22XLTS U3000 ( .A0(Sgf_normalized_result[50]), .A1(n5068), .B0(
final_result_ieee[50]), .B1(n5063), .Y(n300) );
AO22XLTS U3001 ( .A0(Sgf_normalized_result[43]), .A1(n5068), .B0(
final_result_ieee[43]), .B1(n5063), .Y(n307) );
BUFX6TS U3002 ( .A(Op_MY[28]), .Y(n3893) );
INVX2TS U3003 ( .A(n888), .Y(n2147) );
NAND2X1TS U3004 ( .A(n3262), .B(n3893), .Y(n2150) );
INVX2TS U3005 ( .A(n2150), .Y(n889) );
BUFX6TS U3006 ( .A(Op_MY[49]), .Y(n4069) );
BUFX6TS U3007 ( .A(Op_MY[48]), .Y(n4072) );
BUFX6TS U3008 ( .A(Op_MY[44]), .Y(n3184) );
BUFX6TS U3009 ( .A(Op_MY[45]), .Y(n2946) );
BUFX6TS U3010 ( .A(Op_MY[46]), .Y(n2942) );
BUFX6TS U3011 ( .A(Op_MY[47]), .Y(n3233) );
NOR2X2TS U3012 ( .A(n978), .B(n927), .Y(n960) );
BUFX4TS U3013 ( .A(Op_MY[51]), .Y(n4053) );
NOR2X2TS U3014 ( .A(n4053), .B(n699), .Y(n943) );
BUFX6TS U3015 ( .A(Op_MY[29]), .Y(n2981) );
BUFX6TS U3016 ( .A(Op_MY[30]), .Y(n3857) );
BUFX6TS U3017 ( .A(Op_MY[31]), .Y(n3229) );
BUFX6TS U3018 ( .A(Op_MY[32]), .Y(n3888) );
BUFX6TS U3019 ( .A(Op_MY[33]), .Y(n2968) );
BUFX6TS U3020 ( .A(Op_MY[34]), .Y(n3883) );
BUFX6TS U3021 ( .A(Op_MY[35]), .Y(n2962) );
BUFX6TS U3022 ( .A(Op_MY[36]), .Y(n3787) );
BUFX6TS U3023 ( .A(Op_MY[37]), .Y(n3222) );
BUFX6TS U3024 ( .A(Op_MY[38]), .Y(n3848) );
BUFX6TS U3025 ( .A(Op_MY[39]), .Y(n2956) );
BUFX6TS U3026 ( .A(Op_MY[40]), .Y(n2950) );
BUFX6TS U3027 ( .A(Op_MY[41]), .Y(n2954) );
BUFX6TS U3028 ( .A(Op_MY[42]), .Y(n3201) );
NAND2X1TS U3029 ( .A(n931), .B(n998), .Y(n933) );
INVX2TS U3030 ( .A(n1725), .Y(n2974) );
NAND2X1TS U3031 ( .A(n2981), .B(n3857), .Y(n2977) );
INVX2TS U3032 ( .A(n2977), .Y(n902) );
NOR2X1TS U3033 ( .A(n2974), .B(n902), .Y(n1210) );
NAND2X1TS U3034 ( .A(n3857), .B(n3229), .Y(n1278) );
INVX2TS U3035 ( .A(n1278), .Y(n1212) );
NAND2X1TS U3036 ( .A(n3229), .B(n3888), .Y(n1213) );
INVX2TS U3037 ( .A(n1213), .Y(n903) );
INVX2TS U3038 ( .A(n1248), .Y(n1643) );
NAND2X1TS U3039 ( .A(n2968), .B(n3883), .Y(n1646) );
INVX2TS U3040 ( .A(n1646), .Y(n906) );
NOR2X1TS U3041 ( .A(n1643), .B(n906), .Y(n1200) );
NAND2X1TS U3042 ( .A(n3883), .B(n2962), .Y(n1205) );
INVX2TS U3043 ( .A(n1205), .Y(n1477) );
NAND2X1TS U3044 ( .A(n2962), .B(n3787), .Y(n1480) );
INVX2TS U3045 ( .A(n1480), .Y(n907) );
OAI21X1TS U3046 ( .A0(n1200), .A1(n909), .B0(n908), .Y(n910) );
NAND2X1TS U3047 ( .A(n3787), .B(n3222), .Y(n1160) );
INVX2TS U3048 ( .A(n1160), .Y(n1228) );
NAND2X1TS U3049 ( .A(n3222), .B(n3848), .Y(n1231) );
INVX2TS U3050 ( .A(n1231), .Y(n912) );
NOR2X1TS U3051 ( .A(n1228), .B(n912), .Y(n1118) );
NAND2X1TS U3052 ( .A(n3848), .B(n2956), .Y(n1124) );
INVX2TS U3053 ( .A(n1124), .Y(n1134) );
NAND2X1TS U3054 ( .A(n2956), .B(n2950), .Y(n1137) );
INVX2TS U3055 ( .A(n1137), .Y(n913) );
OAI21X2TS U3056 ( .A0(n1118), .A1(n915), .B0(n914), .Y(n1057) );
NAND2X1TS U3057 ( .A(n2950), .B(n2954), .Y(n1061) );
INVX2TS U3058 ( .A(n1061), .Y(n1095) );
NAND2X1TS U3059 ( .A(n2954), .B(n3201), .Y(n1098) );
INVX2TS U3060 ( .A(n1098), .Y(n916) );
NOR2X1TS U3061 ( .A(n1095), .B(n916), .Y(n1043) );
NAND2X1TS U3062 ( .A(n3201), .B(n3199), .Y(n1075) );
INVX2TS U3063 ( .A(n1075), .Y(n1050) );
NAND2X1TS U3064 ( .A(n3199), .B(n3184), .Y(n1051) );
INVX2TS U3065 ( .A(n1051), .Y(n917) );
AOI21X1TS U3066 ( .A0(n1057), .A1(n921), .B0(n920), .Y(n922) );
INVX2TS U3067 ( .A(n1018), .Y(n1002) );
NAND2X1TS U3068 ( .A(n2946), .B(n2942), .Y(n1003) );
INVX2TS U3069 ( .A(n1003), .Y(n924) );
NOR2X1TS U3070 ( .A(n1002), .B(n924), .Y(n979) );
NAND2X1TS U3071 ( .A(n2942), .B(n3233), .Y(n984) );
INVX2TS U3072 ( .A(n984), .Y(n989) );
NAND2X1TS U3073 ( .A(n3233), .B(n4072), .Y(n992) );
INVX2TS U3074 ( .A(n992), .Y(n925) );
OAI21X1TS U3075 ( .A0(n979), .A1(n927), .B0(n926), .Y(n959) );
NAND2X1TS U3076 ( .A(n699), .B(n4069), .Y(n966) );
NAND2X1TS U3077 ( .A(n4072), .B(n4069), .Y(n1025) );
NAND2X1TS U3078 ( .A(n966), .B(n1025), .Y(n928) );
AOI21X1TS U3079 ( .A0(n959), .A1(n929), .B0(n928), .Y(n938) );
AOI21X1TS U3080 ( .A0(n999), .A1(n931), .B0(n930), .Y(n932) );
BUFX4TS U3081 ( .A(n1070), .Y(n3487) );
AOI21X1TS U3082 ( .A0(n2785), .A1(n4053), .B0(n2767), .Y(n935) );
XOR2X1TS U3083 ( .A(n936), .B(n2769), .Y(Sgf_operation_mult_x_1_n3524) );
INVX2TS U3084 ( .A(n937), .Y(n940) );
INVX2TS U3085 ( .A(n938), .Y(n939) );
AOI21X1TS U3086 ( .A0(n999), .A1(n940), .B0(n939), .Y(n941) );
INVX2TS U3087 ( .A(n943), .Y(n950) );
NAND2X1TS U3088 ( .A(n4053), .B(n699), .Y(n949) );
INVX2TS U3089 ( .A(n949), .Y(n944) );
AOI21X1TS U3090 ( .A0(n952), .A1(n950), .B0(n944), .Y(n945) );
BUFX4TS U3091 ( .A(Op_MY[51]), .Y(n4047) );
XNOR2X1TS U3092 ( .A(n945), .B(n4047), .Y(n974) );
BUFX4TS U3093 ( .A(n1163), .Y(n3455) );
AO21XLTS U3094 ( .A0(n4052), .A1(n4047), .B0(n3473), .Y(n946) );
AOI21X1TS U3095 ( .A0(n4054), .A1(n700), .B0(n946), .Y(n947) );
OAI21XLTS U3096 ( .A0(n632), .A1(n4056), .B0(n947), .Y(n948) );
XOR2XLTS U3097 ( .A(n948), .B(n4062), .Y(Sgf_operation_mult_x_1_n3470) );
NAND2X1TS U3098 ( .A(n950), .B(n949), .Y(n951) );
OAI21XLTS U3099 ( .A0(n4046), .A1(n4056), .B0(n954), .Y(n955) );
XOR2X1TS U3100 ( .A(n955), .B(n4062), .Y(Sgf_operation_mult_x_1_n3471) );
XOR2X1TS U3101 ( .A(n958), .B(n2769), .Y(Sgf_operation_mult_x_1_n3523) );
NAND2X1TS U3102 ( .A(n998), .B(n960), .Y(n962) );
AOI21X1TS U3103 ( .A0(n999), .A1(n960), .B0(n959), .Y(n961) );
INVX2TS U3104 ( .A(n963), .Y(n1026) );
INVX2TS U3105 ( .A(n1025), .Y(n964) );
AOI21X1TS U3106 ( .A0(n1028), .A1(n1026), .B0(n964), .Y(n969) );
INVX2TS U3107 ( .A(n965), .Y(n967) );
NAND2X1TS U3108 ( .A(n967), .B(n966), .Y(n968) );
XNOR2X1TS U3109 ( .A(n969), .B(n968), .Y(n1009) );
BUFX4TS U3110 ( .A(Op_MY[49]), .Y(n2752) );
AOI222X1TS U3111 ( .A0(n3473), .A1(n2728), .B0(n4052), .B1(n2752), .C0(n4054), .C1(n4072), .Y(n970) );
OAI21XLTS U3112 ( .A0(n627), .A1(n4056), .B0(n970), .Y(n971) );
XOR2X1TS U3113 ( .A(n971), .B(n4062), .Y(Sgf_operation_mult_x_1_n3472) );
XOR2X1TS U3114 ( .A(n973), .B(n2769), .Y(Sgf_operation_mult_x_1_n3526) );
AO21XLTS U3115 ( .A0(n2767), .A1(n4047), .B0(n1235), .Y(n975) );
AOI21X1TS U3116 ( .A0(n2785), .A1(n700), .B0(n975), .Y(n976) );
XOR2X1TS U3117 ( .A(n977), .B(n2769), .Y(Sgf_operation_mult_x_1_n3525) );
INVX2TS U3118 ( .A(n978), .Y(n981) );
INVX2TS U3119 ( .A(n979), .Y(n980) );
AOI21X1TS U3120 ( .A0(n999), .A1(n981), .B0(n980), .Y(n982) );
NAND2X1TS U3121 ( .A(n990), .B(n984), .Y(n985) );
BUFX4TS U3122 ( .A(Op_MY[46]), .Y(n2653) );
AOI222X1TS U3123 ( .A0(n3465), .A1(n2654), .B0(n4052), .B1(n2653), .C0(n4054), .C1(n2946), .Y(n987) );
XOR2X1TS U3124 ( .A(n988), .B(n4062), .Y(Sgf_operation_mult_x_1_n3475) );
AOI21X1TS U3125 ( .A0(n991), .A1(n990), .B0(n989), .Y(n995) );
NAND2X1TS U3126 ( .A(n993), .B(n992), .Y(n994) );
XNOR2X1TS U3127 ( .A(n995), .B(n994), .Y(n1068) );
BUFX4TS U3128 ( .A(Op_MY[47]), .Y(n2712) );
AOI222X1TS U3129 ( .A0(n3465), .A1(n2713), .B0(n4052), .B1(n2712), .C0(n4054), .C1(n2942), .Y(n996) );
XOR2X1TS U3130 ( .A(n997), .B(n4062), .Y(Sgf_operation_mult_x_1_n3474) );
INVX2TS U3131 ( .A(n998), .Y(n1001) );
INVX2TS U3132 ( .A(n999), .Y(n1000) );
AOI21X1TS U3133 ( .A0(n1021), .A1(n1019), .B0(n1002), .Y(n1006) );
NAND2X1TS U3134 ( .A(n1004), .B(n1003), .Y(n1005) );
XNOR2X1TS U3135 ( .A(n1006), .B(n1005), .Y(n1039) );
BUFX4TS U3136 ( .A(Op_MY[45]), .Y(n2462) );
AOI222X1TS U3137 ( .A0(n3473), .A1(n2607), .B0(n4052), .B1(n2462), .C0(n4054), .C1(n3184), .Y(n1007) );
XOR2X1TS U3138 ( .A(n1008), .B(n4062), .Y(Sgf_operation_mult_x_1_n3476) );
AOI222X1TS U3139 ( .A0(n1235), .A1(n700), .B0(n2767), .B1(n2752), .C0(n2785),
.C1(n4072), .Y(n1010) );
XOR2X1TS U3140 ( .A(n1011), .B(n2769), .Y(Sgf_operation_mult_x_1_n3527) );
XNOR2X2TS U3141 ( .A(n2344), .B(Op_MX[42]), .Y(n1013) );
CLKXOR2X2TS U3142 ( .A(n3344), .B(Op_MX[43]), .Y(n1014) );
NAND2BX2TS U3143 ( .AN(n1013), .B(n1014), .Y(n3192) );
NAND3X2TS U3144 ( .A(n1014), .B(n1013), .C(n1012), .Y(n3194) );
NOR2BX2TS U3145 ( .AN(n1013), .B(n1012), .Y(n1357) );
BUFX4TS U3146 ( .A(n1357), .Y(n3273) );
NOR2X2TS U3147 ( .A(n1014), .B(n1013), .Y(n1295) );
BUFX4TS U3148 ( .A(n1295), .Y(n3508) );
AO21XLTS U3149 ( .A0(n3273), .A1(n4047), .B0(n3508), .Y(n1015) );
AOI21X1TS U3150 ( .A0(n3518), .A1(Op_MY[50]), .B0(n1015), .Y(n1016) );
XOR2X1TS U3151 ( .A(n1017), .B(n3344), .Y(Sgf_operation_mult_x_1_n3580) );
NAND2X1TS U3152 ( .A(n1019), .B(n1018), .Y(n1020) );
BUFX4TS U3153 ( .A(Op_MY[44]), .Y(n3906) );
AOI222X1TS U3154 ( .A0(n3473), .A1(n3907), .B0(n4052), .B1(n3906), .C0(n4054), .C1(n3199), .Y(n1023) );
XOR2X1TS U3155 ( .A(n1024), .B(n4062), .Y(Sgf_operation_mult_x_1_n3477) );
NAND2X1TS U3156 ( .A(n1026), .B(n1025), .Y(n1027) );
BUFX4TS U3157 ( .A(Op_MY[48]), .Y(n3234) );
AOI222X1TS U3158 ( .A0(n1235), .A1(n3235), .B0(n2767), .B1(n3234), .C0(n2785), .C1(n3233), .Y(n1030) );
XOR2X1TS U3159 ( .A(n1031), .B(n2769), .Y(Sgf_operation_mult_x_1_n3528) );
NAND3X2TS U3160 ( .A(n1034), .B(n1033), .C(n1032), .Y(n1436) );
AOI21X1TS U3161 ( .A0(n2342), .A1(n4053), .B0(n3542), .Y(n1035) );
XOR2X1TS U3162 ( .A(n1036), .B(n2344), .Y(Sgf_operation_mult_x_1_n3635) );
XOR2X1TS U3163 ( .A(n1038), .B(n3344), .Y(Sgf_operation_mult_x_1_n3581) );
AOI222X1TS U3164 ( .A0(n1235), .A1(n2607), .B0(n2767), .B1(n2462), .C0(n2785), .C1(n3184), .Y(n1040) );
XOR2X1TS U3165 ( .A(n1041), .B(n2769), .Y(Sgf_operation_mult_x_1_n3531) );
INVX2TS U3166 ( .A(n1058), .Y(n1042) );
INVX2TS U3167 ( .A(n1159), .Y(n1117) );
INVX2TS U3168 ( .A(n1158), .Y(n1121) );
INVX2TS U3169 ( .A(n1057), .Y(n1045) );
AOI21X1TS U3170 ( .A0(n1121), .A1(n1047), .B0(n1046), .Y(n1048) );
AOI21X1TS U3171 ( .A0(n1078), .A1(n1076), .B0(n1050), .Y(n1054) );
NAND2X1TS U3172 ( .A(n1052), .B(n1051), .Y(n1053) );
XNOR2X1TS U3173 ( .A(n1054), .B(n1053), .Y(n1113) );
BUFX4TS U3174 ( .A(Op_MY[43]), .Y(n2507) );
AOI222X1TS U3175 ( .A0(n3465), .A1(n2508), .B0(n4052), .B1(n2507), .C0(n4054), .C1(n3201), .Y(n1055) );
XOR2X1TS U3176 ( .A(n1056), .B(n4062), .Y(Sgf_operation_mult_x_1_n3478) );
NAND2X1TS U3177 ( .A(n1117), .B(n1058), .Y(n1060) );
AOI21X1TS U3178 ( .A0(n1121), .A1(n1058), .B0(n1057), .Y(n1059) );
NAND2X1TS U3179 ( .A(n1096), .B(n1061), .Y(n1062) );
XNOR2X1TS U3180 ( .A(n1097), .B(n1062), .Y(n1063) );
INVX4TS U3181 ( .A(n4041), .Y(n4073) );
BUFX3TS U3182 ( .A(n4070), .Y(n3227) );
CLKAND2X2TS U3183 ( .A(n3227), .B(n2950), .Y(n1064) );
AOI21X1TS U3184 ( .A0(n4073), .A1(n2956), .B0(n1064), .Y(n1065) );
OAI21X1TS U3185 ( .A0(n3925), .A1(n4075), .B0(n1065), .Y(
Sgf_operation_mult_x_1_n1383) );
AOI222X1TS U3186 ( .A0(n3508), .A1(n2728), .B0(n3273), .B1(n2752), .C0(n3518), .C1(n4072), .Y(n1066) );
XOR2X1TS U3187 ( .A(n1067), .B(n3344), .Y(Sgf_operation_mult_x_1_n3582) );
AOI222X1TS U3188 ( .A0(n1235), .A1(n2713), .B0(n2767), .B1(n2712), .C0(n2785), .C1(n2942), .Y(n1069) );
XOR2X1TS U3189 ( .A(n1071), .B(n2769), .Y(Sgf_operation_mult_x_1_n3529) );
AOI222X1TS U3190 ( .A0(n1235), .A1(n2654), .B0(n2767), .B1(n2653), .C0(n2785), .C1(n2946), .Y(n1072) );
XOR2X1TS U3191 ( .A(n1073), .B(n2769), .Y(Sgf_operation_mult_x_1_n3530) );
XOR2X1TS U3192 ( .A(n1074), .B(n2344), .Y(Sgf_operation_mult_x_1_n3634) );
NAND2X1TS U3193 ( .A(n1076), .B(n1075), .Y(n1077) );
BUFX4TS U3194 ( .A(Op_MY[42]), .Y(n3911) );
AOI222X1TS U3195 ( .A0(n3473), .A1(n3912), .B0(n4052), .B1(n3911), .C0(n4054), .C1(n2954), .Y(n1080) );
XOR2X1TS U3196 ( .A(n1081), .B(n4062), .Y(Sgf_operation_mult_x_1_n3479) );
BUFX4TS U3197 ( .A(n1174), .Y(n3544) );
AO21XLTS U3198 ( .A0(n3542), .A1(n4047), .B0(n3554), .Y(n1082) );
AOI21X1TS U3199 ( .A0(n2342), .A1(Op_MY[50]), .B0(n1082), .Y(n1083) );
XOR2X1TS U3200 ( .A(n1084), .B(n2344), .Y(Sgf_operation_mult_x_1_n3636) );
AOI222X1TS U3201 ( .A0(n1235), .A1(n3907), .B0(n2767), .B1(n3906), .C0(n2785), .C1(n3199), .Y(n1085) );
XOR2X1TS U3202 ( .A(n1086), .B(n2769), .Y(Sgf_operation_mult_x_1_n3532) );
AOI222X1TS U3203 ( .A0(n3508), .A1(n2713), .B0(n3273), .B1(n2712), .C0(n3518), .C1(n2942), .Y(n1087) );
XOR2X1TS U3204 ( .A(n1088), .B(n3344), .Y(Sgf_operation_mult_x_1_n3584) );
AOI222X1TS U3205 ( .A0(n1235), .A1(n3912), .B0(n2767), .B1(n3911), .C0(n2785), .C1(n2954), .Y(n1089) );
XOR2X1TS U3206 ( .A(n1090), .B(n2769), .Y(Sgf_operation_mult_x_1_n3534) );
XOR2X1TS U3207 ( .A(n1092), .B(n2344), .Y(Sgf_operation_mult_x_1_n3637) );
BUFX4TS U3208 ( .A(Op_MY[40]), .Y(n3922) );
AOI222X1TS U3209 ( .A0(n3465), .A1(n3923), .B0(n4052), .B1(n3922), .C0(n4054), .C1(n2956), .Y(n1093) );
XOR2X1TS U3210 ( .A(n1094), .B(n4062), .Y(Sgf_operation_mult_x_1_n3481) );
AOI21X1TS U3211 ( .A0(n1097), .A1(n1096), .B0(n1095), .Y(n1101) );
NAND2X1TS U3212 ( .A(n1099), .B(n1098), .Y(n1100) );
XOR2X1TS U3213 ( .A(n1101), .B(n1100), .Y(n1102) );
BUFX4TS U3214 ( .A(Op_MY[41]), .Y(n3917) );
XOR2X1TS U3215 ( .A(n1104), .B(n4062), .Y(Sgf_operation_mult_x_1_n3480) );
BUFX3TS U3216 ( .A(n3192), .Y(n3210) );
AOI222X1TS U3217 ( .A0(n3508), .A1(n2654), .B0(n3273), .B1(n2653), .C0(n3518), .C1(n2946), .Y(n1105) );
XOR2X1TS U3218 ( .A(n1106), .B(n3344), .Y(Sgf_operation_mult_x_1_n3585) );
AOI222X1TS U3219 ( .A0(n3494), .A1(n3918), .B0(n2767), .B1(n3917), .C0(n2785), .C1(n2950), .Y(n1107) );
XOR2X1TS U3220 ( .A(n1108), .B(n2769), .Y(Sgf_operation_mult_x_1_n3535) );
BUFX4TS U3221 ( .A(n3192), .Y(n3514) );
AOI222X1TS U3222 ( .A0(n3508), .A1(n3907), .B0(n3273), .B1(n3906), .C0(n3518), .C1(n3199), .Y(n1109) );
XOR2X1TS U3223 ( .A(n1110), .B(n3344), .Y(Sgf_operation_mult_x_1_n3587) );
BUFX4TS U3224 ( .A(n1435), .Y(n3534) );
AOI222X1TS U3225 ( .A0(n3535), .A1(n3235), .B0(n3534), .B1(n3234), .C0(n2342), .C1(n3233), .Y(n1111) );
XOR2X1TS U3226 ( .A(n1112), .B(n2344), .Y(Sgf_operation_mult_x_1_n3639) );
AOI222X1TS U3227 ( .A0(n1235), .A1(n2508), .B0(n2767), .B1(n2507), .C0(n2785), .C1(n3201), .Y(n1114) );
XOR2X1TS U3228 ( .A(n1115), .B(n2769), .Y(Sgf_operation_mult_x_1_n3533) );
INVX2TS U3229 ( .A(n1116), .Y(n1120) );
NAND2X1TS U3230 ( .A(n1117), .B(n1120), .Y(n1123) );
INVX2TS U3231 ( .A(n1118), .Y(n1119) );
AOI21X1TS U3232 ( .A0(n1121), .A1(n1120), .B0(n1119), .Y(n1122) );
NAND2X1TS U3233 ( .A(n1135), .B(n1124), .Y(n1125) );
XNOR2X1TS U3234 ( .A(n1136), .B(n1125), .Y(n1126) );
BUFX4TS U3235 ( .A(n4056), .Y(n3475) );
BUFX4TS U3236 ( .A(Op_MY[38]), .Y(n2539) );
INVX4TS U3237 ( .A(n4059), .Y(n3468) );
AOI222X1TS U3238 ( .A0(n3473), .A1(n3921), .B0(n4052), .B1(n2539), .C0(n3468), .C1(n3222), .Y(n1127) );
XOR2X1TS U3239 ( .A(n1129), .B(n3476), .Y(Sgf_operation_mult_x_1_n3483) );
AOI222X1TS U3240 ( .A0(n3508), .A1(n2607), .B0(n3273), .B1(n2462), .C0(n3518), .C1(n3184), .Y(n1130) );
XOR2X1TS U3241 ( .A(n1131), .B(n3344), .Y(Sgf_operation_mult_x_1_n3586) );
AOI222X1TS U3242 ( .A0(n3554), .A1(n700), .B0(n3534), .B1(n2752), .C0(n2342),
.C1(n4072), .Y(n1132) );
XOR2X1TS U3243 ( .A(n1133), .B(n2344), .Y(Sgf_operation_mult_x_1_n3638) );
AOI21X1TS U3244 ( .A0(n1136), .A1(n1135), .B0(n1134), .Y(n1140) );
NAND2X1TS U3245 ( .A(n1138), .B(n1137), .Y(n1139) );
XNOR2X1TS U3246 ( .A(n1140), .B(n1139), .Y(n2218) );
BUFX4TS U3247 ( .A(n1164), .Y(n3279) );
BUFX4TS U3248 ( .A(Op_MY[39]), .Y(n3849) );
XOR2X1TS U3249 ( .A(n1142), .B(n3476), .Y(Sgf_operation_mult_x_1_n3482) );
XNOR2X2TS U3250 ( .A(n2666), .B(Op_MX[36]), .Y(n1144) );
CLKXOR2X2TS U3251 ( .A(n3364), .B(Op_MX[37]), .Y(n1145) );
NAND2BX2TS U3252 ( .AN(n1144), .B(n1145), .Y(n3215) );
NOR2X2TS U3253 ( .A(n1145), .B(n1144), .Y(n1425) );
BUFX4TS U3254 ( .A(n1425), .Y(n3561) );
NOR2BX2TS U3255 ( .AN(n1144), .B(n1143), .Y(n1399) );
BUFX4TS U3256 ( .A(n1399), .Y(n3589) );
NAND3X2TS U3257 ( .A(n1145), .B(n1144), .C(n1143), .Y(n3217) );
INVX4TS U3258 ( .A(n3217), .Y(n3574) );
AOI222X1TS U3259 ( .A0(n3561), .A1(n2729), .B0(n3589), .B1(n2728), .C0(n3588), .C1(n4069), .Y(n1146) );
XOR2X1TS U3260 ( .A(n1147), .B(n3364), .Y(Sgf_operation_mult_x_1_n3692) );
AO21XLTS U3261 ( .A0(n3589), .A1(n4047), .B0(n3590), .Y(n1148) );
AOI21X1TS U3262 ( .A0(n3588), .A1(Op_MY[50]), .B0(n1148), .Y(n1149) );
XOR2X1TS U3263 ( .A(n1150), .B(n3364), .Y(Sgf_operation_mult_x_1_n3691) );
BUFX4TS U3264 ( .A(n1611), .Y(n2665) );
NAND3X2TS U3265 ( .A(n1153), .B(n1152), .C(n1151), .Y(n1609) );
AOI21X1TS U3266 ( .A0(n2663), .A1(n4053), .B0(n3598), .Y(n1154) );
XOR2X1TS U3267 ( .A(n1155), .B(n2666), .Y(Sgf_operation_mult_x_1_n3746) );
AOI222X1TS U3268 ( .A0(n1235), .A1(n3923), .B0(n2767), .B1(n3922), .C0(n2785), .C1(n2956), .Y(n1156) );
XOR2X1TS U3269 ( .A(n1157), .B(n2769), .Y(Sgf_operation_mult_x_1_n3536) );
NAND2X1TS U3270 ( .A(n1229), .B(n1160), .Y(n1161) );
XNOR2X1TS U3271 ( .A(n1230), .B(n1161), .Y(n1162) );
BUFX4TS U3272 ( .A(n1163), .Y(n3473) );
BUFX4TS U3273 ( .A(n1164), .Y(n3472) );
BUFX4TS U3274 ( .A(Op_MY[36]), .Y(n2473) );
AOI222X1TS U3275 ( .A0(n3465), .A1(n2474), .B0(n3472), .B1(n2473), .C0(n3468), .C1(n2962), .Y(n1165) );
XOR2X1TS U3276 ( .A(n1166), .B(n3476), .Y(Sgf_operation_mult_x_1_n3485) );
XOR2X1TS U3277 ( .A(n1167), .B(n2666), .Y(Sgf_operation_mult_x_1_n3745) );
AOI222X1TS U3278 ( .A0(n3508), .A1(n3912), .B0(n3273), .B1(n3911), .C0(n3518), .C1(n2954), .Y(n1168) );
XOR2X1TS U3279 ( .A(n1169), .B(n3344), .Y(Sgf_operation_mult_x_1_n3589) );
AOI222X1TS U3280 ( .A0(n3508), .A1(n2508), .B0(n3273), .B1(n2507), .C0(n3518), .C1(n3201), .Y(n1170) );
XOR2X1TS U3281 ( .A(n1171), .B(n3344), .Y(Sgf_operation_mult_x_1_n3588) );
AOI222X1TS U3282 ( .A0(n3554), .A1(n2713), .B0(n3534), .B1(n2712), .C0(n2342), .C1(n2942), .Y(n1172) );
XOR2X1TS U3283 ( .A(n1173), .B(n2344), .Y(Sgf_operation_mult_x_1_n3640) );
BUFX4TS U3284 ( .A(n1174), .Y(n3556) );
AOI222X1TS U3285 ( .A0(n3554), .A1(n2654), .B0(n3534), .B1(n2653), .C0(n2342), .C1(n2946), .Y(n1175) );
XOR2X1TS U3286 ( .A(n1176), .B(n2344), .Y(Sgf_operation_mult_x_1_n3641) );
AOI222X1TS U3287 ( .A0(n1235), .A1(n3921), .B0(n2767), .B1(n2539), .C0(n3493), .C1(n3222), .Y(n1177) );
XOR2X1TS U3288 ( .A(n1178), .B(n3491), .Y(Sgf_operation_mult_x_1_n3538) );
AOI222X1TS U3289 ( .A0(n3535), .A1(n2607), .B0(n3534), .B1(n2462), .C0(n2342), .C1(n3184), .Y(n1179) );
XOR2X1TS U3290 ( .A(n1180), .B(n2344), .Y(Sgf_operation_mult_x_1_n3642) );
AOI222X1TS U3291 ( .A0(n3535), .A1(n3907), .B0(n3534), .B1(n3906), .C0(n2342), .C1(n3199), .Y(n1181) );
XOR2X1TS U3292 ( .A(n1182), .B(n2344), .Y(Sgf_operation_mult_x_1_n3643) );
BUFX4TS U3293 ( .A(n1399), .Y(n3578) );
XOR2X1TS U3294 ( .A(n1184), .B(n3364), .Y(Sgf_operation_mult_x_1_n3693) );
XOR2X1TS U3295 ( .A(n1186), .B(n2666), .Y(Sgf_operation_mult_x_1_n3748) );
AOI21X1TS U3296 ( .A0(n2663), .A1(Op_MY[50]), .B0(n1187), .Y(n1188) );
XOR2X1TS U3297 ( .A(n1189), .B(n2666), .Y(Sgf_operation_mult_x_1_n3747) );
AOI222X1TS U3298 ( .A0(n3508), .A1(n3923), .B0(n3273), .B1(n3922), .C0(n3518), .C1(n2956), .Y(n1190) );
XOR2X1TS U3299 ( .A(n1191), .B(n3344), .Y(Sgf_operation_mult_x_1_n3591) );
AOI222X1TS U3300 ( .A0(n3523), .A1(n3918), .B0(n3273), .B1(n3917), .C0(n3518), .C1(n2950), .Y(n1192) );
XOR2X1TS U3301 ( .A(n1193), .B(n3344), .Y(Sgf_operation_mult_x_1_n3590) );
AOI222X1TS U3302 ( .A0(n3535), .A1(n3912), .B0(n3534), .B1(n3911), .C0(n2342), .C1(n2954), .Y(n1194) );
XOR2X1TS U3303 ( .A(n1195), .B(n2344), .Y(Sgf_operation_mult_x_1_n3645) );
XNOR2X2TS U3304 ( .A(n2758), .B(Op_MX[30]), .Y(n1261) );
CLKXOR2X2TS U3305 ( .A(n3384), .B(Op_MX[31]), .Y(n1262) );
NAND2BX2TS U3306 ( .AN(n1261), .B(n1262), .Y(n1484) );
NAND3X2TS U3307 ( .A(n1262), .B(n1261), .C(n1196), .Y(n3241) );
NOR2BX2TS U3308 ( .AN(n1261), .B(n1196), .Y(n1337) );
BUFX4TS U3309 ( .A(n1337), .Y(n3637) );
AOI21X1TS U3310 ( .A0(n2777), .A1(n4053), .B0(n3637), .Y(n1197) );
XOR2X1TS U3311 ( .A(n1198), .B(n3384), .Y(n3244) );
INVX2TS U3312 ( .A(n3244), .Y(n1221) );
INVX2TS U3313 ( .A(n1199), .Y(n1202) );
NAND2X1TS U3314 ( .A(n1244), .B(n1202), .Y(n1204) );
INVX2TS U3315 ( .A(n1200), .Y(n1201) );
AOI21X1TS U3316 ( .A0(n1245), .A1(n1202), .B0(n1201), .Y(n1203) );
NAND2X1TS U3317 ( .A(n1478), .B(n1205), .Y(n1206) );
XNOR2X1TS U3318 ( .A(n1479), .B(n1206), .Y(n1207) );
BUFX4TS U3319 ( .A(Op_MY[34]), .Y(n2583) );
XOR2X1TS U3320 ( .A(n1209), .B(n3476), .Y(n1220) );
AOI21X1TS U3321 ( .A0(n1281), .A1(n1279), .B0(n1212), .Y(n1216) );
NAND2X1TS U3322 ( .A(n1214), .B(n1213), .Y(n1215) );
XNOR2X1TS U3323 ( .A(n1216), .B(n1215), .Y(n1980) );
AOI21X1TS U3324 ( .A0(n3230), .A1(n3857), .B0(n1217), .Y(n1218) );
OAI21X1TS U3325 ( .A0(n629), .A1(n4075), .B0(n1218), .Y(n1219) );
CMPR32X2TS U3326 ( .A(n1221), .B(n1220), .C(n1219), .CO(
Sgf_operation_mult_x_1_n1483), .S(Sgf_operation_mult_x_1_n1484) );
BUFX4TS U3327 ( .A(n3215), .Y(n3576) );
AOI222X1TS U3328 ( .A0(n3584), .A1(n2654), .B0(n3578), .B1(n2653), .C0(n3588), .C1(n2946), .Y(n1222) );
XOR2X1TS U3329 ( .A(n1223), .B(n3364), .Y(Sgf_operation_mult_x_1_n3696) );
AOI222X1TS U3330 ( .A0(n3501), .A1(n2474), .B0(n3489), .B1(n2473), .C0(n3493), .C1(n2962), .Y(n1224) );
XOR2X1TS U3331 ( .A(n1225), .B(n3491), .Y(Sgf_operation_mult_x_1_n3540) );
AOI222X1TS U3332 ( .A0(n3554), .A1(n2508), .B0(n3534), .B1(n2507), .C0(n2342), .C1(n3201), .Y(n1226) );
XOR2X1TS U3333 ( .A(n1227), .B(n2344), .Y(Sgf_operation_mult_x_1_n3644) );
AOI21X1TS U3334 ( .A0(n1230), .A1(n1229), .B0(n1228), .Y(n1234) );
NAND2X1TS U3335 ( .A(n1232), .B(n1231), .Y(n1233) );
XNOR2X1TS U3336 ( .A(n1234), .B(n1233), .Y(n2306) );
BUFX4TS U3337 ( .A(Op_MY[37]), .Y(n3818) );
AOI222X1TS U3338 ( .A0(n1235), .A1(n3819), .B0(n3489), .B1(n3818), .C0(n3493), .C1(n3787), .Y(n1236) );
XOR2X1TS U3339 ( .A(n1237), .B(n3491), .Y(Sgf_operation_mult_x_1_n3539) );
AOI222X1TS U3340 ( .A0(n3590), .A1(n2713), .B0(n3578), .B1(n2712), .C0(n3582), .C1(n2942), .Y(n1238) );
XOR2X1TS U3341 ( .A(n1239), .B(n3364), .Y(Sgf_operation_mult_x_1_n3695) );
INVX4TS U3342 ( .A(n3194), .Y(n3521) );
AOI222X1TS U3343 ( .A0(n3508), .A1(n3921), .B0(n3273), .B1(n2539), .C0(n3521), .C1(n3222), .Y(n1240) );
XOR2X1TS U3344 ( .A(n1241), .B(n3532), .Y(Sgf_operation_mult_x_1_n3593) );
AOI222X1TS U3345 ( .A0(n3561), .A1(n3907), .B0(n3578), .B1(n3906), .C0(n3588), .C1(n3199), .Y(n1242) );
XOR2X1TS U3346 ( .A(n1243), .B(n3364), .Y(Sgf_operation_mult_x_1_n3698) );
INVX2TS U3347 ( .A(n1244), .Y(n1247) );
INVX2TS U3348 ( .A(n1245), .Y(n1246) );
NAND2X1TS U3349 ( .A(n1644), .B(n1248), .Y(n1249) );
XNOR2X1TS U3350 ( .A(n1645), .B(n1249), .Y(n1250) );
BUFX4TS U3351 ( .A(Op_MY[32]), .Y(n2644) );
XOR2X1TS U3352 ( .A(n1252), .B(n3476), .Y(Sgf_operation_mult_x_1_n3489) );
BUFX4TS U3353 ( .A(n1434), .Y(n3535) );
XOR2X1TS U3354 ( .A(n1254), .B(n2344), .Y(Sgf_operation_mult_x_1_n3646) );
AOI222X1TS U3355 ( .A0(n3590), .A1(n2607), .B0(n3578), .B1(n2462), .C0(n3582), .C1(n3184), .Y(n1255) );
XOR2X1TS U3356 ( .A(n1256), .B(n3364), .Y(Sgf_operation_mult_x_1_n3697) );
BUFX4TS U3357 ( .A(n1713), .Y(n3605) );
XOR2X1TS U3358 ( .A(n1258), .B(n2666), .Y(Sgf_operation_mult_x_1_n3749) );
AOI222X1TS U3359 ( .A0(n3610), .A1(n2713), .B0(n3605), .B1(n2712), .C0(n2663), .C1(n2942), .Y(n1259) );
XOR2X1TS U3360 ( .A(n1260), .B(n2666), .Y(Sgf_operation_mult_x_1_n3751) );
NOR2X2TS U3361 ( .A(n1262), .B(n1261), .Y(n1635) );
BUFX4TS U3362 ( .A(n1635), .Y(n3622) );
AOI21X1TS U3363 ( .A0(n2777), .A1(Op_MY[50]), .B0(n1263), .Y(n1264) );
XOR2X1TS U3364 ( .A(n1265), .B(n3384), .Y(Sgf_operation_mult_x_1_n3802) );
AOI222X1TS U3365 ( .A0(n3610), .A1(n3235), .B0(n3605), .B1(n3234), .C0(n2663), .C1(n3233), .Y(n1266) );
XOR2X1TS U3366 ( .A(n1267), .B(n2666), .Y(Sgf_operation_mult_x_1_n3750) );
XOR2X1TS U3367 ( .A(n1269), .B(n3384), .Y(Sgf_operation_mult_x_1_n3803) );
AOI222X1TS U3368 ( .A0(n3535), .A1(n3923), .B0(n3534), .B1(n3922), .C0(n2342), .C1(n2956), .Y(n1270) );
XOR2X1TS U3369 ( .A(n1271), .B(n2344), .Y(Sgf_operation_mult_x_1_n3647) );
NAND3X2TS U3370 ( .A(n1274), .B(n1273), .C(n1272), .Y(n1736) );
XOR2X1TS U3371 ( .A(n1275), .B(n2758), .Y(Sgf_operation_mult_x_1_n3856) );
AOI222X1TS U3372 ( .A0(n3584), .A1(n2508), .B0(n3578), .B1(n2507), .C0(n3582), .C1(n3201), .Y(n1276) );
XOR2X1TS U3373 ( .A(n1277), .B(n3364), .Y(Sgf_operation_mult_x_1_n3699) );
NAND2X1TS U3374 ( .A(n1279), .B(n1278), .Y(n1280) );
XNOR2X1TS U3375 ( .A(n1281), .B(n1280), .Y(n1282) );
BUFX4TS U3376 ( .A(Op_MY[30]), .Y(n2429) );
XOR2X1TS U3377 ( .A(n1284), .B(n3476), .Y(Sgf_operation_mult_x_1_n3491) );
INVX4TS U3378 ( .A(n1736), .Y(n2755) );
AOI21X1TS U3379 ( .A0(n3649), .A1(n4053), .B0(n3650), .Y(n1285) );
XOR2X1TS U3380 ( .A(n1286), .B(n2758), .Y(Sgf_operation_mult_x_1_n3857) );
AOI222X1TS U3381 ( .A0(n3501), .A1(n2584), .B0(n3489), .B1(n2583), .C0(n3493), .C1(n2968), .Y(n1287) );
XOR2X1TS U3382 ( .A(n1288), .B(n3491), .Y(Sgf_operation_mult_x_1_n3542) );
NAND2X1TS U3383 ( .A(n2986), .B(n2987), .Y(n1302) );
AOI21X1TS U3384 ( .A0(n1302), .A1(n1300), .B0(n1289), .Y(n1293) );
NAND2X1TS U3385 ( .A(n1291), .B(n1290), .Y(n1292) );
XOR2X1TS U3386 ( .A(n1293), .B(n1292), .Y(n1294) );
BUFX4TS U3387 ( .A(n3192), .Y(n3531) );
BUFX4TS U3388 ( .A(n1295), .Y(n3529) );
BUFX4TS U3389 ( .A(n1357), .Y(n3522) );
BUFX4TS U3390 ( .A(Op_MY[3]), .Y(n4118) );
XOR2X1TS U3391 ( .A(n1298), .B(n3525), .Y(Sgf_operation_mult_x_1_n3628) );
NAND2X1TS U3392 ( .A(n1300), .B(n1299), .Y(n1301) );
XNOR2X1TS U3393 ( .A(n1302), .B(n1301), .Y(n1303) );
BUFX4TS U3394 ( .A(Op_MY[2]), .Y(n4140) );
XOR2X1TS U3395 ( .A(n1305), .B(n3525), .Y(Sgf_operation_mult_x_1_n3629) );
XNOR2X2TS U3396 ( .A(n2799), .B(Op_MX[18]), .Y(n1307) );
CLKXOR2X2TS U3397 ( .A(n3424), .B(Op_MX[19]), .Y(n1308) );
NAND2BX2TS U3398 ( .AN(n1307), .B(n1308), .Y(n2734) );
BUFX4TS U3399 ( .A(n2734), .Y(n3752) );
NOR2X2TS U3400 ( .A(n1308), .B(n1307), .Y(n1674) );
BUFX4TS U3401 ( .A(n1674), .Y(n3750) );
NOR2BX2TS U3402 ( .AN(n1307), .B(n1306), .Y(n1632) );
BUFX4TS U3403 ( .A(n1632), .Y(n3743) );
NAND3X2TS U3404 ( .A(n1308), .B(n1307), .C(n1306), .Y(n2792) );
CLKINVX6TS U3405 ( .A(n2792), .Y(n3748) );
AOI222X1TS U3406 ( .A0(n3732), .A1(n4162), .B0(n3743), .B1(n4118), .C0(n3742), .C1(n4090), .Y(n1309) );
CLKINVX6TS U3407 ( .A(n1596), .Y(n3746) );
XOR2X1TS U3408 ( .A(n1310), .B(n3746), .Y(Sgf_operation_mult_x_1_n4074) );
CLKBUFX2TS U3409 ( .A(n5078), .Y(n1573) );
CLKINVX6TS U3410 ( .A(n1573), .Y(n4145) );
XNOR2X2TS U3411 ( .A(n4145), .B(Op_MX[6]), .Y(n1312) );
CLKXOR2X2TS U3412 ( .A(n4094), .B(Op_MX[7]), .Y(n1313) );
NAND2BX2TS U3413 ( .AN(n1312), .B(n1313), .Y(n3875) );
BUFX4TS U3414 ( .A(n3875), .Y(n3880) );
NOR2X4TS U3415 ( .A(n1313), .B(n1312), .Y(n3850) );
NOR2BX2TS U3416 ( .AN(n1312), .B(n1311), .Y(n1569) );
BUFX4TS U3417 ( .A(n1569), .Y(n4035) );
NAND3X2TS U3418 ( .A(n1313), .B(n1312), .C(n1311), .Y(n2702) );
CLKINVX6TS U3419 ( .A(n2702), .Y(n4034) );
CLKINVX6TS U3420 ( .A(n1408), .Y(n4039) );
XOR2X1TS U3421 ( .A(n1315), .B(n4039), .Y(Sgf_operation_mult_x_1_n4298) );
XOR2X1TS U3422 ( .A(n1317), .B(n4039), .Y(Sgf_operation_mult_x_1_n4299) );
BUFX4TS U3423 ( .A(n1337), .Y(n2778) );
AOI222X1TS U3424 ( .A0(n3622), .A1(n3235), .B0(n2778), .B1(n3234), .C0(n2777), .C1(n3233), .Y(n1318) );
XOR2X1TS U3425 ( .A(n1319), .B(n3384), .Y(Sgf_operation_mult_x_1_n3805) );
XNOR2X2TS U3426 ( .A(n2661), .B(Op_MX[12]), .Y(n1321) );
CLKXOR2X2TS U3427 ( .A(n3444), .B(Op_MX[13]), .Y(n1322) );
NAND2BX2TS U3428 ( .AN(n1321), .B(n1322), .Y(n2649) );
BUFX4TS U3429 ( .A(n2649), .Y(n3813) );
NOR2X2TS U3430 ( .A(n1322), .B(n1321), .Y(n1699) );
BUFX4TS U3431 ( .A(n1699), .Y(n3805) );
NOR2BX2TS U3432 ( .AN(n1321), .B(n1320), .Y(n1680) );
BUFX4TS U3433 ( .A(n1680), .Y(n3810) );
NAND3X2TS U3434 ( .A(n1322), .B(n1321), .C(n1320), .Y(n2686) );
CLKINVX6TS U3435 ( .A(n2686), .Y(n3156) );
AOI222X1TS U3436 ( .A0(n3788), .A1(n4162), .B0(n3810), .B1(n4118), .C0(n3803), .C1(n4090), .Y(n1323) );
CLKINVX6TS U3437 ( .A(n1576), .Y(n3814) );
XOR2X1TS U3438 ( .A(n1324), .B(n3814), .Y(Sgf_operation_mult_x_1_n4186) );
AOI222X1TS U3439 ( .A0(n3610), .A1(n2607), .B0(n3605), .B1(n2462), .C0(n2663), .C1(n3184), .Y(n1325) );
XOR2X1TS U3440 ( .A(n1326), .B(n2666), .Y(Sgf_operation_mult_x_1_n3753) );
AOI222X1TS U3441 ( .A0(n3732), .A1(n4151), .B0(n3743), .B1(n4140), .C0(n3742), .C1(n4139), .Y(n1327) );
XOR2X1TS U3442 ( .A(n1328), .B(n3746), .Y(Sgf_operation_mult_x_1_n4075) );
XOR2X1TS U3443 ( .A(n1330), .B(n3384), .Y(Sgf_operation_mult_x_1_n3804) );
AOI222X1TS U3444 ( .A0(n3788), .A1(n4151), .B0(n3810), .B1(n4140), .C0(n3803), .C1(n4139), .Y(n1331) );
XOR2X1TS U3445 ( .A(n1332), .B(n3814), .Y(Sgf_operation_mult_x_1_n4187) );
CLKINVX6TS U3446 ( .A(n4059), .Y(n3471) );
AOI222X1TS U3447 ( .A0(n3455), .A1(n4162), .B0(n3279), .B1(n4118), .C0(n3471), .C1(n4090), .Y(n1333) );
XOR2X1TS U3448 ( .A(n1334), .B(n3282), .Y(Sgf_operation_mult_x_1_n3517) );
AOI222X1TS U3449 ( .A0(n3610), .A1(n2654), .B0(n3605), .B1(n2653), .C0(n2663), .C1(n2946), .Y(n1335) );
XOR2X1TS U3450 ( .A(n1336), .B(n2666), .Y(Sgf_operation_mult_x_1_n3752) );
BUFX4TS U3451 ( .A(n1484), .Y(n3640) );
BUFX4TS U3452 ( .A(n1337), .Y(n3631) );
CLKINVX6TS U3453 ( .A(n3241), .Y(n3636) );
AOI222X1TS U3454 ( .A0(n3638), .A1(n4151), .B0(n3631), .B1(n4140), .C0(n3636), .C1(n4139), .Y(n1338) );
XOR2X1TS U3455 ( .A(n1339), .B(n3634), .Y(Sgf_operation_mult_x_1_n3851) );
AOI222X1TS U3456 ( .A0(n3455), .A1(n4151), .B0(n3279), .B1(n4140), .C0(n3471), .C1(n4139), .Y(n1340) );
XOR2X1TS U3457 ( .A(n1341), .B(n3282), .Y(Sgf_operation_mult_x_1_n3518) );
AOI222X1TS U3458 ( .A0(n3494), .A1(n2645), .B0(n3489), .B1(n2644), .C0(n3493), .C1(n3229), .Y(n1342) );
XOR2X1TS U3459 ( .A(n1343), .B(n3491), .Y(Sgf_operation_mult_x_1_n3544) );
INVX4TS U3460 ( .A(n1436), .Y(n3546) );
AOI222X1TS U3461 ( .A0(n3535), .A1(n3921), .B0(n3542), .B1(n2539), .C0(n3546), .C1(n3222), .Y(n1344) );
XOR2X1TS U3462 ( .A(n1346), .B(n3548), .Y(Sgf_operation_mult_x_1_n3649) );
AOI222X1TS U3463 ( .A0(n3561), .A1(n3912), .B0(n3578), .B1(n3911), .C0(n3588), .C1(n2954), .Y(n1347) );
XOR2X1TS U3464 ( .A(n1348), .B(n3364), .Y(Sgf_operation_mult_x_1_n3700) );
NAND2X1TS U3465 ( .A(n1413), .B(n1350), .Y(n1351) );
XNOR2X1TS U3466 ( .A(n1414), .B(n1351), .Y(n1352) );
BUFX4TS U3467 ( .A(Op_MY[4]), .Y(n4152) );
OAI21X1TS U3468 ( .A0(n4155), .A1(n3531), .B0(n1353), .Y(n1354) );
XOR2X1TS U3469 ( .A(n1354), .B(n3525), .Y(Sgf_operation_mult_x_1_n3627) );
AOI222X1TS U3470 ( .A0(n3622), .A1(n2713), .B0(n2778), .B1(n2712), .C0(n2777), .C1(n2942), .Y(n1355) );
XOR2X1TS U3471 ( .A(n1356), .B(n3384), .Y(Sgf_operation_mult_x_1_n3806) );
BUFX4TS U3472 ( .A(n1357), .Y(n3528) );
AOI222X1TS U3473 ( .A0(n3529), .A1(n2474), .B0(n3528), .B1(n2473), .C0(n3521), .C1(n2962), .Y(n1358) );
XOR2X1TS U3474 ( .A(n1359), .B(n3532), .Y(Sgf_operation_mult_x_1_n3595) );
XNOR2X2TS U3475 ( .A(n2761), .B(Op_MX[24]), .Y(n1361) );
CLKXOR2X2TS U3476 ( .A(n3404), .B(Op_MX[25]), .Y(n1362) );
NAND2BX2TS U3477 ( .AN(n1361), .B(n1362), .Y(n3679) );
BUFX4TS U3478 ( .A(n3679), .Y(n3691) );
NOR2X2TS U3479 ( .A(n1362), .B(n1361), .Y(n1841) );
BUFX4TS U3480 ( .A(n1841), .Y(n3689) );
NOR2BX2TS U3481 ( .AN(n1361), .B(n1360), .Y(n1677) );
BUFX4TS U3482 ( .A(n1677), .Y(n3682) );
NAND3X2TS U3483 ( .A(n1362), .B(n1361), .C(n1360), .Y(n3254) );
CLKINVX6TS U3484 ( .A(n3254), .Y(n3687) );
AOI222X1TS U3485 ( .A0(n3665), .A1(n4151), .B0(n3682), .B1(n4140), .C0(n3677), .C1(n4139), .Y(n1363) );
CLKINVX6TS U3486 ( .A(n1468), .Y(n3685) );
XOR2X1TS U3487 ( .A(n1364), .B(n3685), .Y(Sgf_operation_mult_x_1_n3963) );
BUFX4TS U3488 ( .A(n1984), .Y(n2757) );
AOI21X1TS U3489 ( .A0(n3657), .A1(n2728), .B0(n1365), .Y(n1366) );
XOR2X1TS U3490 ( .A(n1367), .B(n2758), .Y(Sgf_operation_mult_x_1_n3858) );
AOI222X1TS U3491 ( .A0(n3610), .A1(n3907), .B0(n3605), .B1(n3906), .C0(n2663), .C1(n3199), .Y(n1368) );
XOR2X1TS U3492 ( .A(n1369), .B(n2666), .Y(Sgf_operation_mult_x_1_n3754) );
INVX2TS U3493 ( .A(n1370), .Y(n1373) );
INVX2TS U3494 ( .A(n1371), .Y(n1372) );
NAND2X1TS U3495 ( .A(n1376), .B(n1375), .Y(n1377) );
BUFX4TS U3496 ( .A(n2660), .Y(n3845) );
BUFX4TS U3497 ( .A(n1395), .Y(n3843) );
BUFX4TS U3498 ( .A(n1396), .Y(n3835) );
BUFX4TS U3499 ( .A(Op_MY[7]), .Y(n4083) );
NAND3X2TS U3500 ( .A(n1382), .B(n1381), .C(n1380), .Y(n2599) );
CLKINVX6TS U3501 ( .A(n2599), .Y(n3841) );
AOI222X1TS U3502 ( .A0(n3831), .A1(n4084), .B0(n3835), .B1(n4083), .C0(n3827), .C1(n4166), .Y(n1383) );
XOR2X1TS U3503 ( .A(n1385), .B(n3837), .Y(Sgf_operation_mult_x_1_n4238) );
AOI21X1TS U3504 ( .A0(n1405), .A1(n1403), .B0(n1390), .Y(n1394) );
NAND2X1TS U3505 ( .A(n1392), .B(n1391), .Y(n1393) );
XNOR2X1TS U3506 ( .A(n1394), .B(n1393), .Y(n1559) );
BUFX4TS U3507 ( .A(n1395), .Y(n3831) );
BUFX4TS U3508 ( .A(n1396), .Y(n3842) );
BUFX4TS U3509 ( .A(Op_MY[11]), .Y(n3996) );
INVX4TS U3510 ( .A(n2599), .Y(n3827) );
XOR2X1TS U3511 ( .A(n1398), .B(n3846), .Y(Sgf_operation_mult_x_1_n4234) );
BUFX4TS U3512 ( .A(n3215), .Y(n3592) );
BUFX4TS U3513 ( .A(n1425), .Y(n3590) );
BUFX4TS U3514 ( .A(n1399), .Y(n3583) );
CLKINVX6TS U3515 ( .A(n3217), .Y(n3588) );
AOI222X1TS U3516 ( .A0(n3590), .A1(n4151), .B0(n3583), .B1(n4140), .C0(n3574), .C1(n4139), .Y(n1400) );
XOR2X1TS U3517 ( .A(n1401), .B(n3586), .Y(Sgf_operation_mult_x_1_n3740) );
NAND2X1TS U3518 ( .A(n1403), .B(n1402), .Y(n1404) );
XNOR2X1TS U3519 ( .A(n1405), .B(n1404), .Y(n1406) );
BUFX4TS U3520 ( .A(n1569), .Y(n3878) );
BUFX4TS U3521 ( .A(Op_MY[10]), .Y(n1912) );
XOR2X1TS U3522 ( .A(n1409), .B(n3881), .Y(Sgf_operation_mult_x_1_n4291) );
AOI222X1TS U3523 ( .A0(n3455), .A1(n4153), .B0(n3279), .B1(n4152), .C0(n3471), .C1(n4080), .Y(n1410) );
XOR2X1TS U3524 ( .A(n1411), .B(n3282), .Y(Sgf_operation_mult_x_1_n3516) );
AOI21X1TS U3525 ( .A0(n1414), .A1(n1413), .B0(n1412), .Y(n1418) );
NAND2X1TS U3526 ( .A(n1416), .B(n1415), .Y(n1417) );
XOR2X1TS U3527 ( .A(n1418), .B(n1417), .Y(n1419) );
XNOR2X2TS U3528 ( .A(n5152), .B(Op_MX[3]), .Y(n1421) );
CLKXOR2X2TS U3529 ( .A(n4145), .B(Op_MX[4]), .Y(n1422) );
NAND2BX2TS U3530 ( .AN(n1421), .B(n1422), .Y(n3896) );
BUFX4TS U3531 ( .A(n3896), .Y(n4096) );
NOR2X2TS U3532 ( .A(n1422), .B(n1421), .Y(n1564) );
BUFX4TS U3533 ( .A(n1564), .Y(n4106) );
NOR2BX2TS U3534 ( .AN(n1421), .B(n1420), .Y(n1555) );
BUFX4TS U3535 ( .A(n1555), .Y(n4105) );
BUFX4TS U3536 ( .A(Op_MY[5]), .Y(n4164) );
NAND3X2TS U3537 ( .A(n1422), .B(n1421), .C(n1420), .Y(n2651) );
CLKINVX6TS U3538 ( .A(n2651), .Y(n4104) );
AOI222X1TS U3539 ( .A0(n4101), .A1(n4166), .B0(n4105), .B1(n4164), .C0(n2794), .C1(n3720), .Y(n1423) );
XOR2X1TS U3540 ( .A(n1424), .B(n4109), .Y(Sgf_operation_mult_x_1_n4352) );
BUFX4TS U3541 ( .A(n1425), .Y(n3584) );
XOR2X1TS U3542 ( .A(n1427), .B(n3364), .Y(Sgf_operation_mult_x_1_n3701) );
XOR2X1TS U3543 ( .A(n1429), .B(n2758), .Y(Sgf_operation_mult_x_1_n3859) );
AOI222X1TS U3544 ( .A0(n3788), .A1(n4153), .B0(n3810), .B1(n4152), .C0(n3803), .C1(n4080), .Y(n1430) );
XOR2X1TS U3545 ( .A(n1431), .B(n3814), .Y(Sgf_operation_mult_x_1_n4185) );
AOI222X1TS U3546 ( .A0(n3732), .A1(n4153), .B0(n3743), .B1(n4152), .C0(n3742), .C1(n4080), .Y(n1432) );
XOR2X1TS U3547 ( .A(n1433), .B(n3746), .Y(Sgf_operation_mult_x_1_n4073) );
BUFX4TS U3548 ( .A(n1434), .Y(n3554) );
BUFX4TS U3549 ( .A(n1435), .Y(n3553) );
CLKINVX6TS U3550 ( .A(n1436), .Y(n3552) );
AOI222X1TS U3551 ( .A0(n3535), .A1(n4084), .B0(n3553), .B1(n4083), .C0(n3552), .C1(n3297), .Y(n1437) );
XOR2X1TS U3552 ( .A(n1438), .B(n3548), .Y(Sgf_operation_mult_x_1_n3680) );
AOI222X1TS U3553 ( .A0(n3638), .A1(n4162), .B0(n3631), .B1(n4118), .C0(n3636), .C1(n4090), .Y(n1439) );
XOR2X1TS U3554 ( .A(n1440), .B(n3634), .Y(Sgf_operation_mult_x_1_n3850) );
AOI222X1TS U3555 ( .A0(n3638), .A1(n4153), .B0(n3631), .B1(n4152), .C0(n3636), .C1(n4080), .Y(n1441) );
XOR2X1TS U3556 ( .A(n1442), .B(n3634), .Y(Sgf_operation_mult_x_1_n3849) );
AOI222X1TS U3557 ( .A0(n3561), .A1(n3990), .B0(n3589), .B1(n1912), .C0(n3582), .C1(n3289), .Y(n1443) );
XOR2X1TS U3558 ( .A(n1445), .B(n3593), .Y(Sgf_operation_mult_x_1_n3732) );
AOI222X1TS U3559 ( .A0(n3610), .A1(n2508), .B0(n3605), .B1(n2507), .C0(n2663), .C1(n3201), .Y(n1446) );
XOR2X1TS U3560 ( .A(n1447), .B(n2666), .Y(Sgf_operation_mult_x_1_n3755) );
XOR2X1TS U3561 ( .A(n1449), .B(n3532), .Y(Sgf_operation_mult_x_1_n3621) );
AOI222X1TS U3562 ( .A0(n3590), .A1(n3923), .B0(n3578), .B1(n3922), .C0(n3588), .C1(n2956), .Y(n1450) );
XOR2X1TS U3563 ( .A(n1451), .B(n3364), .Y(Sgf_operation_mult_x_1_n3702) );
AOI222X1TS U3564 ( .A0(n3554), .A1(n3819), .B0(n3542), .B1(n3818), .C0(n3546), .C1(n3787), .Y(n1453) );
XOR2X1TS U3565 ( .A(n1454), .B(n3548), .Y(Sgf_operation_mult_x_1_n3650) );
ADDHXLTS U3566 ( .A(n2769), .B(n1455), .CO(n3314), .S(
Sgf_operation_mult_x_1_n2268) );
OAI21X1TS U3567 ( .A0(n4086), .A1(n3531), .B0(n1456), .Y(n1457) );
XOR2X1TS U3568 ( .A(n1457), .B(n3532), .Y(Sgf_operation_mult_x_1_n3624) );
BUFX4TS U3569 ( .A(n3706), .Y(n3702) );
BUFX4TS U3570 ( .A(n1538), .Y(n3713) );
BUFX4TS U3571 ( .A(n1522), .Y(n3712) );
NAND3X2TS U3572 ( .A(n1460), .B(n1459), .C(n1458), .Y(n2760) );
INVX4TS U3573 ( .A(n2760), .Y(n2751) );
OAI21X1TS U3574 ( .A0(n2952), .A1(n3702), .B0(n1461), .Y(n1462) );
XOR2X1TS U3575 ( .A(n1462), .B(n2761), .Y(Sgf_operation_mult_x_1_n3980) );
AOI222X1TS U3576 ( .A0(n3501), .A1(n3990), .B0(n3489), .B1(n1912), .C0(n3499), .C1(n3289), .Y(n1463) );
XOR2X1TS U3577 ( .A(n1464), .B(n3491), .Y(Sgf_operation_mult_x_1_n3566) );
XOR2X1TS U3578 ( .A(n1466), .B(n4039), .Y(Sgf_operation_mult_x_1_n4297) );
BUFX4TS U3579 ( .A(n1677), .Y(n3688) );
AOI222X1TS U3580 ( .A0(n3683), .A1(n3990), .B0(n3688), .B1(n1912), .C0(n3681), .C1(n3289), .Y(n1467) );
XOR2X1TS U3581 ( .A(n1469), .B(n3692), .Y(Sgf_operation_mult_x_1_n3955) );
ADDHXLTS U3582 ( .A(n2761), .B(n1470), .CO(n3395), .S(
Sgf_operation_mult_x_1_n2664) );
AOI222X1TS U3583 ( .A0(n3665), .A1(n4162), .B0(n3682), .B1(n4118), .C0(n3677), .C1(n4090), .Y(n1471) );
XOR2X1TS U3584 ( .A(n1472), .B(n3685), .Y(Sgf_operation_mult_x_1_n3962) );
CLKXOR2X2TS U3585 ( .A(n5152), .B(Op_MX[1]), .Y(n1474) );
NAND2BX2TS U3586 ( .AN(n5071), .B(n1474), .Y(n2623) );
NOR2X2TS U3587 ( .A(n1474), .B(n5071), .Y(n1757) );
BUFX4TS U3588 ( .A(n1757), .Y(n4167) );
NOR2BX2TS U3589 ( .AN(n5071), .B(n1473), .Y(n1879) );
BUFX4TS U3590 ( .A(n1879), .Y(n3937) );
NAND3X2TS U3591 ( .A(n1474), .B(n1473), .C(n5071), .Y(n2670) );
INVX4TS U3592 ( .A(n2670), .Y(n3995) );
AOI222X1TS U3593 ( .A0(n3998), .A1(n2643), .B0(n3937), .B1(n2429), .C0(n3995), .C1(n3264), .Y(n1475) );
CLKINVX6TS U3594 ( .A(n5151), .Y(n4170) );
XOR2X1TS U3595 ( .A(n1476), .B(n4170), .Y(Sgf_operation_mult_x_1_n4383) );
AOI21X1TS U3596 ( .A0(n1479), .A1(n1478), .B0(n1477), .Y(n1483) );
NAND2X1TS U3597 ( .A(n1481), .B(n1480), .Y(n1482) );
XNOR2X1TS U3598 ( .A(n1483), .B(n1482), .Y(n2183) );
BUFX4TS U3599 ( .A(n1484), .Y(n3628) );
BUFX4TS U3600 ( .A(Op_MY[35]), .Y(n3884) );
INVX4TS U3601 ( .A(n3241), .Y(n3630) );
AOI222X1TS U3602 ( .A0(n3638), .A1(n3885), .B0(n3637), .B1(n3884), .C0(n3630), .C1(n3883), .Y(n1485) );
XOR2X1TS U3603 ( .A(n1487), .B(n3641), .Y(Sgf_operation_mult_x_1_n3818) );
AOI222X1TS U3604 ( .A0(n3529), .A1(n2584), .B0(n3528), .B1(n2583), .C0(n3521), .C1(n2968), .Y(n1488) );
XOR2X1TS U3605 ( .A(n1489), .B(n3532), .Y(Sgf_operation_mult_x_1_n3597) );
AOI21X1TS U3606 ( .A0(n1492), .A1(n1491), .B0(n1490), .Y(n1496) );
NAND2X1TS U3607 ( .A(n1494), .B(n1493), .Y(n1495) );
XNOR2X1TS U3608 ( .A(n1496), .B(n1495), .Y(n1691) );
BUFX4TS U3609 ( .A(n1502), .Y(n3651) );
BUFX4TS U3610 ( .A(n1503), .Y(n3643) );
BUFX4TS U3611 ( .A(Op_MY[21]), .Y(n3952) );
XOR2X1TS U3612 ( .A(n1498), .B(n2758), .Y(Sgf_operation_mult_x_1_n3888) );
BUFX4TS U3613 ( .A(Op_MY[13]), .Y(n3308) );
XOR2X1TS U3614 ( .A(n1500), .B(n3557), .Y(Sgf_operation_mult_x_1_n3674) );
ADDHXLTS U3615 ( .A(n2758), .B(n1501), .CO(n3375), .S(
Sgf_operation_mult_x_1_n2592) );
BUFX4TS U3616 ( .A(n1984), .Y(n3661) );
BUFX4TS U3617 ( .A(n1502), .Y(n3659) );
BUFX4TS U3618 ( .A(n1503), .Y(n3658) );
CLKINVX6TS U3619 ( .A(n1736), .Y(n3657) );
AOI222X1TS U3620 ( .A0(n3651), .A1(n4084), .B0(n3658), .B1(n4083), .C0(n3649), .C1(n3297), .Y(n1504) );
XOR2X1TS U3621 ( .A(n1506), .B(n3653), .Y(Sgf_operation_mult_x_1_n3902) );
AOI222X1TS U3622 ( .A0(n3683), .A1(n4084), .B0(n3682), .B1(n4083), .C0(n3687), .C1(n3297), .Y(n1507) );
XOR2X1TS U3623 ( .A(n1508), .B(n3692), .Y(Sgf_operation_mult_x_1_n3958) );
AOI222X1TS U3624 ( .A0(n3665), .A1(n4153), .B0(n3682), .B1(n4152), .C0(n3677), .C1(n4080), .Y(n1509) );
XOR2X1TS U3625 ( .A(n1510), .B(n3685), .Y(Sgf_operation_mult_x_1_n3961) );
AOI21X1TS U3626 ( .A0(n1513), .A1(n1512), .B0(n1511), .Y(n1517) );
NAND2X1TS U3627 ( .A(n1515), .B(n1514), .Y(n1516) );
XNOR2X1TS U3628 ( .A(n1517), .B(n1516), .Y(n2067) );
BUFX3TS U3629 ( .A(n3875), .Y(n4038) );
BUFX4TS U3630 ( .A(Op_MY[15]), .Y(n3981) );
AOI222X1TS U3631 ( .A0(n3850), .A1(n3982), .B0(n4035), .B1(n3981), .C0(n4034), .C1(n3034), .Y(n1518) );
XOR2X1TS U3632 ( .A(n1519), .B(n4039), .Y(Sgf_operation_mult_x_1_n4286) );
AOI222X1TS U3633 ( .A0(n3651), .A1(Op_MY[50]), .B0(n3643), .B1(n2752), .C0(
n3657), .C1(n4072), .Y(n1520) );
XOR2X1TS U3634 ( .A(n1521), .B(n2758), .Y(Sgf_operation_mult_x_1_n3860) );
BUFX4TS U3635 ( .A(n3706), .Y(n3725) );
BUFX4TS U3636 ( .A(n1522), .Y(n3722) );
INVX4TS U3637 ( .A(n2760), .Y(n3708) );
XOR2X1TS U3638 ( .A(n1524), .B(n3726), .Y(Sgf_operation_mult_x_1_n4010) );
INVX2TS U3639 ( .A(n1525), .Y(n1528) );
NAND2X1TS U3640 ( .A(n1542), .B(n1528), .Y(n1530) );
INVX2TS U3641 ( .A(n1526), .Y(n1527) );
AOI21X1TS U3642 ( .A0(n1543), .A1(n1528), .B0(n1527), .Y(n1529) );
NAND2X1TS U3643 ( .A(n1773), .B(n1531), .Y(n1532) );
XNOR2X1TS U3644 ( .A(n1774), .B(n1532), .Y(n1533) );
BUFX4TS U3645 ( .A(Op_MY[18]), .Y(n3966) );
AOI222X1TS U3646 ( .A0(n3494), .A1(n3967), .B0(n3500), .B1(n3966), .C0(n3499), .C1(n3017), .Y(n1534) );
XOR2X1TS U3647 ( .A(n1535), .B(n3504), .Y(Sgf_operation_mult_x_1_n3558) );
AOI222X1TS U3648 ( .A0(n3465), .A1(n3990), .B0(n3472), .B1(n1912), .C0(n3471), .C1(n3289), .Y(n1536) );
XOR2X1TS U3649 ( .A(n1537), .B(n3476), .Y(Sgf_operation_mult_x_1_n3510) );
BUFX4TS U3650 ( .A(n1538), .Y(n3723) );
CLKINVX6TS U3651 ( .A(n2760), .Y(n3721) );
AOI222X1TS U3652 ( .A0(n3696), .A1(n3990), .B0(n3704), .B1(n1912), .C0(n3708), .C1(n3289), .Y(n1539) );
XOR2X1TS U3653 ( .A(n1541), .B(n3710), .Y(Sgf_operation_mult_x_1_n4011) );
INVX2TS U3654 ( .A(n1542), .Y(n1545) );
INVX2TS U3655 ( .A(n1543), .Y(n1544) );
AOI21X1TS U3656 ( .A0(n1707), .A1(n1705), .B0(n1546), .Y(n1550) );
NAND2X1TS U3657 ( .A(n1548), .B(n1547), .Y(n1549) );
XNOR2X1TS U3658 ( .A(n1550), .B(n1549), .Y(n1793) );
BUFX3TS U3659 ( .A(n3896), .Y(n4108) );
BUFX4TS U3660 ( .A(n1564), .Y(n3901) );
BUFX4TS U3661 ( .A(n1555), .Y(n3900) );
BUFX4TS U3662 ( .A(Op_MY[17]), .Y(n3971) );
XOR2X1TS U3663 ( .A(n1552), .B(n4109), .Y(Sgf_operation_mult_x_1_n4340) );
AOI222X1TS U3664 ( .A0(n3501), .A1(n4084), .B0(n3489), .B1(n4083), .C0(n3499), .C1(n3297), .Y(n1553) );
XOR2X1TS U3665 ( .A(n1554), .B(n3491), .Y(Sgf_operation_mult_x_1_n3569) );
BUFX4TS U3666 ( .A(n3896), .Y(n2796) );
BUFX4TS U3667 ( .A(n1555), .Y(n4098) );
INVX4TS U3668 ( .A(n2651), .Y(n2794) );
XOR2X1TS U3669 ( .A(n1557), .B(n4145), .Y(Sgf_operation_mult_x_1_n4316) );
ADDHXLTS U3670 ( .A(n2666), .B(n1558), .CO(n3355), .S(
Sgf_operation_mult_x_1_n2502) );
BUFX4TS U3671 ( .A(n3850), .Y(n4031) );
INVX4TS U3672 ( .A(n2702), .Y(n3867) );
AOI222X1TS U3673 ( .A0(n4031), .A1(n3997), .B0(n4035), .B1(n3996), .C0(n3867), .C1(n3808), .Y(n1560) );
XOR2X1TS U3674 ( .A(n1561), .B(n4039), .Y(Sgf_operation_mult_x_1_n4290) );
AOI222X1TS U3675 ( .A0(n3535), .A1(n3990), .B0(n3542), .B1(n1912), .C0(n3552), .C1(n3289), .Y(n1562) );
XOR2X1TS U3676 ( .A(n1563), .B(n3548), .Y(Sgf_operation_mult_x_1_n3677) );
BUFX4TS U3677 ( .A(n1564), .Y(n4101) );
AOI222X1TS U3678 ( .A0(n3901), .A1(n3912), .B0(n4098), .B1(n3911), .C0(n3894), .C1(n2954), .Y(n1565) );
XOR2X1TS U3679 ( .A(n1566), .B(n4145), .Y(Sgf_operation_mult_x_1_n4315) );
AOI222X1TS U3680 ( .A0(n3455), .A1(n4084), .B0(n3472), .B1(n4083), .C0(n3471), .C1(n3297), .Y(n1567) );
XOR2X1TS U3681 ( .A(n1568), .B(n3476), .Y(Sgf_operation_mult_x_1_n3513) );
BUFX4TS U3682 ( .A(n1569), .Y(n4027) );
AOI222X1TS U3683 ( .A0(n4031), .A1(n3912), .B0(n4027), .B1(n3911), .C0(n3873), .C1(n2954), .Y(n1570) );
XOR2X1TS U3684 ( .A(n1571), .B(n4094), .Y(Sgf_operation_mult_x_1_n4259) );
AOI222X1TS U3685 ( .A0(n4101), .A1(n4084), .B0(n3900), .B1(n4083), .C0(n2794), .C1(n3297), .Y(n1572) );
XOR2X1TS U3686 ( .A(n1574), .B(n3897), .Y(Sgf_operation_mult_x_1_n4350) );
BUFX4TS U3687 ( .A(n2649), .Y(n3798) );
BUFX4TS U3688 ( .A(n1680), .Y(n3804) );
INVX4TS U3689 ( .A(n2686), .Y(n3809) );
AOI222X1TS U3690 ( .A0(n3805), .A1(n2584), .B0(n3804), .B1(n2583), .C0(n3809), .C1(n2968), .Y(n1575) );
XOR2X1TS U3691 ( .A(n1577), .B(n3801), .Y(Sgf_operation_mult_x_1_n4155) );
AOI222X1TS U3692 ( .A0(n3723), .A1(n4084), .B0(n3722), .B1(n4083), .C0(n3708), .C1(n3297), .Y(n1578) );
XOR2X1TS U3693 ( .A(n1579), .B(n3710), .Y(Sgf_operation_mult_x_1_n4014) );
BUFX4TS U3694 ( .A(Op_MY[14]), .Y(n3985) );
XOR2X1TS U3695 ( .A(n1581), .B(n3282), .Y(Sgf_operation_mult_x_1_n3506) );
XOR2X1TS U3696 ( .A(n1583), .B(n3525), .Y(Sgf_operation_mult_x_1_n3618) );
NAND2X1TS U3697 ( .A(n1585), .B(n1584), .Y(n1586) );
XNOR2X1TS U3698 ( .A(n1587), .B(n1586), .Y(n1613) );
BUFX4TS U3699 ( .A(Op_MY[6]), .Y(n4114) );
AOI222X1TS U3700 ( .A0(n4101), .A1(n4115), .B0(n3900), .B1(n4114), .C0(n2794), .C1(n3717), .Y(n1588) );
XOR2X1TS U3701 ( .A(n1589), .B(n4109), .Y(Sgf_operation_mult_x_1_n4351) );
ADDHXLTS U3702 ( .A(n2799), .B(n1590), .CO(n3415), .S(
Sgf_operation_mult_x_1_n2718) );
AOI222X1TS U3703 ( .A0(n3696), .A1(n3907), .B0(n3712), .B1(n3906), .C0(n3708), .C1(n3199), .Y(n1591) );
XOR2X1TS U3704 ( .A(n1592), .B(n2761), .Y(Sgf_operation_mult_x_1_n3977) );
AOI222X1TS U3705 ( .A0(n3788), .A1(n3990), .B0(n3804), .B1(n1912), .C0(n3803), .C1(n3289), .Y(n1593) );
XOR2X1TS U3706 ( .A(n1594), .B(n3801), .Y(Sgf_operation_mult_x_1_n4179) );
BUFX4TS U3707 ( .A(n1632), .Y(n3749) );
AOI222X1TS U3708 ( .A0(n3729), .A1(n3990), .B0(n3749), .B1(n1912), .C0(n3748), .C1(n3289), .Y(n1595) );
XOR2X1TS U3709 ( .A(n1597), .B(n3753), .Y(Sgf_operation_mult_x_1_n4067) );
INVX2TS U3710 ( .A(n1598), .Y(n1943) );
NAND2X1TS U3711 ( .A(n1942), .B(n1599), .Y(n1600) );
XNOR2X1TS U3712 ( .A(n1943), .B(n1600), .Y(n1601) );
BUFX4TS U3713 ( .A(n2623), .Y(n4169) );
BUFX4TS U3714 ( .A(n1879), .Y(n4165) );
BUFX4TS U3715 ( .A(Op_MY[8]), .Y(n2396) );
CLKINVX6TS U3716 ( .A(n2670), .Y(n4163) );
AOI222X1TS U3717 ( .A0(n4134), .A1(n2397), .B0(n4165), .B1(n2396), .C0(n3951), .C1(n4115), .Y(n1602) );
XOR2X1TS U3718 ( .A(n1603), .B(n4170), .Y(Sgf_operation_mult_x_1_n4405) );
BUFX4TS U3719 ( .A(n1611), .Y(n3619) );
CLKINVX6TS U3720 ( .A(n1609), .Y(n3615) );
XOR2X1TS U3721 ( .A(n1606), .B(n3603), .Y(Sgf_operation_mult_x_1_n3788) );
AOI222X1TS U3722 ( .A0(n3561), .A1(n4162), .B0(n3583), .B1(n4118), .C0(n3574), .C1(n4090), .Y(n1607) );
XOR2X1TS U3723 ( .A(n1608), .B(n3586), .Y(Sgf_operation_mult_x_1_n3739) );
BUFX3TS U3724 ( .A(n3595), .Y(n3599) );
BUFX4TS U3725 ( .A(Op_MY[31]), .Y(n3858) );
INVX4TS U3726 ( .A(n1609), .Y(n3609) );
AOI222X1TS U3727 ( .A0(n3599), .A1(n3859), .B0(n3598), .B1(n3858), .C0(n3609), .C1(n3857), .Y(n1610) );
XOR2X1TS U3728 ( .A(n1612), .B(n3603), .Y(Sgf_operation_mult_x_1_n3767) );
AOI222X1TS U3729 ( .A0(n3455), .A1(n4115), .B0(n3279), .B1(n4114), .C0(n3471), .C1(n3717), .Y(n1614) );
XOR2X1TS U3730 ( .A(n1615), .B(n3282), .Y(Sgf_operation_mult_x_1_n3514) );
AOI222X1TS U3731 ( .A0(n3561), .A1(n4084), .B0(n3583), .B1(n4083), .C0(n3582), .C1(n3297), .Y(n1616) );
XOR2X1TS U3732 ( .A(n1617), .B(n3593), .Y(Sgf_operation_mult_x_1_n3735) );
BUFX4TS U3733 ( .A(n1721), .Y(n3780) );
NAND3X2TS U3734 ( .A(n1620), .B(n1619), .C(n1618), .Y(n2790) );
INVX4TS U3735 ( .A(n2790), .Y(n3772) );
AOI222X1TS U3736 ( .A0(n3780), .A1(n2643), .B0(n3758), .B1(n2429), .C0(n3778), .C1(n3264), .Y(n1621) );
XOR2X1TS U3737 ( .A(n1623), .B(n3762), .Y(Sgf_operation_mult_x_1_n4103) );
XOR2X1TS U3738 ( .A(n1625), .B(n4039), .Y(Sgf_operation_mult_x_1_n4287) );
AOI222X1TS U3739 ( .A0(n3696), .A1(n3912), .B0(n3712), .B1(n3911), .C0(n3721), .C1(n2954), .Y(n1626) );
XOR2X1TS U3740 ( .A(n1627), .B(n2761), .Y(Sgf_operation_mult_x_1_n3979) );
BUFX4TS U3741 ( .A(n1757), .Y(n3998) );
XOR2X1TS U3742 ( .A(n1629), .B(n4170), .Y(Sgf_operation_mult_x_1_n4381) );
AOI222X1TS U3743 ( .A0(n3590), .A1(n4153), .B0(n3583), .B1(n4152), .C0(n3574), .C1(n4080), .Y(n1630) );
XOR2X1TS U3744 ( .A(n1631), .B(n3586), .Y(Sgf_operation_mult_x_1_n3738) );
BUFX4TS U3745 ( .A(n2734), .Y(n3745) );
BUFX4TS U3746 ( .A(n1674), .Y(n3732) );
BUFX4TS U3747 ( .A(n1632), .Y(n3728) );
INVX4TS U3748 ( .A(n2792), .Y(n3742) );
AOI222X1TS U3749 ( .A0(n3729), .A1(n2508), .B0(n3728), .B1(n2507), .C0(n3748), .C1(n3201), .Y(n1633) );
XOR2X1TS U3750 ( .A(n1634), .B(n3424), .Y(Sgf_operation_mult_x_1_n4034) );
XOR2X1TS U3751 ( .A(n1637), .B(n3641), .Y(Sgf_operation_mult_x_1_n3821) );
ADDHXLTS U3752 ( .A(n2661), .B(n1638), .CO(n3435), .S(
Sgf_operation_mult_x_1_n2754) );
BUFX4TS U3753 ( .A(n3756), .Y(n3782) );
CLKINVX6TS U3754 ( .A(n2790), .Y(n3778) );
AOI222X1TS U3755 ( .A0(n3780), .A1(n3990), .B0(n3758), .B1(n1912), .C0(n3764), .C1(n2397), .Y(n1639) );
XOR2X1TS U3756 ( .A(n1640), .B(n3762), .Y(Sgf_operation_mult_x_1_n4123) );
AOI222X1TS U3757 ( .A0(n3622), .A1(n2654), .B0(n2778), .B1(n2653), .C0(n2777), .C1(n2946), .Y(n1641) );
XOR2X1TS U3758 ( .A(n1642), .B(n3384), .Y(Sgf_operation_mult_x_1_n3807) );
AOI21X1TS U3759 ( .A0(n1645), .A1(n1644), .B0(n1643), .Y(n1649) );
NAND2X1TS U3760 ( .A(n1647), .B(n1646), .Y(n1648) );
XNOR2X1TS U3761 ( .A(n1649), .B(n1648), .Y(n2080) );
BUFX4TS U3762 ( .A(Op_MY[33]), .Y(n3889) );
AOI222X1TS U3763 ( .A0(n3599), .A1(n3890), .B0(n3598), .B1(n3889), .C0(n3609), .C1(n3888), .Y(n1650) );
XOR2X1TS U3764 ( .A(n1651), .B(n3603), .Y(Sgf_operation_mult_x_1_n3765) );
OAI21X1TS U3765 ( .A0(n644), .A1(n3531), .B0(n1652), .Y(n1653) );
XOR2X1TS U3766 ( .A(n1653), .B(n3525), .Y(Sgf_operation_mult_x_1_n3625) );
AOI222X1TS U3767 ( .A0(n4031), .A1(n3923), .B0(n4027), .B1(n3922), .C0(n3873), .C1(n2956), .Y(n1654) );
XOR2X1TS U3768 ( .A(n1655), .B(n4094), .Y(Sgf_operation_mult_x_1_n4261) );
XOR2X1TS U3769 ( .A(n1657), .B(n3282), .Y(Sgf_operation_mult_x_1_n3509) );
XOR2X1TS U3770 ( .A(n1659), .B(n3663), .Y(Sgf_operation_mult_x_1_n3891) );
AOI222X1TS U3771 ( .A0(n3638), .A1(n4084), .B0(n3631), .B1(n4083), .C0(n3636), .C1(n3297), .Y(n1660) );
XOR2X1TS U3772 ( .A(n1661), .B(n3641), .Y(Sgf_operation_mult_x_1_n3846) );
BUFX4TS U3773 ( .A(n1716), .Y(n3779) );
AOI222X1TS U3774 ( .A0(n2424), .A1(n4084), .B0(n3779), .B1(n4083), .C0(n3764), .C1(n4166), .Y(n1662) );
XOR2X1TS U3775 ( .A(n1663), .B(n3762), .Y(Sgf_operation_mult_x_1_n4126) );
BUFX4TS U3776 ( .A(n2660), .Y(n3829) );
AOI222X1TS U3777 ( .A0(n3820), .A1(n3921), .B0(n3129), .B1(n2539), .C0(n3841), .C1(n2474), .Y(n1664) );
XOR2X1TS U3778 ( .A(n1665), .B(n3837), .Y(Sgf_operation_mult_x_1_n4207) );
AOI222X1TS U3779 ( .A0(n3683), .A1(n4115), .B0(n3682), .B1(n4114), .C0(n3677), .C1(n3717), .Y(n1666) );
XOR2X1TS U3780 ( .A(n1667), .B(n3685), .Y(Sgf_operation_mult_x_1_n3959) );
XOR2X1TS U3781 ( .A(n1669), .B(n3663), .Y(Sgf_operation_mult_x_1_n3889) );
AOI222X1TS U3782 ( .A0(n3584), .A1(n2397), .B0(n3583), .B1(n2396), .C0(n3582), .C1(n3294), .Y(n1670) );
XOR2X1TS U3783 ( .A(n1671), .B(n3593), .Y(Sgf_operation_mult_x_1_n3734) );
AOI222X1TS U3784 ( .A0(n3638), .A1(n2584), .B0(n3637), .B1(n2583), .C0(n3630), .C1(n2968), .Y(n1672) );
XOR2X1TS U3785 ( .A(n1673), .B(n3641), .Y(Sgf_operation_mult_x_1_n3819) );
BUFX4TS U3786 ( .A(n1674), .Y(n3729) );
INVX4TS U3787 ( .A(n2792), .Y(n3739) );
OAI21X1TS U3788 ( .A0(n2973), .A1(n2734), .B0(n1675), .Y(n1676) );
XOR2X1TS U3789 ( .A(n1676), .B(n3753), .Y(Sgf_operation_mult_x_1_n4047) );
BUFX4TS U3790 ( .A(n3679), .Y(n3675) );
BUFX4TS U3791 ( .A(n1841), .Y(n3683) );
BUFX4TS U3792 ( .A(n1677), .Y(n2746) );
INVX4TS U3793 ( .A(n3254), .Y(n3681) );
OAI21X1TS U3794 ( .A0(n630), .A1(n3675), .B0(n1678), .Y(n1679) );
XOR2X1TS U3795 ( .A(n1679), .B(n3692), .Y(Sgf_operation_mult_x_1_n3926) );
BUFX4TS U3796 ( .A(n1699), .Y(n3788) );
BUFX4TS U3797 ( .A(n1680), .Y(n3151) );
INVX4TS U3798 ( .A(n2686), .Y(n3803) );
AOI222X1TS U3799 ( .A0(n3805), .A1(n3923), .B0(n3151), .B1(n3922), .C0(n3809), .C1(n2956), .Y(n1681) );
XOR2X1TS U3800 ( .A(n1682), .B(n3444), .Y(Sgf_operation_mult_x_1_n4149) );
AOI222X1TS U3801 ( .A0(n3599), .A1(n2645), .B0(n3598), .B1(n2644), .C0(n3609), .C1(n3229), .Y(n1683) );
XOR2X1TS U3802 ( .A(n1684), .B(n3603), .Y(Sgf_operation_mult_x_1_n3766) );
AOI222X1TS U3803 ( .A0(n3494), .A1(n2643), .B0(n3489), .B1(n2429), .C0(n3493), .C1(n2981), .Y(n1685) );
XOR2X1TS U3804 ( .A(n1686), .B(n3491), .Y(Sgf_operation_mult_x_1_n3546) );
AOI222X1TS U3805 ( .A0(n4106), .A1(n2508), .B0(n4098), .B1(n2507), .C0(n3894), .C1(n3201), .Y(n1687) );
XOR2X1TS U3806 ( .A(n1688), .B(n4145), .Y(Sgf_operation_mult_x_1_n4314) );
AOI222X1TS U3807 ( .A0(n3723), .A1(n2607), .B0(n3712), .B1(n2462), .C0(n3721), .C1(n3184), .Y(n1689) );
XOR2X1TS U3808 ( .A(n1690), .B(n2761), .Y(Sgf_operation_mult_x_1_n3976) );
INVX4TS U3809 ( .A(n3254), .Y(n3677) );
XOR2X1TS U3810 ( .A(n1693), .B(n3404), .Y(Sgf_operation_mult_x_1_n3944) );
XOR2X1TS U3811 ( .A(n1695), .B(n3692), .Y(Sgf_operation_mult_x_1_n3935) );
XOR2X1TS U3812 ( .A(n1697), .B(n3557), .Y(Sgf_operation_mult_x_1_n3676) );
ADDHXLTS U3813 ( .A(n2344), .B(n1698), .CO(n3334), .S(
Sgf_operation_mult_x_1_n2394) );
BUFX4TS U3814 ( .A(n1699), .Y(n3811) );
XOR2X1TS U3815 ( .A(n1701), .B(n3801), .Y(Sgf_operation_mult_x_1_n4153) );
AOI222X1TS U3816 ( .A0(n3732), .A1(n4084), .B0(n3743), .B1(n4083), .C0(n3742), .C1(n3297), .Y(n1702) );
XOR2X1TS U3817 ( .A(n1703), .B(n3753), .Y(Sgf_operation_mult_x_1_n4070) );
NAND2X1TS U3818 ( .A(n1705), .B(n1704), .Y(n1706) );
XNOR2X1TS U3819 ( .A(n1707), .B(n1706), .Y(n1708) );
BUFX4TS U3820 ( .A(Op_MY[16]), .Y(n3975) );
XOR2X1TS U3821 ( .A(n1710), .B(n4039), .Y(Sgf_operation_mult_x_1_n4285) );
AOI222X1TS U3822 ( .A0(n3901), .A1(n3907), .B0(n4098), .B1(n3906), .C0(n4104), .C1(n3199), .Y(n1711) );
XOR2X1TS U3823 ( .A(n1712), .B(n4145), .Y(Sgf_operation_mult_x_1_n4313) );
BUFX4TS U3824 ( .A(n1713), .Y(n3616) );
XOR2X1TS U3825 ( .A(n1715), .B(n3620), .Y(Sgf_operation_mult_x_1_n3785) );
BUFX4TS U3826 ( .A(n3756), .Y(n3766) );
BUFX4TS U3827 ( .A(n1716), .Y(n3768) );
INVX4TS U3828 ( .A(n2790), .Y(n3764) );
AOI222X1TS U3829 ( .A0(n3780), .A1(n3912), .B0(n3768), .B1(n3911), .C0(n3772), .C1(n3923), .Y(n1717) );
XOR2X1TS U3830 ( .A(n1718), .B(n2799), .Y(Sgf_operation_mult_x_1_n4091) );
AOI222X1TS U3831 ( .A0(n3773), .A1(n3819), .B0(n3758), .B1(n3818), .C0(n3778), .C1(n3885), .Y(n1719) );
XOR2X1TS U3832 ( .A(n1720), .B(n3762), .Y(Sgf_operation_mult_x_1_n4096) );
BUFX4TS U3833 ( .A(n1721), .Y(n3773) );
XOR2X1TS U3834 ( .A(n1723), .B(n3783), .Y(Sgf_operation_mult_x_1_n4116) );
NAND2X1TS U3835 ( .A(n2975), .B(n1725), .Y(n1726) );
BUFX4TS U3836 ( .A(Op_MY[28]), .Y(n3263) );
AOI222X1TS U3837 ( .A0(n3750), .A1(n3264), .B0(n3749), .B1(n3263), .C0(n3748), .C1(n3262), .Y(n1728) );
XOR2X1TS U3838 ( .A(n1729), .B(n3753), .Y(Sgf_operation_mult_x_1_n4049) );
AOI21X1TS U3839 ( .A0(n3156), .A1(n4053), .B0(n3151), .Y(n1730) );
XOR2X1TS U3840 ( .A(n1731), .B(n3444), .Y(Sgf_operation_mult_x_1_n4137) );
AOI222X1TS U3841 ( .A0(n3599), .A1(n3986), .B0(n3616), .B1(n3985), .C0(n3615), .C1(n3301), .Y(n1732) );
XOR2X1TS U3842 ( .A(n1733), .B(n3620), .Y(Sgf_operation_mult_x_1_n3784) );
AOI222X1TS U3843 ( .A0(n3729), .A1(n3912), .B0(n3728), .B1(n3911), .C0(n3748), .C1(n2954), .Y(n1734) );
XOR2X1TS U3844 ( .A(n1735), .B(n3424), .Y(Sgf_operation_mult_x_1_n4035) );
INVX4TS U3845 ( .A(n1736), .Y(n3649) );
XOR2X1TS U3846 ( .A(n1738), .B(n3653), .Y(Sgf_operation_mult_x_1_n3873) );
XOR2X1TS U3847 ( .A(n1740), .B(n3282), .Y(Sgf_operation_mult_x_1_n3507) );
AOI222X1TS U3848 ( .A0(n1452), .A1(n2397), .B0(n3553), .B1(n2396), .C0(n3552), .C1(n3294), .Y(n1741) );
XOR2X1TS U3849 ( .A(n1742), .B(n3548), .Y(Sgf_operation_mult_x_1_n3679) );
XOR2X1TS U3850 ( .A(n1744), .B(n3603), .Y(Sgf_operation_mult_x_1_n3791) );
AOI222X1TS U3851 ( .A0(n3750), .A1(n2607), .B0(n3728), .B1(n2462), .C0(n3748), .C1(n3184), .Y(n1745) );
XOR2X1TS U3852 ( .A(n1746), .B(n3424), .Y(Sgf_operation_mult_x_1_n4032) );
INVX4TS U3853 ( .A(n2599), .Y(n3128) );
AOI222X1TS U3854 ( .A0(n3831), .A1(n3923), .B0(n3129), .B1(n3922), .C0(n3841), .C1(n3921), .Y(n1747) );
XOR2X1TS U3855 ( .A(n1748), .B(n2661), .Y(Sgf_operation_mult_x_1_n4205) );
XOR2X1TS U3856 ( .A(n1750), .B(n4039), .Y(Sgf_operation_mult_x_1_n4295) );
AOI222X1TS U3857 ( .A0(n2695), .A1(n3990), .B0(n3650), .B1(n1912), .C0(n3649), .C1(n3289), .Y(n1751) );
XOR2X1TS U3858 ( .A(n1752), .B(n3653), .Y(Sgf_operation_mult_x_1_n3899) );
AOI222X1TS U3859 ( .A0(n3773), .A1(n3907), .B0(n3768), .B1(n3906), .C0(n3772), .C1(n3912), .Y(n1753) );
XOR2X1TS U3860 ( .A(n1754), .B(n2799), .Y(Sgf_operation_mult_x_1_n4089) );
XOR2X1TS U3861 ( .A(n1756), .B(n3846), .Y(Sgf_operation_mult_x_1_n4231) );
BUFX4TS U3862 ( .A(n1757), .Y(n4134) );
INVX4TS U3863 ( .A(n2670), .Y(n3951) );
AOI222X1TS U3864 ( .A0(n3998), .A1(n3235), .B0(n4165), .B1(n3234), .C0(n3995), .C1(n2654), .Y(n1758) );
XOR2X1TS U3865 ( .A(n1759), .B(n5152), .Y(Sgf_operation_mult_x_1_n4365) );
XOR2X1TS U3866 ( .A(n1761), .B(n3634), .Y(Sgf_operation_mult_x_1_n3837) );
AOI222X1TS U3867 ( .A0(n3831), .A1(n2474), .B0(n3835), .B1(n2473), .C0(n3841), .C1(n2584), .Y(n1762) );
XOR2X1TS U3868 ( .A(n1763), .B(n3837), .Y(Sgf_operation_mult_x_1_n4209) );
AOI222X1TS U3869 ( .A0(n4101), .A1(n2397), .B0(n3900), .B1(n2396), .C0(n2794), .C1(n3294), .Y(n1764) );
XOR2X1TS U3870 ( .A(n1765), .B(n3897), .Y(Sgf_operation_mult_x_1_n4349) );
AOI222X1TS U3871 ( .A0(n3501), .A1(n2397), .B0(n3489), .B1(n2396), .C0(n3499), .C1(n3294), .Y(n1766) );
XOR2X1TS U3872 ( .A(n1767), .B(n3491), .Y(Sgf_operation_mult_x_1_n3568) );
OAI21X1TS U3873 ( .A0(n3288), .A1(n3531), .B0(n1768), .Y(n1769) );
XOR2X1TS U3874 ( .A(n1769), .B(n3532), .Y(Sgf_operation_mult_x_1_n3623) );
AOI222X1TS U3875 ( .A0(n3788), .A1(n4084), .B0(n3804), .B1(n4083), .C0(n3803), .C1(n3297), .Y(n1770) );
XOR2X1TS U3876 ( .A(n1771), .B(n3801), .Y(Sgf_operation_mult_x_1_n4182) );
AOI21X1TS U3877 ( .A0(n1774), .A1(n1773), .B0(n1772), .Y(n1778) );
NAND2X1TS U3878 ( .A(n1776), .B(n1775), .Y(n1777) );
XNOR2X1TS U3879 ( .A(n1778), .B(n1777), .Y(n1850) );
BUFX4TS U3880 ( .A(Op_MY[19]), .Y(n3962) );
AOI222X1TS U3881 ( .A0(n3494), .A1(n3963), .B0(n3500), .B1(n3962), .C0(n3499), .C1(n3015), .Y(n1779) );
XOR2X1TS U3882 ( .A(n1780), .B(n3504), .Y(Sgf_operation_mult_x_1_n3557) );
XOR2X1TS U3883 ( .A(n1782), .B(n3746), .Y(Sgf_operation_mult_x_1_n4066) );
XOR2X1TS U3884 ( .A(n1784), .B(n3525), .Y(Sgf_operation_mult_x_1_n3617) );
XOR2X1TS U3885 ( .A(n1786), .B(n4109), .Y(Sgf_operation_mult_x_1_n4339) );
AOI222X1TS U3886 ( .A0(n4031), .A1(n2508), .B0(n4027), .B1(n2507), .C0(n3873), .C1(n3201), .Y(n1787) );
XOR2X1TS U3887 ( .A(n1788), .B(n4094), .Y(Sgf_operation_mult_x_1_n4258) );
AOI222X1TS U3888 ( .A0(n3713), .A1(n3921), .B0(n3704), .B1(n2539), .C0(n3721), .C1(n3222), .Y(n1789) );
XOR2X1TS U3889 ( .A(n1790), .B(n3710), .Y(Sgf_operation_mult_x_1_n3983) );
AOI222X1TS U3890 ( .A0(n3622), .A1(n3907), .B0(n2778), .B1(n3906), .C0(n2777), .C1(n3199), .Y(n1791) );
XOR2X1TS U3891 ( .A(n1792), .B(n3384), .Y(Sgf_operation_mult_x_1_n3809) );
XOR2X1TS U3892 ( .A(n1795), .B(n3282), .Y(Sgf_operation_mult_x_1_n3503) );
XOR2X1TS U3893 ( .A(n1797), .B(n3663), .Y(Sgf_operation_mult_x_1_n3890) );
XOR2X1TS U3894 ( .A(n1799), .B(n4170), .Y(Sgf_operation_mult_x_1_n4377) );
AOI21X1TS U3895 ( .A0(n3841), .A1(n4047), .B0(n3129), .Y(n1800) );
XOR2X1TS U3896 ( .A(n1801), .B(n2661), .Y(Sgf_operation_mult_x_1_n4193) );
XOR2X1TS U3897 ( .A(n1803), .B(n3801), .Y(Sgf_operation_mult_x_1_n4157) );
XOR2X1TS U3898 ( .A(n1805), .B(n2799), .Y(Sgf_operation_mult_x_1_n4092) );
OAI21X1TS U3899 ( .A0(n2961), .A1(n3702), .B0(n1806), .Y(n1807) );
XOR2X1TS U3900 ( .A(n1807), .B(n3710), .Y(Sgf_operation_mult_x_1_n3985) );
NAND2X1TS U3901 ( .A(n1809), .B(n1808), .Y(n1810) );
XNOR2X1TS U3902 ( .A(n2007), .B(n1810), .Y(n2329) );
BUFX4TS U3903 ( .A(Op_MY[12]), .Y(n3991) );
XOR2X1TS U3904 ( .A(n1812), .B(n3620), .Y(Sgf_operation_mult_x_1_n3786) );
AOI222X1TS U3905 ( .A0(n3599), .A1(n3976), .B0(n3616), .B1(n3975), .C0(n3615), .C1(n3278), .Y(n1813) );
XOR2X1TS U3906 ( .A(n1814), .B(n3620), .Y(Sgf_operation_mult_x_1_n3782) );
INVX4TS U3907 ( .A(n3217), .Y(n3582) );
AOI222X1TS U3908 ( .A0(n3590), .A1(n3921), .B0(n3589), .B1(n2539), .C0(n3588), .C1(n3222), .Y(n1815) );
XOR2X1TS U3909 ( .A(n1816), .B(n3593), .Y(Sgf_operation_mult_x_1_n3704) );
XOR2X1TS U3910 ( .A(n1818), .B(n3634), .Y(Sgf_operation_mult_x_1_n3838) );
XOR2X1TS U3911 ( .A(n1820), .B(n3762), .Y(Sgf_operation_mult_x_1_n4101) );
AOI222X1TS U3912 ( .A0(n3638), .A1(n4115), .B0(n3631), .B1(n4114), .C0(n3636), .C1(n3717), .Y(n1821) );
XOR2X1TS U3913 ( .A(n1822), .B(n3634), .Y(Sgf_operation_mult_x_1_n3847) );
XOR2X1TS U3914 ( .A(n1824), .B(n3783), .Y(Sgf_operation_mult_x_1_n4119) );
XOR2X1TS U3915 ( .A(n1826), .B(n3525), .Y(Sgf_operation_mult_x_1_n3615) );
AOI21X1TS U3916 ( .A0(n1829), .A1(n1828), .B0(n1827), .Y(n1833) );
NAND2X1TS U3917 ( .A(n1831), .B(n1830), .Y(n1832) );
XOR2X1TS U3918 ( .A(n1833), .B(n1832), .Y(n1834) );
BUFX4TS U3919 ( .A(Op_MY[23]), .Y(n3942) );
XOR2X1TS U3920 ( .A(n1836), .B(n2661), .Y(Sgf_operation_mult_x_1_n4222) );
AOI222X1TS U3921 ( .A0(n4101), .A1(n3990), .B0(n3900), .B1(n1912), .C0(n2794), .C1(n3289), .Y(n1837) );
XOR2X1TS U3922 ( .A(n1838), .B(n3897), .Y(Sgf_operation_mult_x_1_n4347) );
AOI222X1TS U3923 ( .A0(n3599), .A1(n2643), .B0(n3598), .B1(n2429), .C0(n3609), .C1(n2981), .Y(n1839) );
XOR2X1TS U3924 ( .A(n1840), .B(n3603), .Y(Sgf_operation_mult_x_1_n3768) );
BUFX4TS U3925 ( .A(n1841), .Y(n3665) );
AOI222X1TS U3926 ( .A0(n3683), .A1(n3921), .B0(n3688), .B1(n2539), .C0(n3687), .C1(n3222), .Y(n1842) );
XOR2X1TS U3927 ( .A(n1843), .B(n3692), .Y(Sgf_operation_mult_x_1_n3927) );
AOI222X1TS U3928 ( .A0(n3665), .A1(n2397), .B0(n3682), .B1(n2396), .C0(n3677), .C1(n3294), .Y(n1844) );
XOR2X1TS U3929 ( .A(n1845), .B(n3692), .Y(Sgf_operation_mult_x_1_n3957) );
XOR2X1TS U3930 ( .A(n1847), .B(n3710), .Y(Sgf_operation_mult_x_1_n3987) );
AOI222X1TS U3931 ( .A0(n3713), .A1(n2397), .B0(n3722), .B1(n2396), .C0(n2751), .C1(n3294), .Y(n1848) );
XOR2X1TS U3932 ( .A(n1849), .B(n3710), .Y(Sgf_operation_mult_x_1_n4013) );
BUFX3TS U3933 ( .A(n2649), .Y(n3158) );
XOR2X1TS U3934 ( .A(n1852), .B(n3814), .Y(Sgf_operation_mult_x_1_n4170) );
XOR2X1TS U3935 ( .A(n1854), .B(n3586), .Y(Sgf_operation_mult_x_1_n3727) );
XOR2X1TS U3936 ( .A(n1856), .B(n3762), .Y(Sgf_operation_mult_x_1_n4097) );
OAI21X1TS U3937 ( .A0(n3960), .A1(n3140), .B0(n1857), .Y(n1858) );
XOR2X1TS U3938 ( .A(n1858), .B(n3685), .Y(Sgf_operation_mult_x_1_n3945) );
AOI222X1TS U3939 ( .A0(n3773), .A1(n2397), .B0(n3779), .B1(n2396), .C0(n3764), .C1(n4115), .Y(n1859) );
XOR2X1TS U3940 ( .A(n1860), .B(n3762), .Y(Sgf_operation_mult_x_1_n4125) );
XOR2X1TS U3941 ( .A(n1862), .B(n3404), .Y(Sgf_operation_mult_x_1_n3924) );
XOR2X1TS U3942 ( .A(n1864), .B(n3586), .Y(Sgf_operation_mult_x_1_n3724) );
XOR2X1TS U3943 ( .A(n1866), .B(n3634), .Y(Sgf_operation_mult_x_1_n3839) );
AOI222X1TS U3944 ( .A0(n3788), .A1(n4115), .B0(n3810), .B1(n4114), .C0(n3803), .C1(n3717), .Y(n1867) );
XOR2X1TS U3945 ( .A(n1868), .B(n3814), .Y(Sgf_operation_mult_x_1_n4183) );
AOI222X1TS U3946 ( .A0(n3750), .A1(n3923), .B0(n3728), .B1(n3922), .C0(n3748), .C1(n2956), .Y(n1869) );
XOR2X1TS U3947 ( .A(n1870), .B(n3424), .Y(Sgf_operation_mult_x_1_n4037) );
BUFX4TS U3948 ( .A(n3875), .Y(n3864) );
AOI222X1TS U3949 ( .A0(n4031), .A1(n3921), .B0(n4027), .B1(n2539), .C0(n3867), .C1(n3222), .Y(n1871) );
XOR2X1TS U3950 ( .A(n1872), .B(n3881), .Y(Sgf_operation_mult_x_1_n4263) );
AOI222X1TS U3951 ( .A0(n3523), .A1(n3953), .B0(n3522), .B1(n3952), .C0(n3518), .C1(n3008), .Y(n1873) );
XOR2X1TS U3952 ( .A(n1874), .B(n3344), .Y(Sgf_operation_mult_x_1_n3610) );
XOR2X1TS U3953 ( .A(n1876), .B(n3783), .Y(Sgf_operation_mult_x_1_n4117) );
AOI222X1TS U3954 ( .A0(n3683), .A1(n3923), .B0(n2746), .B1(n3922), .C0(n3687), .C1(n2956), .Y(n1877) );
XOR2X1TS U3955 ( .A(n1878), .B(n3404), .Y(Sgf_operation_mult_x_1_n3925) );
BUFX4TS U3956 ( .A(n1879), .Y(n4130) );
AOI222X1TS U3957 ( .A0(n4134), .A1(n3990), .B0(n4130), .B1(n1912), .C0(n3951), .C1(n2397), .Y(n1880) );
XOR2X1TS U3958 ( .A(n1881), .B(n4170), .Y(Sgf_operation_mult_x_1_n4403) );
AOI222X1TS U3959 ( .A0(n3843), .A1(n3990), .B0(n3835), .B1(n1912), .C0(n3128), .C1(n2397), .Y(n1882) );
XOR2X1TS U3960 ( .A(n1883), .B(n3837), .Y(Sgf_operation_mult_x_1_n4235) );
XOR2X1TS U3961 ( .A(n1885), .B(n3753), .Y(Sgf_operation_mult_x_1_n4041) );
AOI222X1TS U3962 ( .A0(n3599), .A1(n3967), .B0(n3616), .B1(n3966), .C0(n3615), .C1(n3017), .Y(n1886) );
XOR2X1TS U3963 ( .A(n1887), .B(n3620), .Y(Sgf_operation_mult_x_1_n3780) );
XOR2X1TS U3964 ( .A(n1889), .B(n3881), .Y(Sgf_operation_mult_x_1_n4294) );
AOI222X1TS U3965 ( .A0(n3584), .A1(n4115), .B0(n3583), .B1(n4114), .C0(n3582), .C1(n3717), .Y(n1890) );
XOR2X1TS U3966 ( .A(n1891), .B(n3586), .Y(Sgf_operation_mult_x_1_n3736) );
AOI222X1TS U3967 ( .A0(n3729), .A1(n3907), .B0(n3728), .B1(n3906), .C0(n3739), .C1(n3199), .Y(n1892) );
XOR2X1TS U3968 ( .A(n1893), .B(n3424), .Y(Sgf_operation_mult_x_1_n4033) );
AOI222X1TS U3969 ( .A0(n3820), .A1(n3912), .B0(n3129), .B1(n3911), .C0(n3827), .C1(n3923), .Y(n1894) );
XOR2X1TS U3970 ( .A(n1895), .B(n2661), .Y(Sgf_operation_mult_x_1_n4203) );
AOI222X1TS U3971 ( .A0(n3729), .A1(n2654), .B0(n3728), .B1(n2653), .C0(n3748), .C1(n2946), .Y(n1896) );
XOR2X1TS U3972 ( .A(n1897), .B(n3424), .Y(Sgf_operation_mult_x_1_n4031) );
XOR2X1TS U3973 ( .A(n1899), .B(n2344), .Y(Sgf_operation_mult_x_1_n3666) );
AOI222X1TS U3974 ( .A0(n4031), .A1(n3907), .B0(n4027), .B1(n3906), .C0(n3873), .C1(n3199), .Y(n1900) );
XOR2X1TS U3975 ( .A(n1901), .B(n4094), .Y(Sgf_operation_mult_x_1_n4257) );
XOR2X1TS U3976 ( .A(n1903), .B(n3710), .Y(Sgf_operation_mult_x_1_n3989) );
XOR2X1TS U3977 ( .A(n1905), .B(n3557), .Y(Sgf_operation_mult_x_1_n3667) );
XOR2X1TS U3978 ( .A(n1907), .B(n3653), .Y(Sgf_operation_mult_x_1_n3879) );
OAI21X1TS U3979 ( .A0(n3232), .A1(n3752), .B0(n1908), .Y(n1909) );
XOR2X1TS U3980 ( .A(n1909), .B(n3753), .Y(Sgf_operation_mult_x_1_n4045) );
AOI222X1TS U3981 ( .A0(n2424), .A1(n3923), .B0(n3768), .B1(n3922), .C0(n3764), .C1(n3921), .Y(n1910) );
XOR2X1TS U3982 ( .A(n1911), .B(n2799), .Y(Sgf_operation_mult_x_1_n4093) );
AOI222X1TS U3983 ( .A0(n3638), .A1(n3990), .B0(n3637), .B1(n1912), .C0(n3636), .C1(n3289), .Y(n1913) );
XOR2X1TS U3984 ( .A(n1914), .B(n3641), .Y(Sgf_operation_mult_x_1_n3843) );
AOI222X1TS U3985 ( .A0(n3723), .A1(n2508), .B0(n3712), .B1(n2507), .C0(n3721), .C1(n3201), .Y(n1915) );
XOR2X1TS U3986 ( .A(n1916), .B(n2761), .Y(Sgf_operation_mult_x_1_n3978) );
XOR2X1TS U3987 ( .A(n1918), .B(n2761), .Y(Sgf_operation_mult_x_1_n3998) );
XOR2X1TS U3988 ( .A(n1920), .B(n3444), .Y(Sgf_operation_mult_x_1_n4168) );
AOI222X1TS U3989 ( .A0(n3780), .A1(n2607), .B0(n3768), .B1(n2462), .C0(n3778), .C1(n2508), .Y(n1921) );
XOR2X1TS U3990 ( .A(n1922), .B(n2799), .Y(Sgf_operation_mult_x_1_n4088) );
OAI21X1TS U3991 ( .A0(n3988), .A1(n3580), .B0(n1923), .Y(n1924) );
XOR2X1TS U3992 ( .A(n1924), .B(n3586), .Y(Sgf_operation_mult_x_1_n3728) );
AOI222X1TS U3993 ( .A0(n3788), .A1(n2397), .B0(n3804), .B1(n2396), .C0(n3803), .C1(n3294), .Y(n1925) );
XOR2X1TS U3994 ( .A(n1926), .B(n3801), .Y(Sgf_operation_mult_x_1_n4181) );
AOI222X1TS U3995 ( .A0(n3455), .A1(n2397), .B0(n3472), .B1(n2396), .C0(n3471), .C1(n3294), .Y(n1927) );
XOR2X1TS U3996 ( .A(n1928), .B(n3476), .Y(Sgf_operation_mult_x_1_n3512) );
OAI21X1TS U3997 ( .A0(n3988), .A1(n3076), .B0(n1929), .Y(n1930) );
XOR2X1TS U3998 ( .A(n1930), .B(n3746), .Y(Sgf_operation_mult_x_1_n4063) );
XOR2X1TS U3999 ( .A(n1932), .B(n3525), .Y(Sgf_operation_mult_x_1_n3611) );
XOR2X1TS U4000 ( .A(n1934), .B(n2344), .Y(Sgf_operation_mult_x_1_n3664) );
AOI21X1TS U4001 ( .A0(n4104), .A1(n4047), .B0(n4098), .Y(n1935) );
XOR2X1TS U4002 ( .A(n1936), .B(n4145), .Y(Sgf_operation_mult_x_1_n4305) );
OAI21X1TS U4003 ( .A0(n641), .A1(n3140), .B0(n1937), .Y(n1938) );
XOR2X1TS U4004 ( .A(n1938), .B(n3685), .Y(Sgf_operation_mult_x_1_n3946) );
OAI21X1TS U4005 ( .A0(n639), .A1(n3122), .B0(n1939), .Y(n1940) );
XOR2X1TS U4006 ( .A(n1940), .B(n3634), .Y(Sgf_operation_mult_x_1_n3836) );
AOI21X1TS U4007 ( .A0(n1943), .A1(n1942), .B0(n1941), .Y(n1947) );
NAND2X1TS U4008 ( .A(n1945), .B(n1944), .Y(n1946) );
XNOR2X1TS U4009 ( .A(n1947), .B(n1946), .Y(n1996) );
BUFX4TS U4010 ( .A(Op_MY[9]), .Y(n4001) );
AOI222X1TS U4011 ( .A0(n3811), .A1(n4002), .B0(n3804), .B1(n4001), .C0(n3809), .C1(n3877), .Y(n1948) );
XOR2X1TS U4012 ( .A(n1949), .B(n3801), .Y(Sgf_operation_mult_x_1_n4180) );
XOR2X1TS U4013 ( .A(n1951), .B(n3641), .Y(Sgf_operation_mult_x_1_n3823) );
OAI21X1TS U4014 ( .A0(n637), .A1(n3281), .B0(n1952), .Y(n1953) );
XOR2X1TS U4015 ( .A(n1953), .B(n3282), .Y(Sgf_operation_mult_x_1_n3505) );
XOR2X1TS U4016 ( .A(n1955), .B(n2661), .Y(Sgf_operation_mult_x_1_n4224) );
AOI222X1TS U4017 ( .A0(n3843), .A1(n3907), .B0(n3129), .B1(n3906), .C0(n3128), .C1(n3912), .Y(n1956) );
XOR2X1TS U4018 ( .A(n1957), .B(n2661), .Y(Sgf_operation_mult_x_1_n4201) );
XOR2X1TS U4019 ( .A(n1959), .B(n3710), .Y(Sgf_operation_mult_x_1_n3991) );
XOR2X1TS U4020 ( .A(n1961), .B(n4170), .Y(Sgf_operation_mult_x_1_n4379) );
AOI222X1TS U4021 ( .A0(n3820), .A1(n2397), .B0(n3835), .B1(n2396), .C0(n3128), .C1(n4115), .Y(n1962) );
XOR2X1TS U4022 ( .A(n1963), .B(n3837), .Y(Sgf_operation_mult_x_1_n4237) );
XOR2X1TS U4023 ( .A(n1965), .B(n3846), .Y(Sgf_operation_mult_x_1_n4233) );
XOR2X1TS U4024 ( .A(n1967), .B(n3692), .Y(Sgf_operation_mult_x_1_n3933) );
XOR2X1TS U4025 ( .A(n1969), .B(n3504), .Y(Sgf_operation_mult_x_1_n3560) );
XOR2X1TS U4026 ( .A(n1971), .B(n3663), .Y(Sgf_operation_mult_x_1_n3892) );
XOR2X1TS U4027 ( .A(n1973), .B(n3634), .Y(Sgf_operation_mult_x_1_n3833) );
XOR2X1TS U4028 ( .A(n1975), .B(n3753), .Y(Sgf_operation_mult_x_1_n4043) );
AOI222X1TS U4029 ( .A0(n3638), .A1(n2397), .B0(n3631), .B1(n2396), .C0(n3636), .C1(n3294), .Y(n1976) );
XOR2X1TS U4030 ( .A(n1977), .B(n3641), .Y(Sgf_operation_mult_x_1_n3845) );
AOI222X1TS U4031 ( .A0(n3805), .A1(n3912), .B0(n3151), .B1(n3911), .C0(n3803), .C1(n2954), .Y(n1978) );
XOR2X1TS U4032 ( .A(n1979), .B(n3444), .Y(Sgf_operation_mult_x_1_n4147) );
AOI222X1TS U4033 ( .A0(n3998), .A1(n3859), .B0(n3937), .B1(n3858), .C0(n4163), .C1(n3929), .Y(n1981) );
XOR2X1TS U4034 ( .A(n1982), .B(n4170), .Y(Sgf_operation_mult_x_1_n4382) );
AOI222X1TS U4035 ( .A0(n3659), .A1(n3819), .B0(n3650), .B1(n3818), .C0(n3657), .C1(n3787), .Y(n1983) );
XOR2X1TS U4036 ( .A(n1985), .B(n3653), .Y(Sgf_operation_mult_x_1_n3872) );
AOI222X1TS U4037 ( .A0(n3805), .A1(n3907), .B0(n3151), .B1(n3906), .C0(n3803), .C1(n3199), .Y(n1986) );
XOR2X1TS U4038 ( .A(n1987), .B(n3444), .Y(Sgf_operation_mult_x_1_n4145) );
XOR2X1TS U4039 ( .A(n1989), .B(n3814), .Y(Sgf_operation_mult_x_1_n4169) );
AOI222X1TS U4040 ( .A0(n3750), .A1(n3921), .B0(n3749), .B1(n2539), .C0(n3742), .C1(n3222), .Y(n1990) );
XOR2X1TS U4041 ( .A(n1991), .B(n3753), .Y(Sgf_operation_mult_x_1_n4039) );
AOI21X1TS U4042 ( .A0(n3873), .A1(n4053), .B0(n4027), .Y(n1992) );
XOR2X1TS U4043 ( .A(n1993), .B(n4094), .Y(Sgf_operation_mult_x_1_n4249) );
AOI222X1TS U4044 ( .A0(n2424), .A1(n2728), .B0(n3768), .B1(n2752), .C0(n3778), .C1(n2713), .Y(n1994) );
XOR2X1TS U4045 ( .A(n1995), .B(n2799), .Y(Sgf_operation_mult_x_1_n4084) );
AOI222X1TS U4046 ( .A0(n3501), .A1(n4002), .B0(n3489), .B1(n4001), .C0(n3499), .C1(n3877), .Y(n1997) );
XOR2X1TS U4047 ( .A(n1998), .B(n3491), .Y(Sgf_operation_mult_x_1_n3567) );
AOI222X1TS U4048 ( .A0(n2695), .A1(n2397), .B0(n3658), .B1(n2396), .C0(n2755), .C1(n3294), .Y(n1999) );
XOR2X1TS U4049 ( .A(n2000), .B(n3653), .Y(Sgf_operation_mult_x_1_n3901) );
NAND2X1TS U4050 ( .A(n2001), .B(n2003), .Y(n2006) );
AOI21X1TS U4051 ( .A0(n2004), .A1(n2003), .B0(n2002), .Y(n2005) );
NAND2X1TS U4052 ( .A(n2278), .B(n2008), .Y(n2009) );
BUFX4TS U4053 ( .A(Op_MY[24]), .Y(n3936) );
AOI222X1TS U4054 ( .A0(n3638), .A1(n3938), .B0(n2778), .B1(n3936), .C0(n2777), .C1(n3272), .Y(n2011) );
XOR2X1TS U4055 ( .A(n2012), .B(n3384), .Y(Sgf_operation_mult_x_1_n3829) );
AOI222X1TS U4056 ( .A0(n3850), .A1(n3953), .B0(n4035), .B1(n3952), .C0(n3873), .C1(n3008), .Y(n2013) );
XOR2X1TS U4057 ( .A(n2014), .B(n4094), .Y(Sgf_operation_mult_x_1_n4280) );
AOI222X1TS U4058 ( .A0(n3811), .A1(n3921), .B0(n3151), .B1(n2539), .C0(n3156), .C1(n3222), .Y(n2015) );
XOR2X1TS U4059 ( .A(n2016), .B(n3801), .Y(Sgf_operation_mult_x_1_n4151) );
AOI222X1TS U4060 ( .A0(n3610), .A1(n3912), .B0(n3605), .B1(n3911), .C0(n2663), .C1(n2954), .Y(n2017) );
XOR2X1TS U4061 ( .A(n2018), .B(n2666), .Y(Sgf_operation_mult_x_1_n3756) );
AOI222X1TS U4062 ( .A0(n3523), .A1(n2643), .B0(n3528), .B1(n2429), .C0(n3521), .C1(n2981), .Y(n2019) );
XOR2X1TS U4063 ( .A(n2020), .B(n3532), .Y(Sgf_operation_mult_x_1_n3601) );
BUFX4TS U4064 ( .A(n2623), .Y(n3955) );
AOI222X1TS U4065 ( .A0(n4167), .A1(n2654), .B0(n4165), .B1(n2653), .C0(n3995), .C1(n3907), .Y(n2021) );
XOR2X1TS U4066 ( .A(n2022), .B(n5152), .Y(Sgf_operation_mult_x_1_n4367) );
AOI222X1TS U4067 ( .A0(n2424), .A1(n2654), .B0(n3768), .B1(n2653), .C0(n3778), .C1(n3907), .Y(n2023) );
XOR2X1TS U4068 ( .A(n2024), .B(n2799), .Y(Sgf_operation_mult_x_1_n4087) );
XOR2X1TS U4069 ( .A(n2026), .B(n2799), .Y(Sgf_operation_mult_x_1_n4083) );
XOR2X1TS U4070 ( .A(n2028), .B(n3641), .Y(Sgf_operation_mult_x_1_n3817) );
AOI222X1TS U4071 ( .A0(n3780), .A1(n3859), .B0(n3758), .B1(n3858), .C0(n3778), .C1(n3929), .Y(n2029) );
XOR2X1TS U4072 ( .A(n2030), .B(n3762), .Y(Sgf_operation_mult_x_1_n4102) );
XOR2X1TS U4073 ( .A(n2032), .B(n3557), .Y(Sgf_operation_mult_x_1_n3673) );
XOR2X1TS U4074 ( .A(n2034), .B(n3586), .Y(Sgf_operation_mult_x_1_n3723) );
OAI21X1TS U4075 ( .A0(n636), .A1(n2796), .B0(n2035), .Y(n2036) );
XOR2X1TS U4076 ( .A(n2036), .B(n4145), .Y(Sgf_operation_mult_x_1_n4336) );
XOR2X1TS U4077 ( .A(n2038), .B(n3653), .Y(Sgf_operation_mult_x_1_n3875) );
AOI222X1TS U4078 ( .A0(n3732), .A1(n4115), .B0(n3743), .B1(n4114), .C0(n3742), .C1(n3717), .Y(n2039) );
XOR2X1TS U4079 ( .A(n2040), .B(n3746), .Y(Sgf_operation_mult_x_1_n4071) );
XOR2X1TS U4080 ( .A(n2042), .B(n4039), .Y(Sgf_operation_mult_x_1_n4296) );
AOI222X1TS U4081 ( .A0(n2695), .A1(n3921), .B0(n3650), .B1(n2539), .C0(n2755), .C1(n3222), .Y(n2043) );
XOR2X1TS U4082 ( .A(n2044), .B(n3653), .Y(Sgf_operation_mult_x_1_n3871) );
AOI222X1TS U4083 ( .A0(n3780), .A1(n3921), .B0(n3758), .B1(n2539), .C0(n3764), .C1(n2474), .Y(n2045) );
XOR2X1TS U4084 ( .A(n2046), .B(n3762), .Y(Sgf_operation_mult_x_1_n4095) );
AOI222X1TS U4085 ( .A0(n3622), .A1(n2607), .B0(n2778), .B1(n2462), .C0(n2777), .C1(n3184), .Y(n2047) );
XOR2X1TS U4086 ( .A(n2048), .B(n3384), .Y(Sgf_operation_mult_x_1_n3808) );
XOR2X1TS U4087 ( .A(n2050), .B(n3653), .Y(Sgf_operation_mult_x_1_n3877) );
AOI222X1TS U4088 ( .A0(n4031), .A1(n3963), .B0(n4035), .B1(n3962), .C0(n4034), .C1(n3015), .Y(n2051) );
XOR2X1TS U4089 ( .A(n2052), .B(n4039), .Y(Sgf_operation_mult_x_1_n4282) );
INVX4TS U4090 ( .A(n2651), .Y(n3894) );
XOR2X1TS U4091 ( .A(n2054), .B(n4109), .Y(Sgf_operation_mult_x_1_n4346) );
BUFX3TS U4092 ( .A(n3850), .Y(n3862) );
AOI222X1TS U4093 ( .A0(n3862), .A1(n2643), .B0(n3878), .B1(n2429), .C0(n3867), .C1(n2981), .Y(n2055) );
XOR2X1TS U4094 ( .A(n2056), .B(n3881), .Y(Sgf_operation_mult_x_1_n4271) );
XOR2X1TS U4095 ( .A(n2058), .B(n4094), .Y(Sgf_operation_mult_x_1_n4251) );
AOI222X1TS U4096 ( .A0(n3713), .A1(n2743), .B0(n3704), .B1(n2742), .C0(n3721), .C1(n3247), .Y(n2059) );
XOR2X1TS U4097 ( .A(n2060), .B(n3710), .Y(Sgf_operation_mult_x_1_n3995) );
XOR2X1TS U4098 ( .A(n2062), .B(n3692), .Y(Sgf_operation_mult_x_1_n3931) );
XOR2X1TS U4099 ( .A(n2064), .B(n3685), .Y(Sgf_operation_mult_x_1_n3943) );
XOR2X1TS U4100 ( .A(n2066), .B(n3881), .Y(Sgf_operation_mult_x_1_n4293) );
AOI222X1TS U4101 ( .A0(n3595), .A1(n3982), .B0(n3616), .B1(n3981), .C0(n3615), .C1(n3034), .Y(n2068) );
XOR2X1TS U4102 ( .A(n2069), .B(n3620), .Y(Sgf_operation_mult_x_1_n3783) );
OAI21X1TS U4103 ( .A0(n636), .A1(n3576), .B0(n2070), .Y(n2071) );
XOR2X1TS U4104 ( .A(n2071), .B(n3364), .Y(Sgf_operation_mult_x_1_n3721) );
AOI222X1TS U4105 ( .A0(n3723), .A1(n4002), .B0(n3704), .B1(n4001), .C0(n3708), .C1(n3877), .Y(n2072) );
XOR2X1TS U4106 ( .A(n2073), .B(n3710), .Y(Sgf_operation_mult_x_1_n4012) );
XOR2X1TS U4107 ( .A(n2075), .B(n3762), .Y(Sgf_operation_mult_x_1_n4099) );
AOI222X1TS U4108 ( .A0(n3805), .A1(n2713), .B0(n3151), .B1(n2712), .C0(n3156), .C1(n2942), .Y(n2076) );
XOR2X1TS U4109 ( .A(n2077), .B(n3444), .Y(Sgf_operation_mult_x_1_n4142) );
XOR2X1TS U4110 ( .A(n2079), .B(n3692), .Y(Sgf_operation_mult_x_1_n3929) );
BUFX3TS U4111 ( .A(n2623), .Y(n4136) );
XOR2X1TS U4112 ( .A(n2082), .B(n4170), .Y(Sgf_operation_mult_x_1_n4380) );
OAI21X1TS U4113 ( .A0(n3978), .A1(n3580), .B0(n2083), .Y(n2084) );
XOR2X1TS U4114 ( .A(n2084), .B(n3586), .Y(Sgf_operation_mult_x_1_n3726) );
OAI21X1TS U4115 ( .A0(n4046), .A1(n4096), .B0(n2085), .Y(n2086) );
XOR2X1TS U4116 ( .A(n2086), .B(n4145), .Y(Sgf_operation_mult_x_1_n4307) );
XOR2X1TS U4117 ( .A(n2088), .B(n3620), .Y(Sgf_operation_mult_x_1_n3779) );
AOI222X1TS U4118 ( .A0(n3535), .A1(n4002), .B0(n3542), .B1(n4001), .C0(n3552), .C1(n3877), .Y(n2089) );
XOR2X1TS U4119 ( .A(n2090), .B(n3548), .Y(Sgf_operation_mult_x_1_n3678) );
XOR2X1TS U4120 ( .A(n2092), .B(n3557), .Y(Sgf_operation_mult_x_1_n3671) );
XOR2X1TS U4121 ( .A(n2094), .B(n4109), .Y(Sgf_operation_mult_x_1_n4344) );
XOR2X1TS U4122 ( .A(n2096), .B(n3814), .Y(Sgf_operation_mult_x_1_n4171) );
AOI222X1TS U4123 ( .A0(n2695), .A1(n3938), .B0(n3643), .B1(n3936), .C0(n2755), .C1(n3272), .Y(n2097) );
XOR2X1TS U4124 ( .A(n2098), .B(n2758), .Y(Sgf_operation_mult_x_1_n3885) );
XOR2X1TS U4125 ( .A(n2100), .B(n3663), .Y(Sgf_operation_mult_x_1_n3898) );
OAI21X1TS U4126 ( .A0(n3969), .A1(n3122), .B0(n2101), .Y(n2102) );
XOR2X1TS U4127 ( .A(n2102), .B(n3634), .Y(Sgf_operation_mult_x_1_n3835) );
AOI222X1TS U4128 ( .A0(n3610), .A1(n3953), .B0(n3605), .B1(n3952), .C0(n2663), .C1(n3008), .Y(n2103) );
XOR2X1TS U4129 ( .A(n2104), .B(n2666), .Y(Sgf_operation_mult_x_1_n3777) );
XOR2X1TS U4130 ( .A(n2106), .B(n3783), .Y(Sgf_operation_mult_x_1_n4115) );
AOI222X1TS U4131 ( .A0(n3665), .A1(n3912), .B0(n2746), .B1(n3911), .C0(n3677), .C1(n2954), .Y(n2107) );
XOR2X1TS U4132 ( .A(n2108), .B(n3404), .Y(Sgf_operation_mult_x_1_n3923) );
AOI222X1TS U4133 ( .A0(n3494), .A1(n3982), .B0(n3500), .B1(n3981), .C0(n3499), .C1(n3034), .Y(n2109) );
XOR2X1TS U4134 ( .A(n2110), .B(n3504), .Y(Sgf_operation_mult_x_1_n3561) );
XOR2X1TS U4135 ( .A(n2112), .B(n4109), .Y(Sgf_operation_mult_x_1_n4343) );
AOI222X1TS U4136 ( .A0(n3696), .A1(n3923), .B0(n3712), .B1(n3922), .C0(n3721), .C1(n2956), .Y(n2113) );
XOR2X1TS U4137 ( .A(n2114), .B(n2761), .Y(Sgf_operation_mult_x_1_n3981) );
AOI222X1TS U4138 ( .A0(n3659), .A1(n3859), .B0(n3650), .B1(n3858), .C0(n3657), .C1(n3857), .Y(n2115) );
XOR2X1TS U4139 ( .A(n2116), .B(n3653), .Y(Sgf_operation_mult_x_1_n3878) );
AOI222X1TS U4140 ( .A0(n4106), .A1(n3859), .B0(n4105), .B1(n3858), .C0(n4104), .C1(n3857), .Y(n2117) );
XOR2X1TS U4141 ( .A(n2118), .B(n3897), .Y(Sgf_operation_mult_x_1_n4326) );
XOR2X1TS U4142 ( .A(n2120), .B(n3593), .Y(Sgf_operation_mult_x_1_n3712) );
XOR2X1TS U4143 ( .A(n2122), .B(n3746), .Y(Sgf_operation_mult_x_1_n4061) );
XOR2X1TS U4144 ( .A(n2124), .B(n3557), .Y(Sgf_operation_mult_x_1_n3669) );
AOI222X1TS U4145 ( .A0(n3843), .A1(n2508), .B0(n3129), .B1(n2507), .C0(n3841), .C1(n3918), .Y(n2125) );
XOR2X1TS U4146 ( .A(n2126), .B(n2661), .Y(Sgf_operation_mult_x_1_n4202) );
OAI21X1TS U4147 ( .A0(n2973), .A1(n4096), .B0(n2127), .Y(n2128) );
XOR2X1TS U4148 ( .A(n2128), .B(n3897), .Y(Sgf_operation_mult_x_1_n4327) );
AOI222X1TS U4149 ( .A0(n3723), .A1(n3938), .B0(n3712), .B1(n3936), .C0(n3721), .C1(n3272), .Y(n2129) );
XOR2X1TS U4150 ( .A(n2130), .B(n2761), .Y(Sgf_operation_mult_x_1_n3997) );
AOI222X1TS U4151 ( .A0(n3862), .A1(n3967), .B0(n4035), .B1(n3966), .C0(n4034), .C1(n3017), .Y(n2131) );
XOR2X1TS U4152 ( .A(n2132), .B(n4039), .Y(Sgf_operation_mult_x_1_n4283) );
XOR2X1TS U4153 ( .A(n2134), .B(n3726), .Y(Sgf_operation_mult_x_1_n4007) );
AOI222X1TS U4154 ( .A0(n3811), .A1(n2508), .B0(n3151), .B1(n2507), .C0(n3809), .C1(n3201), .Y(n2135) );
XOR2X1TS U4155 ( .A(n2136), .B(n3444), .Y(Sgf_operation_mult_x_1_n4146) );
AOI222X1TS U4156 ( .A0(n3622), .A1(n2508), .B0(n2778), .B1(n2507), .C0(n2777), .C1(n3201), .Y(n2137) );
XOR2X1TS U4157 ( .A(n2138), .B(n3384), .Y(Sgf_operation_mult_x_1_n3810) );
AOI222X1TS U4158 ( .A0(n3729), .A1(n2743), .B0(n3749), .B1(n2742), .C0(n3748), .C1(n3247), .Y(n2139) );
XOR2X1TS U4159 ( .A(n2140), .B(n3753), .Y(Sgf_operation_mult_x_1_n4051) );
AOI222X1TS U4160 ( .A0(n4106), .A1(n3264), .B0(n4105), .B1(n3263), .C0(n3894), .C1(n3262), .Y(n2141) );
XOR2X1TS U4161 ( .A(n2142), .B(n3897), .Y(Sgf_operation_mult_x_1_n4329) );
XOR2X1TS U4162 ( .A(n2144), .B(n3384), .Y(Sgf_operation_mult_x_1_n3832) );
XOR2X1TS U4163 ( .A(n2146), .B(n3603), .Y(Sgf_operation_mult_x_1_n3770) );
AOI21X1TS U4164 ( .A0(n2149), .A1(n2148), .B0(n2147), .Y(n2153) );
NAND2X1TS U4165 ( .A(n2151), .B(n2150), .Y(n2152) );
XOR2X1TS U4166 ( .A(n2153), .B(n2152), .Y(n2154) );
BUFX4TS U4167 ( .A(Op_MY[27]), .Y(n3868) );
AOI222X1TS U4168 ( .A0(n3638), .A1(n3927), .B0(n3631), .B1(n3868), .C0(n3630), .C1(n3866), .Y(n2155) );
XOR2X1TS U4169 ( .A(n2156), .B(n3641), .Y(Sgf_operation_mult_x_1_n3826) );
OAI21X1TS U4170 ( .A0(n637), .A1(n3076), .B0(n2157), .Y(n2158) );
XOR2X1TS U4171 ( .A(n2158), .B(n3746), .Y(Sgf_operation_mult_x_1_n4062) );
AOI222X1TS U4172 ( .A0(n3584), .A1(n3264), .B0(n3589), .B1(n3263), .C0(n3588), .C1(n3262), .Y(n2159) );
XOR2X1TS U4173 ( .A(n2160), .B(n3593), .Y(Sgf_operation_mult_x_1_n3714) );
AOI222X1TS U4174 ( .A0(n3455), .A1(n4166), .B0(n3279), .B1(n4164), .C0(n3471), .C1(n3720), .Y(n2161) );
XOR2X1TS U4175 ( .A(n2162), .B(n3282), .Y(Sgf_operation_mult_x_1_n3515) );
OAI21X1TS U4176 ( .A0(n641), .A1(n3076), .B0(n2163), .Y(n2164) );
XOR2X1TS U4177 ( .A(n2164), .B(n3746), .Y(Sgf_operation_mult_x_1_n4058) );
AOI222X1TS U4178 ( .A0(n1452), .A1(n2743), .B0(n3542), .B1(n2742), .C0(n3546), .C1(n3247), .Y(n2165) );
XOR2X1TS U4179 ( .A(n2166), .B(n3548), .Y(Sgf_operation_mult_x_1_n3661) );
XOR2X1TS U4180 ( .A(n2168), .B(n3525), .Y(Sgf_operation_mult_x_1_n3614) );
AOI222X1TS U4181 ( .A0(n3665), .A1(n4166), .B0(n3682), .B1(n4164), .C0(n3677), .C1(n3720), .Y(n2169) );
XOR2X1TS U4182 ( .A(n2170), .B(n3685), .Y(Sgf_operation_mult_x_1_n3960) );
AOI222X1TS U4183 ( .A0(n4031), .A1(n2607), .B0(n4027), .B1(n2462), .C0(n3873), .C1(n3184), .Y(n2171) );
XOR2X1TS U4184 ( .A(n2172), .B(n4094), .Y(Sgf_operation_mult_x_1_n4256) );
XOR2X1TS U4185 ( .A(n2174), .B(n2666), .Y(Sgf_operation_mult_x_1_n3774) );
XOR2X1TS U4186 ( .A(n2176), .B(n4109), .Y(Sgf_operation_mult_x_1_n4345) );
AOI222X1TS U4187 ( .A0(n2424), .A1(n2508), .B0(n3768), .B1(n2507), .C0(n3778), .C1(n3918), .Y(n2177) );
XOR2X1TS U4188 ( .A(n2178), .B(n2799), .Y(Sgf_operation_mult_x_1_n4090) );
AOI222X1TS U4189 ( .A0(n2424), .A1(n3235), .B0(n3768), .B1(n3234), .C0(n3772), .C1(n2654), .Y(n2179) );
XOR2X1TS U4190 ( .A(n2180), .B(n2799), .Y(Sgf_operation_mult_x_1_n4085) );
AOI222X1TS U4191 ( .A0(n2695), .A1(n2743), .B0(n3650), .B1(n2742), .C0(n2755), .C1(n3247), .Y(n2181) );
XOR2X1TS U4192 ( .A(n2182), .B(n3653), .Y(Sgf_operation_mult_x_1_n3883) );
AOI222X1TS U4193 ( .A0(n3696), .A1(n3885), .B0(n3704), .B1(n3884), .C0(n3708), .C1(n3883), .Y(n2184) );
XOR2X1TS U4194 ( .A(n2185), .B(n3710), .Y(Sgf_operation_mult_x_1_n3986) );
OAI21X1TS U4195 ( .A0(n3662), .A1(n3531), .B0(n2186), .Y(n2187) );
XOR2X1TS U4196 ( .A(n2187), .B(n3525), .Y(Sgf_operation_mult_x_1_n3626) );
AOI222X1TS U4197 ( .A0(n3494), .A1(n3972), .B0(n3500), .B1(n3971), .C0(n3499), .C1(n3012), .Y(n2188) );
XOR2X1TS U4198 ( .A(n2189), .B(n3504), .Y(Sgf_operation_mult_x_1_n3559) );
XOR2X1TS U4199 ( .A(n2191), .B(n3282), .Y(Sgf_operation_mult_x_1_n3502) );
OAI21X1TS U4200 ( .A0(n631), .A1(n2734), .B0(n2192), .Y(n2193) );
XOR2X1TS U4201 ( .A(n2193), .B(n3753), .Y(Sgf_operation_mult_x_1_n4042) );
XOR2X1TS U4202 ( .A(n2195), .B(n3634), .Y(Sgf_operation_mult_x_1_n3831) );
XOR2X1TS U4203 ( .A(n2197), .B(n4094), .Y(Sgf_operation_mult_x_1_n4277) );
XOR2X1TS U4204 ( .A(n2199), .B(n3525), .Y(Sgf_operation_mult_x_1_n3616) );
OAI21X1TS U4205 ( .A0(n3960), .A1(n4038), .B0(n2200), .Y(n2201) );
XOR2X1TS U4206 ( .A(n2201), .B(n4039), .Y(Sgf_operation_mult_x_1_n4281) );
XOR2X1TS U4207 ( .A(n2203), .B(n4039), .Y(Sgf_operation_mult_x_1_n4284) );
AOI222X1TS U4208 ( .A0(n4031), .A1(n2654), .B0(n4027), .B1(n2653), .C0(n3873), .C1(n2946), .Y(n2204) );
XOR2X1TS U4209 ( .A(n2205), .B(n4094), .Y(Sgf_operation_mult_x_1_n4255) );
XOR2X1TS U4210 ( .A(n2207), .B(n3762), .Y(Sgf_operation_mult_x_1_n4100) );
XOR2X1TS U4211 ( .A(n2209), .B(n3525), .Y(Sgf_operation_mult_x_1_n3609) );
OAI21X1TS U4212 ( .A0(n2961), .A1(n3544), .B0(n2210), .Y(n2211) );
XOR2X1TS U4213 ( .A(n2211), .B(n3548), .Y(Sgf_operation_mult_x_1_n3651) );
AOI222X1TS U4214 ( .A0(n3683), .A1(n3938), .B0(n2746), .B1(n3936), .C0(n3687), .C1(n3272), .Y(n2212) );
XOR2X1TS U4215 ( .A(n2213), .B(n3404), .Y(Sgf_operation_mult_x_1_n3941) );
AOI222X1TS U4216 ( .A0(n3729), .A1(n3859), .B0(n3749), .B1(n3858), .C0(n3748), .C1(n3857), .Y(n2214) );
XOR2X1TS U4217 ( .A(n2215), .B(n3753), .Y(Sgf_operation_mult_x_1_n4046) );
XOR2X1TS U4218 ( .A(n2217), .B(n3746), .Y(Sgf_operation_mult_x_1_n4064) );
OAI21X1TS U4219 ( .A0(n630), .A1(n3782), .B0(n2219), .Y(n2220) );
XOR2X1TS U4220 ( .A(n2220), .B(n3762), .Y(Sgf_operation_mult_x_1_n4094) );
AOI222X1TS U4221 ( .A0(n3523), .A1(n3890), .B0(n3528), .B1(n3889), .C0(n3521), .C1(n3888), .Y(n2221) );
XOR2X1TS U4222 ( .A(n2222), .B(n3532), .Y(Sgf_operation_mult_x_1_n3598) );
OAI21X1TS U4223 ( .A0(n637), .A1(n3715), .B0(n2223), .Y(n2224) );
XOR2X1TS U4224 ( .A(n2224), .B(n3726), .Y(Sgf_operation_mult_x_1_n4006) );
XOR2X1TS U4225 ( .A(n2226), .B(n3525), .Y(Sgf_operation_mult_x_1_n3613) );
AOI222X1TS U4226 ( .A0(n4167), .A1(n3885), .B0(n3937), .B1(n3884), .C0(n3995), .C1(n3890), .Y(n2227) );
XOR2X1TS U4227 ( .A(n2228), .B(n4170), .Y(Sgf_operation_mult_x_1_n4378) );
AOI222X1TS U4228 ( .A0(n3610), .A1(n3923), .B0(n3605), .B1(n3922), .C0(n2663), .C1(n2956), .Y(n2229) );
XOR2X1TS U4229 ( .A(n2230), .B(n2666), .Y(Sgf_operation_mult_x_1_n3758) );
AOI222X1TS U4230 ( .A0(n3651), .A1(n3890), .B0(n3650), .B1(n3889), .C0(n3657), .C1(n3888), .Y(n2231) );
XOR2X1TS U4231 ( .A(n2232), .B(n3653), .Y(Sgf_operation_mult_x_1_n3876) );
AOI222X1TS U4232 ( .A0(n3750), .A1(n3235), .B0(n3728), .B1(n3234), .C0(n3742), .C1(n3233), .Y(n2233) );
XOR2X1TS U4233 ( .A(n2234), .B(n3424), .Y(Sgf_operation_mult_x_1_n4029) );
AOI222X1TS U4234 ( .A0(n3622), .A1(n3923), .B0(n2778), .B1(n3922), .C0(n2777), .C1(n2956), .Y(n2235) );
XOR2X1TS U4235 ( .A(n2236), .B(n3384), .Y(Sgf_operation_mult_x_1_n3813) );
XOR2X1TS U4236 ( .A(n2238), .B(n3557), .Y(Sgf_operation_mult_x_1_n3672) );
XOR2X1TS U4237 ( .A(n2240), .B(n3641), .Y(Sgf_operation_mult_x_1_n3822) );
XOR2X1TS U4238 ( .A(n2242), .B(n2758), .Y(Sgf_operation_mult_x_1_n3886) );
AOI222X1TS U4239 ( .A0(n4031), .A1(n3235), .B0(n4027), .B1(n3234), .C0(n3873), .C1(n3233), .Y(n2243) );
XOR2X1TS U4240 ( .A(n2244), .B(n4094), .Y(Sgf_operation_mult_x_1_n4253) );
AOI222X1TS U4241 ( .A0(n3788), .A1(n4166), .B0(n3810), .B1(n4164), .C0(n3803), .C1(n3720), .Y(n2245) );
XOR2X1TS U4242 ( .A(n2246), .B(n3814), .Y(Sgf_operation_mult_x_1_n4184) );
AOI222X1TS U4243 ( .A0(n3584), .A1(n2743), .B0(n3589), .B1(n2742), .C0(n3574), .C1(n3247), .Y(n2247) );
XOR2X1TS U4244 ( .A(n2248), .B(n3593), .Y(Sgf_operation_mult_x_1_n3716) );
XOR2X1TS U4245 ( .A(n2250), .B(n3663), .Y(Sgf_operation_mult_x_1_n3893) );
XOR2X1TS U4246 ( .A(n2252), .B(n3557), .Y(Sgf_operation_mult_x_1_n3665) );
XOR2X1TS U4247 ( .A(n2254), .B(n3634), .Y(Sgf_operation_mult_x_1_n3834) );
AOI222X1TS U4248 ( .A0(n3811), .A1(n3235), .B0(n3151), .B1(n3234), .C0(n3809), .C1(n3233), .Y(n2255) );
XOR2X1TS U4249 ( .A(n2256), .B(n3444), .Y(Sgf_operation_mult_x_1_n4141) );
XOR2X1TS U4250 ( .A(n2258), .B(n3814), .Y(Sgf_operation_mult_x_1_n4175) );
XOR2X1TS U4251 ( .A(n2260), .B(n3557), .Y(Sgf_operation_mult_x_1_n3675) );
AOI222X1TS U4252 ( .A0(n3901), .A1(n2607), .B0(n4098), .B1(n2462), .C0(n3894), .C1(n3184), .Y(n2261) );
XOR2X1TS U4253 ( .A(n2262), .B(n4145), .Y(Sgf_operation_mult_x_1_n4312) );
AOI222X1TS U4254 ( .A0(n4106), .A1(n2654), .B0(n4098), .B1(n2653), .C0(n4104), .C1(n2946), .Y(n2263) );
XOR2X1TS U4255 ( .A(n2264), .B(n4145), .Y(Sgf_operation_mult_x_1_n4311) );
AOI222X1TS U4256 ( .A0(n4167), .A1(n2607), .B0(n4165), .B1(n2462), .C0(n3995), .C1(n2508), .Y(n2265) );
XOR2X1TS U4257 ( .A(n2266), .B(n5152), .Y(Sgf_operation_mult_x_1_n4368) );
XOR2X1TS U4258 ( .A(n2268), .B(n3603), .Y(Sgf_operation_mult_x_1_n3772) );
AOI222X1TS U4259 ( .A0(n3843), .A1(n2607), .B0(n3129), .B1(n2462), .C0(n3841), .C1(n2508), .Y(n2269) );
XOR2X1TS U4260 ( .A(n2270), .B(n2661), .Y(Sgf_operation_mult_x_1_n4200) );
XOR2X1TS U4261 ( .A(n2272), .B(n3846), .Y(Sgf_operation_mult_x_1_n4232) );
XOR2X1TS U4262 ( .A(n2274), .B(n3814), .Y(Sgf_operation_mult_x_1_n4172) );
OAI21X1TS U4263 ( .A0(n3232), .A1(n4096), .B0(n2275), .Y(n2276) );
XOR2X1TS U4264 ( .A(n2276), .B(n3897), .Y(Sgf_operation_mult_x_1_n4325) );
AOI21X1TS U4265 ( .A0(n2279), .A1(n2278), .B0(n2277), .Y(n2283) );
NAND2X1TS U4266 ( .A(n2281), .B(n2280), .Y(n2282) );
XNOR2X1TS U4267 ( .A(n2283), .B(n2282), .Y(n2419) );
BUFX4TS U4268 ( .A(Op_MY[25]), .Y(n3932) );
AOI222X1TS U4269 ( .A0(n3535), .A1(n3933), .B0(n3553), .B1(n3932), .C0(n2342), .C1(n3872), .Y(n2284) );
XOR2X1TS U4270 ( .A(n2285), .B(n3557), .Y(Sgf_operation_mult_x_1_n3662) );
XOR2X1TS U4271 ( .A(n2287), .B(n3685), .Y(Sgf_operation_mult_x_1_n3952) );
AOI222X1TS U4272 ( .A0(n3901), .A1(n3235), .B0(n4098), .B1(n3234), .C0(n3894), .C1(n3233), .Y(n2288) );
XOR2X1TS U4273 ( .A(n2289), .B(n4145), .Y(Sgf_operation_mult_x_1_n4309) );
AOI222X1TS U4274 ( .A0(n3599), .A1(n2474), .B0(n3598), .B1(n2473), .C0(n3609), .C1(n2962), .Y(n2290) );
XOR2X1TS U4275 ( .A(n2291), .B(n3603), .Y(Sgf_operation_mult_x_1_n3762) );
AOI222X1TS U4276 ( .A0(n3659), .A1(n4002), .B0(n3650), .B1(n4001), .C0(n3649), .C1(n3877), .Y(n2292) );
XOR2X1TS U4277 ( .A(n2293), .B(n3653), .Y(Sgf_operation_mult_x_1_n3900) );
AOI222X1TS U4278 ( .A0(n3595), .A1(n3943), .B0(n3605), .B1(n3942), .C0(n2663), .C1(n3024), .Y(n2294) );
XOR2X1TS U4279 ( .A(n2295), .B(n2666), .Y(Sgf_operation_mult_x_1_n3775) );
AOI222X1TS U4280 ( .A0(n3689), .A1(n3927), .B0(n3682), .B1(n3868), .C0(n3681), .C1(n3866), .Y(n2296) );
XOR2X1TS U4281 ( .A(n2297), .B(n3692), .Y(Sgf_operation_mult_x_1_n3938) );
XOR2X1TS U4282 ( .A(n2299), .B(n3837), .Y(Sgf_operation_mult_x_1_n4211) );
XOR2X1TS U4283 ( .A(n2301), .B(n4109), .Y(Sgf_operation_mult_x_1_n4338) );
XOR2X1TS U4284 ( .A(n2303), .B(n3525), .Y(Sgf_operation_mult_x_1_n3612) );
XOR2X1TS U4285 ( .A(n2305), .B(n3593), .Y(Sgf_operation_mult_x_1_n3708) );
AOI222X1TS U4286 ( .A0(n4031), .A1(n3819), .B0(n3878), .B1(n3818), .C0(n3867), .C1(n3787), .Y(n2307) );
XOR2X1TS U4287 ( .A(n2308), .B(n3881), .Y(Sgf_operation_mult_x_1_n4264) );
AOI222X1TS U4288 ( .A0(n3713), .A1(n3933), .B0(n3722), .B1(n3932), .C0(n3721), .C1(n3872), .Y(n2309) );
XOR2X1TS U4289 ( .A(n2310), .B(n3726), .Y(Sgf_operation_mult_x_1_n3996) );
AOI222X1TS U4290 ( .A0(n3599), .A1(n3885), .B0(n3598), .B1(n3884), .C0(n3609), .C1(n3883), .Y(n2311) );
XOR2X1TS U4291 ( .A(n2312), .B(n3603), .Y(Sgf_operation_mult_x_1_n3763) );
AOI222X1TS U4292 ( .A0(n3659), .A1(n2607), .B0(n3643), .B1(n2462), .C0(n3649), .C1(n3184), .Y(n2313) );
XOR2X1TS U4293 ( .A(n2314), .B(n2758), .Y(Sgf_operation_mult_x_1_n3864) );
XOR2X1TS U4294 ( .A(n2316), .B(n2799), .Y(Sgf_operation_mult_x_1_n4112) );
XOR2X1TS U4295 ( .A(n2318), .B(n3620), .Y(Sgf_operation_mult_x_1_n3781) );
AOI222X1TS U4296 ( .A0(n4101), .A1(n4002), .B0(n3900), .B1(n4001), .C0(n2794), .C1(n3877), .Y(n2319) );
XOR2X1TS U4297 ( .A(n2320), .B(n3897), .Y(Sgf_operation_mult_x_1_n4348) );
OAI21X1TS U4298 ( .A0(n637), .A1(n3770), .B0(n2321), .Y(n2322) );
XOR2X1TS U4299 ( .A(n2322), .B(n3783), .Y(Sgf_operation_mult_x_1_n4118) );
AOI222X1TS U4300 ( .A0(n3732), .A1(n4166), .B0(n3743), .B1(n4164), .C0(n3742), .C1(n3720), .Y(n2323) );
XOR2X1TS U4301 ( .A(n2324), .B(n3746), .Y(Sgf_operation_mult_x_1_n4072) );
AOI222X1TS U4302 ( .A0(n4106), .A1(n2713), .B0(n4098), .B1(n2712), .C0(n3894), .C1(n2942), .Y(n2325) );
XOR2X1TS U4303 ( .A(n2326), .B(n4145), .Y(Sgf_operation_mult_x_1_n4310) );
OAI21X1TS U4304 ( .A0(n2973), .A1(n3544), .B0(n2327), .Y(n2328) );
XOR2X1TS U4305 ( .A(n2328), .B(n3548), .Y(Sgf_operation_mult_x_1_n3657) );
XOR2X1TS U4306 ( .A(n2331), .B(n3586), .Y(Sgf_operation_mult_x_1_n3730) );
AOI222X1TS U4307 ( .A0(n3811), .A1(n2654), .B0(n3151), .B1(n2653), .C0(n3156), .C1(n2946), .Y(n2332) );
XOR2X1TS U4308 ( .A(n2333), .B(n3444), .Y(Sgf_operation_mult_x_1_n4143) );
AOI222X1TS U4309 ( .A0(n3773), .A1(n4002), .B0(n3758), .B1(n4001), .C0(n3764), .C1(n4084), .Y(n2334) );
XOR2X1TS U4310 ( .A(n2335), .B(n3762), .Y(Sgf_operation_mult_x_1_n4124) );
XOR2X1TS U4311 ( .A(n2337), .B(n3726), .Y(Sgf_operation_mult_x_1_n4005) );
XOR2X1TS U4312 ( .A(n2339), .B(n3726), .Y(Sgf_operation_mult_x_1_n4009) );
XOR2X1TS U4313 ( .A(n2341), .B(n3685), .Y(Sgf_operation_mult_x_1_n3947) );
AOI222X1TS U4314 ( .A0(n3535), .A1(n3938), .B0(n3534), .B1(n3936), .C0(n2342), .C1(n3272), .Y(n2343) );
XOR2X1TS U4315 ( .A(n2345), .B(n2344), .Y(Sgf_operation_mult_x_1_n3663) );
OAI21X1TS U4316 ( .A0(n2967), .A1(n2796), .B0(n2346), .Y(n2347) );
XOR2X1TS U4317 ( .A(n2347), .B(n3897), .Y(Sgf_operation_mult_x_1_n4323) );
AOI222X1TS U4318 ( .A0(n3901), .A1(n2743), .B0(n4105), .B1(n2742), .C0(n3894), .C1(n3247), .Y(n2348) );
XOR2X1TS U4319 ( .A(n2349), .B(n3897), .Y(Sgf_operation_mult_x_1_n4331) );
XOR2X1TS U4320 ( .A(n2351), .B(n3746), .Y(Sgf_operation_mult_x_1_n4059) );
XOR2X1TS U4321 ( .A(n2353), .B(n3444), .Y(Sgf_operation_mult_x_1_n4139) );
XOR2X1TS U4322 ( .A(n2355), .B(n3557), .Y(Sgf_operation_mult_x_1_n3670) );
AOI222X1TS U4323 ( .A0(n3665), .A1(n3907), .B0(n2746), .B1(n3906), .C0(n3677), .C1(n3199), .Y(n2356) );
XOR2X1TS U4324 ( .A(n2357), .B(n3404), .Y(Sgf_operation_mult_x_1_n3921) );
AOI222X1TS U4325 ( .A0(n4167), .A1(n3921), .B0(n4130), .B1(n2539), .C0(n3995), .C1(n2474), .Y(n2358) );
XOR2X1TS U4326 ( .A(n2359), .B(n4170), .Y(Sgf_operation_mult_x_1_n4375) );
AOI222X1TS U4327 ( .A0(n3638), .A1(n4166), .B0(n3631), .B1(n4164), .C0(n3636), .C1(n3720), .Y(n2360) );
XOR2X1TS U4328 ( .A(n2361), .B(n3634), .Y(Sgf_operation_mult_x_1_n3848) );
XOR2X1TS U4329 ( .A(n2363), .B(n3532), .Y(Sgf_operation_mult_x_1_n3599) );
AOI222X1TS U4330 ( .A0(n3732), .A1(n2397), .B0(n3743), .B1(n2396), .C0(n3742), .C1(n3294), .Y(n2364) );
XOR2X1TS U4331 ( .A(n2365), .B(n3753), .Y(Sgf_operation_mult_x_1_n4069) );
XOR2X1TS U4332 ( .A(n2367), .B(n3846), .Y(Sgf_operation_mult_x_1_n4228) );
XOR2X1TS U4333 ( .A(n2369), .B(n3548), .Y(Sgf_operation_mult_x_1_n3653) );
AOI222X1TS U4334 ( .A0(n3843), .A1(n3235), .B0(n3129), .B1(n3234), .C0(n3841), .C1(n2654), .Y(n2370) );
XOR2X1TS U4335 ( .A(n2371), .B(n2661), .Y(Sgf_operation_mult_x_1_n4197) );
XOR2X1TS U4336 ( .A(n2373), .B(n3282), .Y(Sgf_operation_mult_x_1_n3508) );
XOR2X1TS U4337 ( .A(n2375), .B(n3726), .Y(Sgf_operation_mult_x_1_n4003) );
XOR2X1TS U4338 ( .A(n2377), .B(n3726), .Y(Sgf_operation_mult_x_1_n4008) );
XOR2X1TS U4339 ( .A(n2379), .B(n3593), .Y(Sgf_operation_mult_x_1_n3706) );
AOI222X1TS U4340 ( .A0(n3610), .A1(n3921), .B0(n3598), .B1(n2539), .C0(n3609), .C1(n3222), .Y(n2380) );
XOR2X1TS U4341 ( .A(n2381), .B(n3603), .Y(Sgf_operation_mult_x_1_n3760) );
XOR2X1TS U4342 ( .A(n2383), .B(n3814), .Y(Sgf_operation_mult_x_1_n4176) );
AOI222X1TS U4343 ( .A0(n3843), .A1(n3938), .B0(n3129), .B1(n3936), .C0(n3827), .C1(n3947), .Y(n2384) );
XOR2X1TS U4344 ( .A(n2385), .B(n2661), .Y(Sgf_operation_mult_x_1_n4221) );
XOR2X1TS U4345 ( .A(n2387), .B(n3746), .Y(Sgf_operation_mult_x_1_n4065) );
AOI222X1TS U4346 ( .A0(n3805), .A1(n2607), .B0(n3151), .B1(n2462), .C0(n3156), .C1(n3184), .Y(n2388) );
XOR2X1TS U4347 ( .A(n2389), .B(n3444), .Y(Sgf_operation_mult_x_1_n4144) );
AOI222X1TS U4348 ( .A0(n4167), .A1(n2508), .B0(n4165), .B1(n2507), .C0(n3995), .C1(n3918), .Y(n2390) );
XOR2X1TS U4349 ( .A(n2391), .B(n5152), .Y(Sgf_operation_mult_x_1_n4370) );
AOI21X1TS U4350 ( .A0(n2751), .A1(n4053), .B0(n3704), .Y(n2392) );
XOR2X1TS U4351 ( .A(n2393), .B(n2761), .Y(Sgf_operation_mult_x_1_n3969) );
XOR2X1TS U4352 ( .A(n2395), .B(n3282), .Y(Sgf_operation_mult_x_1_n3500) );
XOR2X1TS U4353 ( .A(n2399), .B(n3603), .Y(Sgf_operation_mult_x_1_n3790) );
XOR2X1TS U4354 ( .A(n2401), .B(n3881), .Y(Sgf_operation_mult_x_1_n4275) );
OAI21X1TS U4355 ( .A0(n639), .A1(n3580), .B0(n2402), .Y(n2403) );
XOR2X1TS U4356 ( .A(n2403), .B(n3586), .Y(Sgf_operation_mult_x_1_n3725) );
XOR2X1TS U4357 ( .A(n2405), .B(n3557), .Y(Sgf_operation_mult_x_1_n3668) );
OAI21X1TS U4358 ( .A0(n4046), .A1(n3829), .B0(n2406), .Y(n2407) );
XOR2X1TS U4359 ( .A(n2407), .B(n2661), .Y(Sgf_operation_mult_x_1_n4195) );
AOI21X1TS U4360 ( .A0(n3778), .A1(n700), .B0(n2408), .Y(n2409) );
XOR2X1TS U4361 ( .A(n2410), .B(n2799), .Y(Sgf_operation_mult_x_1_n4082) );
OAI21X1TS U4362 ( .A0(n641), .A1(n3770), .B0(n2411), .Y(n2412) );
XOR2X1TS U4363 ( .A(n2412), .B(n3783), .Y(Sgf_operation_mult_x_1_n4114) );
AOI222X1TS U4364 ( .A0(n4106), .A1(n3923), .B0(n4098), .B1(n3922), .C0(n4104), .C1(n2956), .Y(n2413) );
XOR2X1TS U4365 ( .A(n2414), .B(n4145), .Y(Sgf_operation_mult_x_1_n4317) );
XOR2X1TS U4366 ( .A(n2416), .B(n3837), .Y(Sgf_operation_mult_x_1_n4215) );
AOI222X1TS U4367 ( .A0(n3599), .A1(n3947), .B0(n3605), .B1(n3946), .C0(n2663), .C1(n3020), .Y(n2417) );
XOR2X1TS U4368 ( .A(n2418), .B(n3620), .Y(Sgf_operation_mult_x_1_n3776) );
AOI222X1TS U4369 ( .A0(n3638), .A1(n3933), .B0(n3631), .B1(n3932), .C0(n2777), .C1(n3872), .Y(n2420) );
XOR2X1TS U4370 ( .A(n2421), .B(n3634), .Y(Sgf_operation_mult_x_1_n3828) );
AOI222X1TS U4371 ( .A0(n3713), .A1(n3264), .B0(n3704), .B1(n3263), .C0(n3721), .C1(n3262), .Y(n2422) );
XOR2X1TS U4372 ( .A(n2423), .B(n3710), .Y(Sgf_operation_mult_x_1_n3993) );
AOI222X1TS U4373 ( .A0(n3773), .A1(n2713), .B0(n3768), .B1(n2712), .C0(n3772), .C1(n2607), .Y(n2425) );
XOR2X1TS U4374 ( .A(n2426), .B(n2799), .Y(Sgf_operation_mult_x_1_n4086) );
OAI21X1TS U4375 ( .A0(n3232), .A1(n3544), .B0(n2427), .Y(n2428) );
XOR2X1TS U4376 ( .A(n2428), .B(n3548), .Y(Sgf_operation_mult_x_1_n3655) );
XOR2X1TS U4377 ( .A(n2431), .B(n3801), .Y(Sgf_operation_mult_x_1_n4159) );
AOI222X1TS U4378 ( .A0(n3696), .A1(n2654), .B0(n3712), .B1(n2653), .C0(n2751), .C1(n2946), .Y(n2432) );
XOR2X1TS U4379 ( .A(n2433), .B(n2761), .Y(Sgf_operation_mult_x_1_n3975) );
AOI222X1TS U4380 ( .A0(n3750), .A1(n2713), .B0(n3728), .B1(n2712), .C0(n3739), .C1(n2942), .Y(n2434) );
XOR2X1TS U4381 ( .A(n2435), .B(n3424), .Y(Sgf_operation_mult_x_1_n4030) );
AOI222X1TS U4382 ( .A0(n4167), .A1(n3819), .B0(n3937), .B1(n3818), .C0(n4163), .C1(n3885), .Y(n2436) );
XOR2X1TS U4383 ( .A(n2437), .B(n4170), .Y(Sgf_operation_mult_x_1_n4376) );
XOR2X1TS U4384 ( .A(n2439), .B(n3504), .Y(Sgf_operation_mult_x_1_n3564) );
AOI222X1TS U4385 ( .A0(n3523), .A1(n3859), .B0(n3528), .B1(n3858), .C0(n3521), .C1(n3857), .Y(n2440) );
XOR2X1TS U4386 ( .A(n2441), .B(n3532), .Y(Sgf_operation_mult_x_1_n3600) );
XOR2X1TS U4387 ( .A(n2443), .B(n5152), .Y(Sgf_operation_mult_x_1_n4363) );
XOR2X1TS U4388 ( .A(n2445), .B(n3525), .Y(Sgf_operation_mult_x_1_n3619) );
AOI222X1TS U4389 ( .A0(n2695), .A1(n3912), .B0(n3643), .B1(n3911), .C0(n2755), .C1(n2954), .Y(n2446) );
XOR2X1TS U4390 ( .A(n2447), .B(n2758), .Y(Sgf_operation_mult_x_1_n3867) );
AOI222X1TS U4391 ( .A0(n3843), .A1(n2654), .B0(n3129), .B1(n2653), .C0(n3128), .C1(n3907), .Y(n2448) );
XOR2X1TS U4392 ( .A(n2449), .B(n2661), .Y(Sgf_operation_mult_x_1_n4199) );
XOR2X1TS U4393 ( .A(n2451), .B(n3783), .Y(Sgf_operation_mult_x_1_n4120) );
XOR2X1TS U4394 ( .A(n2453), .B(n3685), .Y(Sgf_operation_mult_x_1_n3953) );
AOI21X1TS U4395 ( .A0(n3764), .A1(n4047), .B0(n3758), .Y(n2454) );
XOR2X1TS U4396 ( .A(n2455), .B(n2799), .Y(Sgf_operation_mult_x_1_n4081) );
AOI222X1TS U4397 ( .A0(n3590), .A1(n3938), .B0(n3578), .B1(n3936), .C0(n3588), .C1(n3272), .Y(n2456) );
XOR2X1TS U4398 ( .A(n2457), .B(n3364), .Y(Sgf_operation_mult_x_1_n3718) );
AOI222X1TS U4399 ( .A0(n3659), .A1(n3933), .B0(n3658), .B1(n3932), .C0(n3657), .C1(n3872), .Y(n2458) );
XOR2X1TS U4400 ( .A(n2459), .B(n3663), .Y(Sgf_operation_mult_x_1_n3884) );
AOI222X1TS U4401 ( .A0(n3689), .A1(n2508), .B0(n2746), .B1(n2507), .C0(n3687), .C1(n3201), .Y(n2460) );
XOR2X1TS U4402 ( .A(n2461), .B(n3404), .Y(Sgf_operation_mult_x_1_n3922) );
AOI222X1TS U4403 ( .A0(n3689), .A1(n2607), .B0(n2746), .B1(n2462), .C0(n3687), .C1(n3184), .Y(n2463) );
XOR2X1TS U4404 ( .A(n2464), .B(n3404), .Y(Sgf_operation_mult_x_1_n3920) );
XOR2X1TS U4405 ( .A(n2466), .B(n3846), .Y(Sgf_operation_mult_x_1_n4227) );
AOI222X1TS U4406 ( .A0(n3665), .A1(n2743), .B0(n3688), .B1(n2742), .C0(n3677), .C1(n3247), .Y(n2467) );
XOR2X1TS U4407 ( .A(n2468), .B(n3692), .Y(Sgf_operation_mult_x_1_n3939) );
AOI222X1TS U4408 ( .A0(n3831), .A1(n2743), .B0(n3835), .B1(n2742), .C0(n3827), .C1(n3938), .Y(n2469) );
XOR2X1TS U4409 ( .A(n2470), .B(n3837), .Y(Sgf_operation_mult_x_1_n4219) );
OAI21X1TS U4410 ( .A0(n2961), .A1(n2796), .B0(n2471), .Y(n2472) );
XOR2X1TS U4411 ( .A(n2472), .B(n3897), .Y(Sgf_operation_mult_x_1_n4321) );
AOI222X1TS U4412 ( .A0(n3862), .A1(n2474), .B0(n3878), .B1(n2473), .C0(n3867), .C1(n2962), .Y(n2475) );
XOR2X1TS U4413 ( .A(n2476), .B(n3881), .Y(Sgf_operation_mult_x_1_n4265) );
AOI222X1TS U4414 ( .A0(n3638), .A1(n2743), .B0(n3637), .B1(n2742), .C0(n3630), .C1(n3247), .Y(n2477) );
XOR2X1TS U4415 ( .A(n2478), .B(n3641), .Y(Sgf_operation_mult_x_1_n3827) );
XOR2X1TS U4416 ( .A(n2480), .B(n4109), .Y(Sgf_operation_mult_x_1_n4342) );
XOR2X1TS U4417 ( .A(n2482), .B(n3881), .Y(Sgf_operation_mult_x_1_n4273) );
AOI222X1TS U4418 ( .A0(n3494), .A1(n3953), .B0(n3500), .B1(n3952), .C0(n2785), .C1(n3008), .Y(n2483) );
XOR2X1TS U4419 ( .A(n2484), .B(n2769), .Y(Sgf_operation_mult_x_1_n3555) );
AOI222X1TS U4420 ( .A0(n3862), .A1(n2645), .B0(n3878), .B1(n2644), .C0(n3867), .C1(n3229), .Y(n2485) );
XOR2X1TS U4421 ( .A(n2486), .B(n3881), .Y(Sgf_operation_mult_x_1_n4269) );
OAI21X1TS U4422 ( .A0(n3232), .A1(n3576), .B0(n2487), .Y(n2488) );
XOR2X1TS U4423 ( .A(n2488), .B(n3593), .Y(Sgf_operation_mult_x_1_n3710) );
AOI222X1TS U4424 ( .A0(n3811), .A1(n3938), .B0(n3151), .B1(n3936), .C0(n3156), .C1(n3272), .Y(n2489) );
XOR2X1TS U4425 ( .A(n2490), .B(n3444), .Y(Sgf_operation_mult_x_1_n4165) );
AOI222X1TS U4426 ( .A0(n3622), .A1(n3912), .B0(n2778), .B1(n3911), .C0(n2777), .C1(n2954), .Y(n2491) );
XOR2X1TS U4427 ( .A(n2492), .B(n3384), .Y(Sgf_operation_mult_x_1_n3811) );
AOI222X1TS U4428 ( .A0(n3651), .A1(n3235), .B0(n3643), .B1(n3234), .C0(n3657), .C1(n3233), .Y(n2493) );
XOR2X1TS U4429 ( .A(n2494), .B(n2758), .Y(Sgf_operation_mult_x_1_n3861) );
XOR2X1TS U4430 ( .A(n2496), .B(n3685), .Y(Sgf_operation_mult_x_1_n3951) );
XOR2X1TS U4431 ( .A(n2498), .B(n4062), .Y(Sgf_operation_mult_x_1_n3499) );
AOI222X1TS U4432 ( .A0(n2695), .A1(n3907), .B0(n3643), .B1(n3906), .C0(n2755), .C1(n3199), .Y(n2499) );
XOR2X1TS U4433 ( .A(n2500), .B(n2758), .Y(Sgf_operation_mult_x_1_n3865) );
AOI222X1TS U4434 ( .A0(n4106), .A1(Op_MY[50]), .B0(n4098), .B1(n2752), .C0(
n3894), .C1(n4072), .Y(n2501) );
XOR2X1TS U4435 ( .A(n2502), .B(n4145), .Y(Sgf_operation_mult_x_1_n4308) );
AOI222X1TS U4436 ( .A0(n3901), .A1(n3921), .B0(n4098), .B1(n2539), .C0(n3894), .C1(n3222), .Y(n2503) );
XOR2X1TS U4437 ( .A(n2504), .B(n3897), .Y(Sgf_operation_mult_x_1_n4319) );
XOR2X1TS U4438 ( .A(n2506), .B(n3814), .Y(Sgf_operation_mult_x_1_n4167) );
AOI222X1TS U4439 ( .A0(n3659), .A1(n2508), .B0(n3643), .B1(n2507), .C0(n3657), .C1(n3201), .Y(n2509) );
XOR2X1TS U4440 ( .A(n2510), .B(n2758), .Y(Sgf_operation_mult_x_1_n3866) );
AOI21X1TS U4441 ( .A0(n4163), .A1(n2728), .B0(n2511), .Y(n2512) );
XOR2X1TS U4442 ( .A(n2513), .B(n5152), .Y(Sgf_operation_mult_x_1_n4362) );
AOI222X1TS U4443 ( .A0(n2695), .A1(n3264), .B0(n3650), .B1(n3263), .C0(n2755), .C1(n3262), .Y(n2514) );
XOR2X1TS U4444 ( .A(n2515), .B(n3653), .Y(Sgf_operation_mult_x_1_n3881) );
OAI21X1TS U4445 ( .A0(n2952), .A1(n2660), .B0(n2516), .Y(n2517) );
XOR2X1TS U4446 ( .A(n2517), .B(n2661), .Y(Sgf_operation_mult_x_1_n4204) );
AOI21X1TS U4447 ( .A0(n4104), .A1(n700), .B0(n2518), .Y(n2519) );
XOR2X1TS U4448 ( .A(n2520), .B(n4145), .Y(Sgf_operation_mult_x_1_n4306) );
XOR2X1TS U4449 ( .A(n2522), .B(n3641), .Y(Sgf_operation_mult_x_1_n3814) );
XOR2X1TS U4450 ( .A(n2524), .B(n3384), .Y(Sgf_operation_mult_x_1_n3812) );
AOI222X1TS U4451 ( .A0(n3659), .A1(n2654), .B0(n3643), .B1(n2653), .C0(n3649), .C1(n2946), .Y(n2525) );
XOR2X1TS U4452 ( .A(n2526), .B(n2758), .Y(Sgf_operation_mult_x_1_n3863) );
AOI21X1TS U4453 ( .A0(n3708), .A1(Op_MY[50]), .B0(n2527), .Y(n2528) );
XOR2X1TS U4454 ( .A(n2529), .B(n2761), .Y(Sgf_operation_mult_x_1_n3970) );
AOI21X1TS U4455 ( .A0(n3873), .A1(Op_MY[50]), .B0(n2530), .Y(n2531) );
XOR2X1TS U4456 ( .A(n2532), .B(n4094), .Y(Sgf_operation_mult_x_1_n4250) );
XOR2X1TS U4457 ( .A(n2534), .B(n3746), .Y(Sgf_operation_mult_x_1_n4057) );
XOR2X1TS U4458 ( .A(n2536), .B(n3746), .Y(Sgf_operation_mult_x_1_n4060) );
XOR2X1TS U4459 ( .A(n2538), .B(n3685), .Y(Sgf_operation_mult_x_1_n3948) );
AOI222X1TS U4460 ( .A0(n3622), .A1(n3921), .B0(n3637), .B1(n2539), .C0(n3630), .C1(n3222), .Y(n2540) );
XOR2X1TS U4461 ( .A(n2541), .B(n3641), .Y(Sgf_operation_mult_x_1_n3815) );
OAI21X1TS U4462 ( .A0(n637), .A1(n3833), .B0(n2542), .Y(n2543) );
XOR2X1TS U4463 ( .A(n2543), .B(n3846), .Y(Sgf_operation_mult_x_1_n4230) );
AOI222X1TS U4464 ( .A0(n3862), .A1(n3992), .B0(n4035), .B1(n3991), .C0(n4034), .C1(n3031), .Y(n2544) );
XOR2X1TS U4465 ( .A(n2545), .B(n4039), .Y(Sgf_operation_mult_x_1_n4289) );
AOI222X1TS U4466 ( .A0(n3665), .A1(n3264), .B0(n3688), .B1(n3263), .C0(n3677), .C1(n3262), .Y(n2546) );
XOR2X1TS U4467 ( .A(n2547), .B(n3692), .Y(Sgf_operation_mult_x_1_n3937) );
XOR2X1TS U4468 ( .A(n2549), .B(n3783), .Y(Sgf_operation_mult_x_1_n4121) );
XOR2X1TS U4469 ( .A(n2551), .B(n3548), .Y(Sgf_operation_mult_x_1_n3654) );
AOI222X1TS U4470 ( .A0(n3638), .A1(n3264), .B0(n3637), .B1(n3263), .C0(n3630), .C1(n3262), .Y(n2552) );
XOR2X1TS U4471 ( .A(n2553), .B(n3641), .Y(Sgf_operation_mult_x_1_n3825) );
XOR2X1TS U4472 ( .A(n2555), .B(n3282), .Y(Sgf_operation_mult_x_1_n3501) );
XOR2X1TS U4473 ( .A(n2557), .B(n3663), .Y(Sgf_operation_mult_x_1_n3894) );
OAI21X1TS U4474 ( .A0(n2952), .A1(n2649), .B0(n2558), .Y(n2559) );
XOR2X1TS U4475 ( .A(n2559), .B(n3444), .Y(Sgf_operation_mult_x_1_n4148) );
AOI222X1TS U4476 ( .A0(n3831), .A1(n3264), .B0(n3835), .B1(n3263), .C0(n3841), .C1(n2743), .Y(n2560) );
XOR2X1TS U4477 ( .A(n2561), .B(n3837), .Y(Sgf_operation_mult_x_1_n4217) );
XOR2X1TS U4478 ( .A(n2563), .B(n3663), .Y(Sgf_operation_mult_x_1_n3887) );
AOI222X1TS U4479 ( .A0(n3610), .A1(n3819), .B0(n3598), .B1(n3818), .C0(n3609), .C1(n3787), .Y(n2564) );
XOR2X1TS U4480 ( .A(n2565), .B(n3603), .Y(Sgf_operation_mult_x_1_n3761) );
XOR2X1TS U4481 ( .A(n2567), .B(n2769), .Y(Sgf_operation_mult_x_1_n3553) );
AOI222X1TS U4482 ( .A0(n3599), .A1(n2584), .B0(n3598), .B1(n2583), .C0(n3609), .C1(n2968), .Y(n2568) );
XOR2X1TS U4483 ( .A(n2569), .B(n3603), .Y(Sgf_operation_mult_x_1_n3764) );
AOI21X1TS U4484 ( .A0(n3809), .A1(n700), .B0(n2570), .Y(n2571) );
XOR2X1TS U4485 ( .A(n2572), .B(n3444), .Y(Sgf_operation_mult_x_1_n4138) );
XOR2X1TS U4486 ( .A(n2574), .B(n3634), .Y(Sgf_operation_mult_x_1_n3841) );
XOR2X1TS U4487 ( .A(n2576), .B(n4170), .Y(Sgf_operation_mult_x_1_n4374) );
AOI222X1TS U4488 ( .A0(n3820), .A1(n2713), .B0(n3129), .B1(n2712), .C0(n3841), .C1(n2607), .Y(n2577) );
XOR2X1TS U4489 ( .A(n2578), .B(n2661), .Y(Sgf_operation_mult_x_1_n4198) );
AOI222X1TS U4490 ( .A0(n3773), .A1(n3938), .B0(n3768), .B1(n3936), .C0(n3772), .C1(n3947), .Y(n2579) );
XOR2X1TS U4491 ( .A(n2580), .B(n2799), .Y(Sgf_operation_mult_x_1_n4109) );
XOR2X1TS U4492 ( .A(n2582), .B(n3620), .Y(Sgf_operation_mult_x_1_n3773) );
AOI222X1TS U4493 ( .A0(n3862), .A1(n2584), .B0(n3878), .B1(n2583), .C0(n3867), .C1(n2968), .Y(n2585) );
XOR2X1TS U4494 ( .A(n2586), .B(n3881), .Y(Sgf_operation_mult_x_1_n4267) );
XOR2X1TS U4495 ( .A(n2588), .B(n3663), .Y(Sgf_operation_mult_x_1_n3895) );
XOR2X1TS U4496 ( .A(n2590), .B(n4109), .Y(Sgf_operation_mult_x_1_n4335) );
AOI222X1TS U4497 ( .A0(n3901), .A1(n3819), .B0(n4105), .B1(n3818), .C0(n4104), .C1(n3787), .Y(n2591) );
XOR2X1TS U4498 ( .A(n2592), .B(n3897), .Y(Sgf_operation_mult_x_1_n4320) );
XOR2X1TS U4499 ( .A(n2594), .B(n3726), .Y(Sgf_operation_mult_x_1_n4004) );
OAI21X1TS U4500 ( .A0(n3949), .A1(n3576), .B0(n2595), .Y(n2596) );
XOR2X1TS U4501 ( .A(n2596), .B(n3586), .Y(Sgf_operation_mult_x_1_n3720) );
AOI222X1TS U4502 ( .A0(n3862), .A1(n3980), .B0(n4035), .B1(n3308), .C0(n4034), .C1(n3307), .Y(n2597) );
XOR2X1TS U4503 ( .A(n2598), .B(n4039), .Y(Sgf_operation_mult_x_1_n4288) );
XOR2X1TS U4504 ( .A(n2600), .B(n2661), .Y(Sgf_operation_mult_x_1_n4192) );
AOI222X1TS U4505 ( .A0(n3465), .A1(n2743), .B0(n3472), .B1(n2742), .C0(n3468), .C1(n3247), .Y(n2601) );
XOR2X1TS U4506 ( .A(n2602), .B(n3476), .Y(Sgf_operation_mult_x_1_n3495) );
AOI222X1TS U4507 ( .A0(n3850), .A1(n3918), .B0(n4027), .B1(n3917), .C0(n3873), .C1(n2950), .Y(n2603) );
XOR2X1TS U4508 ( .A(n2604), .B(n4094), .Y(Sgf_operation_mult_x_1_n4260) );
AOI222X1TS U4509 ( .A0(n3696), .A1(n3235), .B0(n3712), .B1(n3234), .C0(n2751), .C1(n3233), .Y(n2605) );
XOR2X1TS U4510 ( .A(n2606), .B(n2761), .Y(Sgf_operation_mult_x_1_n3973) );
AOI222X1TS U4511 ( .A0(n4167), .A1(n2713), .B0(n4165), .B1(n2712), .C0(n4163), .C1(n2607), .Y(n2608) );
XOR2X1TS U4512 ( .A(n2609), .B(n5152), .Y(Sgf_operation_mult_x_1_n4366) );
XOR2X1TS U4513 ( .A(n2611), .B(n3685), .Y(Sgf_operation_mult_x_1_n3950) );
AOI222X1TS U4514 ( .A0(n3773), .A1(n3264), .B0(n3758), .B1(n3263), .C0(n3772), .C1(n2743), .Y(n2612) );
XOR2X1TS U4515 ( .A(n2613), .B(n3762), .Y(Sgf_operation_mult_x_1_n4105) );
XOR2X1TS U4516 ( .A(n2615), .B(n3814), .Y(Sgf_operation_mult_x_1_n4173) );
AOI222X1TS U4517 ( .A0(n2695), .A1(n3923), .B0(n3643), .B1(n3922), .C0(n2755), .C1(n2956), .Y(n2616) );
XOR2X1TS U4518 ( .A(n2617), .B(n2758), .Y(Sgf_operation_mult_x_1_n3869) );
AOI222X1TS U4519 ( .A0(n4031), .A1(n2713), .B0(n4027), .B1(n2712), .C0(n3873), .C1(n2942), .Y(n2618) );
XOR2X1TS U4520 ( .A(n2619), .B(n4094), .Y(Sgf_operation_mult_x_1_n4254) );
XOR2X1TS U4521 ( .A(n2621), .B(n3404), .Y(Sgf_operation_mult_x_1_n3915) );
AOI222X1TS U4522 ( .A0(n4167), .A1(n2728), .B0(n4165), .B1(n2752), .C0(n4163), .C1(n2713), .Y(n2622) );
XOR2X1TS U4523 ( .A(n2624), .B(n5152), .Y(Sgf_operation_mult_x_1_n4364) );
AOI222X1TS U4524 ( .A0(n3723), .A1(n2713), .B0(n3712), .B1(n2712), .C0(n3721), .C1(n2942), .Y(n2625) );
XOR2X1TS U4525 ( .A(n2626), .B(n2761), .Y(Sgf_operation_mult_x_1_n3974) );
XOR2X1TS U4526 ( .A(n2628), .B(n3837), .Y(Sgf_operation_mult_x_1_n4212) );
OAI21X1TS U4527 ( .A0(n630), .A1(n4096), .B0(n2629), .Y(n2630) );
XOR2X1TS U4528 ( .A(n2630), .B(n3897), .Y(Sgf_operation_mult_x_1_n4318) );
AOI21X1TS U4529 ( .A0(n3687), .A1(Op_MY[50]), .B0(n2631), .Y(n2632) );
XOR2X1TS U4530 ( .A(n2633), .B(n3404), .Y(Sgf_operation_mult_x_1_n3914) );
XOR2X1TS U4531 ( .A(n2635), .B(n3814), .Y(Sgf_operation_mult_x_1_n4177) );
AOI21X1TS U4532 ( .A0(n3841), .A1(n700), .B0(n2636), .Y(n2637) );
XOR2X1TS U4533 ( .A(n2638), .B(n2661), .Y(Sgf_operation_mult_x_1_n4194) );
XOR2X1TS U4534 ( .A(n2640), .B(n4094), .Y(Sgf_operation_mult_x_1_n4252) );
XOR2X1TS U4535 ( .A(n2642), .B(n3685), .Y(Sgf_operation_mult_x_1_n3949) );
XOR2X1TS U4536 ( .A(n2647), .B(n3837), .Y(Sgf_operation_mult_x_1_n4213) );
AOI222X1TS U4537 ( .A0(n3805), .A1(Op_MY[50]), .B0(n3151), .B1(n2752), .C0(
n3156), .C1(n4072), .Y(n2648) );
XOR2X1TS U4538 ( .A(n2650), .B(n3444), .Y(Sgf_operation_mult_x_1_n4140) );
XOR2X1TS U4539 ( .A(n2652), .B(n4145), .Y(Sgf_operation_mult_x_1_n4304) );
AOI222X1TS U4540 ( .A0(n3665), .A1(n2654), .B0(n2746), .B1(n2653), .C0(n3677), .C1(n2946), .Y(n2655) );
XOR2X1TS U4541 ( .A(n2656), .B(n3404), .Y(Sgf_operation_mult_x_1_n3919) );
AOI222X1TS U4542 ( .A0(n4167), .A1(n3264), .B0(n3937), .B1(n3263), .C0(n4163), .C1(n2743), .Y(n2657) );
XOR2X1TS U4543 ( .A(n2658), .B(n4170), .Y(Sgf_operation_mult_x_1_n4385) );
AOI222X1TS U4544 ( .A0(n3820), .A1(n2728), .B0(n3129), .B1(n2752), .C0(n3841), .C1(n2713), .Y(n2659) );
XOR2X1TS U4545 ( .A(n2662), .B(n2661), .Y(Sgf_operation_mult_x_1_n4196) );
AOI222X1TS U4546 ( .A0(n3595), .A1(n3918), .B0(n3605), .B1(n3917), .C0(n2663), .C1(n2950), .Y(n2664) );
XOR2X1TS U4547 ( .A(n2667), .B(n2666), .Y(Sgf_operation_mult_x_1_n3757) );
OAI21X1TS U4548 ( .A0(n636), .A1(n3745), .B0(n2668), .Y(n2669) );
XOR2X1TS U4549 ( .A(n2669), .B(n3424), .Y(Sgf_operation_mult_x_1_n4056) );
XOR2X1TS U4550 ( .A(n2671), .B(n5152), .Y(Sgf_operation_mult_x_1_n4360) );
XOR2X1TS U4551 ( .A(n2673), .B(n2761), .Y(Sgf_operation_mult_x_1_n4000) );
AOI222X1TS U4552 ( .A0(n3901), .A1(n3938), .B0(n4098), .B1(n3936), .C0(n4104), .C1(n3272), .Y(n2674) );
XOR2X1TS U4553 ( .A(n2675), .B(n4145), .Y(Sgf_operation_mult_x_1_n4333) );
XOR2X1TS U4554 ( .A(n2677), .B(n3726), .Y(Sgf_operation_mult_x_1_n3999) );
XOR2X1TS U4555 ( .A(n2679), .B(n3846), .Y(Sgf_operation_mult_x_1_n4226) );
OAI21X1TS U4556 ( .A0(n2952), .A1(n3745), .B0(n2680), .Y(n2681) );
XOR2X1TS U4557 ( .A(n2681), .B(n3424), .Y(Sgf_operation_mult_x_1_n4036) );
AOI222X1TS U4558 ( .A0(n3998), .A1(n2743), .B0(n3937), .B1(n2742), .C0(n3995), .C1(n3938), .Y(n2682) );
XOR2X1TS U4559 ( .A(n2683), .B(n5152), .Y(Sgf_operation_mult_x_1_n4387) );
XOR2X1TS U4560 ( .A(n2685), .B(n3814), .Y(Sgf_operation_mult_x_1_n4174) );
XOR2X1TS U4561 ( .A(n2687), .B(n3444), .Y(Sgf_operation_mult_x_1_n4136) );
AOI222X1TS U4562 ( .A0(n3465), .A1(n3933), .B0(n3472), .B1(n3932), .C0(n4054), .C1(n3872), .Y(n2688) );
XOR2X1TS U4563 ( .A(n2689), .B(n3282), .Y(Sgf_operation_mult_x_1_n3496) );
XOR2X1TS U4564 ( .A(n2691), .B(n3663), .Y(Sgf_operation_mult_x_1_n3897) );
AOI222X1TS U4565 ( .A0(n3523), .A1(n3943), .B0(n3273), .B1(n3942), .C0(n3518), .C1(n3024), .Y(n2693) );
XOR2X1TS U4566 ( .A(n2694), .B(n3344), .Y(Sgf_operation_mult_x_1_n3608) );
AOI222X1TS U4567 ( .A0(n3651), .A1(n2713), .B0(n3643), .B1(n2712), .C0(n3649), .C1(n2942), .Y(n2696) );
XOR2X1TS U4568 ( .A(n2697), .B(n2758), .Y(Sgf_operation_mult_x_1_n3862) );
XOR2X1TS U4569 ( .A(n2699), .B(n3603), .Y(Sgf_operation_mult_x_1_n3789) );
OAI21X1TS U4570 ( .A0(n2692), .A1(n3576), .B0(n2700), .Y(n2701) );
XOR2X1TS U4571 ( .A(n2701), .B(n3364), .Y(Sgf_operation_mult_x_1_n3719) );
XOR2X1TS U4572 ( .A(n2703), .B(n4094), .Y(Sgf_operation_mult_x_1_n4248) );
AOI222X1TS U4573 ( .A0(n1452), .A1(n3264), .B0(n3542), .B1(n3263), .C0(n3546), .C1(n3262), .Y(n2704) );
XOR2X1TS U4574 ( .A(n2705), .B(n3548), .Y(Sgf_operation_mult_x_1_n3659) );
AOI222X1TS U4575 ( .A0(n3831), .A1(n3933), .B0(n3835), .B1(n3932), .C0(n3827), .C1(n3943), .Y(n2706) );
XOR2X1TS U4576 ( .A(n2707), .B(n3846), .Y(Sgf_operation_mult_x_1_n4220) );
AOI222X1TS U4577 ( .A0(n3590), .A1(n4166), .B0(n3583), .B1(n4164), .C0(n3582), .C1(n3720), .Y(n2708) );
XOR2X1TS U4578 ( .A(n2709), .B(n3586), .Y(Sgf_operation_mult_x_1_n3737) );
XOR2X1TS U4579 ( .A(n2711), .B(n3424), .Y(Sgf_operation_mult_x_1_n4027) );
AOI222X1TS U4580 ( .A0(n3689), .A1(n2713), .B0(n2746), .B1(n2712), .C0(n3687), .C1(n2942), .Y(n2714) );
XOR2X1TS U4581 ( .A(n2715), .B(n3404), .Y(Sgf_operation_mult_x_1_n3918) );
AOI222X1TS U4582 ( .A0(n3501), .A1(n3264), .B0(n3489), .B1(n3263), .C0(n3493), .C1(n3262), .Y(n2716) );
XOR2X1TS U4583 ( .A(n2717), .B(n3491), .Y(Sgf_operation_mult_x_1_n3548) );
XOR2X1TS U4584 ( .A(n2719), .B(n3404), .Y(Sgf_operation_mult_x_1_n3942) );
AOI222X1TS U4585 ( .A0(n3529), .A1(n2743), .B0(n3528), .B1(n2742), .C0(n3521), .C1(n3247), .Y(n2720) );
XOR2X1TS U4586 ( .A(n2721), .B(n3532), .Y(Sgf_operation_mult_x_1_n3605) );
AOI222X1TS U4587 ( .A0(n3862), .A1(n3947), .B0(n4027), .B1(n3946), .C0(n3873), .C1(n3020), .Y(n2722) );
XOR2X1TS U4588 ( .A(n2723), .B(n4039), .Y(Sgf_operation_mult_x_1_n4279) );
AOI222X1TS U4589 ( .A0(n3750), .A1(n700), .B0(n3728), .B1(n2752), .C0(n3739),
.C1(n4072), .Y(n2724) );
XOR2X1TS U4590 ( .A(n2725), .B(n3424), .Y(Sgf_operation_mult_x_1_n4028) );
XOR2X1TS U4591 ( .A(n2727), .B(n3663), .Y(Sgf_operation_mult_x_1_n3896) );
XOR2X1TS U4592 ( .A(n2731), .B(n2761), .Y(Sgf_operation_mult_x_1_n3971) );
AOI21X1TS U4593 ( .A0(n3739), .A1(Op_MY[50]), .B0(n2732), .Y(n2733) );
XOR2X1TS U4594 ( .A(n2735), .B(n3424), .Y(Sgf_operation_mult_x_1_n4026) );
AOI222X1TS U4595 ( .A0(n3651), .A1(n3927), .B0(n3658), .B1(n3868), .C0(n3649), .C1(n3866), .Y(n2736) );
XOR2X1TS U4596 ( .A(n2737), .B(n3653), .Y(Sgf_operation_mult_x_1_n3882) );
AOI222X1TS U4597 ( .A0(n2424), .A1(n2743), .B0(n3758), .B1(n2742), .C0(n3778), .C1(n3938), .Y(n2738) );
XOR2X1TS U4598 ( .A(n2739), .B(n3762), .Y(Sgf_operation_mult_x_1_n4107) );
AOI222X1TS U4599 ( .A0(n3689), .A1(n700), .B0(n2746), .B1(n2752), .C0(n3687),
.C1(n4072), .Y(n2740) );
XOR2X1TS U4600 ( .A(n2741), .B(n3404), .Y(Sgf_operation_mult_x_1_n3916) );
AOI222X1TS U4601 ( .A0(n3805), .A1(n2743), .B0(n3804), .B1(n2742), .C0(n3809), .C1(n3247), .Y(n2744) );
XOR2X1TS U4602 ( .A(n2745), .B(n3801), .Y(Sgf_operation_mult_x_1_n4163) );
AOI222X1TS U4603 ( .A0(n3665), .A1(n3235), .B0(n2746), .B1(n3234), .C0(n3677), .C1(n3233), .Y(n2747) );
XOR2X1TS U4604 ( .A(n2748), .B(n3404), .Y(Sgf_operation_mult_x_1_n3917) );
XOR2X1TS U4605 ( .A(n2750), .B(n3504), .Y(Sgf_operation_mult_x_1_n3554) );
AOI222X1TS U4606 ( .A0(n3713), .A1(Op_MY[50]), .B0(n3712), .B1(n2752), .C0(
n3721), .C1(n4072), .Y(n2753) );
XOR2X1TS U4607 ( .A(n2754), .B(n2761), .Y(Sgf_operation_mult_x_1_n3972) );
XOR2X1TS U4608 ( .A(n2759), .B(n2758), .Y(Sgf_operation_mult_x_1_n3868) );
XOR2X1TS U4609 ( .A(n2762), .B(n2761), .Y(Sgf_operation_mult_x_1_n3968) );
XOR2X1TS U4610 ( .A(n2764), .B(n3726), .Y(Sgf_operation_mult_x_1_n4002) );
XOR2X1TS U4611 ( .A(n2766), .B(n3746), .Y(Sgf_operation_mult_x_1_n4055) );
XOR2X1TS U4612 ( .A(n2770), .B(n2769), .Y(Sgf_operation_mult_x_1_n3552) );
AOI222X1TS U4613 ( .A0(n3729), .A1(n3938), .B0(n3728), .B1(n3936), .C0(n3748), .C1(n3272), .Y(n2771) );
XOR2X1TS U4614 ( .A(n2772), .B(n3424), .Y(Sgf_operation_mult_x_1_n4053) );
AOI222X1TS U4615 ( .A0(n3901), .A1(n3927), .B0(n4105), .B1(n3868), .C0(n3894), .C1(n3866), .Y(n2773) );
XOR2X1TS U4616 ( .A(n2774), .B(n3897), .Y(Sgf_operation_mult_x_1_n4330) );
AOI222X1TS U4617 ( .A0(n3811), .A1(n3264), .B0(n3804), .B1(n3263), .C0(n3809), .C1(n3262), .Y(n2775) );
XOR2X1TS U4618 ( .A(n2776), .B(n3801), .Y(Sgf_operation_mult_x_1_n4161) );
XOR2X1TS U4619 ( .A(n2780), .B(n3384), .Y(Sgf_operation_mult_x_1_n3830) );
XOR2X1TS U4620 ( .A(n2782), .B(n3444), .Y(Sgf_operation_mult_x_1_n4166) );
AOI222X1TS U4621 ( .A0(n4106), .A1(n3933), .B0(n4105), .B1(n3932), .C0(n3894), .C1(n3872), .Y(n2783) );
XOR2X1TS U4622 ( .A(n2784), .B(n4109), .Y(Sgf_operation_mult_x_1_n4332) );
XOR2X1TS U4623 ( .A(n2787), .B(n3504), .Y(Sgf_operation_mult_x_1_n3551) );
AOI222X1TS U4624 ( .A0(n3831), .A1(n3927), .B0(n3835), .B1(n3868), .C0(n3827), .C1(n3933), .Y(n2788) );
XOR2X1TS U4625 ( .A(n2789), .B(n3837), .Y(Sgf_operation_mult_x_1_n4218) );
XOR2X1TS U4626 ( .A(n2791), .B(n2799), .Y(Sgf_operation_mult_x_1_n4080) );
XOR2X1TS U4627 ( .A(n2793), .B(n3424), .Y(Sgf_operation_mult_x_1_n4024) );
OAI21X1TS U4628 ( .A0(n2692), .A1(n2796), .B0(n2795), .Y(n2797) );
XOR2X1TS U4629 ( .A(n2797), .B(n4145), .Y(Sgf_operation_mult_x_1_n4334) );
XOR2X1TS U4630 ( .A(n2800), .B(n2799), .Y(Sgf_operation_mult_x_1_n4110) );
XOR2X1TS U4631 ( .A(n2802), .B(n4094), .Y(Sgf_operation_mult_x_1_n4278) );
AOI222X1TS U4632 ( .A0(n3998), .A1(n3927), .B0(n3937), .B1(n3868), .C0(n3995), .C1(n3933), .Y(n2803) );
XOR2X1TS U4633 ( .A(n2804), .B(n5152), .Y(Sgf_operation_mult_x_1_n4386) );
XOR2X1TS U4634 ( .A(n2806), .B(n4062), .Y(Sgf_operation_mult_x_1_n3498) );
OAI21X1TS U4635 ( .A0(n2692), .A1(n3745), .B0(n2807), .Y(n2808) );
XOR2X1TS U4636 ( .A(n2808), .B(n3424), .Y(Sgf_operation_mult_x_1_n4054) );
CLKXOR2X2TS U4637 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n3055) );
NOR2XLTS U4638 ( .A(n3055), .B(underflow_flag), .Y(n2809) );
OAI32X1TS U4639 ( .A0(n5063), .A1(n2809), .A2(overflow_flag), .B0(n5069),
.B1(n5149), .Y(n286) );
BUFX3TS U4640 ( .A(n703), .Y(n4986) );
OAI31X1TS U4641 ( .A0(n4951), .A1(n4986), .A2(n5088), .B0(n2810), .Y(n417)
);
NAND2X1TS U4642 ( .A(FS_Module_state_reg[3]), .B(n4903), .Y(n3056) );
INVX2TS U4643 ( .A(n3056), .Y(n4270) );
AOI32X4TS U4644 ( .A0(n4270), .A1(n5150), .A2(n707), .B0(n4272), .B1(n5150),
.Y(n4955) );
NAND2X1TS U4645 ( .A(n4954), .B(n4955), .Y(n2811) );
NOR2X1TS U4646 ( .A(n5074), .B(n2811), .Y(n2932) );
INVX2TS U4647 ( .A(n2932), .Y(n2931) );
NOR2X1TS U4648 ( .A(n4955), .B(n5074), .Y(n2853) );
BUFX4TS U4649 ( .A(n2822), .Y(n2906) );
AOI22X1TS U4650 ( .A0(Add_result[39]), .A1(n2926), .B0(
Sgf_normalized_result[38]), .B1(n2906), .Y(n2814) );
NOR2X1TS U4651 ( .A(FSM_selector_C), .B(n2811), .Y(n2817) );
BUFX4TS U4652 ( .A(n2817), .Y(n2876) );
AOI22X1TS U4653 ( .A0(n2876), .A1(n747), .B0(n2907), .B1(P_Sgf[91]), .Y(
n2813) );
OAI211XLTS U4654 ( .A0(n2913), .A1(n5111), .B0(n2814), .C0(n2813), .Y(n390)
);
AOI22X1TS U4655 ( .A0(Add_result[27]), .A1(n2914), .B0(
Sgf_normalized_result[26]), .B1(n2906), .Y(n2816) );
AOI22X1TS U4656 ( .A0(n2876), .A1(n738), .B0(n2907), .B1(P_Sgf[79]), .Y(
n2815) );
OAI211XLTS U4657 ( .A0(n2910), .A1(n5123), .B0(n2816), .C0(n2815), .Y(n378)
);
AOI22X1TS U4658 ( .A0(Add_result[43]), .A1(n2926), .B0(
Sgf_normalized_result[42]), .B1(n2822), .Y(n2819) );
BUFX3TS U4659 ( .A(n2812), .Y(n2927) );
AOI22X1TS U4660 ( .A0(n2817), .A1(n749), .B0(n2921), .B1(P_Sgf[95]), .Y(
n2818) );
OAI211XLTS U4661 ( .A0(n2903), .A1(n5107), .B0(n2819), .C0(n2818), .Y(n394)
);
AOI22X1TS U4662 ( .A0(Add_result[32]), .A1(n2914), .B0(
Sgf_normalized_result[31]), .B1(n2822), .Y(n2821) );
AOI22X1TS U4663 ( .A0(n2876), .A1(n742), .B0(n2921), .B1(n743), .Y(n2820) );
OAI211XLTS U4664 ( .A0(n2910), .A1(n5118), .B0(n2821), .C0(n2820), .Y(n383)
);
BUFX4TS U4665 ( .A(n2822), .Y(n2919) );
AOI22X1TS U4666 ( .A0(Add_result[29]), .A1(n2914), .B0(
Sgf_normalized_result[28]), .B1(n2919), .Y(n2824) );
AOI22X1TS U4667 ( .A0(n2876), .A1(n739), .B0(n2907), .B1(n740), .Y(n2823) );
OAI211XLTS U4668 ( .A0(n2913), .A1(n5121), .B0(n2824), .C0(n2823), .Y(n380)
);
AOI22X1TS U4669 ( .A0(Add_result[36]), .A1(n2914), .B0(
Sgf_normalized_result[35]), .B1(n2906), .Y(n2826) );
AOI22X1TS U4670 ( .A0(n2876), .A1(P_Sgf[87]), .B0(n2921), .B1(n746), .Y(
n2825) );
OAI211XLTS U4671 ( .A0(n2910), .A1(n5114), .B0(n2826), .C0(n2825), .Y(n387)
);
AOI22X1TS U4672 ( .A0(n2926), .A1(n716), .B0(Sgf_normalized_result[50]),
.B1(n2822), .Y(n2828) );
AOI22X1TS U4673 ( .A0(n2876), .A1(P_Sgf[102]), .B0(n719), .B1(n2927), .Y(
n2827) );
OAI211XLTS U4674 ( .A0(n2913), .A1(n5147), .B0(n2828), .C0(n2827), .Y(n402)
);
AOI22X1TS U4675 ( .A0(Add_result[38]), .A1(n2914), .B0(
Sgf_normalized_result[37]), .B1(n2822), .Y(n2830) );
AOI22X1TS U4676 ( .A0(n2876), .A1(P_Sgf[89]), .B0(n2927), .B1(n747), .Y(
n2829) );
OAI211XLTS U4677 ( .A0(n2910), .A1(n5112), .B0(n2830), .C0(n2829), .Y(n389)
);
AOI22X1TS U4678 ( .A0(Add_result[30]), .A1(n2914), .B0(
Sgf_normalized_result[29]), .B1(n2906), .Y(n2832) );
AOI22X1TS U4679 ( .A0(n2876), .A1(n740), .B0(n2921), .B1(n741), .Y(n2831) );
OAI211XLTS U4680 ( .A0(n2913), .A1(n5120), .B0(n2832), .C0(n2831), .Y(n381)
);
AOI22X1TS U4681 ( .A0(Add_result[35]), .A1(n2914), .B0(
Sgf_normalized_result[34]), .B1(n2822), .Y(n2834) );
AOI22X1TS U4682 ( .A0(n2876), .A1(n745), .B0(n2907), .B1(P_Sgf[87]), .Y(
n2833) );
OAI211XLTS U4683 ( .A0(n2910), .A1(n5115), .B0(n2834), .C0(n2833), .Y(n386)
);
AOI22X1TS U4684 ( .A0(Add_result[28]), .A1(n2914), .B0(
Sgf_normalized_result[27]), .B1(n2906), .Y(n2836) );
AOI22X1TS U4685 ( .A0(n2876), .A1(P_Sgf[79]), .B0(n2927), .B1(n739), .Y(
n2835) );
OAI211XLTS U4686 ( .A0(n2913), .A1(n5122), .B0(n2836), .C0(n2835), .Y(n379)
);
AOI22X1TS U4687 ( .A0(Add_result[37]), .A1(n2914), .B0(
Sgf_normalized_result[36]), .B1(n2919), .Y(n2838) );
AOI22X1TS U4688 ( .A0(n2876), .A1(n746), .B0(n2907), .B1(P_Sgf[89]), .Y(
n2837) );
OAI211XLTS U4689 ( .A0(n2910), .A1(n5113), .B0(n2838), .C0(n2837), .Y(n388)
);
AOI22X1TS U4690 ( .A0(n2926), .A1(Add_result[50]), .B0(
Sgf_normalized_result[49]), .B1(n2822), .Y(n2840) );
AOI22X1TS U4691 ( .A0(n2876), .A1(n753), .B0(P_Sgf[102]), .B1(n2921), .Y(
n2839) );
OAI211XLTS U4692 ( .A0(n2913), .A1(n5100), .B0(n2840), .C0(n2839), .Y(n401)
);
AOI22X1TS U4693 ( .A0(Add_result[34]), .A1(n2914), .B0(
Sgf_normalized_result[33]), .B1(n2919), .Y(n2842) );
AOI22X1TS U4694 ( .A0(n2876), .A1(n744), .B0(n2921), .B1(n745), .Y(n2841) );
OAI211XLTS U4695 ( .A0(n2913), .A1(n5116), .B0(n2842), .C0(n2841), .Y(n385)
);
AOI22X1TS U4696 ( .A0(Add_result[33]), .A1(n2914), .B0(
Sgf_normalized_result[32]), .B1(n2906), .Y(n2844) );
AOI22X1TS U4697 ( .A0(n2876), .A1(n743), .B0(n2907), .B1(n744), .Y(n2843) );
OAI211XLTS U4698 ( .A0(n2910), .A1(n5117), .B0(n2844), .C0(n2843), .Y(n384)
);
AOI22X1TS U4699 ( .A0(Add_result[31]), .A1(n2914), .B0(
Sgf_normalized_result[30]), .B1(n2919), .Y(n2846) );
AOI22X1TS U4700 ( .A0(n2876), .A1(n741), .B0(n2907), .B1(n742), .Y(n2845) );
OAI211XLTS U4701 ( .A0(n2913), .A1(n5119), .B0(n2846), .C0(n2845), .Y(n382)
);
AOI22X1TS U4702 ( .A0(Add_result[48]), .A1(n2926), .B0(
Sgf_normalized_result[47]), .B1(n2822), .Y(n2848) );
BUFX4TS U4703 ( .A(n2876), .Y(n2933) );
AOI22X1TS U4704 ( .A0(n2933), .A1(P_Sgf[99]), .B0(n2921), .B1(n752), .Y(
n2847) );
OAI211XLTS U4705 ( .A0(n2910), .A1(n5102), .B0(n2848), .C0(n2847), .Y(n399)
);
AOI22X1TS U4706 ( .A0(Add_result[46]), .A1(n2926), .B0(
Sgf_normalized_result[45]), .B1(n2822), .Y(n2850) );
AOI22X1TS U4707 ( .A0(n2933), .A1(P_Sgf[97]), .B0(n2927), .B1(n751), .Y(
n2849) );
OAI211XLTS U4708 ( .A0(n2903), .A1(n5104), .B0(n2850), .C0(n2849), .Y(n397)
);
AOI22X1TS U4709 ( .A0(Add_result[44]), .A1(n2926), .B0(
Sgf_normalized_result[43]), .B1(n2822), .Y(n2852) );
AOI22X1TS U4710 ( .A0(n2933), .A1(P_Sgf[95]), .B0(n2921), .B1(n750), .Y(
n2851) );
OAI211XLTS U4711 ( .A0(n2910), .A1(n5106), .B0(n2852), .C0(n2851), .Y(n395)
);
AOI22X1TS U4712 ( .A0(Add_result[1]), .A1(n2920), .B0(
Sgf_normalized_result[0]), .B1(n2822), .Y(n2855) );
AOI22X1TS U4713 ( .A0(n2933), .A1(P_Sgf[52]), .B0(n2921), .B1(P_Sgf[53]),
.Y(n2854) );
OAI211XLTS U4714 ( .A0(n2931), .A1(n5182), .B0(n2855), .C0(n2854), .Y(n352)
);
AOI22X1TS U4715 ( .A0(Add_result[7]), .A1(n2914), .B0(
Sgf_normalized_result[6]), .B1(n2919), .Y(n2857) );
AOI22X1TS U4716 ( .A0(n2933), .A1(n724), .B0(n2921), .B1(n725), .Y(n2856) );
OAI211XLTS U4717 ( .A0(n2903), .A1(n5143), .B0(n2857), .C0(n2856), .Y(n358)
);
AOI22X1TS U4718 ( .A0(Add_result[6]), .A1(n2914), .B0(
Sgf_normalized_result[5]), .B1(n2919), .Y(n2859) );
AOI22X1TS U4719 ( .A0(n2933), .A1(n723), .B0(n2927), .B1(n724), .Y(n2858) );
OAI211XLTS U4720 ( .A0(n2903), .A1(n5144), .B0(n2859), .C0(n2858), .Y(n357)
);
AOI22X1TS U4721 ( .A0(Add_result[5]), .A1(n2914), .B0(
Sgf_normalized_result[4]), .B1(n2919), .Y(n2861) );
AOI22X1TS U4722 ( .A0(n2933), .A1(n722), .B0(n2921), .B1(n723), .Y(n2860) );
OAI211XLTS U4723 ( .A0(n2903), .A1(n5145), .B0(n2861), .C0(n2860), .Y(n356)
);
AOI22X1TS U4724 ( .A0(Add_result[10]), .A1(n2920), .B0(
Sgf_normalized_result[9]), .B1(n2919), .Y(n2863) );
AOI22X1TS U4725 ( .A0(n2933), .A1(n727), .B0(n2927), .B1(n728), .Y(n2862) );
OAI211XLTS U4726 ( .A0(n2903), .A1(n5140), .B0(n2863), .C0(n2862), .Y(n361)
);
AOI22X1TS U4727 ( .A0(Add_result[11]), .A1(n2920), .B0(
Sgf_normalized_result[10]), .B1(n2919), .Y(n2865) );
AOI22X1TS U4728 ( .A0(n2933), .A1(n728), .B0(n2921), .B1(n729), .Y(n2864) );
OAI211XLTS U4729 ( .A0(n2903), .A1(n5139), .B0(n2865), .C0(n2864), .Y(n362)
);
AOI22X1TS U4730 ( .A0(Add_result[12]), .A1(n2920), .B0(
Sgf_normalized_result[11]), .B1(n2919), .Y(n2867) );
AOI22X1TS U4731 ( .A0(n2933), .A1(n729), .B0(n2921), .B1(n730), .Y(n2866) );
OAI211XLTS U4732 ( .A0(n2903), .A1(n5138), .B0(n2867), .C0(n2866), .Y(n363)
);
AOI22X1TS U4733 ( .A0(Add_result[9]), .A1(n2920), .B0(
Sgf_normalized_result[8]), .B1(n2919), .Y(n2869) );
AOI22X1TS U4734 ( .A0(n2933), .A1(n726), .B0(n2927), .B1(n727), .Y(n2868) );
OAI211XLTS U4735 ( .A0(n2903), .A1(n5141), .B0(n2869), .C0(n2868), .Y(n360)
);
AOI22X1TS U4736 ( .A0(Add_result[13]), .A1(n2920), .B0(
Sgf_normalized_result[12]), .B1(n2919), .Y(n2871) );
AOI22X1TS U4737 ( .A0(n2933), .A1(n730), .B0(n2921), .B1(n731), .Y(n2870) );
AOI22X1TS U4738 ( .A0(Add_result[4]), .A1(n2914), .B0(
Sgf_normalized_result[3]), .B1(n2919), .Y(n2873) );
AOI22X1TS U4739 ( .A0(n2933), .A1(n721), .B0(n2927), .B1(n722), .Y(n2872) );
OAI211XLTS U4740 ( .A0(n2903), .A1(n5146), .B0(n2873), .C0(n2872), .Y(n355)
);
AOI22X1TS U4741 ( .A0(Add_result[8]), .A1(n2920), .B0(
Sgf_normalized_result[7]), .B1(n2919), .Y(n2875) );
AOI22X1TS U4742 ( .A0(n2933), .A1(n725), .B0(n2921), .B1(n726), .Y(n2874) );
OAI211XLTS U4743 ( .A0(n2903), .A1(n5142), .B0(n2875), .C0(n2874), .Y(n359)
);
AOI22X1TS U4744 ( .A0(Add_result[21]), .A1(n2920), .B0(
Sgf_normalized_result[20]), .B1(n2906), .Y(n2878) );
BUFX4TS U4745 ( .A(n2876), .Y(n2928) );
AOI22X1TS U4746 ( .A0(n2928), .A1(n735), .B0(n2907), .B1(P_Sgf[73]), .Y(
n2877) );
OAI211XLTS U4747 ( .A0(n2913), .A1(n5129), .B0(n2878), .C0(n2877), .Y(n372)
);
AOI22X1TS U4748 ( .A0(Add_result[18]), .A1(n2920), .B0(
Sgf_normalized_result[17]), .B1(n2906), .Y(n2880) );
AOI22X1TS U4749 ( .A0(n2928), .A1(P_Sgf[69]), .B0(n2907), .B1(n734), .Y(
n2879) );
OAI211XLTS U4750 ( .A0(n2910), .A1(n5132), .B0(n2880), .C0(n2879), .Y(n369)
);
AOI22X1TS U4751 ( .A0(Add_result[22]), .A1(n2920), .B0(
Sgf_normalized_result[21]), .B1(n2906), .Y(n2882) );
AOI22X1TS U4752 ( .A0(n2928), .A1(P_Sgf[73]), .B0(n2907), .B1(n736), .Y(
n2881) );
OAI211XLTS U4753 ( .A0(n2913), .A1(n5128), .B0(n2882), .C0(n2881), .Y(n373)
);
AOI22X1TS U4754 ( .A0(Add_result[15]), .A1(n2920), .B0(
Sgf_normalized_result[14]), .B1(n2906), .Y(n2884) );
AOI22X1TS U4755 ( .A0(n2928), .A1(n732), .B0(n2907), .B1(P_Sgf[67]), .Y(
n2883) );
OAI211XLTS U4756 ( .A0(n2903), .A1(n5135), .B0(n2884), .C0(n2883), .Y(n366)
);
AOI22X1TS U4757 ( .A0(Add_result[20]), .A1(n2920), .B0(
Sgf_normalized_result[19]), .B1(n2906), .Y(n2886) );
AOI22X1TS U4758 ( .A0(n2928), .A1(P_Sgf[71]), .B0(n2907), .B1(n735), .Y(
n2885) );
OAI211XLTS U4759 ( .A0(n2910), .A1(n5130), .B0(n2886), .C0(n2885), .Y(n371)
);
AOI22X1TS U4760 ( .A0(Add_result[19]), .A1(n2920), .B0(
Sgf_normalized_result[18]), .B1(n2906), .Y(n2888) );
AOI22X1TS U4761 ( .A0(n2928), .A1(n734), .B0(n2907), .B1(P_Sgf[71]), .Y(
n2887) );
OAI211XLTS U4762 ( .A0(n2913), .A1(n5131), .B0(n2888), .C0(n2887), .Y(n370)
);
AOI22X1TS U4763 ( .A0(Add_result[49]), .A1(n2926), .B0(
Sgf_normalized_result[48]), .B1(n2822), .Y(n2890) );
AOI22X1TS U4764 ( .A0(n2928), .A1(n752), .B0(n2921), .B1(n753), .Y(n2889) );
OAI211XLTS U4765 ( .A0(n2903), .A1(n5101), .B0(n2890), .C0(n2889), .Y(n400)
);
AOI22X1TS U4766 ( .A0(Add_result[17]), .A1(n2920), .B0(
Sgf_normalized_result[16]), .B1(n2906), .Y(n2892) );
AOI22X1TS U4767 ( .A0(n2928), .A1(n733), .B0(n2907), .B1(P_Sgf[69]), .Y(
n2891) );
OAI211XLTS U4768 ( .A0(n2910), .A1(n5133), .B0(n2892), .C0(n2891), .Y(n368)
);
AOI22X1TS U4769 ( .A0(Add_result[16]), .A1(n2920), .B0(
Sgf_normalized_result[15]), .B1(n2906), .Y(n2894) );
AOI22X1TS U4770 ( .A0(n2928), .A1(P_Sgf[67]), .B0(n2907), .B1(n733), .Y(
n2893) );
OAI211XLTS U4771 ( .A0(n2913), .A1(n5134), .B0(n2894), .C0(n2893), .Y(n367)
);
AOI22X1TS U4772 ( .A0(Add_result[25]), .A1(n2920), .B0(
Sgf_normalized_result[24]), .B1(n2906), .Y(n2896) );
AOI22X1TS U4773 ( .A0(n2928), .A1(n737), .B0(n2907), .B1(P_Sgf[77]), .Y(
n2895) );
OAI211XLTS U4774 ( .A0(n2910), .A1(n5125), .B0(n2896), .C0(n2895), .Y(n376)
);
AOI22X1TS U4775 ( .A0(Add_result[24]), .A1(n2920), .B0(
Sgf_normalized_result[23]), .B1(n2906), .Y(n2898) );
AOI22X1TS U4776 ( .A0(n2928), .A1(P_Sgf[75]), .B0(n2907), .B1(n737), .Y(
n2897) );
OAI211XLTS U4777 ( .A0(n2913), .A1(n5126), .B0(n2898), .C0(n2897), .Y(n375)
);
AOI22X1TS U4778 ( .A0(Add_result[47]), .A1(n2926), .B0(
Sgf_normalized_result[46]), .B1(n2822), .Y(n2900) );
AOI22X1TS U4779 ( .A0(n2928), .A1(n751), .B0(n2927), .B1(P_Sgf[99]), .Y(
n2899) );
OAI211XLTS U4780 ( .A0(n2910), .A1(n5103), .B0(n2900), .C0(n2899), .Y(n398)
);
AOI22X1TS U4781 ( .A0(Add_result[14]), .A1(n2920), .B0(
Sgf_normalized_result[13]), .B1(n2919), .Y(n2902) );
AOI22X1TS U4782 ( .A0(n2928), .A1(n731), .B0(n2907), .B1(n732), .Y(n2901) );
OAI211XLTS U4783 ( .A0(n2903), .A1(n5136), .B0(n2902), .C0(n2901), .Y(n365)
);
AOI22X1TS U4784 ( .A0(Add_result[26]), .A1(n2914), .B0(
Sgf_normalized_result[25]), .B1(n2906), .Y(n2905) );
AOI22X1TS U4785 ( .A0(n2928), .A1(P_Sgf[77]), .B0(n2907), .B1(n738), .Y(
n2904) );
OAI211XLTS U4786 ( .A0(n2913), .A1(n5124), .B0(n2905), .C0(n2904), .Y(n377)
);
AOI22X1TS U4787 ( .A0(Add_result[23]), .A1(n2920), .B0(
Sgf_normalized_result[22]), .B1(n2906), .Y(n2909) );
AOI22X1TS U4788 ( .A0(n2928), .A1(n736), .B0(n2921), .B1(P_Sgf[75]), .Y(
n2908) );
OAI211XLTS U4789 ( .A0(n2910), .A1(n5127), .B0(n2909), .C0(n2908), .Y(n374)
);
AOI22X1TS U4790 ( .A0(Add_result[45]), .A1(n2926), .B0(
Sgf_normalized_result[44]), .B1(n2822), .Y(n2912) );
AOI22X1TS U4791 ( .A0(n2928), .A1(n750), .B0(n2921), .B1(P_Sgf[97]), .Y(
n2911) );
OAI211XLTS U4792 ( .A0(n2913), .A1(n5105), .B0(n2912), .C0(n2911), .Y(n396)
);
AOI22X1TS U4793 ( .A0(Add_result[3]), .A1(n2914), .B0(
Sgf_normalized_result[2]), .B1(n2919), .Y(n2916) );
AOI22X1TS U4794 ( .A0(n2933), .A1(n720), .B0(n2927), .B1(n721), .Y(n2915) );
OAI211XLTS U4795 ( .A0(n2931), .A1(n5097), .B0(n2916), .C0(n2915), .Y(n354)
);
AOI22X1TS U4796 ( .A0(Add_result[40]), .A1(n2926), .B0(
Sgf_normalized_result[39]), .B1(n2919), .Y(n2918) );
AOI22X1TS U4797 ( .A0(n2933), .A1(P_Sgf[91]), .B0(n2927), .B1(n748), .Y(
n2917) );
OAI211XLTS U4798 ( .A0(n2931), .A1(n5110), .B0(n2918), .C0(n2917), .Y(n391)
);
AOI22X1TS U4799 ( .A0(Add_result[2]), .A1(n2920), .B0(
Sgf_normalized_result[1]), .B1(n2919), .Y(n2923) );
AOI22X1TS U4800 ( .A0(n2933), .A1(P_Sgf[53]), .B0(n2927), .B1(n720), .Y(
n2922) );
OAI211XLTS U4801 ( .A0(n2931), .A1(n5098), .B0(n2923), .C0(n2922), .Y(n353)
);
AOI22X1TS U4802 ( .A0(Add_result[42]), .A1(n2926), .B0(
Sgf_normalized_result[41]), .B1(n2822), .Y(n2925) );
AOI22X1TS U4803 ( .A0(n2928), .A1(P_Sgf[93]), .B0(n2927), .B1(n749), .Y(
n2924) );
OAI211XLTS U4804 ( .A0(n2931), .A1(n5108), .B0(n2925), .C0(n2924), .Y(n393)
);
AOI22X1TS U4805 ( .A0(Add_result[41]), .A1(n2926), .B0(
Sgf_normalized_result[40]), .B1(n2822), .Y(n2930) );
AOI22X1TS U4806 ( .A0(n2928), .A1(n748), .B0(n2921), .B1(P_Sgf[93]), .Y(
n2929) );
AOI22X1TS U4807 ( .A0(FSM_selector_C), .A1(Add_result[52]), .B0(P_Sgf[104]),
.B1(n5074), .Y(n4953) );
AOI22X1TS U4808 ( .A0(n716), .A1(n2932), .B0(Sgf_normalized_result[51]),
.B1(n2822), .Y(n2935) );
NAND2X1TS U4809 ( .A(n2933), .B(n719), .Y(n2934) );
OAI211XLTS U4810 ( .A0(n4955), .A1(n4953), .B0(n2935), .C0(n2934), .Y(n403)
);
NOR2X1TS U4811 ( .A(n5070), .B(n5072), .Y(n3059) );
NAND3XLTS U4812 ( .A(n3059), .B(n5073), .C(n5181), .Y(n2936) );
INVX2TS U4813 ( .A(n2936), .Y(ready) );
INVX2TS U4814 ( .A(DP_OP_31J39_122_605_n42), .Y(n4901) );
OAI21XLTS U4815 ( .A0(n5072), .A1(n4904), .B0(FS_Module_state_reg[3]), .Y(
n2937) );
OAI211XLTS U4816 ( .A0(n5099), .A1(n4901), .B0(n2937), .C0(n2822), .Y(n607)
);
CLKAND2X2TS U4817 ( .A(n4048), .B(n4072), .Y(n2938) );
AOI21X1TS U4818 ( .A0(n4073), .A1(n3233), .B0(n2938), .Y(n2939) );
OAI21X1TS U4819 ( .A0(n3237), .A1(n4075), .B0(n2939), .Y(
Sgf_operation_mult_x_1_n3433) );
CLKAND2X2TS U4820 ( .A(n4048), .B(n3233), .Y(n2940) );
AOI21X1TS U4821 ( .A0(n4073), .A1(n2942), .B0(n2940), .Y(n2941) );
OAI21XLTS U4822 ( .A0(n628), .A1(n3203), .B0(n2941), .Y(
Sgf_operation_mult_x_1_n3434) );
CLKAND2X2TS U4823 ( .A(n3295), .B(n2942), .Y(n2943) );
AOI21X1TS U4824 ( .A0(n4073), .A1(n2946), .B0(n2943), .Y(n2944) );
OAI21X1TS U4825 ( .A0(n2945), .A1(n3203), .B0(n2944), .Y(
Sgf_operation_mult_x_1_n1346) );
INVX2TS U4826 ( .A(Sgf_operation_mult_x_1_n1346), .Y(
Sgf_operation_mult_x_1_n1351) );
CLKAND2X2TS U4827 ( .A(n3295), .B(n2946), .Y(n2947) );
AOI21X1TS U4828 ( .A0(n4073), .A1(n3184), .B0(n2947), .Y(n2948) );
OAI21X1TS U4829 ( .A0(n626), .A1(n3203), .B0(n2948), .Y(
Sgf_operation_mult_x_1_n3435) );
CLKAND2X2TS U4830 ( .A(n3295), .B(n2954), .Y(n2949) );
AOI21X1TS U4831 ( .A0(n4073), .A1(n2950), .B0(n2949), .Y(n2951) );
OAI21X1TS U4832 ( .A0(n2952), .A1(n3203), .B0(n2951), .Y(
Sgf_operation_mult_x_1_n3438) );
CLKAND2X2TS U4833 ( .A(n3227), .B(n3201), .Y(n2953) );
AOI21X1TS U4834 ( .A0(n4073), .A1(n2954), .B0(n2953), .Y(n2955) );
OAI21X1TS U4835 ( .A0(n3914), .A1(n4042), .B0(n2955), .Y(
Sgf_operation_mult_x_1_n3437) );
INVX2TS U4836 ( .A(Sgf_operation_mult_x_1_n1383), .Y(
Sgf_operation_mult_x_1_n1391) );
INVX4TS U4837 ( .A(n4041), .Y(n3298) );
CLKAND2X2TS U4838 ( .A(n3227), .B(n2956), .Y(n2957) );
AOI21X1TS U4839 ( .A0(n3298), .A1(n3848), .B0(n2957), .Y(n2958) );
OAI21X1TS U4840 ( .A0(n630), .A1(n4075), .B0(n2958), .Y(
Sgf_operation_mult_x_1_n3439) );
CLKAND2X2TS U4841 ( .A(n3227), .B(n3787), .Y(n2959) );
AOI21X1TS U4842 ( .A0(n3230), .A1(n2962), .B0(n2959), .Y(n2960) );
OAI21X1TS U4843 ( .A0(n2961), .A1(n4075), .B0(n2960), .Y(
Sgf_operation_mult_x_1_n3441) );
CLKAND2X2TS U4844 ( .A(n3227), .B(n2962), .Y(n2963) );
AOI21X1TS U4845 ( .A0(n3298), .A1(n3883), .B0(n2963), .Y(n2964) );
OAI21X1TS U4846 ( .A0(n631), .A1(n4042), .B0(n2964), .Y(
Sgf_operation_mult_x_1_n3442) );
AOI21X1TS U4847 ( .A0(n3230), .A1(n2968), .B0(n2965), .Y(n2966) );
OAI21X1TS U4848 ( .A0(n2967), .A1(n4042), .B0(n2966), .Y(
Sgf_operation_mult_x_1_n1438) );
INVX2TS U4849 ( .A(Sgf_operation_mult_x_1_n1438), .Y(
Sgf_operation_mult_x_1_n1449) );
AOI21X1TS U4850 ( .A0(n3230), .A1(n3888), .B0(n2969), .Y(n2970) );
OAI21X1TS U4851 ( .A0(n635), .A1(n4075), .B0(n2970), .Y(
Sgf_operation_mult_x_1_n3443) );
AOI21X1TS U4852 ( .A0(n3230), .A1(n2981), .B0(n2971), .Y(n2972) );
OAI21X1TS U4853 ( .A0(n2973), .A1(n4075), .B0(n2972), .Y(
Sgf_operation_mult_x_1_n3445) );
NOR2X1TS U4854 ( .A(n4137), .B(n3300), .Y(Sgf_operation_mult_x_1_n3467) );
AOI21X1TS U4855 ( .A0(n2976), .A1(n2975), .B0(n2974), .Y(n2980) );
NAND2X1TS U4856 ( .A(n2978), .B(n2977), .Y(n2979) );
XNOR2X1TS U4857 ( .A(n2980), .B(n2979), .Y(n3464) );
AOI21X1TS U4858 ( .A0(n3298), .A1(n3893), .B0(n2982), .Y(n2983) );
OAI21X1TS U4859 ( .A0(n633), .A1(n4042), .B0(n2983), .Y(
Sgf_operation_mult_x_1_n3446) );
AOI21X1TS U4860 ( .A0(n3298), .A1(n3262), .B0(n2984), .Y(n2985) );
OAI21X1TS U4861 ( .A0(n3266), .A1(n4075), .B0(n2985), .Y(
Sgf_operation_mult_x_1_n1511) );
INVX2TS U4862 ( .A(Sgf_operation_mult_x_1_n1511), .Y(
Sgf_operation_mult_x_1_n1525) );
NAND2X1TS U4863 ( .A(n757), .B(n2986), .Y(n2988) );
XNOR2X1TS U4864 ( .A(n2988), .B(n2987), .Y(n3074) );
AOI21X1TS U4865 ( .A0(n3035), .A1(n4133), .B0(n2989), .Y(n2990) );
OAI21X1TS U4866 ( .A0(n645), .A1(n4075), .B0(n2990), .Y(
Sgf_operation_mult_x_1_n3465) );
NAND2X1TS U4867 ( .A(n3295), .B(n4133), .Y(n2991) );
OAI21X1TS U4868 ( .A0(n3069), .A1(n4042), .B0(n2991), .Y(
Sgf_operation_mult_x_1_n3466) );
AOI21X1TS U4869 ( .A0(n3298), .A1(n4028), .B0(n2992), .Y(n2993) );
OAI21X1TS U4870 ( .A0(n4142), .A1(n4042), .B0(n2993), .Y(
Sgf_operation_mult_x_1_n3464) );
AOI21X1TS U4871 ( .A0(n3298), .A1(n4090), .B0(n2994), .Y(n2995) );
OAI21X1TS U4872 ( .A0(n4120), .A1(n4042), .B0(n2995), .Y(
Sgf_operation_mult_x_1_n3463) );
AOI21X1TS U4873 ( .A0(n3298), .A1(n3720), .B0(n2996), .Y(n2997) );
OAI21X1TS U4874 ( .A0(n3662), .A1(n4042), .B0(n2997), .Y(
Sgf_operation_mult_x_1_n3461) );
AOI21X1TS U4875 ( .A0(n3298), .A1(n3808), .B0(n2998), .Y(n2999) );
OAI21X1TS U4876 ( .A0(n642), .A1(n4075), .B0(n2999), .Y(
Sgf_operation_mult_x_1_n3458) );
AOI21X1TS U4877 ( .A0(n3298), .A1(n3289), .B0(n3000), .Y(n3001) );
OAI21X1TS U4878 ( .A0(n3002), .A1(n3300), .B0(n3001), .Y(
Sgf_operation_mult_x_1_n1836) );
INVX2TS U4879 ( .A(Sgf_operation_mult_x_1_n1836), .Y(
Sgf_operation_mult_x_1_n1859) );
AOI21X1TS U4880 ( .A0(n3298), .A1(n3717), .B0(n3003), .Y(n3004) );
OAI21X1TS U4881 ( .A0(n644), .A1(n3300), .B0(n3004), .Y(
Sgf_operation_mult_x_1_n3460) );
AOI21X1TS U4882 ( .A0(n3035), .A1(n3015), .B0(n3005), .Y(n3006) );
OAI21X1TS U4883 ( .A0(n641), .A1(n4042), .B0(n3006), .Y(
Sgf_operation_mult_x_1_n3452) );
AOI21X1TS U4884 ( .A0(n3035), .A1(n3008), .B0(n3007), .Y(n3009) );
OAI21X1TS U4885 ( .A0(n636), .A1(n4075), .B0(n3009), .Y(
Sgf_operation_mult_x_1_n3451) );
AOI21X1TS U4886 ( .A0(n3035), .A1(n3012), .B0(n3010), .Y(n3011) );
OAI21X1TS U4887 ( .A0(n639), .A1(n4042), .B0(n3011), .Y(
Sgf_operation_mult_x_1_n3454) );
AOI21X1TS U4888 ( .A0(n3035), .A1(n3278), .B0(n3013), .Y(n3014) );
OAI21X1TS U4889 ( .A0(n3978), .A1(n3300), .B0(n3014), .Y(
Sgf_operation_mult_x_1_n1710) );
INVX2TS U4890 ( .A(Sgf_operation_mult_x_1_n1710), .Y(
Sgf_operation_mult_x_1_n1730) );
AOI21X1TS U4891 ( .A0(n3035), .A1(n3017), .B0(n3016), .Y(n3018) );
OAI21X1TS U4892 ( .A0(n3969), .A1(n3300), .B0(n3018), .Y(
Sgf_operation_mult_x_1_n3453) );
AOI21X1TS U4893 ( .A0(n3035), .A1(n3020), .B0(n3019), .Y(n3021) );
OAI21X1TS U4894 ( .A0(n3949), .A1(n3300), .B0(n3021), .Y(
Sgf_operation_mult_x_1_n1601) );
INVX2TS U4895 ( .A(Sgf_operation_mult_x_1_n1601), .Y(
Sgf_operation_mult_x_1_n1618) );
INVX2TS U4896 ( .A(n3022), .Y(Sgf_operation_mult_x_1_n1673) );
AOI21X1TS U4897 ( .A0(n4073), .A1(n3024), .B0(n3023), .Y(n3025) );
OAI21X1TS U4898 ( .A0(n2692), .A1(n4042), .B0(n3025), .Y(
Sgf_operation_mult_x_1_n3450) );
AOI21X1TS U4899 ( .A0(n3298), .A1(n4080), .B0(n3026), .Y(n3027) );
OAI21X1TS U4900 ( .A0(n4155), .A1(n4042), .B0(n3027), .Y(
Sgf_operation_mult_x_1_n3462) );
AOI21X1TS U4901 ( .A0(n4073), .A1(n3272), .B0(n3028), .Y(n3029) );
OAI21X1TS U4902 ( .A0(n3940), .A1(n4075), .B0(n3029), .Y(
Sgf_operation_mult_x_1_n3449) );
AOI21X1TS U4903 ( .A0(n3035), .A1(n3031), .B0(n3030), .Y(n3032) );
OAI21X1TS U4904 ( .A0(n643), .A1(n4042), .B0(n3032), .Y(
Sgf_operation_mult_x_1_n3457) );
AOI21X1TS U4905 ( .A0(n3035), .A1(n3034), .B0(n3033), .Y(n3036) );
OAI21X1TS U4906 ( .A0(n637), .A1(n4042), .B0(n3036), .Y(
Sgf_operation_mult_x_1_n3455) );
NOR4X1TS U4907 ( .A(P_Sgf[3]), .B(P_Sgf[2]), .C(P_Sgf[1]), .D(P_Sgf[0]), .Y(
n3052) );
NOR4X1TS U4908 ( .A(P_Sgf[49]), .B(P_Sgf[9]), .C(P_Sgf[5]), .D(P_Sgf[4]),
.Y(n3051) );
NOR4X1TS U4909 ( .A(P_Sgf[31]), .B(P_Sgf[38]), .C(P_Sgf[37]), .D(P_Sgf[36]),
.Y(n3050) );
OR4X2TS U4910 ( .A(P_Sgf[28]), .B(P_Sgf[34]), .C(P_Sgf[39]), .D(P_Sgf[35]),
.Y(n3048) );
OR4X2TS U4911 ( .A(P_Sgf[30]), .B(P_Sgf[32]), .C(P_Sgf[29]), .D(P_Sgf[33]),
.Y(n3047) );
NOR4X1TS U4912 ( .A(P_Sgf[50]), .B(P_Sgf[51]), .C(P_Sgf[46]), .D(P_Sgf[6]),
.Y(n3040) );
NOR4X1TS U4913 ( .A(P_Sgf[47]), .B(P_Sgf[48]), .C(P_Sgf[44]), .D(P_Sgf[43]),
.Y(n3039) );
NOR4X1TS U4914 ( .A(P_Sgf[45]), .B(P_Sgf[40]), .C(P_Sgf[42]), .D(P_Sgf[41]),
.Y(n3038) );
NOR4X1TS U4915 ( .A(P_Sgf[8]), .B(P_Sgf[10]), .C(P_Sgf[12]), .D(P_Sgf[14]),
.Y(n3037) );
NAND4XLTS U4916 ( .A(n3040), .B(n3039), .C(n3038), .D(n3037), .Y(n3046) );
NOR4X1TS U4917 ( .A(P_Sgf[7]), .B(P_Sgf[15]), .C(P_Sgf[13]), .D(P_Sgf[11]),
.Y(n3044) );
NOR4X1TS U4918 ( .A(P_Sgf[18]), .B(P_Sgf[17]), .C(P_Sgf[25]), .D(P_Sgf[19]),
.Y(n3043) );
NOR4X1TS U4919 ( .A(P_Sgf[16]), .B(P_Sgf[22]), .C(P_Sgf[21]), .D(P_Sgf[20]),
.Y(n3042) );
NAND4XLTS U4920 ( .A(n3044), .B(n3043), .C(n3042), .D(n3041), .Y(n3045) );
NOR4X1TS U4921 ( .A(n3048), .B(n3047), .C(n3046), .D(n3045), .Y(n3049) );
NAND4XLTS U4922 ( .A(n3052), .B(n3051), .C(n3050), .D(n3049), .Y(n3054) );
MXI2X1TS U4923 ( .A(n3055), .B(round_mode[1]), .S0(round_mode[0]), .Y(n3053)
);
OAI211X1TS U4924 ( .A0(n3055), .A1(round_mode[1]), .B0(n3054), .C0(n3053),
.Y(n3057) );
AOI32X1TS U4925 ( .A0(FS_Module_state_reg[3]), .A1(n4903), .A2(n3057), .B0(
n5150), .B1(n4903), .Y(n3058) );
OAI31X1TS U4926 ( .A0(n5150), .A1(n3059), .A2(n5073), .B0(n3058), .Y(n605)
);
AOI222X1TS U4927 ( .A0(n3465), .A1(n3264), .B0(n3472), .B1(n3263), .C0(n3468), .C1(n3262), .Y(n3060) );
XOR2X1TS U4928 ( .A(n3061), .B(n3476), .Y(n3068) );
AOI21X1TS U4929 ( .A0(n4073), .A1(n3872), .B0(n3062), .Y(n3063) );
OAI21X1TS U4930 ( .A0(n638), .A1(n4075), .B0(n3063), .Y(n3067) );
AOI21X1TS U4931 ( .A0(n3687), .A1(n4053), .B0(n3688), .Y(n3064) );
XOR2X1TS U4932 ( .A(n3065), .B(n3404), .Y(n3066) );
CMPR32X2TS U4933 ( .A(n3068), .B(n3067), .C(n3066), .CO(
Sgf_operation_mult_x_1_n1568), .S(Sgf_operation_mult_x_1_n1569) );
AOI22X1TS U4934 ( .A0(n3732), .A1(n4028), .B0(n3749), .B1(n4129), .Y(n3070)
);
XOR2X1TS U4935 ( .A(n3071), .B(n3746), .Y(n3420) );
NAND2X1TS U4936 ( .A(n3732), .B(n4133), .Y(n3072) );
XOR2X1TS U4937 ( .A(n3073), .B(n3746), .Y(n3423) );
BUFX4TS U4938 ( .A(Op_MY[1]), .Y(n4125) );
INVX4TS U4939 ( .A(n4137), .Y(n4124) );
XOR2X1TS U4940 ( .A(n3077), .B(n3746), .Y(n3078) );
ADDHXLTS U4941 ( .A(n3079), .B(n3078), .CO(Sgf_operation_mult_x_1_n2673),
.S(n3086) );
AOI222X1TS U4942 ( .A0(n2424), .A1(n4153), .B0(n3779), .B1(n4152), .C0(n3764), .C1(n4151), .Y(n3080) );
XOR2X1TS U4943 ( .A(n3081), .B(n3783), .Y(n3085) );
XOR2X1TS U4944 ( .A(n3083), .B(n4109), .Y(n3084) );
CMPR32X2TS U4945 ( .A(n3086), .B(n3085), .C(n3084), .CO(
Sgf_operation_mult_x_1_n2671), .S(Sgf_operation_mult_x_1_n2672) );
AOI22X1TS U4946 ( .A0(n3508), .A1(n4028), .B0(n3273), .B1(n4129), .Y(n3087)
);
XOR2X1TS U4947 ( .A(n3088), .B(n3525), .Y(n3340) );
NAND2X1TS U4948 ( .A(n3508), .B(n4133), .Y(n3089) );
XOR2X1TS U4949 ( .A(n3090), .B(n3525), .Y(n3343) );
XOR2X1TS U4950 ( .A(n3092), .B(n3525), .Y(n3093) );
ADDHXLTS U4951 ( .A(n3094), .B(n3093), .CO(Sgf_operation_mult_x_1_n2289),
.S(n3101) );
AOI222X1TS U4952 ( .A0(n1452), .A1(n4153), .B0(n3553), .B1(n4152), .C0(n3552), .C1(n4080), .Y(n3095) );
XOR2X1TS U4953 ( .A(n3096), .B(n3557), .Y(n3100) );
XOR2X1TS U4954 ( .A(n3098), .B(n3634), .Y(n3099) );
CMPR32X2TS U4955 ( .A(n3101), .B(n3100), .C(n3099), .CO(
Sgf_operation_mult_x_1_n2287), .S(Sgf_operation_mult_x_1_n2288) );
AOI22X1TS U4956 ( .A0(n3455), .A1(n4028), .B0(n4052), .B1(n4129), .Y(n3102)
);
XOR2X1TS U4957 ( .A(n3103), .B(n3282), .Y(n3320) );
NAND2X1TS U4958 ( .A(n3455), .B(n4133), .Y(n3104) );
XOR2X1TS U4959 ( .A(n3105), .B(n3282), .Y(n3323) );
XOR2X1TS U4960 ( .A(n3107), .B(n3282), .Y(n3108) );
ADDHXLTS U4961 ( .A(n3109), .B(n3108), .CO(Sgf_operation_mult_x_1_n2148),
.S(n3116) );
AOI222X1TS U4962 ( .A0(n3501), .A1(n4153), .B0(n3500), .B1(n4152), .C0(n3499), .C1(n4080), .Y(n3110) );
XOR2X1TS U4963 ( .A(n3111), .B(n3504), .Y(n3115) );
XOR2X1TS U4964 ( .A(n3113), .B(n3586), .Y(n3114) );
CMPR32X2TS U4965 ( .A(n3116), .B(n3115), .C(n3114), .CO(
Sgf_operation_mult_x_1_n2146), .S(Sgf_operation_mult_x_1_n2147) );
AOI22X1TS U4966 ( .A0(n3622), .A1(n4028), .B0(n3637), .B1(n4129), .Y(n3117)
);
XOR2X1TS U4967 ( .A(n3118), .B(n3634), .Y(n3380) );
NAND2X1TS U4968 ( .A(n3622), .B(n4133), .Y(n3119) );
XOR2X1TS U4969 ( .A(n3120), .B(n3634), .Y(n3383) );
XOR2X1TS U4970 ( .A(n3123), .B(n3634), .Y(n3124) );
ADDHXLTS U4971 ( .A(n3125), .B(n3124), .CO(Sgf_operation_mult_x_1_n2517),
.S(n3134) );
AOI222X1TS U4972 ( .A0(n2695), .A1(n4153), .B0(n3658), .B1(n4152), .C0(n2755), .C1(n4080), .Y(n3126) );
XOR2X1TS U4973 ( .A(n3127), .B(n3663), .Y(n3133) );
OAI21X1TS U4974 ( .A0(n3949), .A1(n3829), .B0(n3130), .Y(n3131) );
XOR2X1TS U4975 ( .A(n3131), .B(n3846), .Y(n3132) );
CMPR32X2TS U4976 ( .A(n3134), .B(n3133), .C(n3132), .CO(
Sgf_operation_mult_x_1_n2515), .S(Sgf_operation_mult_x_1_n2516) );
AOI22X1TS U4977 ( .A0(n3665), .A1(n4028), .B0(n3688), .B1(n4129), .Y(n3135)
);
XOR2X1TS U4978 ( .A(n3136), .B(n3685), .Y(n3400) );
NAND2X1TS U4979 ( .A(n3665), .B(n4129), .Y(n3137) );
XOR2X1TS U4980 ( .A(n3138), .B(n3685), .Y(n3403) );
XOR2X1TS U4981 ( .A(n3141), .B(n3685), .Y(n3142) );
ADDHXLTS U4982 ( .A(n3143), .B(n3142), .CO(Sgf_operation_mult_x_1_n2604),
.S(n3150) );
AOI222X1TS U4983 ( .A0(n3713), .A1(n4153), .B0(n3722), .B1(n4152), .C0(n2751), .C1(n4080), .Y(n3144) );
XOR2X1TS U4984 ( .A(n3145), .B(n3726), .Y(n3149) );
XOR2X1TS U4985 ( .A(n3147), .B(n3846), .Y(n3148) );
CMPR32X2TS U4986 ( .A(n3150), .B(n3149), .C(n3148), .CO(
Sgf_operation_mult_x_1_n2602), .S(Sgf_operation_mult_x_1_n2603) );
AOI22X1TS U4987 ( .A0(n3788), .A1(n4028), .B0(n3151), .B1(n4129), .Y(n3152)
);
XOR2X1TS U4988 ( .A(n3153), .B(n3814), .Y(n3440) );
NAND2X1TS U4989 ( .A(n3788), .B(n4133), .Y(n3154) );
XOR2X1TS U4990 ( .A(n3155), .B(n3814), .Y(n3443) );
XOR2X1TS U4991 ( .A(n3159), .B(n3814), .Y(n3160) );
ADDHXLTS U4992 ( .A(n3161), .B(n3160), .CO(Sgf_operation_mult_x_1_n2724),
.S(n3168) );
AOI222X1TS U4993 ( .A0(n3831), .A1(n4153), .B0(n3842), .B1(n4152), .C0(n3128), .C1(n4151), .Y(n3162) );
XOR2X1TS U4994 ( .A(n3163), .B(n3846), .Y(n3167) );
XOR2X1TS U4995 ( .A(n3165), .B(n754), .Y(n3166) );
CMPR32X2TS U4996 ( .A(n3168), .B(n3167), .C(n3166), .CO(
Sgf_operation_mult_x_1_n2722), .S(Sgf_operation_mult_x_1_n2723) );
AOI22X1TS U4997 ( .A0(n3590), .A1(n4028), .B0(n3589), .B1(n4129), .Y(n3169)
);
XOR2X1TS U4998 ( .A(n3170), .B(n3586), .Y(n3360) );
NAND2X1TS U4999 ( .A(n3561), .B(n4133), .Y(n3171) );
XOR2X1TS U5000 ( .A(n3172), .B(n3586), .Y(n3363) );
XOR2X1TS U5001 ( .A(n3174), .B(n3586), .Y(n3175) );
ADDHXLTS U5002 ( .A(n3176), .B(n3175), .CO(Sgf_operation_mult_x_1_n2412),
.S(n3183) );
XOR2X1TS U5003 ( .A(n3178), .B(n3620), .Y(n3182) );
OAI21X1TS U5004 ( .A0(n3949), .A1(n3766), .B0(n3179), .Y(n3180) );
XOR2X1TS U5005 ( .A(n3180), .B(n3783), .Y(n3181) );
CMPR32X2TS U5006 ( .A(n3183), .B(n3182), .C(n3181), .CO(
Sgf_operation_mult_x_1_n2410), .S(Sgf_operation_mult_x_1_n2411) );
CLKAND2X2TS U5007 ( .A(n3295), .B(n3184), .Y(n3185) );
AOI21X1TS U5008 ( .A0(n4073), .A1(n3199), .B0(n3185), .Y(n3186) );
OAI21X1TS U5009 ( .A0(n3909), .A1(n3203), .B0(n3186), .Y(n3190) );
AOI222X1TS U5010 ( .A0(n3473), .A1(n3235), .B0(n4052), .B1(n3234), .C0(n4054), .C1(n3233), .Y(n3187) );
XOR2X1TS U5011 ( .A(n3188), .B(n4062), .Y(n3189) );
CMPR32X2TS U5012 ( .A(n5092), .B(n3190), .C(n3189), .CO(
Sgf_operation_mult_x_1_n1355), .S(Sgf_operation_mult_x_1_n1356) );
INVX2TS U5013 ( .A(n3190), .Y(n3197) );
AOI21X1TS U5014 ( .A0(n3518), .A1(n4053), .B0(n3273), .Y(n3191) );
XOR2X1TS U5015 ( .A(n3193), .B(n3344), .Y(n3198) );
XOR2X1TS U5016 ( .A(n3195), .B(n3344), .Y(n3196) );
CMPR32X2TS U5017 ( .A(n3197), .B(n3198), .C(n3196), .CO(
Sgf_operation_mult_x_1_n1360), .S(Sgf_operation_mult_x_1_n1361) );
INVX2TS U5018 ( .A(n3198), .Y(n3205) );
CLKAND2X2TS U5019 ( .A(n3295), .B(n3199), .Y(n3200) );
AOI21X1TS U5020 ( .A0(n4073), .A1(n3201), .B0(n3200), .Y(n3202) );
OAI21X1TS U5021 ( .A0(n625), .A1(n3203), .B0(n3202), .Y(n3204) );
CMPR32X2TS U5022 ( .A(n3205), .B(Sgf_operation_mult_x_1_n1374), .C(n3204),
.CO(Sgf_operation_mult_x_1_n1367), .S(Sgf_operation_mult_x_1_n1368) );
CLKAND2X2TS U5023 ( .A(n3227), .B(n3848), .Y(n3206) );
AOI21X1TS U5024 ( .A0(n3230), .A1(n3222), .B0(n3206), .Y(n3207) );
OAI21X1TS U5025 ( .A0(n3208), .A1(n4075), .B0(n3207), .Y(n3213) );
AOI222X1TS U5026 ( .A0(n3508), .A1(n3235), .B0(n3273), .B1(n3234), .C0(n3518), .C1(n3233), .Y(n3209) );
XOR2X1TS U5027 ( .A(n3211), .B(n3344), .Y(n3212) );
CMPR32X2TS U5028 ( .A(n5090), .B(n3213), .C(n3212), .CO(
Sgf_operation_mult_x_1_n1398), .S(Sgf_operation_mult_x_1_n1399) );
INVX2TS U5029 ( .A(n3213), .Y(n3220) );
AOI21X1TS U5030 ( .A0(n3582), .A1(n4053), .B0(n3589), .Y(n3214) );
XOR2X1TS U5031 ( .A(n3216), .B(n3364), .Y(n3221) );
XOR2X1TS U5032 ( .A(n3218), .B(n3364), .Y(n3219) );
CMPR32X2TS U5033 ( .A(n3220), .B(n3221), .C(n3219), .CO(
Sgf_operation_mult_x_1_n1406), .S(Sgf_operation_mult_x_1_n1407) );
INVX2TS U5034 ( .A(n3221), .Y(n3226) );
CLKAND2X2TS U5035 ( .A(n3227), .B(n3222), .Y(n3223) );
AOI21X1TS U5036 ( .A0(n3298), .A1(n3787), .B0(n3223), .Y(n3224) );
OAI21X1TS U5037 ( .A0(n634), .A1(n4042), .B0(n3224), .Y(n3225) );
CMPR32X2TS U5038 ( .A(n3226), .B(Sgf_operation_mult_x_1_n1426), .C(n3225),
.CO(Sgf_operation_mult_x_1_n1416), .S(Sgf_operation_mult_x_1_n1417) );
AOI21X1TS U5039 ( .A0(n3230), .A1(n3229), .B0(n3228), .Y(n3231) );
OAI21X1TS U5040 ( .A0(n3232), .A1(n4075), .B0(n3231), .Y(n3240) );
AOI222X1TS U5041 ( .A0(n3561), .A1(n3235), .B0(n3578), .B1(n3234), .C0(n3588), .C1(n3233), .Y(n3236) );
XOR2X1TS U5042 ( .A(n3238), .B(n3364), .Y(n3239) );
CMPR32X2TS U5043 ( .A(n5086), .B(n3240), .C(n3239), .CO(
Sgf_operation_mult_x_1_n1459), .S(Sgf_operation_mult_x_1_n1460) );
INVX2TS U5044 ( .A(n3240), .Y(n3245) );
XOR2X1TS U5045 ( .A(n3242), .B(n3384), .Y(n3243) );
CMPR32X2TS U5046 ( .A(n3245), .B(n3244), .C(n3243), .CO(
Sgf_operation_mult_x_1_n1470), .S(Sgf_operation_mult_x_1_n1471) );
AOI21X1TS U5047 ( .A0(n3298), .A1(n3247), .B0(n3246), .Y(n3248) );
OAI21X1TS U5048 ( .A0(n3249), .A1(n4042), .B0(n3248), .Y(n3253) );
AOI21X1TS U5049 ( .A0(n3298), .A1(n3866), .B0(n3250), .Y(n3251) );
OAI21X1TS U5050 ( .A0(n3870), .A1(n4075), .B0(n3251), .Y(n3252) );
CMPR32X2TS U5051 ( .A(n5084), .B(n3253), .C(n3252), .CO(
Sgf_operation_mult_x_1_n1538), .S(Sgf_operation_mult_x_1_n1539) );
INVX2TS U5052 ( .A(n3253), .Y(n3257) );
XOR2X1TS U5053 ( .A(n3255), .B(n3404), .Y(n3256) );
CMPR32X2TS U5054 ( .A(n3257), .B(Sgf_operation_mult_x_1_n1570), .C(n3256),
.CO(Sgf_operation_mult_x_1_n1552), .S(Sgf_operation_mult_x_1_n1553) );
AOI222X1TS U5055 ( .A0(n3455), .A1(n3938), .B0(n4052), .B1(n3936), .C0(n4054), .C1(n3272), .Y(n3258) );
XOR2X1TS U5056 ( .A(n3259), .B(n4062), .Y(n3260) );
CMPR32X2TS U5057 ( .A(n5081), .B(n3261), .C(n3260), .CO(
Sgf_operation_mult_x_1_n1634), .S(Sgf_operation_mult_x_1_n1635) );
AOI222X1TS U5058 ( .A0(n3529), .A1(n3264), .B0(n3528), .B1(n3263), .C0(n3521), .C1(n3262), .Y(n3265) );
XOR2X1TS U5059 ( .A(n3267), .B(n3532), .Y(n3271) );
AOI21X1TS U5060 ( .A0(n3742), .A1(n4053), .B0(n3749), .Y(n3268) );
XOR2X1TS U5061 ( .A(n3269), .B(n3424), .Y(n3270) );
CMPR32X2TS U5062 ( .A(Sgf_operation_mult_x_1_n1689), .B(n3271), .C(n3270),
.CO(Sgf_operation_mult_x_1_n1670), .S(Sgf_operation_mult_x_1_n1671) );
AOI222X1TS U5063 ( .A0(n3529), .A1(n3938), .B0(n3273), .B1(n3936), .C0(n3518), .C1(n3272), .Y(n3274) );
XOR2X1TS U5064 ( .A(n3275), .B(n3344), .Y(n3276) );
CMPR32X2TS U5065 ( .A(n5082), .B(n3277), .C(n3276), .CO(
Sgf_operation_mult_x_1_n1749), .S(Sgf_operation_mult_x_1_n1750) );
OAI21X1TS U5066 ( .A0(n3978), .A1(n3281), .B0(n3280), .Y(n3283) );
XOR2X1TS U5067 ( .A(n3283), .B(n3282), .Y(n3284) );
CMPR32X2TS U5068 ( .A(n3285), .B(Sgf_operation_mult_x_1_n1812), .C(n3284),
.CO(Sgf_operation_mult_x_1_n1791), .S(Sgf_operation_mult_x_1_n1792) );
AOI21X1TS U5069 ( .A0(n3298), .A1(n3294), .B0(n3286), .Y(n3287) );
OAI21X1TS U5070 ( .A0(n3288), .A1(n3300), .B0(n3287), .Y(n3293) );
AOI21X1TS U5071 ( .A0(n3298), .A1(n3877), .B0(n3290), .Y(n3291) );
OAI21X1TS U5072 ( .A0(n640), .A1(n4042), .B0(n3291), .Y(n3292) );
CMPR32X2TS U5073 ( .A(n5083), .B(n3293), .C(n3292), .CO(
Sgf_operation_mult_x_1_n1881), .S(Sgf_operation_mult_x_1_n1882) );
INVX2TS U5074 ( .A(n3293), .Y(n3305) );
AOI21X1TS U5075 ( .A0(n3298), .A1(n3297), .B0(n3296), .Y(n3299) );
OAI21X1TS U5076 ( .A0(n4086), .A1(n3300), .B0(n3299), .Y(n3306) );
AOI222X1TS U5077 ( .A0(n3494), .A1(n3986), .B0(n3500), .B1(n3985), .C0(n3499), .C1(n3301), .Y(n3302) );
XOR2X1TS U5078 ( .A(n3303), .B(n3504), .Y(n3304) );
CMPR32X2TS U5079 ( .A(n3305), .B(n3306), .C(n3304), .CO(
Sgf_operation_mult_x_1_n1904), .S(Sgf_operation_mult_x_1_n1905) );
INVX2TS U5080 ( .A(n3306), .Y(n3313) );
XOR2X1TS U5081 ( .A(n3311), .B(n3504), .Y(n3312) );
CMPR32X2TS U5082 ( .A(n3313), .B(Sgf_operation_mult_x_1_n1954), .C(n3312),
.CO(Sgf_operation_mult_x_1_n1929), .S(Sgf_operation_mult_x_1_n1930) );
ADDHXLTS U5083 ( .A(n3315), .B(n3314), .CO(n3327), .S(
Sgf_operation_mult_x_1_n2245) );
XOR2X1TS U5084 ( .A(n3318), .B(n3504), .Y(n3326) );
ADDHXLTS U5085 ( .A(n3320), .B(n3319), .CO(n3109), .S(n3330) );
AOI222X1TS U5086 ( .A0(n3501), .A1(n4162), .B0(n3500), .B1(n4118), .C0(n3499), .C1(n4090), .Y(n3321) );
XOR2X1TS U5087 ( .A(n3322), .B(n3504), .Y(n3329) );
ADDHXLTS U5088 ( .A(n4062), .B(n3323), .CO(n3319), .S(n3333) );
AOI222X1TS U5089 ( .A0(n3501), .A1(n4151), .B0(n3500), .B1(n4140), .C0(n3499), .C1(n4139), .Y(n3324) );
XOR2X1TS U5090 ( .A(n3325), .B(n3504), .Y(n3332) );
ADDHXLTS U5091 ( .A(n3327), .B(n3326), .CO(n3331), .S(
Sgf_operation_mult_x_1_n2222) );
CMPR32X2TS U5092 ( .A(n3330), .B(n3329), .C(n3328), .CO(
Sgf_operation_mult_x_1_n2171), .S(Sgf_operation_mult_x_1_n2172) );
CMPR32X2TS U5093 ( .A(n3333), .B(n3332), .C(n3331), .CO(n3328), .S(
Sgf_operation_mult_x_1_n2197) );
ADDHXLTS U5094 ( .A(n3335), .B(n3334), .CO(n3348), .S(
Sgf_operation_mult_x_1_n2374) );
XOR2X1TS U5095 ( .A(n3338), .B(n3557), .Y(n3347) );
ADDHXLTS U5096 ( .A(n3340), .B(n3339), .CO(n3094), .S(n3351) );
AOI222X1TS U5097 ( .A0(n1452), .A1(n4162), .B0(n3553), .B1(n4118), .C0(n3552), .C1(n4090), .Y(n3341) );
XOR2X1TS U5098 ( .A(n3342), .B(n3557), .Y(n3350) );
ADDHXLTS U5099 ( .A(n3344), .B(n3343), .CO(n3339), .S(n3354) );
AOI222X1TS U5100 ( .A0(n1452), .A1(n4151), .B0(n3553), .B1(n4140), .C0(n3552), .C1(n4139), .Y(n3345) );
XOR2X1TS U5101 ( .A(n3346), .B(n3557), .Y(n3353) );
ADDHXLTS U5102 ( .A(n3348), .B(n3347), .CO(n3352), .S(
Sgf_operation_mult_x_1_n2354) );
CMPR32X2TS U5103 ( .A(n3351), .B(n3350), .C(n3349), .CO(
Sgf_operation_mult_x_1_n2309), .S(Sgf_operation_mult_x_1_n2310) );
CMPR32X2TS U5104 ( .A(n3354), .B(n3353), .C(n3352), .CO(n3349), .S(
Sgf_operation_mult_x_1_n2332) );
ADDHXLTS U5105 ( .A(n3356), .B(n3355), .CO(n3368), .S(
Sgf_operation_mult_x_1_n2485) );
XOR2X1TS U5106 ( .A(n3358), .B(n3620), .Y(n3367) );
ADDHXLTS U5107 ( .A(n3360), .B(n3359), .CO(n3176), .S(n3371) );
XOR2X1TS U5108 ( .A(n3362), .B(n3620), .Y(n3370) );
ADDHXLTS U5109 ( .A(n3364), .B(n3363), .CO(n3359), .S(n3374) );
XOR2X1TS U5110 ( .A(n3366), .B(n3620), .Y(n3373) );
ADDHXLTS U5111 ( .A(n3368), .B(n3367), .CO(n3372), .S(
Sgf_operation_mult_x_1_n2468) );
CMPR32X2TS U5112 ( .A(n3371), .B(n3370), .C(n3369), .CO(
Sgf_operation_mult_x_1_n2429), .S(Sgf_operation_mult_x_1_n2430) );
CMPR32X2TS U5113 ( .A(n3374), .B(n3373), .C(n3372), .CO(n3369), .S(
Sgf_operation_mult_x_1_n2449) );
ADDHXLTS U5114 ( .A(n3376), .B(n3375), .CO(n3388), .S(
Sgf_operation_mult_x_1_n2578) );
XOR2X1TS U5115 ( .A(n3378), .B(n3663), .Y(n3387) );
ADDHXLTS U5116 ( .A(n3380), .B(n3379), .CO(n3125), .S(n3391) );
AOI222X1TS U5117 ( .A0(n2695), .A1(n4162), .B0(n3658), .B1(n4118), .C0(n2755), .C1(n4090), .Y(n3381) );
XOR2X1TS U5118 ( .A(n3382), .B(n3663), .Y(n3390) );
ADDHXLTS U5119 ( .A(n3384), .B(n3383), .CO(n3379), .S(n3394) );
AOI222X1TS U5120 ( .A0(n2695), .A1(n4151), .B0(n3658), .B1(n4140), .C0(n2755), .C1(n4139), .Y(n3385) );
XOR2X1TS U5121 ( .A(n3386), .B(n3663), .Y(n3393) );
ADDHXLTS U5122 ( .A(n3388), .B(n3387), .CO(n3392), .S(
Sgf_operation_mult_x_1_n2564) );
CMPR32X2TS U5123 ( .A(n3391), .B(n3390), .C(n3389), .CO(
Sgf_operation_mult_x_1_n2531), .S(Sgf_operation_mult_x_1_n2532) );
CMPR32X2TS U5124 ( .A(n3394), .B(n3393), .C(n3392), .CO(n3389), .S(
Sgf_operation_mult_x_1_n2548) );
ADDHXLTS U5125 ( .A(n3396), .B(n3395), .CO(n3408), .S(
Sgf_operation_mult_x_1_n2653) );
XOR2X1TS U5126 ( .A(n3398), .B(n3726), .Y(n3407) );
AOI222X1TS U5127 ( .A0(n3723), .A1(n4162), .B0(n3722), .B1(n4118), .C0(n2751), .C1(n4090), .Y(n3401) );
XOR2X1TS U5128 ( .A(n3402), .B(n3726), .Y(n3410) );
AOI222X1TS U5129 ( .A0(n3696), .A1(n4151), .B0(n3722), .B1(n4140), .C0(n2751), .C1(n4139), .Y(n3405) );
XOR2X1TS U5130 ( .A(n3406), .B(n3726), .Y(n3413) );
ADDHXLTS U5131 ( .A(n3408), .B(n3407), .CO(n3412), .S(
Sgf_operation_mult_x_1_n2642) );
CMPR32X2TS U5132 ( .A(n3411), .B(n3410), .C(n3409), .CO(
Sgf_operation_mult_x_1_n2615), .S(Sgf_operation_mult_x_1_n2616) );
CMPR32X2TS U5133 ( .A(n3414), .B(n3413), .C(n3412), .CO(n3409), .S(
Sgf_operation_mult_x_1_n2629) );
ADDHXLTS U5134 ( .A(n3416), .B(n3415), .CO(n3428), .S(
Sgf_operation_mult_x_1_n2710) );
XOR2X1TS U5135 ( .A(n3418), .B(n3783), .Y(n3427) );
AOI222X1TS U5136 ( .A0(n3780), .A1(n4162), .B0(n3779), .B1(n4118), .C0(n3764), .C1(n4126), .Y(n3421) );
XOR2X1TS U5137 ( .A(n3422), .B(n3783), .Y(n3430) );
AOI222X1TS U5138 ( .A0(n2424), .A1(n4151), .B0(n3779), .B1(n4140), .C0(n3764), .C1(n4139), .Y(n3425) );
XOR2X1TS U5139 ( .A(n3426), .B(n3783), .Y(n3433) );
ADDHXLTS U5140 ( .A(n3428), .B(n3427), .CO(n3432), .S(
Sgf_operation_mult_x_1_n2702) );
CMPR32X2TS U5141 ( .A(n3431), .B(n3430), .C(n3429), .CO(
Sgf_operation_mult_x_1_n2681), .S(Sgf_operation_mult_x_1_n2682) );
CMPR32X2TS U5142 ( .A(n3434), .B(n3433), .C(n3432), .CO(n3429), .S(
Sgf_operation_mult_x_1_n2692) );
ADDHXLTS U5143 ( .A(n3436), .B(n3435), .CO(n3448), .S(
Sgf_operation_mult_x_1_n2749) );
AOI222X1TS U5144 ( .A0(n3831), .A1(n4126), .B0(n3842), .B1(n4125), .C0(n3128), .C1(n4124), .Y(n3437) );
XOR2X1TS U5145 ( .A(n3438), .B(n3846), .Y(n3447) );
AOI222X1TS U5146 ( .A0(n3843), .A1(n4162), .B0(n3842), .B1(n4118), .C0(n3128), .C1(n4126), .Y(n3441) );
XOR2X1TS U5147 ( .A(n3442), .B(n3846), .Y(n3450) );
AOI222X1TS U5148 ( .A0(n3820), .A1(n4151), .B0(n3842), .B1(n4140), .C0(n3128), .C1(n4139), .Y(n3445) );
XOR2X1TS U5149 ( .A(n3446), .B(n3846), .Y(n3453) );
ADDHXLTS U5150 ( .A(n3448), .B(n3447), .CO(n3452), .S(
Sgf_operation_mult_x_1_n2744) );
CMPR32X2TS U5151 ( .A(n3451), .B(n3450), .C(n3449), .CO(
Sgf_operation_mult_x_1_n2729), .S(Sgf_operation_mult_x_1_n2730) );
CMPR32X2TS U5152 ( .A(n3454), .B(n3453), .C(n3452), .CO(n3449), .S(
Sgf_operation_mult_x_1_n2737) );
AOI222X1TS U5153 ( .A0(n3465), .A1(n3819), .B0(n3472), .B1(n3818), .C0(n3468), .C1(n3787), .Y(n3456) );
XOR2X1TS U5154 ( .A(n3457), .B(n3476), .Y(Sgf_operation_mult_x_1_n3484) );
AOI222X1TS U5155 ( .A0(n3473), .A1(n3885), .B0(n3472), .B1(n3884), .C0(n3468), .C1(n3883), .Y(n3458) );
XOR2X1TS U5156 ( .A(n3459), .B(n3476), .Y(Sgf_operation_mult_x_1_n3486) );
AOI222X1TS U5157 ( .A0(n3465), .A1(n3890), .B0(n3472), .B1(n3889), .C0(n3468), .C1(n3888), .Y(n3460) );
XOR2X1TS U5158 ( .A(n3461), .B(n3476), .Y(Sgf_operation_mult_x_1_n3488) );
XOR2X1TS U5159 ( .A(n3463), .B(n3476), .Y(Sgf_operation_mult_x_1_n3490) );
BUFX4TS U5160 ( .A(Op_MY[29]), .Y(n3928) );
XOR2X1TS U5161 ( .A(n3467), .B(n3476), .Y(Sgf_operation_mult_x_1_n3492) );
AOI222X1TS U5162 ( .A0(n3465), .A1(n3927), .B0(n3472), .B1(n3868), .C0(n3468), .C1(n3866), .Y(n3469) );
XOR2X1TS U5163 ( .A(n3470), .B(n3476), .Y(Sgf_operation_mult_x_1_n3494) );
AOI222X1TS U5164 ( .A0(n3473), .A1(n4002), .B0(n3472), .B1(n4001), .C0(n3471), .C1(n3877), .Y(n3474) );
XOR2X1TS U5165 ( .A(n3477), .B(n3476), .Y(Sgf_operation_mult_x_1_n3511) );
AOI222X1TS U5166 ( .A0(n3494), .A1(n3916), .B0(n3500), .B1(n3849), .C0(n3493), .C1(n3848), .Y(n3478) );
XOR2X1TS U5167 ( .A(n3479), .B(n3491), .Y(Sgf_operation_mult_x_1_n3537) );
AOI222X1TS U5168 ( .A0(n3501), .A1(n3885), .B0(n3489), .B1(n3884), .C0(n3493), .C1(n3883), .Y(n3480) );
XOR2X1TS U5169 ( .A(n3481), .B(n3491), .Y(Sgf_operation_mult_x_1_n3541) );
AOI222X1TS U5170 ( .A0(n3494), .A1(n3890), .B0(n3489), .B1(n3889), .C0(n3493), .C1(n3888), .Y(n3482) );
XOR2X1TS U5171 ( .A(n3483), .B(n3491), .Y(Sgf_operation_mult_x_1_n3543) );
AOI222X1TS U5172 ( .A0(n3494), .A1(n3859), .B0(n3489), .B1(n3858), .C0(n3493), .C1(n3857), .Y(n3484) );
XOR2X1TS U5173 ( .A(n3485), .B(n3491), .Y(Sgf_operation_mult_x_1_n3545) );
AOI222X1TS U5174 ( .A0(n3494), .A1(n3929), .B0(n3489), .B1(n3928), .C0(n3493), .C1(n3893), .Y(n3486) );
XOR2X1TS U5175 ( .A(n3488), .B(n3491), .Y(Sgf_operation_mult_x_1_n3547) );
AOI222X1TS U5176 ( .A0(n3501), .A1(n3927), .B0(n3489), .B1(n3868), .C0(n3493), .C1(n3866), .Y(n3490) );
XOR2X1TS U5177 ( .A(n3492), .B(n3491), .Y(Sgf_operation_mult_x_1_n3549) );
AOI222X1TS U5178 ( .A0(n3494), .A1(n3997), .B0(n3500), .B1(n3996), .C0(n3493), .C1(n3808), .Y(n3495) );
XOR2X1TS U5179 ( .A(n3496), .B(n3504), .Y(Sgf_operation_mult_x_1_n3565) );
AOI222X1TS U5180 ( .A0(n3501), .A1(n4115), .B0(n3500), .B1(n4114), .C0(n3499), .C1(n3717), .Y(n3497) );
XOR2X1TS U5181 ( .A(n3498), .B(n3504), .Y(Sgf_operation_mult_x_1_n3570) );
AOI222X1TS U5182 ( .A0(n3501), .A1(n4166), .B0(n3500), .B1(n4164), .C0(n3499), .C1(n3720), .Y(n3502) );
XOR2X1TS U5183 ( .A(n3505), .B(n3504), .Y(Sgf_operation_mult_x_1_n3571) );
AOI222X1TS U5184 ( .A0(n3523), .A1(n3916), .B0(n3522), .B1(n3849), .C0(n3521), .C1(n3848), .Y(n3506) );
XOR2X1TS U5185 ( .A(n3507), .B(n3532), .Y(Sgf_operation_mult_x_1_n3592) );
AOI222X1TS U5186 ( .A0(n3508), .A1(n3819), .B0(n3528), .B1(n3818), .C0(n3521), .C1(n3787), .Y(n3509) );
XOR2X1TS U5187 ( .A(n3510), .B(n3532), .Y(Sgf_operation_mult_x_1_n3594) );
AOI222X1TS U5188 ( .A0(n3529), .A1(n3885), .B0(n3528), .B1(n3884), .C0(n3521), .C1(n3883), .Y(n3511) );
XOR2X1TS U5189 ( .A(n3512), .B(n3532), .Y(Sgf_operation_mult_x_1_n3596) );
AOI222X1TS U5190 ( .A0(n3523), .A1(n3929), .B0(n3528), .B1(n3928), .C0(n3521), .C1(n3893), .Y(n3513) );
XOR2X1TS U5191 ( .A(n3515), .B(n3532), .Y(Sgf_operation_mult_x_1_n3602) );
AOI222X1TS U5192 ( .A0(n3529), .A1(n3927), .B0(n3528), .B1(n3868), .C0(n3521), .C1(n3866), .Y(n3516) );
XOR2X1TS U5193 ( .A(n3517), .B(n3532), .Y(Sgf_operation_mult_x_1_n3604) );
AOI222X1TS U5194 ( .A0(n3529), .A1(n3933), .B0(n3528), .B1(n3932), .C0(n3518), .C1(n3872), .Y(n3519) );
XOR2X1TS U5195 ( .A(n3520), .B(n3525), .Y(Sgf_operation_mult_x_1_n3606) );
AOI222X1TS U5196 ( .A0(n3523), .A1(n3997), .B0(n3522), .B1(n3996), .C0(n3521), .C1(n3808), .Y(n3524) );
XOR2X1TS U5197 ( .A(n3526), .B(n3525), .Y(Sgf_operation_mult_x_1_n3620) );
XOR2X1TS U5198 ( .A(n3533), .B(n3532), .Y(Sgf_operation_mult_x_1_n3622) );
XOR2X1TS U5199 ( .A(n3537), .B(n3548), .Y(Sgf_operation_mult_x_1_n3648) );
AOI222X1TS U5200 ( .A0(n3535), .A1(n3885), .B0(n3542), .B1(n3884), .C0(n3546), .C1(n3883), .Y(n3538) );
XOR2X1TS U5201 ( .A(n3539), .B(n3548), .Y(Sgf_operation_mult_x_1_n3652) );
AOI222X1TS U5202 ( .A0(n3554), .A1(n3859), .B0(n3542), .B1(n3858), .C0(n3546), .C1(n3857), .Y(n3540) );
XOR2X1TS U5203 ( .A(n3541), .B(n3548), .Y(Sgf_operation_mult_x_1_n3656) );
AOI222X1TS U5204 ( .A0(n1452), .A1(n3929), .B0(n3542), .B1(n3928), .C0(n3546), .C1(n3893), .Y(n3543) );
XOR2X1TS U5205 ( .A(n3545), .B(n3548), .Y(Sgf_operation_mult_x_1_n3658) );
AOI222X1TS U5206 ( .A0(n3554), .A1(n3927), .B0(n3553), .B1(n3868), .C0(n3546), .C1(n3866), .Y(n3547) );
XOR2X1TS U5207 ( .A(n3549), .B(n3548), .Y(Sgf_operation_mult_x_1_n3660) );
AOI222X1TS U5208 ( .A0(n3535), .A1(n4115), .B0(n3553), .B1(n4114), .C0(n3552), .C1(n3717), .Y(n3550) );
XOR2X1TS U5209 ( .A(n3551), .B(n3557), .Y(Sgf_operation_mult_x_1_n3681) );
AOI222X1TS U5210 ( .A0(n3535), .A1(n4166), .B0(n3553), .B1(n4164), .C0(n3552), .C1(n3720), .Y(n3555) );
XOR2X1TS U5211 ( .A(n3558), .B(n3557), .Y(Sgf_operation_mult_x_1_n3682) );
XOR2X1TS U5212 ( .A(n3560), .B(n3593), .Y(Sgf_operation_mult_x_1_n3703) );
AOI222X1TS U5213 ( .A0(n3584), .A1(n3819), .B0(n3589), .B1(n3818), .C0(n3582), .C1(n3787), .Y(n3562) );
XOR2X1TS U5214 ( .A(n3563), .B(n3593), .Y(Sgf_operation_mult_x_1_n3705) );
AOI222X1TS U5215 ( .A0(n3561), .A1(n3885), .B0(n3589), .B1(n3884), .C0(n3582), .C1(n3883), .Y(n3564) );
XOR2X1TS U5216 ( .A(n3565), .B(n3593), .Y(Sgf_operation_mult_x_1_n3707) );
OAI21X1TS U5217 ( .A0(n635), .A1(n3592), .B0(n3566), .Y(n3567) );
XOR2X1TS U5218 ( .A(n3567), .B(n3593), .Y(Sgf_operation_mult_x_1_n3709) );
AOI222X1TS U5219 ( .A0(n3590), .A1(n3859), .B0(n3589), .B1(n3858), .C0(n3588), .C1(n3857), .Y(n3568) );
XOR2X1TS U5220 ( .A(n3569), .B(n3593), .Y(Sgf_operation_mult_x_1_n3711) );
AOI222X1TS U5221 ( .A0(n3584), .A1(n3929), .B0(n3589), .B1(n3928), .C0(n3588), .C1(n3893), .Y(n3570) );
XOR2X1TS U5222 ( .A(n3571), .B(n3593), .Y(Sgf_operation_mult_x_1_n3713) );
AOI222X1TS U5223 ( .A0(n3584), .A1(n3927), .B0(n3583), .B1(n3868), .C0(n3588), .C1(n3866), .Y(n3572) );
XOR2X1TS U5224 ( .A(n3573), .B(n3593), .Y(Sgf_operation_mult_x_1_n3715) );
AOI222X1TS U5225 ( .A0(n3561), .A1(n3933), .B0(n3583), .B1(n3932), .C0(n3588), .C1(n3872), .Y(n3575) );
XOR2X1TS U5226 ( .A(n3577), .B(n3586), .Y(Sgf_operation_mult_x_1_n3717) );
XOR2X1TS U5227 ( .A(n3581), .B(n3586), .Y(Sgf_operation_mult_x_1_n3722) );
XOR2X1TS U5228 ( .A(n3587), .B(n3586), .Y(Sgf_operation_mult_x_1_n3731) );
AOI222X1TS U5229 ( .A0(n3584), .A1(n4002), .B0(n3589), .B1(n4001), .C0(n3588), .C1(n3877), .Y(n3591) );
XOR2X1TS U5230 ( .A(n3594), .B(n3593), .Y(Sgf_operation_mult_x_1_n3733) );
AOI222X1TS U5231 ( .A0(n3595), .A1(n3916), .B0(n3605), .B1(n3849), .C0(n3609), .C1(n3848), .Y(n3596) );
XOR2X1TS U5232 ( .A(n3597), .B(n3603), .Y(Sgf_operation_mult_x_1_n3759) );
AOI222X1TS U5233 ( .A0(n3599), .A1(n3929), .B0(n3598), .B1(n3928), .C0(n3609), .C1(n3893), .Y(n3600) );
XOR2X1TS U5234 ( .A(n3601), .B(n3603), .Y(Sgf_operation_mult_x_1_n3769) );
XOR2X1TS U5235 ( .A(n3604), .B(n3603), .Y(Sgf_operation_mult_x_1_n3771) );
XOR2X1TS U5236 ( .A(n3608), .B(n3620), .Y(Sgf_operation_mult_x_1_n3778) );
AOI222X1TS U5237 ( .A0(n3610), .A1(n3997), .B0(n3616), .B1(n3996), .C0(n3609), .C1(n3808), .Y(n3611) );
XOR2X1TS U5238 ( .A(n3612), .B(n3620), .Y(Sgf_operation_mult_x_1_n3787) );
XOR2X1TS U5239 ( .A(n3614), .B(n3620), .Y(Sgf_operation_mult_x_1_n3792) );
XOR2X1TS U5240 ( .A(n3621), .B(n3620), .Y(Sgf_operation_mult_x_1_n3793) );
AOI222X1TS U5241 ( .A0(n3622), .A1(n3819), .B0(n3637), .B1(n3818), .C0(n3630), .C1(n3787), .Y(n3623) );
XOR2X1TS U5242 ( .A(n3624), .B(n3641), .Y(Sgf_operation_mult_x_1_n3816) );
AOI222X1TS U5243 ( .A0(n3638), .A1(n3890), .B0(n3637), .B1(n3889), .C0(n3630), .C1(n3888), .Y(n3625) );
XOR2X1TS U5244 ( .A(n3626), .B(n3641), .Y(Sgf_operation_mult_x_1_n3820) );
XOR2X1TS U5245 ( .A(n3629), .B(n3641), .Y(Sgf_operation_mult_x_1_n3824) );
XOR2X1TS U5246 ( .A(n3635), .B(n3634), .Y(Sgf_operation_mult_x_1_n3842) );
AOI222X1TS U5247 ( .A0(n3638), .A1(n4002), .B0(n3637), .B1(n4001), .C0(n3636), .C1(n3877), .Y(n3639) );
XOR2X1TS U5248 ( .A(n3642), .B(n3641), .Y(Sgf_operation_mult_x_1_n3844) );
XOR2X1TS U5249 ( .A(n3645), .B(n3653), .Y(Sgf_operation_mult_x_1_n3870) );
AOI222X1TS U5250 ( .A0(n3651), .A1(n3885), .B0(n3650), .B1(n3884), .C0(n3657), .C1(n3883), .Y(n3646) );
XOR2X1TS U5251 ( .A(n3648), .B(n3653), .Y(Sgf_operation_mult_x_1_n3874) );
XOR2X1TS U5252 ( .A(n3654), .B(n3653), .Y(Sgf_operation_mult_x_1_n3880) );
AOI222X1TS U5253 ( .A0(n3651), .A1(n4115), .B0(n3658), .B1(n4114), .C0(n3649), .C1(n3717), .Y(n3655) );
XOR2X1TS U5254 ( .A(n3656), .B(n3663), .Y(Sgf_operation_mult_x_1_n3903) );
AOI222X1TS U5255 ( .A0(n3659), .A1(n4166), .B0(n3658), .B1(n4164), .C0(n3649), .C1(n3720), .Y(n3660) );
XOR2X1TS U5256 ( .A(n3664), .B(n3663), .Y(Sgf_operation_mult_x_1_n3904) );
AOI222X1TS U5257 ( .A0(n3689), .A1(n3819), .B0(n3688), .B1(n3818), .C0(n3681), .C1(n3787), .Y(n3666) );
XOR2X1TS U5258 ( .A(n3667), .B(n3692), .Y(Sgf_operation_mult_x_1_n3928) );
AOI222X1TS U5259 ( .A0(n3683), .A1(n3885), .B0(n3688), .B1(n3884), .C0(n3687), .C1(n3883), .Y(n3668) );
XOR2X1TS U5260 ( .A(n3669), .B(n3692), .Y(Sgf_operation_mult_x_1_n3930) );
AOI222X1TS U5261 ( .A0(n3689), .A1(n3890), .B0(n3688), .B1(n3889), .C0(n3687), .C1(n3888), .Y(n3670) );
XOR2X1TS U5262 ( .A(n3671), .B(n3692), .Y(Sgf_operation_mult_x_1_n3932) );
AOI222X1TS U5263 ( .A0(n3683), .A1(n3859), .B0(n3688), .B1(n3858), .C0(n3681), .C1(n3857), .Y(n3672) );
XOR2X1TS U5264 ( .A(n3673), .B(n3692), .Y(Sgf_operation_mult_x_1_n3934) );
XOR2X1TS U5265 ( .A(n3676), .B(n3692), .Y(Sgf_operation_mult_x_1_n3936) );
AOI222X1TS U5266 ( .A0(n3683), .A1(n3933), .B0(n3682), .B1(n3932), .C0(n3687), .C1(n3872), .Y(n3678) );
XOR2X1TS U5267 ( .A(n3680), .B(n3685), .Y(Sgf_operation_mult_x_1_n3940) );
XOR2X1TS U5268 ( .A(n3686), .B(n3685), .Y(Sgf_operation_mult_x_1_n3954) );
AOI222X1TS U5269 ( .A0(n3689), .A1(n4002), .B0(n3688), .B1(n4001), .C0(n3681), .C1(n3877), .Y(n3690) );
XOR2X1TS U5270 ( .A(n3693), .B(n3692), .Y(Sgf_operation_mult_x_1_n3956) );
OAI21X1TS U5271 ( .A0(n630), .A1(n3702), .B0(n3694), .Y(n3695) );
XOR2X1TS U5272 ( .A(n3695), .B(n3710), .Y(Sgf_operation_mult_x_1_n3982) );
AOI222X1TS U5273 ( .A0(n3696), .A1(n3819), .B0(n3704), .B1(n3818), .C0(n3721), .C1(n3787), .Y(n3697) );
XOR2X1TS U5274 ( .A(n3698), .B(n3710), .Y(Sgf_operation_mult_x_1_n3984) );
AOI222X1TS U5275 ( .A0(n3723), .A1(n3890), .B0(n3704), .B1(n3889), .C0(n3721), .C1(n3888), .Y(n3699) );
XOR2X1TS U5276 ( .A(n3700), .B(n3710), .Y(Sgf_operation_mult_x_1_n3988) );
AOI222X1TS U5277 ( .A0(n3713), .A1(n3859), .B0(n3704), .B1(n3858), .C0(n3708), .C1(n3857), .Y(n3701) );
XOR2X1TS U5278 ( .A(n3703), .B(n3710), .Y(Sgf_operation_mult_x_1_n3990) );
XOR2X1TS U5279 ( .A(n3707), .B(n3710), .Y(Sgf_operation_mult_x_1_n3992) );
AOI222X1TS U5280 ( .A0(n3713), .A1(n3927), .B0(n3722), .B1(n3868), .C0(n3721), .C1(n3866), .Y(n3709) );
XOR2X1TS U5281 ( .A(n3711), .B(n3710), .Y(Sgf_operation_mult_x_1_n3994) );
XOR2X1TS U5282 ( .A(n3716), .B(n3726), .Y(Sgf_operation_mult_x_1_n4001) );
AOI222X1TS U5283 ( .A0(n3723), .A1(n4115), .B0(n3722), .B1(n4114), .C0(n3708), .C1(n3717), .Y(n3718) );
XOR2X1TS U5284 ( .A(n3719), .B(n3726), .Y(Sgf_operation_mult_x_1_n4015) );
AOI222X1TS U5285 ( .A0(n3713), .A1(n4166), .B0(n3722), .B1(n4164), .C0(n2751), .C1(n3720), .Y(n3724) );
XOR2X1TS U5286 ( .A(n3727), .B(n3726), .Y(Sgf_operation_mult_x_1_n4016) );
OAI21X1TS U5287 ( .A0(n630), .A1(n3745), .B0(n3730), .Y(n3731) );
XOR2X1TS U5288 ( .A(n3731), .B(n3753), .Y(Sgf_operation_mult_x_1_n4038) );
AOI222X1TS U5289 ( .A0(n3729), .A1(n3819), .B0(n3749), .B1(n3818), .C0(n3739), .C1(n3787), .Y(n3733) );
XOR2X1TS U5290 ( .A(n3734), .B(n3753), .Y(Sgf_operation_mult_x_1_n4040) );
AOI222X1TS U5291 ( .A0(n3750), .A1(n3890), .B0(n3749), .B1(n3889), .C0(n3739), .C1(n3888), .Y(n3735) );
XOR2X1TS U5292 ( .A(n3736), .B(n3753), .Y(Sgf_operation_mult_x_1_n4044) );
AOI222X1TS U5293 ( .A0(n3750), .A1(n3929), .B0(n3749), .B1(n3928), .C0(n3748), .C1(n3893), .Y(n3737) );
XOR2X1TS U5294 ( .A(n3738), .B(n3753), .Y(Sgf_operation_mult_x_1_n4048) );
AOI222X1TS U5295 ( .A0(n3729), .A1(n3927), .B0(n3743), .B1(n3868), .C0(n3748), .C1(n3866), .Y(n3740) );
XOR2X1TS U5296 ( .A(n3741), .B(n3753), .Y(Sgf_operation_mult_x_1_n4050) );
AOI222X1TS U5297 ( .A0(n3750), .A1(n3933), .B0(n3743), .B1(n3932), .C0(n3739), .C1(n3872), .Y(n3744) );
XOR2X1TS U5298 ( .A(n3747), .B(n3746), .Y(Sgf_operation_mult_x_1_n4052) );
AOI222X1TS U5299 ( .A0(n3729), .A1(n4002), .B0(n3749), .B1(n4001), .C0(n3739), .C1(n3877), .Y(n3751) );
XOR2X1TS U5300 ( .A(n3754), .B(n3753), .Y(Sgf_operation_mult_x_1_n4068) );
AOI222X1TS U5301 ( .A0(n3780), .A1(n3885), .B0(n3758), .B1(n3884), .C0(n3778), .C1(n3890), .Y(n3755) );
XOR2X1TS U5302 ( .A(n3757), .B(n3762), .Y(Sgf_operation_mult_x_1_n4098) );
XOR2X1TS U5303 ( .A(n3760), .B(n3762), .Y(Sgf_operation_mult_x_1_n4104) );
AOI222X1TS U5304 ( .A0(n3773), .A1(n3927), .B0(n3779), .B1(n3868), .C0(n3772), .C1(n3933), .Y(n3761) );
XOR2X1TS U5305 ( .A(n3763), .B(n3762), .Y(Sgf_operation_mult_x_1_n4106) );
AOI222X1TS U5306 ( .A0(n3773), .A1(n3933), .B0(n3779), .B1(n3932), .C0(n3778), .C1(n3943), .Y(n3765) );
XOR2X1TS U5307 ( .A(n3767), .B(n3783), .Y(Sgf_operation_mult_x_1_n4108) );
XOR2X1TS U5308 ( .A(n3771), .B(n3783), .Y(Sgf_operation_mult_x_1_n4113) );
XOR2X1TS U5309 ( .A(n3775), .B(n3783), .Y(Sgf_operation_mult_x_1_n4122) );
AOI222X1TS U5310 ( .A0(n2424), .A1(n4115), .B0(n3779), .B1(n4114), .C0(n3772), .C1(n4153), .Y(n3776) );
XOR2X1TS U5311 ( .A(n3777), .B(n3783), .Y(Sgf_operation_mult_x_1_n4127) );
AOI222X1TS U5312 ( .A0(n3780), .A1(n4166), .B0(n3779), .B1(n4164), .C0(n3764), .C1(n4162), .Y(n3781) );
XOR2X1TS U5313 ( .A(n3784), .B(n3783), .Y(Sgf_operation_mult_x_1_n4128) );
OAI21X1TS U5314 ( .A0(n630), .A1(n3798), .B0(n3785), .Y(n3786) );
XOR2X1TS U5315 ( .A(n3786), .B(n3801), .Y(Sgf_operation_mult_x_1_n4150) );
AOI222X1TS U5316 ( .A0(n3805), .A1(n3819), .B0(n3804), .B1(n3818), .C0(n3156), .C1(n3787), .Y(n3789) );
XOR2X1TS U5317 ( .A(n3790), .B(n3801), .Y(Sgf_operation_mult_x_1_n4152) );
AOI222X1TS U5318 ( .A0(n3811), .A1(n3885), .B0(n3804), .B1(n3884), .C0(n3809), .C1(n3883), .Y(n3791) );
XOR2X1TS U5319 ( .A(n3792), .B(n3801), .Y(Sgf_operation_mult_x_1_n4154) );
AOI222X1TS U5320 ( .A0(n3811), .A1(n3890), .B0(n3804), .B1(n3889), .C0(n3156), .C1(n3888), .Y(n3793) );
XOR2X1TS U5321 ( .A(n3794), .B(n3801), .Y(Sgf_operation_mult_x_1_n4156) );
XOR2X1TS U5322 ( .A(n3796), .B(n3801), .Y(Sgf_operation_mult_x_1_n4158) );
XOR2X1TS U5323 ( .A(n3799), .B(n3801), .Y(Sgf_operation_mult_x_1_n4160) );
AOI222X1TS U5324 ( .A0(n3811), .A1(n3927), .B0(n3804), .B1(n3868), .C0(n3156), .C1(n3866), .Y(n3800) );
XOR2X1TS U5325 ( .A(n3802), .B(n3801), .Y(Sgf_operation_mult_x_1_n4162) );
AOI222X1TS U5326 ( .A0(n3805), .A1(n3933), .B0(n3804), .B1(n3932), .C0(n3156), .C1(n3872), .Y(n3806) );
XOR2X1TS U5327 ( .A(n3807), .B(n3814), .Y(Sgf_operation_mult_x_1_n4164) );
XOR2X1TS U5328 ( .A(n3815), .B(n3814), .Y(Sgf_operation_mult_x_1_n4178) );
XOR2X1TS U5329 ( .A(n3817), .B(n3837), .Y(Sgf_operation_mult_x_1_n4206) );
AOI222X1TS U5330 ( .A0(n3831), .A1(n3819), .B0(n3835), .B1(n3818), .C0(n3841), .C1(n3885), .Y(n3821) );
XOR2X1TS U5331 ( .A(n3822), .B(n3837), .Y(Sgf_operation_mult_x_1_n4208) );
AOI222X1TS U5332 ( .A0(n3843), .A1(n3885), .B0(n3835), .B1(n3884), .C0(n3841), .C1(n3890), .Y(n3823) );
XOR2X1TS U5333 ( .A(n3824), .B(n3837), .Y(Sgf_operation_mult_x_1_n4210) );
AOI222X1TS U5334 ( .A0(n3820), .A1(n3859), .B0(n3835), .B1(n3858), .C0(n3827), .C1(n3929), .Y(n3825) );
XOR2X1TS U5335 ( .A(n3826), .B(n3837), .Y(Sgf_operation_mult_x_1_n4214) );
XOR2X1TS U5336 ( .A(n3830), .B(n3837), .Y(Sgf_operation_mult_x_1_n4216) );
XOR2X1TS U5337 ( .A(n3834), .B(n3846), .Y(Sgf_operation_mult_x_1_n4225) );
AOI222X1TS U5338 ( .A0(n3820), .A1(n4002), .B0(n3835), .B1(n4001), .C0(n3128), .C1(n4084), .Y(n3836) );
XOR2X1TS U5339 ( .A(n3838), .B(n3837), .Y(Sgf_operation_mult_x_1_n4236) );
AOI222X1TS U5340 ( .A0(n3831), .A1(n4115), .B0(n3842), .B1(n4114), .C0(n3128), .C1(n4153), .Y(n3839) );
XOR2X1TS U5341 ( .A(n3840), .B(n3846), .Y(Sgf_operation_mult_x_1_n4239) );
AOI222X1TS U5342 ( .A0(n3831), .A1(n4166), .B0(n3842), .B1(n4164), .C0(n3128), .C1(n4162), .Y(n3844) );
XOR2X1TS U5343 ( .A(n3847), .B(n3846), .Y(Sgf_operation_mult_x_1_n4240) );
AOI222X1TS U5344 ( .A0(n3850), .A1(n3916), .B0(n4035), .B1(n3849), .C0(n3867), .C1(n3848), .Y(n3851) );
XOR2X1TS U5345 ( .A(n3852), .B(n3881), .Y(Sgf_operation_mult_x_1_n4262) );
AOI222X1TS U5346 ( .A0(n3862), .A1(n3885), .B0(n3878), .B1(n3884), .C0(n3867), .C1(n3883), .Y(n3853) );
XOR2X1TS U5347 ( .A(n3854), .B(n3881), .Y(Sgf_operation_mult_x_1_n4266) );
AOI222X1TS U5348 ( .A0(n3862), .A1(n3890), .B0(n3878), .B1(n3889), .C0(n3867), .C1(n3888), .Y(n3855) );
XOR2X1TS U5349 ( .A(n3856), .B(n3881), .Y(Sgf_operation_mult_x_1_n4268) );
AOI222X1TS U5350 ( .A0(n3862), .A1(n3859), .B0(n3878), .B1(n3858), .C0(n3867), .C1(n3857), .Y(n3860) );
XOR2X1TS U5351 ( .A(n3861), .B(n3881), .Y(Sgf_operation_mult_x_1_n4270) );
AOI222X1TS U5352 ( .A0(n3862), .A1(n3929), .B0(n3878), .B1(n3928), .C0(n3867), .C1(n3893), .Y(n3863) );
XOR2X1TS U5353 ( .A(n3865), .B(n3881), .Y(Sgf_operation_mult_x_1_n4272) );
XOR2X1TS U5354 ( .A(n3871), .B(n3881), .Y(Sgf_operation_mult_x_1_n4274) );
XOR2X1TS U5355 ( .A(n3876), .B(n4039), .Y(Sgf_operation_mult_x_1_n4276) );
XOR2X1TS U5356 ( .A(n3882), .B(n3881), .Y(Sgf_operation_mult_x_1_n4292) );
XOR2X1TS U5357 ( .A(n3887), .B(n3897), .Y(Sgf_operation_mult_x_1_n4322) );
AOI222X1TS U5358 ( .A0(n3901), .A1(n3890), .B0(n4105), .B1(n3889), .C0(n3894), .C1(n3888), .Y(n3891) );
XOR2X1TS U5359 ( .A(n3892), .B(n3897), .Y(Sgf_operation_mult_x_1_n4324) );
AOI222X1TS U5360 ( .A0(n4106), .A1(n3929), .B0(n4105), .B1(n3928), .C0(n3894), .C1(n3893), .Y(n3895) );
XOR2X1TS U5361 ( .A(n3898), .B(n3897), .Y(Sgf_operation_mult_x_1_n4328) );
XOR2X1TS U5362 ( .A(n3903), .B(n4109), .Y(Sgf_operation_mult_x_1_n4337) );
AOI21X1TS U5363 ( .A0(n4163), .A1(n4047), .B0(n4130), .Y(n3904) );
XOR2X1TS U5364 ( .A(n3905), .B(n5152), .Y(Sgf_operation_mult_x_1_n4361) );
AOI222X1TS U5365 ( .A0(n4167), .A1(n3907), .B0(n4165), .B1(n3906), .C0(n3995), .C1(n3912), .Y(n3908) );
XOR2X1TS U5366 ( .A(n3910), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4369)
);
AOI222X1TS U5367 ( .A0(n3998), .A1(n3912), .B0(n3937), .B1(n3911), .C0(n4163), .C1(n3923), .Y(n3913) );
XOR2X1TS U5368 ( .A(n3915), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4371)
);
XOR2X1TS U5369 ( .A(n3920), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4372)
);
AOI222X1TS U5370 ( .A0(n3998), .A1(n3923), .B0(n3937), .B1(n3922), .C0(n3995), .C1(n3921), .Y(n3924) );
XOR2X1TS U5371 ( .A(n3926), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4373)
);
XOR2X1TS U5372 ( .A(n3931), .B(n4170), .Y(Sgf_operation_mult_x_1_n4384) );
AOI222X1TS U5373 ( .A0(n3998), .A1(n3933), .B0(n3937), .B1(n3932), .C0(n3995), .C1(n3943), .Y(n3934) );
XOR2X1TS U5374 ( .A(n3935), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4388)
);
AOI222X1TS U5375 ( .A0(n4167), .A1(n3938), .B0(n3937), .B1(n3936), .C0(n4163), .C1(n3947), .Y(n3939) );
XOR2X1TS U5376 ( .A(n3941), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4389)
);
OAI21X1TS U5377 ( .A0(n2692), .A1(n3955), .B0(n3944), .Y(n3945) );
XOR2X1TS U5378 ( .A(n3945), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4390)
);
XOR2X1TS U5379 ( .A(n3950), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4391)
);
OAI21X1TS U5380 ( .A0(n636), .A1(n3955), .B0(n3954), .Y(n3956) );
XOR2X1TS U5381 ( .A(n3956), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4392)
);
XOR2X1TS U5382 ( .A(n3961), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4393)
);
XOR2X1TS U5383 ( .A(n3965), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4394)
);
XOR2X1TS U5384 ( .A(n3970), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4395)
);
XOR2X1TS U5385 ( .A(n3974), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4396)
);
XOR2X1TS U5386 ( .A(n3979), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4397)
);
XOR2X1TS U5387 ( .A(n3984), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4398)
);
XOR2X1TS U5388 ( .A(n3989), .B(Op_MX[2]), .Y(Sgf_operation_mult_x_1_n4399)
);
XOR2X1TS U5389 ( .A(n3994), .B(n754), .Y(Sgf_operation_mult_x_1_n4401) );
OAI21X1TS U5390 ( .A0(n642), .A1(n4169), .B0(n3999), .Y(n4000) );
XOR2X1TS U5391 ( .A(n4000), .B(n4170), .Y(Sgf_operation_mult_x_1_n4402) );
AOI222X1TS U5392 ( .A0(n4134), .A1(n4002), .B0(n4165), .B1(n4001), .C0(n3951), .C1(n4084), .Y(n4003) );
XOR2X1TS U5393 ( .A(n4004), .B(n4170), .Y(Sgf_operation_mult_x_1_n4404) );
NOR3BX1TS U5394 ( .AN(Op_MY[62]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n4005) );
XOR2X1TS U5395 ( .A(DP_OP_31J39_122_605_n42), .B(n4005), .Y(
DP_OP_31J39_122_605_n18) );
OAI2BB1X1TS U5396 ( .A0N(n705), .A1N(n5088), .B0(n4015), .Y(n4006) );
XOR2X1TS U5397 ( .A(DP_OP_31J39_122_605_n42), .B(n4006), .Y(
DP_OP_31J39_122_605_n19) );
OAI2BB1X1TS U5398 ( .A0N(n706), .A1N(n5088), .B0(n4015), .Y(n4007) );
XOR2X1TS U5399 ( .A(DP_OP_31J39_122_605_n42), .B(n4007), .Y(
DP_OP_31J39_122_605_n20) );
OAI2BB1X1TS U5400 ( .A0N(Op_MY[59]), .A1N(n5088), .B0(n4015), .Y(n4008) );
XOR2X1TS U5401 ( .A(DP_OP_31J39_122_605_n42), .B(n4008), .Y(
DP_OP_31J39_122_605_n21) );
OAI2BB1X1TS U5402 ( .A0N(Op_MY[58]), .A1N(n5088), .B0(n4015), .Y(n4009) );
XOR2X1TS U5403 ( .A(DP_OP_31J39_122_605_n42), .B(n4009), .Y(
DP_OP_31J39_122_605_n22) );
OAI2BB1X1TS U5404 ( .A0N(n712), .A1N(n5088), .B0(n4015), .Y(n4010) );
XOR2X1TS U5405 ( .A(DP_OP_31J39_122_605_n42), .B(n4010), .Y(
DP_OP_31J39_122_605_n23) );
OAI2BB1X1TS U5406 ( .A0N(n713), .A1N(n5088), .B0(n4015), .Y(n4011) );
XOR2X1TS U5407 ( .A(DP_OP_31J39_122_605_n42), .B(n4011), .Y(
DP_OP_31J39_122_605_n24) );
OAI2BB1X1TS U5408 ( .A0N(n711), .A1N(n5088), .B0(n4015), .Y(n4012) );
XOR2X1TS U5409 ( .A(DP_OP_31J39_122_605_n42), .B(n4012), .Y(
DP_OP_31J39_122_605_n25) );
OAI2BB1X1TS U5410 ( .A0N(Op_MY[54]), .A1N(n5088), .B0(n4015), .Y(n4013) );
XOR2X1TS U5411 ( .A(DP_OP_31J39_122_605_n42), .B(n4013), .Y(
DP_OP_31J39_122_605_n26) );
OAI2BB1X1TS U5412 ( .A0N(n704), .A1N(n5088), .B0(n4015), .Y(n4014) );
XOR2X1TS U5413 ( .A(DP_OP_31J39_122_605_n42), .B(n4014), .Y(
DP_OP_31J39_122_605_n27) );
NOR2XLTS U5414 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n4016) );
OAI21XLTS U5415 ( .A0(FSM_selector_B[0]), .A1(n4016), .B0(n4015), .Y(n4017)
);
XOR2X1TS U5416 ( .A(DP_OP_31J39_122_605_n42), .B(n4017), .Y(
DP_OP_31J39_122_605_n28) );
INVX4TS U5417 ( .A(n4609), .Y(n4020) );
MX2X1TS U5418 ( .A(Data_MX[51]), .B(Op_MX[51]), .S0(n4020), .Y(n590) );
MX2X1TS U5419 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n4020), .Y(n589) );
MX2X1TS U5420 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n4020), .Y(n588) );
MX2X1TS U5421 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n4020), .Y(n587) );
MX2X1TS U5422 ( .A(Data_MX[47]), .B(Op_MX[47]), .S0(n4020), .Y(n586) );
MX2X1TS U5423 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n4020), .Y(n585) );
MX2X1TS U5424 ( .A(Data_MX[45]), .B(Op_MX[45]), .S0(n4020), .Y(n584) );
MX2X1TS U5425 ( .A(Data_MX[44]), .B(Op_MX[44]), .S0(n4020), .Y(n583) );
MX2X1TS U5426 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n4020), .Y(n582) );
MX2X1TS U5427 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n4020), .Y(n581) );
MX2X1TS U5428 ( .A(Data_MX[41]), .B(Op_MX[41]), .S0(n4020), .Y(n580) );
MX2X1TS U5429 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n4020), .Y(n579) );
MX2X1TS U5430 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n4020), .Y(n578) );
INVX4TS U5431 ( .A(n4609), .Y(n4021) );
MX2X1TS U5432 ( .A(Data_MX[38]), .B(Op_MX[38]), .S0(n4021), .Y(n577) );
MX2X1TS U5433 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n4021), .Y(n576) );
MX2X1TS U5434 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n4021), .Y(n575) );
MX2X1TS U5435 ( .A(Data_MX[35]), .B(Op_MX[35]), .S0(n4021), .Y(n574) );
MX2X1TS U5436 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n4021), .Y(n573) );
MX2X1TS U5437 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n4021), .Y(n572) );
MX2X1TS U5438 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n4021), .Y(n571) );
MX2X1TS U5439 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n4021), .Y(n570) );
MX2X1TS U5440 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n4021), .Y(n569) );
MX2X1TS U5441 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n4021), .Y(n568) );
MX2X1TS U5442 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n4021), .Y(n567) );
MX2X1TS U5443 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n4021), .Y(n566) );
MX2X1TS U5444 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n4021), .Y(n565) );
INVX4TS U5445 ( .A(n4609), .Y(n4022) );
MX2X1TS U5446 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n4022), .Y(n564) );
MX2X1TS U5447 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n4022), .Y(n563) );
MX2X1TS U5448 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n4022), .Y(n562) );
MX2X1TS U5449 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n4020), .Y(n561) );
MX2X1TS U5450 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n4020), .Y(n560) );
INVX4TS U5451 ( .A(n4609), .Y(n4024) );
MX2X1TS U5452 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n4024), .Y(n559) );
MX2X1TS U5453 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n4024), .Y(n558) );
MX2X1TS U5454 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n4024), .Y(n557) );
MX2X1TS U5455 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n4021), .Y(n556) );
MX2X1TS U5456 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n4021), .Y(n555) );
MX2X1TS U5457 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n4021), .Y(n554) );
INVX4TS U5458 ( .A(n4609), .Y(n4023) );
MX2X1TS U5459 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n4023), .Y(n553) );
MX2X1TS U5460 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n4023), .Y(n552) );
MX2X1TS U5461 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n4022), .Y(n551) );
MX2X1TS U5462 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n4022), .Y(n550) );
MX2X1TS U5463 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n4022), .Y(n549) );
MX2X1TS U5464 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n4022), .Y(n548) );
MX2X1TS U5465 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n4022), .Y(n547) );
MX2X1TS U5466 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n4022), .Y(n546) );
MX2X1TS U5467 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n4022), .Y(n545) );
MX2X1TS U5468 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n4022), .Y(n544) );
MX2X1TS U5469 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n4022), .Y(n543) );
MX2X1TS U5470 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n4022), .Y(n542) );
MX2X1TS U5471 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n4022), .Y(n541) );
MX2X1TS U5472 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n4022), .Y(n540) );
MX2X1TS U5473 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n4022), .Y(n539) );
MX2X1TS U5474 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n4023), .Y(n526) );
MX2X1TS U5475 ( .A(Data_MY[50]), .B(n2728), .S0(n4023), .Y(n525) );
MX2X1TS U5476 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n4023), .Y(n524) );
MX2X1TS U5477 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n4023), .Y(n523) );
MX2X1TS U5478 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n4023), .Y(n522) );
MX2X1TS U5479 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n4023), .Y(n521) );
MX2X1TS U5480 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n4023), .Y(n520) );
MX2X1TS U5481 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n4023), .Y(n519) );
MX2X1TS U5482 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n4023), .Y(n518) );
MX2X1TS U5483 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n4023), .Y(n517) );
MX2X1TS U5484 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n4023), .Y(n516) );
MX2X1TS U5485 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n4023), .Y(n515) );
MX2X1TS U5486 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n4023), .Y(n514) );
MX2X1TS U5487 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n4024), .Y(n513) );
MX2X1TS U5488 ( .A(Data_MY[37]), .B(Op_MY[37]), .S0(n4024), .Y(n512) );
MX2X1TS U5489 ( .A(Data_MY[36]), .B(Op_MY[36]), .S0(n4024), .Y(n511) );
MX2X1TS U5490 ( .A(Data_MY[35]), .B(Op_MY[35]), .S0(n4024), .Y(n510) );
MX2X1TS U5491 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n4024), .Y(n509) );
MX2X1TS U5492 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n4024), .Y(n508) );
MX2X1TS U5493 ( .A(Data_MY[32]), .B(Op_MY[32]), .S0(n4024), .Y(n507) );
MX2X1TS U5494 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n4024), .Y(n506) );
MX2X1TS U5495 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n4024), .Y(n505) );
MX2X1TS U5496 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n4024), .Y(n504) );
MX2X1TS U5497 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n4024), .Y(n503) );
MX2X1TS U5498 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n4024), .Y(n502) );
MX2X1TS U5499 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n4024), .Y(n501) );
INVX4TS U5500 ( .A(n4609), .Y(n4025) );
MX2X1TS U5501 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n4025), .Y(n500) );
MX2X1TS U5502 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n4025), .Y(n499) );
MX2X1TS U5503 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n4025), .Y(n498) );
MX2X1TS U5504 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n4025), .Y(n497) );
MX2X1TS U5505 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n4025), .Y(n496) );
MX2X1TS U5506 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n4025), .Y(n495) );
MX2X1TS U5507 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n4025), .Y(n494) );
MX2X1TS U5508 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n4025), .Y(n493) );
MX2X1TS U5509 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n4025), .Y(n492) );
MX2X1TS U5510 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n4025), .Y(n491) );
MX2X1TS U5511 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n4025), .Y(n490) );
MX2X1TS U5512 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n4025), .Y(n489) );
MX2X1TS U5513 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n4025), .Y(n488) );
INVX4TS U5514 ( .A(n4609), .Y(n4026) );
MX2X1TS U5515 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n4026), .Y(n487) );
MX2X1TS U5516 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n4026), .Y(n486) );
MX2X1TS U5517 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n4026), .Y(n485) );
MX2X1TS U5518 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n4026), .Y(n484) );
MX2X1TS U5519 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n4026), .Y(n483) );
MX2X1TS U5520 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n4026), .Y(n482) );
MX2X1TS U5521 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n4026), .Y(n481) );
MX2X1TS U5522 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n4026), .Y(n480) );
MX2X1TS U5523 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n4026), .Y(n479) );
MX2X1TS U5524 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n4026), .Y(n478) );
MX2X1TS U5525 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n4026), .Y(n477) );
MX2X1TS U5526 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n4026), .Y(n476) );
MX2X1TS U5527 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n4026), .Y(n475) );
AOI22X1TS U5528 ( .A0(n4031), .A1(n4028), .B0(n4027), .B1(n4129), .Y(n4029)
);
XOR2X1TS U5529 ( .A(n4030), .B(n4039), .Y(n4089) );
NAND2X1TS U5530 ( .A(n4031), .B(n4133), .Y(n4032) );
XOR2X1TS U5531 ( .A(n4033), .B(n4039), .Y(n4093) );
XOR2X1TS U5532 ( .A(n4040), .B(n4039), .Y(n4078) );
OAI21XLTS U5533 ( .A0(n956), .A1(n4075), .B0(n4041), .Y(n4269) );
AOI21X1TS U5534 ( .A0(n4073), .A1(n4053), .B0(n4070), .Y(n4043) );
OA21X1TS U5535 ( .A0(n4057), .A1(n4075), .B0(n4043), .Y(n4613) );
AOI21X1TS U5536 ( .A0(n4073), .A1(n4069), .B0(n4044), .Y(n4045) );
OAI21X1TS U5537 ( .A0(n4046), .A1(n4042), .B0(n4045), .Y(n4065) );
CLKAND2X2TS U5538 ( .A(n4048), .B(n4047), .Y(n4049) );
AOI21X1TS U5539 ( .A0(n4073), .A1(n2728), .B0(n4049), .Y(n4051) );
OAI21XLTS U5540 ( .A0(n632), .A1(n4075), .B0(n4051), .Y(n4064) );
INVX2TS U5541 ( .A(n4065), .Y(n4067) );
AOI21X1TS U5542 ( .A0(n4054), .A1(n4053), .B0(n4052), .Y(n4055) );
XOR2X1TS U5543 ( .A(n4058), .B(n4062), .Y(n4068) );
OAI21XLTS U5544 ( .A0(n956), .A1(n4060), .B0(n4059), .Y(n4063) );
XOR2X1TS U5545 ( .A(n4063), .B(n4062), .Y(n4066) );
CMPR32X2TS U5546 ( .A(n5094), .B(n4065), .C(n4064), .CO(n4612), .S(n4616) );
CMPR32X2TS U5547 ( .A(n4067), .B(n4068), .C(n4066), .CO(n4617), .S(n4621) );
INVX2TS U5548 ( .A(n4068), .Y(n4077) );
AOI21X1TS U5549 ( .A0(n4073), .A1(n4072), .B0(n4071), .Y(n4074) );
CMPR32X2TS U5550 ( .A(n4077), .B(Sgf_operation_mult_x_1_n1340), .C(n4076),
.CO(n4620), .S(n4624) );
NOR2X2TS U5551 ( .A(Sgf_operation_mult_x_1_n2031), .B(
Sgf_operation_mult_x_1_n2054), .Y(n4870) );
NOR2X1TS U5552 ( .A(Sgf_operation_mult_x_1_n2055), .B(
Sgf_operation_mult_x_1_n2078), .Y(n4868) );
NOR2X1TS U5553 ( .A(n4870), .B(n4868), .Y(n4236) );
NOR2X2TS U5554 ( .A(Sgf_operation_mult_x_1_n2079), .B(
Sgf_operation_mult_x_1_n2102), .Y(n4886) );
NOR2X1TS U5555 ( .A(Sgf_operation_mult_x_1_n2103), .B(
Sgf_operation_mult_x_1_n2126), .Y(n4405) );
NOR2X1TS U5556 ( .A(n4886), .B(n4405), .Y(n4863) );
NAND2X1TS U5557 ( .A(n4236), .B(n4863), .Y(n4238) );
NOR2X2TS U5558 ( .A(Sgf_operation_mult_x_1_n2127), .B(
Sgf_operation_mult_x_1_n2151), .Y(n4421) );
NOR2X1TS U5559 ( .A(Sgf_operation_mult_x_1_n2152), .B(
Sgf_operation_mult_x_1_n2176), .Y(n4308) );
NOR2X1TS U5560 ( .A(n4421), .B(n4308), .Y(n4234) );
NOR2X1TS U5561 ( .A(n4433), .B(n4431), .Y(n4304) );
NAND2X1TS U5562 ( .A(n4234), .B(n4304), .Y(n4404) );
NOR2X1TS U5563 ( .A(n4238), .B(n4404), .Y(n4240) );
NOR2X1TS U5564 ( .A(Sgf_operation_mult_x_1_n2721), .B(
Sgf_operation_mult_x_1_n2727), .Y(n4505) );
INVX2TS U5565 ( .A(n4505), .Y(n4495) );
NAND2X1TS U5566 ( .A(n4507), .B(n4495), .Y(n4554) );
ADDHXLTS U5567 ( .A(n4079), .B(n4078), .CO(Sgf_operation_mult_x_1_n2757),
.S(n4185) );
AOI222X1TS U5568 ( .A0(n4101), .A1(n4153), .B0(n4105), .B1(n4152), .C0(n2794), .C1(n4080), .Y(n4081) );
XOR2X1TS U5569 ( .A(n4082), .B(n4109), .Y(n4184) );
AOI222X1TS U5570 ( .A0(n4134), .A1(n4084), .B0(n4165), .B1(n4083), .C0(n3951), .C1(n4166), .Y(n4085) );
XOR2X1TS U5571 ( .A(n4087), .B(n4170), .Y(n4183) );
ADDHXLTS U5572 ( .A(n4089), .B(n4088), .CO(n4079), .S(n4113) );
AOI222X1TS U5573 ( .A0(n4101), .A1(n4162), .B0(n4105), .B1(n4118), .C0(n2794), .C1(n4090), .Y(n4091) );
XOR2X1TS U5574 ( .A(n4092), .B(n4109), .Y(n4112) );
ADDHXLTS U5575 ( .A(n4094), .B(n4093), .CO(n4088), .S(n4174) );
AOI222X1TS U5576 ( .A0(n4101), .A1(n4151), .B0(n4105), .B1(n4140), .C0(n2794), .C1(n4139), .Y(n4095) );
XOR2X1TS U5577 ( .A(n4097), .B(n4109), .Y(n4173) );
AOI22X1TS U5578 ( .A0(n4098), .A1(n4129), .B0(n4101), .B1(n4139), .Y(n4099)
);
XOR2X1TS U5579 ( .A(n4100), .B(n4109), .Y(n4123) );
NAND2X1TS U5580 ( .A(n4101), .B(n4133), .Y(n4102) );
XOR2X1TS U5581 ( .A(n4103), .B(n4109), .Y(n4144) );
XOR2X1TS U5582 ( .A(n4110), .B(n4109), .Y(n4157) );
AOI222X1TS U5583 ( .A0(n4134), .A1(n4115), .B0(n4165), .B1(n4114), .C0(n3951), .C1(n4153), .Y(n4116) );
XOR2X1TS U5584 ( .A(n4117), .B(n4170), .Y(n4177) );
AOI222X1TS U5585 ( .A0(n4134), .A1(n4162), .B0(n4165), .B1(n4118), .C0(n3951), .C1(n4126), .Y(n4119) );
XOR2X1TS U5586 ( .A(n4121), .B(n754), .Y(n4150) );
ADDHX1TS U5587 ( .A(n4123), .B(n4122), .CO(n4158), .S(n4149) );
NOR2X1TS U5588 ( .A(n4150), .B(n4149), .Y(n4286) );
AOI22X1TS U5589 ( .A0(n4134), .A1(n4139), .B0(n4130), .B1(n4129), .Y(n4131)
);
XOR2X1TS U5590 ( .A(n4132), .B(n754), .Y(n4281) );
NAND2X1TS U5591 ( .A(n4134), .B(n4133), .Y(n4135) );
OAI21X1TS U5592 ( .A0(n4137), .A1(n4136), .B0(n4135), .Y(n4285) );
XOR2X1TS U5593 ( .A(n4285), .B(n754), .Y(n4138) );
NAND2X1TS U5594 ( .A(n4281), .B(n4282), .Y(n4279) );
NOR2X1TS U5595 ( .A(n756), .B(n4279), .Y(n4276) );
AOI222X1TS U5596 ( .A0(n4134), .A1(n4151), .B0(n4165), .B1(n4140), .C0(n3951), .C1(n4139), .Y(n4141) );
XOR2X1TS U5597 ( .A(n4143), .B(n754), .Y(n4147) );
ADDHX1TS U5598 ( .A(n4145), .B(n4144), .CO(n4122), .S(n4146) );
NAND2X1TS U5599 ( .A(n4147), .B(n4146), .Y(n4274) );
INVX2TS U5600 ( .A(n4274), .Y(n4148) );
AOI21X1TS U5601 ( .A0(n4276), .A1(n4275), .B0(n4148), .Y(n4289) );
NAND2X1TS U5602 ( .A(n4150), .B(n4149), .Y(n4287) );
OAI21X1TS U5603 ( .A0(n4286), .A1(n4289), .B0(n4287), .Y(n4301) );
AOI222X1TS U5604 ( .A0(n4134), .A1(n4153), .B0(n4165), .B1(n4152), .C0(n3951), .C1(n4151), .Y(n4154) );
XOR2X1TS U5605 ( .A(n4156), .B(n4170), .Y(n4160) );
ADDHX1TS U5606 ( .A(n4158), .B(n4157), .CO(n4172), .S(n4159) );
NAND2X1TS U5607 ( .A(n4160), .B(n4159), .Y(n4298) );
INVX2TS U5608 ( .A(n4298), .Y(n4161) );
AOI21X1TS U5609 ( .A0(n4301), .A1(n4299), .B0(n4161), .Y(n4401) );
AOI222X1TS U5610 ( .A0(n4134), .A1(n4166), .B0(n4165), .B1(n4164), .C0(n3951), .C1(n4162), .Y(n4168) );
XOR2X1TS U5611 ( .A(n4171), .B(n4170), .Y(n4176) );
CMPR32X2TS U5612 ( .A(n4174), .B(n4173), .C(n4172), .CO(n4111), .S(n4175) );
NOR2X1TS U5613 ( .A(n4176), .B(n4175), .Y(n4397) );
NAND2X1TS U5614 ( .A(n4176), .B(n4175), .Y(n4398) );
OAI21X1TS U5615 ( .A0(n4401), .A1(n4397), .B0(n4398), .Y(n4479) );
NAND2X1TS U5616 ( .A(n4178), .B(n4177), .Y(n4499) );
NAND2X1TS U5617 ( .A(n4180), .B(n4179), .Y(n4481) );
AOI21X1TS U5618 ( .A0(n4182), .A1(n4479), .B0(n4181), .Y(n4296) );
CMPR32X2TS U5619 ( .A(n4185), .B(n4184), .C(n4183), .CO(n4186), .S(n4180) );
NOR2X1TS U5620 ( .A(Sgf_operation_mult_x_1_n2752), .B(n4186), .Y(n4292) );
NAND2X1TS U5621 ( .A(Sgf_operation_mult_x_1_n2752), .B(n4186), .Y(n4293) );
OAI21X1TS U5622 ( .A0(n4296), .A1(n4292), .B0(n4293), .Y(n4486) );
NAND2X1TS U5623 ( .A(Sgf_operation_mult_x_1_n2747), .B(
Sgf_operation_mult_x_1_n2751), .Y(n4519) );
NAND2X1TS U5624 ( .A(Sgf_operation_mult_x_1_n2742), .B(
Sgf_operation_mult_x_1_n2746), .Y(n4523) );
AOI21X1TS U5625 ( .A0(n4486), .A1(n4188), .B0(n4187), .Y(n4490) );
NAND2X1TS U5626 ( .A(n4512), .B(n4515), .Y(n4191) );
NAND2X1TS U5627 ( .A(Sgf_operation_mult_x_1_n2735), .B(
Sgf_operation_mult_x_1_n2741), .Y(n4491) );
INVX2TS U5628 ( .A(n4491), .Y(n4511) );
NAND2X1TS U5629 ( .A(Sgf_operation_mult_x_1_n2728), .B(
Sgf_operation_mult_x_1_n2734), .Y(n4514) );
INVX2TS U5630 ( .A(n4514), .Y(n4189) );
AOI21X1TS U5631 ( .A0(n4511), .A1(n4515), .B0(n4189), .Y(n4190) );
NAND2X1TS U5632 ( .A(Sgf_operation_mult_x_1_n2721), .B(
Sgf_operation_mult_x_1_n2727), .Y(n4504) );
INVX2TS U5633 ( .A(n4504), .Y(n4193) );
NAND2X1TS U5634 ( .A(Sgf_operation_mult_x_1_n2713), .B(
Sgf_operation_mult_x_1_n2720), .Y(n4506) );
INVX2TS U5635 ( .A(n4506), .Y(n4192) );
AOI21X1TS U5636 ( .A0(n4507), .A1(n4193), .B0(n4192), .Y(n4553) );
NAND2X1TS U5637 ( .A(Sgf_operation_mult_x_1_n2705), .B(
Sgf_operation_mult_x_1_n2712), .Y(n4557) );
AOI21X1TS U5638 ( .A0(n4195), .A1(n4494), .B0(n4194), .Y(n4528) );
NAND2X1TS U5639 ( .A(n4531), .B(n4536), .Y(n4198) );
NAND2X1TS U5640 ( .A(Sgf_operation_mult_x_1_n2697), .B(
Sgf_operation_mult_x_1_n2704), .Y(n4535) );
INVX2TS U5641 ( .A(n4535), .Y(n4529) );
NAND2X1TS U5642 ( .A(Sgf_operation_mult_x_1_n2687), .B(
Sgf_operation_mult_x_1_n2696), .Y(n4530) );
INVX2TS U5643 ( .A(n4530), .Y(n4196) );
AOI21X1TS U5644 ( .A0(n4531), .A1(n4529), .B0(n4196), .Y(n4197) );
NOR2X1TS U5645 ( .A(Sgf_operation_mult_x_1_n2677), .B(
Sgf_operation_mult_x_1_n2686), .Y(n4574) );
INVX2TS U5646 ( .A(n4574), .Y(n4550) );
NAND2X1TS U5647 ( .A(n4577), .B(n4550), .Y(n4566) );
NAND2X1TS U5648 ( .A(Sgf_operation_mult_x_1_n2677), .B(
Sgf_operation_mult_x_1_n2686), .Y(n4573) );
INVX2TS U5649 ( .A(n4573), .Y(n4200) );
NAND2X1TS U5650 ( .A(Sgf_operation_mult_x_1_n2667), .B(
Sgf_operation_mult_x_1_n2676), .Y(n4576) );
INVX2TS U5651 ( .A(n4576), .Y(n4199) );
AOI21X1TS U5652 ( .A0(n4577), .A1(n4200), .B0(n4199), .Y(n4565) );
NAND2X1TS U5653 ( .A(Sgf_operation_mult_x_1_n2656), .B(
Sgf_operation_mult_x_1_n2666), .Y(n4568) );
AOI21X1TS U5654 ( .A0(n4549), .A1(n4202), .B0(n4201), .Y(n4540) );
NOR2X1TS U5655 ( .A(n4581), .B(n4543), .Y(n4204) );
NOR2X1TS U5656 ( .A(Sgf_operation_mult_x_1_n2645), .B(
Sgf_operation_mult_x_1_n2655), .Y(n4562) );
NOR2X1TS U5657 ( .A(n4562), .B(n4603), .Y(n4542) );
NAND2X1TS U5658 ( .A(n4204), .B(n4542), .Y(n4206) );
NAND2X1TS U5659 ( .A(Sgf_operation_mult_x_1_n2645), .B(
Sgf_operation_mult_x_1_n2655), .Y(n4599) );
NAND2X1TS U5660 ( .A(Sgf_operation_mult_x_1_n2634), .B(
Sgf_operation_mult_x_1_n2644), .Y(n4604) );
OAI21X1TS U5661 ( .A0(n4603), .A1(n4599), .B0(n4604), .Y(n4541) );
NAND2X1TS U5662 ( .A(Sgf_operation_mult_x_1_n2621), .B(
Sgf_operation_mult_x_1_n2633), .Y(n4582) );
NAND2X1TS U5663 ( .A(Sgf_operation_mult_x_1_n2608), .B(
Sgf_operation_mult_x_1_n2620), .Y(n4544) );
AOI21X1TS U5664 ( .A0(n4204), .A1(n4541), .B0(n4203), .Y(n4205) );
OAI21X1TS U5665 ( .A0(n4540), .A1(n4206), .B0(n4205), .Y(n4339) );
NAND2X1TS U5666 ( .A(n4372), .B(n4387), .Y(n4210) );
NOR2X1TS U5667 ( .A(n4587), .B(n4593), .Y(n4340) );
NAND2X1TS U5668 ( .A(n4340), .B(n4345), .Y(n4369) );
NAND2X1TS U5669 ( .A(Sgf_operation_mult_x_1_n2595), .B(
Sgf_operation_mult_x_1_n2607), .Y(n4594) );
NAND2X1TS U5670 ( .A(Sgf_operation_mult_x_1_n2581), .B(
Sgf_operation_mult_x_1_n2594), .Y(n4588) );
OAI21X1TS U5671 ( .A0(n4587), .A1(n4594), .B0(n4588), .Y(n4341) );
NAND2X1TS U5672 ( .A(Sgf_operation_mult_x_1_n2567), .B(
Sgf_operation_mult_x_1_n2580), .Y(n4344) );
INVX2TS U5673 ( .A(n4344), .Y(n4207) );
AOI21X1TS U5674 ( .A0(n4341), .A1(n4345), .B0(n4207), .Y(n4368) );
NAND2X1TS U5675 ( .A(Sgf_operation_mult_x_1_n2553), .B(
Sgf_operation_mult_x_1_n2566), .Y(n4386) );
INVX2TS U5676 ( .A(n4386), .Y(n4370) );
NAND2X1TS U5677 ( .A(Sgf_operation_mult_x_1_n2537), .B(
Sgf_operation_mult_x_1_n2552), .Y(n4371) );
INVX2TS U5678 ( .A(n4371), .Y(n4208) );
AOI21X1TS U5679 ( .A0(n4372), .A1(n4370), .B0(n4208), .Y(n4209) );
AOI21X1TS U5680 ( .A0(n4339), .A1(n4212), .B0(n4211), .Y(n4311) );
NOR2X1TS U5681 ( .A(n4351), .B(n4391), .Y(n4214) );
NOR2X1TS U5682 ( .A(Sgf_operation_mult_x_1_n2521), .B(
Sgf_operation_mult_x_1_n2536), .Y(n4312) );
NOR2X1TS U5683 ( .A(n4380), .B(n4312), .Y(n4350) );
NAND2X1TS U5684 ( .A(n4214), .B(n4350), .Y(n4216) );
NAND2X1TS U5685 ( .A(Sgf_operation_mult_x_1_n2521), .B(
Sgf_operation_mult_x_1_n2536), .Y(n4376) );
NAND2X1TS U5686 ( .A(Sgf_operation_mult_x_1_n2505), .B(
Sgf_operation_mult_x_1_n2520), .Y(n4381) );
OAI21X1TS U5687 ( .A0(n4380), .A1(n4376), .B0(n4381), .Y(n4349) );
NAND2X1TS U5688 ( .A(Sgf_operation_mult_x_1_n2488), .B(
Sgf_operation_mult_x_1_n2504), .Y(n4392) );
NAND2X1TS U5689 ( .A(Sgf_operation_mult_x_1_n2471), .B(
Sgf_operation_mult_x_1_n2487), .Y(n4352) );
AOI21X1TS U5690 ( .A0(n4214), .A1(n4349), .B0(n4213), .Y(n4215) );
NOR2X1TS U5691 ( .A(Sgf_operation_mult_x_1_n2416), .B(
Sgf_operation_mult_x_1_n2434), .Y(n4320) );
NOR2X1TS U5692 ( .A(n4322), .B(n4320), .Y(n4218) );
NOR2X1TS U5693 ( .A(n4333), .B(n4362), .Y(n4316) );
NAND2X1TS U5694 ( .A(n4218), .B(n4316), .Y(n4358) );
NAND2X1TS U5695 ( .A(n4464), .B(n4461), .Y(n4221) );
NOR2X1TS U5696 ( .A(n4358), .B(n4221), .Y(n4223) );
NAND2X1TS U5697 ( .A(Sgf_operation_mult_x_1_n2454), .B(
Sgf_operation_mult_x_1_n2470), .Y(n4363) );
NAND2X1TS U5698 ( .A(Sgf_operation_mult_x_1_n2435), .B(
Sgf_operation_mult_x_1_n2453), .Y(n4334) );
OAI21X1TS U5699 ( .A0(n4333), .A1(n4363), .B0(n4334), .Y(n4317) );
NAND2X1TS U5700 ( .A(Sgf_operation_mult_x_1_n2416), .B(
Sgf_operation_mult_x_1_n2434), .Y(n4328) );
NAND2X1TS U5701 ( .A(Sgf_operation_mult_x_1_n2397), .B(
Sgf_operation_mult_x_1_n2415), .Y(n4323) );
AOI21X1TS U5702 ( .A0(n4218), .A1(n4317), .B0(n4217), .Y(n4357) );
NAND2X1TS U5703 ( .A(Sgf_operation_mult_x_1_n2377), .B(
Sgf_operation_mult_x_1_n2396), .Y(n4359) );
INVX2TS U5704 ( .A(n4359), .Y(n4460) );
NAND2X1TS U5705 ( .A(Sgf_operation_mult_x_1_n2357), .B(
Sgf_operation_mult_x_1_n2376), .Y(n4463) );
INVX2TS U5706 ( .A(n4463), .Y(n4219) );
AOI21X1TS U5707 ( .A0(n4464), .A1(n4460), .B0(n4219), .Y(n4220) );
OAI21X1TS U5708 ( .A0(n4357), .A1(n4221), .B0(n4220), .Y(n4222) );
AOI21X2TS U5709 ( .A0(n4315), .A1(n4223), .B0(n4222), .Y(n4408) );
NOR2X1TS U5710 ( .A(Sgf_operation_mult_x_1_n2293), .B(
Sgf_operation_mult_x_1_n2314), .Y(n4443) );
INVX2TS U5711 ( .A(n4443), .Y(n4450) );
NAND2X1TS U5712 ( .A(n4445), .B(n4450), .Y(n4228) );
NAND2X1TS U5713 ( .A(n4470), .B(n4475), .Y(n4439) );
NOR2X1TS U5714 ( .A(n4228), .B(n4439), .Y(n4410) );
NOR2X2TS U5715 ( .A(Sgf_operation_mult_x_1_n2225), .B(
Sgf_operation_mult_x_1_n2247), .Y(n4411) );
NOR2X1TS U5716 ( .A(n4411), .B(n4454), .Y(n4230) );
NAND2X1TS U5717 ( .A(n4410), .B(n4230), .Y(n4232) );
NAND2X1TS U5718 ( .A(Sgf_operation_mult_x_1_n2337), .B(
Sgf_operation_mult_x_1_n2356), .Y(n4474) );
INVX2TS U5719 ( .A(n4474), .Y(n4468) );
NAND2X1TS U5720 ( .A(Sgf_operation_mult_x_1_n2315), .B(
Sgf_operation_mult_x_1_n2336), .Y(n4469) );
INVX2TS U5721 ( .A(n4469), .Y(n4224) );
AOI21X1TS U5722 ( .A0(n4470), .A1(n4468), .B0(n4224), .Y(n4440) );
NAND2X1TS U5723 ( .A(Sgf_operation_mult_x_1_n2293), .B(
Sgf_operation_mult_x_1_n2314), .Y(n4449) );
INVX2TS U5724 ( .A(n4449), .Y(n4226) );
NAND2X1TS U5725 ( .A(Sgf_operation_mult_x_1_n2271), .B(
Sgf_operation_mult_x_1_n2292), .Y(n4444) );
INVX2TS U5726 ( .A(n4444), .Y(n4225) );
AOI21X1TS U5727 ( .A0(n4445), .A1(n4226), .B0(n4225), .Y(n4227) );
OAI21X1TS U5728 ( .A0(n4228), .A1(n4440), .B0(n4227), .Y(n4409) );
NAND2X1TS U5729 ( .A(Sgf_operation_mult_x_1_n2248), .B(
Sgf_operation_mult_x_1_n2270), .Y(n4455) );
NAND2X1TS U5730 ( .A(Sgf_operation_mult_x_1_n2225), .B(
Sgf_operation_mult_x_1_n2247), .Y(n4412) );
AOI21X1TS U5731 ( .A0(n4409), .A1(n4230), .B0(n4229), .Y(n4231) );
NAND2X1TS U5732 ( .A(Sgf_operation_mult_x_1_n2202), .B(
Sgf_operation_mult_x_1_n2224), .Y(n4430) );
NAND2X1TS U5733 ( .A(Sgf_operation_mult_x_1_n2177), .B(
Sgf_operation_mult_x_1_n2201), .Y(n4434) );
OAI21X1TS U5734 ( .A0(n4433), .A1(n4430), .B0(n4434), .Y(n4305) );
NAND2X1TS U5735 ( .A(Sgf_operation_mult_x_1_n2152), .B(
Sgf_operation_mult_x_1_n2176), .Y(n4417) );
NAND2X1TS U5736 ( .A(Sgf_operation_mult_x_1_n2127), .B(
Sgf_operation_mult_x_1_n2151), .Y(n4422) );
AOI21X1TS U5737 ( .A0(n4234), .A1(n4305), .B0(n4233), .Y(n4403) );
NAND2X1TS U5738 ( .A(Sgf_operation_mult_x_1_n2103), .B(
Sgf_operation_mult_x_1_n2126), .Y(n4882) );
NAND2X1TS U5739 ( .A(Sgf_operation_mult_x_1_n2079), .B(
Sgf_operation_mult_x_1_n2102), .Y(n4887) );
OAI21X1TS U5740 ( .A0(n4886), .A1(n4882), .B0(n4887), .Y(n4864) );
NAND2X1TS U5741 ( .A(Sgf_operation_mult_x_1_n2055), .B(
Sgf_operation_mult_x_1_n2078), .Y(n4877) );
NAND2X1TS U5742 ( .A(Sgf_operation_mult_x_1_n2031), .B(
Sgf_operation_mult_x_1_n2054), .Y(n4871) );
AOI21X1TS U5743 ( .A0(n4236), .A1(n4864), .B0(n4235), .Y(n4237) );
OAI21X1TS U5744 ( .A0(n4403), .A1(n4238), .B0(n4237), .Y(n4239) );
NOR2X1TS U5745 ( .A(n4844), .B(n4838), .Y(n4242) );
NOR2X1TS U5746 ( .A(Sgf_operation_mult_x_1_n2007), .B(
Sgf_operation_mult_x_1_n2030), .Y(n4850) );
NOR2X1TS U5747 ( .A(n4850), .B(n4852), .Y(n4837) );
NAND2X1TS U5748 ( .A(n4242), .B(n4837), .Y(n4805) );
NOR2X1TS U5749 ( .A(n4830), .B(n4824), .Y(n4810) );
NOR2X1TS U5750 ( .A(n4811), .B(n4817), .Y(n4244) );
NAND2X1TS U5751 ( .A(n4810), .B(n4244), .Y(n4246) );
NOR2X1TS U5752 ( .A(n4805), .B(n4246), .Y(n4745) );
NOR2X1TS U5753 ( .A(n4793), .B(n4799), .Y(n4779) );
NOR2X1TS U5754 ( .A(n4786), .B(n4780), .Y(n4248) );
NAND2X1TS U5755 ( .A(n4779), .B(n4248), .Y(n4746) );
NOR2X1TS U5756 ( .A(n4765), .B(n4771), .Y(n4751) );
NOR2X1TS U5757 ( .A(n4758), .B(n4752), .Y(n4250) );
NAND2X1TS U5758 ( .A(n4751), .B(n4250), .Y(n4252) );
NAND2X1TS U5759 ( .A(n4745), .B(n4254), .Y(n4256) );
NAND2X1TS U5760 ( .A(Sgf_operation_mult_x_1_n2007), .B(
Sgf_operation_mult_x_1_n2030), .Y(n4858) );
NAND2X1TS U5761 ( .A(Sgf_operation_mult_x_1_n1983), .B(
Sgf_operation_mult_x_1_n2006), .Y(n4853) );
OAI21X1TS U5762 ( .A0(n4852), .A1(n4858), .B0(n4853), .Y(n4836) );
NAND2X1TS U5763 ( .A(Sgf_operation_mult_x_1_n1959), .B(
Sgf_operation_mult_x_1_n1982), .Y(n4845) );
NAND2X1TS U5764 ( .A(Sgf_operation_mult_x_1_n1935), .B(
Sgf_operation_mult_x_1_n1958), .Y(n4839) );
AOI21X1TS U5765 ( .A0(n4242), .A1(n4836), .B0(n4241), .Y(n4806) );
NAND2X1TS U5766 ( .A(Sgf_operation_mult_x_1_n1910), .B(
Sgf_operation_mult_x_1_n1934), .Y(n4831) );
NAND2X1TS U5767 ( .A(Sgf_operation_mult_x_1_n1885), .B(
Sgf_operation_mult_x_1_n1909), .Y(n4825) );
OAI21X1TS U5768 ( .A0(n4831), .A1(n4824), .B0(n4825), .Y(n4809) );
NAND2X1TS U5769 ( .A(Sgf_operation_mult_x_1_n1862), .B(
Sgf_operation_mult_x_1_n1884), .Y(n4818) );
NAND2X1TS U5770 ( .A(Sgf_operation_mult_x_1_n1840), .B(
Sgf_operation_mult_x_1_n1861), .Y(n4812) );
AOI21X1TS U5771 ( .A0(n4244), .A1(n4809), .B0(n4243), .Y(n4245) );
OAI21X1TS U5772 ( .A0(n4806), .A1(n4246), .B0(n4245), .Y(n4744) );
NAND2X1TS U5773 ( .A(Sgf_operation_mult_x_1_n1817), .B(
Sgf_operation_mult_x_1_n1839), .Y(n4800) );
NAND2X1TS U5774 ( .A(Sgf_operation_mult_x_1_n1796), .B(
Sgf_operation_mult_x_1_n1816), .Y(n4794) );
OAI21X1TS U5775 ( .A0(n4793), .A1(n4800), .B0(n4794), .Y(n4778) );
NAND2X1TS U5776 ( .A(Sgf_operation_mult_x_1_n1775), .B(
Sgf_operation_mult_x_1_n1795), .Y(n4787) );
NAND2X1TS U5777 ( .A(Sgf_operation_mult_x_1_n1753), .B(
Sgf_operation_mult_x_1_n1774), .Y(n4781) );
AOI21X1TS U5778 ( .A0(n4778), .A1(n4248), .B0(n4247), .Y(n4747) );
NAND2X1TS U5779 ( .A(Sgf_operation_mult_x_1_n1733), .B(
Sgf_operation_mult_x_1_n1752), .Y(n4772) );
NAND2X1TS U5780 ( .A(Sgf_operation_mult_x_1_n1714), .B(
Sgf_operation_mult_x_1_n1732), .Y(n4766) );
OAI21X1TS U5781 ( .A0(n4765), .A1(n4772), .B0(n4766), .Y(n4750) );
NAND2X1TS U5782 ( .A(Sgf_operation_mult_x_1_n1694), .B(
Sgf_operation_mult_x_1_n1713), .Y(n4759) );
NAND2X1TS U5783 ( .A(Sgf_operation_mult_x_1_n1676), .B(
Sgf_operation_mult_x_1_n1693), .Y(n4753) );
AOI21X1TS U5784 ( .A0(n4750), .A1(n4250), .B0(n4249), .Y(n4251) );
AOI21X1TS U5785 ( .A0(n4744), .A1(n4254), .B0(n4253), .Y(n4255) );
NOR2X1TS U5786 ( .A(Sgf_operation_mult_x_1_n1657), .B(
Sgf_operation_mult_x_1_n1675), .Y(n4732) );
INVX2TS U5787 ( .A(n4732), .Y(n4739) );
NAND2X1TS U5788 ( .A(n4739), .B(n4734), .Y(n4720) );
NAND2X1TS U5789 ( .A(n4723), .B(n4728), .Y(n4261) );
NOR2X1TS U5790 ( .A(n4720), .B(n4261), .Y(n4695) );
NAND2X1TS U5791 ( .A(n4715), .B(n4710), .Y(n4700) );
NOR2X2TS U5792 ( .A(Sgf_operation_mult_x_1_n1558), .B(
Sgf_operation_mult_x_1_n1573), .Y(n4701) );
NOR2X1TS U5793 ( .A(n4700), .B(n4701), .Y(n4264) );
NAND2X1TS U5794 ( .A(n4695), .B(n4264), .Y(n4688) );
NOR2X2TS U5795 ( .A(Sgf_operation_mult_x_1_n1542), .B(
Sgf_operation_mult_x_1_n1557), .Y(n4689) );
NOR2X2TS U5796 ( .A(Sgf_operation_mult_x_1_n1515), .B(
Sgf_operation_mult_x_1_n1527), .Y(n4672) );
NAND2X1TS U5797 ( .A(Sgf_operation_mult_x_1_n1657), .B(
Sgf_operation_mult_x_1_n1675), .Y(n4738) );
NAND2X1TS U5798 ( .A(Sgf_operation_mult_x_1_n1638), .B(
Sgf_operation_mult_x_1_n1656), .Y(n4733) );
INVX2TS U5799 ( .A(n4733), .Y(n4257) );
NAND2X1TS U5800 ( .A(Sgf_operation_mult_x_1_n1621), .B(
Sgf_operation_mult_x_1_n1637), .Y(n4727) );
INVX2TS U5801 ( .A(n4727), .Y(n4721) );
NAND2X1TS U5802 ( .A(Sgf_operation_mult_x_1_n1605), .B(
Sgf_operation_mult_x_1_n1620), .Y(n4722) );
INVX2TS U5803 ( .A(n4722), .Y(n4259) );
AOI21X1TS U5804 ( .A0(n4723), .A1(n4721), .B0(n4259), .Y(n4260) );
OAI21X1TS U5805 ( .A0(n4719), .A1(n4261), .B0(n4260), .Y(n4696) );
NAND2X1TS U5806 ( .A(Sgf_operation_mult_x_1_n1588), .B(
Sgf_operation_mult_x_1_n1604), .Y(n4714) );
INVX2TS U5807 ( .A(n4714), .Y(n4707) );
NAND2X1TS U5808 ( .A(Sgf_operation_mult_x_1_n1574), .B(
Sgf_operation_mult_x_1_n1587), .Y(n4709) );
INVX2TS U5809 ( .A(n4709), .Y(n4262) );
AOI21X1TS U5810 ( .A0(n4710), .A1(n4707), .B0(n4262), .Y(n4699) );
NAND2X1TS U5811 ( .A(Sgf_operation_mult_x_1_n1558), .B(
Sgf_operation_mult_x_1_n1573), .Y(n4702) );
AOI21X1TS U5812 ( .A0(n4696), .A1(n4264), .B0(n4263), .Y(n4687) );
NAND2X1TS U5813 ( .A(Sgf_operation_mult_x_1_n1542), .B(
Sgf_operation_mult_x_1_n1557), .Y(n4690) );
OAI21X1TS U5814 ( .A0(n4687), .A1(n4689), .B0(n4690), .Y(n4679) );
NAND2X1TS U5815 ( .A(Sgf_operation_mult_x_1_n1528), .B(
Sgf_operation_mult_x_1_n1541), .Y(n4682) );
INVX2TS U5816 ( .A(n4682), .Y(n4265) );
AFHCINX2TS U5817 ( .CIN(n4268), .B(n4613), .A(n4269), .S(n4273) );
NAND2X1TS U5818 ( .A(n4275), .B(n4274), .Y(n4277) );
XNOR2X1TS U5819 ( .A(n4277), .B(n4276), .Y(n4278) );
MX2X1TS U5820 ( .A(P_Sgf[3]), .B(n4278), .S0(n4892), .Y(Sgf_operation_n106)
);
XOR2XLTS U5821 ( .A(n756), .B(n4279), .Y(n4280) );
MX2X1TS U5822 ( .A(P_Sgf[2]), .B(n4280), .S0(n4892), .Y(Sgf_operation_n107)
);
INVX2TS U5823 ( .A(n4281), .Y(n4283) );
XNOR2X1TS U5824 ( .A(n4283), .B(n4282), .Y(n4284) );
MX2X1TS U5825 ( .A(P_Sgf[1]), .B(n4284), .S0(n4892), .Y(Sgf_operation_n108)
);
MX2X1TS U5826 ( .A(P_Sgf[0]), .B(n4285), .S0(n4892), .Y(Sgf_operation_n109)
);
INVX2TS U5827 ( .A(n4286), .Y(n4288) );
NAND2X1TS U5828 ( .A(n4288), .B(n4287), .Y(n4290) );
XOR2XLTS U5829 ( .A(n4290), .B(n4289), .Y(n4291) );
MX2X1TS U5830 ( .A(P_Sgf[4]), .B(n4291), .S0(n4892), .Y(Sgf_operation_n105)
);
INVX2TS U5831 ( .A(n4292), .Y(n4294) );
NAND2X1TS U5832 ( .A(n4294), .B(n4293), .Y(n4295) );
XOR2XLTS U5833 ( .A(n4296), .B(n4295), .Y(n4297) );
MX2X1TS U5834 ( .A(P_Sgf[9]), .B(n4297), .S0(n4892), .Y(Sgf_operation_n100)
);
NAND2X1TS U5835 ( .A(n4299), .B(n4298), .Y(n4300) );
XNOR2X1TS U5836 ( .A(n4301), .B(n4300), .Y(n4302) );
MX2X1TS U5837 ( .A(P_Sgf[5]), .B(n4302), .S0(n4892), .Y(Sgf_operation_n104)
);
INVX2TS U5838 ( .A(n4303), .Y(n4432) );
INVX2TS U5839 ( .A(n4304), .Y(n4307) );
INVX2TS U5840 ( .A(n4305), .Y(n4306) );
OAI21X1TS U5841 ( .A0(n4432), .A1(n4307), .B0(n4306), .Y(n4420) );
INVX2TS U5842 ( .A(n4308), .Y(n4419) );
NAND2X1TS U5843 ( .A(n4419), .B(n4417), .Y(n4309) );
XNOR2X1TS U5844 ( .A(n4420), .B(n4309), .Y(n4310) );
INVX2TS U5845 ( .A(n4311), .Y(n4379) );
INVX2TS U5846 ( .A(n4312), .Y(n4378) );
NAND2X1TS U5847 ( .A(n4378), .B(n4376), .Y(n4313) );
XNOR2X1TS U5848 ( .A(n4379), .B(n4313), .Y(n4314) );
INVX2TS U5849 ( .A(n4315), .Y(n4366) );
INVX2TS U5850 ( .A(n4316), .Y(n4319) );
INVX2TS U5851 ( .A(n4317), .Y(n4318) );
OAI21X1TS U5852 ( .A0(n4366), .A1(n4319), .B0(n4318), .Y(n4331) );
INVX2TS U5853 ( .A(n4320), .Y(n4329) );
INVX2TS U5854 ( .A(n4328), .Y(n4321) );
AOI21X1TS U5855 ( .A0(n4331), .A1(n4329), .B0(n4321), .Y(n4326) );
INVX2TS U5856 ( .A(n4322), .Y(n4324) );
NAND2X1TS U5857 ( .A(n4324), .B(n4323), .Y(n4325) );
XOR2X1TS U5858 ( .A(n4326), .B(n4325), .Y(n4327) );
NAND2X1TS U5859 ( .A(n4329), .B(n4328), .Y(n4330) );
XNOR2X1TS U5860 ( .A(n4331), .B(n4330), .Y(n4332) );
INVX2TS U5861 ( .A(n4333), .Y(n4335) );
NAND2X1TS U5862 ( .A(n4335), .B(n4334), .Y(n4336) );
XNOR2X1TS U5863 ( .A(n4337), .B(n4336), .Y(n4338) );
INVX2TS U5864 ( .A(n4339), .Y(n4597) );
INVX2TS U5865 ( .A(n4340), .Y(n4343) );
INVX2TS U5866 ( .A(n4341), .Y(n4342) );
NAND2X1TS U5867 ( .A(n4345), .B(n4344), .Y(n4346) );
XNOR2X1TS U5868 ( .A(n4347), .B(n4346), .Y(n4348) );
AOI21X1TS U5869 ( .A0(n4379), .A1(n4350), .B0(n4349), .Y(n4395) );
INVX2TS U5870 ( .A(n4351), .Y(n4353) );
NAND2X1TS U5871 ( .A(n4353), .B(n4352), .Y(n4354) );
XNOR2X1TS U5872 ( .A(n4355), .B(n4354), .Y(n4356) );
OAI21X1TS U5873 ( .A0(n4366), .A1(n4358), .B0(n4357), .Y(n4462) );
NAND2X1TS U5874 ( .A(n4461), .B(n4359), .Y(n4360) );
XNOR2X1TS U5875 ( .A(n4462), .B(n4360), .Y(n4361) );
INVX2TS U5876 ( .A(n4362), .Y(n4364) );
NAND2X1TS U5877 ( .A(n4364), .B(n4363), .Y(n4365) );
XOR2X1TS U5878 ( .A(n4366), .B(n4365), .Y(n4367) );
OAI21X1TS U5879 ( .A0(n4597), .A1(n4369), .B0(n4368), .Y(n4389) );
AOI21X1TS U5880 ( .A0(n4389), .A1(n4387), .B0(n4370), .Y(n4374) );
NAND2X1TS U5881 ( .A(n4372), .B(n4371), .Y(n4373) );
XOR2X1TS U5882 ( .A(n4374), .B(n4373), .Y(n4375) );
INVX2TS U5883 ( .A(n4376), .Y(n4377) );
AOI21X1TS U5884 ( .A0(n4379), .A1(n4378), .B0(n4377), .Y(n4384) );
INVX2TS U5885 ( .A(n4380), .Y(n4382) );
NAND2X1TS U5886 ( .A(n4382), .B(n4381), .Y(n4383) );
XOR2X1TS U5887 ( .A(n4384), .B(n4383), .Y(n4385) );
NAND2X1TS U5888 ( .A(n4387), .B(n4386), .Y(n4388) );
XNOR2X1TS U5889 ( .A(n4389), .B(n4388), .Y(n4390) );
INVX2TS U5890 ( .A(n4391), .Y(n4393) );
NAND2X1TS U5891 ( .A(n4393), .B(n4392), .Y(n4394) );
XOR2X1TS U5892 ( .A(n4395), .B(n4394), .Y(n4396) );
INVX2TS U5893 ( .A(n4397), .Y(n4399) );
NAND2X1TS U5894 ( .A(n4399), .B(n4398), .Y(n4400) );
XOR2XLTS U5895 ( .A(n4401), .B(n4400), .Y(n4402) );
MX2X1TS U5896 ( .A(P_Sgf[6]), .B(n4402), .S0(n4645), .Y(Sgf_operation_n103)
);
OAI21X1TS U5897 ( .A0(n4432), .A1(n4404), .B0(n4403), .Y(n4885) );
INVX2TS U5898 ( .A(n4885), .Y(n4867) );
INVX2TS U5899 ( .A(n4405), .Y(n4884) );
NAND2X1TS U5900 ( .A(n4884), .B(n4882), .Y(n4406) );
XOR2X1TS U5901 ( .A(n4867), .B(n4406), .Y(n4407) );
INVX2TS U5902 ( .A(n4408), .Y(n4477) );
AOI21X1TS U5903 ( .A0(n4477), .A1(n4410), .B0(n4409), .Y(n4458) );
INVX2TS U5904 ( .A(n4411), .Y(n4413) );
NAND2X1TS U5905 ( .A(n4413), .B(n4412), .Y(n4414) );
XNOR2X1TS U5906 ( .A(n4415), .B(n4414), .Y(n4416) );
INVX2TS U5907 ( .A(n4417), .Y(n4418) );
AOI21X1TS U5908 ( .A0(n4420), .A1(n4419), .B0(n4418), .Y(n4425) );
INVX2TS U5909 ( .A(n4421), .Y(n4423) );
NAND2X1TS U5910 ( .A(n4423), .B(n4422), .Y(n4424) );
XOR2X1TS U5911 ( .A(n4425), .B(n4424), .Y(n4426) );
INVX2TS U5912 ( .A(n4431), .Y(n4427) );
NAND2X1TS U5913 ( .A(n4427), .B(n4430), .Y(n4428) );
XOR2X1TS U5914 ( .A(n4432), .B(n4428), .Y(n4429) );
INVX2TS U5915 ( .A(n4433), .Y(n4435) );
NAND2X1TS U5916 ( .A(n4435), .B(n4434), .Y(n4436) );
XNOR2X1TS U5917 ( .A(n4437), .B(n4436), .Y(n4438) );
INVX2TS U5918 ( .A(n4439), .Y(n4442) );
INVX2TS U5919 ( .A(n4440), .Y(n4441) );
AOI21X1TS U5920 ( .A0(n4477), .A1(n4442), .B0(n4441), .Y(n4452) );
NAND2X1TS U5921 ( .A(n4445), .B(n4444), .Y(n4446) );
XNOR2X1TS U5922 ( .A(n4447), .B(n4446), .Y(n4448) );
NAND2X1TS U5923 ( .A(n4450), .B(n4449), .Y(n4451) );
XOR2X1TS U5924 ( .A(n4452), .B(n4451), .Y(n4453) );
INVX2TS U5925 ( .A(n4454), .Y(n4456) );
NAND2X1TS U5926 ( .A(n4456), .B(n4455), .Y(n4457) );
XOR2X1TS U5927 ( .A(n4458), .B(n4457), .Y(n4459) );
AOI21X1TS U5928 ( .A0(n4462), .A1(n4461), .B0(n4460), .Y(n4466) );
NAND2X1TS U5929 ( .A(n4464), .B(n4463), .Y(n4465) );
XOR2X1TS U5930 ( .A(n4466), .B(n4465), .Y(n4467) );
AOI21X1TS U5931 ( .A0(n4477), .A1(n4475), .B0(n4468), .Y(n4472) );
NAND2X1TS U5932 ( .A(n4470), .B(n4469), .Y(n4471) );
XOR2X1TS U5933 ( .A(n4472), .B(n4471), .Y(n4473) );
NAND2X1TS U5934 ( .A(n4475), .B(n4474), .Y(n4476) );
XNOR2X1TS U5935 ( .A(n4477), .B(n4476), .Y(n4478) );
INVX2TS U5936 ( .A(n4479), .Y(n4502) );
INVX2TS U5937 ( .A(n4480), .Y(n4482) );
NAND2X1TS U5938 ( .A(n4482), .B(n4481), .Y(n4483) );
XNOR2X1TS U5939 ( .A(n4484), .B(n4483), .Y(n4485) );
MX2X1TS U5940 ( .A(P_Sgf[8]), .B(n4485), .S0(n4652), .Y(Sgf_operation_n101)
);
INVX2TS U5941 ( .A(n4486), .Y(n4521) );
INVX2TS U5942 ( .A(n4520), .Y(n4487) );
NAND2X1TS U5943 ( .A(n4487), .B(n4519), .Y(n4488) );
XOR2XLTS U5944 ( .A(n4521), .B(n4488), .Y(n4489) );
MX2X1TS U5945 ( .A(P_Sgf[10]), .B(n4489), .S0(n4776), .Y(Sgf_operation_n99)
);
INVX2TS U5946 ( .A(n4490), .Y(n4513) );
NAND2X1TS U5947 ( .A(n4512), .B(n4491), .Y(n4492) );
XNOR2X1TS U5948 ( .A(n4513), .B(n4492), .Y(n4493) );
MX2X1TS U5949 ( .A(P_Sgf[12]), .B(n4493), .S0(n4645), .Y(Sgf_operation_n97)
);
INVX2TS U5950 ( .A(n4494), .Y(n4555) );
NAND2X1TS U5951 ( .A(n4495), .B(n4504), .Y(n4496) );
XOR2XLTS U5952 ( .A(n4555), .B(n4496), .Y(n4497) );
MX2X1TS U5953 ( .A(P_Sgf[14]), .B(n4497), .S0(n4645), .Y(Sgf_operation_n95)
);
INVX2TS U5954 ( .A(n4498), .Y(n4500) );
NAND2X1TS U5955 ( .A(n4500), .B(n4499), .Y(n4501) );
XOR2XLTS U5956 ( .A(n4502), .B(n4501), .Y(n4503) );
MX2X1TS U5957 ( .A(P_Sgf[7]), .B(n4503), .S0(n4652), .Y(Sgf_operation_n102)
);
NAND2X1TS U5958 ( .A(n4507), .B(n4506), .Y(n4508) );
XNOR2X1TS U5959 ( .A(n4509), .B(n4508), .Y(n4510) );
MX2X1TS U5960 ( .A(P_Sgf[15]), .B(n4510), .S0(n4776), .Y(Sgf_operation_n94)
);
AOI21X1TS U5961 ( .A0(n4513), .A1(n4512), .B0(n4511), .Y(n4517) );
NAND2X1TS U5962 ( .A(n4515), .B(n4514), .Y(n4516) );
XOR2XLTS U5963 ( .A(n4517), .B(n4516), .Y(n4518) );
MX2X1TS U5964 ( .A(P_Sgf[13]), .B(n4518), .S0(n4776), .Y(Sgf_operation_n96)
);
OAI21XLTS U5965 ( .A0(n4521), .A1(n4520), .B0(n4519), .Y(n4526) );
INVX2TS U5966 ( .A(n4522), .Y(n4524) );
NAND2X1TS U5967 ( .A(n4524), .B(n4523), .Y(n4525) );
XNOR2X1TS U5968 ( .A(n4526), .B(n4525), .Y(n4527) );
MX2X1TS U5969 ( .A(P_Sgf[11]), .B(n4527), .S0(n4652), .Y(Sgf_operation_n98)
);
INVX2TS U5970 ( .A(n4528), .Y(n4538) );
AOI21X1TS U5971 ( .A0(n4538), .A1(n4536), .B0(n4529), .Y(n4533) );
NAND2X1TS U5972 ( .A(n4531), .B(n4530), .Y(n4532) );
XOR2XLTS U5973 ( .A(n4533), .B(n4532), .Y(n4534) );
MX2X1TS U5974 ( .A(P_Sgf[18]), .B(n4534), .S0(n4645), .Y(Sgf_operation_n91)
);
NAND2X1TS U5975 ( .A(n4536), .B(n4535), .Y(n4537) );
XNOR2X1TS U5976 ( .A(n4538), .B(n4537), .Y(n4539) );
MX2X1TS U5977 ( .A(P_Sgf[17]), .B(n4539), .S0(n4776), .Y(Sgf_operation_n92)
);
INVX2TS U5978 ( .A(n4540), .Y(n4602) );
AOI21X1TS U5979 ( .A0(n4602), .A1(n4542), .B0(n4541), .Y(n4585) );
INVX2TS U5980 ( .A(n4543), .Y(n4545) );
NAND2X1TS U5981 ( .A(n4545), .B(n4544), .Y(n4546) );
XNOR2X1TS U5982 ( .A(n4547), .B(n4546), .Y(n4548) );
INVX2TS U5983 ( .A(n4549), .Y(n4575) );
NAND2X1TS U5984 ( .A(n4550), .B(n4573), .Y(n4551) );
XOR2XLTS U5985 ( .A(n4575), .B(n4551), .Y(n4552) );
MX2X1TS U5986 ( .A(P_Sgf[19]), .B(n4552), .S0(n4652), .Y(Sgf_operation_n90)
);
OAI21XLTS U5987 ( .A0(n4555), .A1(n4554), .B0(n4553), .Y(n4560) );
INVX2TS U5988 ( .A(n4556), .Y(n4558) );
NAND2X1TS U5989 ( .A(n4558), .B(n4557), .Y(n4559) );
XNOR2X1TS U5990 ( .A(n4560), .B(n4559), .Y(n4561) );
MX2X1TS U5991 ( .A(P_Sgf[16]), .B(n4561), .S0(n4895), .Y(Sgf_operation_n93)
);
INVX2TS U5992 ( .A(n4562), .Y(n4601) );
NAND2X1TS U5993 ( .A(n4601), .B(n4599), .Y(n4563) );
XNOR2X1TS U5994 ( .A(n4602), .B(n4563), .Y(n4564) );
MX2X1TS U5995 ( .A(P_Sgf[22]), .B(n4564), .S0(n4895), .Y(Sgf_operation_n87)
);
INVX2TS U5996 ( .A(n4567), .Y(n4569) );
NAND2X1TS U5997 ( .A(n4569), .B(n4568), .Y(n4570) );
XNOR2X1TS U5998 ( .A(n4571), .B(n4570), .Y(n4572) );
MX2X1TS U5999 ( .A(P_Sgf[21]), .B(n4572), .S0(n4645), .Y(Sgf_operation_n88)
);
NAND2X1TS U6000 ( .A(n4577), .B(n4576), .Y(n4578) );
XNOR2X1TS U6001 ( .A(n4579), .B(n4578), .Y(n4580) );
MX2X1TS U6002 ( .A(P_Sgf[20]), .B(n4580), .S0(n4776), .Y(Sgf_operation_n89)
);
INVX2TS U6003 ( .A(n4581), .Y(n4583) );
NAND2X1TS U6004 ( .A(n4583), .B(n4582), .Y(n4584) );
XOR2X1TS U6005 ( .A(n4585), .B(n4584), .Y(n4586) );
INVX2TS U6006 ( .A(n4587), .Y(n4589) );
NAND2X1TS U6007 ( .A(n4589), .B(n4588), .Y(n4590) );
XNOR2X1TS U6008 ( .A(n4591), .B(n4590), .Y(n4592) );
INVX2TS U6009 ( .A(n4593), .Y(n4595) );
NAND2X1TS U6010 ( .A(n4595), .B(n4594), .Y(n4596) );
XOR2X1TS U6011 ( .A(n4597), .B(n4596), .Y(n4598) );
INVX2TS U6012 ( .A(n4599), .Y(n4600) );
AOI21X1TS U6013 ( .A0(n4602), .A1(n4601), .B0(n4600), .Y(n4607) );
INVX2TS U6014 ( .A(n4603), .Y(n4605) );
NAND2X1TS U6015 ( .A(n4605), .B(n4604), .Y(n4606) );
XOR2X1TS U6016 ( .A(n4607), .B(n4606), .Y(n4608) );
INVX4TS U6017 ( .A(n4609), .Y(n4610) );
MX2X1TS U6018 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n4610), .Y(n527) );
MX2X1TS U6019 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n4610), .Y(n537) );
MX2X1TS U6020 ( .A(Data_MY[61]), .B(n705), .S0(n4610), .Y(n536) );
MX2X1TS U6021 ( .A(Data_MY[60]), .B(n706), .S0(n4610), .Y(n535) );
MX2X1TS U6022 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n4610), .Y(n534) );
MX2X1TS U6023 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n4610), .Y(n533) );
MX2X1TS U6024 ( .A(Data_MY[57]), .B(n712), .S0(n4610), .Y(n532) );
MX2X1TS U6025 ( .A(Data_MY[56]), .B(n713), .S0(n4610), .Y(n531) );
MX2X1TS U6026 ( .A(Data_MY[55]), .B(n711), .S0(n4610), .Y(n530) );
MX2X1TS U6027 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n4610), .Y(n529) );
MX2X1TS U6028 ( .A(Data_MY[53]), .B(n704), .S0(n4610), .Y(n528) );
MX2X1TS U6029 ( .A(Data_MX[62]), .B(n715), .S0(n4610), .Y(n601) );
MX2X1TS U6030 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n4610), .Y(n600) );
MX2X1TS U6031 ( .A(Data_MX[60]), .B(n717), .S0(n4908), .Y(n599) );
MX2X1TS U6032 ( .A(Data_MX[59]), .B(n718), .S0(n4908), .Y(n598) );
MX2X1TS U6033 ( .A(Data_MX[58]), .B(n714), .S0(n4908), .Y(n597) );
MX2X1TS U6034 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n4908), .Y(n596) );
MX2X1TS U6035 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n4908), .Y(n595) );
MX2X1TS U6036 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n4908), .Y(n594) );
MX2X1TS U6037 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n4908), .Y(n593) );
MX2X1TS U6038 ( .A(Data_MX[53]), .B(n709), .S0(n4908), .Y(n592) );
MX2X1TS U6039 ( .A(Data_MX[52]), .B(n710), .S0(n4908), .Y(n591) );
AFHCONX2TS U6040 ( .A(n4613), .B(n4612), .CI(n4611), .CON(n4268), .S(n4614)
);
AFHCONX2TS U6041 ( .A(Sgf_operation_mult_x_1_n1353), .B(
Sgf_operation_mult_x_1_n1350), .CI(n4630), .CON(n4628), .S(n4631) );
AFHCINX2TS U6042 ( .CIN(n4632), .B(Sgf_operation_mult_x_1_n1354), .A(
Sgf_operation_mult_x_1_n1358), .S(n4633), .CO(n4630) );
AFHCONX2TS U6043 ( .A(Sgf_operation_mult_x_1_n1359), .B(
Sgf_operation_mult_x_1_n1365), .CI(n4634), .CON(n4632), .S(n4635) );
AFHCINX2TS U6044 ( .CIN(n4636), .B(Sgf_operation_mult_x_1_n1372), .A(
Sgf_operation_mult_x_1_n1366), .S(n4637), .CO(n4634) );
AFHCONX2TS U6045 ( .A(Sgf_operation_mult_x_1_n1378), .B(
Sgf_operation_mult_x_1_n1373), .CI(n4638), .CON(n4636), .S(n4639) );
AFHCINX2TS U6046 ( .CIN(n4640), .B(Sgf_operation_mult_x_1_n1386), .A(
Sgf_operation_mult_x_1_n1379), .S(n4641), .CO(n4638) );
AFHCONX2TS U6047 ( .A(Sgf_operation_mult_x_1_n1393), .B(
Sgf_operation_mult_x_1_n1387), .CI(n4642), .CON(n4640), .S(n4643) );
AFHCINX2TS U6048 ( .CIN(n4644), .B(Sgf_operation_mult_x_1_n1394), .A(
Sgf_operation_mult_x_1_n1401), .S(n4646), .CO(n4642) );
AFHCONX2TS U6049 ( .A(Sgf_operation_mult_x_1_n1411), .B(
Sgf_operation_mult_x_1_n1402), .CI(n4647), .CON(n4644), .S(n4648) );
AFHCINX2TS U6050 ( .CIN(n4649), .B(Sgf_operation_mult_x_1_n1412), .A(
Sgf_operation_mult_x_1_n1421), .S(n4650), .CO(n4647) );
AFHCONX2TS U6051 ( .A(Sgf_operation_mult_x_1_n1430), .B(
Sgf_operation_mult_x_1_n1422), .CI(n4651), .CON(n4649), .S(n4653) );
AFHCINX2TS U6052 ( .CIN(n4654), .B(Sgf_operation_mult_x_1_n1431), .A(
Sgf_operation_mult_x_1_n1441), .S(n4655), .CO(n4651) );
AFHCONX2TS U6053 ( .A(Sgf_operation_mult_x_1_n1451), .B(
Sgf_operation_mult_x_1_n1442), .CI(n4656), .CON(n4654), .S(n4658) );
AFHCINX2TS U6054 ( .CIN(n4659), .B(Sgf_operation_mult_x_1_n1452), .A(
Sgf_operation_mult_x_1_n1462), .S(n4660), .CO(n4656) );
AFHCONX2TS U6055 ( .A(Sgf_operation_mult_x_1_n1463), .B(
Sgf_operation_mult_x_1_n1475), .CI(n4661), .CON(n4659), .S(n4662) );
AFHCINX2TS U6056 ( .CIN(n4663), .B(Sgf_operation_mult_x_1_n1488), .A(
Sgf_operation_mult_x_1_n1476), .S(n4664), .CO(n4661) );
AFHCONX2TS U6057 ( .A(Sgf_operation_mult_x_1_n1500), .B(
Sgf_operation_mult_x_1_n1489), .CI(n4665), .CON(n4663), .S(n4666) );
AFHCINX2TS U6058 ( .CIN(n4667), .B(Sgf_operation_mult_x_1_n1501), .A(
Sgf_operation_mult_x_1_n1514), .S(n4668), .CO(n4665) );
INVX2TS U6059 ( .A(n4669), .Y(n4741) );
XNOR2X1TS U6060 ( .A(n4676), .B(n4675), .Y(n4677) );
XNOR2X1TS U6061 ( .A(n4685), .B(n4684), .Y(n4686) );
NAND2X1TS U6062 ( .A(n4691), .B(n4690), .Y(n4692) );
XNOR2X1TS U6063 ( .A(n4693), .B(n4692), .Y(n4694) );
INVX2TS U6064 ( .A(n4696), .Y(n4697) );
OAI21X1TS U6065 ( .A0(n4741), .A1(n4698), .B0(n4697), .Y(n4708) );
INVX2TS U6066 ( .A(n4708), .Y(n4717) );
INVX2TS U6067 ( .A(n4701), .Y(n4703) );
NAND2X1TS U6068 ( .A(n4703), .B(n4702), .Y(n4704) );
XNOR2X1TS U6069 ( .A(n4705), .B(n4704), .Y(n4706) );
AOI21X1TS U6070 ( .A0(n4708), .A1(n4715), .B0(n4707), .Y(n4712) );
NAND2X1TS U6071 ( .A(n4710), .B(n4709), .Y(n4711) );
XOR2X1TS U6072 ( .A(n4712), .B(n4711), .Y(n4713) );
NAND2X1TS U6073 ( .A(n4715), .B(n4714), .Y(n4716) );
XOR2X1TS U6074 ( .A(n4717), .B(n4716), .Y(n4718) );
OAI21X1TS U6075 ( .A0(n4741), .A1(n4720), .B0(n4719), .Y(n4730) );
AOI21X1TS U6076 ( .A0(n4730), .A1(n4728), .B0(n4721), .Y(n4725) );
NAND2X1TS U6077 ( .A(n4723), .B(n4722), .Y(n4724) );
XOR2X1TS U6078 ( .A(n4725), .B(n4724), .Y(n4726) );
NAND2X1TS U6079 ( .A(n4728), .B(n4727), .Y(n4729) );
XNOR2X1TS U6080 ( .A(n4730), .B(n4729), .Y(n4731) );
NAND2X1TS U6081 ( .A(n4734), .B(n4733), .Y(n4735) );
XNOR2X1TS U6082 ( .A(n4736), .B(n4735), .Y(n4737) );
NAND2X1TS U6083 ( .A(n4739), .B(n4738), .Y(n4740) );
XOR2X1TS U6084 ( .A(n4741), .B(n4740), .Y(n4742) );
INVX2TS U6085 ( .A(n4743), .Y(n4861) );
AOI21X1TS U6086 ( .A0(n4861), .A1(n4745), .B0(n4744), .Y(n4792) );
INVX2TS U6087 ( .A(n4792), .Y(n4803) );
INVX2TS U6088 ( .A(n4746), .Y(n4749) );
INVX2TS U6089 ( .A(n4747), .Y(n4748) );
AOI21X1TS U6090 ( .A0(n4803), .A1(n4749), .B0(n4748), .Y(n4764) );
INVX2TS U6091 ( .A(n4764), .Y(n4775) );
AOI21X1TS U6092 ( .A0(n4775), .A1(n4751), .B0(n4750), .Y(n4762) );
INVX2TS U6093 ( .A(n4752), .Y(n4754) );
NAND2X1TS U6094 ( .A(n4754), .B(n4753), .Y(n4755) );
XNOR2X1TS U6095 ( .A(n4756), .B(n4755), .Y(n4757) );
INVX2TS U6096 ( .A(n4758), .Y(n4760) );
NAND2X1TS U6097 ( .A(n4760), .B(n4759), .Y(n4761) );
XOR2X1TS U6098 ( .A(n4762), .B(n4761), .Y(n4763) );
INVX2TS U6099 ( .A(n4765), .Y(n4767) );
NAND2X1TS U6100 ( .A(n4767), .B(n4766), .Y(n4768) );
XNOR2X1TS U6101 ( .A(n4769), .B(n4768), .Y(n4770) );
INVX2TS U6102 ( .A(n4771), .Y(n4773) );
NAND2X1TS U6103 ( .A(n4773), .B(n4772), .Y(n4774) );
XNOR2X1TS U6104 ( .A(n4775), .B(n4774), .Y(n4777) );
AOI21X1TS U6105 ( .A0(n4803), .A1(n4779), .B0(n4778), .Y(n4790) );
INVX2TS U6106 ( .A(n4780), .Y(n4782) );
NAND2X1TS U6107 ( .A(n4782), .B(n4781), .Y(n4783) );
XNOR2X1TS U6108 ( .A(n4784), .B(n4783), .Y(n4785) );
INVX2TS U6109 ( .A(n4786), .Y(n4788) );
NAND2X1TS U6110 ( .A(n4788), .B(n4787), .Y(n4789) );
XOR2X1TS U6111 ( .A(n4790), .B(n4789), .Y(n4791) );
INVX2TS U6112 ( .A(n4793), .Y(n4795) );
NAND2X1TS U6113 ( .A(n4795), .B(n4794), .Y(n4796) );
XNOR2X1TS U6114 ( .A(n4797), .B(n4796), .Y(n4798) );
INVX2TS U6115 ( .A(n4799), .Y(n4801) );
NAND2X1TS U6116 ( .A(n4801), .B(n4800), .Y(n4802) );
XNOR2X1TS U6117 ( .A(n4803), .B(n4802), .Y(n4804) );
INVX2TS U6118 ( .A(n4805), .Y(n4808) );
INVX2TS U6119 ( .A(n4806), .Y(n4807) );
AOI21X1TS U6120 ( .A0(n4861), .A1(n4808), .B0(n4807), .Y(n4823) );
INVX2TS U6121 ( .A(n4823), .Y(n4834) );
AOI21X1TS U6122 ( .A0(n4834), .A1(n4810), .B0(n4809), .Y(n4821) );
INVX2TS U6123 ( .A(n4811), .Y(n4813) );
NAND2X1TS U6124 ( .A(n4813), .B(n4812), .Y(n4814) );
XNOR2X1TS U6125 ( .A(n4815), .B(n4814), .Y(n4816) );
INVX2TS U6126 ( .A(n4817), .Y(n4819) );
NAND2X1TS U6127 ( .A(n4819), .B(n4818), .Y(n4820) );
XOR2X1TS U6128 ( .A(n4821), .B(n4820), .Y(n4822) );
INVX2TS U6129 ( .A(n4824), .Y(n4826) );
NAND2X1TS U6130 ( .A(n4826), .B(n4825), .Y(n4827) );
XNOR2X1TS U6131 ( .A(n4828), .B(n4827), .Y(n4829) );
INVX2TS U6132 ( .A(n4830), .Y(n4832) );
NAND2X1TS U6133 ( .A(n4832), .B(n4831), .Y(n4833) );
XNOR2X1TS U6134 ( .A(n4834), .B(n4833), .Y(n4835) );
AOI21X1TS U6135 ( .A0(n4861), .A1(n4837), .B0(n4836), .Y(n4848) );
INVX2TS U6136 ( .A(n4838), .Y(n4840) );
NAND2X1TS U6137 ( .A(n4840), .B(n4839), .Y(n4841) );
XNOR2X1TS U6138 ( .A(n4842), .B(n4841), .Y(n4843) );
INVX2TS U6139 ( .A(n4844), .Y(n4846) );
NAND2X1TS U6140 ( .A(n4846), .B(n4845), .Y(n4847) );
XOR2X1TS U6141 ( .A(n4848), .B(n4847), .Y(n4849) );
INVX2TS U6142 ( .A(n4850), .Y(n4859) );
INVX2TS U6143 ( .A(n4858), .Y(n4851) );
AOI21X1TS U6144 ( .A0(n4861), .A1(n4859), .B0(n4851), .Y(n4856) );
INVX2TS U6145 ( .A(n4852), .Y(n4854) );
NAND2X1TS U6146 ( .A(n4854), .B(n4853), .Y(n4855) );
XOR2X1TS U6147 ( .A(n4856), .B(n4855), .Y(n4857) );
NAND2X1TS U6148 ( .A(n4859), .B(n4858), .Y(n4860) );
XNOR2X1TS U6149 ( .A(n4861), .B(n4860), .Y(n4862) );
INVX2TS U6150 ( .A(n4863), .Y(n4866) );
INVX2TS U6151 ( .A(n4864), .Y(n4865) );
OAI21X1TS U6152 ( .A0(n4867), .A1(n4866), .B0(n4865), .Y(n4880) );
INVX2TS U6153 ( .A(n4868), .Y(n4878) );
INVX2TS U6154 ( .A(n4877), .Y(n4869) );
AOI21X1TS U6155 ( .A0(n4880), .A1(n4878), .B0(n4869), .Y(n4874) );
INVX2TS U6156 ( .A(n4870), .Y(n4872) );
NAND2X1TS U6157 ( .A(n4872), .B(n4871), .Y(n4873) );
XOR2X1TS U6158 ( .A(n4874), .B(n4873), .Y(n4876) );
NAND2X1TS U6159 ( .A(n4878), .B(n4877), .Y(n4879) );
XNOR2X1TS U6160 ( .A(n4880), .B(n4879), .Y(n4881) );
INVX2TS U6161 ( .A(n4882), .Y(n4883) );
AOI21X1TS U6162 ( .A0(n4885), .A1(n4884), .B0(n4883), .Y(n4890) );
INVX2TS U6163 ( .A(n4886), .Y(n4888) );
NAND2X1TS U6164 ( .A(n4888), .B(n4887), .Y(n4889) );
XOR2X1TS U6165 ( .A(n4890), .B(n4889), .Y(n4891) );
NAND2X1TS U6166 ( .A(n4949), .B(n5095), .Y(n603) );
NOR2BX1TS U6167 ( .AN(exp_oper_result[11]), .B(n5095), .Y(S_Oper_A_exp[11])
);
MX2X1TS U6168 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n4894), .Y(n406) );
MX2X1TS U6169 ( .A(n715), .B(exp_oper_result[10]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[10]) );
MX2X1TS U6170 ( .A(Exp_module_Data_S[9]), .B(n708), .S0(n4894), .Y(n407) );
MX2X1TS U6171 ( .A(Op_MX[61]), .B(n708), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[9]) );
MX2X1TS U6172 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n4894),
.Y(n408) );
MX2X1TS U6173 ( .A(n717), .B(exp_oper_result[8]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[8]) );
MX2X1TS U6174 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n4894),
.Y(n409) );
MX2X1TS U6175 ( .A(n718), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U6176 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n4894),
.Y(n410) );
MX2X1TS U6177 ( .A(n714), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U6178 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n4894),
.Y(n411) );
MX2X1TS U6179 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U6180 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n4894),
.Y(n412) );
MX2X1TS U6181 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U6182 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n4894),
.Y(n413) );
MX2X1TS U6183 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U6184 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n4894),
.Y(n414) );
MX2X1TS U6185 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U6186 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n4894),
.Y(n415) );
MX2X1TS U6187 ( .A(n709), .B(exp_oper_result[1]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[1]) );
MX2X1TS U6188 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n4894),
.Y(n416) );
MX2X1TS U6189 ( .A(n710), .B(exp_oper_result[0]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[0]) );
MX2X1TS U6190 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n4894), .Y(n405) );
XNOR2X1TS U6191 ( .A(DP_OP_31J39_122_605_n1), .B(n4901), .Y(n4896) );
MX2X1TS U6192 ( .A(Exp_module_Overflow_flag_A), .B(n4896), .S0(n4895), .Y(
n404) );
NAND4XLTS U6193 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n4897) );
NAND4BXLTS U6194 ( .AN(n4897), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n4898) );
NAND4BXLTS U6195 ( .AN(n4898), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n4899) );
NAND3BXLTS U6196 ( .AN(Exp_module_Data_S[10]), .B(n4951), .C(n4899), .Y(
n4900) );
OAI22X1TS U6197 ( .A0(Exp_module_Data_S[11]), .A1(n4900), .B0(n4951), .B1(
n5096), .Y(n351) );
OAI22X1TS U6198 ( .A0(zero_flag), .A1(n4901), .B0(P_Sgf[105]), .B1(n4905),
.Y(n4902) );
AOI2BB1XLTS U6199 ( .A0N(n4903), .A1N(n4902), .B0(n4904), .Y(n606) );
AOI21X1TS U6200 ( .A0(FS_Module_state_reg[2]), .A1(n4904), .B0(
DP_OP_31J39_122_605_n42), .Y(n4907) );
NAND3XLTS U6201 ( .A(n4907), .B(n4906), .C(n4905), .Y(n604) );
NAND4XLTS U6202 ( .A(n4912), .B(n4911), .C(n4910), .D(n4909), .Y(n4928) );
NAND4XLTS U6203 ( .A(n4916), .B(n4915), .C(n4914), .D(n4913), .Y(n4927) );
NAND4XLTS U6204 ( .A(n4920), .B(n4919), .C(n4918), .D(n4917), .Y(n4926) );
NOR4X1TS U6205 ( .A(Op_MY[58]), .B(n712), .C(n713), .D(n711), .Y(n4924) );
NAND4XLTS U6206 ( .A(n4924), .B(n4923), .C(n4922), .D(n4921), .Y(n4925) );
OR4X2TS U6207 ( .A(n4928), .B(n4927), .C(n4926), .D(n4925), .Y(n4952) );
NAND4XLTS U6208 ( .A(n4932), .B(n4931), .C(n4930), .D(n4929), .Y(n4948) );
NAND4XLTS U6209 ( .A(n4936), .B(n4935), .C(n4934), .D(n4933), .Y(n4947) );
NOR4X1TS U6210 ( .A(Op_MX[47]), .B(Op_MX[41]), .C(Op_MX[35]), .D(Op_MX[29]),
.Y(n4940) );
NOR4X1TS U6211 ( .A(Op_MX[44]), .B(Op_MX[32]), .C(Op_MX[23]), .D(Op_MX[17]),
.Y(n4939) );
NOR4X1TS U6212 ( .A(Op_MX[26]), .B(Op_MX[20]), .C(Op_MX[14]), .D(Op_MX[11]),
.Y(n4938) );
NAND4XLTS U6213 ( .A(n4940), .B(n4939), .C(n4938), .D(n4937), .Y(n4946) );
NOR4X1TS U6214 ( .A(Op_MX[61]), .B(n717), .C(n718), .D(n714), .Y(n4943) );
NOR4X1TS U6215 ( .A(Op_MX[50]), .B(Op_MX[38]), .C(Op_MX[2]), .D(n715), .Y(
n4942) );
NOR3XLTS U6216 ( .A(Op_MX[1]), .B(n709), .C(n710), .Y(n4941) );
NAND4XLTS U6217 ( .A(n4944), .B(n4943), .C(n4942), .D(n4941), .Y(n4945) );
OR4X2TS U6218 ( .A(n4948), .B(n4947), .C(n4946), .D(n4945), .Y(n4950) );
AOI32X1TS U6219 ( .A0(n4952), .A1(n4951), .A2(n4950), .B0(n5099), .B1(n4949),
.Y(n474) );
AOI32X1TS U6220 ( .A0(n4955), .A1(n4954), .A2(n4953), .B0(n5148), .B1(n2822),
.Y(n473) );
AOI2BB2XLTS U6221 ( .B0(n5182), .B1(n5051), .A0N(n5051), .A1N(
Sgf_normalized_result[0]), .Y(n472) );
AOI2BB2XLTS U6222 ( .B0(n5098), .B1(n5051), .A0N(n5051), .A1N(
Sgf_normalized_result[1]), .Y(n471) );
BUFX3TS U6223 ( .A(n703), .Y(n5062) );
AOI22X1TS U6224 ( .A0(n5062), .A1(Sgf_normalized_result[2]), .B0(n5097),
.B1(n5051), .Y(n470) );
AO22XLTS U6225 ( .A0(n5051), .A1(Add_result[3]), .B0(n703), .B1(n4956), .Y(
n469) );
INVX4TS U6226 ( .A(n703), .Y(n5053) );
BUFX3TS U6227 ( .A(n703), .Y(n5058) );
XNOR2X1TS U6228 ( .A(n4958), .B(Sgf_normalized_result[4]), .Y(n4957) );
AO22XLTS U6229 ( .A0(n5053), .A1(Add_result[4]), .B0(n5058), .B1(n4957), .Y(
n468) );
XNOR2X1TS U6230 ( .A(n4960), .B(Sgf_normalized_result[5]), .Y(n4959) );
AO22XLTS U6231 ( .A0(n5053), .A1(Add_result[5]), .B0(n4986), .B1(n4959), .Y(
n467) );
AO22XLTS U6232 ( .A0(n5053), .A1(Add_result[6]), .B0(n5058), .B1(n4961), .Y(
n466) );
AO22XLTS U6233 ( .A0(n5053), .A1(Add_result[7]), .B0(n4986), .B1(n4963), .Y(
n465) );
AO22XLTS U6234 ( .A0(n5053), .A1(Add_result[8]), .B0(n4986), .B1(n4965), .Y(
n464) );
AO22XLTS U6235 ( .A0(n5053), .A1(Add_result[9]), .B0(n4986), .B1(n4967), .Y(
n463) );
AO22XLTS U6236 ( .A0(n5053), .A1(Add_result[10]), .B0(n4986), .B1(n4969),
.Y(n462) );
AO22XLTS U6237 ( .A0(n5053), .A1(Add_result[11]), .B0(n4986), .B1(n4971),
.Y(n461) );
AO22XLTS U6238 ( .A0(n5053), .A1(Add_result[12]), .B0(n4986), .B1(n4973),
.Y(n460) );
AO22XLTS U6239 ( .A0(n5053), .A1(Add_result[13]), .B0(n4986), .B1(n4975),
.Y(n459) );
AO22XLTS U6240 ( .A0(n5053), .A1(Add_result[14]), .B0(n4986), .B1(n4977),
.Y(n458) );
AO22XLTS U6241 ( .A0(n5053), .A1(Add_result[15]), .B0(n4986), .B1(n4979),
.Y(n457) );
AO22XLTS U6242 ( .A0(n5053), .A1(Add_result[16]), .B0(n4986), .B1(n4981),
.Y(n456) );
AO22XLTS U6243 ( .A0(n5060), .A1(Add_result[17]), .B0(n4986), .B1(n4983),
.Y(n455) );
AO22XLTS U6244 ( .A0(n5060), .A1(Add_result[18]), .B0(n4986), .B1(n4985),
.Y(n454) );
AO22XLTS U6245 ( .A0(n5060), .A1(Add_result[19]), .B0(n5058), .B1(n4988),
.Y(n453) );
AO22XLTS U6246 ( .A0(n5051), .A1(Add_result[20]), .B0(n5058), .B1(n4990),
.Y(n452) );
AO22XLTS U6247 ( .A0(n5051), .A1(Add_result[21]), .B0(n5058), .B1(n4992),
.Y(n451) );
AO22XLTS U6248 ( .A0(n5053), .A1(Add_result[22]), .B0(n5058), .B1(n4994),
.Y(n450) );
AO22XLTS U6249 ( .A0(n5051), .A1(Add_result[23]), .B0(n5058), .B1(n4996),
.Y(n449) );
AO22XLTS U6250 ( .A0(n5053), .A1(Add_result[24]), .B0(n5058), .B1(n4998),
.Y(n448) );
AO22XLTS U6251 ( .A0(n5051), .A1(Add_result[25]), .B0(n5058), .B1(n5000),
.Y(n447) );
AO22XLTS U6252 ( .A0(n5053), .A1(Add_result[26]), .B0(n5058), .B1(n5002),
.Y(n446) );
AO22XLTS U6253 ( .A0(n5051), .A1(Add_result[27]), .B0(n5058), .B1(n5004),
.Y(n445) );
AO22XLTS U6254 ( .A0(n5053), .A1(Add_result[28]), .B0(n5058), .B1(n5006),
.Y(n444) );
AO22XLTS U6255 ( .A0(n5051), .A1(Add_result[29]), .B0(n5062), .B1(n5008),
.Y(n443) );
AO22XLTS U6256 ( .A0(n5060), .A1(Add_result[30]), .B0(n5062), .B1(n5010),
.Y(n442) );
AO22XLTS U6257 ( .A0(n5060), .A1(Add_result[31]), .B0(n5062), .B1(n5012),
.Y(n441) );
AO22XLTS U6258 ( .A0(n5060), .A1(Add_result[32]), .B0(n5062), .B1(n5014),
.Y(n440) );
AO22XLTS U6259 ( .A0(n5060), .A1(Add_result[33]), .B0(n5062), .B1(n5016),
.Y(n439) );
AO22XLTS U6260 ( .A0(n5060), .A1(Add_result[34]), .B0(n5062), .B1(n5018),
.Y(n438) );
AO22XLTS U6261 ( .A0(n5060), .A1(Add_result[35]), .B0(n5062), .B1(n5020),
.Y(n437) );
AO22XLTS U6262 ( .A0(n5060), .A1(Add_result[36]), .B0(n5062), .B1(n5022),
.Y(n436) );
AO22XLTS U6263 ( .A0(n5060), .A1(Add_result[37]), .B0(n5062), .B1(n5024),
.Y(n435) );
AO22XLTS U6264 ( .A0(n5060), .A1(Add_result[38]), .B0(n5062), .B1(n5026),
.Y(n434) );
AO22XLTS U6265 ( .A0(n5060), .A1(Add_result[39]), .B0(n5058), .B1(n5028),
.Y(n433) );
AO22XLTS U6266 ( .A0(Sgf_normalized_result[1]), .A1(n5064), .B0(
final_result_ieee[1]), .B1(n5063), .Y(n349) );
BUFX4TS U6267 ( .A(n5063), .Y(n5067) );
AO22XLTS U6268 ( .A0(Sgf_normalized_result[2]), .A1(n5064), .B0(
final_result_ieee[2]), .B1(n5067), .Y(n348) );
AO22XLTS U6269 ( .A0(Sgf_normalized_result[3]), .A1(n5064), .B0(
final_result_ieee[3]), .B1(n5067), .Y(n347) );
BUFX4TS U6270 ( .A(n5067), .Y(n5065) );
AO22XLTS U6271 ( .A0(Sgf_normalized_result[4]), .A1(n5064), .B0(
final_result_ieee[4]), .B1(n5065), .Y(n346) );
AO22XLTS U6272 ( .A0(Sgf_normalized_result[5]), .A1(n5064), .B0(
final_result_ieee[5]), .B1(n5067), .Y(n345) );
AO22XLTS U6273 ( .A0(Sgf_normalized_result[6]), .A1(n5064), .B0(
final_result_ieee[6]), .B1(n5067), .Y(n344) );
AO22XLTS U6274 ( .A0(Sgf_normalized_result[7]), .A1(n5064), .B0(
final_result_ieee[7]), .B1(n5067), .Y(n343) );
AO22XLTS U6275 ( .A0(Sgf_normalized_result[8]), .A1(n5064), .B0(
final_result_ieee[8]), .B1(n5065), .Y(n342) );
AO22XLTS U6276 ( .A0(Sgf_normalized_result[9]), .A1(n5064), .B0(
final_result_ieee[9]), .B1(n5065), .Y(n341) );
AO22XLTS U6277 ( .A0(Sgf_normalized_result[10]), .A1(n5064), .B0(
final_result_ieee[10]), .B1(n5065), .Y(n340) );
AO22XLTS U6278 ( .A0(Sgf_normalized_result[11]), .A1(n5064), .B0(
final_result_ieee[11]), .B1(n5065), .Y(n339) );
AO22XLTS U6279 ( .A0(Sgf_normalized_result[12]), .A1(n5064), .B0(
final_result_ieee[12]), .B1(n5065), .Y(n338) );
AO22XLTS U6280 ( .A0(Sgf_normalized_result[13]), .A1(n5066), .B0(
final_result_ieee[13]), .B1(n5065), .Y(n337) );
AO22XLTS U6281 ( .A0(Sgf_normalized_result[14]), .A1(n5066), .B0(
final_result_ieee[14]), .B1(n5065), .Y(n336) );
AO22XLTS U6282 ( .A0(Sgf_normalized_result[15]), .A1(n5066), .B0(
final_result_ieee[15]), .B1(n5065), .Y(n335) );
AO22XLTS U6283 ( .A0(Sgf_normalized_result[16]), .A1(n5066), .B0(
final_result_ieee[16]), .B1(n5065), .Y(n334) );
AO22XLTS U6284 ( .A0(Sgf_normalized_result[17]), .A1(n5066), .B0(
final_result_ieee[17]), .B1(n5065), .Y(n333) );
AO22XLTS U6285 ( .A0(Sgf_normalized_result[18]), .A1(n5066), .B0(
final_result_ieee[18]), .B1(n5065), .Y(n332) );
AO22XLTS U6286 ( .A0(Sgf_normalized_result[19]), .A1(n5066), .B0(
final_result_ieee[19]), .B1(n5065), .Y(n331) );
AO22XLTS U6287 ( .A0(Sgf_normalized_result[20]), .A1(n5066), .B0(
final_result_ieee[20]), .B1(n5065), .Y(n330) );
AO22XLTS U6288 ( .A0(Sgf_normalized_result[21]), .A1(n5066), .B0(
final_result_ieee[21]), .B1(n5065), .Y(n329) );
AO22XLTS U6289 ( .A0(Sgf_normalized_result[22]), .A1(n5066), .B0(
final_result_ieee[22]), .B1(n5065), .Y(n328) );
AO22XLTS U6290 ( .A0(Sgf_normalized_result[23]), .A1(n5066), .B0(
final_result_ieee[23]), .B1(n5065), .Y(n327) );
AO22XLTS U6291 ( .A0(Sgf_normalized_result[24]), .A1(n5066), .B0(
final_result_ieee[24]), .B1(n5065), .Y(n326) );
AO22XLTS U6292 ( .A0(Sgf_normalized_result[25]), .A1(n5066), .B0(
final_result_ieee[25]), .B1(n5065), .Y(n325) );
AO22XLTS U6293 ( .A0(Sgf_normalized_result[26]), .A1(n5068), .B0(
final_result_ieee[26]), .B1(n5065), .Y(n324) );
AO22XLTS U6294 ( .A0(Sgf_normalized_result[27]), .A1(n5066), .B0(
final_result_ieee[27]), .B1(n5067), .Y(n323) );
AO22XLTS U6295 ( .A0(Sgf_normalized_result[28]), .A1(n5068), .B0(
final_result_ieee[28]), .B1(n5067), .Y(n322) );
AO22XLTS U6296 ( .A0(Sgf_normalized_result[29]), .A1(n5066), .B0(
final_result_ieee[29]), .B1(n5067), .Y(n321) );
AO22XLTS U6297 ( .A0(Sgf_normalized_result[30]), .A1(n5068), .B0(
final_result_ieee[30]), .B1(n5067), .Y(n320) );
AO22XLTS U6298 ( .A0(Sgf_normalized_result[31]), .A1(n5066), .B0(
final_result_ieee[31]), .B1(n5067), .Y(n319) );
AO22XLTS U6299 ( .A0(Sgf_normalized_result[32]), .A1(n5068), .B0(
final_result_ieee[32]), .B1(n5067), .Y(n318) );
AO22XLTS U6300 ( .A0(Sgf_normalized_result[33]), .A1(n5066), .B0(
final_result_ieee[33]), .B1(n5067), .Y(n317) );
AO22XLTS U6301 ( .A0(Sgf_normalized_result[34]), .A1(n5068), .B0(
final_result_ieee[34]), .B1(n5067), .Y(n316) );
AO22XLTS U6302 ( .A0(Sgf_normalized_result[35]), .A1(n5066), .B0(
final_result_ieee[35]), .B1(n5067), .Y(n315) );
AO22XLTS U6303 ( .A0(Sgf_normalized_result[36]), .A1(n5068), .B0(
final_result_ieee[36]), .B1(n5067), .Y(n314) );
AO22XLTS U6304 ( .A0(Sgf_normalized_result[37]), .A1(n5066), .B0(
final_result_ieee[37]), .B1(n5067), .Y(n313) );
AO22XLTS U6305 ( .A0(Sgf_normalized_result[38]), .A1(n5068), .B0(
final_result_ieee[38]), .B1(n5067), .Y(n312) );
AO22XLTS U6306 ( .A0(Sgf_normalized_result[39]), .A1(n5068), .B0(
final_result_ieee[39]), .B1(n5067), .Y(n311) );
AO22XLTS U6307 ( .A0(Sgf_normalized_result[40]), .A1(n5068), .B0(
final_result_ieee[40]), .B1(n5067), .Y(n310) );
OA22X1TS U6308 ( .A0(n5069), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n885), .Y(n298) );
OA22X1TS U6309 ( .A0(n5069), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n885), .Y(n297) );
OA22X1TS U6310 ( .A0(n5069), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n885), .Y(n296) );
OA22X1TS U6311 ( .A0(n5069), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n885), .Y(n295) );
OA22X1TS U6312 ( .A0(n5069), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n885), .Y(n294) );
OA22X1TS U6313 ( .A0(n5069), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n885), .Y(n293) );
OA22X1TS U6314 ( .A0(n5069), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n885), .Y(n292) );
OA22X1TS U6315 ( .A0(n5069), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n885), .Y(n291) );
OA22X1TS U6316 ( .A0(n5069), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n885), .Y(n290) );
OA22X1TS U6317 ( .A0(n5069), .A1(final_result_ieee[61]), .B0(n708), .B1(n885), .Y(n289) );
OA22X1TS U6318 ( .A0(n5069), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n885), .Y(n288) );
CMPR42X1TS U6319 ( .A(Sgf_operation_mult_x_1_n2342), .B(
Sgf_operation_mult_x_1_n2321), .C(Sgf_operation_mult_x_1_n2339), .D(
Sgf_operation_mult_x_1_n2318), .ICI(Sgf_operation_mult_x_1_n2335), .S(
Sgf_operation_mult_x_1_n2315), .ICO(Sgf_operation_mult_x_1_n2313),
.CO(Sgf_operation_mult_x_1_n2314) );
CMPR42X1TS U6320 ( .A(Sgf_operation_mult_x_1_n2562), .B(
Sgf_operation_mult_x_1_n2572), .C(Sgf_operation_mult_x_1_n2569), .D(
Sgf_operation_mult_x_1_n2556), .ICI(Sgf_operation_mult_x_1_n2565), .S(
Sgf_operation_mult_x_1_n2553), .ICO(Sgf_operation_mult_x_1_n2551),
.CO(Sgf_operation_mult_x_1_n2552) );
CMPR42X1TS U6321 ( .A(Sgf_operation_mult_x_1_n3706), .B(
Sgf_operation_mult_x_1_n1635), .C(Sgf_operation_mult_x_1_n1651), .D(
Sgf_operation_mult_x_1_n3549), .ICI(Sgf_operation_mult_x_1_n1645), .S(
Sgf_operation_mult_x_1_n1630), .ICO(Sgf_operation_mult_x_1_n1628),
.CO(Sgf_operation_mult_x_1_n1629) );
CMPR42X1TS U6322 ( .A(Sgf_operation_mult_x_1_n4278), .B(
Sgf_operation_mult_x_1_n4066), .C(Sgf_operation_mult_x_1_n2561), .D(
Sgf_operation_mult_x_1_n2554), .ICI(Sgf_operation_mult_x_1_n2558), .S(
Sgf_operation_mult_x_1_n2540), .ICO(Sgf_operation_mult_x_1_n2538),
.CO(Sgf_operation_mult_x_1_n2539) );
CMPR42X1TS U6323 ( .A(Sgf_operation_mult_x_1_n4321), .B(
Sgf_operation_mult_x_1_n2387), .C(Sgf_operation_mult_x_1_n4056), .D(
Sgf_operation_mult_x_1_n3950), .ICI(Sgf_operation_mult_x_1_n2381), .S(
Sgf_operation_mult_x_1_n2366), .ICO(Sgf_operation_mult_x_1_n2364),
.CO(Sgf_operation_mult_x_1_n2365) );
CMPR42X1TS U6324 ( .A(Sgf_operation_mult_x_1_n4332), .B(
Sgf_operation_mult_x_1_n4226), .C(Sgf_operation_mult_x_1_n2571), .D(
Sgf_operation_mult_x_1_n2568), .ICI(Sgf_operation_mult_x_1_n2559), .S(
Sgf_operation_mult_x_1_n2556), .ICO(Sgf_operation_mult_x_1_n2554),
.CO(Sgf_operation_mult_x_1_n2555) );
CMPR42X1TS U6325 ( .A(Sgf_operation_mult_x_1_n2326), .B(
Sgf_operation_mult_x_1_n2319), .C(Sgf_operation_mult_x_1_n2305), .D(
Sgf_operation_mult_x_1_n2323), .ICI(Sgf_operation_mult_x_1_n2320), .S(
Sgf_operation_mult_x_1_n2296), .ICO(Sgf_operation_mult_x_1_n2294),
.CO(Sgf_operation_mult_x_1_n2295) );
CMPR42X1TS U6326 ( .A(Sgf_operation_mult_x_1_n2407), .B(
Sgf_operation_mult_x_1_n4004), .C(Sgf_operation_mult_x_1_n4110), .D(
Sgf_operation_mult_x_1_n2404), .ICI(Sgf_operation_mult_x_1_n2401), .S(
Sgf_operation_mult_x_1_n2383), .ICO(Sgf_operation_mult_x_1_n2381),
.CO(Sgf_operation_mult_x_1_n2382) );
CMPR42X1TS U6327 ( .A(Sgf_operation_mult_x_1_n3657), .B(
Sgf_operation_mult_x_1_n3973), .C(Sgf_operation_mult_x_1_n3604), .D(
Sgf_operation_mult_x_1_n3499), .ICI(Sgf_operation_mult_x_1_n1708), .S(
Sgf_operation_mult_x_1_n1688), .ICO(Sgf_operation_mult_x_1_n1686),
.CO(Sgf_operation_mult_x_1_n1687) );
CMPR42X1TS U6328 ( .A(Sgf_operation_mult_x_1_n1622), .B(
Sgf_operation_mult_x_1_n1611), .C(Sgf_operation_mult_x_1_n1623), .D(
Sgf_operation_mult_x_1_n1608), .ICI(Sgf_operation_mult_x_1_n1619), .S(
Sgf_operation_mult_x_1_n1605), .ICO(Sgf_operation_mult_x_1_n1603),
.CO(Sgf_operation_mult_x_1_n1604) );
CMPR42X1TS U6329 ( .A(Sgf_operation_mult_x_1_n1644), .B(
Sgf_operation_mult_x_1_n1658), .C(Sgf_operation_mult_x_1_n1659), .D(
Sgf_operation_mult_x_1_n1641), .ICI(Sgf_operation_mult_x_1_n1655), .S(
Sgf_operation_mult_x_1_n1638), .ICO(Sgf_operation_mult_x_1_n1636),
.CO(Sgf_operation_mult_x_1_n1637) );
CMPR42X1TS U6330 ( .A(Sgf_operation_mult_x_1_n2316), .B(
Sgf_operation_mult_x_1_n2299), .C(Sgf_operation_mult_x_1_n2317), .D(
Sgf_operation_mult_x_1_n2296), .ICI(Sgf_operation_mult_x_1_n2313), .S(
Sgf_operation_mult_x_1_n2293), .ICO(Sgf_operation_mult_x_1_n2291),
.CO(Sgf_operation_mult_x_1_n2292) );
CMPR42X1TS U6331 ( .A(Sgf_operation_mult_x_1_n1677), .B(
Sgf_operation_mult_x_1_n1663), .C(Sgf_operation_mult_x_1_n1678), .D(
Sgf_operation_mult_x_1_n1660), .ICI(Sgf_operation_mult_x_1_n1674), .S(
Sgf_operation_mult_x_1_n1657), .ICO(Sgf_operation_mult_x_1_n1655),
.CO(Sgf_operation_mult_x_1_n1656) );
CMPR42X1TS U6332 ( .A(Sgf_operation_mult_x_1_n1758), .B(
Sgf_operation_mult_x_1_n1739), .C(Sgf_operation_mult_x_1_n1755), .D(
Sgf_operation_mult_x_1_n1736), .ICI(Sgf_operation_mult_x_1_n1751), .S(
Sgf_operation_mult_x_1_n1733), .ICO(Sgf_operation_mult_x_1_n1731),
.CO(Sgf_operation_mult_x_1_n1732) );
CMPR42X1TS U6333 ( .A(Sgf_operation_mult_x_1_n1801), .B(
Sgf_operation_mult_x_1_n1781), .C(Sgf_operation_mult_x_1_n1798), .D(
Sgf_operation_mult_x_1_n1778), .ICI(Sgf_operation_mult_x_1_n1794), .S(
Sgf_operation_mult_x_1_n1775), .ICO(Sgf_operation_mult_x_1_n1773),
.CO(Sgf_operation_mult_x_1_n1774) );
CMPR42X1TS U6334 ( .A(Sgf_operation_mult_x_1_n1936), .B(
Sgf_operation_mult_x_1_n1916), .C(Sgf_operation_mult_x_1_n1937), .D(
Sgf_operation_mult_x_1_n1913), .ICI(Sgf_operation_mult_x_1_n1933), .S(
Sgf_operation_mult_x_1_n1910), .ICO(Sgf_operation_mult_x_1_n1908),
.CO(Sgf_operation_mult_x_1_n1909) );
CMPR42X1TS U6335 ( .A(Sgf_operation_mult_x_1_n1984), .B(
Sgf_operation_mult_x_1_n1965), .C(Sgf_operation_mult_x_1_n1985), .D(
Sgf_operation_mult_x_1_n1962), .ICI(Sgf_operation_mult_x_1_n1981), .S(
Sgf_operation_mult_x_1_n1959), .ICO(Sgf_operation_mult_x_1_n1957),
.CO(Sgf_operation_mult_x_1_n1958) );
CMPR42X1TS U6336 ( .A(Sgf_operation_mult_x_1_n2639), .B(
Sgf_operation_mult_x_1_n2627), .C(Sgf_operation_mult_x_1_n2636), .D(
Sgf_operation_mult_x_1_n2624), .ICI(Sgf_operation_mult_x_1_n2632), .S(
Sgf_operation_mult_x_1_n2621), .ICO(Sgf_operation_mult_x_1_n2619),
.CO(Sgf_operation_mult_x_1_n2620) );
CMPR42X1TS U6337 ( .A(Sgf_operation_mult_x_1_n4236), .B(
Sgf_operation_mult_x_1_n2688), .C(Sgf_operation_mult_x_1_n2689), .D(
Sgf_operation_mult_x_1_n2680), .ICI(Sgf_operation_mult_x_1_n2685), .S(
Sgf_operation_mult_x_1_n2677), .ICO(Sgf_operation_mult_x_1_n2675),
.CO(Sgf_operation_mult_x_1_n2676) );
CMPR42X1TS U6338 ( .A(Sgf_operation_mult_x_1_n1579), .B(
Sgf_operation_mult_x_1_n1564), .C(Sgf_operation_mult_x_1_n1576), .D(
Sgf_operation_mult_x_1_n1561), .ICI(Sgf_operation_mult_x_1_n1572), .S(
Sgf_operation_mult_x_1_n1558), .ICO(Sgf_operation_mult_x_1_n1556),
.CO(Sgf_operation_mult_x_1_n1557) );
CMPR42X1TS U6339 ( .A(Sgf_operation_mult_x_1_n1964), .B(
Sgf_operation_mult_x_1_n1941), .C(Sgf_operation_mult_x_1_n1961), .D(
Sgf_operation_mult_x_1_n1938), .ICI(Sgf_operation_mult_x_1_n1957), .S(
Sgf_operation_mult_x_1_n1935), .ICO(Sgf_operation_mult_x_1_n1933),
.CO(Sgf_operation_mult_x_1_n1934) );
CMPR42X1TS U6340 ( .A(Sgf_operation_mult_x_1_n2157), .B(
Sgf_operation_mult_x_1_n2133), .C(Sgf_operation_mult_x_1_n2154), .D(
Sgf_operation_mult_x_1_n2130), .ICI(Sgf_operation_mult_x_1_n2150), .S(
Sgf_operation_mult_x_1_n2127), .ICO(Sgf_operation_mult_x_1_n2125),
.CO(Sgf_operation_mult_x_1_n2126) );
CMPR42X1TS U6341 ( .A(Sgf_operation_mult_x_1_n2203), .B(
Sgf_operation_mult_x_1_n2183), .C(Sgf_operation_mult_x_1_n2204), .D(
Sgf_operation_mult_x_1_n2180), .ICI(Sgf_operation_mult_x_1_n2200), .S(
Sgf_operation_mult_x_1_n2177), .ICO(Sgf_operation_mult_x_1_n2175),
.CO(Sgf_operation_mult_x_1_n2176) );
CMPR42X1TS U6342 ( .A(Sgf_operation_mult_x_1_n2421), .B(
Sgf_operation_mult_x_1_n2403), .C(Sgf_operation_mult_x_1_n2418), .D(
Sgf_operation_mult_x_1_n2400), .ICI(Sgf_operation_mult_x_1_n2414), .S(
Sgf_operation_mult_x_1_n2397), .ICO(Sgf_operation_mult_x_1_n2395),
.CO(Sgf_operation_mult_x_1_n2396) );
CMPR42X1TS U6343 ( .A(Sgf_operation_mult_x_1_n2455), .B(
Sgf_operation_mult_x_1_n2441), .C(Sgf_operation_mult_x_1_n2456), .D(
Sgf_operation_mult_x_1_n2438), .ICI(Sgf_operation_mult_x_1_n2452), .S(
Sgf_operation_mult_x_1_n2435), .ICO(Sgf_operation_mult_x_1_n2433),
.CO(Sgf_operation_mult_x_1_n2434) );
CMPR42X1TS U6344 ( .A(Sgf_operation_mult_x_1_n1682), .B(
Sgf_operation_mult_x_1_n1699), .C(Sgf_operation_mult_x_1_n1696), .D(
Sgf_operation_mult_x_1_n1679), .ICI(Sgf_operation_mult_x_1_n1692), .S(
Sgf_operation_mult_x_1_n1676), .ICO(Sgf_operation_mult_x_1_n1674),
.CO(Sgf_operation_mult_x_1_n1675) );
CMPR42X1TS U6345 ( .A(Sgf_operation_mult_x_1_n2178), .B(
Sgf_operation_mult_x_1_n2158), .C(Sgf_operation_mult_x_1_n2179), .D(
Sgf_operation_mult_x_1_n2155), .ICI(Sgf_operation_mult_x_1_n2175), .S(
Sgf_operation_mult_x_1_n2152), .ICO(Sgf_operation_mult_x_1_n2150),
.CO(Sgf_operation_mult_x_1_n2151) );
CMPR42X1TS U6346 ( .A(Sgf_operation_mult_x_1_n2678), .B(
Sgf_operation_mult_x_1_n2672), .C(Sgf_operation_mult_x_1_n2679), .D(
Sgf_operation_mult_x_1_n2670), .ICI(Sgf_operation_mult_x_1_n2675), .S(
Sgf_operation_mult_x_1_n2667), .ICO(Sgf_operation_mult_x_1_n2665),
.CO(Sgf_operation_mult_x_1_n2666) );
CMPR42X1TS U6347 ( .A(Sgf_operation_mult_x_1_n1625), .B(
Sgf_operation_mult_x_1_n1617), .C(Sgf_operation_mult_x_1_n1632), .D(
Sgf_operation_mult_x_1_n1614), .ICI(Sgf_operation_mult_x_1_n1626), .S(
Sgf_operation_mult_x_1_n1608), .ICO(Sgf_operation_mult_x_1_n1606),
.CO(Sgf_operation_mult_x_1_n1607) );
CMPR42X1TS U6348 ( .A(Sgf_operation_mult_x_1_n1946), .B(
Sgf_operation_mult_x_1_n1939), .C(Sgf_operation_mult_x_1_n1943), .D(
Sgf_operation_mult_x_1_n1919), .ICI(Sgf_operation_mult_x_1_n1940), .S(
Sgf_operation_mult_x_1_n1913), .ICO(Sgf_operation_mult_x_1_n1911),
.CO(Sgf_operation_mult_x_1_n1912) );
CMPR42X1TS U6349 ( .A(Sgf_operation_mult_x_1_n3809), .B(
Sgf_operation_mult_x_1_n1612), .C(Sgf_operation_mult_x_1_n3862), .D(
Sgf_operation_mult_x_1_n3757), .ICI(Sgf_operation_mult_x_1_n3652), .S(
Sgf_operation_mult_x_1_n1594), .ICO(Sgf_operation_mult_x_1_n1592),
.CO(Sgf_operation_mult_x_1_n1593) );
CMPR42X1TS U6350 ( .A(Sgf_operation_mult_x_1_n4057), .B(
Sgf_operation_mult_x_1_n4163), .C(Sgf_operation_mult_x_1_n3951), .D(
Sgf_operation_mult_x_1_n2410), .ICI(Sgf_operation_mult_x_1_n2392), .S(
Sgf_operation_mult_x_1_n2389), .ICO(Sgf_operation_mult_x_1_n2387),
.CO(Sgf_operation_mult_x_1_n2388) );
CMPR42X1TS U6351 ( .A(Sgf_operation_mult_x_1_n4034), .B(
Sgf_operation_mult_x_1_n1858), .C(Sgf_operation_mult_x_1_n1869), .D(
Sgf_operation_mult_x_1_n1855), .ICI(Sgf_operation_mult_x_1_n1873), .S(
Sgf_operation_mult_x_1_n1846), .ICO(Sgf_operation_mult_x_1_n1844),
.CO(Sgf_operation_mult_x_1_n1845) );
CMPR42X1TS U6352 ( .A(Sgf_operation_mult_x_1_n1966), .B(
Sgf_operation_mult_x_1_n1953), .C(Sgf_operation_mult_x_1_n1976), .D(
Sgf_operation_mult_x_1_n1973), .ICI(Sgf_operation_mult_x_1_n1967), .S(
Sgf_operation_mult_x_1_n1941), .ICO(Sgf_operation_mult_x_1_n1939),
.CO(Sgf_operation_mult_x_1_n1940) );
CMPR42X1TS U6353 ( .A(Sgf_operation_mult_x_1_n4196), .B(
Sgf_operation_mult_x_1_n4090), .C(Sgf_operation_mult_x_1_n3878), .D(
Sgf_operation_mult_x_1_n1948), .ICI(Sgf_operation_mult_x_1_n1925), .S(
Sgf_operation_mult_x_1_n1919), .ICO(Sgf_operation_mult_x_1_n1917),
.CO(Sgf_operation_mult_x_1_n1918) );
CMPR42X1TS U6354 ( .A(Sgf_operation_mult_x_1_n1770), .B(
Sgf_operation_mult_x_1_n1791), .C(Sgf_operation_mult_x_1_n3503), .D(
Sgf_operation_mult_x_1_n4030), .ICI(Sgf_operation_mult_x_1_n1789), .S(
Sgf_operation_mult_x_1_n1762), .ICO(Sgf_operation_mult_x_1_n1760),
.CO(Sgf_operation_mult_x_1_n1761) );
CMPR42X1TS U6355 ( .A(Sgf_operation_mult_x_1_n4333), .B(
Sgf_operation_mult_x_1_n4227), .C(Sgf_operation_mult_x_1_n4068), .D(
Sgf_operation_mult_x_1_n2585), .ICI(Sgf_operation_mult_x_1_n4280), .S(
Sgf_operation_mult_x_1_n2573), .ICO(Sgf_operation_mult_x_1_n2571),
.CO(Sgf_operation_mult_x_1_n2572) );
CMPR42X1TS U6356 ( .A(Sgf_operation_mult_x_1_n3887), .B(
Sgf_operation_mult_x_1_n3677), .C(Sgf_operation_mult_x_1_n3993), .D(
Sgf_operation_mult_x_1_n2171), .ICI(Sgf_operation_mult_x_1_n2165), .S(
Sgf_operation_mult_x_1_n2145), .ICO(Sgf_operation_mult_x_1_n2143),
.CO(Sgf_operation_mult_x_1_n2144) );
CMPR42X1TS U6357 ( .A(Sgf_operation_mult_x_1_n4363), .B(
Sgf_operation_mult_x_1_n4045), .C(Sgf_operation_mult_x_1_n3676), .D(
Sgf_operation_mult_x_1_n3992), .ICI(Sgf_operation_mult_x_1_n4098), .S(
Sgf_operation_mult_x_1_n2118), .ICO(Sgf_operation_mult_x_1_n2116),
.CO(Sgf_operation_mult_x_1_n2117) );
CMPR42X1TS U6358 ( .A(Sgf_operation_mult_x_1_n4387), .B(
Sgf_operation_mult_x_1_n4175), .C(Sgf_operation_mult_x_1_n4281), .D(
Sgf_operation_mult_x_1_n2602), .ICI(Sgf_operation_mult_x_1_n2590), .S(
Sgf_operation_mult_x_1_n2587), .ICO(Sgf_operation_mult_x_1_n2585),
.CO(Sgf_operation_mult_x_1_n2586) );
CMPR42X1TS U6359 ( .A(Sgf_operation_mult_x_1_n4176), .B(
Sgf_operation_mult_x_1_n4070), .C(Sgf_operation_mult_x_1_n4123), .D(
Sgf_operation_mult_x_1_n2615), .ICI(Sgf_operation_mult_x_1_n2609), .S(
Sgf_operation_mult_x_1_n2601), .ICO(Sgf_operation_mult_x_1_n2599),
.CO(Sgf_operation_mult_x_1_n2600) );
CMPR42X1TS U6360 ( .A(Sgf_operation_mult_x_1_n4331), .B(
Sgf_operation_mult_x_1_n4119), .C(Sgf_operation_mult_x_1_n2560), .D(
Sgf_operation_mult_x_1_n2557), .ICI(Sgf_operation_mult_x_1_n4384), .S(
Sgf_operation_mult_x_1_n2543), .ICO(Sgf_operation_mult_x_1_n2541),
.CO(Sgf_operation_mult_x_1_n2542) );
CMPR42X1TS U6361 ( .A(Sgf_operation_mult_x_1_n3766), .B(
Sgf_operation_mult_x_1_n3977), .C(Sgf_operation_mult_x_1_n3608), .D(
Sgf_operation_mult_x_1_n3713), .ICI(Sgf_operation_mult_x_1_n1785), .S(
Sgf_operation_mult_x_1_n1765), .ICO(Sgf_operation_mult_x_1_n1763),
.CO(Sgf_operation_mult_x_1_n1764) );
CMPR42X1TS U6362 ( .A(Sgf_operation_mult_x_1_n4005), .B(
Sgf_operation_mult_x_1_n3899), .C(Sgf_operation_mult_x_1_n3846), .D(
Sgf_operation_mult_x_1_n2429), .ICI(Sgf_operation_mult_x_1_n2423), .S(
Sgf_operation_mult_x_1_n2409), .ICO(Sgf_operation_mult_x_1_n2407),
.CO(Sgf_operation_mult_x_1_n2408) );
CMPR42X1TS U6363 ( .A(Sgf_operation_mult_x_1_n3833), .B(
Sgf_operation_mult_x_1_n3939), .C(Sgf_operation_mult_x_1_n3728), .D(
Sgf_operation_mult_x_1_n2146), .ICI(Sgf_operation_mult_x_1_n2124), .S(
Sgf_operation_mult_x_1_n2121), .ICO(Sgf_operation_mult_x_1_n2119),
.CO(Sgf_operation_mult_x_1_n2120) );
CMPR42X1TS U6364 ( .A(Sgf_operation_mult_x_1_n2642), .B(
Sgf_operation_mult_x_1_n4073), .C(Sgf_operation_mult_x_1_n4391), .D(
Sgf_operation_mult_x_1_n4285), .ICI(Sgf_operation_mult_x_1_n2649), .S(
Sgf_operation_mult_x_1_n2640), .ICO(Sgf_operation_mult_x_1_n2638),
.CO(Sgf_operation_mult_x_1_n2639) );
CMPR42X1TS U6365 ( .A(Sgf_operation_mult_x_1_n3865), .B(
Sgf_operation_mult_x_1_n3760), .C(Sgf_operation_mult_x_1_n3602), .D(
Sgf_operation_mult_x_1_n1670), .ICI(Sgf_operation_mult_x_1_n3707), .S(
Sgf_operation_mult_x_1_n1647), .ICO(Sgf_operation_mult_x_1_n1645),
.CO(Sgf_operation_mult_x_1_n1646) );
CMPR42X1TS U6366 ( .A(Sgf_operation_mult_x_1_n2564), .B(
Sgf_operation_mult_x_1_n3961), .C(Sgf_operation_mult_x_1_n4173), .D(
Sgf_operation_mult_x_1_n4279), .ICI(Sgf_operation_mult_x_1_n2574), .S(
Sgf_operation_mult_x_1_n2562), .ICO(Sgf_operation_mult_x_1_n2560),
.CO(Sgf_operation_mult_x_1_n2561) );
CMPR42X1TS U6367 ( .A(Sgf_operation_mult_x_1_n1705), .B(
Sgf_operation_mult_x_1_n1702), .C(Sgf_operation_mult_x_1_n1698), .D(
Sgf_operation_mult_x_1_n1685), .ICI(Sgf_operation_mult_x_1_n1695), .S(
Sgf_operation_mult_x_1_n1679), .ICO(Sgf_operation_mult_x_1_n1677),
.CO(Sgf_operation_mult_x_1_n1678) );
CMPR42X1TS U6368 ( .A(Sgf_operation_mult_x_1_n4330), .B(
Sgf_operation_mult_x_1_n4224), .C(Sgf_operation_mult_x_1_n2545), .D(
Sgf_operation_mult_x_1_n2530), .ICI(Sgf_operation_mult_x_1_n2538), .S(
Sgf_operation_mult_x_1_n2524), .ICO(Sgf_operation_mult_x_1_n2522),
.CO(Sgf_operation_mult_x_1_n2523) );
CMPR42X1TS U6369 ( .A(n5152), .B(Sgf_operation_mult_x_1_n3462), .C(
Sgf_operation_mult_x_1_n3671), .D(Sgf_operation_mult_x_1_n3776), .ICI(
Sgf_operation_mult_x_1_n3618), .S(Sgf_operation_mult_x_1_n2004), .ICO(
Sgf_operation_mult_x_1_n2002), .CO(Sgf_operation_mult_x_1_n2003) );
CMPR42X1TS U6370 ( .A(Sgf_operation_mult_x_1_n4151), .B(
Sgf_operation_mult_x_1_n4257), .C(Sgf_operation_mult_x_1_n3781), .D(
Sgf_operation_mult_x_1_n3886), .ICI(Sgf_operation_mult_x_1_n4204), .S(
Sgf_operation_mult_x_1_n2115), .ICO(Sgf_operation_mult_x_1_n2113),
.CO(Sgf_operation_mult_x_1_n2114) );
CMPR42X1TS U6371 ( .A(Sgf_operation_mult_x_1_n4027), .B(
Sgf_operation_mult_x_1_n3921), .C(Sgf_operation_mult_x_1_n3658), .D(
Sgf_operation_mult_x_1_n1724), .ICI(Sgf_operation_mult_x_1_n1728), .S(
Sgf_operation_mult_x_1_n1703), .ICO(Sgf_operation_mult_x_1_n1701),
.CO(Sgf_operation_mult_x_1_n1702) );
CMPR42X1TS U6372 ( .A(Sgf_operation_mult_x_1_n1652), .B(
Sgf_operation_mult_x_1_n1667), .C(Sgf_operation_mult_x_1_n3918), .D(
Sgf_operation_mult_x_1_n3812), .ICI(Sgf_operation_mult_x_1_n1668), .S(
Sgf_operation_mult_x_1_n1644), .ICO(Sgf_operation_mult_x_1_n1642),
.CO(Sgf_operation_mult_x_1_n1643) );
CMPR42X1TS U6373 ( .A(Sgf_operation_mult_x_1_n3991), .B(
Sgf_operation_mult_x_1_n4097), .C(Sgf_operation_mult_x_1_n3938), .D(
Sgf_operation_mult_x_1_n3832), .ICI(Sgf_operation_mult_x_1_n2116), .S(
Sgf_operation_mult_x_1_n2094), .ICO(Sgf_operation_mult_x_1_n2092),
.CO(Sgf_operation_mult_x_1_n2093) );
CMPR42X1TS U6374 ( .A(Sgf_operation_mult_x_1_n4038), .B(
Sgf_operation_mult_x_1_n4144), .C(Sgf_operation_mult_x_1_n3932), .D(
Sgf_operation_mult_x_1_n1956), .ICI(Sgf_operation_mult_x_1_n1970), .S(
Sgf_operation_mult_x_1_n1944), .ICO(Sgf_operation_mult_x_1_n1942),
.CO(Sgf_operation_mult_x_1_n1943) );
CMPR42X1TS U6375 ( .A(Sgf_operation_mult_x_1_n4117), .B(
Sgf_operation_mult_x_1_n4329), .C(Sgf_operation_mult_x_1_n2528), .D(
Sgf_operation_mult_x_1_n2516), .ICI(Sgf_operation_mult_x_1_n4276), .S(
Sgf_operation_mult_x_1_n2511), .ICO(Sgf_operation_mult_x_1_n2509),
.CO(Sgf_operation_mult_x_1_n2510) );
CMPR42X1TS U6376 ( .A(Sgf_operation_mult_x_1_n4096), .B(
Sgf_operation_mult_x_1_n2096), .C(Sgf_operation_mult_x_1_n2086), .D(
Sgf_operation_mult_x_1_n2093), .ICI(Sgf_operation_mult_x_1_n2070), .S(
Sgf_operation_mult_x_1_n2061), .ICO(Sgf_operation_mult_x_1_n2059),
.CO(Sgf_operation_mult_x_1_n2060) );
CMPR42X1TS U6377 ( .A(Sgf_operation_mult_x_1_n4198), .B(
Sgf_operation_mult_x_1_n3986), .C(Sgf_operation_mult_x_1_n4092), .D(
Sgf_operation_mult_x_1_n2000), .ICI(Sgf_operation_mult_x_1_n1974), .S(
Sgf_operation_mult_x_1_n1968), .ICO(Sgf_operation_mult_x_1_n1966),
.CO(Sgf_operation_mult_x_1_n1967) );
CMPR42X1TS U6378 ( .A(Sgf_operation_mult_x_1_n3999), .B(
Sgf_operation_mult_x_1_n4105), .C(Sgf_operation_mult_x_1_n3735), .D(
Sgf_operation_mult_x_1_n2309), .ICI(Sgf_operation_mult_x_1_n2303), .S(
Sgf_operation_mult_x_1_n2286), .ICO(Sgf_operation_mult_x_1_n2284),
.CO(Sgf_operation_mult_x_1_n2285) );
CMPR42X1TS U6379 ( .A(Sgf_operation_mult_x_1_n1571), .B(
Sgf_operation_mult_x_1_n3597), .C(Sgf_operation_mult_x_1_n3807), .D(
Sgf_operation_mult_x_1_n3702), .ICI(Sgf_operation_mult_x_1_n1581), .S(
Sgf_operation_mult_x_1_n1567), .ICO(Sgf_operation_mult_x_1_n1565),
.CO(Sgf_operation_mult_x_1_n1566) );
CMPR42X1TS U6380 ( .A(Sgf_operation_mult_x_1_n1792), .B(
Sgf_operation_mult_x_1_n1806), .C(Sgf_operation_mult_x_1_n3872), .D(
Sgf_operation_mult_x_1_n3978), .ICI(Sgf_operation_mult_x_1_n1803), .S(
Sgf_operation_mult_x_1_n1784), .ICO(Sgf_operation_mult_x_1_n1782),
.CO(Sgf_operation_mult_x_1_n1783) );
CMPR42X1TS U6381 ( .A(Sgf_operation_mult_x_1_n4089), .B(
Sgf_operation_mult_x_1_n3983), .C(Sgf_operation_mult_x_1_n3614), .D(
Sgf_operation_mult_x_1_n3719), .ICI(Sgf_operation_mult_x_1_n4142), .S(
Sgf_operation_mult_x_1_n1897), .ICO(Sgf_operation_mult_x_1_n1895),
.CO(Sgf_operation_mult_x_1_n1896) );
CMPR42X1TS U6382 ( .A(Sgf_operation_mult_x_1_n4252), .B(
Sgf_operation_mult_x_1_n4146), .C(Sgf_operation_mult_x_1_n2020), .D(
Sgf_operation_mult_x_1_n2004), .ICI(Sgf_operation_mult_x_1_n1998), .S(
Sgf_operation_mult_x_1_n1992), .ICO(Sgf_operation_mult_x_1_n1990),
.CO(Sgf_operation_mult_x_1_n1991) );
CMPR42X1TS U6383 ( .A(Sgf_operation_mult_x_1_n4269), .B(
Sgf_operation_mult_x_1_n4375), .C(Sgf_operation_mult_x_1_n3898), .D(
Sgf_operation_mult_x_1_n4216), .ICI(Sgf_operation_mult_x_1_n4322), .S(
Sgf_operation_mult_x_1_n2386), .ICO(Sgf_operation_mult_x_1_n2384),
.CO(Sgf_operation_mult_x_1_n2385) );
CMPR42X1TS U6384 ( .A(Sgf_operation_mult_x_1_n3808), .B(
Sgf_operation_mult_x_1_n1592), .C(Sgf_operation_mult_x_1_n1585), .D(
Sgf_operation_mult_x_1_n1596), .ICI(Sgf_operation_mult_x_1_n1593), .S(
Sgf_operation_mult_x_1_n1577), .ICO(Sgf_operation_mult_x_1_n1575),
.CO(Sgf_operation_mult_x_1_n1576) );
CMPR42X1TS U6385 ( .A(Sgf_operation_mult_x_1_n1786), .B(
Sgf_operation_mult_x_1_n1779), .C(Sgf_operation_mult_x_1_n1762), .D(
Sgf_operation_mult_x_1_n1783), .ICI(Sgf_operation_mult_x_1_n1780), .S(
Sgf_operation_mult_x_1_n1756), .ICO(Sgf_operation_mult_x_1_n1754),
.CO(Sgf_operation_mult_x_1_n1755) );
CMPR42X1TS U6386 ( .A(Sgf_operation_mult_x_1_n1808), .B(
Sgf_operation_mult_x_1_n1821), .C(Sgf_operation_mult_x_1_n1825), .D(
Sgf_operation_mult_x_1_n1805), .ICI(Sgf_operation_mult_x_1_n1802), .S(
Sgf_operation_mult_x_1_n1799), .ICO(Sgf_operation_mult_x_1_n1797),
.CO(Sgf_operation_mult_x_1_n1798) );
CMPR42X1TS U6387 ( .A(Sgf_operation_mult_x_1_n1876), .B(
Sgf_operation_mult_x_1_n1866), .C(Sgf_operation_mult_x_1_n1870), .D(
Sgf_operation_mult_x_1_n1849), .ICI(Sgf_operation_mult_x_1_n1863), .S(
Sgf_operation_mult_x_1_n1843), .ICO(Sgf_operation_mult_x_1_n1841),
.CO(Sgf_operation_mult_x_1_n1842) );
CMPR42X1TS U6388 ( .A(Sgf_operation_mult_x_1_n2259), .B(
Sgf_operation_mult_x_1_n2256), .C(Sgf_operation_mult_x_1_n2252), .D(
Sgf_operation_mult_x_1_n2234), .ICI(Sgf_operation_mult_x_1_n2253), .S(
Sgf_operation_mult_x_1_n2228), .ICO(Sgf_operation_mult_x_1_n2226),
.CO(Sgf_operation_mult_x_1_n2227) );
CMPR42X1TS U6389 ( .A(Sgf_operation_mult_x_1_n2384), .B(
Sgf_operation_mult_x_1_n2369), .C(Sgf_operation_mult_x_1_n2385), .D(
Sgf_operation_mult_x_1_n2366), .ICI(Sgf_operation_mult_x_1_n2382), .S(
Sgf_operation_mult_x_1_n2360), .ICO(Sgf_operation_mult_x_1_n2358),
.CO(Sgf_operation_mult_x_1_n2359) );
CMPR42X1TS U6390 ( .A(Sgf_operation_mult_x_1_n2446), .B(
Sgf_operation_mult_x_1_n2428), .C(Sgf_operation_mult_x_1_n2443), .D(
Sgf_operation_mult_x_1_n2436), .ICI(Sgf_operation_mult_x_1_n2440), .S(
Sgf_operation_mult_x_1_n2419), .ICO(Sgf_operation_mult_x_1_n2417),
.CO(Sgf_operation_mult_x_1_n2418) );
CMPR42X1TS U6391 ( .A(Sgf_operation_mult_x_1_n4003), .B(
Sgf_operation_mult_x_1_n4109), .C(Sgf_operation_mult_x_1_n3844), .D(
Sgf_operation_mult_x_1_n4215), .ICI(Sgf_operation_mult_x_1_n4162), .S(
Sgf_operation_mult_x_1_n2369), .ICO(Sgf_operation_mult_x_1_n2367),
.CO(Sgf_operation_mult_x_1_n2368) );
CMPR42X1TS U6392 ( .A(Sgf_operation_mult_x_1_n3817), .B(
Sgf_operation_mult_x_1_n3712), .C(Sgf_operation_mult_x_1_n3555), .D(
Sgf_operation_mult_x_1_n3660), .ICI(Sgf_operation_mult_x_1_n1760), .S(
Sgf_operation_mult_x_1_n1745), .ICO(Sgf_operation_mult_x_1_n1743),
.CO(Sgf_operation_mult_x_1_n1744) );
CMPR42X1TS U6393 ( .A(Sgf_operation_mult_x_1_n3935), .B(
Sgf_operation_mult_x_1_n3882), .C(Sgf_operation_mult_x_1_n2051), .D(
Sgf_operation_mult_x_1_n4306), .ICI(Sgf_operation_mult_x_1_n2028), .S(
Sgf_operation_mult_x_1_n2019), .ICO(Sgf_operation_mult_x_1_n2017),
.CO(Sgf_operation_mult_x_1_n2018) );
CMPR42X1TS U6394 ( .A(Sgf_operation_mult_x_1_n2134), .B(
Sgf_operation_mult_x_1_n2141), .C(Sgf_operation_mult_x_1_n2121), .D(
Sgf_operation_mult_x_1_n2138), .ICI(Sgf_operation_mult_x_1_n2135), .S(
Sgf_operation_mult_x_1_n2109), .ICO(Sgf_operation_mult_x_1_n2107),
.CO(Sgf_operation_mult_x_1_n2108) );
CMPR42X1TS U6395 ( .A(Sgf_operation_mult_x_1_n2468), .B(
Sgf_operation_mult_x_1_n3849), .C(Sgf_operation_mult_x_1_n4008), .D(
Sgf_operation_mult_x_1_n4167), .ICI(Sgf_operation_mult_x_1_n2481), .S(
Sgf_operation_mult_x_1_n2466), .ICO(Sgf_operation_mult_x_1_n2464),
.CO(Sgf_operation_mult_x_1_n2465) );
CMPR42X1TS U6396 ( .A(Sgf_operation_mult_x_1_n1764), .B(
Sgf_operation_mult_x_1_n1745), .C(Sgf_operation_mult_x_1_n1761), .D(
Sgf_operation_mult_x_1_n1742), .ICI(Sgf_operation_mult_x_1_n1754), .S(
Sgf_operation_mult_x_1_n1736), .ICO(Sgf_operation_mult_x_1_n1734),
.CO(Sgf_operation_mult_x_1_n1735) );
CMPR42X1TS U6397 ( .A(Sgf_operation_mult_x_1_n2282), .B(
Sgf_operation_mult_x_1_n2260), .C(Sgf_operation_mult_x_1_n2279), .D(
Sgf_operation_mult_x_1_n2257), .ICI(Sgf_operation_mult_x_1_n2276), .S(
Sgf_operation_mult_x_1_n2251), .ICO(Sgf_operation_mult_x_1_n2249),
.CO(Sgf_operation_mult_x_1_n2250) );
CMPR42X1TS U6398 ( .A(Sgf_operation_mult_x_1_n4115), .B(
Sgf_operation_mult_x_1_n4221), .C(Sgf_operation_mult_x_1_n3956), .D(
Sgf_operation_mult_x_1_n4327), .ICI(Sgf_operation_mult_x_1_n4274), .S(
Sgf_operation_mult_x_1_n2480), .ICO(Sgf_operation_mult_x_1_n2478),
.CO(Sgf_operation_mult_x_1_n2479) );
CMPR42X1TS U6399 ( .A(Sgf_operation_mult_x_1_n3653), .B(
Sgf_operation_mult_x_1_n3758), .C(Sgf_operation_mult_x_1_n3863), .D(
Sgf_operation_mult_x_1_n1631), .ICI(Sgf_operation_mult_x_1_n1628), .S(
Sgf_operation_mult_x_1_n1614), .ICO(Sgf_operation_mult_x_1_n1612),
.CO(Sgf_operation_mult_x_1_n1613) );
CMPR42X1TS U6400 ( .A(Sgf_operation_mult_x_1_n1851), .B(
Sgf_operation_mult_x_1_n1844), .C(Sgf_operation_mult_x_1_n1826), .D(
Sgf_operation_mult_x_1_n1848), .ICI(Sgf_operation_mult_x_1_n1845), .S(
Sgf_operation_mult_x_1_n1820), .ICO(Sgf_operation_mult_x_1_n1818),
.CO(Sgf_operation_mult_x_1_n1819) );
CMPR42X1TS U6401 ( .A(Sgf_operation_mult_x_1_n1900), .B(
Sgf_operation_mult_x_1_n1921), .C(Sgf_operation_mult_x_1_n1914), .D(
Sgf_operation_mult_x_1_n1894), .ICI(Sgf_operation_mult_x_1_n1915), .S(
Sgf_operation_mult_x_1_n1888), .ICO(Sgf_operation_mult_x_1_n1886),
.CO(Sgf_operation_mult_x_1_n1887) );
CMPR42X1TS U6402 ( .A(Sgf_operation_mult_x_1_n2526), .B(
Sgf_operation_mult_x_1_n2511), .C(Sgf_operation_mult_x_1_n2523), .D(
Sgf_operation_mult_x_1_n2508), .ICI(Sgf_operation_mult_x_1_n2519), .S(
Sgf_operation_mult_x_1_n2505), .ICO(Sgf_operation_mult_x_1_n2503),
.CO(Sgf_operation_mult_x_1_n2504) );
CMPR42X1TS U6403 ( .A(Sgf_operation_mult_x_1_n2354), .B(
Sgf_operation_mult_x_1_n3738), .C(Sgf_operation_mult_x_1_n3896), .D(
Sgf_operation_mult_x_1_n4055), .ICI(Sgf_operation_mult_x_1_n2370), .S(
Sgf_operation_mult_x_1_n2352), .ICO(Sgf_operation_mult_x_1_n2350),
.CO(Sgf_operation_mult_x_1_n2351) );
CMPR42X1TS U6404 ( .A(Sgf_operation_mult_x_1_n3929), .B(
Sgf_operation_mult_x_1_n3823), .C(Sgf_operation_mult_x_1_n4141), .D(
Sgf_operation_mult_x_1_n3771), .ICI(Sgf_operation_mult_x_1_n1895), .S(
Sgf_operation_mult_x_1_n1874), .ICO(Sgf_operation_mult_x_1_n1872),
.CO(Sgf_operation_mult_x_1_n1873) );
CMPR42X1TS U6405 ( .A(Sgf_operation_mult_x_1_n2083), .B(
Sgf_operation_mult_x_1_n2067), .C(Sgf_operation_mult_x_1_n2087), .D(
Sgf_operation_mult_x_1_n2064), .ICI(Sgf_operation_mult_x_1_n2061), .S(
Sgf_operation_mult_x_1_n2058), .ICO(Sgf_operation_mult_x_1_n2056),
.CO(Sgf_operation_mult_x_1_n2057) );
CMPR42X1TS U6406 ( .A(Sgf_operation_mult_x_1_n1841), .B(
Sgf_operation_mult_x_1_n1823), .C(Sgf_operation_mult_x_1_n1842), .D(
Sgf_operation_mult_x_1_n1820), .ICI(Sgf_operation_mult_x_1_n1838), .S(
Sgf_operation_mult_x_1_n1817), .ICO(Sgf_operation_mult_x_1_n1815),
.CO(Sgf_operation_mult_x_1_n1816) );
CMPR42X1TS U6407 ( .A(n5077), .B(Sgf_operation_mult_x_1_n1710), .C(
Sgf_operation_mult_x_1_n3453), .D(Sgf_operation_mult_x_1_n3552), .ICI(
Sgf_operation_mult_x_1_n3867), .S(Sgf_operation_mult_x_1_n1691), .ICO(
Sgf_operation_mult_x_1_n1689), .CO(Sgf_operation_mult_x_1_n1690) );
CMPR42X1TS U6408 ( .A(Sgf_operation_mult_x_1_n4147), .B(
Sgf_operation_mult_x_1_n4041), .C(Sgf_operation_mult_x_1_n3672), .D(
Sgf_operation_mult_x_1_n3777), .ICI(Sgf_operation_mult_x_1_n2041), .S(
Sgf_operation_mult_x_1_n2022), .ICO(Sgf_operation_mult_x_1_n2020),
.CO(Sgf_operation_mult_x_1_n2021) );
CMPR42X1TS U6409 ( .A(Sgf_operation_mult_x_1_n3937), .B(
Sgf_operation_mult_x_1_n3569), .C(Sgf_operation_mult_x_1_n2098), .D(
Sgf_operation_mult_x_1_n4361), .ICI(Sgf_operation_mult_x_1_n2099), .S(
Sgf_operation_mult_x_1_n2073), .ICO(Sgf_operation_mult_x_1_n2071),
.CO(Sgf_operation_mult_x_1_n2072) );
CMPR42X1TS U6410 ( .A(n5152), .B(Sgf_operation_mult_x_1_n3461), .C(
Sgf_operation_mult_x_1_n3512), .D(Sgf_operation_mult_x_1_n3827), .ICI(
Sgf_operation_mult_x_1_n3722), .S(Sgf_operation_mult_x_1_n1980), .ICO(
Sgf_operation_mult_x_1_n1978), .CO(Sgf_operation_mult_x_1_n1979) );
CMPR42X1TS U6411 ( .A(Sgf_operation_mult_x_1_n3669), .B(
Sgf_operation_mult_x_1_n1978), .C(Sgf_operation_mult_x_1_n3511), .D(
Sgf_operation_mult_x_1_n4197), .ICI(Sgf_operation_mult_x_1_n1979), .S(
Sgf_operation_mult_x_1_n1953), .ICO(Sgf_operation_mult_x_1_n1951),
.CO(Sgf_operation_mult_x_1_n1952) );
CMPR42X1TS U6412 ( .A(Sgf_operation_mult_x_1_n4139), .B(
Sgf_operation_mult_x_1_n3927), .C(Sgf_operation_mult_x_1_n3559), .D(
Sgf_operation_mult_x_1_n1853), .ICI(Sgf_operation_mult_x_1_n1857), .S(
Sgf_operation_mult_x_1_n1829), .ICO(Sgf_operation_mult_x_1_n1827),
.CO(Sgf_operation_mult_x_1_n1828) );
CMPR42X1TS U6413 ( .A(Sgf_operation_mult_x_1_n3916), .B(
Sgf_operation_mult_x_1_n3600), .C(Sgf_operation_mult_x_1_n3705), .D(
Sgf_operation_mult_x_1_n3810), .ICI(Sgf_operation_mult_x_1_n1629), .S(
Sgf_operation_mult_x_1_n1611), .ICO(Sgf_operation_mult_x_1_n1609),
.CO(Sgf_operation_mult_x_1_n1610) );
CMPR42X1TS U6414 ( .A(Sgf_operation_mult_x_1_n2411), .B(
Sgf_operation_mult_x_1_n4058), .C(Sgf_operation_mult_x_1_n4376), .D(
Sgf_operation_mult_x_1_n4270), .ICI(Sgf_operation_mult_x_1_n2427), .S(
Sgf_operation_mult_x_1_n2403), .ICO(Sgf_operation_mult_x_1_n2401),
.CO(Sgf_operation_mult_x_1_n2402) );
CMPR42X1TS U6415 ( .A(Sgf_operation_mult_x_1_n2230), .B(
Sgf_operation_mult_x_1_n2208), .C(Sgf_operation_mult_x_1_n2227), .D(
Sgf_operation_mult_x_1_n2205), .ICI(Sgf_operation_mult_x_1_n2223), .S(
Sgf_operation_mult_x_1_n2202), .ICO(Sgf_operation_mult_x_1_n2200),
.CO(Sgf_operation_mult_x_1_n2201) );
CMPR42X1TS U6416 ( .A(Sgf_operation_mult_x_1_n1559), .B(
Sgf_operation_mult_x_1_n1563), .C(Sgf_operation_mult_x_1_n1560), .D(
Sgf_operation_mult_x_1_n1545), .ICI(Sgf_operation_mult_x_1_n1556), .S(
Sgf_operation_mult_x_1_n1542), .ICO(Sgf_operation_mult_x_1_n1540),
.CO(Sgf_operation_mult_x_1_n1541) );
CMPR42X1TS U6417 ( .A(Sgf_operation_mult_x_1_n4170), .B(
Sgf_operation_mult_x_1_n4382), .C(Sgf_operation_mult_x_1_n2529), .D(
Sgf_operation_mult_x_1_n2514), .ICI(Sgf_operation_mult_x_1_n2522), .S(
Sgf_operation_mult_x_1_n2508), .ICO(Sgf_operation_mult_x_1_n2506),
.CO(Sgf_operation_mult_x_1_n2507) );
CMPR42X1TS U6418 ( .A(Sgf_operation_mult_x_1_n1569), .B(
Sgf_operation_mult_x_1_n3650), .C(Sgf_operation_mult_x_1_n3755), .D(
Sgf_operation_mult_x_1_n3860), .ICI(Sgf_operation_mult_x_1_n1578), .S(
Sgf_operation_mult_x_1_n1564), .ICO(Sgf_operation_mult_x_1_n1562),
.CO(Sgf_operation_mult_x_1_n1563) );
CMPR42X1TS U6419 ( .A(Sgf_operation_mult_x_1_n4381), .B(
Sgf_operation_mult_x_1_n2512), .C(Sgf_operation_mult_x_1_n4010), .D(
Sgf_operation_mult_x_1_n4328), .ICI(Sgf_operation_mult_x_1_n2500), .S(
Sgf_operation_mult_x_1_n2494), .ICO(Sgf_operation_mult_x_1_n2492),
.CO(Sgf_operation_mult_x_1_n2493) );
CMPR42X1TS U6420 ( .A(Sgf_operation_mult_x_1_n3819), .B(
Sgf_operation_mult_x_1_n4031), .C(Sgf_operation_mult_x_1_n3662), .D(
Sgf_operation_mult_x_1_n3557), .ICI(Sgf_operation_mult_x_1_n1809), .S(
Sgf_operation_mult_x_1_n1787), .ICO(Sgf_operation_mult_x_1_n1785),
.CO(Sgf_operation_mult_x_1_n1786) );
CMPR42X1TS U6421 ( .A(Sgf_operation_mult_x_1_n3465), .B(
Sgf_operation_mult_x_1_n3516), .C(Sgf_operation_mult_x_1_n3726), .D(
Sgf_operation_mult_x_1_n3831), .ICI(Sgf_operation_mult_x_1_n3674), .S(
Sgf_operation_mult_x_1_n2076), .ICO(Sgf_operation_mult_x_1_n2074),
.CO(Sgf_operation_mult_x_1_n2075) );
CMPR42X1TS U6422 ( .A(Sgf_operation_mult_x_1_n2222), .B(
Sgf_operation_mult_x_1_n3627), .C(Sgf_operation_mult_x_1_n3837), .D(
Sgf_operation_mult_x_1_n3785), .ICI(Sgf_operation_mult_x_1_n2241), .S(
Sgf_operation_mult_x_1_n2220), .ICO(Sgf_operation_mult_x_1_n2218),
.CO(Sgf_operation_mult_x_1_n2219) );
CMPR42X1TS U6423 ( .A(Sgf_operation_mult_x_1_n4064), .B(
Sgf_operation_mult_x_1_n4011), .C(Sgf_operation_mult_x_1_n3958), .D(
Sgf_operation_mult_x_1_n2531), .ICI(Sgf_operation_mult_x_1_n2525), .S(
Sgf_operation_mult_x_1_n2514), .ICO(Sgf_operation_mult_x_1_n2512),
.CO(Sgf_operation_mult_x_1_n2513) );
CMPR42X1TS U6424 ( .A(Sgf_operation_mult_x_1_n3595), .B(
Sgf_operation_mult_x_1_n3700), .C(Sgf_operation_mult_x_1_n1539), .D(
Sgf_operation_mult_x_1_n1552), .ICI(Sgf_operation_mult_x_1_n1546), .S(
Sgf_operation_mult_x_1_n1537), .ICO(Sgf_operation_mult_x_1_n1535),
.CO(Sgf_operation_mult_x_1_n1536) );
CMPR42X1TS U6425 ( .A(Sgf_operation_mult_x_1_n2229), .B(
Sgf_operation_mult_x_1_n2236), .C(Sgf_operation_mult_x_1_n2233), .D(
Sgf_operation_mult_x_1_n2211), .ICI(Sgf_operation_mult_x_1_n2226), .S(
Sgf_operation_mult_x_1_n2205), .ICO(Sgf_operation_mult_x_1_n2203),
.CO(Sgf_operation_mult_x_1_n2204) );
CMPR42X1TS U6426 ( .A(Sgf_operation_mult_x_1_n3780), .B(
Sgf_operation_mult_x_1_n3885), .C(Sgf_operation_mult_x_1_n3622), .D(
Sgf_operation_mult_x_1_n4309), .ICI(Sgf_operation_mult_x_1_n3727), .S(
Sgf_operation_mult_x_1_n2097), .ICO(Sgf_operation_mult_x_1_n2095),
.CO(Sgf_operation_mult_x_1_n2096) );
CMPR42X1TS U6427 ( .A(Sgf_operation_mult_x_1_n3839), .B(
Sgf_operation_mult_x_1_n3945), .C(Sgf_operation_mult_x_1_n4051), .D(
Sgf_operation_mult_x_1_n2287), .ICI(Sgf_operation_mult_x_1_n2266), .S(
Sgf_operation_mult_x_1_n2263), .ICO(Sgf_operation_mult_x_1_n2261),
.CO(Sgf_operation_mult_x_1_n2262) );
CMPR42X1TS U6428 ( .A(Sgf_operation_mult_x_1_n3464), .B(
Sgf_operation_mult_x_1_n3568), .C(Sgf_operation_mult_x_1_n3515), .D(
Sgf_operation_mult_x_1_n3673), .ICI(Sgf_operation_mult_x_1_n3778), .S(
Sgf_operation_mult_x_1_n2052), .ICO(Sgf_operation_mult_x_1_n2050),
.CO(Sgf_operation_mult_x_1_n2051) );
CMPR42X1TS U6429 ( .A(Sgf_operation_mult_x_1_n3997), .B(
Sgf_operation_mult_x_1_n3891), .C(Sgf_operation_mult_x_1_n3733), .D(
Sgf_operation_mult_x_1_n4209), .ICI(Sgf_operation_mult_x_1_n3944), .S(
Sgf_operation_mult_x_1_n2240), .ICO(Sgf_operation_mult_x_1_n2238),
.CO(Sgf_operation_mult_x_1_n2239) );
CMPR42X1TS U6430 ( .A(Sgf_operation_mult_x_1_n3754), .B(
Sgf_operation_mult_x_1_n3859), .C(Sgf_operation_mult_x_1_n3492), .D(
Sgf_operation_mult_x_1_n1568), .ICI(Sgf_operation_mult_x_1_n3596), .S(
Sgf_operation_mult_x_1_n1551), .ICO(Sgf_operation_mult_x_1_n1549),
.CO(Sgf_operation_mult_x_1_n1550) );
CMPR42X1TS U6431 ( .A(Sgf_operation_mult_x_1_n3858), .B(
Sgf_operation_mult_x_1_n3753), .C(Sgf_operation_mult_x_1_n1550), .D(
Sgf_operation_mult_x_1_n1537), .ICI(Sgf_operation_mult_x_1_n1547), .S(
Sgf_operation_mult_x_1_n1531), .ICO(Sgf_operation_mult_x_1_n1529),
.CO(Sgf_operation_mult_x_1_n1530) );
CMPR42X1TS U6432 ( .A(Sgf_operation_mult_x_1_n4085), .B(
Sgf_operation_mult_x_1_n3768), .C(Sgf_operation_mult_x_1_n1833), .D(
Sgf_operation_mult_x_1_n3715), .ICI(Sgf_operation_mult_x_1_n1814), .S(
Sgf_operation_mult_x_1_n1808), .ICO(Sgf_operation_mult_x_1_n1806),
.CO(Sgf_operation_mult_x_1_n1807) );
CMPR42X1TS U6433 ( .A(Sgf_operation_mult_x_1_n2744), .B(
Sgf_operation_mult_x_1_n4297), .C(Sgf_operation_mult_x_1_n4403), .D(
Sgf_operation_mult_x_1_n4350), .ICI(Sgf_operation_mult_x_1_n2745), .S(
Sgf_operation_mult_x_1_n2742), .ICO(Sgf_operation_mult_x_1_n2740),
.CO(Sgf_operation_mult_x_1_n2741) );
CMPR42X1TS U6434 ( .A(Sgf_operation_mult_x_1_n2702), .B(
Sgf_operation_mult_x_1_n4185), .C(Sgf_operation_mult_x_1_n4397), .D(
Sgf_operation_mult_x_1_n4344), .ICI(Sgf_operation_mult_x_1_n2706), .S(
Sgf_operation_mult_x_1_n2700), .ICO(Sgf_operation_mult_x_1_n2698),
.CO(Sgf_operation_mult_x_1_n2699) );
CMPR42X1TS U6435 ( .A(Sgf_operation_mult_x_1_n4103), .B(
Sgf_operation_mult_x_1_n4315), .C(Sgf_operation_mult_x_1_n3838), .D(
Sgf_operation_mult_x_1_n4050), .ICI(Sgf_operation_mult_x_1_n2258), .S(
Sgf_operation_mult_x_1_n2237), .ICO(Sgf_operation_mult_x_1_n2235),
.CO(Sgf_operation_mult_x_1_n2236) );
CMPR42X1TS U6436 ( .A(Sgf_operation_mult_x_1_n3873), .B(
Sgf_operation_mult_x_1_n3979), .C(Sgf_operation_mult_x_1_n3505), .D(
Sgf_operation_mult_x_1_n3610), .ICI(Sgf_operation_mult_x_1_n1834), .S(
Sgf_operation_mult_x_1_n1811), .ICO(Sgf_operation_mult_x_1_n1809),
.CO(Sgf_operation_mult_x_1_n1810) );
CMPR42X1TS U6437 ( .A(Sgf_operation_mult_x_1_n3879), .B(
Sgf_operation_mult_x_1_n3985), .C(Sgf_operation_mult_x_1_n3616), .D(
Sgf_operation_mult_x_1_n3721), .ICI(Sgf_operation_mult_x_1_n1969), .S(
Sgf_operation_mult_x_1_n1950), .ICO(Sgf_operation_mult_x_1_n1948),
.CO(Sgf_operation_mult_x_1_n1949) );
CMPR42X1TS U6438 ( .A(Sgf_operation_mult_x_1_n1859), .B(
Sgf_operation_mult_x_1_n3560), .C(Sgf_operation_mult_x_1_n3665), .D(
Sgf_operation_mult_x_1_n3507), .ICI(Sgf_operation_mult_x_1_n3717), .S(
Sgf_operation_mult_x_1_n1858), .ICO(Sgf_operation_mult_x_1_n1856),
.CO(Sgf_operation_mult_x_1_n1857) );
CMPR42X1TS U6439 ( .A(Sgf_operation_mult_x_1_n4145), .B(
Sgf_operation_mult_x_1_n3670), .C(Sgf_operation_mult_x_1_n3775), .D(
Sgf_operation_mult_x_1_n3565), .ICI(Sgf_operation_mult_x_1_n2003), .S(
Sgf_operation_mult_x_1_n1971), .ICO(Sgf_operation_mult_x_1_n1969),
.CO(Sgf_operation_mult_x_1_n1970) );
CMPR42X1TS U6440 ( .A(Sgf_operation_mult_x_1_n1529), .B(
Sgf_operation_mult_x_1_n1521), .C(Sgf_operation_mult_x_1_n1530), .D(
Sgf_operation_mult_x_1_n1518), .ICI(Sgf_operation_mult_x_1_n1526), .S(
Sgf_operation_mult_x_1_n1515), .ICO(Sgf_operation_mult_x_1_n1513),
.CO(Sgf_operation_mult_x_1_n1514) );
CMPR42X1TS U6441 ( .A(Sgf_operation_mult_x_1_n3490), .B(
Sgf_operation_mult_x_1_n1532), .C(Sgf_operation_mult_x_1_n1524), .D(
Sgf_operation_mult_x_1_n1536), .ICI(Sgf_operation_mult_x_1_n1533), .S(
Sgf_operation_mult_x_1_n1518), .ICO(Sgf_operation_mult_x_1_n1516),
.CO(Sgf_operation_mult_x_1_n1517) );
CMPR42X1TS U6442 ( .A(Sgf_operation_mult_x_1_n1507), .B(
Sgf_operation_mult_x_1_n1520), .C(Sgf_operation_mult_x_1_n1517), .D(
Sgf_operation_mult_x_1_n1504), .ICI(Sgf_operation_mult_x_1_n1513), .S(
Sgf_operation_mult_x_1_n1501), .ICO(Sgf_operation_mult_x_1_n1499),
.CO(Sgf_operation_mult_x_1_n1500) );
CMPR42X1TS U6443 ( .A(Sgf_operation_mult_x_1_n3541), .B(
Sgf_operation_mult_x_1_n1519), .C(Sgf_operation_mult_x_1_n1523), .D(
Sgf_operation_mult_x_1_n1510), .ICI(Sgf_operation_mult_x_1_n1516), .S(
Sgf_operation_mult_x_1_n1504), .ICO(Sgf_operation_mult_x_1_n1502),
.CO(Sgf_operation_mult_x_1_n1503) );
CMPR42X1TS U6444 ( .A(Sgf_operation_mult_x_1_n3698), .B(
Sgf_operation_mult_x_1_n3593), .C(Sgf_operation_mult_x_1_n1522), .D(
Sgf_operation_mult_x_1_n3646), .ICI(Sgf_operation_mult_x_1_n3751), .S(
Sgf_operation_mult_x_1_n1507), .ICO(Sgf_operation_mult_x_1_n1505),
.CO(Sgf_operation_mult_x_1_n1506) );
CMPR42X1TS U6445 ( .A(Sgf_operation_mult_x_1_n1464), .B(
Sgf_operation_mult_x_1_n1458), .C(Sgf_operation_mult_x_1_n1465), .D(
Sgf_operation_mult_x_1_n1455), .ICI(Sgf_operation_mult_x_1_n1461), .S(
Sgf_operation_mult_x_1_n1452), .ICO(Sgf_operation_mult_x_1_n1450),
.CO(Sgf_operation_mult_x_1_n1451) );
CMPR42X1TS U6446 ( .A(Sgf_operation_mult_x_1_n1447), .B(
Sgf_operation_mult_x_1_n1437), .C(Sgf_operation_mult_x_1_n1434), .D(
Sgf_operation_mult_x_1_n1444), .ICI(Sgf_operation_mult_x_1_n1440), .S(
Sgf_operation_mult_x_1_n1431), .ICO(Sgf_operation_mult_x_1_n1429),
.CO(Sgf_operation_mult_x_1_n1430) );
CMPR42X1TS U6447 ( .A(Sgf_operation_mult_x_1_n3483), .B(
Sgf_operation_mult_x_1_n3442), .C(Sgf_operation_mult_x_1_n1446), .D(
Sgf_operation_mult_x_1_n3640), .ICI(Sgf_operation_mult_x_1_n1443), .S(
Sgf_operation_mult_x_1_n1434), .ICO(Sgf_operation_mult_x_1_n1432),
.CO(Sgf_operation_mult_x_1_n1433) );
CMPR42X1TS U6448 ( .A(Sgf_operation_mult_x_1_n1459), .B(
Sgf_operation_mult_x_1_n1456), .C(Sgf_operation_mult_x_1_n3693), .D(
Sgf_operation_mult_x_1_n3484), .ICI(Sgf_operation_mult_x_1_n1448), .S(
Sgf_operation_mult_x_1_n1445), .ICO(Sgf_operation_mult_x_1_n1443),
.CO(Sgf_operation_mult_x_1_n1444) );
CMPR42X1TS U6449 ( .A(Sgf_operation_mult_x_1_n3584), .B(
Sgf_operation_mult_x_1_n1413), .C(Sgf_operation_mult_x_1_n1414), .D(
Sgf_operation_mult_x_1_n1405), .ICI(Sgf_operation_mult_x_1_n1410), .S(
Sgf_operation_mult_x_1_n1402), .ICO(Sgf_operation_mult_x_1_n1400),
.CO(Sgf_operation_mult_x_1_n1401) );
CMPR42X1TS U6450 ( .A(Sgf_operation_mult_x_1_n1417), .B(
Sgf_operation_mult_x_1_n1423), .C(Sgf_operation_mult_x_1_n1415), .D(
Sgf_operation_mult_x_1_n1424), .ICI(Sgf_operation_mult_x_1_n1420), .S(
Sgf_operation_mult_x_1_n1412), .ICO(Sgf_operation_mult_x_1_n1410),
.CO(Sgf_operation_mult_x_1_n1411) );
CMPR42X1TS U6451 ( .A(n5087), .B(Sgf_operation_mult_x_1_n1438), .C(
Sgf_operation_mult_x_1_n3441), .D(Sgf_operation_mult_x_1_n3639), .ICI(
Sgf_operation_mult_x_1_n3534), .S(Sgf_operation_mult_x_1_n1428), .ICO(
Sgf_operation_mult_x_1_n1426), .CO(Sgf_operation_mult_x_1_n1427) );
CMPR42X1TS U6452 ( .A(Sgf_operation_mult_x_1_n3438), .B(
Sgf_operation_mult_x_1_n1388), .C(Sgf_operation_mult_x_1_n1389), .D(
Sgf_operation_mult_x_1_n1382), .ICI(Sgf_operation_mult_x_1_n1385), .S(
Sgf_operation_mult_x_1_n1379), .ICO(Sgf_operation_mult_x_1_n1377),
.CO(Sgf_operation_mult_x_1_n1378) );
CMPR42X1TS U6453 ( .A(Sgf_operation_mult_x_1_n3580), .B(
Sgf_operation_mult_x_1_n3476), .C(Sgf_operation_mult_x_1_n1376), .D(
Sgf_operation_mult_x_1_n1381), .ICI(Sgf_operation_mult_x_1_n1377), .S(
Sgf_operation_mult_x_1_n1373), .ICO(Sgf_operation_mult_x_1_n1371),
.CO(Sgf_operation_mult_x_1_n1372) );
CMPR42X1TS U6454 ( .A(Sgf_operation_mult_x_1_n3526), .B(
Sgf_operation_mult_x_1_n1361), .C(Sgf_operation_mult_x_1_n1367), .D(
Sgf_operation_mult_x_1_n3474), .ICI(Sgf_operation_mult_x_1_n1364), .S(
Sgf_operation_mult_x_1_n1359), .ICO(Sgf_operation_mult_x_1_n1357),
.CO(Sgf_operation_mult_x_1_n1358) );
CMPR42X1TS U6455 ( .A(Sgf_operation_mult_x_1_n3475), .B(
Sgf_operation_mult_x_1_n3527), .C(Sgf_operation_mult_x_1_n1368), .D(
Sgf_operation_mult_x_1_n1375), .ICI(Sgf_operation_mult_x_1_n1371), .S(
Sgf_operation_mult_x_1_n1366), .ICO(Sgf_operation_mult_x_1_n1364),
.CO(Sgf_operation_mult_x_1_n1365) );
CMPR42X1TS U6456 ( .A(Sgf_operation_mult_x_1_n1351), .B(
Sgf_operation_mult_x_1_n3524), .C(Sgf_operation_mult_x_1_n1355), .D(
Sgf_operation_mult_x_1_n3472), .ICI(Sgf_operation_mult_x_1_n1352), .S(
Sgf_operation_mult_x_1_n1350), .ICO(Sgf_operation_mult_x_1_n1348),
.CO(Sgf_operation_mult_x_1_n1349) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk30.tcl_DW_1STAGE_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
module CORDIC_FSM_v2_tb;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//declaration of signals
//Input Signals
reg clk; // Reloj del sitema.
reg reset; // Reset del sitema.
reg beg_FSM_CORDIC; // Señal de inicio de la maquina de estados.
reg ACK_FSM_CORDIC; // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
reg operation; // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
reg [1:0] shift_region_flag; // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
reg [1:0] cont_var; // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
reg ready_add_subt; // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
reg max_tick_iter;
reg min_tick_iter; // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
reg max_tick_var;
reg min_tick_var; // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
wire reset_reg_cordic;
wire ready_CORDIC; // Señal que indica que el calculo CORDIC se ha terminado.
wire beg_add_subt; // Señal que indica al modulo de suma/resta que inicie su operacion.
wire ack_add_subt; // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
wire sel_mux_1;
wire sel_mux_3; // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
wire [1:0] sel_mux_2; // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
wire mode; // 1'b0 si el modo es rotacion(signo de Y), 1'b1 si el modo es vectorizacion(signo de Z).
wire enab_cont_iter;
wire load_cont_iter; // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
wire enab_cont_var;
wire load_cont_var; // Señales de habilitacion y carga, respectivamente, en el contador de variables.
wire enab_RB1;
wire enab_RB2; // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
wire enab_d_ff_Xn;
wire enab_d_ff_Yn;
wire enab_d_ff_Zn; // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
wire enab_d_ff_out; // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
wire enab_dff_shifted_x;
wire enab_dff_shifted_y; // Señales de habilitacion para los registros que guardan el valor de las variables X y Y luego de realizarles los desplazamientos.
wire enab_dff_LUT;
wire enab_dff_sign; // Señales de habilitacion para los registros que guardan los valores provenientes de la look-up table y del signo, respectivamente.
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Instantiation of the FSM
CORDIC_FSM_v2 cordic_fsm_v2
(
//Input Signals
.clk(clk), // Reloj del sitema.
.reset(reset), // Reset del sitema.
.beg_FSM_CORDIC(beg_FSM_CORDIC), // Señal de inicio de la maquina de estados.
.ACK_FSM_CORDIC(ACK_FSM_CORDIC), // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
.operation(operation), // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
.shift_region_flag(shift_region_flag), // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
.cont_var(cont_var), // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
.ready_add_subt(ready_add_subt), // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
.max_tick_iter(max_tick_iter),
.min_tick_iter(min_tick_iter), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
.max_tick_var(max_tick_var),
.min_tick_var(min_tick_var), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
.reset_reg_cordic(reset_reg_cordic),
.ready_CORDIC(ready_CORDIC), // Señal que indica que el calculo CORDIC se ha terminado.
.beg_add_subt(beg_add_subt), // Señal que indica al modulo de suma/resta que inicie su operacion.
.ack_add_subt(ack_add_subt), // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
.sel_mux_1(sel_mux_1),
.sel_mux_3(sel_mux_3), // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
.sel_mux_2(sel_mux_2), // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
.mode(mode), // 1'b0 si el modo es rotacion(signo de Y), 1'b1 si el modo es vectorizacion(signo de Z).
.enab_cont_iter(enab_cont_iter),
.load_cont_iter(load_cont_iter), // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
.enab_cont_var(enab_cont_var),
.load_cont_var(load_cont_var), // Señales de habilitacion y carga, respectivamente, en el contador de variables.
.enab_RB1(enab_RB1),
.enab_RB2(enab_RB2), // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
.enab_d_ff_Xn(enab_d_ff_Xn),
.enab_d_ff_Yn(enab_d_ff_Yn),
.enab_d_ff_Zn(enab_d_ff_Zn), // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
.enab_d_ff_out(enab_d_ff_out), // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
.enab_dff_shifted_x(enab_dff_shifted_x),
.enab_dff_shifted_y(enab_dff_shifted_y), // Señales de habilitacion para los registros que guardan el valor de las variables X y Y luego de realizarles los desplazamientos.
.enab_dff_LUT(enab_dff_LUT),
.enab_dff_sign(enab_dff_sign) // Señales de habilitacion para los registros que guardan los valores provenientes de la look-up table y del signo, respectivamente.
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Generation of the clock
initial
begin
clk = 1;
forever #5 clk = ~clk;
end
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Stimulus specification
initial
begin
//inicializacion de señales
reset = 0;
beg_FSM_CORDIC = 0;
ACK_FSM_CORDIC = 0;
operation = 0;
shift_region_flag = 2'b10;
cont_var = 2'b00;
ready_add_subt = 0;
max_tick_iter = 0;
min_tick_iter = 0;
max_tick_var = 0;
min_tick_var = 0;
#100
reset = 1;
operation = 0;
shift_region_flag = 2'b00;
#10
reset = 0;
#10
beg_FSM_CORDIC = 1;
min_tick_iter = 1;
min_tick_var = 1;
#10
beg_FSM_CORDIC = 0;
#55
ready_add_subt = 1;
#10
ready_add_subt = 0;
min_tick_var = 0;
cont_var = 2'b01;
#25
ready_add_subt = 1;
#30
ready_add_subt = 0;
cont_var = 2'b10;
max_tick_var = 1;
#35
ready_add_subt = 1;
#10
ready_add_subt = 0;
min_tick_iter = 0;
#25
max_tick_var = 0;
min_tick_var = 0;
max_tick_iter = 1;
#5
max_tick_var = 1;
#30
ready_add_subt = 1;
#10
ready_add_subt = 0;
#40
ACK_FSM_CORDIC = 1'b1;
#100 $stop;
end
endmodule
|
module daala_4x4_transpose_v1_0_S00_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// AXI4Stream sink: Data Width
parameter integer C_S_AXIS_TDATA_WIDTH = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// AXI4Stream sink: Clock
input wire S_AXIS_ACLK,
// AXI4Stream sink: Reset
input wire S_AXIS_ARESETN,
// Ready to accept data in
output wire S_AXIS_TREADY,
// Data in
input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
// Byte qualifier
input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
// Indicates boundary of last packet
input wire S_AXIS_TLAST,
// Data is in valid
input wire S_AXIS_TVALID
);
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// Total number of input data.
localparam NUMBER_OF_INPUT_WORDS = 8;
// bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
// Define the states of state machine
// The control state machine oversees the writing of input streaming data to the FIFO,
// and outputs the streaming data from the FIFO
parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
WRITE_FIFO = 1'b1; // In this state FIFO is written with the
// input stream data S_AXIS_TDATA
wire axis_tready;
// State variable
reg mst_exec_state;
// FIFO implementation signals
genvar byte_index;
// FIFO write enable
wire fifo_wren;
// FIFO full flag
reg fifo_full_flag;
// FIFO write pointer
reg [bit_num-1:0] write_pointer;
// sink has accepted all the streaming data and stored in FIFO
reg writes_done;
// I/O Connections assignments
assign S_AXIS_TREADY = axis_tready;
// Control state machine implementation
always @(posedge S_AXIS_ACLK)
begin
if (!S_AXIS_ARESETN)
// Synchronous reset (active low)
begin
mst_exec_state <= IDLE;
end
else
case (mst_exec_state)
IDLE:
// The sink starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if (S_AXIS_TVALID)
begin
mst_exec_state <= WRITE_FIFO;
end
else
begin
mst_exec_state <= IDLE;
end
WRITE_FIFO:
// When the sink has accepted all the streaming input data,
// the interface swiches functionality to a streaming master
if (writes_done)
begin
mst_exec_state <= IDLE;
end
else
begin
// The sink accepts and stores tdata
// into FIFO
mst_exec_state <= WRITE_FIFO;
end
endcase
end
// AXI Streaming Sink
//
// The example design sink is always ready to accept the S_AXIS_TDATA until
// the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
always@(posedge S_AXIS_ACLK)
begin
if(!S_AXIS_ARESETN)
begin
write_pointer <= 0;
writes_done <= 1'b0;
end
else
if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
begin
if (fifo_wren)
begin
// write pointer is incremented after every write to the FIFO
// when FIFO write signal is enabled.
write_pointer <= write_pointer + 1;
writes_done <= 1'b0;
end
if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
begin
// reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
// has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
writes_done <= 1'b1;
end
end
end
// FIFO write enable generation
assign fifo_wren = S_AXIS_TVALID && axis_tready;
// FIFO Implementation
generate
for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
begin:FIFO_GEN
reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
// Streaming input data is stored in FIFO
always @( posedge S_AXIS_ACLK )
begin
if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
begin
stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
end
end
end
endgenerate
// Add user logic here
// User logic ends
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:59 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_0/system_auto_us_0_stub.v
// Design : system_auto_us_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion,
m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp,
m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/*
* Planar mode graphics for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_planar_fml (
input clk,
input rst,
input enable,
// CSR slave interface for reading
output [17:1] fml_adr_o,
input [15:0] fml_dat_i,
output fml_stb_o,
// Controller registers
input [3:0] attr_plane_enable,
input x_dotclockdiv2,
input [9:0] h_count,
input [9:0] v_count,
input horiz_sync_i,
input video_on_h_i,
output video_on_h_o,
output reg [3:0] attr,
output horiz_sync_o
);
// Registers and net
reg [11:0] row_addr;
reg [ 5:0] col_addr;
reg [14:0] word_offset;
reg [ 1:0] plane_addr0;
reg [ 1:0] plane_addr;
reg [15:0] plane0;
reg [15:0] plane0_tmp;
reg [15:0] plane1;
reg [15:0] plane1_tmp;
reg [15:0] plane2;
reg [15:0] plane2_tmp;
reg [15:0] plane3;
reg [ 7:0] bit_mask0;
reg [ 7:0] bit_mask1;
wire [15:0] bit_mask;
wire v_count0;
wire bit3, bit2, bit1, bit0;
reg [9:0] video_on_h;
reg [9:0] horiz_sync;
reg [7:0] pipe;
// Continous assignments
assign fml_adr_o = { word_offset, plane_addr };
assign bit_mask = { bit_mask1, bit_mask0 };
assign bit0 = |(bit_mask & plane0);
assign bit1 = |(bit_mask & plane1);
assign bit2 = |(bit_mask & plane2);
assign bit3 = |(bit_mask & plane3);
assign video_on_h_o = video_on_h[9];
assign horiz_sync_o = horiz_sync[9];
assign fml_stb_o = |pipe[4:1];
assign v_count0 = x_dotclockdiv2 ? 1'b0 : v_count[0];
// Behaviour
// Pipeline count
always @(posedge clk)
if (rst)
begin
pipe <= 8'b0;
end
else
if (enable)
begin
pipe <= { pipe[6:0],
x_dotclockdiv2 ? (h_count[4:0]==5'h0) : (h_count[3:0]==4'h0) };
end
// video_on_h
always @(posedge clk)
if (rst)
begin
video_on_h <= 10'b0;
end
else
if (enable)
begin
video_on_h <= { video_on_h[8:0], video_on_h_i };
end
// horiz_sync
always @(posedge clk)
if (rst)
begin
horiz_sync <= 10'b0;
end
else
if (enable)
begin
horiz_sync <= { horiz_sync[8:0], horiz_sync_i };
end
// Address generation
always @(posedge clk)
if (rst)
begin
row_addr <= 12'h0;
col_addr <= 6'h0;
plane_addr0 <= 2'b00;
word_offset <= 15'h0;
plane_addr <= 2'b00;
end
else
if (enable)
begin
// Loading new row_addr and col_addr when h_count[3:0]==4'h0
// v_count * 40 or 22 (depending on x_dotclockdiv2)
row_addr <= { v_count[9:1], v_count0, 2'b00 } + { v_count[9:1], v_count0 }
+ (x_dotclockdiv2 ? v_count[9:1] : 9'h0);
col_addr <= x_dotclockdiv2 ? h_count[9:5] : h_count[9:4];
plane_addr0 <= h_count[1:0];
// Load new word_offset at +1
word_offset <= (x_dotclockdiv2 ? { row_addr, 1'b0 }
: { row_addr, 3'b000 }) + col_addr;
plane_addr <= plane_addr0;
end
// Temporary plane data
always @(posedge clk)
if (rst)
begin
plane0_tmp <= 16'h0;
plane1_tmp <= 16'h0;
plane2_tmp <= 16'h0;
end
else
if (enable)
begin
// Load plane0 when pipe == 4
plane0_tmp <= pipe[4] ? fml_dat_i : plane0_tmp;
plane1_tmp <= pipe[5] ? fml_dat_i : plane1_tmp;
plane2_tmp <= pipe[6] ? fml_dat_i : plane2_tmp;
end
// Plane data
always @(posedge clk)
if (rst)
begin
plane0 <= 16'h0;
plane1 <= 16'h0;
plane2 <= 16'h0;
plane3 <= 16'h0;
end
else
if (enable)
begin
plane0 <= pipe[7] ? plane0_tmp : plane0;
plane1 <= pipe[7] ? plane1_tmp : plane1;
plane2 <= pipe[7] ? plane2_tmp : plane2;
plane3 <= pipe[7] ? fml_dat_i : plane3;
end
// Bit masks
always @(posedge clk)
if (rst)
begin
bit_mask0 <= 8'h0;
bit_mask1 <= 8'h0;
end
else
if (enable)
begin
bit_mask0 <= (h_count[0] & x_dotclockdiv2) ? bit_mask0
: { pipe[7], bit_mask0[7:1] };
bit_mask1 <= (h_count[0] & x_dotclockdiv2) ? bit_mask1
: { bit_mask0[0], bit_mask1[7:1] };
end
// attr
always @(posedge clk)
if (rst)
begin
attr <= 4'h0;
end
else
if (enable)
begin
attr <= (attr_plane_enable & { bit3, bit2, bit1, bit0 });
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule
|
// This Verilog file automatically generated from controller.asm
//
module serial_wb_program(clk_i, pm_addr_i, pm_insn_o);
input clk_i;
input [9:0] pm_addr_i;
output [15:0] pm_insn_o;
wire clk_i;
wire [9:0] pm_addr_i;
reg [15:0] pm_insn_o;
always @(posedge clk_i)
case(pm_addr_i)
10'h000: pm_insn_o <= 16'h4f00; // set #0x0,r15
10'h001: pm_insn_o <= 16'hffff; // nop
10'h002: pm_insn_o <= 16'hffff; // nop
10'h003: pm_insn_o <= 16'h4000; // set #0x0,r0
10'h004: pm_insn_o <= 16'h4100; // set #0x0,r1
10'h005: pm_insn_o <= 16'h40ff; // set #0xff,r0
10'h006: pm_insn_o <= 16'h41ff; // set #0xff,r1
10'h007: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h008: pm_insn_o <= 16'h8407; // jmpc delayloop
10'h009: pm_insn_o <= 16'hffff; // nop
10'h00a: pm_insn_o <= 16'h4040; // set #0x40,r0
10'h00b: pm_insn_o <= 16'h8625; // jsr putc
10'h00c: pm_insn_o <= 16'h4300; // set LOW greetingstring,r3 ; Pointer to greeting string
10'h00d: pm_insn_o <= 16'h4405; // set HIGH greetingstring,r4
10'h00e: pm_insn_o <= 16'h87d3; // jsr puts
10'h00f: pm_insn_o <= 16'h400d; // set #0x0d,r0
10'h010: pm_insn_o <= 16'h8625; // jsr putc
10'h011: pm_insn_o <= 16'h400a; // set #0x0a,r0
10'h012: pm_insn_o <= 16'h8625; // jsr putc
10'h013: pm_insn_o <= 16'h403e; // set #0x3e,r0 ; '>'
10'h014: pm_insn_o <= 16'h8625; // jsr putc ; print prompt
10'h015: pm_insn_o <= 16'h8631; // jsr getc ; get command character
10'h016: pm_insn_o <= 16'h4144; // set #0x44,r1 ; 'D'
10'h017: pm_insn_o <= 16'h1101; // xor r0,r1,r1
10'h018: pm_insn_o <= 16'h82cd; // jmpz handle_logicanalyzer
10'h019: pm_insn_o <= 16'hffff; // nop
10'h01a: pm_insn_o <= 16'h4154; // set #0x54,r1 ; 'T' set trigger
10'h01b: pm_insn_o <= 16'h1101; // xor r0,r1,r1
10'h01c: pm_insn_o <= 16'h8380; // jmpz handle_settrigger
10'h01d: pm_insn_o <= 16'hffff; // nop
10'h01e: pm_insn_o <= 16'h4174; // set #0x74,r1 ; 't' trigger it
10'h01f: pm_insn_o <= 16'h1101; // xor r0,r1,r1
10'h020: pm_insn_o <= 16'h8334; // jmpz handle_trigger
10'h021: pm_insn_o <= 16'hffff; // nop
10'h022: pm_insn_o <= 16'h4007; // set #0x7,r0 ; ctrl g
10'h023: pm_insn_o <= 16'h8625; // jsr putc
10'h024: pm_insn_o <= 16'h800f; // jmp menuloop
10'h025: pm_insn_o <= 16'h4101; // set #0x1,r1
10'h026: pm_insn_o <= 16'h9010; // out0 r1
10'h027: pm_insn_o <= 16'h4202; // set #0x2,r2 ; UART_TX_IDLE
10'h028: pm_insn_o <= 16'hffff; // nop
10'h029: pm_insn_o <= 16'h5100; // in2 r1 ; get status flags from UART
10'h02a: pm_insn_o <= 16'h2112; // and r1,r2,r1 ; zero flag set if no TX slot available
10'h02b: pm_insn_o <= 16'h8229; // jmpz putc_waitidle
10'h02c: pm_insn_o <= 16'hffff; // nop
10'h02d: pm_insn_o <= 16'h4100; // set #0x0,r1 ; Output register of UART
10'h02e: pm_insn_o <= 16'h9010; // out0 r1 ; Address for TX transmit reg
10'h02f: pm_insn_o <= 16'h9100; // out1 r0 ; Transmit character
10'h030: pm_insn_o <= 16'h8800; // rts
10'h031: pm_insn_o <= 16'h4101; // set #0x1,r1
10'h032: pm_insn_o <= 16'h9010; // out0 r1
10'h033: pm_insn_o <= 16'h4201; // set #0x1,r2 ; UART_RX_IDLE
10'h034: pm_insn_o <= 16'hffff; // nop
10'h035: pm_insn_o <= 16'h5100; // in2 r1
10'h036: pm_insn_o <= 16'h2112; // and r1,r2,r1
10'h037: pm_insn_o <= 16'h8235; // jmpz getc_waitchar
10'h038: pm_insn_o <= 16'hffff; // nop
10'h039: pm_insn_o <= 16'h4100; // set #0x0,r1 ; Address of RX recv reg
10'h03a: pm_insn_o <= 16'h9010; // out0 r1
10'h03b: pm_insn_o <= 16'hffff; // nop
10'h03c: pm_insn_o <= 16'hffff; // nop
10'h03d: pm_insn_o <= 16'h5000; // in2 r0 ; Get character
10'h03e: pm_insn_o <= 16'h4103; // set #0x3,r1 ; ctrl c
10'h03f: pm_insn_o <= 16'h1101; // xor r0,r1,r1
10'h040: pm_insn_o <= 16'h8200; // jmpz restart ; Restart if ctrl c was pressed
10'h041: pm_insn_o <= 16'hffff; // nop
10'h042: pm_insn_o <= 16'h8025; // jmp putc ; Echo character
10'h043: pm_insn_o <= 16'h4101; // set #0x1,r1
10'h044: pm_insn_o <= 16'h9010; // out0 r1
10'h045: pm_insn_o <= 16'h4201; // set #0x1,r2 ; UART_RX_IDLE
10'h046: pm_insn_o <= 16'hffff; // nop
10'h047: pm_insn_o <= 16'h5100; // in2 r1
10'h048: pm_insn_o <= 16'h2112; // and r1,r2,r1
10'h049: pm_insn_o <= 16'h8247; // jmpz getc_quiet_waitchar
10'h04a: pm_insn_o <= 16'hffff; // nop
10'h04b: pm_insn_o <= 16'h4100; // set #0x0,r1 ; Address of RX recv reg
10'h04c: pm_insn_o <= 16'h9010; // out0 r1
10'h04d: pm_insn_o <= 16'hffff; // nop
10'h04e: pm_insn_o <= 16'hffff; // nop
10'h04f: pm_insn_o <= 16'h5000; // in2 r0 ; Get character
10'h050: pm_insn_o <= 16'h4103; // set #0x3,r1 ; ctrl c
10'h051: pm_insn_o <= 16'h1101; // xor r0,r1,r1
10'h052: pm_insn_o <= 16'h8200; // jmpz restart ; Restart if ctrl c was pressed
10'h053: pm_insn_o <= 16'hffff; // nop
10'h054: pm_insn_o <= 16'h8800; // rts
10'h055: pm_insn_o <= 16'h4101; // set #0x1,r1 ; inc factor
10'h056: pm_insn_o <= 16'h9000; // out0 r0
10'h057: pm_insn_o <= 16'h9140; // out1 r4
10'h058: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h059: pm_insn_o <= 16'h9000; // out0 r0
10'h05a: pm_insn_o <= 16'h9150; // out1 r5
10'h05b: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h05c: pm_insn_o <= 16'h9000; // out0 r0
10'h05d: pm_insn_o <= 16'h9160; // out1 r6
10'h05e: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h05f: pm_insn_o <= 16'h9000; // out0 r0
10'h060: pm_insn_o <= 16'h9170; // out1 r7
10'h061: pm_insn_o <= 16'h8800; // rts
10'h062: pm_insn_o <= 16'h4101; // set #0x01,r1 ; increment constant
10'h063: pm_insn_o <= 16'h9000; // out0 r0
10'h064: pm_insn_o <= 16'hffff; // nop ; Get rid of nop!
10'h065: pm_insn_o <= 16'hffff; // nop
10'h066: pm_insn_o <= 16'h5400; // in2 r4
10'h067: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h068: pm_insn_o <= 16'h9000; // out0 r0
10'h069: pm_insn_o <= 16'hffff; // nop
10'h06a: pm_insn_o <= 16'hffff; // nop
10'h06b: pm_insn_o <= 16'h5500; // in2 r5
10'h06c: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h06d: pm_insn_o <= 16'h9000; // out0 r0
10'h06e: pm_insn_o <= 16'hffff; // nop
10'h06f: pm_insn_o <= 16'hffff; // nop
10'h070: pm_insn_o <= 16'h5600; // in2 r6
10'h071: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h072: pm_insn_o <= 16'h9000; // out0 r0
10'h073: pm_insn_o <= 16'hffff; // nop
10'h074: pm_insn_o <= 16'hffff; // nop
10'h075: pm_insn_o <= 16'h5700; // in2 r7
10'h076: pm_insn_o <= 16'h8800; // rts
10'h077: pm_insn_o <= 16'h8643; // jsr getc_quiet
10'h078: pm_insn_o <= 16'h41d0; // set #0xd0,r1 ; 0x100 - 0x30
10'h079: pm_insn_o <= 16'h0101; // add r0,r1,r1
10'h07a: pm_insn_o <= 16'h847f; // jmpc convascii_ge0 ; jump if greater or equal to '0'
10'h07b: pm_insn_o <= 16'hffff; // nop
10'h07c: pm_insn_o <= 16'h4007; // set #0x7,r0 ; ctrl g
10'h07d: pm_insn_o <= 16'h8625; // jsr putc
10'h07e: pm_insn_o <= 16'h8077; // jmp getnibble ; restart nibbleloop
10'h07f: pm_insn_o <= 16'h41c6; // set #0xc6,r1 ; 0x100 - 0x39
10'h080: pm_insn_o <= 16'h0101; // add r0,r1,r1
10'h081: pm_insn_o <= 16'h8486; // jmpc convascii_gt9
10'h082: pm_insn_o <= 16'hffff; // nop
10'h083: pm_insn_o <= 16'h41d0; // set #0xd0,r1 ; -0x30
10'h084: pm_insn_o <= 16'h0301; // add r0,r1,r3 ; result in r3
10'h085: pm_insn_o <= 16'h8025; // jmp putc ; jump to putc to end it all
10'h086: pm_insn_o <= 16'h419f; // set #0x9f,r1 ; 0x100 - 0x61 ('a')
10'h087: pm_insn_o <= 16'h0101; // add r0,r1,r1
10'h088: pm_insn_o <= 16'h848d; // jmpc convascii_gea ; Value is larger than or equal to 'a'
10'h089: pm_insn_o <= 16'hffff; // nop
10'h08a: pm_insn_o <= 16'h4007; // set #0x7,r0 ; ctrl g
10'h08b: pm_insn_o <= 16'h8625; // jsr putc
10'h08c: pm_insn_o <= 16'h8077; // jmp getnibble ; restart nibbleloop
10'h08d: pm_insn_o <= 16'h4199; // set #0x99,r1; 0x100 - 0x66 - 1 (0x66 = 'f')
10'h08e: pm_insn_o <= 16'h0101; // add r0,r1,r1
10'h08f: pm_insn_o <= 16'h8494; // jmpc invalidchar
10'h090: pm_insn_o <= 16'hffff; // nop
10'h091: pm_insn_o <= 16'h41a9; // set #0xa9,r1 ; -0x61+0xa
10'h092: pm_insn_o <= 16'h0301; // add r0,r1,r3 ; result in r3
10'h093: pm_insn_o <= 16'h8025; // jmp putc
10'h094: pm_insn_o <= 16'h4007; // set #0x7,r0
10'h095: pm_insn_o <= 16'h8625; // jsr putc
10'h096: pm_insn_o <= 16'h8077; // jmp getnibble
10'h097: pm_insn_o <= 16'h420f; // set #0xf,r2 ; Mask out LSB nibble
10'h098: pm_insn_o <= 16'h2202; // and r0,r2,r2
10'h099: pm_insn_o <= 16'h43f6; // set #0xf6,r3
10'h09a: pm_insn_o <= 16'h0323; // add r2,r3,r3
10'h09b: pm_insn_o <= 16'h84a0; // jmpc convnibble_lsb_gtten ; Jump if r2 greater than 9
10'h09c: pm_insn_o <= 16'hffff; // nop
10'h09d: pm_insn_o <= 16'h4330; // set #0x30,r3 ; '0'
10'h09e: pm_insn_o <= 16'h0123; // add r2,r3,r1 ; convert first nibble into '0'..'9'
10'h09f: pm_insn_o <= 16'h80a2; // jmp convnibble_msb
10'h0a0: pm_insn_o <= 16'h4357; // set #0x57,r3 ; 'a'
10'h0a1: pm_insn_o <= 16'h0123; // add r2,r3,r1
10'h0a2: pm_insn_o <= 16'h420f; // set #0xf,r2 ; mask out MSB nibble
10'h0a3: pm_insn_o <= 16'h7000; // swap r0,r0
10'h0a4: pm_insn_o <= 16'h2202; // and r0,r2,r2
10'h0a5: pm_insn_o <= 16'h43f6; // set #0xf6,r3
10'h0a6: pm_insn_o <= 16'h0323; // add r2,r3,r3
10'h0a7: pm_insn_o <= 16'h84ac; // jmpc convnibble_msb_gtten
10'h0a8: pm_insn_o <= 16'hffff; // nop
10'h0a9: pm_insn_o <= 16'h4330; // set #0x30,r3 ; '0'
10'h0aa: pm_insn_o <= 16'h0023; // add r2,r3,r0
10'h0ab: pm_insn_o <= 16'h80ae; // jmp convnibble_msb_done
10'h0ac: pm_insn_o <= 16'h4357; // set #0x57,r3 ; 'a'
10'h0ad: pm_insn_o <= 16'h0023; // add r2,r3,r0
10'h0ae: pm_insn_o <= 16'h3311; // or r1,r1,r3 ; move r1 to r3 FIXME - remove the need for this?
10'h0af: pm_insn_o <= 16'h8800; // rts
10'h0b0: pm_insn_o <= 16'h400d; // set #0xd,r0
10'h0b1: pm_insn_o <= 16'h8625; // jsr putc
10'h0b2: pm_insn_o <= 16'h400a; // set #0xa,r0
10'h0b3: pm_insn_o <= 16'h8625; // jsr putc
10'h0b4: pm_insn_o <= 16'h4001; // set #0x1,r0
10'h0b5: pm_insn_o <= 16'h0c0c; // add r0,r12,r12
10'h0b6: pm_insn_o <= 16'h0b0b; // add r0,r11,r11
10'h0b7: pm_insn_o <= 16'h84bb; // jmpc nextrow_carry
10'h0b8: pm_insn_o <= 16'hffff; // nop
10'h0b9: pm_insn_o <= 16'h40ff; // set #0xff,r0
10'h0ba: pm_insn_o <= 16'h0c0c; // add r0,r12,r12
10'h0bb: pm_insn_o <= 16'h4508; // set #0x8,r5
10'h0bc: pm_insn_o <= 16'h4400; // set #0x0,r4
10'h0bd: pm_insn_o <= 16'h155c; // xor r5,r12,r5
10'h0be: pm_insn_o <= 16'h144b; // xor r4,r11,r4
10'h0bf: pm_insn_o <= 16'h3454; // or r5,r4,r4
10'h0c0: pm_insn_o <= 16'h820f; // jmpz menuloop
10'h0c1: pm_insn_o <= 16'hffff; // nop
10'h0c2: pm_insn_o <= 16'h4d00; // set LOW signalinfo,r13
10'h0c3: pm_insn_o <= 16'h4700; // set #0x0,r7
10'h0c4: pm_insn_o <= 16'h4600; // set #0x0,r6
10'h0c5: pm_insn_o <= 16'h4500; // set #0x0,r5
10'h0c6: pm_insn_o <= 16'h4414; // set #0x14,r4
10'h0c7: pm_insn_o <= 16'h8730; // jsr setwbaddr
10'h0c8: pm_insn_o <= 16'h35cc; // or r12,r12,r5
10'h0c9: pm_insn_o <= 16'h34bb; // or r11,r11,r4
10'h0ca: pm_insn_o <= 16'h8732; // jsr setwbdata
10'h0cb: pm_insn_o <= 16'h872b; // jsr write_to_wb
10'h0cc: pm_insn_o <= 16'h80d3; // jmp handle_logicanalyzer_mainloop
10'h0cd: pm_insn_o <= 16'h4300; // set LOW signalnames,r3
10'h0ce: pm_insn_o <= 16'h4406; // set HIGH signalnames,r4
10'h0cf: pm_insn_o <= 16'h87d3; // jsr puts
10'h0d0: pm_insn_o <= 16'h4b00; // set #0x0,r11
10'h0d1: pm_insn_o <= 16'h4c00; // set #0x0,r12 ; Entry to display...
10'h0d2: pm_insn_o <= 16'h80c2; // jmp nextrow_setup
10'h0d3: pm_insn_o <= 16'h4009; // set #0x9,r0 ; tab
10'h0d4: pm_insn_o <= 16'h8625; // jsr putc
10'h0d5: pm_insn_o <= 16'h4104; // set HIGH signalinfo,r1
10'h0d6: pm_insn_o <= 16'h6e1d; // ld r1,r13,r14
10'h0d7: pm_insn_o <= 16'h6e1d; // ld r1,r13,r14
10'h0d8: pm_insn_o <= 16'h4001; // set #0x1,r0
10'h0d9: pm_insn_o <= 16'h0d0d; // add r0,r13,r13
10'h0da: pm_insn_o <= 16'h6f1d; // ld r1,r13,r15
10'h0db: pm_insn_o <= 16'h6f1d; // ld r1,r13,r15
10'h0dc: pm_insn_o <= 16'h0d0d; // add r0,r13,r13
10'h0dd: pm_insn_o <= 16'h3eee; // or r14,r14,r14
10'h0de: pm_insn_o <= 16'h82b0; // jmpz logicanalyzer_nextrow ; Finished (well, not really...)
10'h0df: pm_insn_o <= 16'hffff; // nop
10'h0e0: pm_insn_o <= 16'h4900; // set #0x0,r9
10'h0e1: pm_insn_o <= 16'h38ff; // or r15,r15,r8
10'h0e2: pm_insn_o <= 16'h8702; // jsr getbit_from_analyzer
10'h0e3: pm_insn_o <= 16'h0999; // add r9,r9,r9
10'h0e4: pm_insn_o <= 16'h3989; // or r8,r9,r9
10'h0e5: pm_insn_o <= 16'h40ff; // set #0xff,r0
10'h0e6: pm_insn_o <= 16'h0f0f; // add r0,r15,r15
10'h0e7: pm_insn_o <= 16'h0e0e; // add r0,r14,r14
10'h0e8: pm_insn_o <= 16'h4003; // set #0x3,r0
10'h0e9: pm_insn_o <= 16'h200e; // and r0,r14,r0
10'h0ea: pm_insn_o <= 16'h82f0; // jmpz logicloop_printnibble
10'h0eb: pm_insn_o <= 16'hffff; // nop
10'h0ec: pm_insn_o <= 16'h3eee; // or r14,r14,r14
10'h0ed: pm_insn_o <= 16'h82d3; // jmpz handle_logicanalyzer_mainloop
10'h0ee: pm_insn_o <= 16'hffff; // nop
10'h0ef: pm_insn_o <= 16'h80e1; // jmp logicloop
10'h0f0: pm_insn_o <= 16'h3099; // or r9,r9,r0
10'h0f1: pm_insn_o <= 16'h8697; // jsr convnibble
10'h0f2: pm_insn_o <= 16'h3033; // or r3,r3,r0
10'h0f3: pm_insn_o <= 16'h8625; // jsr putc
10'h0f4: pm_insn_o <= 16'h4900; // set #0x0,r9
10'h0f5: pm_insn_o <= 16'h80ec; // jmp logicloop_continue
10'h0f6: pm_insn_o <= 16'h4018; // set #0x18,r0
10'h0f7: pm_insn_o <= 16'h9000; // out0 r0
10'h0f8: pm_insn_o <= 16'h45f1; // set #0xf1,r5 ; Read, sel is 0xf
10'h0f9: pm_insn_o <= 16'h9150; // out1 r5
10'h0fa: pm_insn_o <= 16'h8800; // rts
10'h0fb: pm_insn_o <= 16'h4101; // set #0x1,r1
10'h0fc: pm_insn_o <= 16'h0000; // add r0,r0,r0
10'h0fd: pm_insn_o <= 16'h8500; // jmpc rol1_carry
10'h0fe: pm_insn_o <= 16'hffff; // nop
10'h0ff: pm_insn_o <= 16'h8800; // rts
10'h100: pm_insn_o <= 16'h0001; // add r0,r1,r0
10'h101: pm_insn_o <= 16'h8800; // rts
10'h102: pm_insn_o <= 16'h41e0; // set #0xe0,r1
10'h103: pm_insn_o <= 16'h2081; // and r8,r1,r0 ; r0 contains the address to read from logicanalyzer
10'h104: pm_insn_o <= 16'h86fb; // jsr rol1
10'h105: pm_insn_o <= 16'h86fb; // jsr rol1
10'h106: pm_insn_o <= 16'h86fb; // jsr rol1
10'h107: pm_insn_o <= 16'h0000; // add r0,r0,r0 ; Multiply it with 2
10'h108: pm_insn_o <= 16'h0000; // add r0,r0,r0
10'h109: pm_insn_o <= 16'h4140; // set #0x40,r1
10'h10a: pm_insn_o <= 16'h0401; // add r0,r1,r4 ; Add the offset to logic analyzer port (0x40) to it
10'h10b: pm_insn_o <= 16'h4500; // set #0x0,r5
10'h10c: pm_insn_o <= 16'h4600; // set #0x0,r6
10'h10d: pm_insn_o <= 16'h4700; // set #0x0,r7
10'h10e: pm_insn_o <= 16'h4010; // set #0x10,r0 ; Set wishbone address
10'h10f: pm_insn_o <= 16'h8655; // jsr setport ; r4-r7 -> port 0x10 => wb addr
10'h110: pm_insn_o <= 16'h86f6; // jsr wishbone_do_read
10'h111: pm_insn_o <= 16'h4118; // set #0x18,r1 ; Byte to read
10'h112: pm_insn_o <= 16'h2081; // and r8,r1,r0
10'h113: pm_insn_o <= 16'h86fb; // jsr rol1
10'h114: pm_insn_o <= 16'h86fb; // jsr rol1
10'h115: pm_insn_o <= 16'h86fb; // jsr rol1
10'h116: pm_insn_o <= 16'h86fb; // jsr rol1
10'h117: pm_insn_o <= 16'h86fb; // jsr rol1 ; r0 now contains the byte to read from logicanalyzer
10'h118: pm_insn_o <= 16'h4114; // set #0x14,r1 ; offset to WB master peripheral
10'h119: pm_insn_o <= 16'h0101; // add r0,r1,r1
10'h11a: pm_insn_o <= 16'h9010; // out0 r1
10'h11b: pm_insn_o <= 16'h4107; // set #0x7,r1
10'h11c: pm_insn_o <= 16'h2081; // and r8,r1,r0 ; r0 contains the bitnumber we are interested in
10'h11d: pm_insn_o <= 16'h5800; // in2 r8 ; r8 now contains the byte we are interested in
10'h11e: pm_insn_o <= 16'h43ff; // set #0xff,r3
10'h11f: pm_insn_o <= 16'h4201; // set #0x1,r2 ; mask
10'h120: pm_insn_o <= 16'h3000; // or r0,r0,r0
10'h121: pm_insn_o <= 16'h8326; // jmpz getbit_loopend
10'h122: pm_insn_o <= 16'hffff; // nop
10'h123: pm_insn_o <= 16'h0003; // add r0,r3,r0 ; r0--
10'h124: pm_insn_o <= 16'h0222; // add r2,r2,r2 ; r2 = r2 << 1
10'h125: pm_insn_o <= 16'h8120; // jmp getbit_loopstart
10'h126: pm_insn_o <= 16'h2828; // and r2,r8,r8 ; r8 is now masked
10'h127: pm_insn_o <= 16'h832a; // jmpz getbit_iszero
10'h128: pm_insn_o <= 16'hffff; // nop
10'h129: pm_insn_o <= 16'h4801; // set #0x1,r8
10'h12a: pm_insn_o <= 16'h8800; // rts
10'h12b: pm_insn_o <= 16'h4018; // set #0x18,r0
10'h12c: pm_insn_o <= 16'h41f9; // set #0xf9,r1
10'h12d: pm_insn_o <= 16'h9000; // out0 r0
10'h12e: pm_insn_o <= 16'h9110; // out1 r1
10'h12f: pm_insn_o <= 16'h8800; // rts
10'h130: pm_insn_o <= 16'h4010; // set #0x10,r0
10'h131: pm_insn_o <= 16'h8055; // jmp setport
10'h132: pm_insn_o <= 16'h4014; // set #0x14,r0
10'h133: pm_insn_o <= 16'h8055; // jmp setport
10'h134: pm_insn_o <= 16'h4700; // set #0x0,r7
10'h135: pm_insn_o <= 16'h4600; // set #0x0,r6
10'h136: pm_insn_o <= 16'h4500; // set #0x0,r5
10'h137: pm_insn_o <= 16'h4420; // set #0x20,r4
10'h138: pm_insn_o <= 16'h8730; // jsr setwbaddr
10'h139: pm_insn_o <= 16'h4400; // set #0x0,r4
10'h13a: pm_insn_o <= 16'h8732; // jsr setwbdata
10'h13b: pm_insn_o <= 16'h872b; // jsr write_to_wb ; Stop tracer machine
10'h13c: pm_insn_o <= 16'h4700; // set #0x0,r7
10'h13d: pm_insn_o <= 16'h4600; // set #0x0,r6
10'h13e: pm_insn_o <= 16'h4500; // set #0x0,r5
10'h13f: pm_insn_o <= 16'h4400; // set #0x0,r4
10'h140: pm_insn_o <= 16'h8730; // jsr setwbaddr
10'h141: pm_insn_o <= 16'h4401; // set #0x1,r4
10'h142: pm_insn_o <= 16'h8732; // jsr setwbdata
10'h143: pm_insn_o <= 16'h872b; // jsr write_to_wb
10'h144: pm_insn_o <= 16'h86f6; // jsr wishbone_do_read
10'h145: pm_insn_o <= 16'h4014; // set #0x14,r0
10'h146: pm_insn_o <= 16'h8662; // jsr getport
10'h147: pm_insn_o <= 16'h3444; // or r4,r4,r4
10'h148: pm_insn_o <= 16'h8344; // jmpz handle_trigger_wait
10'h149: pm_insn_o <= 16'h4330; // set LOW triggermessage,r3
10'h14a: pm_insn_o <= 16'h4405; // set HIGH triggermessage,r4
10'h14b: pm_insn_o <= 16'h800e; // jmp greetloop
10'h14c: pm_insn_o <= 16'h4201; // set #0x1,r2
10'h14d: pm_insn_o <= 16'h43ff; // set #0xff,r3
10'h14e: pm_insn_o <= 16'h3000; // or r0,r0,r0
10'h14f: pm_insn_o <= 16'h8354; // jmpz createbitmask_end
10'h150: pm_insn_o <= 16'hffff; // nop
10'h151: pm_insn_o <= 16'h0003; // add r0,r3,r0 ; r0--
10'h152: pm_insn_o <= 16'h0222; // add r2,r2,r2 ; r2 = r2 << 1
10'h153: pm_insn_o <= 16'h814e; // jmp createbitmask_loop
10'h154: pm_insn_o <= 16'h8800; // rts
10'h155: pm_insn_o <= 16'h4700; // set #0x00,r7
10'h156: pm_insn_o <= 16'h4600; // set #0x00,r6
10'h157: pm_insn_o <= 16'h4500; // set #0x00,r5
10'h158: pm_insn_o <= 16'h34bb; // or r11,r11,r4
10'h159: pm_insn_o <= 16'h41e0; // set #0xe0,r1
10'h15a: pm_insn_o <= 16'h2081; // and r8,r1,r0
10'h15b: pm_insn_o <= 16'h86fb; // jsr rol1
10'h15c: pm_insn_o <= 16'h86fb; // jsr rol1
10'h15d: pm_insn_o <= 16'h86fb; // jsr rol1
10'h15e: pm_insn_o <= 16'h0000; // add r0,r0,r0
10'h15f: pm_insn_o <= 16'h0000; // add r0,r0,r0
10'h160: pm_insn_o <= 16'h0404; // add r0,r4,r4 ; r7-r4 now contains WB word for matchbit
10'h161: pm_insn_o <= 16'h8730; // jsr setwbaddr
10'h162: pm_insn_o <= 16'h86f6; // jsr wishbone_do_read
10'h163: pm_insn_o <= 16'h4118; // set #0x18,r1 ; Byte to read
10'h164: pm_insn_o <= 16'h2081; // and r8,r1,r0
10'h165: pm_insn_o <= 16'h86fb; // jsr rol1
10'h166: pm_insn_o <= 16'h86fb; // jsr rol1
10'h167: pm_insn_o <= 16'h86fb; // jsr rol1
10'h168: pm_insn_o <= 16'h86fb; // jsr rol1
10'h169: pm_insn_o <= 16'h86fb; // jsr rol1 ; r0 now contains the byte to read from logicanalyzer
10'h16a: pm_insn_o <= 16'h4114; // set #0x14,r1 ; offset to WB master peripheral
10'h16b: pm_insn_o <= 16'h0a01; // add r0,r1,r10 ; Save port offset in r10
10'h16c: pm_insn_o <= 16'h90a0; // out0 r10
10'h16d: pm_insn_o <= 16'h5400; // in2 r4 ; r4 contains the byte we want to mask
10'h16e: pm_insn_o <= 16'h4107; // set #0x7,r1
10'h16f: pm_insn_o <= 16'h2081; // and r8,r1,r0 ; r0 contains the bitnumber we are interested in
10'h170: pm_insn_o <= 16'h874c; // jsr createbitmask
10'h171: pm_insn_o <= 16'h43ff; // set #0xff,r3
10'h172: pm_insn_o <= 16'h1323; // xor r2,r3,r3 ; r3 now contains inverted mask for anding
10'h173: pm_insn_o <= 16'h2443; // and r4,r3,r4 ; r4 is now cleared
10'h174: pm_insn_o <= 16'h3999; // or r9,r9,r9 ; set flags
10'h175: pm_insn_o <= 16'h8378; // jmpz setbit_writeback
10'h176: pm_insn_o <= 16'hffff; // nop
10'h177: pm_insn_o <= 16'h3442; // or r4,r2,r4 ; r9 now contains correct byte value
10'h178: pm_insn_o <= 16'h3944; // or r4,r4,r9 ; Save byte in r9
10'h179: pm_insn_o <= 16'h4014; // set #0x14,r0
10'h17a: pm_insn_o <= 16'h8662; // jsr getport ; Read port data
10'h17b: pm_insn_o <= 16'h4014; // set #0x14,r0
10'h17c: pm_insn_o <= 16'h8655; // jsr setport ; Write it back
10'h17d: pm_insn_o <= 16'h90a0; // out0 r10 ; Update this particular byte
10'h17e: pm_insn_o <= 16'h9190; // out1 r9
10'h17f: pm_insn_o <= 16'h812b; // jmp write_to_wb
10'h180: pm_insn_o <= 16'h4300; // set LOW signalnames,r3
10'h181: pm_insn_o <= 16'h4406; // set HIGH signalnames,r4
10'h182: pm_insn_o <= 16'h87d3; // jsr puts
10'h183: pm_insn_o <= 16'h4b00; // set #0x0,r11
10'h184: pm_insn_o <= 16'h4000; // set #0x0,r0
10'h185: pm_insn_o <= 16'h10b0; // xor r11,r0,r0
10'h186: pm_insn_o <= 16'h8390; // jmpz handle_settrigger_setval
10'h187: pm_insn_o <= 16'h400c; // set #0xc,r0
10'h188: pm_insn_o <= 16'h10b0; // xor r11,r0,r0
10'h189: pm_insn_o <= 16'h838b; // jmpz handle_settrigger_setmask
10'h18a: pm_insn_o <= 16'h800f; // jmp menuloop ; Exit handle_settrigger
10'h18b: pm_insn_o <= 16'h4b04; // set #0x4,r11
10'h18c: pm_insn_o <= 16'h4322; // set LOW maskvalstring,r3
10'h18d: pm_insn_o <= 16'h4405; // set HIGH maskvalstring,r4
10'h18e: pm_insn_o <= 16'h87d3; // jsr puts
10'h18f: pm_insn_o <= 16'h8194; // jmp handle_settrigger_main
10'h190: pm_insn_o <= 16'h4314; // set LOW trigvalstring,r3
10'h191: pm_insn_o <= 16'h4405; // set HIGH trigvalstring,r4
10'h192: pm_insn_o <= 16'h87d3; // jsr puts
10'h193: pm_insn_o <= 16'h4b0c; // set #0xc,r11
10'h194: pm_insn_o <= 16'h4d00; // set LOW signalinfo,r13 ;r13 contains pointer to current
10'h195: pm_insn_o <= 16'h4009; // set #0x9,r0 ; '\t'
10'h196: pm_insn_o <= 16'h8625; // jsr putc
10'h197: pm_insn_o <= 16'h4104; // set HIGH signalinfo,r1
10'h198: pm_insn_o <= 16'h6e1d; // ld r1,r13,r14
10'h199: pm_insn_o <= 16'h6e1d; // ld r1,r13,r14 ;r14 contains length of current entry
10'h19a: pm_insn_o <= 16'h3eee; // or r14,r14,r14
10'h19b: pm_insn_o <= 16'h8384; // jmpz handle_settrigger_setvalormask ; No more entry
10'h19c: pm_insn_o <= 16'hffff; // nop
10'h19d: pm_insn_o <= 16'h4001; // set #0x1,r0
10'h19e: pm_insn_o <= 16'h0d0d; // add r0,r13,r13
10'h19f: pm_insn_o <= 16'h6f1d; // ld r1,r13,r15
10'h1a0: pm_insn_o <= 16'h6f1d; // ld r1,r13,r15 ; r15 contains bit offset of current entry
10'h1a1: pm_insn_o <= 16'h0d0d; // add r0,r13,r13 ; r13 points to next entry
10'h1a2: pm_insn_o <= 16'h3eee; // or r14,r14,r14
10'h1a3: pm_insn_o <= 16'h8395; // jmpz handle_settrigger_nextentry ; No more entry
10'h1a4: pm_insn_o <= 16'hffff; // nop
10'h1a5: pm_insn_o <= 16'h8677; // jsr getnibble ; r3 contains input
10'h1a6: pm_insn_o <= 16'h3c33; // or r3,r3,r12
10'h1a7: pm_insn_o <= 16'h4203; // set #0x3,r2
10'h1a8: pm_insn_o <= 16'h222e; // and r2,r14,r2 ; r2 contains length & 3
10'h1a9: pm_insn_o <= 16'h4900; // set #0x0,r9
10'h1aa: pm_insn_o <= 16'h1992; // xor r9,r2,r9 ; (length & 3) == 0 ?
10'h1ab: pm_insn_o <= 16'h83b5; // jmpz handle_settrigger_use4
10'h1ac: pm_insn_o <= 16'h4903; // set #0x3,r9
10'h1ad: pm_insn_o <= 16'h1992; // xor r9,r2,r9 ; (length & 3) == 3 ?
10'h1ae: pm_insn_o <= 16'h83bc; // jmpz handle_settrigger_use3
10'h1af: pm_insn_o <= 16'h4902; // set #0x2,r9
10'h1b0: pm_insn_o <= 16'h1992; // xor r9,r2,r9 ; (length & 3) == 2 ?
10'h1b1: pm_insn_o <= 16'h83c3; // jmpz handle_settrigger_use2
10'h1b2: pm_insn_o <= 16'h4901; // set #0x1,r9
10'h1b3: pm_insn_o <= 16'h1992; // xor r9,r2,r9 ; (length & 3) == 1 ?
10'h1b4: pm_insn_o <= 16'h83ca; // jmpz handle_settrigger_use1
10'h1b5: pm_insn_o <= 16'h4008; // set #0x8,r0
10'h1b6: pm_insn_o <= 16'h290c; // and r0,r12,r9
10'h1b7: pm_insn_o <= 16'h38ff; // or r15,r15,r8
10'h1b8: pm_insn_o <= 16'h8755; // jsr setbit
10'h1b9: pm_insn_o <= 16'h4aff; // set #0xff,r10 ; r10 = -1
10'h1ba: pm_insn_o <= 16'h0eea; // add r14,r10,r14
10'h1bb: pm_insn_o <= 16'h0ffa; // add r15,r10,r15
10'h1bc: pm_insn_o <= 16'h4004; // set #0x4,r0
10'h1bd: pm_insn_o <= 16'h290c; // and r0,r12,r9
10'h1be: pm_insn_o <= 16'h38ff; // or r15,r15,r8
10'h1bf: pm_insn_o <= 16'h8755; // jsr setbit
10'h1c0: pm_insn_o <= 16'h4aff; // set #0xff,r10 ; r10 = -1
10'h1c1: pm_insn_o <= 16'h0eea; // add r14,r10,r14
10'h1c2: pm_insn_o <= 16'h0ffa; // add r15,r10,r15
10'h1c3: pm_insn_o <= 16'h4002; // set #0x2,r0
10'h1c4: pm_insn_o <= 16'h290c; // and r0,r12,r9
10'h1c5: pm_insn_o <= 16'h38ff; // or r15,r15,r8
10'h1c6: pm_insn_o <= 16'h8755; // jsr setbit
10'h1c7: pm_insn_o <= 16'h4aff; // set #0xff,r10 ; r10 = -1
10'h1c8: pm_insn_o <= 16'h0eea; // add r14,r10,r14
10'h1c9: pm_insn_o <= 16'h0ffa; // add r15,r10,r15
10'h1ca: pm_insn_o <= 16'h4001; // set #0x1,r0
10'h1cb: pm_insn_o <= 16'h290c; // and r0,r12,r9
10'h1cc: pm_insn_o <= 16'h38ff; // or r15,r15,r8
10'h1cd: pm_insn_o <= 16'h8755; // jsr setbit
10'h1ce: pm_insn_o <= 16'h4aff; // set #0xff,r10 ; r10 = -1
10'h1cf: pm_insn_o <= 16'h0eea; // add r14,r10,r14
10'h1d0: pm_insn_o <= 16'h0ffa; // add r15,r10,r15
10'h1d1: pm_insn_o <= 16'h81a2; // jmp handle_settrigger_nextnibble
10'h1d2: pm_insn_o <= 16'h800f; // jmp menuloop
10'h1d3: pm_insn_o <= 16'h6043; // ld r4,r3,r0
10'h1d4: pm_insn_o <= 16'h6043; // ld r4,r3,r0
10'h1d5: pm_insn_o <= 16'h3000; // or r0,r0,r0
10'h1d6: pm_insn_o <= 16'h83dc; // jmpz end_puts
10'h1d7: pm_insn_o <= 16'hffff; // nop
10'h1d8: pm_insn_o <= 16'h8625; // jsr putc
10'h1d9: pm_insn_o <= 16'h4001; // set #0x01,r0
10'h1da: pm_insn_o <= 16'h0303; // add r0,r3,r3 ;charptr++
10'h1db: pm_insn_o <= 16'h81d3; // jmp puts
10'h1dc: pm_insn_o <= 16'h8800; // rts
10'h1dd: pm_insn_o <= 16'h0000;
10'h1de: pm_insn_o <= 16'h0000;
10'h1df: pm_insn_o <= 16'h0000;
10'h1e0: pm_insn_o <= 16'h0000;
10'h1e1: pm_insn_o <= 16'h0000;
10'h1e2: pm_insn_o <= 16'h0000;
10'h1e3: pm_insn_o <= 16'h0000;
10'h1e4: pm_insn_o <= 16'h0000;
10'h1e5: pm_insn_o <= 16'h0000;
10'h1e6: pm_insn_o <= 16'h0000;
10'h1e7: pm_insn_o <= 16'h0000;
10'h1e8: pm_insn_o <= 16'h0000;
10'h1e9: pm_insn_o <= 16'h0000;
10'h1ea: pm_insn_o <= 16'h0000;
10'h1eb: pm_insn_o <= 16'h0000;
10'h1ec: pm_insn_o <= 16'h0000;
10'h1ed: pm_insn_o <= 16'h0000;
10'h1ee: pm_insn_o <= 16'h0000;
10'h1ef: pm_insn_o <= 16'h0000;
10'h1f0: pm_insn_o <= 16'h0000;
10'h1f1: pm_insn_o <= 16'h0000;
10'h1f2: pm_insn_o <= 16'h0000;
10'h1f3: pm_insn_o <= 16'h0000;
10'h1f4: pm_insn_o <= 16'h0000;
10'h1f5: pm_insn_o <= 16'h0000;
10'h1f6: pm_insn_o <= 16'h0000;
10'h1f7: pm_insn_o <= 16'h0000;
10'h1f8: pm_insn_o <= 16'h0000;
10'h1f9: pm_insn_o <= 16'h0000;
10'h1fa: pm_insn_o <= 16'h0000;
10'h1fb: pm_insn_o <= 16'h0000;
10'h1fc: pm_insn_o <= 16'h0000;
10'h1fd: pm_insn_o <= 16'h0000;
10'h1fe: pm_insn_o <= 16'h0000;
10'h1ff: pm_insn_o <= 16'h0000;
10'h200: pm_insn_o <= 16'h070e; // dw 0x070e
10'h201: pm_insn_o <= 16'h0807; // dw 0x0807
10'h202: pm_insn_o <= 16'h0000; // dw 0x0000
10'h203: pm_insn_o <= 16'h0000; // dw 0x0000
10'h204: pm_insn_o <= 16'h0000;
10'h205: pm_insn_o <= 16'h0000;
10'h206: pm_insn_o <= 16'h0000;
10'h207: pm_insn_o <= 16'h0000;
10'h208: pm_insn_o <= 16'h0000;
10'h209: pm_insn_o <= 16'h0000;
10'h20a: pm_insn_o <= 16'h0000;
10'h20b: pm_insn_o <= 16'h0000;
10'h20c: pm_insn_o <= 16'h0000;
10'h20d: pm_insn_o <= 16'h0000;
10'h20e: pm_insn_o <= 16'h0000;
10'h20f: pm_insn_o <= 16'h0000;
10'h210: pm_insn_o <= 16'h0000;
10'h211: pm_insn_o <= 16'h0000;
10'h212: pm_insn_o <= 16'h0000;
10'h213: pm_insn_o <= 16'h0000;
10'h214: pm_insn_o <= 16'h0000;
10'h215: pm_insn_o <= 16'h0000;
10'h216: pm_insn_o <= 16'h0000;
10'h217: pm_insn_o <= 16'h0000;
10'h218: pm_insn_o <= 16'h0000;
10'h219: pm_insn_o <= 16'h0000;
10'h21a: pm_insn_o <= 16'h0000;
10'h21b: pm_insn_o <= 16'h0000;
10'h21c: pm_insn_o <= 16'h0000;
10'h21d: pm_insn_o <= 16'h0000;
10'h21e: pm_insn_o <= 16'h0000;
10'h21f: pm_insn_o <= 16'h0000;
10'h220: pm_insn_o <= 16'h0000;
10'h221: pm_insn_o <= 16'h0000;
10'h222: pm_insn_o <= 16'h0000;
10'h223: pm_insn_o <= 16'h0000;
10'h224: pm_insn_o <= 16'h0000;
10'h225: pm_insn_o <= 16'h0000;
10'h226: pm_insn_o <= 16'h0000;
10'h227: pm_insn_o <= 16'h0000;
10'h228: pm_insn_o <= 16'h0000;
10'h229: pm_insn_o <= 16'h0000;
10'h22a: pm_insn_o <= 16'h0000;
10'h22b: pm_insn_o <= 16'h0000;
10'h22c: pm_insn_o <= 16'h0000;
10'h22d: pm_insn_o <= 16'h0000;
10'h22e: pm_insn_o <= 16'h0000;
10'h22f: pm_insn_o <= 16'h0000;
10'h230: pm_insn_o <= 16'h0000;
10'h231: pm_insn_o <= 16'h0000;
10'h232: pm_insn_o <= 16'h0000;
10'h233: pm_insn_o <= 16'h0000;
10'h234: pm_insn_o <= 16'h0000;
10'h235: pm_insn_o <= 16'h0000;
10'h236: pm_insn_o <= 16'h0000;
10'h237: pm_insn_o <= 16'h0000;
10'h238: pm_insn_o <= 16'h0000;
10'h239: pm_insn_o <= 16'h0000;
10'h23a: pm_insn_o <= 16'h0000;
10'h23b: pm_insn_o <= 16'h0000;
10'h23c: pm_insn_o <= 16'h0000;
10'h23d: pm_insn_o <= 16'h0000;
10'h23e: pm_insn_o <= 16'h0000;
10'h23f: pm_insn_o <= 16'h0000;
10'h240: pm_insn_o <= 16'h0000;
10'h241: pm_insn_o <= 16'h0000;
10'h242: pm_insn_o <= 16'h0000;
10'h243: pm_insn_o <= 16'h0000;
10'h244: pm_insn_o <= 16'h0000;
10'h245: pm_insn_o <= 16'h0000;
10'h246: pm_insn_o <= 16'h0000;
10'h247: pm_insn_o <= 16'h0000;
10'h248: pm_insn_o <= 16'h0000;
10'h249: pm_insn_o <= 16'h0000;
10'h24a: pm_insn_o <= 16'h0000;
10'h24b: pm_insn_o <= 16'h0000;
10'h24c: pm_insn_o <= 16'h0000;
10'h24d: pm_insn_o <= 16'h0000;
10'h24e: pm_insn_o <= 16'h0000;
10'h24f: pm_insn_o <= 16'h0000;
10'h250: pm_insn_o <= 16'h0000;
10'h251: pm_insn_o <= 16'h0000;
10'h252: pm_insn_o <= 16'h0000;
10'h253: pm_insn_o <= 16'h0000;
10'h254: pm_insn_o <= 16'h0000;
10'h255: pm_insn_o <= 16'h0000;
10'h256: pm_insn_o <= 16'h0000;
10'h257: pm_insn_o <= 16'h0000;
10'h258: pm_insn_o <= 16'h0000;
10'h259: pm_insn_o <= 16'h0000;
10'h25a: pm_insn_o <= 16'h0000;
10'h25b: pm_insn_o <= 16'h0000;
10'h25c: pm_insn_o <= 16'h0000;
10'h25d: pm_insn_o <= 16'h0000;
10'h25e: pm_insn_o <= 16'h0000;
10'h25f: pm_insn_o <= 16'h0000;
10'h260: pm_insn_o <= 16'h0000;
10'h261: pm_insn_o <= 16'h0000;
10'h262: pm_insn_o <= 16'h0000;
10'h263: pm_insn_o <= 16'h0000;
10'h264: pm_insn_o <= 16'h0000;
10'h265: pm_insn_o <= 16'h0000;
10'h266: pm_insn_o <= 16'h0000;
10'h267: pm_insn_o <= 16'h0000;
10'h268: pm_insn_o <= 16'h0000;
10'h269: pm_insn_o <= 16'h0000;
10'h26a: pm_insn_o <= 16'h0000;
10'h26b: pm_insn_o <= 16'h0000;
10'h26c: pm_insn_o <= 16'h0000;
10'h26d: pm_insn_o <= 16'h0000;
10'h26e: pm_insn_o <= 16'h0000;
10'h26f: pm_insn_o <= 16'h0000;
10'h270: pm_insn_o <= 16'h0000;
10'h271: pm_insn_o <= 16'h0000;
10'h272: pm_insn_o <= 16'h0000;
10'h273: pm_insn_o <= 16'h0000;
10'h274: pm_insn_o <= 16'h0000;
10'h275: pm_insn_o <= 16'h0000;
10'h276: pm_insn_o <= 16'h0000;
10'h277: pm_insn_o <= 16'h0000;
10'h278: pm_insn_o <= 16'h0000;
10'h279: pm_insn_o <= 16'h0000;
10'h27a: pm_insn_o <= 16'h0000;
10'h27b: pm_insn_o <= 16'h0000;
10'h27c: pm_insn_o <= 16'h0000;
10'h27d: pm_insn_o <= 16'h0000;
10'h27e: pm_insn_o <= 16'h0000;
10'h27f: pm_insn_o <= 16'h0000;
10'h280: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h281: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h282: pm_insn_o <= 16'h2a2a; // dw 0x2a2a ; **
10'h283: pm_insn_o <= 16'h2a20; // dw 0x2a20 ; *
10'h284: pm_insn_o <= 16'h4145; // dw 0x4145 ; AE
10'h285: pm_insn_o <= 16'h2044; // dw 0x2044 ; D
10'h286: pm_insn_o <= 16'h6562; // dw 0x6562 ; eb
10'h287: pm_insn_o <= 16'h7567; // dw 0x7567 ; ug
10'h288: pm_insn_o <= 16'h2049; // dw 0x2049 ; I
10'h289: pm_insn_o <= 16'h4600; // dw 0x4600 ; F\0
10'h28a: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h28b: pm_insn_o <= 16'h5472; // dw 0x5472 ;
10'h28c: pm_insn_o <= 16'h6967; // dw 0x6967
10'h28d: pm_insn_o <= 16'h7661; // dw 0x7661
10'h28e: pm_insn_o <= 16'h6c3a; // dw 0x6c3a
10'h28f: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h290: pm_insn_o <= 16'h0000; // dw 0x0000
10'h291: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h292: pm_insn_o <= 16'h4d61; // dw 0x4d61
10'h293: pm_insn_o <= 16'h736b; // dw 0x736b
10'h294: pm_insn_o <= 16'h7661; // dw 0x7661
10'h295: pm_insn_o <= 16'h6c3a; // dw 0x6c3a
10'h296: pm_insn_o <= 16'h0d0a; // dw 0x0d0a ; \r\n
10'h297: pm_insn_o <= 16'h0000; // dw 0x0000
10'h298: pm_insn_o <= 16'h5761; // dw 0x5761
10'h299: pm_insn_o <= 16'h6974; // dw 0x6974
10'h29a: pm_insn_o <= 16'h696e; // dw 0x696e
10'h29b: pm_insn_o <= 16'h6720; // dw 0x6720
10'h29c: pm_insn_o <= 16'h666f; // dw 0x666f
10'h29d: pm_insn_o <= 16'h7220; // dw 0x7220
10'h29e: pm_insn_o <= 16'h7472; // dw 0x7472
10'h29f: pm_insn_o <= 16'h6967; // dw 0x6967
10'h2a0: pm_insn_o <= 16'h6765; // dw 0x6765
10'h2a1: pm_insn_o <= 16'h722e; // dw 0x722e
10'h2a2: pm_insn_o <= 16'h2e2e; // dw 0x2e2e
10'h2a3: pm_insn_o <= 16'h0d0a; // dw 0x0d0a
10'h2a4: pm_insn_o <= 16'h0000; // dw 0x0000
10'h2a5: pm_insn_o <= 16'h0000;
10'h2a6: pm_insn_o <= 16'h0000;
10'h2a7: pm_insn_o <= 16'h0000;
10'h2a8: pm_insn_o <= 16'h0000;
10'h2a9: pm_insn_o <= 16'h0000;
10'h2aa: pm_insn_o <= 16'h0000;
10'h2ab: pm_insn_o <= 16'h0000;
10'h2ac: pm_insn_o <= 16'h0000;
10'h2ad: pm_insn_o <= 16'h0000;
10'h2ae: pm_insn_o <= 16'h0000;
10'h2af: pm_insn_o <= 16'h0000;
10'h2b0: pm_insn_o <= 16'h0000;
10'h2b1: pm_insn_o <= 16'h0000;
10'h2b2: pm_insn_o <= 16'h0000;
10'h2b3: pm_insn_o <= 16'h0000;
10'h2b4: pm_insn_o <= 16'h0000;
10'h2b5: pm_insn_o <= 16'h0000;
10'h2b6: pm_insn_o <= 16'h0000;
10'h2b7: pm_insn_o <= 16'h0000;
10'h2b8: pm_insn_o <= 16'h0000;
10'h2b9: pm_insn_o <= 16'h0000;
10'h2ba: pm_insn_o <= 16'h0000;
10'h2bb: pm_insn_o <= 16'h0000;
10'h2bc: pm_insn_o <= 16'h0000;
10'h2bd: pm_insn_o <= 16'h0000;
10'h2be: pm_insn_o <= 16'h0000;
10'h2bf: pm_insn_o <= 16'h0000;
10'h2c0: pm_insn_o <= 16'h0000;
10'h2c1: pm_insn_o <= 16'h0000;
10'h2c2: pm_insn_o <= 16'h0000;
10'h2c3: pm_insn_o <= 16'h0000;
10'h2c4: pm_insn_o <= 16'h0000;
10'h2c5: pm_insn_o <= 16'h0000;
10'h2c6: pm_insn_o <= 16'h0000;
10'h2c7: pm_insn_o <= 16'h0000;
10'h2c8: pm_insn_o <= 16'h0000;
10'h2c9: pm_insn_o <= 16'h0000;
10'h2ca: pm_insn_o <= 16'h0000;
10'h2cb: pm_insn_o <= 16'h0000;
10'h2cc: pm_insn_o <= 16'h0000;
10'h2cd: pm_insn_o <= 16'h0000;
10'h2ce: pm_insn_o <= 16'h0000;
10'h2cf: pm_insn_o <= 16'h0000;
10'h2d0: pm_insn_o <= 16'h0000;
10'h2d1: pm_insn_o <= 16'h0000;
10'h2d2: pm_insn_o <= 16'h0000;
10'h2d3: pm_insn_o <= 16'h0000;
10'h2d4: pm_insn_o <= 16'h0000;
10'h2d5: pm_insn_o <= 16'h0000;
10'h2d6: pm_insn_o <= 16'h0000;
10'h2d7: pm_insn_o <= 16'h0000;
10'h2d8: pm_insn_o <= 16'h0000;
10'h2d9: pm_insn_o <= 16'h0000;
10'h2da: pm_insn_o <= 16'h0000;
10'h2db: pm_insn_o <= 16'h0000;
10'h2dc: pm_insn_o <= 16'h0000;
10'h2dd: pm_insn_o <= 16'h0000;
10'h2de: pm_insn_o <= 16'h0000;
10'h2df: pm_insn_o <= 16'h0000;
10'h2e0: pm_insn_o <= 16'h0000;
10'h2e1: pm_insn_o <= 16'h0000;
10'h2e2: pm_insn_o <= 16'h0000;
10'h2e3: pm_insn_o <= 16'h0000;
10'h2e4: pm_insn_o <= 16'h0000;
10'h2e5: pm_insn_o <= 16'h0000;
10'h2e6: pm_insn_o <= 16'h0000;
10'h2e7: pm_insn_o <= 16'h0000;
10'h2e8: pm_insn_o <= 16'h0000;
10'h2e9: pm_insn_o <= 16'h0000;
10'h2ea: pm_insn_o <= 16'h0000;
10'h2eb: pm_insn_o <= 16'h0000;
10'h2ec: pm_insn_o <= 16'h0000;
10'h2ed: pm_insn_o <= 16'h0000;
10'h2ee: pm_insn_o <= 16'h0000;
10'h2ef: pm_insn_o <= 16'h0000;
10'h2f0: pm_insn_o <= 16'h0000;
10'h2f1: pm_insn_o <= 16'h0000;
10'h2f2: pm_insn_o <= 16'h0000;
10'h2f3: pm_insn_o <= 16'h0000;
10'h2f4: pm_insn_o <= 16'h0000;
10'h2f5: pm_insn_o <= 16'h0000;
10'h2f6: pm_insn_o <= 16'h0000;
10'h2f7: pm_insn_o <= 16'h0000;
10'h2f8: pm_insn_o <= 16'h0000;
10'h2f9: pm_insn_o <= 16'h0000;
10'h2fa: pm_insn_o <= 16'h0000;
10'h2fb: pm_insn_o <= 16'h0000;
10'h2fc: pm_insn_o <= 16'h0000;
10'h2fd: pm_insn_o <= 16'h0000;
10'h2fe: pm_insn_o <= 16'h0000;
10'h2ff: pm_insn_o <= 16'h0000;
10'h300: pm_insn_o <= 16'h0d0a; // dw 0x0d0a
10'h301: pm_insn_o <= 16'h4145; // dw 0x4145
10'h302: pm_insn_o <= 16'h0000; // dw 0x0000
10'h303: pm_insn_o <= 16'h0000;
10'h304: pm_insn_o <= 16'h0000;
10'h305: pm_insn_o <= 16'h0000;
10'h306: pm_insn_o <= 16'h0000;
10'h307: pm_insn_o <= 16'h0000;
10'h308: pm_insn_o <= 16'h0000;
10'h309: pm_insn_o <= 16'h0000;
10'h30a: pm_insn_o <= 16'h0000;
10'h30b: pm_insn_o <= 16'h0000;
10'h30c: pm_insn_o <= 16'h0000;
10'h30d: pm_insn_o <= 16'h0000;
10'h30e: pm_insn_o <= 16'h0000;
10'h30f: pm_insn_o <= 16'h0000;
10'h310: pm_insn_o <= 16'h0000;
10'h311: pm_insn_o <= 16'h0000;
10'h312: pm_insn_o <= 16'h0000;
10'h313: pm_insn_o <= 16'h0000;
10'h314: pm_insn_o <= 16'h0000;
10'h315: pm_insn_o <= 16'h0000;
10'h316: pm_insn_o <= 16'h0000;
10'h317: pm_insn_o <= 16'h0000;
10'h318: pm_insn_o <= 16'h0000;
10'h319: pm_insn_o <= 16'h0000;
10'h31a: pm_insn_o <= 16'h0000;
10'h31b: pm_insn_o <= 16'h0000;
10'h31c: pm_insn_o <= 16'h0000;
10'h31d: pm_insn_o <= 16'h0000;
10'h31e: pm_insn_o <= 16'h0000;
10'h31f: pm_insn_o <= 16'h0000;
10'h320: pm_insn_o <= 16'h0000;
10'h321: pm_insn_o <= 16'h0000;
10'h322: pm_insn_o <= 16'h0000;
10'h323: pm_insn_o <= 16'h0000;
10'h324: pm_insn_o <= 16'h0000;
10'h325: pm_insn_o <= 16'h0000;
10'h326: pm_insn_o <= 16'h0000;
10'h327: pm_insn_o <= 16'h0000;
10'h328: pm_insn_o <= 16'h0000;
10'h329: pm_insn_o <= 16'h0000;
10'h32a: pm_insn_o <= 16'h0000;
10'h32b: pm_insn_o <= 16'h0000;
10'h32c: pm_insn_o <= 16'h0000;
10'h32d: pm_insn_o <= 16'h0000;
10'h32e: pm_insn_o <= 16'h0000;
10'h32f: pm_insn_o <= 16'h0000;
10'h330: pm_insn_o <= 16'h0000;
10'h331: pm_insn_o <= 16'h0000;
10'h332: pm_insn_o <= 16'h0000;
10'h333: pm_insn_o <= 16'h0000;
10'h334: pm_insn_o <= 16'h0000;
10'h335: pm_insn_o <= 16'h0000;
10'h336: pm_insn_o <= 16'h0000;
10'h337: pm_insn_o <= 16'h0000;
10'h338: pm_insn_o <= 16'h0000;
10'h339: pm_insn_o <= 16'h0000;
10'h33a: pm_insn_o <= 16'h0000;
10'h33b: pm_insn_o <= 16'h0000;
10'h33c: pm_insn_o <= 16'h0000;
10'h33d: pm_insn_o <= 16'h0000;
10'h33e: pm_insn_o <= 16'h0000;
10'h33f: pm_insn_o <= 16'h0000;
10'h340: pm_insn_o <= 16'h0000;
10'h341: pm_insn_o <= 16'h0000;
10'h342: pm_insn_o <= 16'h0000;
10'h343: pm_insn_o <= 16'h0000;
10'h344: pm_insn_o <= 16'h0000;
10'h345: pm_insn_o <= 16'h0000;
10'h346: pm_insn_o <= 16'h0000;
10'h347: pm_insn_o <= 16'h0000;
10'h348: pm_insn_o <= 16'h0000;
10'h349: pm_insn_o <= 16'h0000;
10'h34a: pm_insn_o <= 16'h0000;
10'h34b: pm_insn_o <= 16'h0000;
10'h34c: pm_insn_o <= 16'h0000;
10'h34d: pm_insn_o <= 16'h0000;
10'h34e: pm_insn_o <= 16'h0000;
10'h34f: pm_insn_o <= 16'h0000;
10'h350: pm_insn_o <= 16'h0000;
10'h351: pm_insn_o <= 16'h0000;
10'h352: pm_insn_o <= 16'h0000;
10'h353: pm_insn_o <= 16'h0000;
10'h354: pm_insn_o <= 16'h0000;
10'h355: pm_insn_o <= 16'h0000;
10'h356: pm_insn_o <= 16'h0000;
10'h357: pm_insn_o <= 16'h0000;
10'h358: pm_insn_o <= 16'h0000;
10'h359: pm_insn_o <= 16'h0000;
10'h35a: pm_insn_o <= 16'h0000;
10'h35b: pm_insn_o <= 16'h0000;
10'h35c: pm_insn_o <= 16'h0000;
10'h35d: pm_insn_o <= 16'h0000;
10'h35e: pm_insn_o <= 16'h0000;
10'h35f: pm_insn_o <= 16'h0000;
10'h360: pm_insn_o <= 16'h0000;
10'h361: pm_insn_o <= 16'h0000;
10'h362: pm_insn_o <= 16'h0000;
10'h363: pm_insn_o <= 16'h0000;
10'h364: pm_insn_o <= 16'h0000;
10'h365: pm_insn_o <= 16'h0000;
10'h366: pm_insn_o <= 16'h0000;
10'h367: pm_insn_o <= 16'h0000;
10'h368: pm_insn_o <= 16'h0000;
10'h369: pm_insn_o <= 16'h0000;
10'h36a: pm_insn_o <= 16'h0000;
10'h36b: pm_insn_o <= 16'h0000;
10'h36c: pm_insn_o <= 16'h0000;
10'h36d: pm_insn_o <= 16'h0000;
10'h36e: pm_insn_o <= 16'h0000;
10'h36f: pm_insn_o <= 16'h0000;
10'h370: pm_insn_o <= 16'h0000;
10'h371: pm_insn_o <= 16'h0000;
10'h372: pm_insn_o <= 16'h0000;
10'h373: pm_insn_o <= 16'h0000;
10'h374: pm_insn_o <= 16'h0000;
10'h375: pm_insn_o <= 16'h0000;
10'h376: pm_insn_o <= 16'h0000;
10'h377: pm_insn_o <= 16'h0000;
10'h378: pm_insn_o <= 16'h0000;
10'h379: pm_insn_o <= 16'h0000;
10'h37a: pm_insn_o <= 16'h0000;
10'h37b: pm_insn_o <= 16'h0000;
10'h37c: pm_insn_o <= 16'h0000;
10'h37d: pm_insn_o <= 16'h0000;
10'h37e: pm_insn_o <= 16'h0000;
10'h37f: pm_insn_o <= 16'h0000;
10'h380: pm_insn_o <= 16'h0000;
10'h381: pm_insn_o <= 16'h0000;
10'h382: pm_insn_o <= 16'h0000;
10'h383: pm_insn_o <= 16'h0000;
10'h384: pm_insn_o <= 16'h0000;
10'h385: pm_insn_o <= 16'h0000;
10'h386: pm_insn_o <= 16'h0000;
10'h387: pm_insn_o <= 16'h0000;
10'h388: pm_insn_o <= 16'h0000;
10'h389: pm_insn_o <= 16'h0000;
10'h38a: pm_insn_o <= 16'h0000;
10'h38b: pm_insn_o <= 16'h0000;
10'h38c: pm_insn_o <= 16'h0000;
10'h38d: pm_insn_o <= 16'h0000;
10'h38e: pm_insn_o <= 16'h0000;
10'h38f: pm_insn_o <= 16'h0000;
10'h390: pm_insn_o <= 16'h0000;
10'h391: pm_insn_o <= 16'h0000;
10'h392: pm_insn_o <= 16'h0000;
10'h393: pm_insn_o <= 16'h0000;
10'h394: pm_insn_o <= 16'h0000;
10'h395: pm_insn_o <= 16'h0000;
10'h396: pm_insn_o <= 16'h0000;
10'h397: pm_insn_o <= 16'h0000;
10'h398: pm_insn_o <= 16'h0000;
10'h399: pm_insn_o <= 16'h0000;
10'h39a: pm_insn_o <= 16'h0000;
10'h39b: pm_insn_o <= 16'h0000;
10'h39c: pm_insn_o <= 16'h0000;
10'h39d: pm_insn_o <= 16'h0000;
10'h39e: pm_insn_o <= 16'h0000;
10'h39f: pm_insn_o <= 16'h0000;
10'h3a0: pm_insn_o <= 16'h0000;
10'h3a1: pm_insn_o <= 16'h0000;
10'h3a2: pm_insn_o <= 16'h0000;
10'h3a3: pm_insn_o <= 16'h0000;
10'h3a4: pm_insn_o <= 16'h0000;
10'h3a5: pm_insn_o <= 16'h0000;
10'h3a6: pm_insn_o <= 16'h0000;
10'h3a7: pm_insn_o <= 16'h0000;
10'h3a8: pm_insn_o <= 16'h0000;
10'h3a9: pm_insn_o <= 16'h0000;
10'h3aa: pm_insn_o <= 16'h0000;
10'h3ab: pm_insn_o <= 16'h0000;
10'h3ac: pm_insn_o <= 16'h0000;
10'h3ad: pm_insn_o <= 16'h0000;
10'h3ae: pm_insn_o <= 16'h0000;
10'h3af: pm_insn_o <= 16'h0000;
10'h3b0: pm_insn_o <= 16'h0000;
10'h3b1: pm_insn_o <= 16'h0000;
10'h3b2: pm_insn_o <= 16'h0000;
10'h3b3: pm_insn_o <= 16'h0000;
10'h3b4: pm_insn_o <= 16'h0000;
10'h3b5: pm_insn_o <= 16'h0000;
10'h3b6: pm_insn_o <= 16'h0000;
10'h3b7: pm_insn_o <= 16'h0000;
10'h3b8: pm_insn_o <= 16'h0000;
10'h3b9: pm_insn_o <= 16'h0000;
10'h3ba: pm_insn_o <= 16'h0000;
10'h3bb: pm_insn_o <= 16'h0000;
10'h3bc: pm_insn_o <= 16'h0000;
10'h3bd: pm_insn_o <= 16'h0000;
10'h3be: pm_insn_o <= 16'h0000;
10'h3bf: pm_insn_o <= 16'h0000;
10'h3c0: pm_insn_o <= 16'h0000;
10'h3c1: pm_insn_o <= 16'h0000;
10'h3c2: pm_insn_o <= 16'h0000;
10'h3c3: pm_insn_o <= 16'h0000;
10'h3c4: pm_insn_o <= 16'h0000;
10'h3c5: pm_insn_o <= 16'h0000;
10'h3c6: pm_insn_o <= 16'h0000;
10'h3c7: pm_insn_o <= 16'h0000;
10'h3c8: pm_insn_o <= 16'h0000;
10'h3c9: pm_insn_o <= 16'h0000;
10'h3ca: pm_insn_o <= 16'h0000;
10'h3cb: pm_insn_o <= 16'h0000;
10'h3cc: pm_insn_o <= 16'h0000;
10'h3cd: pm_insn_o <= 16'h0000;
10'h3ce: pm_insn_o <= 16'h0000;
10'h3cf: pm_insn_o <= 16'h0000;
10'h3d0: pm_insn_o <= 16'h0000;
10'h3d1: pm_insn_o <= 16'h0000;
10'h3d2: pm_insn_o <= 16'h0000;
10'h3d3: pm_insn_o <= 16'h0000;
10'h3d4: pm_insn_o <= 16'h0000;
10'h3d5: pm_insn_o <= 16'h0000;
10'h3d6: pm_insn_o <= 16'h0000;
10'h3d7: pm_insn_o <= 16'h0000;
10'h3d8: pm_insn_o <= 16'h0000;
10'h3d9: pm_insn_o <= 16'h0000;
10'h3da: pm_insn_o <= 16'h0000;
10'h3db: pm_insn_o <= 16'h0000;
10'h3dc: pm_insn_o <= 16'h0000;
10'h3dd: pm_insn_o <= 16'h0000;
10'h3de: pm_insn_o <= 16'h0000;
10'h3df: pm_insn_o <= 16'h0000;
10'h3e0: pm_insn_o <= 16'h0000;
10'h3e1: pm_insn_o <= 16'h0000;
10'h3e2: pm_insn_o <= 16'h0000;
10'h3e3: pm_insn_o <= 16'h0000;
10'h3e4: pm_insn_o <= 16'h0000;
10'h3e5: pm_insn_o <= 16'h0000;
10'h3e6: pm_insn_o <= 16'h0000;
10'h3e7: pm_insn_o <= 16'h0000;
10'h3e8: pm_insn_o <= 16'h0000;
10'h3e9: pm_insn_o <= 16'h0000;
10'h3ea: pm_insn_o <= 16'h0000;
10'h3eb: pm_insn_o <= 16'h0000;
10'h3ec: pm_insn_o <= 16'h0000;
10'h3ed: pm_insn_o <= 16'h0000;
10'h3ee: pm_insn_o <= 16'h0000;
10'h3ef: pm_insn_o <= 16'h0000;
10'h3f0: pm_insn_o <= 16'h0000;
10'h3f1: pm_insn_o <= 16'h0000;
10'h3f2: pm_insn_o <= 16'h0000;
10'h3f3: pm_insn_o <= 16'h0000;
10'h3f4: pm_insn_o <= 16'h0000;
10'h3f5: pm_insn_o <= 16'h0000;
10'h3f6: pm_insn_o <= 16'h0000;
10'h3f7: pm_insn_o <= 16'h0000;
10'h3f8: pm_insn_o <= 16'h0000;
10'h3f9: pm_insn_o <= 16'h0000;
10'h3fa: pm_insn_o <= 16'h0000;
10'h3fb: pm_insn_o <= 16'h0000;
10'h3fc: pm_insn_o <= 16'h0000;
10'h3fd: pm_insn_o <= 16'h0000;
10'h3fe: pm_insn_o <= 16'h0000;
10'h3ff: pm_insn_o <= 16'hab54; // dw 0xab54 ; Just a check intended for tools that automatically poke around inside this memory
default: pm_insn_o <= 16'h0000;
endcase // case(pm_addr_i)
endmodule // serial_wb_program
|
//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.v
// Version: 1.00.a
// Description: User logic module.
// Date: Tue May 02 19:23:30 2017 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
`uselib lib=unisims_ver
`uselib lib=proc_common_v3_00_a
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
in_states,
out_states,
num_reads,
num_writes,
read_ctr,
write_ctr,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Resetn, // Bus to IP reset
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
Bus2IP_RdCE, // Bus to IP read chip enable
Bus2IP_WrCE, // Bus to IP write chip enable
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
IP2Bus_Error // IP to Bus error response
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
input wire [7:0] in_states;
input wire [7:0] out_states;
input wire [31:0] num_reads;
input wire [31:0] num_writes;
input wire [7:0] read_ctr;
input wire [7:0] write_ctr;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data;
input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE;
input [C_NUM_REG-1 : 0] Bus2IP_RdCE;
input [C_NUM_REG-1 : 0] Bus2IP_WrCE;
output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Nets for user logic slave model s/w accessible register example
reg [C_SLV_DWIDTH-1 : 0] slv_reg0;
reg [C_SLV_DWIDTH-1 : 0] slv_reg1;
reg [C_SLV_DWIDTH-1 : 0] slv_reg2;
reg [C_SLV_DWIDTH-1 : 0] slv_reg3;
reg [C_SLV_DWIDTH-1 : 0] slv_reg4;
reg [C_SLV_DWIDTH-1 : 0] slv_reg5;
reg [C_SLV_DWIDTH-1 : 0] slv_reg6;
reg [C_SLV_DWIDTH-1 : 0] slv_reg7;
reg [C_SLV_DWIDTH-1 : 0] slv_reg8;
reg [C_SLV_DWIDTH-1 : 0] slv_reg9;
reg [C_SLV_DWIDTH-1 : 0] slv_reg10;
reg [C_SLV_DWIDTH-1 : 0] slv_reg11;
reg [C_SLV_DWIDTH-1 : 0] slv_reg12;
reg [C_SLV_DWIDTH-1 : 0] slv_reg13;
reg [C_SLV_DWIDTH-1 : 0] slv_reg14;
reg [C_SLV_DWIDTH-1 : 0] slv_reg15;
reg [C_SLV_DWIDTH-1 : 0] slv_reg16;
reg [C_SLV_DWIDTH-1 : 0] slv_reg17;
reg [C_SLV_DWIDTH-1 : 0] slv_reg18;
reg [C_SLV_DWIDTH-1 : 0] slv_reg19;
reg [C_SLV_DWIDTH-1 : 0] slv_reg20;
reg [C_SLV_DWIDTH-1 : 0] slv_reg21;
reg [C_SLV_DWIDTH-1 : 0] slv_reg22;
reg [C_SLV_DWIDTH-1 : 0] slv_reg23;
reg [C_SLV_DWIDTH-1 : 0] slv_reg24;
reg [C_SLV_DWIDTH-1 : 0] slv_reg25;
reg [C_SLV_DWIDTH-1 : 0] slv_reg26;
reg [C_SLV_DWIDTH-1 : 0] slv_reg27;
reg [C_SLV_DWIDTH-1 : 0] slv_reg28;
reg [C_SLV_DWIDTH-1 : 0] slv_reg29;
reg [C_SLV_DWIDTH-1 : 0] slv_reg30;
reg [C_SLV_DWIDTH-1 : 0] slv_reg31;
wire [31 : 0] slv_reg_write_sel;
wire [31 : 0] slv_reg_read_sel;
reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// USER logic implementation added here
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
// Note:
// The example code presented here is to show you one way of reading/writing
// software accessible registers implemented in the user logic slave model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
// to one software accessible register by the top level template. For example,
// if you have four 32 bit software accessible registers in the user logic,
// you are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_sel = Bus2IP_WrCE[31:0],
slv_reg_read_sel = Bus2IP_RdCE[31:0],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15] || Bus2IP_WrCE[16] || Bus2IP_WrCE[17] || Bus2IP_WrCE[18] || Bus2IP_WrCE[19] || Bus2IP_WrCE[20] || Bus2IP_WrCE[21] || Bus2IP_WrCE[22] || Bus2IP_WrCE[23] || Bus2IP_WrCE[24] || Bus2IP_WrCE[25] || Bus2IP_WrCE[26] || Bus2IP_WrCE[27] || Bus2IP_WrCE[28] || Bus2IP_WrCE[29] || Bus2IP_WrCE[30] || Bus2IP_WrCE[31],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15] || Bus2IP_RdCE[16] || Bus2IP_RdCE[17] || Bus2IP_RdCE[18] || Bus2IP_RdCE[19] || Bus2IP_RdCE[20] || Bus2IP_RdCE[21] || Bus2IP_RdCE[22] || Bus2IP_RdCE[23] || Bus2IP_RdCE[24] || Bus2IP_RdCE[25] || Bus2IP_RdCE[26] || Bus2IP_RdCE[27] || Bus2IP_RdCE[28] || Bus2IP_RdCE[29] || Bus2IP_RdCE[30] || Bus2IP_RdCE[31];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin
if ( Bus2IP_Resetn == 1'b0 )
begin
slv_reg0 <= 0;
// slv_reg1 <= 0;
// slv_reg2 <= 0;
// slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
slv_reg16 <= 0;
slv_reg17 <= 0;
slv_reg18 <= 0;
slv_reg19 <= 0;
slv_reg20 <= 0;
slv_reg21 <= 0;
slv_reg22 <= 0;
slv_reg23 <= 0;
slv_reg24 <= 0;
slv_reg25 <= 0;
slv_reg26 <= 0;
slv_reg27 <= 0;
slv_reg28 <= 0;
slv_reg29 <= 0;
slv_reg30 <= 0;
slv_reg31 <= 0;
end
else
case ( slv_reg_write_sel )
32'b10000000000000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
// 32'b01000000000000000000000000000000 :
// for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
// if ( Bus2IP_BE[byte_index] == 1 )
// slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
// 32'b00100000000000000000000000000000 :
// for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
// if ( Bus2IP_BE[byte_index] == 1 )
// slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
// 32'b00010000000000000000000000000000 :
// for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
// if ( Bus2IP_BE[byte_index] == 1 )
// slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00001000000000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000100000000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000010000000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000001000000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000100000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000010000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000001000000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000100000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000010000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000001000000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000100000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg14[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000010000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg15[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000001000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg16[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000100000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg17[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000010000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg18[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000001000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg19[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000100000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg20[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000010000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg21[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000001000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg22[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000100000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg23[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000010000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg24[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000001000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg25[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000100000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg26[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000010000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg27[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000001000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg28[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000000100 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg29[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000000010 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg30[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
32'b00000000000000000000000000000001 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
slv_reg31[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
default : begin
slv_reg0 <= slv_reg0;
// slv_reg1 <= slv_reg1;
// slv_reg2 <= slv_reg2;
// slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;
slv_reg20 <= slv_reg20;
slv_reg21 <= slv_reg21;
slv_reg22 <= slv_reg22;
slv_reg23 <= slv_reg23;
slv_reg24 <= slv_reg24;
slv_reg25 <= slv_reg25;
slv_reg26 <= slv_reg26;
slv_reg27 <= slv_reg27;
slv_reg28 <= slv_reg28;
slv_reg29 <= slv_reg29;
slv_reg30 <= slv_reg30;
slv_reg31 <= slv_reg31;
end
endcase
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 or slv_reg16 or slv_reg17 or slv_reg18 or slv_reg19 or slv_reg20 or slv_reg21 or slv_reg22 or slv_reg23 or slv_reg24 or slv_reg25 or slv_reg26 or slv_reg27 or slv_reg28 or slv_reg29 or slv_reg30 or slv_reg31 )
begin
case ( slv_reg_read_sel )
32'b10000000000000000000000000000000 : slv_ip2bus_data <= slv_reg0;
32'b01000000000000000000000000000000 : slv_ip2bus_data <= slv_reg1;
32'b00100000000000000000000000000000 : slv_ip2bus_data <= slv_reg2;
32'b00010000000000000000000000000000 : slv_ip2bus_data <= slv_reg3;
32'b00001000000000000000000000000000 : slv_ip2bus_data <= slv_reg4;
32'b00000100000000000000000000000000 : slv_ip2bus_data <= slv_reg5;
32'b00000010000000000000000000000000 : slv_ip2bus_data <= slv_reg6;
32'b00000001000000000000000000000000 : slv_ip2bus_data <= slv_reg7;
32'b00000000100000000000000000000000 : slv_ip2bus_data <= slv_reg8;
32'b00000000010000000000000000000000 : slv_ip2bus_data <= slv_reg9;
32'b00000000001000000000000000000000 : slv_ip2bus_data <= slv_reg10;
32'b00000000000100000000000000000000 : slv_ip2bus_data <= slv_reg11;
32'b00000000000010000000000000000000 : slv_ip2bus_data <= slv_reg12;
32'b00000000000001000000000000000000 : slv_ip2bus_data <= slv_reg13;
32'b00000000000000100000000000000000 : slv_ip2bus_data <= slv_reg14;
32'b00000000000000010000000000000000 : slv_ip2bus_data <= slv_reg15;
32'b00000000000000001000000000000000 : slv_ip2bus_data <= slv_reg16;
32'b00000000000000000100000000000000 : slv_ip2bus_data <= slv_reg17;
32'b00000000000000000010000000000000 : slv_ip2bus_data <= slv_reg18;
32'b00000000000000000001000000000000 : slv_ip2bus_data <= slv_reg19;
32'b00000000000000000000100000000000 : slv_ip2bus_data <= slv_reg20;
32'b00000000000000000000010000000000 : slv_ip2bus_data <= slv_reg21;
32'b00000000000000000000001000000000 : slv_ip2bus_data <= slv_reg22;
32'b00000000000000000000000100000000 : slv_ip2bus_data <= slv_reg23;
32'b00000000000000000000000010000000 : slv_ip2bus_data <= slv_reg24;
32'b00000000000000000000000001000000 : slv_ip2bus_data <= slv_reg25;
32'b00000000000000000000000000100000 : slv_ip2bus_data <= slv_reg26;
32'b00000000000000000000000000010000 : slv_ip2bus_data <= slv_reg27;
32'b00000000000000000000000000001000 : slv_ip2bus_data <= slv_reg28;
32'b00000000000000000000000000000100 : slv_ip2bus_data <= slv_reg29;
32'b00000000000000000000000000000010 : slv_ip2bus_data <= slv_reg30;
32'b00000000000000000000000000000001 : slv_ip2bus_data <= slv_reg31;
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ;
assign IP2Bus_WrAck = slv_write_ack;
assign IP2Bus_RdAck = slv_read_ack;
assign IP2Bus_Error = 0;
always @* begin
slv_reg1 <= {in_states, out_states, read_ctr, write_ctr};
slv_reg2 <= num_reads;
slv_reg3 <= num_writes;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_PIO0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
irq,
readdata
)
;
inout [ 4: 0] bidir_port;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 4: 0] bidir_port;
wire clk_en;
reg [ 4: 0] d1_data_in;
reg [ 4: 0] d2_data_in;
reg [ 4: 0] data_dir;
wire [ 4: 0] data_in;
reg [ 4: 0] data_out;
reg [ 4: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 4: 0] edge_detect;
wire irq;
reg [ 4: 0] irq_mask;
wire [ 4: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({5 {(address == 0)}} & data_in) |
({5 {(address == 1)}} & data_dir) |
({5 {(address == 2)}} & irq_mask) |
({5 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[4 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[4 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[4 : 0];
end
assign irq = |(data_in & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
//`include "elink_regmap.v"
module dut(/*AUTOARG*/
// Outputs
dut_active, clkout, wait_out, access_out, packet_out,
// Inputs
clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
);
//##########################################################################
//# INTERFACE
//##########################################################################
parameter AW = 32;
parameter ID = 12'h810;
parameter S_IDW = 12;
parameter M_IDW = 6;
parameter PW = 2*AW + 40;
parameter N = 1;
//clock,reset
input clk1;
input clk2;
input nreset;
input [N*N-1:0] vdd;
input vss;
output dut_active;
output clkout;
//Stimulus Driven Transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//DUT driven transaction
output [N-1:0] access_out;
output [N*PW-1:0] packet_out;
input [N-1:0] wait_in;
//##########################################################################
//#BODY
//##########################################################################
wire mem_rd_wait;
wire mem_wr_wait;
wire mem_access;
wire [PW-1:0] mem_packet;
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
assign clkout = clk1;
assign dut_active = 1'b1;
assign wait_out = 1'b0;
emmu eemu (// Outputs
.reg_rdata (),
.emesh_access_out (access_out),
.emesh_packet_out (packet_out[PW-1:0]),
// Inputs
.nreset (nreset),
.mmu_en (1'b0),
.wr_clk (clk1),
.reg_access (1'b0),
.reg_packet ({(PW){1'b0}}),
.rd_clk (clk1),
.emesh_access_in (access_in),
.emesh_packet_in (packet_in[PW-1:0]),
.emesh_wait_in (wait_in));
endmodule
// Local Variables:
// verilog-library-directories:("." "../hdl")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTP_BEHAVIORAL_PP_V |
//UART FIFO
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1ns/1ps
/*
A custom FIFO that can take multiple bytes in at a time
*/
module uart_fifo (
clk,
rst,
size,
write_strobe,
write_available,
write_data,
read_strobe,
read_count,
read_data,
overflow,
underflow,
full,
empty
);
//parameters
parameter FIFO_SIZE = 10;
input clk;
input rst;
output wire [31:0] size;
input write_strobe;
output wire [31:0] write_available;
input [7:0] write_data;
input read_strobe;
output reg [31:0] read_count;
output wire [7:0] read_data;
output reg overflow;
output reg underflow;
output full;
output empty;
//Wires, Registers
reg [FIFO_SIZE - 1: 0] in_pointer;
reg [FIFO_SIZE - 1: 0] out_pointer;
dual_port_bram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(FIFO_SIZE),
//`ifdef SIMULATION
// .MEM_FILE("mem_file.txt"),
// .MEM_FILE_LENGTH(8)
//`else
.MEM_FILE("NOTHING"),
.MEM_FILE_LENGTH(0)
//`endif
) mem (
.a_clk(clk),
.a_wr(write_strobe),
.a_addr(in_pointer),
.a_din(write_data),
//.a_dout(),
.b_clk(clk),
.b_wr(1'b0),
.b_addr(out_pointer),
.b_din(8'h0),
.b_dout(read_data)
);
//synthesis attribute ram_style of mem is block
wire [FIFO_SIZE - 1: 0] last;
//Asynchronous Logic
assign size = 1 << FIFO_SIZE;
assign last = (out_pointer - 1);
assign full = (in_pointer == last);
assign empty = (read_count == 0);
assign write_available = size - read_count;
integer i;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
read_count <= 0;
in_pointer <= 0;
out_pointer <= 0;
//`ifdef SIMULATION
// read_count <= 8;
// in_pointer <= 8;
//`endif
overflow <= 0;
underflow <= 0;
end
else begin
overflow <= 0;
underflow <= 0;
if (write_strobe) begin
if (full && !read_strobe) begin
//overflow
$display ("UART CONTROLLER: Overflow condition");
out_pointer <= out_pointer + 1;
overflow <= 1;
end
else begin
//not overflow
if (!read_strobe) begin
read_count <= read_count + 1;
end
end
in_pointer <= in_pointer + 1;
end
if (read_strobe) begin
if (empty) begin
//empty
underflow <= 1;
end
else begin
if (full && write_strobe) begin
//check for that very rare condition where the write strobe and the read strobe is begin used at the same time
//and the FIFO is full
overflow <= 0;
end
else begin
if (!write_strobe) begin
read_count <= read_count - 1;
end
out_pointer <= out_pointer + 1;
end
end
end
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
module inject_inst_net_case (
output logic [7:0] q2,
input logic [7:0] d,
input logic clk, rst_n
/*AUTOARG*/);
logic [7:0] Q1;
register2 r2 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Outputs
.q2 (q2[7:0]),
// Inputs
.rst_n (rst_n));
register1 r1 (.q1(Q1), .ck(clk),
/*AUTOINST*/
// Inputs
.d (d[7:0]),
.rst_n (rst_n));
endmodule
module register2 (
output logic [7:0] q2,
input logic [7:0] q1,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q2 <= '0;
else q2 <= q1;
endmodule
module register1 (
output logic [7:0] q1,
input logic [7:0] d,
input logic ck, rst_n
/*AUTOARG*/);
always_ff @(posedge ck or negedge rst_n)
if (!rst_n) q1 <= '0;
else q1 <= d;
endmodule
|
////////////////////////////////////////////////////////////////
// File: vga_sync.v
// Author: BBB (based on Terasic module VGA_Ctrl.v)
// About: Same VGA controller from vga_demo except push button
// logic has been removed and input RGB data added.
////////////////////////////////////////////////////////////////
module vga_sync #(
parameter H_TOTAL_WIDTH = 11,
parameter V_TOTAL_WIDTH = 11,
//0 for active low, 1 for active high
parameter POLARITY = 1'b1,
parameter H_FRONT = 56,
parameter H_SYNC = 120,
parameter H_BACK = 64,
parameter H_ACT = 800,
parameter V_FRONT = 37,
parameter V_SYNC = 6,
parameter V_BACK = 23,
parameter V_ACT = 600
)(
input wire clock,
input wire aresetn,
//Input Data
input wire [9:0] R_in,
input wire [9:0] G_in,
input wire [9:0] B_in,
//Output Control Logic
output wire [(H_TOTAL_WIDTH-1):0] current_x,
output wire [(V_TOTAL_WIDTH-1):0] current_y,
output wire ready,
//Output VGA Signals
output wire vga_clk,
output reg [7:0] R_out,
output reg [7:0] G_out,
output reg [7:0] B_out,
output reg h_sync,
output reg v_sync,
output wire blank_n,
output wire sync_n
);
//Parameters
localparam H_BLANK = H_FRONT+H_SYNC+H_BACK;
localparam H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
localparam V_BLANK = V_FRONT+V_SYNC+V_BACK;
localparam V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
//Internal Signals
reg [(H_TOTAL_WIDTH-1):0] hor_pos;
reg [(V_TOTAL_WIDTH-1):0] ver_pos;
reg is_active_high;
//Check Sync Polarity Type
always @(posedge clock) begin
is_active_high = POLARITY;
end
//Clock
assign vga_clk = ~clock;
//Position Info (External Logic)
assign current_x = (hor_pos >= H_BLANK) ? hor_pos - H_BLANK : 'd0;
assign current_y = (ver_pos >= V_BLANK) ? ver_pos - V_BLANK : 'd0;
//Horizontal Data
always @(posedge clock or negedge aresetn) begin
if (~aresetn)
begin
hor_pos <= 'd0;
h_sync <= is_active_high ? 1'b0 : 1'b1;
end
else
begin
if (hor_pos < H_TOTAL) hor_pos <= hor_pos + 1;
else hor_pos <= 0;
if (hor_pos == H_FRONT-1) h_sync <= is_active_high ? 1'b1 : 1'b0;
if (hor_pos == H_FRONT+H_SYNC-1) h_sync <= is_active_high ? 1'b0 : 1'b1;
end
end
//Vertical Data
always @(posedge h_sync or negedge aresetn) begin
if (~aresetn)
begin
ver_pos <= 'd0;
v_sync <= is_active_high ? 1'b0 : 1'b1;
end
else
begin
if (ver_pos < V_TOTAL) ver_pos <= ver_pos + 1;
else ver_pos <= 0;
if (ver_pos == V_FRONT-1) v_sync <= is_active_high ? 1'b1 : 1'b0;
if (ver_pos == V_FRONT+V_SYNC-1) v_sync <= is_active_high ? 1'b0 : 1'b1;
end
end
//RGB Data
always @(posedge clock or negedge aresetn) begin
if (~aresetn)
begin
R_out <= 8'd0;
B_out <= 8'd0;
G_out <= 8'd0;
end
else if ((hor_pos < H_BLANK) | (ver_pos < V_BLANK))
begin
R_out <= 8'd0;
B_out <= 8'd0;
G_out <= 8'd0;
end
else
begin
R_out <= R_in[9:2];
B_out <= B_in[9:2];
G_out <= G_in[9:2];
end
end
//Blank (ADV7123)
assign blank_n = ~((hor_pos < H_BLANK) | (ver_pos < V_BLANK));
//Sync (ADV7123)
assign sync_n = 1'b1;
//Ready (External Logic)
assign ready = ((hor_pos >= H_BLANK & hor_pos < H_TOTAL) & (ver_pos >= V_BLANK & ver_pos < V_TOTAL));
endmodule
|
// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.1.0.96
// Netlist written on Wed Apr 23 01:04:44 2014
//
// Verilog Description of module Lab2_TekbotRemote_schematic
//
module Lab2_TekbotRemote_schematic (A, B, C, Ld, Le, Rd, Re) /* synthesis syn_module_defined=1 */ ; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(3[8:35])
input A; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(4[8:9])
input B; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(5[8:9])
input C; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(6[8:9])
output Ld; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(7[8:10])
output Le; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(8[8:10])
output Rd; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(9[8:10])
output Re; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(10[8:10])
wire A_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(4[8:9])
wire B_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(5[8:9])
wire C_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(6[8:9])
wire Ld_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(7[8:10])
wire Le_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(8[8:10])
wire Rd_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(9[8:10])
wire Re_c; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(10[8:10])
wire N_16; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(11[6:10])
wire N_17; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(12[6:10])
wire N_11; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(13[6:10])
wire N_12; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(14[6:10])
wire N_13; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(15[6:10])
wire N_14; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(16[6:10])
wire N_15; // c:/lscc/diamond/3.1_x64/bin/nt64/lab2_tekbotremote/lab2_tekbotremote/lab2_tekbotremote_schematic.v(17[6:10])
wire VCC_net, GND_net;
AND2 I14 (.A(N_15), .B(C_c), .Z(N_12)) /* synthesis syn_instantiated=1 */ ;
PUR PUR_INST (.PUR(VCC_net));
defparam PUR_INST.RST_PULSE = 1;
VHI i26 (.Z(VCC_net));
GSR GSR_INST (.GSR(VCC_net));
IB C_pad (.I(C), .O(C_c));
IB B_pad (.I(B), .O(B_c));
IB A_pad (.I(A), .O(A_c));
OB Re_pad (.I(Re_c), .O(Re));
OB Rd_pad (.I(Rd_c), .O(Rd));
OB Le_pad (.I(Le_c), .O(Le));
OB Ld_pad (.I(Ld_c), .O(Ld));
VLO i30 (.Z(GND_net));
OR3 I13 (.A(N_13), .B(N_14), .C(B_c), .Z(Ld_c)) /* synthesis syn_instantiated=1 */ ;
AND2 I15 (.A(N_15), .B(Rd_c), .Z(N_13)) /* synthesis syn_instantiated=1 */ ;
AND2 I16 (.A(A_c), .B(C_c), .Z(N_14)) /* synthesis syn_instantiated=1 */ ;
OR2 I17 (.A(N_12), .B(N_11), .Z(N_16)) /* synthesis syn_instantiated=1 */ ;
OR2 I18 (.A(N_11), .B(N_13), .Z(N_17)) /* synthesis syn_instantiated=1 */ ;
INV I23 (.A(N_16), .Z(Le_c));
INV I24 (.A(N_17), .Z(Re_c));
INV I19 (.A(B_c), .Z(N_11));
INV I20 (.A(C_c), .Z(Rd_c));
INV I21 (.A(A_c), .Z(N_15));
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box.
//
|
module alu_issue_logic
(/*AUTOARG*/
// Outputs
c_issued_valid, c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select, c_simf0_alu_select,
c_simf1_alu_select, c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select, c_issued_wfid,
// Inputs
clk, rst, f_lsu_ready, f_salu_alu_ready, f_simf3_alu_ready,
f_simf2_alu_ready, f_simf1_alu_ready, f_simf0_alu_ready,
f_simd3_alu_ready, f_simd2_alu_ready, f_simd1_alu_ready,
f_simd0_alu_ready, lsu_wf_valid, simd_wf_valid, simf_wf_valid,
salu_wf_valid, lsu_wf_chosen, simd_wf_choosen, simf_wf_choosen,
salu_wf_choosen
);
input clk,rst;
input f_lsu_ready, f_salu_alu_ready,
f_simf3_alu_ready,f_simf2_alu_ready,
f_simf1_alu_ready,f_simf0_alu_ready,
f_simd3_alu_ready,f_simd2_alu_ready,
f_simd1_alu_ready,f_simd0_alu_ready;
input lsu_wf_valid, simd_wf_valid, simf_wf_valid ,salu_wf_valid;
input [`WF_ID_LENGTH-1:0] lsu_wf_chosen, simd_wf_choosen, simf_wf_choosen, salu_wf_choosen;
output c_issued_valid;
output c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
output [`WF_ID_LENGTH-1:0] c_issued_wfid;
reg [`WF_ID_LENGTH-1:0] c_issued_wfid;
wire [1:0] last_fu_selected;
reg [1:0] curr_fu_selected;
reg_param #(2) last_fu(.out(last_fu_selected), .in(curr_fu_selected),
.wr_en(c_issued_valid), .clk(clk), .rst(rst));
reg c_issued_valid;
reg c_simd0_alu_select, c_simd1_alu_select,
c_simd2_alu_select, c_simd3_alu_select,
c_simf0_alu_select, c_simf1_alu_select,
c_simf2_alu_select, c_simf3_alu_select,
c_lsu_lsu_select, c_salu_alu_select;
reg [3:0] fu_ready_shifted, fu_selected_shifted;
reg [3:0] fu_ready_arry, fu_selected_arry;
always @(last_fu_selected or f_lsu_ready
or lsu_wf_chosen or lsu_wf_valid or f_salu_alu_ready
or salu_wf_choosen or salu_wf_valid or f_simd0_alu_ready
or f_simd1_alu_ready or f_simd2_alu_ready or f_simd3_alu_ready
or simd_wf_choosen or simd_wf_valid or f_simf0_alu_ready
or f_simf1_alu_ready or f_simf2_alu_ready or f_simf3_alu_ready
or simf_wf_choosen or simf_wf_valid
or fu_ready_arry or fu_ready_shifted or fu_selected_shifted
or fu_selected_arry) begin
fu_ready_arry <= { (f_simd0_alu_ready | f_simd1_alu_ready | f_simd2_alu_ready |
f_simd3_alu_ready) & simd_wf_valid,
(f_simf0_alu_ready | f_simf1_alu_ready | f_simf2_alu_ready |
f_simf3_alu_ready) & simf_wf_valid,
f_lsu_ready & lsu_wf_valid,
f_salu_alu_ready & salu_wf_valid };
// Select one fu based on round robin between fu classes
case( last_fu_selected )
2'b00 : fu_ready_shifted <= fu_ready_arry;
2'b01 : fu_ready_shifted <= {fu_ready_arry[0], fu_ready_arry[3:1]};
2'b10 : fu_ready_shifted <= {fu_ready_arry[1:0], fu_ready_arry[3:2]};
2'b11 : fu_ready_shifted <= {fu_ready_arry[2:0], fu_ready_arry[3]};
endcase
casex( fu_ready_shifted )
4'b1??? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b1000;
curr_fu_selected <= 2'h3;
end
4'b01?? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0100;
curr_fu_selected <= 2'h2;
end
4'b001? : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0010;
curr_fu_selected <= 2'h1;
end
4'b0001 : begin
fu_selected_shifted <= fu_ready_shifted & 4'b0001;
curr_fu_selected <= 2'h0;
end
default : begin
fu_selected_shifted <= 4'b0000;
curr_fu_selected <= last_fu_selected;
end
endcase // casex ( fu_ready_shifted )
case( last_fu_selected )
2'b00 : fu_selected_arry <= fu_selected_shifted;
2'b01 : fu_selected_arry <= {fu_selected_shifted[2:0], fu_selected_shifted[3]};
2'b10 : fu_selected_arry <= {fu_selected_shifted[1:0], fu_selected_shifted[3:2]};
2'b11 : fu_selected_arry <= {fu_selected_shifted[0], fu_selected_shifted[3:1]};
endcase // case ( last_fu_selected )
// With the class selected, we select the correct alu
casex( { f_simd0_alu_ready,f_simd1_alu_ready,f_simd2_alu_ready,f_simd3_alu_ready} )
4'b1??? : begin
c_simd0_alu_select <= fu_selected_arry[3];
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
4'b01?? : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= fu_selected_arry[3];
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
4'b001? : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= fu_selected_arry[3];
c_simd3_alu_select <= 1'b0;
end
4'b0001 : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= fu_selected_arry[3];
end
default : begin
c_simd0_alu_select <= 1'b0;
c_simd1_alu_select <= 1'b0;
c_simd2_alu_select <= 1'b0;
c_simd3_alu_select <= 1'b0;
end
endcase
casex( { f_simf0_alu_ready,f_simf1_alu_ready,f_simf2_alu_ready,f_simf3_alu_ready} )
4'b1??? : begin
c_simf0_alu_select <= fu_selected_arry[2];
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
4'b01?? : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= fu_selected_arry[2];
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
4'b001? : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= fu_selected_arry[2];
c_simf3_alu_select <= 1'b0;
end
4'b0001 : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= fu_selected_arry[2];
end
default : begin
c_simf0_alu_select <= 1'b0;
c_simf1_alu_select <= 1'b0;
c_simf2_alu_select <= 1'b0;
c_simf3_alu_select <= 1'b0;
end
endcase
c_lsu_lsu_select <= fu_selected_arry[1];
c_salu_alu_select <= fu_selected_arry[0];
// Select the correct wfid
case( fu_selected_arry )
4'b1000 : c_issued_wfid <= simd_wf_choosen;
4'b0100 : c_issued_wfid <= simf_wf_choosen;
4'b0010 : c_issued_wfid <= lsu_wf_chosen;
4'b0001 : c_issued_wfid <= salu_wf_choosen;
default : c_issued_wfid <= {`WF_ID_LENGTH{1'bx}};
endcase // case ( fu_selected_arry )
c_issued_valid <= |fu_selected_arry;
end
endmodule
|
// 32-bit Ripple-Carry Adder
module adder32 (cout,
s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,
a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,
b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15);
input a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15;
input b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15;
output s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15;
output cout; // carry out bit
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15;
assign s0 = a0 ^ b0 ^ 1'b0;
assign c1 = (a0&b0);
assign c2 = (a1&b1)|(a1&c1)|(b1&c1);
assign s1 = a1 ^ b1 ^ c1;
assign c3 = (a2&b2)|(a2&c2)|(b2&c2);
assign s2 = a2 ^ b2 ^ c2;
assign c4 = (a3&b3)|(a3&c3)|(b3&c3);
assign s3 = a3 ^ b3 ^ c3;
assign c5 = (a4&b4)|(a4&c4)|(b4&c4);
assign s4 = a4 ^ b4 ^ c4;
assign c6 = (a5&b5)|(a5&c5)|(b5&c5);
assign s5 = a5 ^ b5 ^ c5;
assign c7 = (a6&b6)|(a6&c6)|(b6&c6);
assign s6 = a6 ^ b6 ^ c6;
assign c8 = (a7&b7)|(a7&c7)|(b7&c7);
assign s7 = a7 ^ b7 ^ c7;
assign c9 = (a8&b8)|(a8&c8)|(b8&c8);
assign s8 = a8 ^ b8 ^ c8;
assign c10 = (a9&b9)|(a9&c9)|(b9&c9);
assign s9 = a9 ^ b9 ^ c9;
assign c11 = (a10&b10)|(a10&c10)|(b10&c10);
assign s10 = a10 ^ b10 ^ c10;
assign c12 = (a11&b11)|(a11&c11)|(b11&c11);
assign s11 = a11 ^ b11 ^ c11;
assign c13 = (a12&b12)|(a12&c12)|(b12&c12);
assign s12 = a12 ^ b12 ^ c12;
assign c14 = (a13&b13)|(a13&c13)|(b13&c13);
assign s13 = a13 ^ b13 ^ c13;
assign c15 = (a14&b14)|(a14&c14)|(b14&c14);
assign s14 = a14 ^ b14 ^ c14;
assign cout = (a15&b15)|(a15&c15)|(b15&c15);
assign s15 = a15 ^ b15 ^ c15;
endmodule
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
//`include "phy.vh"
module mig_7series_v2_3_ddr_byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter RCLK_SELECT_LANE = "B",
parameter PC_CLK_RATIO = 4,
parameter USE_PRE_POST_FIFO = "FALSE",
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "FALSE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SEL_CLK_OFFSET = 0,
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_BYPASS = "FALSE",
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
// OSERDES
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
//IDELAY
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
// local constants, do not pass in from above
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
,parameter CKE_ODT_AUX = "FALSE"
)(
input rst,
input phy_clk,
input freq_refclk,
input mem_refclk,
input idelayctrl_refclk,
input sync_pulse,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
output [11:0] ddr_ck_out,
output rclk,
input if_empty_def,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output pre_fifo_a_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input if_rst,
input [2:0] byte_rd_en_oth_lanes,
input [1:0] byte_rd_en_oth_banks,
output byte_rd_en,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
(PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
(PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
localparam real L_FREQ_REF_PERIOD_NS = TCK > 2500.0 ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0;
localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam PO_DCD_CORRECTION = "ON";
localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? 1 : 0;
localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK > 2500)) ? "001" : "000";
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire iserdes_clk;
wire iserdes_clkdiv;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire po_oserdes_rst;
wire empty_post_fifo;
reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
reg ififo_rst = 1'b1;
reg ofifo_rst = 1'b1;
wire of_wren_pre;
wire [79:0] pre_fifo_dout;
wire pre_fifo_full;
wire pre_fifo_rden;
wire [5:0] ddr_ck_out_q;
wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;
wire oserdes_clkdiv;
wire oserdes_clk_delayed;
wire po_rd_enable;
always @(posedge phy_clk) begin
ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
// reset only data o-fifos on reset of dqs_found
ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
end
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
//assign #(25) phy_rd_en_ = phy_rd_en;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = empty_post_fifo;
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
assign byte_rd_en = 1'b1;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
if_empty_r[0] <= #(025) if_empty_;
if_empty_r[1] <= #(025) if_empty_;
if_empty_r[2] <= #(025) if_empty_;
if_empty_r[3] <= #(025) if_empty_;
end
mig_7series_v2_3_ddr_if_post_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (4), //2 // depth - account for up to 2 cycles of skew
.WIDTH (80) // width
)
u_ddr_if_post_fifo
(
.clk (phy_clk),
.rst (ififo_rst),
.empty_in (if_empty_r),
.rd_en_in (ififo_rd_en_in),
.d_in (rd_data_r),
.empty_out (empty_post_fifo),
.byte_rd_en (byte_rd_en),
.d_out (phy_din)
);
end
else begin : phy_din_gen
assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
assign empty_post_fifo = if_empty_;
end
end
endgenerate
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
generate
if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (9), // depth - set to 9 to accommodate flow control
.WIDTH (80) // width
)
u_ddr_of_pre_fifo
(
.clk (phy_clk),
.rst (ofifo_rst),
.full_in (of_full),
.wr_en_in (phy_wr_en),
.d_in (phy_dout),
.wr_en_out (of_wren_pre),
.d_out (pre_fifo_dout),
.afull (pre_fifo_a_full)
);
end
else begin
// wire direct to ofifo
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
assign of_wren_pre = phy_wr_en;
end
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
else begin
assign pi_dqs_found = 1'b1;
// assign pi_dqs_out_of_range = 1'b0;
assign pi_phase_locked = 1'b1;
end
endgenerate
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
PHASER_OUT_PHY #(
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( 1), // dummy, not used
.PO ( PO_DCD_SETTING ),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (po_oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
generate
if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
IN_FIFO #(
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (if_d0),
.D1 (if_d1),
.D2 (if_d2),
.D3 (if_d3),
.D4 (if_d4),
.D5 ({dummy_i5,if_d5}),
.D6 ({dummy_i6,if_d6}),
.D7 (if_d7),
.D8 (if_d8),
.D9 (if_d9),
.RDCLK (phy_clk),
.RDEN (phy_rd_en_),
.RESET (ififo_rst),
.WRCLK (iserdes_clkdiv),
.WREN (ififo_wr_enable)
);
end
endgenerate
OUT_FIFO #(
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (ofifo_rst),
.WRCLK (phy_clk),
.WREN (of_wren_pre)
);
mig_7series_v2_3_ddr_byte_group_io #
(
.PO_DATA_CTL (PO_DATA_CTL),
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.TCK (TCK),
.SYNTHESIS (SYNTHESIS)
)
ddr_byte_group_io
(
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (po_oserdes_rst),
.iserdes_rst (pi_iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.idelayctrl_refclk (idelayctrl_refclk),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
genvar i;
generate
for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
ddr_ck (
.C (oserdes_clk),
.R (1'b0),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q[i])
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
end // ddr_ck_gen
else begin : ddr_ck_null
assign ddr_ck_out[i*2+1:i*2] = 2'b0;
end
end // ddr_ck_gen_loop
endgenerate
endmodule // byte_lane
|
// This module converts between the valid-ready (input) and
// valid-credit (output) handshakes, by keeping the count of
// available credits
`include "bsg_defines.v"
module bsg_ready_to_credit_flow_converter #( parameter `BSG_INV_PARAM(credit_initial_p )
, parameter `BSG_INV_PARAM(credit_max_val_p )
, parameter decimation_p = 1
//local parameter
, parameter ptr_width_lp =
`BSG_WIDTH(credit_max_val_p)
)
( input clk_i
, input reset_i
, input v_i
, output ready_o
, output v_o
, input credit_i
);
// if toekens are used, up and down values would not be single bits anymore
localparam step_width_lp = `BSG_WIDTH(decimation_p);
logic [step_width_lp-1:0] up,down;
// credit_counter signal
logic [ptr_width_lp-1:0] credit_cnt;
// conversion between valid-credit and valid-credit protocols
// in case of reset, credit_cnt is not zero, so the ready
// and valid signals
assign ready_o = (credit_cnt!=0);
assign v_o = v_i & ready_o;
assign up = credit_i ? step_width_lp'($unsigned(decimation_p)) : step_width_lp'(0);
assign down = {{(step_width_lp-1){1'b0}},v_o};
// counter for credits. When each data is sent it goes down
// by 1 and when it receives a credit acknowledge it goes
// up. If other side of handshake has more buffer it can
// send some credit acknowledges at first to raise the limit
bsg_counter_up_down_variable #( .max_val_p(credit_max_val_p)
, .init_val_p(credit_initial_p)
, .max_step_p(decimation_p)
) credit_counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(up)
, .down_i(down)
, .count_o(credit_cnt)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_ready_to_credit_flow_converter)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test of the export parameter used with modport
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
interface test_if;
// Pre-declare function
extern function myfunc (input logic val);
// Interface variable
logic data;
// Modport
modport mp_e(
export myfunc,
output data
);
// Modport
modport mp_i(
import myfunc,
output data
);
endinterface // test_if
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
test_if i ();
testmod_callee testmod_callee_i (.ie (i.mp_e));
testmod_caller testmod_caller_i (.clk (clk),
.ii (i.mp_i));
endmodule
module testmod_callee
(
test_if.mp_e ie
);
function automatic logic ie.myfunc (input logic val);
begin
myfunc = (val == 1'b0);
end
endfunction
endmodule // testmod_caller
module testmod_caller
(
input clk,
test_if.mp_i ii
);
always @(posedge clk) begin
ii.data = 1'b0;
if (ii.myfunc (1'b0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_core(clock, resetn, dataa, datab, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input valid_in, stall_in;
output valid_out, stall_out;
input enable;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter FINITE_MATH_ONLY = 0;
parameter REMOVE_STICKY = 0;
// Total Latency = 12-7.
wire [26:0] input_a_mantissa;
wire [26:0] input_b_mantissa;
wire input_a_sign, input_b_sign;
wire [8:0] input_a_exponent;
wire [8:0] input_b_exponent;
wire [26:0] left_mantissa;
wire [26:0] right_mantissa;
wire left_sign, right_sign, align_valid_out;
wire [8:0] align_exponent;
wire stall_align;
wire conversion_valid, alignment_stall;
acl_fp_convert_to_internal left(
.clock(clock),
.resetn(resetn),
.data(dataa),
.mantissa(input_a_mantissa),
.exponent(input_a_exponent),
.sign(input_a_sign),
.valid_in(valid_in),
.valid_out(conversion_valid),
.stall_in(alignment_stall),
.stall_out(stall_out),
.enable(enable));
defparam left.HIGH_CAPACITY = HIGH_CAPACITY;
defparam left.FLUSH_DENORMS = FLUSH_DENORMS;
defparam left.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_internal right(
.clock(clock),
.resetn(resetn),
.data(datab),
.mantissa(input_b_mantissa),
.exponent(input_b_exponent),
.sign(input_b_sign),
.valid_in(valid_in),
.valid_out(),
.stall_in(alignment_stall),
.stall_out(),
.enable(enable));
defparam right.HIGH_CAPACITY = HIGH_CAPACITY;
defparam right.FLUSH_DENORMS = FLUSH_DENORMS;
defparam right.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_custom_align alignment(
.clock(clock),
.resetn(resetn),
.input_a_mantissa(input_a_mantissa),
.input_a_exponent(input_a_exponent),
.input_a_sign(input_a_sign),
.input_b_mantissa(input_b_mantissa),
.input_b_exponent(input_b_exponent),
.input_b_sign(input_b_sign),
.left_mantissa(left_mantissa),
.left_exponent(align_exponent),
.left_sign(left_sign),
.right_mantissa(right_mantissa),
.right_exponent(),
.right_sign(right_sign),
.valid_in(conversion_valid),
.valid_out(align_valid_out),
.stall_in(stall_align),
.stall_out(alignment_stall),
.enable(enable));
defparam alignment.HIGH_CAPACITY = HIGH_CAPACITY;
defparam alignment.FLUSH_DENORMS = FLUSH_DENORMS;
defparam alignment.HIGH_LATENCY = HIGH_LATENCY;
defparam alignment.ROUNDING_MODE = ROUNDING_MODE;
defparam alignment.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
defparam alignment.REMOVE_STICKY = REMOVE_STICKY;
wire [27:0] resulting_mantissa;
wire [8:0] resulting_exponent;
wire resulting_sign;
wire valid_sum;
wire stall_sum;
acl_fp_custom_add_op op(
.clock(clock),
.resetn(resetn),
.left_mantissa(left_mantissa),
.right_mantissa(right_mantissa),
.left_sign(left_sign),
.right_sign(right_sign),
.common_exponent(align_exponent),
.resulting_mantissa(resulting_mantissa),
.resulting_exponent(resulting_exponent),
.resulting_sign(resulting_sign),
.valid_in(align_valid_out),
.valid_out(valid_sum),
.stall_in(stall_sum),
.stall_out(stall_align),
.enable(enable));
defparam op.HIGH_CAPACITY = HIGH_CAPACITY;
wire stall_from_norm;
wire [27:0] new_mantissa;
wire [8:0] new_exponent;
wire new_sign, new_valid;
generate
if ((HIGH_CAPACITY==1) && (HIGH_LATENCY==1))
begin
// Staging register.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] mantissa_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [7:0] exponent_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg sign_str;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg staging_valid;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
staging_valid <= 1'b0;
mantissa_str <= 28'bxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
exponent_str <= 8'bxxxxxxxx;
sign_str <= 1'bx;
end
else
begin
if (~stall_from_norm)
staging_valid <= 1'b0;
else if (~staging_valid)
staging_valid <= valid_sum;
if (~staging_valid)
begin
mantissa_str <= resulting_mantissa;
exponent_str <= resulting_exponent;
sign_str <= resulting_sign;
end
end
end
assign new_mantissa = staging_valid ? mantissa_str : resulting_mantissa;
assign new_exponent = staging_valid ? exponent_str : resulting_exponent;
assign new_sign = staging_valid ? sign_str : resulting_sign;
assign new_valid = valid_sum | staging_valid;
assign stall_sum = staging_valid;
end
else
begin
assign new_mantissa = resulting_mantissa;
assign new_exponent = resulting_exponent;
assign new_sign = resulting_sign;
assign new_valid = valid_sum;
assign stall_sum = stall_from_norm;
end
endgenerate
wire rednorm_valid_out, stall_from_round;
wire [26:0] mantissa_norm;
wire [8:0] exponent_norm;
wire sign_norm;
acl_fp_custom_reduced_normalize rednorm(
.clock(clock),
.resetn(resetn),
.mantissa(new_mantissa),
.exponent(new_exponent),
.sign(new_sign),
.stall_in(stall_from_round),
.valid_in(new_valid),
.stall_out(stall_from_norm),
.valid_out(rednorm_valid_out),
.enable(enable),
.mantissa_out(mantissa_norm),
.exponent_out(exponent_norm),
.sign_out(sign_norm));
defparam rednorm.HIGH_CAPACITY = HIGH_CAPACITY;
defparam rednorm.FLUSH_DENORMS = FLUSH_DENORMS;
defparam rednorm.HIGH_LATENCY = HIGH_LATENCY;
defparam rednorm.REMOVE_STICKY = REMOVE_STICKY;
defparam rednorm.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
wire round_valid_out, stall_from_ieee;
wire [26:0] mantissa_round;
wire [8:0] exponent_round;
wire sign_round;
acl_fp_custom_round_post round(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_norm),
.exponent(exponent_norm),
.sign(sign_norm),
.mantissa_out(mantissa_round),
.exponent_out(exponent_round),
.sign_out(sign_round),
.valid_in(rednorm_valid_out),
.valid_out(round_valid_out),
.stall_in(stall_from_ieee),
.stall_out(stall_from_round),
.enable(enable));
defparam round.HIGH_CAPACITY = HIGH_CAPACITY;
defparam round.FLUSH_DENORMS = FLUSH_DENORMS;
defparam round.HIGH_LATENCY = HIGH_LATENCY;
defparam round.ROUNDING_MODE = ROUNDING_MODE;
defparam round.REMOVE_STICKY = REMOVE_STICKY;
defparam round.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
acl_fp_convert_to_ieee toieee(
.clock(clock),
.resetn(resetn),
.mantissa(mantissa_round),
.exponent(exponent_round),
.sign(sign_round),
.result(result),
.valid_in(round_valid_out),
.valid_out(valid_out),
.stall_in(stall_in),
.stall_out(stall_from_ieee),
.enable(enable));
defparam toieee.FINITE_MATH_ONLY = FINITE_MATH_ONLY;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_2_V
`define SKY130_FD_SC_LS__O22A_2_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_2_V
|
module spi_ctrl(
clk,rst_n,sck,mosi,miso,cs_n,spi_tx_en,spi_rx_en,mode_select,receive_status
);
input clk,rst_n,miso;
input mode_select;
output sck,mosi,cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_en;
wire spi_over;
wire receive_status;
wire tran_cs;
reg spi_clk;
reg cs_n;
reg[7:0] clk_count;
reg[7:0] rst_count;
reg rst_flag;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
clk_count <= 8'h0;
spi_clk <= 1'b0;
end
else begin
if(clk_count < 8'd250)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
spi_clk <= ~spi_clk;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cs_n <= 1'b1;
else begin
if(spi_over || ((spi_tx_en == 1'b0) && (spi_rx_en == 1'b0)))
cs_n <= 1'b1;
else
cs_n <= tran_cs;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
rst_flag <= 1'b0;
rst_count <= 'h0;
end
else begin
if(rst_count<8'd20)
rst_count <= rst_count + 1'b1;
else
rst_flag <= 1'b1;
end
end
spi_master spi_master_instance(
.clk(spi_clk),
.rst_n(rst_flag),
.spi_miso(miso),
.spi_mosi(mosi),
.spi_clk(sck),
.spi_tx_en(spi_tx_en),
.spi_over(spi_over),
.spi_rx_en(spi_rx_en),
.mode_select(mode_select),
.receive_status(receive_status),
.cs(tran_cs)
);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A41OI_PP_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : LPDDR2 controller address and command decoder
//
// File : alt_mem_ddrx_lpddr2_addr_cmd.v
//
// Abstract : LPDDR2 Address and command decoder
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_lpddr2_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 20,
CFG_MEM_IF_ROW_WIDTH = 15, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_output_regd,
cfg_enable_chipsel_for_sideband,
// AFI interface (Signals from Arbiter block)
do_write,
do_read,
do_auto_precharge,
do_activate,
do_precharge,
do_precharge_all,
do_refresh,
do_self_refresh,
do_power_down,
do_lmr,
do_lmr_read, //Currently does not exist in arbiter
do_refresh_1bank, //Currently does not exist in arbiter
do_burst_terminate, //Currently does not exist in arbiter
do_deep_pwrdwn, //Currently does not exist in arbiter
// address information
to_chip, // active high input (one hot)
to_bank,
to_row,
to_col,
to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
input cfg_enable_chipsel_for_sideband;
// Arbiter command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_activate;
input do_precharge;
input [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] do_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_power_down;
input [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
input do_lmr;
input do_lmr_read;
input do_refresh_1bank;
input do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] to_col;
input [7:0] to_lmr;
input [7:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_auto_precharge;
wire do_activate;
wire do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
wire do_lmr;
wire do_lmr_read;
wire do_refresh_1bank;
wire do_burst_terminate;
reg [2:0] temp_bank_addr;
reg [14:0] temp_row_addr;
reg [11:0] temp_col_addr;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r;
reg [CFG_MEM_IF_CHIP - 1:0] do_power_down_r;
reg [CFG_MEM_IF_CHIP - 1:0] do_self_refresh_r;
reg [CFG_MEM_IF_CHIP - 1:0] do_deep_pwrdwn_r;
reg [CFG_MEM_IF_CHIP - 1:0] int_do_power_down;
reg [CFG_MEM_IF_CHIP - 1:0] int_do_self_refresh;
reg [CFG_MEM_IF_CHIP - 1:0] int_do_deep_pwrdwn;
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
generate
if (CFG_DWIDTH_RATIO == 2) begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_addr = int_addr;
end
else begin
assign afi_cke = {int_cke,int_cke};
assign afi_cs_n = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
// need half rate code to adjust for half rate cke or cs
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
begin
if (!ctl_reset_n)
begin
do_power_down_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_self_refresh_r <= {(CFG_MEM_IF_CHIP){1'b0}};
do_deep_pwrdwn_r <= {(CFG_MEM_IF_CHIP){1'b0}};
end
else
begin
do_power_down_r <= ~do_power_down;
do_self_refresh_r <= ~do_self_refresh;
do_deep_pwrdwn_r <= ~do_deep_pwrdwn;
end
end
always @(*)
begin
int_do_power_down = do_power_down & do_power_down_r;
int_do_self_refresh = do_self_refresh & do_self_refresh_r;
int_do_deep_pwrdwn = do_deep_pwrdwn & do_deep_pwrdwn_r;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
combi_cke_r <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
combi_cs_n_r <= {CFG_MEM_IF_CHIP{1'b1}} ;
combi_addr_r <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
end
else
begin
combi_cke_r <= combi_cke ;
combi_cs_n_r <= combi_cs_n ;
combi_addr_r <= combi_addr ;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_addr = combi_addr;
end
end
always @ (*)
begin
temp_row_addr = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
temp_col_addr = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
temp_bank_addr = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
temp_row_addr = to_row ;
temp_col_addr = to_col ;
temp_bank_addr = to_bank;
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
always @(*)
begin
if (ctl_cal_success)
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|do_refresh)
begin
combi_cs_n = ~do_refresh;
combi_addr[3:0] = 4'b1100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_refresh_1bank)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_precharge_all)
begin
combi_cs_n = ~do_precharge_all;
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,2'b00,(|do_precharge_all)};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_activate)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = {temp_row_addr[9:8],2'b10};
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_row_addr[12:10]};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_precharge)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,3'b000};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_write)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0001;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (do_read)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0101;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (|int_do_power_down)
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|int_do_deep_pwrdwn)
begin
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~int_do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in deep power down;
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|int_do_self_refresh)
begin
if (cfg_enable_chipsel_for_sideband)
begin
combi_cs_n = ~int_do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in deep power down;
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
end
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_lmr)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],lmr_opcode};
end
if (do_lmr_read)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],{8{1'b0}}};
end
if (do_burst_terminate)
begin
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
end
else
begin
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.03
// \ \ Filename: kcuart_tx.v
// / / Date Last Modified: November 2, 2004
// /___/ /\ Date Created: October 14, 2002
// \ \ / \
// \___\/\___\
//
//Device: Xilinx
//Purpose:
// Constant (K) Compact UART Transmitter
//Reference:
// None
//Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, October 14, 2002
// Rev 1.01 - sus - Converted to verilog, August 4, 2004
// Rev 1.02 - njs - Synplicity attributes added, September 6, 2004
// Rev 1.03 - njs - Fixed simulation attributes from string to hex,
// November 2, 2004
//////////////////////////////////////////////////////////////////////////////////
// Contact: e-mail [email protected]
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// LIMITED WARRANTY AND DISCLAIMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement, or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrant or
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits, cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module kcuart_tx
(data_in,
send_character,
en_16_x_baud,
serial_out,
Tx_complete,
clk);
input [7:0] data_in;
input send_character;
input en_16_x_baud;
output serial_out;
output Tx_complete;
input clk;
//
////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_TX
//
//
////////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////////
//
// wires used in KCUART_TX
//
////////////////////////////////////////////////////////////////////////////////////
//
wire data_01;
wire data_23;
wire data_45;
wire data_67;
wire data_0123;
wire data_4567;
wire data_01234567;
wire [2:0] bit_select;
wire [2:0] next_count;
wire [2:0] mask_count;
wire [2:0] mask_count_carry;
wire [2:0] count_carry;
wire ready_to_start;
wire decode_Tx_start;
wire Tx_start;
wire decode_Tx_run;
wire Tx_run;
wire decode_hot_state;
wire hot_state;
wire hot_delay;
wire Tx_bit;
wire decode_Tx_stop;
wire Tx_stop;
wire decode_Tx_complete;
//
//
////////////////////////////////////////////////////////////////////////////////////
//
// Attributes to define LUT contents during implementation
// The information is repeated in the generic map for functional simulation//
//
////////////////////////////////////////////////////////////////////////////////////
// synthesis attribute init of mux1_lut is "E4FF";
// synthesis attribute init of mux2_lut is "E4FF";
// synthesis attribute init of mux3_lut is "E4FF";
// synthesis attribute init of mux4_lut is "E4FF";
// synthesis attribute init of ready_lut is "10";
// synthesis attribute init of start_lut is "0190";
// synthesis attribute init of run_lut is "1540";
// synthesis attribute init of hot_state_lut is "94";
// synthesis attribute init of delay14_srl is "0000";
// synthesis attribute init of stop_lut is "0180";
// synthesis attribute init of complete_lut is "8";
// synthesis attribute init of count_lut_0 is "8";
// synthesis attribute init of count_lut_1 is "8";
// synthesis attribute init of count_lut_2 is "8";
//
////////////////////////////////////////////////////////////////////////////////////
//
// Start of KCUART_TX circuit description
//
////////////////////////////////////////////////////////////////////////////////////
//
// 8 to 1 multiplexer to convert parallel data to serial
LUT4 mux1_lut
( .I0(bit_select[0]),
.I1(data_in[0]),
.I2(data_in[1]),
.I3(Tx_run),
.O(data_01) )/* synthesis xc_props = "INIT=E4FF"*/;
// synthesis translate_off
defparam mux1_lut.INIT = 16'hE4FF;
// synthesis translate_on
LUT4 mux2_lut
( .I0(bit_select[0]),
.I1(data_in[2]),
.I2(data_in[3]),
.I3(Tx_run),
.O(data_23) )/* synthesis xc_props = "INIT=E4FF"*/;
// synthesis translate_off
defparam mux2_lut.INIT = 16'hE4FF;
// synthesis translate_on
LUT4 mux3_lut
(.I0(bit_select[0]),
.I1(data_in[4]),
.I2(data_in[5]),
.I3(Tx_run),
.O(data_45) )/* synthesis xc_props = "INIT=E4FF"*/;
// synthesis translate_off
defparam mux3_lut.INIT = 16'hE4FF;
// synthesis translate_on
LUT4 mux4_lut
(.I0(bit_select[0]),
.I1(data_in[6]),
.I2(data_in[7]),
.I3(Tx_run),
.O(data_67) )/* synthesis xc_props = "INIT=E4FF"*/;
// synthesis translate_off
defparam mux4_lut.INIT = 16'hE4FF;
// synthesis translate_on
MUXF5 mux5_muxf5
( .I1(data_23),
.I0(data_01),
.S(bit_select[1]),
.O(data_0123) );
MUXF5 mux6_muxf5
( .I1(data_67),
.I0(data_45),
.S(bit_select[1]),
.O(data_4567) );
MUXF6 mux7_muxf6
( .I1(data_4567),
.I0(data_0123),
.S(bit_select[2]),
.O(data_01234567) );
// Register serial output and force start and stop bits
FDRS pipeline_serial
( .D(data_01234567),
.Q(serial_out),
.R(Tx_start),
.S(Tx_stop),
.C(clk) ) ;
// 3-bit counter
// Counter is clock enabled by en_16_x_baud
// Counter will be reset when 'Tx_start' is active
// Counter will increment when Tx_bit is active
// Tx_run must be active to count
// count_carry[2] indicates when terminal count [7] is reached and Tx_bit=1 (ie overflow)
FDRE register_bit_0
(.D(next_count[0]),
.Q(bit_select[0]),
.CE(en_16_x_baud),
.R(Tx_start),
.C(clk) );
LUT2 count_lut_0
(.I0(bit_select[0]),
.I1(Tx_run),
.O(mask_count[0]) )/* synthesis xc_props = "INIT=8"*/;
// synthesis translate_off
defparam count_lut_0.INIT = 4'h8;
// synthesis translate_on
MULT_AND mask_and_0
(.I0(bit_select[0]),
.I1(Tx_run),
.LO(mask_count_carry[0]) );
MUXCY count_muxcy_0
( .DI(mask_count_carry[0]),
.CI(Tx_bit),
.S(mask_count[0]),
.O(count_carry[0]) );
XORCY count_xor_0
(.LI(mask_count[0]),
.CI(Tx_bit),
.O(next_count[0]) );
FDRE register_bit_1
(.D(next_count[1]),
.Q(bit_select[1]),
.CE(en_16_x_baud),
.R(Tx_start),
.C(clk) );
LUT2 count_lut_1
(.I0(bit_select[1]),
.I1(Tx_run),
.O(mask_count[1]) )/* synthesis xc_props = "INIT=8"*/;
// synthesis translate_off
defparam count_lut_1.INIT = 4'h8;
// synthesis translate_on
MULT_AND mask_and_1
( .I0(bit_select[1]),
.I1(Tx_run),
.LO(mask_count_carry[1]) );
MUXCY count_muxcy_1
( .DI(mask_count_carry[1]),
.CI(count_carry[0]),
.S(mask_count[1]),
.O(count_carry[1]) );
XORCY count_xor_1
( .LI(mask_count[1]),
.CI(count_carry[0]),
.O(next_count[1]) );
FDRE register_bit_2
( .D(next_count[2]),
.Q(bit_select[2]),
.CE(en_16_x_baud),
.R(Tx_start),
.C(clk) );
LUT2 count_lut_2
( .I0(bit_select[2]),
.I1(Tx_run),
.O(mask_count[2]) )/* synthesis xc_props = "INIT=8"*/;
// synthesis translate_off
defparam count_lut_2.INIT = 4'h8;
// synthesis translate_on
MULT_AND mask_and_2
( .I0(bit_select[2]),
.I1(Tx_run),
.LO(mask_count_carry[2]) );
MUXCY count_muxcy_2
( .DI(mask_count_carry[2]),
.CI(count_carry[1]),
.S(mask_count[2]) ,
.O(count_carry[2]) );
XORCY count_xor_2
( .LI(mask_count[2]),
.CI(count_carry[1]),
.O(next_count[2]) );
// Ready to start decode
LUT3 ready_lut
( .I0(Tx_run),
.I1(Tx_start),
.I2(send_character),
.O(ready_to_start ) )/* synthesis xc_props = "INIT=10"*/;
// synthesis translate_off
defparam ready_lut.INIT = 8'h10;
// synthesis translate_on
// Start bit enable
LUT4 start_lut
( .I0(Tx_bit),
.I1(Tx_stop),
.I2(ready_to_start),
.I3(Tx_start),
.O(decode_Tx_start ) )/* synthesis xc_props = "INIT=0190"*/;
// synthesis translate_off
defparam start_lut.INIT = 16'h0190;
// synthesis translate_on
FDE Tx_start_reg
( .D(decode_Tx_start),
.Q(Tx_start),
.CE(en_16_x_baud),
.C(clk) );
// Run bit enable
LUT4 run_lut
( .I0(count_carry[2]),
.I1(Tx_bit),
.I2(Tx_start),
.I3(Tx_run),
.O(decode_Tx_run ) )/* synthesis xc_props = "INIT=1540"*/;
// synthesis translate_off
defparam run_lut.INIT = 16'h1540;
// synthesis translate_on
FDE Tx_run_reg
( .D(decode_Tx_run),
.Q(Tx_run),
.CE(en_16_x_baud),
.C(clk) );
// Bit rate enable
LUT3 hot_state_lut
( .I0(Tx_stop),
.I1(ready_to_start),
.I2(Tx_bit),
.O(decode_hot_state) )/* synthesis xc_props = "INIT=94"*/;
// synthesis translate_off
defparam hot_state_lut.INIT = 8'h94;
// synthesis translate_on
FDE hot_state_reg
( .D(decode_hot_state),
.Q(hot_state),
.CE(en_16_x_baud),
.C(clk) );
SRL16E delay14_srl
( .D(hot_state),
.CE(en_16_x_baud),
.CLK(clk),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(hot_delay) )/* synthesis xc_props = "INIT=0000"*/;
// synthesis translate_off
defparam delay14_srl.INIT = 16'h0000;
// synthesis translate_on
FDE Tx_bit_reg
( .D(hot_delay),
.Q(Tx_bit),
.CE(en_16_x_baud),
.C(clk) );
// Stop bit enable
LUT4 stop_lut
( .I0(Tx_bit),
.I1(Tx_run),
.I2(count_carry[2]),
.I3(Tx_stop),
.O(decode_Tx_stop) )/* synthesis xc_props = "INIT=0180"*/;
// synthesis translate_off
defparam stop_lut.INIT = 16'h0180;
// synthesis translate_on
FDE Tx_stop_reg
( .D(decode_Tx_stop),
.Q(Tx_stop),
.CE(en_16_x_baud),
.C(clk) );
// Tx_complete strobe
LUT2 complete_lut
( .I0(count_carry[2]),
.I1(en_16_x_baud),
.O(decode_Tx_complete) )/* synthesis xc_props = "INIT=8"*/;
// synthesis translate_off
defparam complete_lut.INIT = 4'h8;
// synthesis translate_on
FD Tx_complete_reg
( .D(decode_Tx_complete),
.Q(Tx_complete),
.C(clk) );
endmodule
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE KCUART_TX.V
//
////////////////////////////////////////////////////////////////////////////////////
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [127:0] i;
wire [127:0] q1;
wire [127:0] q32;
wire [127:0] q64;
wire [63:0] q64_low;
assign q1 = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1],
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64[127:64] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4],
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q64[63:0] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q64_low = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2],
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
assign q32[127:96] = {
i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4],
i[16*4], i[17*4], i[18*4], i[19*4], i[20*4], i[21*4], i[22*4], i[23*4],
i[8*4], i[9*4], i[10*4], i[11*4], i[12*4], i[13*4], i[14*4], i[15*4],
i[0*4], i[1*4], i[2*4], i[3*4], i[4*4], i[5*4], i[6*4], i[7*4]};
assign q32[95:64] = {
i[24*4+1], i[25*4+1], i[26*4+1], i[27*4+1], i[28*4+1], i[29*4+1], i[30*4+1], i[31*4+1],
i[16*4+1], i[17*4+1], i[18*4+1], i[19*4+1], i[20*4+1], i[21*4+1], i[22*4+1], i[23*4+1],
i[8*4+1], i[9*4+1], i[10*4+1], i[11*4+1], i[12*4+1], i[13*4+1], i[14*4+1], i[15*4+1],
i[0*4+1], i[1*4+1], i[2*4+1], i[3*4+1], i[4*4+1], i[5*4+1], i[6*4+1], i[7*4+1]};
assign q32[63:32] = {
i[24*4+2], i[25*4+2], i[26*4+2], i[27*4+2], i[28*4+2], i[29*4+2], i[30*4+2], i[31*4+2],
i[16*4+2], i[17*4+2], i[18*4+2], i[19*4+2], i[20*4+2], i[21*4+2], i[22*4+2], i[23*4+2],
i[8*4+2], i[9*4+2], i[10*4+2], i[11*4+2], i[12*4+2], i[13*4+2], i[14*4+2], i[15*4+2],
i[0*4+2], i[1*4+2], i[2*4+2], i[3*4+2], i[4*4+2], i[5*4+2], i[6*4+2], i[7*4+2]};
assign q32[31:0] = {
i[24*4+3], i[25*4+3], i[26*4+3], i[27*4+3], i[28*4+3], i[29*4+3], i[30*4+3], i[31*4+3],
i[16*4+3], i[17*4+3], i[18*4+3], i[19*4+3], i[20*4+3], i[21*4+3], i[22*4+3], i[23*4+3],
i[8*4+3], i[9*4+3], i[10*4+3], i[11*4+3], i[12*4+3], i[13*4+3], i[14*4+3], i[15*4+3],
i[0*4+3], i[1*4+3], i[2*4+3], i[3*4+3], i[4*4+3], i[5*4+3], i[6*4+3], i[7*4+3]};
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x %x\n", q1, i);
`endif
if (cyc==1) begin
i <= 128'hed388e646c843d35de489bab2413d770;
end
if (cyc==2) begin
i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3;
if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==3) begin
i <= 128'he236ddfddddbdad20a48e039c9f395b8;
if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==4) begin
i <= 128'h45e0eb7642b148537491f3da147e7f26;
if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop;
if (q1 != q32) $stop;
if (q1 != q64) $stop;
if (q1[63:0] != q64_low) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
module generator(clk, out1, out2, out3, out4, out5, out6,out7,out8);
input wire clk;
output wire out1,out2,out3,out4,out5,out6,out7,out8;
reg [129:0] d1_max; initial d1_max <= 130'd956;
divmod div1(.clk(clk), .max_val(d1_max[ 9: 0]), .out_clk(out1));
divmod div2(.clk(clk), .max_val(d1_max[19:10]), .out_clk(out2));
divmod div3(.clk(clk), .max_val(d1_max[29:20]), .out_clk(out3));
divmod div4(.clk(clk), .max_val(d1_max[39:30]), .out_clk(out4));
divmod div5(.clk(clk), .max_val(d1_max[49:40]), .out_clk(out5));
divmod div6(.clk(clk), .max_val(d1_max[59:50]), .out_clk(out6));
divmod div7(.clk(clk), .max_val(d1_max[69:60]), .out_clk(out7));
divmod div8(.clk(clk), .max_val(d1_max[79:70]), .out_clk(out8));
always @ (posedge clk) d1_max <= d1_max + 1'b1;
//frqdivmod #(.DIV(73)) div1(.clk(clk), .s_out(out1));
//wire reset_div5;
//reg [2:0] div5; initial div5 <= 3'd0;
//assign reset_div5 = div5[2] & !div5[1] & !div5[0];
//
//always @ (posedge clk) begin
// div5 <= (reset_div5) ? 3'd0 : div5 + 1'b1;
//end
//assign out = reset_div5;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o311a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_BEHAVIORAL_PP_V |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module prog_counter2 (out_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] out_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] out_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst==1)
begin
// Set its value to ZERO
out_pc<=32'd0;
end
else
begin
out_pc<=out_pc+32'd4;
end
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream frame length adjuster with FIFO
*/
module axis_frame_length_adjust_fifo #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// Depth of data FIFO in words
parameter FRAME_FIFO_DEPTH = 4096,
// Depth of header FIFO
parameter HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire m_axis_hdr_valid,
input wire m_axis_hdr_ready,
output wire m_axis_hdr_pad,
output wire m_axis_hdr_truncate,
output wire [15:0] m_axis_hdr_length,
output wire [15:0] m_axis_hdr_original_length,
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
wire [DATA_WIDTH-1:0] fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] fifo_axis_tkeep;
wire fifo_axis_tvalid;
wire fifo_axis_tready;
wire fifo_axis_tlast;
wire [ID_WIDTH-1:0] fifo_axis_tid;
wire [DEST_WIDTH-1:0] fifo_axis_tdest;
wire [USER_WIDTH-1:0] fifo_axis_tuser;
wire status_valid;
wire status_ready;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
axis_frame_length_adjust_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(fifo_axis_tdata),
.m_axis_tkeep(fifo_axis_tkeep),
.m_axis_tvalid(fifo_axis_tvalid),
.m_axis_tready(fifo_axis_tready),
.m_axis_tlast(fifo_axis_tlast),
.m_axis_tid(fifo_axis_tid),
.m_axis_tdest(fifo_axis_tdest),
.m_axis_tuser(fifo_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
axis_fifo #(
.DEPTH(FRAME_FIFO_DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO(0)
)
frame_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(fifo_axis_tdata),
.s_axis_tkeep(fifo_axis_tkeep),
.s_axis_tvalid(fifo_axis_tvalid),
.s_axis_tready(fifo_axis_tready),
.s_axis_tlast(fifo_axis_tlast),
.s_axis_tid(fifo_axis_tid),
.s_axis_tdest(fifo_axis_tdest),
.s_axis_tuser(fifo_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
axis_fifo #(
.DEPTH(HEADER_FIFO_DEPTH),
.DATA_WIDTH(1+1+16+16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
header_fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata({status_frame_pad, status_frame_truncate, status_frame_length, status_frame_original_length}),
.s_axis_tkeep(0),
.s_axis_tvalid(status_valid),
.s_axis_tready(status_ready),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata({m_axis_hdr_pad, m_axis_hdr_truncate, m_axis_hdr_length, m_axis_hdr_original_length}),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_hdr_valid),
.m_axis_tready(m_axis_hdr_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_0_V
`define SKY130_FD_SC_LP__A2BB2O_0_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_0 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2o_0 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_0_V
|
module butterfly_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [26:0] i_0;
input signed [26:0] i_1;
input signed [26:0] i_2;
input signed [26:0] i_3;
input signed [26:0] i_4;
input signed [26:0] i_5;
input signed [26:0] i_6;
input signed [26:0] i_7;
input signed [26:0] i_8;
input signed [26:0] i_9;
input signed [26:0] i_10;
input signed [26:0] i_11;
input signed [26:0] i_12;
input signed [26:0] i_13;
input signed [26:0] i_14;
input signed [26:0] i_15;
input signed [26:0] i_16;
input signed [26:0] i_17;
input signed [26:0] i_18;
input signed [26:0] i_19;
input signed [26:0] i_20;
input signed [26:0] i_21;
input signed [26:0] i_22;
input signed [26:0] i_23;
input signed [26:0] i_24;
input signed [26:0] i_25;
input signed [26:0] i_26;
input signed [26:0] i_27;
input signed [26:0] i_28;
input signed [26:0] i_29;
input signed [26:0] i_30;
input signed [26:0] i_31;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
wire signed [27:0] b_16;
wire signed [27:0] b_17;
wire signed [27:0] b_18;
wire signed [27:0] b_19;
wire signed [27:0] b_20;
wire signed [27:0] b_21;
wire signed [27:0] b_22;
wire signed [27:0] b_23;
wire signed [27:0] b_24;
wire signed [27:0] b_25;
wire signed [27:0] b_26;
wire signed [27:0] b_27;
wire signed [27:0] b_28;
wire signed [27:0] b_29;
wire signed [27:0] b_30;
wire signed [27:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule |
////////////////////////////////////////////////////////////////////////////////
// //
// This file is placed into the Public Domain, for any use, without warranty. //
// 2012 by Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// This testbench contains a bus source and a bus drain. The source creates //
// address and data bus values, while the drain is the final destination of //
// such pairs. All source and drain transfers are logged into memories, which //
// are used at the end of simulation to check for data transfer correctness. //
// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they //
// bus transfers into a 8bit data stream and back. Both stream input and //
// output are exposed, they are connected together into a loopback. //
// //
// ----------- --------------------- //
// | bso_mem | | wrap | //
// ----------- | | //
// ----------- | | ----------- | //
// | bsi src | ------------> | -> | mux | -> | -> - sto //
// ----------- | ----------- | \ //
// | | | loopback //
// ----------- | ----------- | / //
// | bso drn | <------------ | <- | demux | <- | <- - sti //
// ----------- | | ----------- | //
// ----------- | | //
// | bso_mem | | | //
// ----------- --------------------- //
// //
// PROTOCOL: //
// //
// The 'vld' signal is driven by the source to indicate valid data is //
// available, 'rdy' is used by the drain to indicate is is ready to accept //
// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. //
// //
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
// include RTL files
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZ = 10;
// system signals
//logic clk = 1'b1; // clock
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// input bus
logic bsi_vld; // valid (chip select)
logic [31:0] bsi_adr; // address
logic [31:0] bsi_dat; // data
logic bsi_rdy; // ready (acknowledge)
logic bsi_trn; // data transfer
logic [31:0] bsi_mem [SIZ];
// output stream
logic sto_vld; // valid (chip select)
logic [7:0] sto_bus; // data bus
logic sto_rdy; // ready (acknowledge)
// input stream
logic sti_vld; // valid (chip select)
logic [7:0] sti_bus; // data bus
logic sti_rdy; // ready (acknowledge)
// output bus
logic bso_vld; // valid (chip select)
logic [31:0] bso_adr; // address
logic [31:0] bso_dat; // data
logic bso_rdy; // ready (acknowledge)
logic bso_trn; // data transfer
logic [31:0] bso_mem [SIZ];
integer bso_cnt = 0;
////////////////////////////////////////////////////////////////////////////////
// clock and reset
////////////////////////////////////////////////////////////////////////////////
// clock toggling
//always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// reset is removed after a delay
always @ (posedge clk)
if (bso_cnt == SIZ) begin
if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end
else begin $display ("FAILED"); $stop(); end
end
////////////////////////////////////////////////////////////////////////////////
// input data generator
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bsi_trn = bsi_vld & bsi_rdy;
// valid (for SIZ transfers)
always @ (posedge clk, posedge rst)
if (rst) bsi_vld = 1'b0;
else bsi_vld = (bsi_adr < SIZ);
// address (increments every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_adr <= 32'h00000000;
else if (bsi_trn) bsi_adr <= bsi_adr + 'd1;
// data (new random value generated after every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_dat <= 32'h00000000;
else if (bsi_trn) bsi_dat <= $random();
// storing transferred data into memory for final check
always @ (posedge clk)
if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat;
////////////////////////////////////////////////////////////////////////////////
// RTL instance
////////////////////////////////////////////////////////////////////////////////
sv_bus_mux_demux_wrap wrap (
// system signals
.clk (clk),
.rst (rst),
// input bus
.bsi_vld (bsi_vld),
.bsi_adr (bsi_adr),
.bsi_dat (bsi_dat),
.bsi_rdy (bsi_rdy),
// output stream
.sto_vld (sto_vld),
.sto_bus (sto_bus),
.sto_rdy (sto_rdy),
// input stream
.sti_vld (sti_vld),
.sti_bus (sti_bus),
.sti_rdy (sti_rdy),
// output bus
.bso_vld (bso_vld),
.bso_adr (bso_adr),
.bso_dat (bso_dat),
.bso_rdy (bso_rdy)
);
// stream output from mux is looped back into stream input for demux
assign sti_vld = sto_vld;
assign sti_bus = sto_bus;
assign sto_rdy = sti_rdy;
////////////////////////////////////////////////////////////////////////////////
// output data monitor
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bso_trn = bso_vld & bso_rdy;
// output transfer counter used to end the test
always @ (posedge clk, posedge rst)
if (rst) bso_cnt <= 0;
else if (bso_trn) bso_cnt <= bso_cnt + 1;
// storing transferred data into memory for final check
always @ (posedge clk)
if (bso_trn) bso_mem [bso_adr] <= bso_dat;
// every output transfer against expected value stored in memory
always @ (posedge clk)
if (bso_trn && (bsi_mem [bso_adr] !== bso_dat))
$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat);
// ready is active for SIZ transfers
always @ (posedge clk, posedge rst)
if (rst) bso_rdy = 1'b0;
else bso_rdy = 1'b1;
endmodule : sv_bus_mux_demux_tb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg signed [64+15:0] data;
integer i;
integer b;
reg signed [64+15:0] srs;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==2) begin
data <= 80'h0;
data[75] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==3) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b==(75-i) || b==(10-i))) $stop;
end
end
end
if (cyc==10) begin
data <= 80'h0;
data[79] <= 1'b1;
data[10] <= 1'b1;
end
if (cyc==12) begin
for (i=0; i<85; i=i+1) begin
srs = data>>>i;
//$write (" %x >>> %d == %x\n",data,i,srs);
for (b=0; b<80; b=b+1) begin
if (srs[b] != (b>=(79-i) || b==(10-i))) $stop;
end
end
end
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_PO_reset for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_PO_reset
// Module Name: NPCG_Toggle_SCC_PO_reset
// File Name: NPCG_Toggle_SCC_PO_reset.v
//
// Version: v1.0.0
//
// Description: NFC phy output module reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_PO_reset
#
(
parameter NumberOfWays = 4
)
(
iSystemClock,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep,
oPM_PCommand
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
wire wModuleTriggered ;
localparam State_Idle = 3'b000;
localparam State_POResetIssue = 3'b001;
localparam State_POWait = 3'b011;
reg [1:0] rCurState ;
reg [1:0] rNextState ;
wire wPOResetTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_POResetIssue:State_Idle;
State_POResetIssue:
rNextState <= (iPM_Ready)?State_POWait:State_POResetIssue;
State_POWait:
rNextState <= (oLastStep)?State_Idle:State_POWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID == 5'b00101 && iOpcode == 6'b110000);
assign oCMDReady = (rCurState == State_Idle);
assign wPOResetTrig = (rCurState == State_POResetIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_POWait) & iPM_LastStep[5];
assign oPM_PCommand = {1'b0, 1'b0, wPOResetTrig, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
endmodule
|
module cclk_detector #(
parameter CLK_RATE = 50000000
)(
input clk,
input rst,
input cclk,
output ready
);
parameter CTR_SIZE = $clog2(CLK_RATE/50000);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg ready_d, ready_q;
assign ready = ready_q;
// ready should only go high once cclk has been high for a while
// if cclk ever falls, ready should go low again
always @(ctr_q or cclk) begin
ready_d = 1'b0;
if (cclk == 1'b0) begin // when cclk is 0 reset the counter
ctr_d = 1'b0;
end else if (ctr_q != {CTR_SIZE{1'b1}}) begin
ctr_d = ctr_q + 1'b1; // counter isn't max value yet
end else begin
ctr_d = ctr_q;
ready_d = 1'b1; // counter reached the max, we are ready
end
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
ready_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
ready_q <= ready_d;
end
end
endmodule
|
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____20.000______0.000______50.0_____1200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary___________50.00____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input clk,
// Clock out ports
output clk_20MHz
);
// Input buffering
//------------------------------------
assign clkin1 = clk;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.500),
.CLKFX_DIVIDE (5),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (clk_20MHz),
.I (clkfx));
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="hls_saturation_enhance,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=7,HLS_SYN_DSP=8,HLS_SYN_FF=7965,HLS_SYN_LUT=7349}" *)
module hls_saturation_enhance (
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
ap_clk,
ap_rst_n,
stream_in_TDATA,
stream_in_TKEEP,
stream_in_TSTRB,
stream_in_TUSER,
stream_in_TLAST,
stream_in_TID,
stream_in_TDEST,
stream_out_TDATA,
stream_out_TKEEP,
stream_out_TSTRB,
stream_out_TUSER,
stream_out_TLAST,
stream_out_TID,
stream_out_TDEST,
stream_in_TVALID,
stream_in_TREADY,
stream_out_TVALID,
stream_out_TREADY
);
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 6;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_ADDR_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1:0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
input ap_clk;
input ap_rst_n;
input [23:0] stream_in_TDATA;
input [2:0] stream_in_TKEEP;
input [2:0] stream_in_TSTRB;
input [0:0] stream_in_TUSER;
input [0:0] stream_in_TLAST;
input [0:0] stream_in_TID;
input [0:0] stream_in_TDEST;
output [23:0] stream_out_TDATA;
output [2:0] stream_out_TKEEP;
output [2:0] stream_out_TSTRB;
output [0:0] stream_out_TUSER;
output [0:0] stream_out_TLAST;
output [0:0] stream_out_TID;
output [0:0] stream_out_TDEST;
input stream_in_TVALID;
output stream_in_TREADY;
output stream_out_TVALID;
input stream_out_TREADY;
reg ap_rst_n_inv;
wire [15:0] height;
wire [15:0] width;
wire [7:0] sat;
wire Block_Mat_exit1573_p_U0_ap_start;
wire Block_Mat_exit1573_p_U0_start_full_n;
wire Block_Mat_exit1573_p_U0_ap_done;
wire Block_Mat_exit1573_p_U0_ap_continue;
wire Block_Mat_exit1573_p_U0_ap_idle;
wire Block_Mat_exit1573_p_U0_ap_ready;
wire Block_Mat_exit1573_p_U0_start_out;
wire Block_Mat_exit1573_p_U0_start_write;
wire [15:0] Block_Mat_exit1573_p_U0_img0_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img0_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img0_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img0_cols_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img2_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img2_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img2_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img2_cols_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img3_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img3_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img3_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img3_cols_V_out_write;
wire [11:0] Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din;
wire Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write;
wire [11:0] Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din;
wire Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write;
wire [7:0] Block_Mat_exit1573_p_U0_sat_out_din;
wire Block_Mat_exit1573_p_U0_sat_out_write;
wire AXIvideo2Mat_U0_ap_start;
wire AXIvideo2Mat_U0_ap_done;
wire AXIvideo2Mat_U0_ap_continue;
wire AXIvideo2Mat_U0_ap_idle;
wire AXIvideo2Mat_U0_ap_ready;
wire AXIvideo2Mat_U0_start_out;
wire AXIvideo2Mat_U0_start_write;
wire AXIvideo2Mat_U0_stream_in_TREADY;
wire AXIvideo2Mat_U0_img_rows_V_read;
wire AXIvideo2Mat_U0_img_cols_V_read;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_0_V_din;
wire AXIvideo2Mat_U0_img_data_stream_0_V_write;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_1_V_din;
wire AXIvideo2Mat_U0_img_data_stream_1_V_write;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_2_V_din;
wire AXIvideo2Mat_U0_img_data_stream_2_V_write;
wire [15:0] AXIvideo2Mat_U0_img_rows_V_out_din;
wire AXIvideo2Mat_U0_img_rows_V_out_write;
wire [15:0] AXIvideo2Mat_U0_img_cols_V_out_din;
wire AXIvideo2Mat_U0_img_cols_V_out_write;
wire CvtColor_U0_ap_start;
wire CvtColor_U0_ap_done;
wire CvtColor_U0_ap_continue;
wire CvtColor_U0_ap_idle;
wire CvtColor_U0_ap_ready;
wire CvtColor_U0_p_src_rows_V_read;
wire CvtColor_U0_p_src_cols_V_read;
wire CvtColor_U0_p_src_data_stream_0_V_read;
wire CvtColor_U0_p_src_data_stream_1_V_read;
wire CvtColor_U0_p_src_data_stream_2_V_read;
wire [7:0] CvtColor_U0_p_dst_data_stream_0_V_din;
wire CvtColor_U0_p_dst_data_stream_0_V_write;
wire [7:0] CvtColor_U0_p_dst_data_stream_1_V_din;
wire CvtColor_U0_p_dst_data_stream_1_V_write;
wire [7:0] CvtColor_U0_p_dst_data_stream_2_V_din;
wire CvtColor_U0_p_dst_data_stream_2_V_write;
wire Loop_loop_height_pro_U0_ap_start;
wire Loop_loop_height_pro_U0_ap_done;
wire Loop_loop_height_pro_U0_ap_continue;
wire Loop_loop_height_pro_U0_ap_idle;
wire Loop_loop_height_pro_U0_ap_ready;
wire Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read;
wire Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_0_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_0_V_write;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_1_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_1_V_write;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_2_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_2_V_write;
wire Loop_loop_height_pro_U0_img1_data_stream_0_V_read;
wire Loop_loop_height_pro_U0_img1_data_stream_1_V_read;
wire Loop_loop_height_pro_U0_img1_data_stream_2_V_read;
wire Loop_loop_height_pro_U0_sat_read;
wire CvtColor_1_U0_ap_start;
wire CvtColor_1_U0_ap_done;
wire CvtColor_1_U0_ap_continue;
wire CvtColor_1_U0_ap_idle;
wire CvtColor_1_U0_ap_ready;
wire CvtColor_1_U0_p_src_rows_V_read;
wire CvtColor_1_U0_p_src_cols_V_read;
wire CvtColor_1_U0_p_src_data_stream_0_V_read;
wire CvtColor_1_U0_p_src_data_stream_1_V_read;
wire CvtColor_1_U0_p_src_data_stream_2_V_read;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_0_V_din;
wire CvtColor_1_U0_p_dst_data_stream_0_V_write;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_1_V_din;
wire CvtColor_1_U0_p_dst_data_stream_1_V_write;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_2_V_din;
wire CvtColor_1_U0_p_dst_data_stream_2_V_write;
wire Mat2AXIvideo_U0_ap_start;
wire Mat2AXIvideo_U0_ap_done;
wire Mat2AXIvideo_U0_ap_continue;
wire Mat2AXIvideo_U0_ap_idle;
wire Mat2AXIvideo_U0_ap_ready;
wire Mat2AXIvideo_U0_img_rows_V_read;
wire Mat2AXIvideo_U0_img_cols_V_read;
wire Mat2AXIvideo_U0_img_data_stream_0_V_read;
wire Mat2AXIvideo_U0_img_data_stream_1_V_read;
wire Mat2AXIvideo_U0_img_data_stream_2_V_read;
wire [23:0] Mat2AXIvideo_U0_stream_out_TDATA;
wire Mat2AXIvideo_U0_stream_out_TVALID;
wire [2:0] Mat2AXIvideo_U0_stream_out_TKEEP;
wire [2:0] Mat2AXIvideo_U0_stream_out_TSTRB;
wire [0:0] Mat2AXIvideo_U0_stream_out_TUSER;
wire [0:0] Mat2AXIvideo_U0_stream_out_TLAST;
wire [0:0] Mat2AXIvideo_U0_stream_out_TID;
wire [0:0] Mat2AXIvideo_U0_stream_out_TDEST;
wire ap_sync_continue;
wire img0_rows_V_c_full_n;
wire [15:0] img0_rows_V_c_dout;
wire img0_rows_V_c_empty_n;
wire img0_cols_V_c_full_n;
wire [15:0] img0_cols_V_c_dout;
wire img0_cols_V_c_empty_n;
wire img2_rows_V_c_full_n;
wire [15:0] img2_rows_V_c_dout;
wire img2_rows_V_c_empty_n;
wire img2_cols_V_c_full_n;
wire [15:0] img2_cols_V_c_dout;
wire img2_cols_V_c_empty_n;
wire img3_rows_V_c_full_n;
wire [15:0] img3_rows_V_c_dout;
wire img3_rows_V_c_empty_n;
wire img3_cols_V_c_full_n;
wire [15:0] img3_cols_V_c_dout;
wire img3_cols_V_c_empty_n;
wire p_cols_assign_cast_lo_full_n;
wire [11:0] p_cols_assign_cast_lo_dout;
wire p_cols_assign_cast_lo_empty_n;
wire p_rows_assign_cast_lo_full_n;
wire [11:0] p_rows_assign_cast_lo_dout;
wire p_rows_assign_cast_lo_empty_n;
wire sat_c_full_n;
wire [7:0] sat_c_dout;
wire sat_c_empty_n;
wire img0_data_stream_0_s_full_n;
wire [7:0] img0_data_stream_0_s_dout;
wire img0_data_stream_0_s_empty_n;
wire img0_data_stream_1_s_full_n;
wire [7:0] img0_data_stream_1_s_dout;
wire img0_data_stream_1_s_empty_n;
wire img0_data_stream_2_s_full_n;
wire [7:0] img0_data_stream_2_s_dout;
wire img0_data_stream_2_s_empty_n;
wire img0_rows_V_c83_full_n;
wire [15:0] img0_rows_V_c83_dout;
wire img0_rows_V_c83_empty_n;
wire img0_cols_V_c84_full_n;
wire [15:0] img0_cols_V_c84_dout;
wire img0_cols_V_c84_empty_n;
wire img1_data_stream_0_s_full_n;
wire [7:0] img1_data_stream_0_s_dout;
wire img1_data_stream_0_s_empty_n;
wire img1_data_stream_1_s_full_n;
wire [7:0] img1_data_stream_1_s_dout;
wire img1_data_stream_1_s_empty_n;
wire img1_data_stream_2_s_full_n;
wire [7:0] img1_data_stream_2_s_dout;
wire img1_data_stream_2_s_empty_n;
wire img2_data_stream_0_s_full_n;
wire [7:0] img2_data_stream_0_s_dout;
wire img2_data_stream_0_s_empty_n;
wire img2_data_stream_1_s_full_n;
wire [7:0] img2_data_stream_1_s_dout;
wire img2_data_stream_1_s_empty_n;
wire img2_data_stream_2_s_full_n;
wire [7:0] img2_data_stream_2_s_dout;
wire img2_data_stream_2_s_empty_n;
wire img3_data_stream_0_s_full_n;
wire [7:0] img3_data_stream_0_s_dout;
wire img3_data_stream_0_s_empty_n;
wire img3_data_stream_1_s_full_n;
wire [7:0] img3_data_stream_1_s_dout;
wire img3_data_stream_1_s_empty_n;
wire img3_data_stream_2_s_full_n;
wire [7:0] img3_data_stream_2_s_dout;
wire img3_data_stream_2_s_empty_n;
wire [0:0] start_for_Loop_loop_height_pro_U0_din;
wire start_for_Loop_loop_height_pro_U0_full_n;
wire [0:0] start_for_Loop_loop_height_pro_U0_dout;
wire start_for_Loop_loop_height_pro_U0_empty_n;
wire [0:0] start_for_CvtColor_1_U0_din;
wire start_for_CvtColor_1_U0_full_n;
wire [0:0] start_for_CvtColor_1_U0_dout;
wire start_for_CvtColor_1_U0_empty_n;
wire [0:0] start_for_Mat2AXIvideo_U0_din;
wire start_for_Mat2AXIvideo_U0_full_n;
wire [0:0] start_for_Mat2AXIvideo_U0_dout;
wire start_for_Mat2AXIvideo_U0_empty_n;
wire [0:0] start_for_CvtColor_U0_din;
wire start_for_CvtColor_U0_full_n;
wire [0:0] start_for_CvtColor_U0_dout;
wire start_for_CvtColor_U0_empty_n;
wire CvtColor_U0_start_full_n;
wire CvtColor_U0_start_write;
wire Loop_loop_height_pro_U0_start_full_n;
wire Loop_loop_height_pro_U0_start_write;
wire CvtColor_1_U0_start_full_n;
wire CvtColor_1_U0_start_write;
wire Mat2AXIvideo_U0_start_full_n;
wire Mat2AXIvideo_U0_start_write;
hls_saturation_enhance_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
hls_saturation_enhance_AXILiteS_s_axi_U(
.AWVALID(s_axi_AXILiteS_AWVALID),
.AWREADY(s_axi_AXILiteS_AWREADY),
.AWADDR(s_axi_AXILiteS_AWADDR),
.WVALID(s_axi_AXILiteS_WVALID),
.WREADY(s_axi_AXILiteS_WREADY),
.WDATA(s_axi_AXILiteS_WDATA),
.WSTRB(s_axi_AXILiteS_WSTRB),
.ARVALID(s_axi_AXILiteS_ARVALID),
.ARREADY(s_axi_AXILiteS_ARREADY),
.ARADDR(s_axi_AXILiteS_ARADDR),
.RVALID(s_axi_AXILiteS_RVALID),
.RREADY(s_axi_AXILiteS_RREADY),
.RDATA(s_axi_AXILiteS_RDATA),
.RRESP(s_axi_AXILiteS_RRESP),
.BVALID(s_axi_AXILiteS_BVALID),
.BREADY(s_axi_AXILiteS_BREADY),
.BRESP(s_axi_AXILiteS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.height(height),
.width(width),
.sat(sat)
);
Block_Mat_exit1573_p Block_Mat_exit1573_p_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Block_Mat_exit1573_p_U0_ap_start),
.start_full_n(Block_Mat_exit1573_p_U0_start_full_n),
.ap_done(Block_Mat_exit1573_p_U0_ap_done),
.ap_continue(Block_Mat_exit1573_p_U0_ap_continue),
.ap_idle(Block_Mat_exit1573_p_U0_ap_idle),
.ap_ready(Block_Mat_exit1573_p_U0_ap_ready),
.start_out(Block_Mat_exit1573_p_U0_start_out),
.start_write(Block_Mat_exit1573_p_U0_start_write),
.height(height),
.width(width),
.sat(sat),
.img0_rows_V_out_din(Block_Mat_exit1573_p_U0_img0_rows_V_out_din),
.img0_rows_V_out_full_n(img0_rows_V_c_full_n),
.img0_rows_V_out_write(Block_Mat_exit1573_p_U0_img0_rows_V_out_write),
.img0_cols_V_out_din(Block_Mat_exit1573_p_U0_img0_cols_V_out_din),
.img0_cols_V_out_full_n(img0_cols_V_c_full_n),
.img0_cols_V_out_write(Block_Mat_exit1573_p_U0_img0_cols_V_out_write),
.img2_rows_V_out_din(Block_Mat_exit1573_p_U0_img2_rows_V_out_din),
.img2_rows_V_out_full_n(img2_rows_V_c_full_n),
.img2_rows_V_out_write(Block_Mat_exit1573_p_U0_img2_rows_V_out_write),
.img2_cols_V_out_din(Block_Mat_exit1573_p_U0_img2_cols_V_out_din),
.img2_cols_V_out_full_n(img2_cols_V_c_full_n),
.img2_cols_V_out_write(Block_Mat_exit1573_p_U0_img2_cols_V_out_write),
.img3_rows_V_out_din(Block_Mat_exit1573_p_U0_img3_rows_V_out_din),
.img3_rows_V_out_full_n(img3_rows_V_c_full_n),
.img3_rows_V_out_write(Block_Mat_exit1573_p_U0_img3_rows_V_out_write),
.img3_cols_V_out_din(Block_Mat_exit1573_p_U0_img3_cols_V_out_din),
.img3_cols_V_out_full_n(img3_cols_V_c_full_n),
.img3_cols_V_out_write(Block_Mat_exit1573_p_U0_img3_cols_V_out_write),
.p_cols_assign_cast_out_out_din(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din),
.p_cols_assign_cast_out_out_full_n(p_cols_assign_cast_lo_full_n),
.p_cols_assign_cast_out_out_write(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write),
.p_rows_assign_cast_out_out_din(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din),
.p_rows_assign_cast_out_out_full_n(p_rows_assign_cast_lo_full_n),
.p_rows_assign_cast_out_out_write(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write),
.sat_out_din(Block_Mat_exit1573_p_U0_sat_out_din),
.sat_out_full_n(sat_c_full_n),
.sat_out_write(Block_Mat_exit1573_p_U0_sat_out_write)
);
AXIvideo2Mat AXIvideo2Mat_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(AXIvideo2Mat_U0_ap_start),
.start_full_n(start_for_CvtColor_U0_full_n),
.ap_done(AXIvideo2Mat_U0_ap_done),
.ap_continue(AXIvideo2Mat_U0_ap_continue),
.ap_idle(AXIvideo2Mat_U0_ap_idle),
.ap_ready(AXIvideo2Mat_U0_ap_ready),
.start_out(AXIvideo2Mat_U0_start_out),
.start_write(AXIvideo2Mat_U0_start_write),
.stream_in_TDATA(stream_in_TDATA),
.stream_in_TVALID(stream_in_TVALID),
.stream_in_TREADY(AXIvideo2Mat_U0_stream_in_TREADY),
.stream_in_TKEEP(stream_in_TKEEP),
.stream_in_TSTRB(stream_in_TSTRB),
.stream_in_TUSER(stream_in_TUSER),
.stream_in_TLAST(stream_in_TLAST),
.stream_in_TID(stream_in_TID),
.stream_in_TDEST(stream_in_TDEST),
.img_rows_V_dout(img0_rows_V_c_dout),
.img_rows_V_empty_n(img0_rows_V_c_empty_n),
.img_rows_V_read(AXIvideo2Mat_U0_img_rows_V_read),
.img_cols_V_dout(img0_cols_V_c_dout),
.img_cols_V_empty_n(img0_cols_V_c_empty_n),
.img_cols_V_read(AXIvideo2Mat_U0_img_cols_V_read),
.img_data_stream_0_V_din(AXIvideo2Mat_U0_img_data_stream_0_V_din),
.img_data_stream_0_V_full_n(img0_data_stream_0_s_full_n),
.img_data_stream_0_V_write(AXIvideo2Mat_U0_img_data_stream_0_V_write),
.img_data_stream_1_V_din(AXIvideo2Mat_U0_img_data_stream_1_V_din),
.img_data_stream_1_V_full_n(img0_data_stream_1_s_full_n),
.img_data_stream_1_V_write(AXIvideo2Mat_U0_img_data_stream_1_V_write),
.img_data_stream_2_V_din(AXIvideo2Mat_U0_img_data_stream_2_V_din),
.img_data_stream_2_V_full_n(img0_data_stream_2_s_full_n),
.img_data_stream_2_V_write(AXIvideo2Mat_U0_img_data_stream_2_V_write),
.img_rows_V_out_din(AXIvideo2Mat_U0_img_rows_V_out_din),
.img_rows_V_out_full_n(img0_rows_V_c83_full_n),
.img_rows_V_out_write(AXIvideo2Mat_U0_img_rows_V_out_write),
.img_cols_V_out_din(AXIvideo2Mat_U0_img_cols_V_out_din),
.img_cols_V_out_full_n(img0_cols_V_c84_full_n),
.img_cols_V_out_write(AXIvideo2Mat_U0_img_cols_V_out_write)
);
CvtColor CvtColor_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(CvtColor_U0_ap_start),
.ap_done(CvtColor_U0_ap_done),
.ap_continue(CvtColor_U0_ap_continue),
.ap_idle(CvtColor_U0_ap_idle),
.ap_ready(CvtColor_U0_ap_ready),
.p_src_rows_V_dout(img0_rows_V_c83_dout),
.p_src_rows_V_empty_n(img0_rows_V_c83_empty_n),
.p_src_rows_V_read(CvtColor_U0_p_src_rows_V_read),
.p_src_cols_V_dout(img0_cols_V_c84_dout),
.p_src_cols_V_empty_n(img0_cols_V_c84_empty_n),
.p_src_cols_V_read(CvtColor_U0_p_src_cols_V_read),
.p_src_data_stream_0_V_dout(img0_data_stream_0_s_dout),
.p_src_data_stream_0_V_empty_n(img0_data_stream_0_s_empty_n),
.p_src_data_stream_0_V_read(CvtColor_U0_p_src_data_stream_0_V_read),
.p_src_data_stream_1_V_dout(img0_data_stream_1_s_dout),
.p_src_data_stream_1_V_empty_n(img0_data_stream_1_s_empty_n),
.p_src_data_stream_1_V_read(CvtColor_U0_p_src_data_stream_1_V_read),
.p_src_data_stream_2_V_dout(img0_data_stream_2_s_dout),
.p_src_data_stream_2_V_empty_n(img0_data_stream_2_s_empty_n),
.p_src_data_stream_2_V_read(CvtColor_U0_p_src_data_stream_2_V_read),
.p_dst_data_stream_0_V_din(CvtColor_U0_p_dst_data_stream_0_V_din),
.p_dst_data_stream_0_V_full_n(img1_data_stream_0_s_full_n),
.p_dst_data_stream_0_V_write(CvtColor_U0_p_dst_data_stream_0_V_write),
.p_dst_data_stream_1_V_din(CvtColor_U0_p_dst_data_stream_1_V_din),
.p_dst_data_stream_1_V_full_n(img1_data_stream_1_s_full_n),
.p_dst_data_stream_1_V_write(CvtColor_U0_p_dst_data_stream_1_V_write),
.p_dst_data_stream_2_V_din(CvtColor_U0_p_dst_data_stream_2_V_din),
.p_dst_data_stream_2_V_full_n(img1_data_stream_2_s_full_n),
.p_dst_data_stream_2_V_write(CvtColor_U0_p_dst_data_stream_2_V_write)
);
Loop_loop_height_pro Loop_loop_height_pro_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Loop_loop_height_pro_U0_ap_start),
.ap_done(Loop_loop_height_pro_U0_ap_done),
.ap_continue(Loop_loop_height_pro_U0_ap_continue),
.ap_idle(Loop_loop_height_pro_U0_ap_idle),
.ap_ready(Loop_loop_height_pro_U0_ap_ready),
.p_rows_assign_cast_loc_dout(p_rows_assign_cast_lo_dout),
.p_rows_assign_cast_loc_empty_n(p_rows_assign_cast_lo_empty_n),
.p_rows_assign_cast_loc_read(Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read),
.p_cols_assign_cast_loc_dout(p_cols_assign_cast_lo_dout),
.p_cols_assign_cast_loc_empty_n(p_cols_assign_cast_lo_empty_n),
.p_cols_assign_cast_loc_read(Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read),
.img2_data_stream_0_V_din(Loop_loop_height_pro_U0_img2_data_stream_0_V_din),
.img2_data_stream_0_V_full_n(img2_data_stream_0_s_full_n),
.img2_data_stream_0_V_write(Loop_loop_height_pro_U0_img2_data_stream_0_V_write),
.img2_data_stream_1_V_din(Loop_loop_height_pro_U0_img2_data_stream_1_V_din),
.img2_data_stream_1_V_full_n(img2_data_stream_1_s_full_n),
.img2_data_stream_1_V_write(Loop_loop_height_pro_U0_img2_data_stream_1_V_write),
.img2_data_stream_2_V_din(Loop_loop_height_pro_U0_img2_data_stream_2_V_din),
.img2_data_stream_2_V_full_n(img2_data_stream_2_s_full_n),
.img2_data_stream_2_V_write(Loop_loop_height_pro_U0_img2_data_stream_2_V_write),
.img1_data_stream_0_V_dout(img1_data_stream_0_s_dout),
.img1_data_stream_0_V_empty_n(img1_data_stream_0_s_empty_n),
.img1_data_stream_0_V_read(Loop_loop_height_pro_U0_img1_data_stream_0_V_read),
.img1_data_stream_1_V_dout(img1_data_stream_1_s_dout),
.img1_data_stream_1_V_empty_n(img1_data_stream_1_s_empty_n),
.img1_data_stream_1_V_read(Loop_loop_height_pro_U0_img1_data_stream_1_V_read),
.img1_data_stream_2_V_dout(img1_data_stream_2_s_dout),
.img1_data_stream_2_V_empty_n(img1_data_stream_2_s_empty_n),
.img1_data_stream_2_V_read(Loop_loop_height_pro_U0_img1_data_stream_2_V_read),
.sat_dout(sat_c_dout),
.sat_empty_n(sat_c_empty_n),
.sat_read(Loop_loop_height_pro_U0_sat_read)
);
CvtColor_1 CvtColor_1_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(CvtColor_1_U0_ap_start),
.ap_done(CvtColor_1_U0_ap_done),
.ap_continue(CvtColor_1_U0_ap_continue),
.ap_idle(CvtColor_1_U0_ap_idle),
.ap_ready(CvtColor_1_U0_ap_ready),
.p_src_rows_V_dout(img2_rows_V_c_dout),
.p_src_rows_V_empty_n(img2_rows_V_c_empty_n),
.p_src_rows_V_read(CvtColor_1_U0_p_src_rows_V_read),
.p_src_cols_V_dout(img2_cols_V_c_dout),
.p_src_cols_V_empty_n(img2_cols_V_c_empty_n),
.p_src_cols_V_read(CvtColor_1_U0_p_src_cols_V_read),
.p_src_data_stream_0_V_dout(img2_data_stream_0_s_dout),
.p_src_data_stream_0_V_empty_n(img2_data_stream_0_s_empty_n),
.p_src_data_stream_0_V_read(CvtColor_1_U0_p_src_data_stream_0_V_read),
.p_src_data_stream_1_V_dout(img2_data_stream_1_s_dout),
.p_src_data_stream_1_V_empty_n(img2_data_stream_1_s_empty_n),
.p_src_data_stream_1_V_read(CvtColor_1_U0_p_src_data_stream_1_V_read),
.p_src_data_stream_2_V_dout(img2_data_stream_2_s_dout),
.p_src_data_stream_2_V_empty_n(img2_data_stream_2_s_empty_n),
.p_src_data_stream_2_V_read(CvtColor_1_U0_p_src_data_stream_2_V_read),
.p_dst_data_stream_0_V_din(CvtColor_1_U0_p_dst_data_stream_0_V_din),
.p_dst_data_stream_0_V_full_n(img3_data_stream_0_s_full_n),
.p_dst_data_stream_0_V_write(CvtColor_1_U0_p_dst_data_stream_0_V_write),
.p_dst_data_stream_1_V_din(CvtColor_1_U0_p_dst_data_stream_1_V_din),
.p_dst_data_stream_1_V_full_n(img3_data_stream_1_s_full_n),
.p_dst_data_stream_1_V_write(CvtColor_1_U0_p_dst_data_stream_1_V_write),
.p_dst_data_stream_2_V_din(CvtColor_1_U0_p_dst_data_stream_2_V_din),
.p_dst_data_stream_2_V_full_n(img3_data_stream_2_s_full_n),
.p_dst_data_stream_2_V_write(CvtColor_1_U0_p_dst_data_stream_2_V_write)
);
Mat2AXIvideo Mat2AXIvideo_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Mat2AXIvideo_U0_ap_start),
.ap_done(Mat2AXIvideo_U0_ap_done),
.ap_continue(Mat2AXIvideo_U0_ap_continue),
.ap_idle(Mat2AXIvideo_U0_ap_idle),
.ap_ready(Mat2AXIvideo_U0_ap_ready),
.img_rows_V_dout(img3_rows_V_c_dout),
.img_rows_V_empty_n(img3_rows_V_c_empty_n),
.img_rows_V_read(Mat2AXIvideo_U0_img_rows_V_read),
.img_cols_V_dout(img3_cols_V_c_dout),
.img_cols_V_empty_n(img3_cols_V_c_empty_n),
.img_cols_V_read(Mat2AXIvideo_U0_img_cols_V_read),
.img_data_stream_0_V_dout(img3_data_stream_0_s_dout),
.img_data_stream_0_V_empty_n(img3_data_stream_0_s_empty_n),
.img_data_stream_0_V_read(Mat2AXIvideo_U0_img_data_stream_0_V_read),
.img_data_stream_1_V_dout(img3_data_stream_1_s_dout),
.img_data_stream_1_V_empty_n(img3_data_stream_1_s_empty_n),
.img_data_stream_1_V_read(Mat2AXIvideo_U0_img_data_stream_1_V_read),
.img_data_stream_2_V_dout(img3_data_stream_2_s_dout),
.img_data_stream_2_V_empty_n(img3_data_stream_2_s_empty_n),
.img_data_stream_2_V_read(Mat2AXIvideo_U0_img_data_stream_2_V_read),
.stream_out_TDATA(Mat2AXIvideo_U0_stream_out_TDATA),
.stream_out_TVALID(Mat2AXIvideo_U0_stream_out_TVALID),
.stream_out_TREADY(stream_out_TREADY),
.stream_out_TKEEP(Mat2AXIvideo_U0_stream_out_TKEEP),
.stream_out_TSTRB(Mat2AXIvideo_U0_stream_out_TSTRB),
.stream_out_TUSER(Mat2AXIvideo_U0_stream_out_TUSER),
.stream_out_TLAST(Mat2AXIvideo_U0_stream_out_TLAST),
.stream_out_TID(Mat2AXIvideo_U0_stream_out_TID),
.stream_out_TDEST(Mat2AXIvideo_U0_stream_out_TDEST)
);
fifo_w16_d1_A img0_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img0_rows_V_out_din),
.if_full_n(img0_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img0_rows_V_out_write),
.if_dout(img0_rows_V_c_dout),
.if_empty_n(img0_rows_V_c_empty_n),
.if_read(AXIvideo2Mat_U0_img_rows_V_read)
);
fifo_w16_d1_A img0_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img0_cols_V_out_din),
.if_full_n(img0_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img0_cols_V_out_write),
.if_dout(img0_cols_V_c_dout),
.if_empty_n(img0_cols_V_c_empty_n),
.if_read(AXIvideo2Mat_U0_img_cols_V_read)
);
fifo_w16_d4_A img2_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img2_rows_V_out_din),
.if_full_n(img2_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img2_rows_V_out_write),
.if_dout(img2_rows_V_c_dout),
.if_empty_n(img2_rows_V_c_empty_n),
.if_read(CvtColor_1_U0_p_src_rows_V_read)
);
fifo_w16_d4_A img2_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img2_cols_V_out_din),
.if_full_n(img2_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img2_cols_V_out_write),
.if_dout(img2_cols_V_c_dout),
.if_empty_n(img2_cols_V_c_empty_n),
.if_read(CvtColor_1_U0_p_src_cols_V_read)
);
fifo_w16_d5_A img3_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img3_rows_V_out_din),
.if_full_n(img3_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img3_rows_V_out_write),
.if_dout(img3_rows_V_c_dout),
.if_empty_n(img3_rows_V_c_empty_n),
.if_read(Mat2AXIvideo_U0_img_rows_V_read)
);
fifo_w16_d5_A img3_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img3_cols_V_out_din),
.if_full_n(img3_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img3_cols_V_out_write),
.if_dout(img3_cols_V_c_dout),
.if_empty_n(img3_cols_V_c_empty_n),
.if_read(Mat2AXIvideo_U0_img_cols_V_read)
);
fifo_w12_d3_A p_cols_assign_cast_lo_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din),
.if_full_n(p_cols_assign_cast_lo_full_n),
.if_write(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write),
.if_dout(p_cols_assign_cast_lo_dout),
.if_empty_n(p_cols_assign_cast_lo_empty_n),
.if_read(Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read)
);
fifo_w12_d3_A p_rows_assign_cast_lo_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din),
.if_full_n(p_rows_assign_cast_lo_full_n),
.if_write(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write),
.if_dout(p_rows_assign_cast_lo_dout),
.if_empty_n(p_rows_assign_cast_lo_empty_n),
.if_read(Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read)
);
fifo_w8_d3_A sat_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_sat_out_din),
.if_full_n(sat_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_sat_out_write),
.if_dout(sat_c_dout),
.if_empty_n(sat_c_empty_n),
.if_read(Loop_loop_height_pro_U0_sat_read)
);
fifo_w8_d1_A img0_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_0_V_din),
.if_full_n(img0_data_stream_0_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_0_V_write),
.if_dout(img0_data_stream_0_s_dout),
.if_empty_n(img0_data_stream_0_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_0_V_read)
);
fifo_w8_d1_A img0_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_1_V_din),
.if_full_n(img0_data_stream_1_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_1_V_write),
.if_dout(img0_data_stream_1_s_dout),
.if_empty_n(img0_data_stream_1_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_1_V_read)
);
fifo_w8_d1_A img0_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_2_V_din),
.if_full_n(img0_data_stream_2_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_2_V_write),
.if_dout(img0_data_stream_2_s_dout),
.if_empty_n(img0_data_stream_2_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_2_V_read)
);
fifo_w16_d1_A img0_rows_V_c83_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_rows_V_out_din),
.if_full_n(img0_rows_V_c83_full_n),
.if_write(AXIvideo2Mat_U0_img_rows_V_out_write),
.if_dout(img0_rows_V_c83_dout),
.if_empty_n(img0_rows_V_c83_empty_n),
.if_read(CvtColor_U0_p_src_rows_V_read)
);
fifo_w16_d1_A img0_cols_V_c84_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_cols_V_out_din),
.if_full_n(img0_cols_V_c84_full_n),
.if_write(AXIvideo2Mat_U0_img_cols_V_out_write),
.if_dout(img0_cols_V_c84_dout),
.if_empty_n(img0_cols_V_c84_empty_n),
.if_read(CvtColor_U0_p_src_cols_V_read)
);
fifo_w8_d1_A img1_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_0_V_din),
.if_full_n(img1_data_stream_0_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_0_V_write),
.if_dout(img1_data_stream_0_s_dout),
.if_empty_n(img1_data_stream_0_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_0_V_read)
);
fifo_w8_d1_A img1_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_1_V_din),
.if_full_n(img1_data_stream_1_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_1_V_write),
.if_dout(img1_data_stream_1_s_dout),
.if_empty_n(img1_data_stream_1_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_1_V_read)
);
fifo_w8_d1_A img1_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_2_V_din),
.if_full_n(img1_data_stream_2_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_2_V_write),
.if_dout(img1_data_stream_2_s_dout),
.if_empty_n(img1_data_stream_2_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_2_V_read)
);
fifo_w8_d1_A img2_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_0_V_din),
.if_full_n(img2_data_stream_0_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_0_V_write),
.if_dout(img2_data_stream_0_s_dout),
.if_empty_n(img2_data_stream_0_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_0_V_read)
);
fifo_w8_d1_A img2_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_1_V_din),
.if_full_n(img2_data_stream_1_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_1_V_write),
.if_dout(img2_data_stream_1_s_dout),
.if_empty_n(img2_data_stream_1_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_1_V_read)
);
fifo_w8_d1_A img2_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_2_V_din),
.if_full_n(img2_data_stream_2_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_2_V_write),
.if_dout(img2_data_stream_2_s_dout),
.if_empty_n(img2_data_stream_2_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_2_V_read)
);
fifo_w8_d1_A img3_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_0_V_din),
.if_full_n(img3_data_stream_0_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_0_V_write),
.if_dout(img3_data_stream_0_s_dout),
.if_empty_n(img3_data_stream_0_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_0_V_read)
);
fifo_w8_d1_A img3_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_1_V_din),
.if_full_n(img3_data_stream_1_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_1_V_write),
.if_dout(img3_data_stream_1_s_dout),
.if_empty_n(img3_data_stream_1_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_1_V_read)
);
fifo_w8_d1_A img3_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_2_V_din),
.if_full_n(img3_data_stream_2_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_2_V_write),
.if_dout(img3_data_stream_2_s_dout),
.if_empty_n(img3_data_stream_2_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_2_V_read)
);
start_for_Loop_lotde start_for_Loop_lotde_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_Loop_loop_height_pro_U0_din),
.if_full_n(start_for_Loop_loop_height_pro_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_Loop_loop_height_pro_U0_dout),
.if_empty_n(start_for_Loop_loop_height_pro_U0_empty_n),
.if_read(Loop_loop_height_pro_U0_ap_ready)
);
start_for_CvtColoudo start_for_CvtColoudo_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_CvtColor_1_U0_din),
.if_full_n(start_for_CvtColor_1_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_CvtColor_1_U0_dout),
.if_empty_n(start_for_CvtColor_1_U0_empty_n),
.if_read(CvtColor_1_U0_ap_ready)
);
start_for_Mat2AXIvdy start_for_Mat2AXIvdy_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_Mat2AXIvideo_U0_din),
.if_full_n(start_for_Mat2AXIvideo_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_Mat2AXIvideo_U0_dout),
.if_empty_n(start_for_Mat2AXIvideo_U0_empty_n),
.if_read(Mat2AXIvideo_U0_ap_ready)
);
start_for_CvtColowdI start_for_CvtColowdI_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_CvtColor_U0_din),
.if_full_n(start_for_CvtColor_U0_full_n),
.if_write(AXIvideo2Mat_U0_start_write),
.if_dout(start_for_CvtColor_U0_dout),
.if_empty_n(start_for_CvtColor_U0_empty_n),
.if_read(CvtColor_U0_ap_ready)
);
assign AXIvideo2Mat_U0_ap_continue = 1'b1;
assign AXIvideo2Mat_U0_ap_start = 1'b1;
assign Block_Mat_exit1573_p_U0_ap_continue = 1'b1;
assign Block_Mat_exit1573_p_U0_ap_start = 1'b1;
assign Block_Mat_exit1573_p_U0_start_full_n = (start_for_Mat2AXIvideo_U0_full_n & start_for_Loop_loop_height_pro_U0_full_n & start_for_CvtColor_1_U0_full_n);
assign CvtColor_1_U0_ap_continue = 1'b1;
assign CvtColor_1_U0_ap_start = start_for_CvtColor_1_U0_empty_n;
assign CvtColor_1_U0_start_full_n = 1'b1;
assign CvtColor_1_U0_start_write = 1'b0;
assign CvtColor_U0_ap_continue = 1'b1;
assign CvtColor_U0_ap_start = start_for_CvtColor_U0_empty_n;
assign CvtColor_U0_start_full_n = 1'b1;
assign CvtColor_U0_start_write = 1'b0;
assign Loop_loop_height_pro_U0_ap_continue = 1'b1;
assign Loop_loop_height_pro_U0_ap_start = start_for_Loop_loop_height_pro_U0_empty_n;
assign Loop_loop_height_pro_U0_start_full_n = 1'b1;
assign Loop_loop_height_pro_U0_start_write = 1'b0;
assign Mat2AXIvideo_U0_ap_continue = 1'b1;
assign Mat2AXIvideo_U0_ap_start = start_for_Mat2AXIvideo_U0_empty_n;
assign Mat2AXIvideo_U0_start_full_n = 1'b1;
assign Mat2AXIvideo_U0_start_write = 1'b0;
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign ap_sync_continue = 1'b0;
assign start_for_CvtColor_1_U0_din = 1'b1;
assign start_for_CvtColor_U0_din = 1'b1;
assign start_for_Loop_loop_height_pro_U0_din = 1'b1;
assign start_for_Mat2AXIvideo_U0_din = 1'b1;
assign stream_in_TREADY = AXIvideo2Mat_U0_stream_in_TREADY;
assign stream_out_TDATA = Mat2AXIvideo_U0_stream_out_TDATA;
assign stream_out_TDEST = Mat2AXIvideo_U0_stream_out_TDEST;
assign stream_out_TID = Mat2AXIvideo_U0_stream_out_TID;
assign stream_out_TKEEP = Mat2AXIvideo_U0_stream_out_TKEEP;
assign stream_out_TLAST = Mat2AXIvideo_U0_stream_out_TLAST;
assign stream_out_TSTRB = Mat2AXIvideo_U0_stream_out_TSTRB;
assign stream_out_TUSER = Mat2AXIvideo_U0_stream_out_TUSER;
assign stream_out_TVALID = Mat2AXIvideo_U0_stream_out_TVALID;
endmodule //hls_saturation_enhance
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:51:58 03/24/2014
// Design Name:
// Module Name: MIPS32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mips32(/*AUTOARG*/
// Outputs
porta_out, portb_out,
// Inputs
rst, clk, porta_in, portb_in, interrupts
);
input rst;
input clk;
input porta_in;
input portb_in;
input [4:0] interrupts;
output porta_out;
output portb_out;
reg [31:0] PC;
reg [31:0] PCadd4;
wire [31:0] PCnext, PCout;
wire [31:0] HI;
wire [31:0] LO;
wire [31:0] inst;
wire [31:0] immediate;
wire [4:0] rs, rt, rd;
wire load, store, move, ssnop, nop,jump, branch,sign, regwrite,memtoreg,memread, memwrite;
wire [20:0] aluc;
wire [3:0] move_op;
wire [8:0] load_op;
wire [5:0] store_op;
wire [31:0] regrs_data, regrt_data;
wire [31:0] memaddr;
wire [31:0] memdata_in;
// IF stage
wire IF_stall;
wire IF_flush;
wire [31:0] IF_inst;
wire [31:0] IF_PC, IF_PCnext;
//wire [31:0] ID_inst;
//wire [31:0] ID_PCnext;
// ID stage
wire ID_stall;
wire ID_flush;
wire [31:0] ID_inst;
wire [31:0] ID_PCnext;
wire [4:0] ID_reg_dst;
wire [31:0] ID_data_a, ID_data_b, ID_data_c;
//wire [20:0] aluc;
wire ID_sign;
wire ID_memread, ID_memwrite;
wire [31:0] ID_memaddr;
wire [8:0] ID_load_op;
wire [5:0] ID_store_op;
wire ID_memtoreg, ID_regwrite;
wire [31:0] EX_data_a, EX_data_b, EX_data_c;
wire [20:0] EX_aluc;
wire EX_sign;
wire EX_memread, EX_memwrite;
wire [31:0] EX_memaddr;
wire [8:0] EX_load_op;
wire [5:0] EX_store_op;
wire EX_memtoreg, EX_regwrite;
// EXE stage:
wire EX_stall;
wire EX_flush;
wire [31:0] EX_alu_out;
wire [31:0] EX_alu_out_t;
wire [4:0] EX_rt_rd;
wire M_regwrite;
wire M_memtoreg;
wire M_memread;
wire M_memwrite;
wire [31:0] M_memaddr;
wire [8:0] M_load_op;
wire [5:0] M_store_op;
wire [31:0] M_alu_out;
wire [31:0] M_readdata;
wire [4:0] M_rt_rd;
wire M_flush;
wire M_stall;
wire WB_stall;
wire WB_regwrite;
wire WB_memtoreg;
wire [31:0] WB_readdata;
wire [31:0] WB_alu_out;
wire [4:0] WB_rtrd;
IF_stage IF_stage_0(/*AUTOINST*/
// Outputs
.ID_inst (ID_inst[31:0]),
.ID_PCnext (ID_PCnext[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.IF_stall (IF_stall),
.IF_flush (IF_flush),
.ID_stall (ID_stall),
.IF_inst (IF_inst[31:0]),
.IF_PCnext (IF_PCnext[31:0]),
.IF_PC (IF_PC[31:0]));
always @(posedge clk) begin
if (rst)
PC <= 32'b0;
else begin
PC <= PCnext;
PCadd4 <= PC + 32'h0000_0004;
end
end
mux2 #(.WIDTH(32)) PC_mux(
.sel (jump|branch),
.in0 (PCadd4),
.in1 (PCout),
.out (PCnext)
);
rom rom_0(
.PC (PC),
.inst (IF_inst),
.clk (clk)
);
//wire [31:0] target_offset;
//wire [25:0] inst_idx;
//wire [4:0] regdst;
decode decode_0(
.clk (clk),
.inst_in (ID_inst),
.PCin (ID_PCnext),
.regrs_data (regrs_data),
.regrt_data (regrt_data),
//Outputs
.PCout (PCout),
.jump (jump),
.ssnop (ssnop),
.branch (branch),
.aluc (ID_aluc),
.sign (ID_sign),
//.base (base),
//.immediate (immediate),
.store (store),
.store_op (ID_store_op),
.op_a (ID_data_a),
.op_b (ID_data_b),
.op_sa (ID_data_c),
.move (move),
.move_op (move_op),
.rs (rs),
.rt (rt),
.rd (rd),
.nop (nop),
.load (load),
.load_op (ID_load_op),
//.target_offset(target_offset),
//.inst_idx (inst_idx),
.regwrite (ID_regwrite),
.memtoreg (ID_memtoreg),
.memread (ID_memread),
.regdst (ID_reg_dst),
.memwrite (ID_memwrite),
.memaddr (ID_memaddr)
);
ID_stage ID_stage_0(/*AUTOINST*/
// Outputs
.EX_data_a (EX_data_a[31:0]),
.EX_data_b (EX_data_b[31:0]),
.EX_data_c (EX_data_c[31:0]),
.EX_aluc (EX_aluc[20:0]),
.EX_sign (EX_sign),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_memtoreg (EX_memtoreg),
.EX_regwrite (EX_regwrite),
// Inputs
.clk (clk),
.rst (rst),
.ID_stall (ID_stall),
.ID_flush (ID_flush),
.EX_stall (EX_stall),
.ID_reg_dst (ID_reg_dst[4:0]),
.ID_data_a (ID_data_a[31:0]),
.ID_data_b (ID_data_b[31:0]),
.ID_data_c (ID_data_c[31:0]),
.ID_aluc (ID_aluc),
.ID_sign (ID_sign),
.ID_memread (ID_memread),
.ID_memwrite (ID_memwrite),
.ID_memaddr (ID_memaddr),
.ID_load_op (ID_load_op[8:0]),
.ID_store_op (ID_store_op[5:0]),
.ID_memtoreg (ID_memtoreg),
.ID_regwrite (ID_regwrite));
alu alu_0(
//Inputs
//.data_c (ID_data_c),
.clk (clk),
.aluc (EX_aluc),
.sign (EX_sign),
.data_a (EX_data_a),
.data_b (EX_data_b),
.data_c (EX_data_c),
//Outputs
.data_out_t (EX_alu_out_t),
.overflow (overflow),
.ready (ready),
.data_out (EX_alu_out));
EX_stage EX_stage_0(
// Outputs
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_memread (M_memread),
.M_memwrite (M_memwrite),
.M_memaddr (M_memaddr),
.M_load_op (M_load_op[8:0]),
.M_store_op (M_store_op[5:0]),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]),
// Inputs
.clk (clk),
.rst (rst),
.EX_stall (EX_stall),
.EX_flush (EX_flush),
.M_stall (M_stall),
.EX_regwrite (EX_regwrite),
//.EX_reg_dst (ID_reg_dst),
.EX_memtoreg (EX_memtoreg),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_alu_out (EX_alu_out[31:0]),
.EX_alu_out_t (EX_alu_out_t[31:0]),
.EX_rt_rd (ID_reg_dst));
reg [31:0] gpr_data_in;
always @* begin
case (WB_memtoreg)
1'b1: gpr_data_in <= WB_readdata;
1'b0: gpr_data_in <= WB_alu_out;
endcase
end
gpr gpr_0(
// Outputs
.reg_out1 (regrt_data),
.reg_out2 (regrs_data),
// Inputs
.clk (clk),
.regwrite (WB_regwrite),
.data_in (gpr_data_in),
.write_addr (WB_rtrd),
.reg_addr1 (rs),
.reg_addr2 (rt));
data_ram data_ram_0(
.clk (clk),
.rst (rst),
.m_read (M_memread),
.m_write (M_memwrite),
.m_addr (M_memaddr),
.m_din (memdata_in),
// Outputs
.m_dout (M_readdata)
);
MEM_stage MEM_stage_0(
// Outputs
.WB_regwrite (WB_regwrite),
.WB_memtoreg (WB_memtoreg),
.WB_readdata (WB_readdata),
.WB_alu_out (WB_alu_out[31:0]),
.WB_rt_rd (WB_rtrd),
// Inputs
.clk (clk),
.rst (rst),
.M_flush (M_flush),
.M_stall (M_stall),
.WB_stall (WB_stall),
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_readdata (M_readdata),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]));
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_interrupt.v
// Title : Interrupt logic
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_interrupt (
// ----- Inputs -------
clk_i,
rst_i,
// From external devices
interrupt,
// From pipeline
stall_x,
`ifdef CFG_DEBUG_ENABLED
non_debug_exception,
debug_exception,
`else
exception,
`endif
eret_q_x,
`ifdef CFG_DEBUG_ENABLED
bret_q_x,
`endif
csr,
csr_write_data,
csr_write_enable,
// ----- Outputs -------
interrupt_exception,
// To pipeline
csr_read_data
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [interrupts-1:0] interrupt; // Interrupt pins
input stall_x; // Stall X pipeline stage
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception; // Non-debug related exception has been raised
input debug_exception; // Debug-related exception has been raised
`else
input exception; // Exception has been raised
`endif
input eret_q_x; // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x; // Return from breakpoint
`endif
input [`LM32_CSR_RNG] csr; // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input csr_write_enable; // CSR write enable
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output interrupt_exception; // Request to raide an interrupt exception
wire interrupt_exception;
output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
reg [`LM32_WORD_RNG] csr_read_data;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
`endif
wire [interrupts-1:0] interrupt_n_exception;
// Interrupt CSRs
reg ie; // Interrupt enable
reg eie; // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie; // Breakpoint interrupt enable
`endif
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] ip; // Interrupt pending
`else
reg [interrupts-1:0] ip; // Interrupt pending
`endif
reg [interrupts-1:0] im; // Interrupt mask
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
// Determine which interrupts are currently being asserted or are already pending
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
assign ip = interrupt;
`else
assign asserted = ip | interrupt;
`endif
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
if (interrupts > 1)
begin
// CSR read
always @(*)
begin
case (csr)
`ifdef CFG_MMU_ENABLED
`LM32_CSR_PSW,
`endif
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
`LM32_CSR_IM: csr_read_data = im;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
else
begin
// CSR read
always @(*)
begin
case (csr)
`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
bie,
`else
1'b0,
`endif
eie,
ie
};
`LM32_CSR_IP: csr_read_data = ip;
default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
end
endgenerate
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
generate
if (interrupts > 1)
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
im <= {interrupts{1'b0}};
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
`endif
end
else
begin
// Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if ( (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
|| (csr == `LM32_CSR_PSW)
`endif
)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
if (csr == `LM32_CSR_IM)
im <= csr_write_data[interrupts-1:0];
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
end
end
end
end
end
else
begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
ie <= `FALSE;
eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
bie <= `FALSE;
`endif
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= {interrupts{1'b0}};
`endif
end
else
begin
// Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
if (non_debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
else if (debug_exception == `TRUE)
begin
// Save and then clear interrupt enable
bie <= ie;
ie <= `FALSE;
end
`else
if (exception == `TRUE)
begin
// Save and then clear interrupt enable
eie <= ie;
ie <= `FALSE;
end
`endif
else if (stall_x == `FALSE)
begin
if (eret_q_x == `TRUE)
// Restore interrupt enable
ie <= eie;
`ifdef CFG_DEBUG_ENABLED
else if (bret_q_x == `TRUE)
// Restore interrupt enable
ie <= bie;
`endif
else if (csr_write_enable == `TRUE)
begin
// Handle wcsr write
if ( (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
|| (csr == `LM32_CSR_PSW)
`endif
)
begin
ie <= csr_write_data[0];
eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
bie <= csr_write_data[2];
`endif
end
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
if (csr == `LM32_CSR_IP)
ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
end
end
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_4_V
`define SKY130_FD_SC_MS__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by ____YOUR_NAME_HERE____.
interface if1;
integer var1;
endinterface
interface if2;
if1 i1 ();
integer var2;
endinterface
module mod1
(
input clk,
input integer modnum, // Don't use parameter, want same module twice for better checking
if2 foo
);
logic l1, l2;
always_ff @(posedge clk) begin
if (modnum==1) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
if (modnum==2) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
end
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
if2 i2a ();
if2 i2b ();
assign i2a.i1.var1 = 1;
assign i2a.var2 = 2;
assign i2b.i1.var1 = 3;
assign i2b.var2 = 4;
mod1 mod1a
(
.modnum (1),
.clk (clk),
.foo (i2a)
);
mod1 mod1b
(
.modnum (2),
.clk (clk),
.foo (i2a)
);
integer cyc = 0;
always_ff @(posedge clk) begin
cyc <= cyc+1;
if (cyc==2) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Thu Jul 11 11:26:45 2013
// ============================================================================
//`define ENABLE_HPS
//`define ENABLE_USB
module DE1_SoC_CAMERA(
///////// ADC /////////
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK2 /////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
///////// DRAM /////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
///////// FAN /////////
output FAN_CTRL,
///////// FPGA /////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
///////// GPIO /////////
inout [35:0] GPIO_0,
///////// HEX0 /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
`ifdef ENABLE_HPS
///////// HPS /////////
input HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// IRDA /////////
input IRDA_RXD,
output IRDA_TXD,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// SW /////////
input [9:0] SW,
///////// TD /////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
`ifdef ENABLE_USB
///////// USB /////////
input USB_B2_CLK,
inout [7:0] USB_B2_DATA,
output USB_EMPTY,
output USB_FULL,
input USB_OE_N,
input USB_RD_N,
input USB_RESET_N,
inout USB_SCL,
inout USB_SDA,
input USB_WR_N,
`endif /*ENABLE_USB*/
///////// VGA /////////
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_SYNC_N,
output VGA_CLK,
output VGA_HS,
output VGA_VS,
//////////// GPIO1, GPIO1 connect to D5M - 5M Pixel Camera //////////
input [11:0] D5M_D,
input D5M_FVAL,
input D5M_LVAL,
input D5M_PIXLCLK,
output D5M_RESET_N,
output D5M_SCLK,
inout D5M_SDATA,
input D5M_STROBE,
output D5M_TRIGGER,
output D5M_XCLKIN
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [15:0] Read_DATA1;
wire [15:0] Read_DATA2;
wire [11:0] mCCD_DATA;
wire mCCD_DVAL;
wire mCCD_DVAL_d;
wire [15:0] X_Cont;
wire [15:0] Y_Cont;
wire [9:0] X_ADDR;
wire DLY_RST_0;
wire DLY_RST_1;
wire DLY_RST_2;
wire DLY_RST_3;
wire DLY_RST_4;
wire Read;
reg [11:0] rCCD_DATA;
reg rCCD_LVAL;
reg rCCD_FVAL;
wire [11:0] sCCD_R;
wire [11:0] sCCD_G;
wire [11:0] sCCD_B;
wire sCCD_DVAL;
wire sdram_ctrl_clk;
//Image processing connectors
wire [23:0] wDebugProc;
wire [7:0] wRProc;
wire [7:0] wGProc;
wire [7:0] wBProc;
wire wHSyncProc;
wire wVSyncProc;
wire wLineValidProc;
wire wFrameValidProc;
//power on start
wire auto_start;
//=======================================================
// Structural coding
//=======================================================
// D5M
assign D5M_TRIGGER = 1'b1; // tRIGGER
assign D5M_RESET_N = DLY_RST_1;
assign VGA_CTRL_CLK = VGA_CLK;
assign VGA_SYNC_N = 0;
assign LEDR = 0;
//D5M read
always@(posedge D5M_PIXLCLK)
begin
rCCD_DATA <= D5M_D;
rCCD_LVAL <= D5M_LVAL;
rCCD_FVAL <= D5M_FVAL;
end
//auto start when power on
assign auto_start = ((KEY[0])&&(DLY_RST_3)&&(!DLY_RST_4))? 1'b1:1'b0;
//Reset module
Reset_Delay u2 (
.iCLK(CLOCK_50),
.iRST(KEY[0]),
.oRST_0(DLY_RST_0),
.oRST_1(DLY_RST_1),
.oRST_2(DLY_RST_2),
.oRST_3(DLY_RST_3),
.oRST_4(DLY_RST_4)
);
//D5M image capture
CCD_Capture u3 (
.oDATA(mCCD_DATA),
.oDVAL(mCCD_DVAL),
.oX_Cont(X_Cont),
.oY_Cont(Y_Cont),
.iDATA(rCCD_DATA),
.iFVAL(rCCD_FVAL),
.iLVAL(rCCD_LVAL),
.iSTART(!KEY[3]|auto_start),
.iEND(!KEY[2]),
.iCLK(~D5M_PIXLCLK),
.iRST(DLY_RST_2)
);
//D5M raw date convert to RGB data
RAW2RGB u4 (
.iCLK(D5M_PIXLCLK),
.iRST(DLY_RST_1),
.iDATA(mCCD_DATA),
.iDVAL(mCCD_DVAL),
.oRed(sCCD_R),
.oGreen(sCCD_G),
.oBlue(sCCD_B),
.oDVAL(sCCD_DVAL),
.iX_Cont(X_Cont),
.iY_Cont(Y_Cont)
);
//Frame count display
SEG7_LUT_6 u5 (
.oSEG0(HEX0),.oSEG1(HEX1),
.oSEG2(HEX2),.oSEG3(HEX3),
.oSEG4(HEX4),.oSEG5(HEX5),
.iDIG(wDebugProc)
);
sdram_pll u6 (
.refclk(CLOCK_50),
.rst(1'b0),
.outclk_0(sdram_ctrl_clk),
.outclk_1(DRAM_CLK),
.outclk_2(D5M_XCLKIN), //25M
.outclk_3(VGA_CLK) //25M
);
//SDRam Read and Write as Frame Buffer
Sdram_Control u7 (
// HOST Side
.RESET_N(KEY[0]),
.CLK(sdram_ctrl_clk),
// FIFO Write Side 1
.WR1_DATA({1'b0,sCCD_G[11:7],sCCD_B[11:2]}),
.WR1(sCCD_DVAL),
.WR1_ADDR(0),
.WR1_MAX_ADDR(640*480),
.WR1_LENGTH(8'h50),
.WR1_LOAD(!DLY_RST_0),
.WR1_CLK(~D5M_PIXLCLK),
// FIFO Write Side 2
.WR2_DATA({1'b0,sCCD_G[6:2],sCCD_R[11:2]}),
.WR2(sCCD_DVAL),
.WR2_ADDR(23'h100000),
.WR2_MAX_ADDR(23'h100000+640*480),
.WR2_LENGTH(8'h50),
.WR2_LOAD(!DLY_RST_0),
.WR2_CLK(~D5M_PIXLCLK),
// FIFO Read Side 1
.RD1_DATA(Read_DATA1),
.RD1(wLineValidProc),
.RD1_ADDR(0),
.RD1_MAX_ADDR(640*480),
.RD1_LENGTH(8'h50),
.RD1_LOAD(!DLY_RST_0),
.RD1_CLK(~VGA_CTRL_CLK),
// FIFO Read Side 2
.RD2_DATA(Read_DATA2),
.RD2(wLineValidProc),
.RD2_ADDR(23'h100000),
.RD2_MAX_ADDR(23'h100000+640*480),
.RD2_LENGTH(8'h50),
.RD2_LOAD(!DLY_RST_0),
.RD2_CLK(~VGA_CTRL_CLK),
// SDRAM Side
.SA(DRAM_ADDR),
.BA(DRAM_BA),
.CS_N(DRAM_CS_N),
.CKE(DRAM_CKE),
.RAS_N(DRAM_RAS_N),
.CAS_N(DRAM_CAS_N),
.WE_N(DRAM_WE_N),
.DQ(DRAM_DQ),
.DQM({DRAM_UDQM,DRAM_LDQM})
);
//D5M I2C control
I2C_CCD_Config u8 (
// Host Side
.iCLK(CLOCK2_50),
.iRST_N(DLY_RST_2),
.iEXPOSURE_ADJ(KEY[1]),
.iEXPOSURE_DEC_p(SW[8]),
.iZOOM_MODE_SW(SW[9]),
// I2C Side
.I2C_SCLK(D5M_SCLK),
.I2C_SDAT(D5M_SDATA)
);
//Image processing
image_processor u9 (
.iR(wRProc),
.iG(wGProc),
.iB(wBProc),
.iHSync(wHSyncProc),
.iVSync(wVSyncProc),
.iLineValid(wLineValidProc),
.iFrameValid(wFrameValidProc),
.iClk(VGA_CTRL_CLK),
.iDebug(SW[0]),
.oR(VGA_R),
.oG(VGA_G),
.oB(VGA_B),
.oHSync(VGA_HS),
.oVSync(VGA_VS),
.oLineValid(VGA_BLANK_N),
.oDebug(wDebugProc)
);
//VGA DISPLAY
VGAController u1 (
.iClk(VGA_CTRL_CLK),
.inRst(DLY_RST_2),
.iR(Read_DATA2[9:2]),
.iG({Read_DATA1[14:10],Read_DATA2[14:12]}),
.iB(Read_DATA1[9:2]),
.oR(wRProc),
.oG(wGProc),
.oB(wBProc),
.oHSync(wHSyncProc),
.oVSync(wVSyncProc),
.oLineValid(wLineValidProc),
.oFrameValid(wFrameValidProc)
);
endmodule
|
//altera message_off 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_addr_cmd_wrap
# ( parameter
CFG_MEM_IF_CHIP = 2,
CFG_MEM_IF_CKE_WIDTH = 2, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 16, // max supported address bits, must be >= row bits
CFG_MEM_IF_ROW_WIDTH = 16, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_LPDDR2_ENABLED = 1,
CFG_PORT_WIDTH_TYPE = 3,
CFG_DWIDTH_RATIO = 2,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_LOCAL_ID_WIDTH = 8,
CFG_DATA_ID_WIDTH = 4,
CFG_INT_SIZE_WIDTH = 4,
CFG_ODT_ENABLED = 1,
CFG_MEM_IF_ODT_WIDTH = 2,
CFG_PORT_WIDTH_CAS_WR_LAT = 5,
CFG_PORT_WIDTH_TCL = 5,
CFG_PORT_WIDTH_ADD_LAT = 5,
CFG_PORT_WIDTH_WRITE_ODT_CHIP = 4,
CFG_PORT_WIDTH_READ_ODT_CHIP = 4,
CFG_PORT_WIDTH_OUTPUT_REGD = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
cfg_type,
cfg_tcl,
cfg_cas_wr_lat,
cfg_add_lat,
cfg_write_odt_chip,
cfg_read_odt_chip,
cfg_burst_length,
cfg_output_regd_for_afi_output,
// burst generator command signals
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_auto_precharge,
bg_do_activate,
bg_do_precharge,
bg_do_precharge_all,
bg_do_refresh,
bg_do_self_refresh,
bg_do_power_down,
bg_do_deep_pdown,
bg_do_rmw_correct,
bg_do_rmw_partial,
bg_do_lmr_read,
bg_do_refresh_1bank,
bg_do_zq_cal,
bg_do_lmr,
bg_localid,
bg_dataid,
bg_size,
// burst generator address signals
bg_to_chip, // active high input (one hot)
bg_to_bank,
bg_to_row,
bg_to_col,
bg_to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_rst_n,
afi_odt
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam CFG_FR_DWIDTH_RATIO = 2;
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk ;
input ctl_reset_n ;
input ctl_cal_success ;
//run-time csr chain input
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type ;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl ;
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat ;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat ;
input [CFG_PORT_WIDTH_WRITE_ODT_CHIP - 1 : 0] cfg_write_odt_chip ;
input [CFG_PORT_WIDTH_READ_ODT_CHIP - 1 : 0] cfg_read_odt_chip ;
input [4:0] cfg_burst_length ;
//output regd signal from rdwr_tmg block
input [CFG_PORT_WIDTH_OUTPUT_REGD - 1 : 0] cfg_output_regd_for_afi_output;
//command inputs
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_auto_precharge ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_correct ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_rmw_partial ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_precharge_all ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_power_down ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_zq_cal ;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_lmr ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH) - 1 : 0] bg_to_bank ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row ;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col ;
input bg_do_lmr_read ;
input bg_do_refresh_1bank ;
input [2:0] bg_to_lmr ;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] bg_localid ;
input [CFG_DATA_ID_WIDTH - 1 : 0] bg_dataid ;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_size ;
input [CFG_MEM_IF_ADDR_WIDTH-1:0] lmr_opcode ;
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
output [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
output [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// port type declaration
// -----------------------------
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke ;
reg [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_ras_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_cas_n ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_we_n ;
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_ba ;
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n ;
reg [(CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_odt ;
// -----------------------------
// signal declaration
// -----------------------------
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_correct ;
reg [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rmw_partial ;
wire [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_ras_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_cas_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_we_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba [(CFG_DWIDTH_RATIO/2)-1:0];
wire [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rst_n [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_correct [(CFG_DWIDTH_RATIO/2)-1:0];
wire int_afi_rmw_partial [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CKE_WIDTH - 1:0] int_afi_cke_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_CHIP- 1:0] int_afi_cs_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_ras_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_cas_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_we_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_BA_WIDTH - 1:0] int_afi_ba_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [CFG_MEM_IF_ADDR_WIDTH-1:0] int_afi_addr_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rst_n_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_correct_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg int_afi_rmw_partial_r [(CFG_DWIDTH_RATIO/2)-1:0];
reg [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] phase_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] phase_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_ddrx_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_ddrx_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] int_lpddr2_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [(CFG_FR_DWIDTH_RATIO/2) - 1:0] int_lpddr2_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cke ;
wire [(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_cs_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_ras_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_cas_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_we_n ;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_ba ;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) - 1:0] fr_afi_addr ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rst_n ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_correct ;
wire [(CFG_FR_DWIDTH_RATIO/2) - 1:0] fr_afi_rmw_partial ;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_cs_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_ras_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_cas_n;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_we_n;
wire [(CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_ba;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] lpddr2_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] lpddr2_rst_n;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_write ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_read ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_chop ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_burst_terminate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_auto_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_activate ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_precharge ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_correct_r ;
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_rmw_partial_r ;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_precharge_all [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_self_refresh [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_power_down [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_deep_pdown [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_CHIP - 1 : 0] int_bg_do_zq_cal [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] int_bg_do_lmr ;
reg [CFG_MEM_IF_CHIP -1:0] int_bg_to_chip [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH -1:0] int_bg_to_bank [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH -1:0] int_bg_to_row [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH -1:0] int_bg_to_col [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_LOCAL_ID_WIDTH - 1 : 0] int_bg_localid;
reg [CFG_DATA_ID_WIDTH - 1 : 0] int_bg_dataid;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_bg_size;
reg int_bg_do_lmr_read;
reg int_bg_do_refresh_1bank;
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
wire [(CFG_MEM_IF_ODT_WIDTH*(CFG_DWIDTH_RATIO/2)) - 1 : 0] mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1:0];
reg [CFG_AFI_INTF_PHASE_NUM - 1 : 0] cfg_enable_chipsel_for_sideband;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_self_refresh_r;
reg [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_do_deep_pdown_r;
wire one = 1'b1;
wire zero = 1'b0;
// -----------------------------
// module definition
// -----------------------------
genvar afi_j, afi_n;
generate
// map int_afi_* multi-dimensional array signals to afi_* output port signals
for (afi_n = 0; afi_n < (CFG_DWIDTH_RATIO/2); afi_n = afi_n + 1'b1)
begin : gen_afi_signals
always @ (*)
begin
if (cfg_output_regd_for_afi_output == 2)
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke_r [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n_r [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n_r [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n_r [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n_r [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba_r [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr_r [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n_r [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct_r [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial_r [afi_n] ;
end
else
begin
afi_cke [((afi_n+1) * CFG_MEM_IF_CKE_WIDTH) -1 : (afi_n * CFG_MEM_IF_CKE_WIDTH)] = int_afi_cke [afi_n] ;
afi_cs_n [((afi_n+1) * CFG_MEM_IF_CHIP) -1 : (afi_n * CFG_MEM_IF_CHIP)] = int_afi_cs_n [afi_n] ;
afi_ras_n [afi_n] = int_afi_ras_n [afi_n] ;
afi_cas_n [afi_n] = int_afi_cas_n [afi_n] ;
afi_we_n [afi_n] = int_afi_we_n [afi_n] ;
afi_ba [((afi_n+1) * CFG_MEM_IF_BA_WIDTH) -1 : (afi_n * CFG_MEM_IF_BA_WIDTH)] = int_afi_ba [afi_n] ;
afi_addr [((afi_n+1) * CFG_MEM_IF_ADDR_WIDTH)-1 : (afi_n * CFG_MEM_IF_ADDR_WIDTH)] = int_afi_addr [afi_n] ;
afi_rst_n [afi_n] = int_afi_rst_n [afi_n] ;
afi_rmw_correct [afi_n] = int_afi_rmw_correct [afi_n] ;
afi_rmw_partial [afi_n] = int_afi_rmw_partial [afi_n] ;
end
end
end
// generate int_afi_* signals based on CFG_DWIDTH_RATIO & CFG_AFI_INTF_PHASE_NUM
if (CFG_DWIDTH_RATIO == 2)
begin
// full rate, with any phase
assign int_afi_cke [0] = fr_afi_cke ;
assign int_afi_cs_n [0] = fr_afi_cs_n ;
assign int_afi_ras_n [0] = fr_afi_ras_n ;
assign int_afi_cas_n [0] = fr_afi_cas_n ;
assign int_afi_we_n [0] = fr_afi_we_n ;
assign int_afi_ba [0] = fr_afi_ba ;
assign int_afi_addr [0] = fr_afi_addr ;
assign int_afi_rst_n [0] = fr_afi_rst_n ;
assign int_afi_rmw_correct [0] = fr_afi_rmw_correct ;
assign int_afi_rmw_partial [0] = fr_afi_rmw_partial ;
end
else if ((CFG_DWIDTH_RATIO/2) == CFG_AFI_INTF_PHASE_NUM)
begin
// map phase_afi_* signals to int_afi_* signals
// half rate , with phase=2
// quarter rate, with phase=4
for (afi_j = 0; afi_j < CFG_AFI_INTF_PHASE_NUM; afi_j = afi_j + 1'b1)
begin : gen_afi_signals_0
assign int_afi_cke [afi_j] = phase_afi_cke [afi_j] ;
assign int_afi_cs_n [afi_j] = phase_afi_cs_n [afi_j] ;
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j] ;
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j] ;
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j] ;
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j] ;
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j] ;
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j] ;
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j] ;
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j] ;
end
end
else // only supports case CFG_AFI_INTF_PHASE_NUM < (CFG_DWIDTH_RATIO/2)
begin
// map phase_afi_* signals to selected int_afi_* signals, and drive the rest to default values
// for cs_n signals:
// half rate , with phase=1, drives int_afi_* 1 only
// quarter rate , with phase=2, drives int_afi_* 1 & 3
// for other signals:
// half rate , with phase=1, drives int_afi_* 0 & 1 with the same value
// quarter rate , with phase=2, drives int_afi_* 0 & 1 or 2 & 3 with the same value
// Why? to improve timing margin on PHY side
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_1
// Assign even phase with '1' because we only issue on odd phase (2T timing)
assign int_afi_cs_n [afi_j] = ((afi_j % CFG_AFI_INTF_PHASE_NUM) == 1) ? phase_afi_cs_n [afi_j / CFG_AFI_INTF_PHASE_NUM] : { CFG_MEM_IF_CHIP {1'b1} };
// Assign the last CKE with phase_afi_cs_n[1], the rest with phase_afi_cs_n[0]
assign int_afi_cke [afi_j] = (afi_j == ((CFG_DWIDTH_RATIO/2) - 1)) ? phase_afi_cke [1] : phase_afi_cke [0];
assign int_afi_ras_n [afi_j] = phase_afi_ras_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_cas_n [afi_j] = phase_afi_cas_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_we_n [afi_j] = phase_afi_we_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_ba [afi_j] = phase_afi_ba [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_addr [afi_j] = phase_afi_addr [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rst_n [afi_j] = phase_afi_rst_n [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_correct [afi_j] = phase_afi_rmw_correct [afi_j / CFG_AFI_INTF_PHASE_NUM];
assign int_afi_rmw_partial [afi_j] = phase_afi_rmw_partial [afi_j / CFG_AFI_INTF_PHASE_NUM];
end
end
for (afi_j = 0; afi_j < (CFG_DWIDTH_RATIO/2); afi_j = afi_j + 1)
begin : gen_afi_signals_r
// Registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_afi_cke_r [afi_j] <= 0;
int_afi_cs_n_r [afi_j] <= 0;
int_afi_ras_n_r [afi_j] <= 0;
int_afi_cas_n_r [afi_j] <= 0;
int_afi_we_n_r [afi_j] <= 0;
int_afi_ba_r [afi_j] <= 0;
int_afi_addr_r [afi_j] <= 0;
int_afi_rst_n_r [afi_j] <= 0;
int_afi_rmw_correct_r [afi_j] <= 0;
int_afi_rmw_partial_r [afi_j] <= 0;
end
else
begin
int_afi_cke_r [afi_j] <= int_afi_cke [afi_j];
int_afi_cs_n_r [afi_j] <= int_afi_cs_n [afi_j];
int_afi_ras_n_r [afi_j] <= int_afi_ras_n [afi_j];
int_afi_cas_n_r [afi_j] <= int_afi_cas_n [afi_j];
int_afi_we_n_r [afi_j] <= int_afi_we_n [afi_j];
int_afi_ba_r [afi_j] <= int_afi_ba [afi_j];
int_afi_addr_r [afi_j] <= int_afi_addr [afi_j];
int_afi_rst_n_r [afi_j] <= int_afi_rst_n [afi_j];
int_afi_rmw_correct_r [afi_j] <= int_afi_rmw_correct [afi_j];
int_afi_rmw_partial_r [afi_j] <= int_afi_rmw_partial [afi_j];
end
end
end
endgenerate
// phase_afi_* signal generation
// instantiates an alt_mem_ddrx_addr_cmd for every phase
// maps bg_* signals to the correct instantiation
genvar afi_k;
generate
for (afi_k = 0; afi_k < CFG_AFI_INTF_PHASE_NUM; afi_k = afi_k + 1)
begin : gen_bg_afi_signal_decode
always @ (*)
begin
int_bg_do_write [afi_k] = bg_do_write [afi_k];
int_bg_do_read [afi_k] = bg_do_read [afi_k];
int_bg_do_burst_chop [afi_k] = bg_do_burst_chop [afi_k];
int_bg_do_burst_terminate [afi_k] = bg_do_burst_terminate [afi_k];
int_bg_do_auto_precharge [afi_k] = bg_do_auto_precharge [afi_k];
int_bg_do_rmw_correct [afi_k] = bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial [afi_k] = bg_do_rmw_partial [afi_k];
int_bg_do_activate [afi_k] = bg_do_activate [afi_k];
int_bg_do_precharge [afi_k] = bg_do_precharge [afi_k];
int_bg_to_chip [afi_k] = bg_to_chip [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_to_bank [afi_k] = bg_to_bank [(((afi_k+1)*CFG_MEM_IF_BA_WIDTH )-1):(afi_k*CFG_MEM_IF_BA_WIDTH )];
int_bg_to_row [afi_k] = bg_to_row [(((afi_k+1)*CFG_MEM_IF_ROW_WIDTH)-1):(afi_k*CFG_MEM_IF_ROW_WIDTH)];
int_bg_to_col [afi_k] = bg_to_col [(((afi_k+1)*CFG_MEM_IF_COL_WIDTH)-1):(afi_k*CFG_MEM_IF_COL_WIDTH)];
end
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_refresh [afi_k] = bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_self_refresh [afi_k] = bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_deep_pdown [afi_k] = bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_zq_cal [afi_k] = bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )];
int_bg_do_lmr [afi_k] = bg_do_lmr [afi_k];
end
always @ (*)
begin
cfg_enable_chipsel_for_sideband [afi_k] = one;
end
end
else // half and quarter rate
begin
always @ (*)
begin
int_bg_do_precharge_all [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_precharge_all [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_zq_cal [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_zq_cal [(((afi_k+1)*CFG_MEM_IF_CHIP )-1):(afi_k*CFG_MEM_IF_CHIP )] : {CFG_MEM_IF_CHIP{1'b0}};
int_bg_do_lmr [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_lmr [afi_k ] : 1'b0;
// We need to assign these command to all phase
// because these command might take one or more controller clock cycles
// and we want to prevent CKE from toggling due to prolong commands
int_bg_do_power_down [afi_k] = bg_do_power_down [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_self_refresh [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_self_refresh [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_self_refresh_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
int_bg_do_deep_pdown [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] :
bg_do_deep_pdown [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)] & bg_do_deep_pdown_r [(((afi_k+1)*CFG_MEM_IF_CHIP)-1):(afi_k*CFG_MEM_IF_CHIP)];
end
always @ (*)
begin
// We need to disable one phase of chipsel logic for sideband in half/quarter rate
// in order to prevent CS_N from going low for 2 clock cycles (deep power down and self refresh only)
cfg_enable_chipsel_for_sideband [afi_k] = ((afi_k % CFG_AFI_INTF_PHASE_NUM) == 1) ? one : zero;
end
end
// addresss command block instantiated based on number of phases
alt_mem_ddrx_addr_cmd # (
.CFG_PORT_WIDTH_TYPE ( CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_OUTPUT_REGD ( CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP ( CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH ( CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH ( CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH ( CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH ( CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH ( CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO ( CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_addr_cmd_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_cal_success ( ctl_cal_success ),
.cfg_type ( cfg_type ),
.cfg_output_regd ( cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband ( cfg_enable_chipsel_for_sideband [afi_k] ),
.bg_do_write ( int_bg_do_write [afi_k] ),
.bg_do_read ( int_bg_do_read [afi_k] ),
.bg_do_auto_precharge ( int_bg_do_auto_precharge [afi_k] ),
.bg_do_burst_chop ( int_bg_do_burst_chop [afi_k] ),
.bg_do_activate ( int_bg_do_activate [afi_k] ),
.bg_do_precharge ( int_bg_do_precharge [afi_k] ),
.bg_do_refresh ( int_bg_do_refresh [afi_k] ),
.bg_do_power_down ( int_bg_do_power_down [afi_k] ),
.bg_do_self_refresh ( int_bg_do_self_refresh [afi_k] ),
.bg_do_lmr ( int_bg_do_lmr [afi_k] ),
.bg_do_precharge_all ( int_bg_do_precharge_all [afi_k] ),
.bg_do_zq_cal ( int_bg_do_zq_cal [afi_k] ),
.bg_do_deep_pdown ( int_bg_do_deep_pdown [afi_k] ),
.bg_do_burst_terminate ( int_bg_do_burst_terminate [afi_k] ),
.bg_to_chip ( int_bg_to_chip [afi_k] ),
.bg_to_bank ( int_bg_to_bank [afi_k] ),
.bg_to_row ( int_bg_to_row [afi_k] ),
.bg_to_col ( int_bg_to_col [afi_k] ),
.bg_to_lmr ( bg_to_lmr ),
.lmr_opcode ( lmr_opcode ),
.afi_cke ( int_ddrx_afi_cke [afi_k] ),
.afi_cs_n ( int_ddrx_afi_cs_n [afi_k] ),
.afi_ras_n ( int_ddrx_afi_ras_n [afi_k] ),
.afi_cas_n ( int_ddrx_afi_cas_n [afi_k] ),
.afi_we_n ( int_ddrx_afi_we_n [afi_k] ),
.afi_ba ( int_ddrx_afi_ba [afi_k] ),
.afi_addr ( int_ddrx_afi_addr [afi_k] ),
.afi_rst_n ( int_ddrx_afi_rst_n [afi_k] )
);
if (CFG_LPDDR2_ENABLED)
begin
alt_mem_ddrx_lpddr2_addr_cmd # (
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_CKE_WIDTH (CFG_MEM_IF_CKE_WIDTH ),
.CFG_MEM_IF_ADDR_WIDTH (CFG_MEM_IF_ADDR_WIDTH ),
.CFG_MEM_IF_ROW_WIDTH (CFG_MEM_IF_ROW_WIDTH ),
.CFG_MEM_IF_COL_WIDTH (CFG_MEM_IF_COL_WIDTH ),
.CFG_MEM_IF_BA_WIDTH (CFG_MEM_IF_BA_WIDTH ),
.CFG_DWIDTH_RATIO (CFG_FR_DWIDTH_RATIO )
) alt_mem_ddrx_lpddr2_addr_cmd_inst (
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.ctl_cal_success (ctl_cal_success ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.cfg_enable_chipsel_for_sideband (cfg_enable_chipsel_for_sideband [afi_k]),
.do_write (int_bg_do_write [afi_k]),
.do_read (int_bg_do_read [afi_k]),
.do_auto_precharge (int_bg_do_auto_precharge [afi_k]),
.do_activate (int_bg_do_activate [afi_k]),
.do_precharge (int_bg_do_precharge [afi_k]),
.do_refresh (int_bg_do_refresh [afi_k]),
.do_power_down (int_bg_do_power_down [afi_k]),
.do_self_refresh (int_bg_do_self_refresh [afi_k]),
.do_lmr (int_bg_do_lmr [afi_k]),
.do_precharge_all (int_bg_do_precharge_all [afi_k]),
.do_deep_pwrdwn (int_bg_do_deep_pdown [afi_k]),
.do_burst_terminate (int_bg_do_burst_terminate [afi_k]),
.do_lmr_read (int_bg_do_lmr_read ),
.do_refresh_1bank (int_bg_do_refresh_1bank ),
.to_chip (int_bg_to_chip [afi_k]),
.to_bank (int_bg_to_bank [afi_k]),
.to_row (int_bg_to_row [afi_k]),
.to_col (int_bg_to_col [afi_k]),
.to_lmr (bg_to_lmr ),
.lmr_opcode (lmr_opcode[7:0] ),
.afi_cke (int_lpddr2_afi_cke [afi_k]),
.afi_cs_n (int_lpddr2_afi_cs_n [afi_k]),
.afi_addr (int_lpddr2_afi_addr [afi_k]),
.afi_rst_n (int_lpddr2_afi_rst_n [afi_k])
);
end
else
begin
assign int_lpddr2_afi_cke [afi_k] = {(CFG_MEM_IF_CKE_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_cs_n [afi_k] = {(CFG_MEM_IF_CHIP * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_addr [afi_k] = {(CFG_MEM_IF_ADDR_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
assign int_lpddr2_afi_rst_n [afi_k] = { (CFG_FR_DWIDTH_RATIO/2) {1'b0}};
end
always @ (*)
begin
// Mux to select ddrx or lpddr2 addrcmd decoder blocks
if (cfg_type == `MMR_TYPE_LPDDR2)
begin
phase_afi_cke [afi_k] = int_lpddr2_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_lpddr2_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_cas_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_we_n [afi_k] = {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
phase_afi_ba [afi_k] = {(CFG_MEM_IF_BA_WIDTH * (CFG_FR_DWIDTH_RATIO/2)) {1'b0}};
phase_afi_addr [afi_k] = int_lpddr2_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_lpddr2_afi_rst_n[afi_k] ;
end
else
begin
phase_afi_cke [afi_k] = int_ddrx_afi_cke [afi_k] ;
phase_afi_cs_n [afi_k] = int_ddrx_afi_cs_n [afi_k] ;
phase_afi_ras_n [afi_k] = int_ddrx_afi_ras_n [afi_k] ;
phase_afi_cas_n [afi_k] = int_ddrx_afi_cas_n [afi_k] ;
phase_afi_we_n [afi_k] = int_ddrx_afi_we_n [afi_k] ;
phase_afi_ba [afi_k] = int_ddrx_afi_ba [afi_k] ;
phase_afi_addr [afi_k] = int_ddrx_afi_addr [afi_k] ;
phase_afi_rst_n [afi_k] = int_ddrx_afi_rst_n [afi_k] ;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_bg_do_rmw_correct_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
int_bg_do_rmw_partial_r[afi_k] <= {(CFG_FR_DWIDTH_RATIO/2){1'b0}};
end
else
begin
int_bg_do_rmw_correct_r[afi_k] <= int_bg_do_rmw_correct [afi_k];
int_bg_do_rmw_partial_r[afi_k] <= int_bg_do_rmw_partial [afi_k];
end
end
always @ (*)
begin
if (cfg_output_regd_for_afi_output)
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct_r [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial_r [afi_k];
end
else
begin
phase_afi_rmw_correct[afi_k] = int_bg_do_rmw_correct [afi_k];
phase_afi_rmw_partial[afi_k] = int_bg_do_rmw_partial [afi_k];
end
end
alt_mem_ddrx_odt_gen #
(
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO ),
.CFG_ODT_ENABLED (CFG_ODT_ENABLED ),
.CFG_MEM_IF_CHIP (CFG_MEM_IF_CHIP ),
.CFG_MEM_IF_ODT_WIDTH (CFG_MEM_IF_ODT_WIDTH ),
.CFG_PORT_WIDTH_CAS_WR_LAT (CFG_PORT_WIDTH_CAS_WR_LAT ),
.CFG_PORT_WIDTH_TCL (CFG_PORT_WIDTH_TCL ),
.CFG_PORT_WIDTH_ADD_LAT (CFG_PORT_WIDTH_ADD_LAT ),
.CFG_PORT_WIDTH_TYPE (CFG_PORT_WIDTH_TYPE ),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP (CFG_PORT_WIDTH_WRITE_ODT_CHIP ),
.CFG_PORT_WIDTH_READ_ODT_CHIP (CFG_PORT_WIDTH_READ_ODT_CHIP ),
.CFG_PORT_WIDTH_OUTPUT_REGD (CFG_PORT_WIDTH_OUTPUT_REGD )
)
odt_gen_inst
(
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.cfg_type (cfg_type ),
.cfg_tcl (cfg_tcl ),
.cfg_cas_wr_lat (cfg_cas_wr_lat ),
.cfg_add_lat (cfg_add_lat ),
.cfg_write_odt_chip (cfg_write_odt_chip ),
.cfg_read_odt_chip (cfg_read_odt_chip ),
.cfg_burst_length (cfg_burst_length ),
.cfg_output_regd (cfg_output_regd_for_afi_output ),
.bg_do_read (int_bg_do_read [afi_k]),
.bg_do_write (int_bg_do_write [afi_k]),
.bg_do_burst_chop (int_bg_do_burst_chop [afi_k]),
.bg_to_chip (int_bg_to_chip [afi_k]),
.afi_odt (afi_odt_h_l [afi_k])
);
end
always @ (*)
begin
int_bg_dataid = bg_dataid;
int_bg_localid = bg_localid;
int_bg_size = bg_size;
int_bg_do_lmr_read = bg_do_lmr_read;
int_bg_do_refresh_1bank = bg_do_refresh_1bank;
end
endgenerate
// ODT output generation
always @ (*)
begin
afi_odt = mux_afi_odt_h_l [CFG_AFI_INTF_PHASE_NUM-1];
end
// generate ODT output signal from odt_gen
assign mux_afi_odt_h_l [0] = afi_odt_h_l [0];
genvar afi_m;
generate
for (afi_m = 1; afi_m < CFG_AFI_INTF_PHASE_NUM; afi_m = afi_m + 1)
begin : mux_for_odt
assign mux_afi_odt_h_l [afi_m] = mux_afi_odt_h_l [afi_m-1] | afi_odt_h_l [afi_m];
end
endgenerate
// generate fr_* signals from phase_* signals
assign mux_afi_cke [0] = phase_afi_cke [0];
assign mux_afi_cs_n [0] = phase_afi_cs_n [0];
assign mux_afi_ras_n [0] = phase_afi_ras_n [0];
assign mux_afi_cas_n [0] = phase_afi_cas_n [0];
assign mux_afi_we_n [0] = phase_afi_we_n [0];
assign mux_afi_ba [0] = phase_afi_ba [0];
assign mux_afi_addr [0] = phase_afi_addr [0];
assign mux_afi_rst_n [0] = phase_afi_rst_n [0];
assign mux_afi_rmw_correct [0] = phase_afi_rmw_correct [0];
assign mux_afi_rmw_partial [0] = phase_afi_rmw_partial [0];
genvar afi_l;
generate
for (afi_l = 1; afi_l < CFG_AFI_INTF_PHASE_NUM; afi_l = afi_l + 1)
begin : gen_resolve_phase_for_fullrate
assign mux_afi_cke [afi_l] = mux_afi_cke [(afi_l-1)] & phase_afi_cke [afi_l];
assign mux_afi_cs_n [afi_l] = mux_afi_cs_n [(afi_l-1)] & phase_afi_cs_n [afi_l];
assign mux_afi_ras_n [afi_l] = mux_afi_ras_n [(afi_l-1)] & phase_afi_ras_n [afi_l];
assign mux_afi_cas_n [afi_l] = mux_afi_cas_n [(afi_l-1)] & phase_afi_cas_n [afi_l];
assign mux_afi_we_n [afi_l] = mux_afi_we_n [(afi_l-1)] & phase_afi_we_n [afi_l];
assign mux_afi_ba [afi_l] = mux_afi_ba [(afi_l-1)] | phase_afi_ba [afi_l];
assign mux_afi_addr [afi_l] = mux_afi_addr [(afi_l-1)] | phase_afi_addr [afi_l];
assign mux_afi_rst_n [afi_l] = mux_afi_rst_n [(afi_l-1)] | phase_afi_rst_n [afi_l];
assign mux_afi_rmw_correct [afi_l] = mux_afi_rmw_correct [(afi_l-1)] | phase_afi_rmw_correct [afi_l];
assign mux_afi_rmw_partial [afi_l] = mux_afi_rmw_partial [(afi_l-1)] | phase_afi_rmw_partial [afi_l];
end
endgenerate
assign fr_afi_cke = mux_afi_cke [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cs_n = mux_afi_cs_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ras_n = mux_afi_ras_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_cas_n = mux_afi_cas_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_we_n = mux_afi_we_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_ba = mux_afi_ba [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_addr = mux_afi_addr [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rst_n = mux_afi_rst_n [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_correct = mux_afi_rmw_correct [CFG_AFI_INTF_PHASE_NUM-1];
assign fr_afi_rmw_partial = mux_afi_rmw_partial [CFG_AFI_INTF_PHASE_NUM-1];
// Registered version of self refresh and power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bg_do_self_refresh_r <= 0;
bg_do_deep_pdown_r <= 0;
end
else
begin
bg_do_self_refresh_r <= bg_do_self_refresh;
bg_do_deep_pdown_r <= bg_do_deep_pdown;
end
end
endmodule
|
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*########################################################################
AXI WRAPPER FOR ECFG BLOCK
########################################################################
*/
module axi_ecfg (/*AUTOARG*/
// Outputs
s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid,
esys_tx_enable, esys_tx_mmu_mode, esys_tx_gpio_mode,
esys_tx_ctrl_mode, esys_tx_clkdiv, esys_rx_enable,
esys_rx_mmu_mode, esys_rx_gpio_mode, esys_rx_loopback_mode,
esys_cclk_div, esys_cclk_pllcfg, esys_coreid, esys_dataout,
esys_irqsrc_read,
// Inputs
s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_rready, param_coreid, erx_irq_fifo_src, erx_irq_fifo_data,
erx_rdfifo_access, erx_rdfifo_wait, erx_wrfifo_access,
erx_wrfifo_wait, erx_wbfifo_access, erx_wbfifo_wait,
etx_rdfifo_access, etx_rdfifo_wait, etx_wrfifo_access,
etx_wrfifo_wait, etx_wbfifo_access, etx_wbfifo_wait
);
//Register file parameters
/*
#####################################################################
COMPILE TIME PARAMETERS
######################################################################
*/
parameter DW = 32; //elink monitor register width
parameter AW = 32; //mmu table address width
parameter SW = DW/8; //mmu table address width
parameter MAW = 6; //register file address width
parameter MDW = 32; //
parameter IDW = 12; //Elink ID (row,column coordinate)
/*****************************/
/*AXI SLAVE INTERFACE (LITE) */
/*****************************/
//Global signals
input s_axi_aclk; //clock source for axi slave interfaces
input s_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
input [AW-1:0] s_axi_awaddr; //write address
input [2:0] s_axi_awprot; //write protection type
input s_axi_awvalid; //write address valid
output s_axi_awready; //write address ready
//Write data channel
input [DW-1:0] s_axi_wdata; //write data
input [SW-1:0] s_axi_wstrb; //write strobes
input s_axi_wvalid; //write valid
output s_axi_wready; //write channel ready
//Buffered write response channel
input s_axi_bready; //write ready
output [1:0] s_axi_bresp; //write response
output s_axi_bvalid; //write response valid
//Read address channel
input [AW-1:0] s_axi_araddr; //read address
input [2:0] s_axi_arprot; //read protection type
input s_axi_arvalid; //read address valid
output s_axi_arready; //read address ready
//Read data channel
output [DW-1:0] s_axi_rdata; //read data
output [1:0] s_axi_rresp; //read response
output s_axi_rvalid; //read valid
input s_axi_rready; //read ready
/*****************************/
/*STATIC SIGNALS */
/*****************************/
input [IDW-1:0] param_coreid;
/*****************************/
/*ELINK DATAPATH INPUTS */
/*****************************/
input [11:0] erx_irq_fifo_src;
input [11:0] erx_irq_fifo_data;
input erx_rdfifo_access;
input erx_rdfifo_wait;
input erx_wrfifo_access;
input erx_wrfifo_wait;
input erx_wbfifo_access;
input erx_wbfifo_wait;
input etx_rdfifo_access;
input etx_rdfifo_wait;
input etx_wrfifo_access;
input etx_wrfifo_wait;
input etx_wbfifo_access;
input etx_wbfifo_wait;
/*****************************/
/*ECFG CONTROL OUTPUTS */
/*****************************/
//tx
output esys_tx_enable; //enable signal for TX
output esys_tx_mmu_mode; //enables MMU on transnmit path
output esys_tx_gpio_mode; //forces TX output pins to constants
output [3:0] esys_tx_ctrl_mode; //value for emesh ctrlmode tag
output [3:0] esys_tx_clkdiv; //transmit clock divider
//rx
output esys_rx_enable; //enable signal for rx
output esys_rx_mmu_mode; //enables MMU on rx path
output esys_rx_gpio_mode; //forces rx wait pins to constants
output esys_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
//cclk
output [3:0] esys_cclk_div; //cclk divider setting
output [3:0] esys_cclk_pllcfg; //pll configuration
//coreid
output [11:0] esys_coreid; //core-id for fpga elink
//gpio
output [11:0] esys_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
//irq
output esys_irqsrc_read; //increments the irq fifo pointer
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
wire [11:0] ecfg_dataout; // From ecfg of ecfg.v
wire ecfg_rx_enable; // From ecfg of ecfg.v
wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
wire ecfg_rx_loopback_mode; // From ecfg of ecfg.v
wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
wire ecfg_tx_enable; // From ecfg of ecfg.v
wire ecfg_tx_gpio_mode; // From ecfg of ecfg.v
wire ecfg_tx_mmu_mode; // From ecfg of ecfg.v
wire mi_access; // From axi_memif of axi_memif.v
wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
wire [MDW-1:0] mi_data_in; // From axi_memif of axi_memif.v
wire [31:0] mi_data_out; // From ecfg of ecfg.v
wire mi_write; // From axi_memif of axi_memif.v
// End of automatics
axi_memif axi_memif(/*AUTOINST*/
// Outputs
.s_axi_awready (s_axi_awready),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata[DW-1:0]),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.mi_addr (mi_addr[MAW-1:0]),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_data_in (mi_data_in[MDW-1:0]),
// Inputs
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_wdata (s_axi_wdata[DW-1:0]),
.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr[AW-1:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_rready (s_axi_rready),
.mi_data_out (mi_data_out[MDW-1:0]));
ecfg ecfg(
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[31:0]),
.ecfg_tx_enable (ecfg_tx_enable),
.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
.ecfg_rx_enable (ecfg_rx_enable),
.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
.ecfg_rx_loopback_mode (ecfg_rx_loopback_mode),
.ecfg_cclk_div (ecfg_cclk_div[3:0]),
.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
.ecfg_coreid (ecfg_coreid[11:0]),
.ecfg_dataout (ecfg_dataout[11:0]),
// Inputs
.param_coreid (param_coreid[IDW-1:0]),
.clk (clk),
.reset (reset),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[5:0]),
.mi_data_in (mi_data_in[31:0]));
endmodule // axi_ecfg
// Local Variables:
// verilog-library-directories:("." "../axi")
// End:
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1421777838 : 2899645186;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub4 (/*AUTOARG*/
// Outputs
outq,
// Inputs
index
);
input [7:0] index;
output [9:0] outq;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [9:0] outq;
// End of automatics
// =============================
always @(/*AS*/index) begin
case (index)
// default below: no change
8'h00: begin outq = 10'h001; end
8'he0: begin outq = 10'h05b; end
8'he1: begin outq = 10'h126; end
8'he2: begin outq = 10'h369; end
8'he3: begin outq = 10'h291; end
8'he4: begin outq = 10'h2ca; end
8'he5: begin outq = 10'h25b; end
8'he6: begin outq = 10'h106; end
8'he7: begin outq = 10'h172; end
8'he8: begin outq = 10'h2f7; end
8'he9: begin outq = 10'h2d3; end
8'hea: begin outq = 10'h182; end
8'heb: begin outq = 10'h327; end
8'hec: begin outq = 10'h1d0; end
8'hed: begin outq = 10'h204; end
8'hee: begin outq = 10'h11f; end
8'hef: begin outq = 10'h365; end
8'hf0: begin outq = 10'h2c2; end
8'hf1: begin outq = 10'h2b5; end
8'hf2: begin outq = 10'h1f8; end
8'hf3: begin outq = 10'h2a7; end
8'hf4: begin outq = 10'h1be; end
8'hf5: begin outq = 10'h25e; end
8'hf6: begin outq = 10'h032; end
8'hf7: begin outq = 10'h2ef; end
8'hf8: begin outq = 10'h02f; end
8'hf9: begin outq = 10'h201; end
8'hfa: begin outq = 10'h054; end
8'hfb: begin outq = 10'h013; end
8'hfc: begin outq = 10'h249; end
8'hfd: begin outq = 10'h09a; end
8'hfe: begin outq = 10'h012; end
8'hff: begin outq = 10'h114; end
default: ; // No change
endcase
end
endmodule
|
Require Import Coq.Strings.String.
Require Import Prog ProgMonad.
Require Import Log.
Require Import BFile.
Require Import Word.
Require Import Omega.
Require Import BasicProg.
Require Import Bool.
Require Import Pred PredCrash.
Require Import DirCache.
Require Import Hoare.
Require Import GenSepN.
Require Import ListPred.
Require Import SepAuto.
Require Import Idempotent.
Require Import Inode.
Require Import List ListUtils.
Require Import Balloc.
Require Import Bytes.
Require Import DirTree.
Require Import Rec.
Require Import Arith.
Require Import Array.
Require Import FSLayout.
Require Import Cache.
Require Import Errno.
Require Import AsyncDisk.
Require Import SyncedMem.
Require Import GroupLog.
Require Import DiskLogHash.
Require Import SuperBlock.
Require Import DiskSet.
Require Import Lia.
Require Import FunctionalExtensionality.
Require Import DirTreeDef.
Require Import DirTreeRep.
Require Import DirTreePred.
Require Import DirTreeInodes.
Require Import DirTreeSafe.
Set Implicit Arguments.
Import DirTree.
Import ListNotations.
Module AFS.
(* Programs *)
Definition compute_xparams (data_bitmaps inode_bitmaps log_descr_blocks : addr) :=
(**
* Block 0 stores the superblock (layout information).
* The other block numbers, except for Log, are relative to
* the Log data area, which starts at $1.
* To account for this, we bump [log_base] by $1, to ensure that
* the data area does not run into the logging structures.
*)
(**
* File system layout:
* +--------+--------+--------+-------+-------+-------+--------+-------+------+
* | Super- | Data | Inode | Inode | Data1 | Data2 | Log | Log | Log |
* | block | blocks | blocks | alloc | alloc | alloc | header | descr | data |
* +--------+--------+--------+-------+-------+-------+--------+-------+------+
**)
(* XXX: not quite right, fix later *)
let data_blocks := data_bitmaps * valulen in
let inode_blocks := inode_bitmaps * valulen / INODE.IRecSig.items_per_val in
let inode_base := data_blocks in
let balloc_base1 := inode_base + inode_blocks + inode_bitmaps in
let balloc_base2 := balloc_base1 + data_bitmaps in
let log_hdr := 1 + balloc_base2 + data_bitmaps in
let log_descr := log_hdr + 1 in
let log_data := log_descr + log_descr_blocks in
let log_data_size := log_descr_blocks * PaddedLog.DescSig.items_per_val in
let max_addr := log_data + log_data_size in
(Build_fs_xparams
(Build_log_xparams 1 log_hdr log_descr log_descr_blocks log_data log_data_size)
(Build_inode_xparams inode_base inode_blocks)
(Build_balloc_xparams balloc_base1 data_bitmaps)
(Build_balloc_xparams balloc_base2 data_bitmaps)
(Build_balloc_xparams (inode_base + inode_blocks) inode_bitmaps)
1
max_addr).
Lemma compute_xparams_ok : forall data_bitmaps inode_bitmaps log_descr_blocks magic,
goodSize addrlen magic ->
goodSize addrlen (1 +
data_bitmaps * valulen +
inode_bitmaps * valulen / INODE.IRecSig.items_per_val +
inode_bitmaps + data_bitmaps + data_bitmaps +
1 + log_descr_blocks + log_descr_blocks * PaddedLog.DescSig.items_per_val) ->
fs_xparams_ok (compute_xparams data_bitmaps inode_bitmaps log_descr_blocks magic).
Proof.
unfold fs_xparams_ok.
unfold log_xparams_ok, inode_xparams_ok, balloc_xparams_ok.
unfold compute_xparams; simpl.
intuition.
all: eapply goodSize_trans; try eassumption.
all: lia.
Qed.
Notation MSLL := BFILE.MSLL.
Notation MSAllocC := BFILE.MSAllocC.
Notation MSIAllocC := BFILE.MSIAllocC.
Notation MSICache := BFILE.MSICache.
Notation MSAlloc := BFILE.MSAlloc.
Notation MSDBlocks := BFILE.MSDBlocks.
Import DIRTREE.
Definition mkfs cachesize data_bitmaps inode_bitmaps log_descr_blocks :=
let fsxp := compute_xparams data_bitmaps inode_bitmaps log_descr_blocks SB.magic_number in
cs <- BUFCACHE.init_load cachesize;
cs <- SB.init fsxp cs;
mscs <- LOG.init (FSXPLog fsxp) cs;
mscs <- LOG.begin (FSXPLog fsxp) mscs;
ms <- BFILE.init (FSXPLog fsxp) (FSXPBlockAlloc1 fsxp, FSXPBlockAlloc2 fsxp) fsxp (FSXPInode fsxp) mscs;
let^ (ialloc_ms, r) <- IAlloc.alloc (FSXPLog fsxp) fsxp (BFILE.MSIAlloc ms);
let mscs := IAlloc.MSLog ialloc_ms in
match r with
| None =>
mscs <- LOG.abort (FSXPLog fsxp) mscs;
Ret (Err ENOSPCINODE)
| Some inum =>
(**
* We should write a new fsxp back to the superblock with the new root
* inode number.
* In practice, the root inode is always the same, so it doesn't matter.
*)
If (eq_nat_dec inum (FSXPRootInum fsxp)) {
let^ (mscs, ok) <- LOG.commit (FSXPLog fsxp) mscs;
If (bool_dec ok true) {
mscs <- LOG.flushsync (FSXPLog fsxp) mscs;
Ret (OK ((BFILE.mk_memstate (MSAlloc ms) mscs (MSAllocC ms) (IAlloc.MSCache ialloc_ms) (MSICache ms) (MSCache ms) (MSDBlocks ms)), fsxp))
} else {
Ret (Err ELOGOVERFLOW)
}
} else {
mscs <- LOG.abort (FSXPLog fsxp) mscs;
Ret (Err ELOGOVERFLOW)
}
end.
Lemma S_minus_1_helper : forall n a b,
S (n + 1 + a + b) - 1 - n = S (a + b).
Proof.
intros; omega.
Qed.
Lemma S_minus_1_helper2 : forall n,
S n - 1 = n.
Proof.
intros; omega.
Qed.
Ltac equate_log_rep :=
match goal with
| [ r : BFILE.memstate,
H : context [ compute_xparams ?a1 ?a2 ?a3 ?a4 ],
Hi: context [IAlloc.Alloc.rep _ _ _ _ ?x_]
|- LOG.rep ?xp ?F ?d ?ms _ _ =p=> LOG.rep ?xp' ?F' ?d' ?ms' _ _ * _ ] =>
equate d d'; equate ms' (MSLL (
BFILE.mk_memstate (MSAlloc r) ms (MSAllocC r) (IAlloc.MSCache x_) (MSICache r) (MSCache r) (MSDBlocks r)
));
equate xp' (FSXPLog (compute_xparams a1 a2 a3 a4))
| [ r : BFILE.memstate,
H : context [ compute_xparams ?a1 ?a2 ?a3 ?a4 ]
|- LOG.rep ?xp ?F ?d ?ms _ _ =p=> LOG.rep ?xp' ?F' ?d' ?ms' _ _ * _ ] =>
equate d d'; equate ms' (MSLL (
BFILE.mk_memstate (MSAlloc r) ms (MSAllocC r) (IAlloc.Alloc.freelist0) (MSICache r) (MSCache r) (MSDBlocks r)
));
equate xp' (FSXPLog (compute_xparams a1 a2 a3 a4))
end.
Theorem mkfs_ok : forall cachesize data_bitmaps inode_bitmaps log_descr_blocks,
{!!< disk,
PRE:vm,hm
arrayS 0 disk *
[[ cachesize <> 0 /\ data_bitmaps <> 0 /\ inode_bitmaps <> 0 ]] *
[[ data_bitmaps <= valulen * valulen /\ inode_bitmaps <= valulen * valulen ]] *
[[ length disk = 1 +
data_bitmaps * valulen +
inode_bitmaps * valulen / INODE.IRecSig.items_per_val +
inode_bitmaps + data_bitmaps + data_bitmaps +
1 + log_descr_blocks + log_descr_blocks * PaddedLog.DescSig.items_per_val ]] *
[[ goodSize addrlen (length disk) ]]
POST:vm',hm' RET:r exists ms fsxp d sm,
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (d, nil)) (MSLL ms) sm hm' *
[[ vm' = vm ]] *
( [[ isError r ]] \/ exists ilist frees,
[[ r = OK (ms, fsxp) ]] *
[[[ d ::: rep fsxp emp (TreeDir (FSXPRootInum fsxp) nil) ilist frees ms sm ]]] )
CRASH:hm'
any
>!!} mkfs cachesize data_bitmaps inode_bitmaps log_descr_blocks.
Proof.
unfold mkfs.
safestep.
prestep.
norml; unfold stars; simpl.
denote! (arrayS _ _ _) as Hx.
eapply arrayN_isolate_hd in Hx.
unfold ptsto_subset in Hx at 1.
safecancel.
apply compute_xparams_ok.
apply SB.goodSize_magic_number.
denote (length disk = _) as Heq; rewrite Heq in *; auto.
auto.
(* LOG.init *)
prestep. norm. cancel.
intuition simpl. pred_apply.
(* split LHS into log region and data region *)
erewrite arrayN_split at 1.
simpl.
rewrite sep_star_comm.
apply sep_star_assoc.
rewrite skipn_length.
setoid_rewrite skipn_length with (n := 1).
substl (length disk).
apply S_minus_1_helper.
rewrite firstn_length.
setoid_rewrite skipn_length with (n := 1).
substl (length disk).
rewrite Nat.min_l.
rewrite Nat.sub_0_r; auto.
rewrite S_minus_1_helper2.
generalize (data_bitmaps * valulen + inode_bitmaps * valulen / INODE.IRecSig.items_per_val); intros.
generalize (log_descr_blocks * PaddedLog.DescSig.items_per_val); intros.
omega.
eapply goodSize_trans; [ | eauto ].
rewrite skipn_length.
setoid_rewrite skipn_length with (n := 1).
substl (length disk).
generalize (data_bitmaps * valulen + inode_bitmaps * valulen / INODE.IRecSig.items_per_val); intros.
generalize (log_descr_blocks * PaddedLog.DescSig.items_per_val); intros.
omega.
auto.
auto.
step.
rewrite Nat.sub_0_r in *.
(* BFILE.init *)
step.
(* IAlloc.alloc *)
step.
step.
step.
step.
(* LOG.flushsync *)
step.
step.
rewrite latest_pushd.
equate_log_rep.
cancel. or_r.
unfold rep. cancel.
denote (_ =p=> freeinode_pred) as Hy.
denote (freeinode_pred =p=> _) as Hz.
rewrite <- Hy in Hz.
2: apply repeat_length with (x := BFILE.bfile0).
assert (1 < length (repeat BFILE.bfile0 (inode_bitmaps * valulen
/ INODE.IRecSig.items_per_val * INODE.IRecSig.items_per_val))) as Hlen.
rewrite repeat_length; omega.
specialize (Hz _ (list2nmem_array _)).
pred_apply; cancel.
pose proof (list2nmem_ptsto_cancel BFILE.bfile0 _ Hlen).
unfold tree_dir_names_pred.
cancel.
unfold BFILE.freepred in *. subst.
apply DirTreePred.SDIR.bfile0_empty.
apply emp_empty_mem.
eapply Forall_repeat.
eauto.
(* failure cases *)
apply pimpl_any.
step.
step.
step.
equate_log_rep.
cancel.
or_l; cancel.
apply pimpl_any.
step.
step.
equate_log_rep.
cancel.
or_l; cancel.
apply pimpl_any.
step.
equate_log_rep.
cancel.
or_l; cancel.
all: try solve [ try xcrash; apply pimpl_any ].
substl (length disk).
apply gt_Sn_O.
Unshelve.
all: try easy.
try exact ($0, nil).
Qed.
Definition recover cachesize :=
cs <- BUFCACHE.init_recover cachesize;
let^ (cs, fsxp) <- SB.load cs;
If (addr_eq_dec (FSXPMagic fsxp) SB.magic_number) {
mscs <- LOG.recover (FSXPLog fsxp) cs;
mscs <- BFILE.recover mscs;
Ret (OK (mscs, fsxp))
} else {
Ret (Err EINVAL)
}.
Definition file_get_attr fsxp inum ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, attr) <- DIRTREE.getattr fsxp inum (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), attr);
t2 <- Rdtsc ;
Debug "get_attr" (t2-t1) ;;
Ret r.
Definition file_get_sz fsxp inum ams :=
t1 <- Rdtsc ;
let^ (ams, attr) <- file_get_attr fsxp inum ams;
t2 <- Rdtsc ;
Debug "file_get_sz" (t2-t1) ;;
Ret ^(ams, INODE.ABytes attr).
Definition file_set_attr fsxp inum attr ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
ams' <- DIRTREE.setattr fsxp inum attr (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
let^ (ms', ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
If (bool_dec ok true) {
Ret ^((BFILE.mk_memstate (MSAlloc ams') ms' (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK tt)
} else {
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms' (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
}.
(* note that file_set_sz is not the same as ftruncate - it does not allocate
new blocks, but merely sets the size in the inode to the specified sz (in
bytes) *)
Definition file_set_sz fsxp inum sz ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
ams <- DIRTREE.updattr fsxp inum (INODE.UBytes sz) (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams);
If (bool_dec ok true) {
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), OK tt)
} else {
Ret ^(ams, Err ELOGOVERFLOW)
}.
Definition read_fblock fsxp inum off ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, b) <- DIRTREE.read fsxp inum off (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), b);
t2 <- Rdtsc ;
Debug "read_fblock" (t2-t1) ;;
Ret r.
(* note that file_truncate takes sz in blocks *)
Definition file_truncate fsxp inum sz ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams', ok) <- DIRTREE.truncate fsxp inum sz (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
r <- match ok with
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams');
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
| OK _ =>
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
If (bool_dec ok true) {
Ret ^((BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK tt)
} else {
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
}
end;
t2 <- Rdtsc ;
Debug "truncate" (t2-t1) ;;
Ret r.
(* ftruncate is an _unverified_ implementation of the ftruncate system call
(it is similar to the verified file_truncate code, but has some adjustments to
work in terms of bytes) *)
(* TODO: this code is not verified, although its core (DIRTREE.truncate and
DIRTREE.updattr) are, as well as [file_truncate]. *)
Definition ftruncate fsxp inum sz ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let sz_blocks := (sz + valulen - 1) / valulen in
let^ (ams', ok) <- DIRTREE.truncate fsxp inum sz_blocks (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
r <- match ok with
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams');
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
| OK _ =>
ams' <- DIRTREE.updattr fsxp inum (INODE.UBytes (addr2w sz)) (BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams'));
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
If (bool_dec ok true) {
Ret ^((BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK tt)
} else {
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)),
Err ELOGOVERFLOW)
}
end;
t2 <- Rdtsc ;
Debug "ftruncate" (t2-t1) ;;
Ret r.
(* update an existing block of an *existing* file with bypassing the log *)
Definition update_fblock_d fsxp inum off v ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
ams <- DIRTREE.dwrite fsxp inum off v (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)));
t2 <- Rdtsc ;
Debug "update_fblock_d" (t2-t1) ;;
Ret r.
Definition update_fblock fsxp inum off v ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
ams <- DIRTREE.write fsxp inum off v (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), ok);
t2 <- Rdtsc ;
Debug "update_fblock" (t2-t1) ;;
Ret r.
(* sync only data blocks of a file. *)
Definition file_sync fsxp inum ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
ams <- DIRTREE.datasync fsxp inum (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)));
t2 <- Rdtsc ;
Debug "file_sync" (t2-t1) ;;
Ret r.
Definition readdir fsxp dnum ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, files) <- SDIR.readdir (FSXPLog fsxp) (FSXPInode fsxp) dnum (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), files).
Definition create fsxp dnum name ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams', oi) <- DIRTREE.mkfile fsxp dnum name (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
r <- match oi with
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams');
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
| OK inum =>
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
match ok with
| true => Ret ^((BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK inum)
| false => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
end
end;
t2 <- Rdtsc ;
Debug "create" (t2-t1) ;;
Ret r.
Definition mksock fsxp dnum name ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, oi) <- DIRTREE.mkfile fsxp dnum name (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
match oi with
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams);
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
| OK inum =>
ams <- BFILE.updattr (FSXPLog fsxp) (FSXPInode fsxp) inum (INODE.UType $1) ams;
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams);
match ok with
| true => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), OK inum)
| false => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
end
end.
Definition mkdir fsxp dnum name ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, oi) <- DIRTREE.mkdir fsxp dnum name (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
match oi with
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams);
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
| OK inum =>
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams);
match ok with
| true => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), OK inum)
| false => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
end
end.
Definition delete fsxp dnum name ams :=
t1 <- Rdtsc;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams', ok) <- DIRTREE.delete fsxp dnum name (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
res <- match ok with
| OK _ =>
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
match ok with
| true => Ret ^((BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK tt)
| false => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
end
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams');
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
end;
t2 <- Rdtsc;
Debug "delete" (t2-t1);;
Ret res.
Definition lookup fsxp dnum names ams :=
t1 <- Rdtsc ;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams, r) <- DIRTREE.namei fsxp dnum names (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
ms <- LOG.commit_ro (FSXPLog fsxp) (MSLL ams);
r <- Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), r);
t2 <- Rdtsc ;
Debug "lookup" (t2-t1) ;;
Ret r.
Definition rename fsxp dnum srcpath srcname dstpath dstname ams :=
t1 <- Rdtsc;
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
let^ (ams', r) <- DIRTREE.rename fsxp dnum srcpath srcname dstpath dstname (BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams));
res <- match r with
| OK _ =>
let^ (ms, ok) <- LOG.commit (FSXPLog fsxp) (MSLL ams');
match ok with
| true => Ret ^((BFILE.mk_memstate (MSAlloc ams') ms (MSAllocC ams') (MSIAllocC ams') (MSICache ams') (MSCache ams') (MSDBlocks ams')), OK tt)
| false => Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err ELOGOVERFLOW)
end
| Err e =>
ms <- LOG.abort (FSXPLog fsxp) (MSLL ams');
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), Err e)
end;
t2 <- Rdtsc;
Debug "rename" (t2-t1);;
Ret res.
(* sync directory tree; will flush all outstanding changes to tree (but not dupdates to files) *)
Definition tree_sync fsxp ams :=
t1 <- Rdtsc ;
ams <- DIRTREE.sync fsxp ams;
t2 <- Rdtsc ;
Debug "tree_sync" (t2-t1) ;;
Ret ^(ams).
Definition tree_sync_noop fsxp ams :=
ams <- DIRTREE.sync_noop fsxp ams;
Ret ^(ams).
Definition umount fsxp ams :=
ams <- DIRTREE.sync fsxp ams;
ms <- LOG.sync_cache (FSXPLog fsxp) (MSLL ams);
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams))).
Definition statfs fsxp ams :=
ms <- LOG.begin (FSXPLog fsxp) (MSLL ams);
(*
let^ (mscs, free_blocks) <- BALLOC.numfree (FSXPLog fsxp) (FSXPBlockAlloc fsxp) mscs;
let^ (mscs, free_inodes) <- BALLOC.numfree (FSXPLog fsxp) (FSXPInodeAlloc fsxp) mscs;
*)
ms <- LOG.commit_ro (FSXPLog fsxp) ms;
(* Ret ^(mscs, free_blocks, free_inodes). *)
Ret ^((BFILE.mk_memstate (MSAlloc ams) ms (MSAllocC ams) (MSIAllocC ams) (MSICache ams) (MSCache ams) (MSDBlocks ams)), 0, 0).
(* Recover theorems *)
Hint Extern 0 (okToUnify (LOG.rep_inner _ _ _ _) (LOG.rep_inner _ _ _ _)) => constructor : okToUnify.
Theorem recover_ok : forall cachesize,
{< fsxp cs ds,
PRE:hm
LOG.after_crash (FSXPLog fsxp) (SB.rep fsxp) ds cs hm *
[[ cachesize <> 0 ]]
POST:hm' RET:r exists ms fsxp',
[[ fsxp' = fsxp ]] * [[ r = OK (ms, fsxp') ]] *
exists d n sm, [[ n <= length (snd ds) ]] *
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (d, nil)) (MSLL ms) sm hm' *
[[ sm = sm_synced ]] *
[[[ d ::: crash_xform (diskIs (list2nmem (nthd n ds))) ]]] *
[[ BFILE.MSinitial ms ]]
XCRASH:hm'
LOG.before_crash (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} recover cachesize.
Proof.
unfold recover, LOG.after_crash; intros.
eapply pimpl_ok2; monad_simpl.
eapply BUFCACHE.init_recover_ok.
intros; norm. cancel.
intuition simpl. eauto.
prestep. norml.
denote ((crash_xform _) d') as Hx.
apply crash_xform_sep_star_dist in Hx.
rewrite SB.crash_xform_rep in Hx.
rewrite LOG.after_crash_idem' in Hx; eauto.
destruct_lift Hx; denote (crash_xform (crash_xform _)) as Hx.
apply crash_xform_idem_l in Hx.
norm. cancel.
intuition.
pred_apply.
apply sep_star_comm; eauto.
step.
prestep. norm. cancel.
unfold LOG.after_crash; norm. cancel.
intuition simpl.
pred_apply; norml.
unfold stars; simpl.
norm. cancel.
rewrite LOG.rep_inner_hashmap_subset.
eassign (SB.rep fsxp).
cancel.
or_l; cancel.
auto.
intuition simpl; eauto.
safecancel.
rewrite LOG.rep_inner_hashmap_subset.
or_r; cancel.
auto.
eauto.
auto.
intuition.
step.
prestep. norm.
2: intuition idtac.
cancel.
intuition simpl; eauto.
intuition simpl; eauto.
intuition simpl; eauto.
xcrash.
eapply LOG.crash_xform_cached_before; eauto.
xcrash.
denote (SB.rep) as Hsb. rewrite SB.rep_magic_number in Hsb. destruct_lift Hsb.
step.
xcrash.
unfold LOG.before_crash.
denote or as Hor; apply sep_star_or_distr in Hor.
destruct Hor as [ Hor | Hor ];
rewrite LOG.rep_inner_hashmap_subset in Hor; eauto.
rewrite LOG.rep_inner_notxn_pimpl in Hor.
destruct_lift Hor.
norm. cancel.
intuition.
pred_apply.
safecancel.
rewrite LOG.rep_inner_rollbacktxn_pimpl in Hor.
norm. cancel.
intuition.
pred_apply.
safecancel.
xcrash.
unfold LOG.before_crash.
denote or as Hor; apply sep_star_or_distr in Hor.
destruct Hor as [ Hor | Hor ];
rewrite LOG.rep_inner_hashmap_subset in Hor; eauto.
rewrite LOG.rep_inner_notxn_pimpl in Hor.
destruct_lift Hor.
norm. cancel.
intuition.
pred_apply.
safecancel.
rewrite LOG.rep_inner_rollbacktxn_pimpl in Hor.
norm. cancel.
intuition.
pred_apply.
safecancel.
Unshelve. all: eauto.
Qed.
Hint Extern 1 ({{_}} Bind (recover _) _) => apply recover_ok : prog.
Ltac recover_ro_ok := intros;
repeat match goal with
| [ |- forall_helper _ ] => unfold forall_helper; intros; eexists; intros
| [ |- corr3 ?pre' _ _ ] => eapply corr3_from_corr2_rx; eauto with prog
| [ |- corr3 _ _ _ ] => eapply pimpl_ok3; intros
| [ |- corr2 _ _ ] => step
| [ H: crash_xform ?x =p=> ?x |- context [ crash_xform ?x ] ] => rewrite H
| [ H: diskIs _ _ |- _ ] => unfold diskIs in *
| [ |- pimpl (crash_xform _) _ ] => progress autorewrite with crash_xform
end.
Hint Extern 0 (okToUnify (LOG.idempred _ _ _ _) (LOG.idempred _ _ _ _)) => constructor : okToUnify.
Hint Extern 0 (okToUnify (LOG.after_crash _ _ _ _ _) (LOG.after_crash _ _ _ _ _)) => constructor : okToUnify.
(* Specs and proofs *)
Theorem file_getattr_ok : forall fsxp inum mscs,
{< ds sm pathname Fm Ftop tree f ilist frees,
PRE:hm LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]]
POST:hm' RET:^(mscs',r)
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] *
[[ r = DFAttr f /\ MSAlloc mscs' = MSAlloc mscs /\ MSCache mscs' = MSCache mscs ]]
CRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} file_get_attr fsxp inum mscs.
Proof.
unfold file_get_attr; intros.
step.
safestep.
safestep.
eassumption.
eapply pimpl_ok2; monad_simpl.
apply LOG.commit_ro_ok.
cancel.
step.
step.
cancel.
subst; pimpl_crash; cancel.
rewrite LOG.notxn_intact. rewrite LOG.intact_idempred. reflexivity.
rewrite LOG.intact_idempred.
pimpl_crash; cancel.
pimpl_crash. norml. clear H. safecancel.
rewrite LOG.notxn_intact. rewrite LOG.intact_idempred. reflexivity.
Unshelve. all: exact tt.
Qed.
Hint Extern 1 ({{_}} Bind (file_get_attr _ _ _) _) => apply file_getattr_ok : prog.
Theorem file_get_sz_ok : forall fsxp inum mscs,
{< ds sm pathname Fm Ftop tree f ilist frees,
PRE:hm LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]]
POST:hm' RET:^(mscs',r)
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] *
[[ r = INODE.ABytes (DFAttr f) /\ MSAlloc mscs' = MSAlloc mscs ]]
CRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} file_get_sz fsxp inum mscs.
Proof.
unfold file_get_sz; intros.
step.
step.
step.
step.
Unshelve. all: exact tt.
Qed.
Hint Extern 1 ({{_}} Bind (file_get_sz _ _ _) _) => apply file_get_sz_ok : prog.
Ltac xcrash_solve :=
repeat match goal with
| [ H: forall _ _ _, _ =p=> (?crash _) |- _ =p=> (?crash _) ] => eapply pimpl_trans; try apply H; cancel
| [ |- crash_xform (LOG.rep _ _ _ _ _ _) =p=> _ ] => rewrite LOG.notxn_intact; cancel
| [ H: crash_xform ?rc =p=> _ |- crash_xform ?rc =p=> _ ] => rewrite H; xform_norm
end.
(* Dumb and fast version of intuition *)
Ltac intuition' :=
match goal with
| [|- _ /\ _] => split; intuition'
| [|- True] => auto
| _ => idtac
end.
(* Try to simplify a pimpl with idempred on the left side. *)
Ltac simpl_idempred_l :=
simpl;
repeat xform_dist;
repeat xform_deex_l;
xform_dist;
rewrite crash_xform_lift_empty;
norml; unfold stars; simpl;
match goal with
| [ H: crash_xform ?x =p=> crash_xform _ |- context[crash_xform ?x] ] => rewrite H
end;
repeat xform_dist;
try rewrite sep_star_or_distr;
rewrite LOG.crash_xform_idempred.
(* Try to simplify a pimpl with idempred on the right side. *)
Ltac simpl_idempred_r :=
recover_ro_ok;
(norml; unfold stars; simpl);
(norm'r; unfold stars; simpl);
try (cancel);
intuition';
repeat xform_dist;
repeat rewrite crash_xform_idem.
Theorem read_fblock_ok : forall fsxp inum off mscs,
{< ds sm Fm Ftop tree pathname f Fd vs ilist frees,
PRE:hm LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]] *
[[[ (DFData f) ::: (Fd * off |-> vs) ]]]
POST:hm' RET:^(mscs', r)
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] *
[[ r = fst vs /\ MSAlloc mscs' = MSAlloc mscs ]]
CRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} read_fblock fsxp inum off mscs.
Proof.
unfold read_fblock; intros.
step.
safestep.
safestep.
all: try eassumption.
eapply pimpl_ok2; monad_simpl.
apply LOG.commit_ro_ok.
cancel.
step.
step.
pimpl_crash; cancel.
rewrite LOG.notxn_intact.
apply LOG.intact_idempred.
pimpl_crash; cancel.
apply LOG.intact_idempred.
pimpl_crash. norml. clear H. cancel.
apply LOG.notxn_idempred.
Unshelve. all: exact tt.
Qed.
Hint Extern 1 ({{_}} Bind (read_fblock _ _ _ _) _) => apply read_fblock_ok : prog.
Theorem file_set_attr_ok : forall fsxp inum attr mscs,
{< ds sm pathname Fm Ftop tree f ilist frees,
PRE:hm LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]]
POST:hm' RET:^(mscs', ok)
[[ MSAlloc mscs' = MSAlloc mscs ]] *
([[ isError ok ]] *
(LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[ BFILE.mscs_same_except_log mscs mscs' ]] *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]]) \/
([[ ok = OK tt ]] * exists d tree' f' ilist',
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (pushd d ds)) (MSLL mscs') sm hm' *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees mscs' sm)]]] *
[[ tree' = update_subtree pathname (TreeFile inum f') tree ]] *
[[ f' = mk_dirfile (DFData f) attr ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees (MSAlloc mscs')) tree' ]] *
[[ BFILE.treeseq_ilist_safe inum ilist ilist' ]])
)
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists d tree' f' ilist' mscs',
[[ MSAlloc mscs' = MSAlloc mscs ]] *
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (pushd d ds) hm' *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees mscs' sm)]]] *
[[ tree' = update_subtree pathname (TreeFile inum f') tree ]] *
[[ f' = mk_dirfile (DFData f) attr ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees (MSAlloc mscs')) tree' ]] *
[[ BFILE.treeseq_ilist_safe inum ilist ilist' ]]
>} file_set_attr fsxp inum attr mscs.
Proof.
unfold file_set_attr; intros.
step.
step.
step.
step.
step.
step.
step.
step.
or_l; cancel.
unfold BFILE.mscs_same_except_log; intuition.
xcrash_solve.
xcrash_solve.
{
rewrite LOG.recover_any_idempred; cancel.
or_r; cancel.
xform_norm; cancel.
xform_norm; cancel.
xform_norm; cancel.
xform_norm; cancel.
xform_norm; safecancel.
2: reflexivity.
eauto.
}
xcrash_solve.
rewrite LOG.intact_idempred. xform_norm. cancel.
xcrash_solve.
rewrite LOG.intact_idempred. xform_norm. cancel.
Qed.
Hint Extern 1 ({{_}} Bind (file_set_attr _ _ _ _) _) => apply file_set_attr_ok : prog.
Theorem file_truncate_ok : forall fsxp inum sz mscs,
{< ds sm Fm Ftop tree pathname f ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm)]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]]
POST:hm' RET:^(mscs', r)
[[ MSAlloc mscs' = MSAlloc mscs ]] *
([[ isError r ]] * LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] \/
[[ r = OK tt ]] * exists d tree' f' ilist' frees',
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (pushd d ds)) (MSLL mscs') sm hm' *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm)]]] *
[[ tree' = update_subtree pathname (TreeFile inum f') tree ]] *
[[ f' = mk_dirfile (setlen (DFData f) sz ($0, nil)) (DFAttr f) ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ sz >= Datatypes.length (DFData f) -> BFILE.treeseq_ilist_safe inum ilist ilist' ]] )
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists d tree' f' ilist' frees' mscs',
[[ MSAlloc mscs' = MSAlloc mscs ]] *
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (pushd d ds) hm' *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm)]]] *
[[ tree' = update_subtree pathname (TreeFile inum f') tree ]] *
[[ f' = mk_dirfile (setlen (DFData f) sz ($0, nil)) (DFAttr f) ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ sz >= Datatypes.length (DFData f) -> BFILE.treeseq_ilist_safe inum ilist ilist' ]]
>} file_truncate fsxp inum sz mscs.
Proof.
unfold file_truncate; intros.
step.
step.
step.
step.
step.
step.
step.
step.
step.
step.
step.
xcrash_solve.
{
or_r; cancel.
rewrite LOG.recover_any_idempred.
xform_normr.
safecancel.
eauto.
}
step.
step.
xcrash_solve.
rewrite LOG.intact_idempred. xform_norm. cancel.
xcrash_solve.
rewrite LOG.intact_idempred. xform_norm. cancel.
xcrash_solve.
rewrite LOG.intact_idempred. xform_norm. cancel.
Unshelve.
all: easy.
Qed.
Hint Extern 1 ({{_}} Bind (file_truncate _ _ _ _) _) => apply file_truncate_ok : prog.
Ltac latest_rewrite := unfold latest, pushd; simpl.
Theorem update_fblock_d_ok : forall fsxp inum off v mscs,
{< ds sm Fm Ftop tree pathname f Fd vs frees ilist,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm)]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]] *
[[[ (DFData f) ::: (Fd * off |-> vs) ]]]
POST:hm' RET:^(mscs')
exists tree' f' ds' sm' bn,
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds') (MSLL mscs') sm' hm' *
[[ ds' = dsupd ds bn (v, vsmerge vs) ]] *
[[ BFILE.block_belong_to_file ilist bn inum off ]] *
[[ MSAlloc mscs' = MSAlloc mscs ]] *
[[ MSCache mscs' = MSCache mscs ]] *
[[ MSAllocC mscs' = MSAllocC mscs ]] *
[[ MSIAllocC mscs' = MSIAllocC mscs ]] *
(* spec about files on the latest diskset *)
[[[ ds'!! ::: (Fm * rep fsxp Ftop tree' ilist frees mscs' sm') ]]] *
[[ tree' = update_subtree pathname (TreeFile inum f') tree ]] *
[[[ (DFData f') ::: (Fd * off |-> (v, vsmerge vs)) ]]] *
[[ DFAttr f' = DFAttr f ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree' ]]
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists bn, [[ BFILE.block_belong_to_file ilist bn inum off ]] *
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (dsupd ds bn (v, vsmerge vs)) hm'
>} update_fblock_d fsxp inum off v mscs.
Proof.
unfold update_fblock_d; intros.
step.
step.
prestep.
(* extract dset_match from (rep ds), this is useful for proving crash condition *)
rewrite LOG.active_dset_match_pimpl at 1.
norm. cancel.
xcrash_solve.
intuition.
latest_rewrite.
pred_apply; cancel.
eauto.
eauto.
safestep.
step.
step.
xcrash_solve.
- xform_normr; cancel.
or_r; xform_normr; cancel.
apply LOG.notxn_idempred.
eauto.
- cancel.
repeat xcrash_rewrite.
xform_norm.
rewrite LOG.recover_any_idempred.
or_l; cancel.
rewrite LOG.recover_any_idempred.
or_r; cancel; xform_normr; cancel.
- cancel.
repeat xcrash_rewrite.
xform_norm; cancel.
rewrite LOG.notxn_intact, LOG.intact_idempred.
xform_normr; cancel.
Unshelve.
all: easy.
Qed.
Hint Extern 1 ({{_}} Bind (update_fblock_d _ _ _ _ _) _) => apply update_fblock_d_ok : prog.
Theorem file_sync_ok: forall fsxp inum mscs,
{< ds sm Fm Ftop tree pathname f ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm)]]] *
[[ find_subtree pathname tree = Some (TreeFile inum f) ]]
POST:hm' RET:^(mscs')
exists ds' sm' tree' al,
[[ MSAlloc mscs = MSAlloc mscs' ]] *
[[ MSCache mscs = MSCache mscs' ]] *
[[ MSAllocC mscs = MSAllocC mscs' ]] *
[[ MSIAllocC mscs = MSIAllocC mscs' ]] *
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds') (MSLL mscs') sm' hm' *
[[ ds' = dssync_vecs ds al]] *
[[ length al = length (DFData f) /\ forall i, i < length al ->
BFILE.block_belong_to_file ilist (selN al i 0) inum i ]] *
[[[ ds'!! ::: (Fm * rep fsxp Ftop tree' ilist frees mscs' sm')]]] *
[[ tree' = update_subtree pathname (TreeFile inum (synced_dirfile f)) tree ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree' ]]
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} file_sync fsxp inum mscs.
Proof.
unfold file_sync; intros.
step.
step.
prestep; norm. cancel. intuition.
latest_rewrite.
pred_apply; cancel.
eauto.
step.
step.
step.
- xcrash_solve.
rewrite <- crash_xform_idem.
rewrite LOG.crash_xform_intact_dssync_vecs_idempred.
rewrite SB.crash_xform_rep.
xcrash.
- xcrash_solve.
rewrite LOG.recover_any_idempred.
xcrash.
- xcrash_solve.
rewrite LOG.intact_idempred.
xcrash.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (file_sync _ _ _) _) => apply file_sync_ok : prog.
Theorem tree_sync_ok: forall fsxp mscs,
{< ds sm Fm Ftop tree ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm)]]]
POST:hm' RET:^(mscs')
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (ds!!, nil)) (MSLL mscs') sm hm' *
[[ MSAlloc mscs' = negb (MSAlloc mscs) ]] *
[[ MSCache mscs' = MSCache mscs ]] *
[[ MSICache mscs' = MSICache mscs ]] *
[[ MSAllocC mscs' = MSAllocC mscs ]] *
[[ MSIAllocC mscs' = MSIAllocC mscs ]] *
[[ MSDBlocks mscs' = MSDBlocks mscs ]]
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} tree_sync fsxp mscs.
Proof.
unfold tree_sync; intros.
step.
step using auto.
step.
step.
xcrash_solve.
rewrite LOG.recover_any_idempred.
cancel.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (tree_sync _ _) _) => apply tree_sync_ok : prog.
Theorem tree_sync_noop_ok: forall fsxp mscs,
{< ds sm Fm Ftop tree ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm)]]]
POST:hm' RET:^(mscs')
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[ MSAlloc mscs' = negb (MSAlloc mscs) ]]
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} tree_sync_noop fsxp mscs.
Proof.
unfold tree_sync_noop; intros.
step.
step.
xcrash_solve.
rewrite LOG.recover_any_idempred.
cancel.
Qed.
Hint Extern 1 ({{_}} Bind (tree_sync_noop _ _) _) => apply tree_sync_noop_ok : prog.
Theorem lookup_ok: forall fsxp dnum fnlist mscs,
{< ds sm Fm Ftop tree ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ dirtree_inum tree = dnum]] *
[[ dirtree_isdir tree = true ]]
POST:hm' RET:^(mscs', r)
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] *
[[ (isError r /\ None = find_name fnlist tree) \/
(exists v, r = OK v /\ Some v = find_name fnlist tree)%type ]] *
[[ MSAlloc mscs' = MSAlloc mscs ]] *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]]
CRASH:hm' LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm'
>} lookup fsxp dnum fnlist mscs.
Proof.
unfold lookup; intros.
step.
step.
(* `step` here is really slow *)
prestep. cancel.
eapply pimpl_ok2; monad_simpl.
apply LOG.commit_ro_ok.
cancel.
step.
step.
subst; pimpl_crash; cancel.
apply LOG.notxn_idempred.
step.
step.
cancel. apply LOG.notxn_idempred.
cancel. apply LOG.intact_idempred.
cancel. apply LOG.notxn_idempred.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (lookup _ _ _ _) _) => apply lookup_ok : prog.
Theorem create_ok : forall fsxp dnum name mscs,
{< ds sm pathname Fm Ftop tree tree_elem ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeDir dnum tree_elem) ]]
POST:hm' RET:^(mscs',r)
[[ MSAlloc mscs' = MSAlloc mscs ]] *
([[ isError r ]] *
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]]
\/ exists inum,
[[ r = OK inum ]] * exists d tree' ilist' frees',
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (pushd d ds)) (MSLL mscs') sm hm' *
[[ tree' = tree_graft dnum tree_elem pathname name (TreeFile inum dirfile0) tree ]] *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm) ]]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]])
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists d inum tree' ilist' frees' mscs',
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (pushd d ds) hm' *
[[ tree' = tree_graft dnum tree_elem pathname name (TreeFile inum dirfile0) tree ]] *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm) ]]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ MSAlloc mscs' = MSAlloc mscs ]]
>} create fsxp dnum name mscs.
Proof.
unfold create; intros.
step.
step.
step.
step.
step.
step.
step.
xcrash_solve.
or_r; cancel.
repeat (cancel; progress xform_norm).
safecancel.
2: reflexivity. cancel.
rewrite LOG.recover_any_idempred; cancel.
pred_apply; cancel.
auto.
auto.
step.
step.
xcrash_solve. xform_norm. or_l. rewrite LOG.intact_idempred. cancel.
xcrash_solve. xform_norm. or_l. rewrite LOG.intact_idempred. cancel.
xcrash_solve. xform_norm. or_l. rewrite LOG.intact_idempred. cancel.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (create _ _ _ _ ) _) => apply create_ok : prog.
Definition rename_rep_inner d frees' ilist' tree' srcnum srcents subtree pruned dstnum dstents renamed mscs' sm Fm fsxp Ftop tree tree_elem ilist frees cwd dnum srcpath srcname dstpath dstname
: @pred addr addr_eq_dec valuset :=
([[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm) ]]] *
[[ find_subtree srcpath (TreeDir dnum tree_elem) = Some (TreeDir srcnum srcents) ]] *
[[ find_dirlist srcname srcents = Some subtree ]] *
[[ pruned = tree_prune srcnum srcents srcpath srcname (TreeDir dnum tree_elem) ]] *
[[ find_subtree dstpath pruned = Some (TreeDir dstnum dstents) ]] *
[[ renamed = tree_graft dstnum dstents dstpath dstname subtree pruned ]] *
[[ tree' = update_subtree cwd renamed tree ]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ forall inum' def', inum' <> srcnum -> inum' <> dstnum ->
In inum' (tree_inodes tree') ->
selN ilist inum' def' = selN ilist' inum' def' ]])%pred.
Definition rename_rep ds mscs' sm Fm fsxp Ftop tree tree_elem ilist frees cwd dnum srcpath srcname dstpath dstname hm :=
(exists d tree' srcnum srcents dstnum dstents subtree pruned renamed ilist' frees',
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (pushd d ds)) (MSLL mscs') sm hm *
rename_rep_inner d frees' ilist' tree' srcnum srcents subtree pruned dstnum dstents renamed mscs' sm Fm fsxp Ftop tree tree_elem ilist frees cwd dnum srcpath srcname dstpath dstname
)%pred.
Theorem rename_ok : forall fsxp dnum srcpath srcname dstpath dstname mscs,
{< ds sm Fm Ftop tree cwd tree_elem ilist frees,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree cwd tree = Some (TreeDir dnum tree_elem) ]]
POST:hm' RET:^(mscs', ok)
[[ MSAlloc mscs' = MSAlloc mscs ]] *
([[ isError ok ]] * LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] \/
[[ ok = OK tt ]] *
rename_rep ds mscs' sm Fm fsxp Ftop tree tree_elem ilist frees cwd dnum srcpath srcname dstpath dstname hm')
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists d tree' srcnum srcents dstnum dstents subtree pruned renamed ilist' frees' mscs',
[[ MSAlloc mscs' = MSAlloc mscs ]] *
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (pushd d ds) hm' *
rename_rep_inner d frees' ilist' tree' srcnum srcents subtree pruned dstnum dstents renamed mscs' sm Fm fsxp Ftop tree tree_elem ilist frees cwd dnum srcpath srcname dstpath dstname
>} rename fsxp dnum srcpath srcname dstpath dstname mscs.
Proof.
unfold rename, rename_rep, rename_rep_inner; intros.
step.
step.
step.
step.
step.
step.
step.
xcrash. or_r. cancel.
repeat (cancel; progress xform_norm).
safecancel.
rewrite LOG.recover_any_idempred. cancel.
2: pred_apply; cancel.
all: eauto.
step.
step.
xcrash. or_l. rewrite LOG.notxn_idempred. cancel.
xcrash. or_l. rewrite LOG.intact_idempred. cancel.
xcrash. or_l. rewrite LOG.notxn_idempred. cancel.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (rename _ _ _ _ _ _ _) _) => apply rename_ok : prog.
Theorem delete_ok : forall fsxp dnum name mscs,
{< ds sm pathname Fm Ftop tree tree_elem frees ilist,
PRE:hm
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs) sm hm *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs sm) ]]] *
[[ find_subtree pathname tree = Some (TreeDir dnum tree_elem) ]]
POST:hm' RET:^(mscs', ok)
[[ MSAlloc mscs' = MSAlloc mscs ]] *
([[ isError ok ]] *
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn ds) (MSLL mscs') sm hm' *
[[[ ds!! ::: (Fm * rep fsxp Ftop tree ilist frees mscs' sm) ]]] \/
[[ ok = OK tt ]] * exists d tree' ilist' frees',
LOG.rep (FSXPLog fsxp) (SB.rep fsxp) (LOG.NoTxn (pushd d ds)) (MSLL mscs') sm hm' *
[[ tree' = update_subtree pathname
(delete_from_dir name (TreeDir dnum tree_elem)) tree ]] *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm) ]]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ forall inum def', inum <> dnum -> In inum (tree_inodes tree) ->
In inum (tree_inodes tree') ->
selN ilist inum def' = selN ilist' inum def' ]])
XCRASH:hm'
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) ds hm' \/
exists d tree' ilist' frees' mscs',
[[ MSAlloc mscs' = MSAlloc mscs ]] *
LOG.idempred (FSXPLog fsxp) (SB.rep fsxp) (pushd d ds) hm' *
[[ tree' = update_subtree pathname
(delete_from_dir name (TreeDir dnum tree_elem)) tree ]] *
[[[ d ::: (Fm * rep fsxp Ftop tree' ilist' frees' mscs' sm) ]]] *
[[ dirtree_safe ilist (BFILE.pick_balloc frees (MSAlloc mscs')) tree
ilist' (BFILE.pick_balloc frees' (MSAlloc mscs')) tree' ]] *
[[ forall inum def', inum <> dnum ->
(In inum (tree_inodes tree') \/ (~ In inum (tree_inodes tree))) ->
selN ilist inum def' = selN ilist' inum def' ]]
>} delete fsxp dnum name mscs.
Proof.
unfold delete; intros.
step.
step.
step.
step.
step.
step.
step.
xcrash. or_r.
repeat (cancel; progress xform_norm).
safecancel. rewrite LOG.recover_any_idempred. cancel.
3: pred_apply; cancel.
all: eauto.
step.
step.
xcrash. or_l. rewrite LOG.notxn_idempred. cancel.
xcrash. or_l. rewrite LOG.intact_idempred. cancel.
xcrash. or_l. rewrite LOG.notxn_idempred. cancel.
Unshelve.
all: constructor.
Qed.
Hint Extern 1 ({{_}} Bind (delete _ _ _ _) _) => apply delete_ok : prog.
End AFS.
|
// This file extends the original bug test case to explore all the
// forms of a signed right shift that are treated as special cases.
module test;
reg pass;
reg [8*40:1] str;
integer s;
initial begin
pass = 1'b1;
s = 1;
$sformat(str, "%0d", ((0 >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 1st test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> 1) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 2nd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((2 >> s) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 3rd test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 1) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 4th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 0) + 1) * -1);
if (str[8*2:1] !== "-2" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 5th test, expected \"-2\", got %s", str);
pass = 1'b0;
end
$sformat(str, "%0d", ((s >> 64) + 1) * -1);
if (str[8*2:1] !== "-1" || str[8*40:8*2+1] !== 0) begin
$display("FAILED 6th test, expected \"-1\", got %s", str);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// finalproject_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.04.23.00:32:39
`timescale 1 ps / 1 ps
module finalproject_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire clocks_c0_clk, // clocks_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
input wire [28:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [28:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [21:0] clock_crossing_io_s0_address, // clock_crossing_io_s0.address
output wire clock_crossing_io_s0_write, // .write
output wire clock_crossing_io_s0_read, // .read
input wire [31:0] clock_crossing_io_s0_readdata, // .readdata
output wire [31:0] clock_crossing_io_s0_writedata, // .writedata
output wire [0:0] clock_crossing_io_s0_burstcount, // .burstcount
output wire [3:0] clock_crossing_io_s0_byteenable, // .byteenable
input wire clock_crossing_io_s0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_s0_waitrequest, // .waitrequest
output wire clock_crossing_io_s0_debugaccess, // .debugaccess
output wire [1:0] clocks_pll_slave_address, // clocks_pll_slave.address
output wire clocks_pll_slave_write, // .write
output wire clocks_pll_slave_read, // .read
input wire [31:0] clocks_pll_slave_readdata, // .readdata
output wire [31:0] clocks_pll_slave_writedata, // .writedata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keycode_s1_address, // keycode_s1.address
output wire keycode_s1_write, // .write
input wire [31:0] keycode_s1_readdata, // .readdata
output wire [31:0] keycode_s1_writedata, // .writedata
output wire keycode_s1_chipselect, // .chipselect
output wire [24:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [31:0] sdram_s1_readdata, // .readdata
output wire [31:0] sdram_s1_writedata, // .writedata
output wire [3:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [28:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [28:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [28:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire [105:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire [105:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> cpu_jtag_debug_module_agent:cp_data
wire cmd_mux_001_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux_001:src_ready
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire [31:0] clocks_pll_slave_agent_m0_readdata; // clocks_pll_slave_translator:uav_readdata -> clocks_pll_slave_agent:m0_readdata
wire clocks_pll_slave_agent_m0_waitrequest; // clocks_pll_slave_translator:uav_waitrequest -> clocks_pll_slave_agent:m0_waitrequest
wire clocks_pll_slave_agent_m0_debugaccess; // clocks_pll_slave_agent:m0_debugaccess -> clocks_pll_slave_translator:uav_debugaccess
wire [28:0] clocks_pll_slave_agent_m0_address; // clocks_pll_slave_agent:m0_address -> clocks_pll_slave_translator:uav_address
wire [3:0] clocks_pll_slave_agent_m0_byteenable; // clocks_pll_slave_agent:m0_byteenable -> clocks_pll_slave_translator:uav_byteenable
wire clocks_pll_slave_agent_m0_read; // clocks_pll_slave_agent:m0_read -> clocks_pll_slave_translator:uav_read
wire clocks_pll_slave_agent_m0_readdatavalid; // clocks_pll_slave_translator:uav_readdatavalid -> clocks_pll_slave_agent:m0_readdatavalid
wire clocks_pll_slave_agent_m0_lock; // clocks_pll_slave_agent:m0_lock -> clocks_pll_slave_translator:uav_lock
wire [31:0] clocks_pll_slave_agent_m0_writedata; // clocks_pll_slave_agent:m0_writedata -> clocks_pll_slave_translator:uav_writedata
wire clocks_pll_slave_agent_m0_write; // clocks_pll_slave_agent:m0_write -> clocks_pll_slave_translator:uav_write
wire [2:0] clocks_pll_slave_agent_m0_burstcount; // clocks_pll_slave_agent:m0_burstcount -> clocks_pll_slave_translator:uav_burstcount
wire clocks_pll_slave_agent_rf_source_valid; // clocks_pll_slave_agent:rf_source_valid -> clocks_pll_slave_agent_rsp_fifo:in_valid
wire [105:0] clocks_pll_slave_agent_rf_source_data; // clocks_pll_slave_agent:rf_source_data -> clocks_pll_slave_agent_rsp_fifo:in_data
wire clocks_pll_slave_agent_rf_source_ready; // clocks_pll_slave_agent_rsp_fifo:in_ready -> clocks_pll_slave_agent:rf_source_ready
wire clocks_pll_slave_agent_rf_source_startofpacket; // clocks_pll_slave_agent:rf_source_startofpacket -> clocks_pll_slave_agent_rsp_fifo:in_startofpacket
wire clocks_pll_slave_agent_rf_source_endofpacket; // clocks_pll_slave_agent:rf_source_endofpacket -> clocks_pll_slave_agent_rsp_fifo:in_endofpacket
wire clocks_pll_slave_agent_rsp_fifo_out_valid; // clocks_pll_slave_agent_rsp_fifo:out_valid -> clocks_pll_slave_agent:rf_sink_valid
wire [105:0] clocks_pll_slave_agent_rsp_fifo_out_data; // clocks_pll_slave_agent_rsp_fifo:out_data -> clocks_pll_slave_agent:rf_sink_data
wire clocks_pll_slave_agent_rsp_fifo_out_ready; // clocks_pll_slave_agent:rf_sink_ready -> clocks_pll_slave_agent_rsp_fifo:out_ready
wire clocks_pll_slave_agent_rsp_fifo_out_startofpacket; // clocks_pll_slave_agent_rsp_fifo:out_startofpacket -> clocks_pll_slave_agent:rf_sink_startofpacket
wire clocks_pll_slave_agent_rsp_fifo_out_endofpacket; // clocks_pll_slave_agent_rsp_fifo:out_endofpacket -> clocks_pll_slave_agent:rf_sink_endofpacket
wire clocks_pll_slave_agent_rdata_fifo_src_valid; // clocks_pll_slave_agent:rdata_fifo_src_valid -> clocks_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] clocks_pll_slave_agent_rdata_fifo_src_data; // clocks_pll_slave_agent:rdata_fifo_src_data -> clocks_pll_slave_agent:rdata_fifo_sink_data
wire clocks_pll_slave_agent_rdata_fifo_src_ready; // clocks_pll_slave_agent:rdata_fifo_sink_ready -> clocks_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> clocks_pll_slave_agent:cp_valid
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> clocks_pll_slave_agent:cp_data
wire cmd_mux_002_src_ready; // clocks_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> clocks_pll_slave_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> clocks_pll_slave_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> clocks_pll_slave_agent:cp_endofpacket
wire [31:0] clock_crossing_io_s0_agent_m0_readdata; // clock_crossing_io_s0_translator:uav_readdata -> clock_crossing_io_s0_agent:m0_readdata
wire clock_crossing_io_s0_agent_m0_waitrequest; // clock_crossing_io_s0_translator:uav_waitrequest -> clock_crossing_io_s0_agent:m0_waitrequest
wire clock_crossing_io_s0_agent_m0_debugaccess; // clock_crossing_io_s0_agent:m0_debugaccess -> clock_crossing_io_s0_translator:uav_debugaccess
wire [28:0] clock_crossing_io_s0_agent_m0_address; // clock_crossing_io_s0_agent:m0_address -> clock_crossing_io_s0_translator:uav_address
wire [3:0] clock_crossing_io_s0_agent_m0_byteenable; // clock_crossing_io_s0_agent:m0_byteenable -> clock_crossing_io_s0_translator:uav_byteenable
wire clock_crossing_io_s0_agent_m0_read; // clock_crossing_io_s0_agent:m0_read -> clock_crossing_io_s0_translator:uav_read
wire clock_crossing_io_s0_agent_m0_readdatavalid; // clock_crossing_io_s0_translator:uav_readdatavalid -> clock_crossing_io_s0_agent:m0_readdatavalid
wire clock_crossing_io_s0_agent_m0_lock; // clock_crossing_io_s0_agent:m0_lock -> clock_crossing_io_s0_translator:uav_lock
wire [31:0] clock_crossing_io_s0_agent_m0_writedata; // clock_crossing_io_s0_agent:m0_writedata -> clock_crossing_io_s0_translator:uav_writedata
wire clock_crossing_io_s0_agent_m0_write; // clock_crossing_io_s0_agent:m0_write -> clock_crossing_io_s0_translator:uav_write
wire [2:0] clock_crossing_io_s0_agent_m0_burstcount; // clock_crossing_io_s0_agent:m0_burstcount -> clock_crossing_io_s0_translator:uav_burstcount
wire clock_crossing_io_s0_agent_rf_source_valid; // clock_crossing_io_s0_agent:rf_source_valid -> clock_crossing_io_s0_agent_rsp_fifo:in_valid
wire [105:0] clock_crossing_io_s0_agent_rf_source_data; // clock_crossing_io_s0_agent:rf_source_data -> clock_crossing_io_s0_agent_rsp_fifo:in_data
wire clock_crossing_io_s0_agent_rf_source_ready; // clock_crossing_io_s0_agent_rsp_fifo:in_ready -> clock_crossing_io_s0_agent:rf_source_ready
wire clock_crossing_io_s0_agent_rf_source_startofpacket; // clock_crossing_io_s0_agent:rf_source_startofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_startofpacket
wire clock_crossing_io_s0_agent_rf_source_endofpacket; // clock_crossing_io_s0_agent:rf_source_endofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_endofpacket
wire clock_crossing_io_s0_agent_rsp_fifo_out_valid; // clock_crossing_io_s0_agent_rsp_fifo:out_valid -> clock_crossing_io_s0_agent:rf_sink_valid
wire [105:0] clock_crossing_io_s0_agent_rsp_fifo_out_data; // clock_crossing_io_s0_agent_rsp_fifo:out_data -> clock_crossing_io_s0_agent:rf_sink_data
wire clock_crossing_io_s0_agent_rsp_fifo_out_ready; // clock_crossing_io_s0_agent:rf_sink_ready -> clock_crossing_io_s0_agent_rsp_fifo:out_ready
wire clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_startofpacket -> clock_crossing_io_s0_agent:rf_sink_startofpacket
wire clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_endofpacket -> clock_crossing_io_s0_agent:rf_sink_endofpacket
wire clock_crossing_io_s0_agent_rdata_fifo_src_valid; // clock_crossing_io_s0_agent:rdata_fifo_src_valid -> clock_crossing_io_s0_agent:rdata_fifo_sink_valid
wire [33:0] clock_crossing_io_s0_agent_rdata_fifo_src_data; // clock_crossing_io_s0_agent:rdata_fifo_src_data -> clock_crossing_io_s0_agent:rdata_fifo_sink_data
wire clock_crossing_io_s0_agent_rdata_fifo_src_ready; // clock_crossing_io_s0_agent:rdata_fifo_sink_ready -> clock_crossing_io_s0_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> clock_crossing_io_s0_agent:cp_valid
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> clock_crossing_io_s0_agent:cp_data
wire cmd_mux_003_src_ready; // clock_crossing_io_s0_agent:cp_ready -> cmd_mux_003:src_ready
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> clock_crossing_io_s0_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> clock_crossing_io_s0_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> clock_crossing_io_s0_agent:cp_endofpacket
wire [31:0] keycode_s1_agent_m0_readdata; // keycode_s1_translator:uav_readdata -> keycode_s1_agent:m0_readdata
wire keycode_s1_agent_m0_waitrequest; // keycode_s1_translator:uav_waitrequest -> keycode_s1_agent:m0_waitrequest
wire keycode_s1_agent_m0_debugaccess; // keycode_s1_agent:m0_debugaccess -> keycode_s1_translator:uav_debugaccess
wire [28:0] keycode_s1_agent_m0_address; // keycode_s1_agent:m0_address -> keycode_s1_translator:uav_address
wire [3:0] keycode_s1_agent_m0_byteenable; // keycode_s1_agent:m0_byteenable -> keycode_s1_translator:uav_byteenable
wire keycode_s1_agent_m0_read; // keycode_s1_agent:m0_read -> keycode_s1_translator:uav_read
wire keycode_s1_agent_m0_readdatavalid; // keycode_s1_translator:uav_readdatavalid -> keycode_s1_agent:m0_readdatavalid
wire keycode_s1_agent_m0_lock; // keycode_s1_agent:m0_lock -> keycode_s1_translator:uav_lock
wire [31:0] keycode_s1_agent_m0_writedata; // keycode_s1_agent:m0_writedata -> keycode_s1_translator:uav_writedata
wire keycode_s1_agent_m0_write; // keycode_s1_agent:m0_write -> keycode_s1_translator:uav_write
wire [2:0] keycode_s1_agent_m0_burstcount; // keycode_s1_agent:m0_burstcount -> keycode_s1_translator:uav_burstcount
wire keycode_s1_agent_rf_source_valid; // keycode_s1_agent:rf_source_valid -> keycode_s1_agent_rsp_fifo:in_valid
wire [105:0] keycode_s1_agent_rf_source_data; // keycode_s1_agent:rf_source_data -> keycode_s1_agent_rsp_fifo:in_data
wire keycode_s1_agent_rf_source_ready; // keycode_s1_agent_rsp_fifo:in_ready -> keycode_s1_agent:rf_source_ready
wire keycode_s1_agent_rf_source_startofpacket; // keycode_s1_agent:rf_source_startofpacket -> keycode_s1_agent_rsp_fifo:in_startofpacket
wire keycode_s1_agent_rf_source_endofpacket; // keycode_s1_agent:rf_source_endofpacket -> keycode_s1_agent_rsp_fifo:in_endofpacket
wire keycode_s1_agent_rsp_fifo_out_valid; // keycode_s1_agent_rsp_fifo:out_valid -> keycode_s1_agent:rf_sink_valid
wire [105:0] keycode_s1_agent_rsp_fifo_out_data; // keycode_s1_agent_rsp_fifo:out_data -> keycode_s1_agent:rf_sink_data
wire keycode_s1_agent_rsp_fifo_out_ready; // keycode_s1_agent:rf_sink_ready -> keycode_s1_agent_rsp_fifo:out_ready
wire keycode_s1_agent_rsp_fifo_out_startofpacket; // keycode_s1_agent_rsp_fifo:out_startofpacket -> keycode_s1_agent:rf_sink_startofpacket
wire keycode_s1_agent_rsp_fifo_out_endofpacket; // keycode_s1_agent_rsp_fifo:out_endofpacket -> keycode_s1_agent:rf_sink_endofpacket
wire keycode_s1_agent_rdata_fifo_src_valid; // keycode_s1_agent:rdata_fifo_src_valid -> keycode_s1_agent:rdata_fifo_sink_valid
wire [33:0] keycode_s1_agent_rdata_fifo_src_data; // keycode_s1_agent:rdata_fifo_src_data -> keycode_s1_agent:rdata_fifo_sink_data
wire keycode_s1_agent_rdata_fifo_src_ready; // keycode_s1_agent:rdata_fifo_sink_ready -> keycode_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> keycode_s1_agent:cp_valid
wire [104:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> keycode_s1_agent:cp_data
wire cmd_mux_004_src_ready; // keycode_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> keycode_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> keycode_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> keycode_s1_agent:cp_endofpacket
wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [28:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire [105:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire [105:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [33:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sdram_s1_agent:cp_valid
wire [104:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sdram_s1_agent:cp_data
wire cmd_mux_005_src_ready; // sdram_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sdram_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sdram_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire [104:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [104:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [104:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [104:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_003:sink_valid
wire [104:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_003:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_003:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_003:sink_startofpacket
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire clocks_pll_slave_agent_rp_valid; // clocks_pll_slave_agent:rp_valid -> router_004:sink_valid
wire [104:0] clocks_pll_slave_agent_rp_data; // clocks_pll_slave_agent:rp_data -> router_004:sink_data
wire clocks_pll_slave_agent_rp_ready; // router_004:sink_ready -> clocks_pll_slave_agent:rp_ready
wire clocks_pll_slave_agent_rp_startofpacket; // clocks_pll_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire clocks_pll_slave_agent_rp_endofpacket; // clocks_pll_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire clock_crossing_io_s0_agent_rp_valid; // clock_crossing_io_s0_agent:rp_valid -> router_005:sink_valid
wire [104:0] clock_crossing_io_s0_agent_rp_data; // clock_crossing_io_s0_agent:rp_data -> router_005:sink_data
wire clock_crossing_io_s0_agent_rp_ready; // router_005:sink_ready -> clock_crossing_io_s0_agent:rp_ready
wire clock_crossing_io_s0_agent_rp_startofpacket; // clock_crossing_io_s0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire clock_crossing_io_s0_agent_rp_endofpacket; // clock_crossing_io_s0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [104:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire keycode_s1_agent_rp_valid; // keycode_s1_agent:rp_valid -> router_006:sink_valid
wire [104:0] keycode_s1_agent_rp_data; // keycode_s1_agent:rp_data -> router_006:sink_data
wire keycode_s1_agent_rp_ready; // router_006:sink_ready -> keycode_s1_agent:rp_ready
wire keycode_s1_agent_rp_startofpacket; // keycode_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire keycode_s1_agent_rp_endofpacket; // keycode_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_007:sink_valid
wire [104:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_007:sink_data
wire sdram_s1_agent_rp_ready; // router_007:sink_ready -> sdram_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [104:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [104:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [104:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [104:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [5:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [104:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [5:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [104:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [5:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [104:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> crosser:in_valid
wire [104:0] cmd_demux_src5_data; // cmd_demux:src5_data -> crosser:in_data
wire cmd_demux_src5_ready; // crosser:in_ready -> cmd_demux:src5_ready
wire [5:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> crosser:in_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_005:sink0_valid
wire [104:0] crosser_out_data; // crosser:out_data -> cmd_mux_005:sink0_data
wire crosser_out_ready; // cmd_mux_005:sink0_ready -> crosser:out_ready
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_005:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> crosser_001:in_valid
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> crosser_001:in_data
wire cmd_demux_001_src2_ready; // crosser_001:in_ready -> cmd_demux_001:src2_ready
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> crosser_001:in_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_005:sink1_valid
wire [104:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_005:sink1_data
wire crosser_001_out_ready; // cmd_mux_005:sink1_ready -> crosser_001:out_ready
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_005:sink1_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_005:sink1_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_005:sink1_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> crosser_002:in_valid
wire [104:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> crosser_002:in_data
wire rsp_demux_005_src0_ready; // crosser_002:in_ready -> rsp_demux_005:src0_ready
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> crosser_002:in_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> crosser_002:in_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink5_valid
wire [104:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink5_data
wire crosser_002_out_ready; // rsp_mux:sink5_ready -> crosser_002:out_ready
wire [5:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink5_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink5_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> crosser_003:in_valid
wire [104:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> crosser_003:in_data
wire rsp_demux_005_src1_ready; // crosser_003:in_ready -> rsp_demux_005:src1_ready
wire [5:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> crosser_003:in_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> crosser_003:in_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink2_valid
wire [104:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink2_data
wire crosser_003_out_ready; // rsp_mux_001:sink2_ready -> crosser_003:out_ready
wire [5:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink2_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink2_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink2_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clocks_pll_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clocks_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (clocks_pll_slave_agent_m0_read), // .read
.uav_write (clocks_pll_slave_agent_m0_write), // .write
.uav_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (clocks_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (clocks_pll_slave_address), // avalon_anti_slave_0.address
.av_write (clocks_pll_slave_write), // .write
.av_read (clocks_pll_slave_read), // .read
.av_readdata (clocks_pll_slave_readdata), // .readdata
.av_writedata (clocks_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clock_crossing_io_s0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.uav_read (clock_crossing_io_s0_agent_m0_read), // .read
.uav_write (clock_crossing_io_s0_agent_m0_write), // .write
.uav_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.uav_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.uav_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.uav_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_s0_address), // avalon_anti_slave_0.address
.av_write (clock_crossing_io_s0_write), // .write
.av_read (clock_crossing_io_s0_read), // .read
.av_readdata (clock_crossing_io_s0_readdata), // .readdata
.av_writedata (clock_crossing_io_s0_writedata), // .writedata
.av_burstcount (clock_crossing_io_s0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_s0_byteenable), // .byteenable
.av_readdatavalid (clock_crossing_io_s0_readdatavalid), // .readdatavalid
.av_waitrequest (clock_crossing_io_s0_waitrequest), // .waitrequest
.av_debugaccess (clock_crossing_io_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keycode_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keycode_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.uav_read (keycode_s1_agent_m0_read), // .read
.uav_write (keycode_s1_agent_m0_write), // .write
.uav_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keycode_s1_agent_m0_readdata), // .readdata
.uav_writedata (keycode_s1_agent_m0_writedata), // .writedata
.uav_lock (keycode_s1_agent_m0_lock), // .lock
.uav_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keycode_s1_address), // avalon_anti_slave_0.address
.av_write (keycode_s1_write), // .write
.av_readdata (keycode_s1_readdata), // .readdata
.av_writedata (keycode_s1_writedata), // .writedata
.av_chipselect (keycode_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clocks_pll_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clocks_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (clocks_pll_slave_agent_m0_lock), // .lock
.m0_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clocks_pll_slave_agent_m0_read), // .read
.m0_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.m0_write (clocks_pll_slave_agent_m0_write), // .write
.rp_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clocks_pll_slave_agent_rp_ready), // .ready
.rp_valid (clocks_pll_slave_agent_rp_valid), // .valid
.rp_data (clocks_pll_slave_agent_rp_data), // .data
.rp_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clocks_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clocks_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clocks_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clocks_pll_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clocks_pll_slave_agent_rf_source_data), // in.data
.in_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.in_ready (clocks_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (clocks_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clock_crossing_io_s0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clock_crossing_io_s0_agent_m0_address), // m0.address
.m0_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.m0_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clock_crossing_io_s0_agent_m0_read), // .read
.m0_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.m0_write (clock_crossing_io_s0_agent_m0_write), // .write
.rp_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clock_crossing_io_s0_agent_rp_ready), // .ready
.rp_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.rp_data (clock_crossing_io_s0_agent_rp_data), // .data
.rp_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clock_crossing_io_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clock_crossing_io_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (129),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clock_crossing_io_s0_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clock_crossing_io_s0_agent_rf_source_data), // in.data
.in_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.in_ready (clock_crossing_io_s0_agent_rf_source_ready), // .ready
.in_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keycode_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keycode_s1_agent_m0_address), // m0.address
.m0_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keycode_s1_agent_m0_lock), // .lock
.m0_readdata (keycode_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keycode_s1_agent_m0_read), // .read
.m0_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keycode_s1_agent_m0_writedata), // .writedata
.m0_write (keycode_s1_agent_m0_write), // .write
.rp_endofpacket (keycode_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keycode_s1_agent_rp_ready), // .ready
.rp_valid (keycode_s1_agent_rp_valid), // .valid
.rp_data (keycode_s1_agent_rp_data), // .data
.rp_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (keycode_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keycode_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keycode_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keycode_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keycode_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keycode_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keycode_s1_agent_rf_source_data), // in.data
.in_valid (keycode_s1_agent_rf_source_valid), // .valid
.in_ready (keycode_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keycode_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keycode_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
finalproject_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_003 router_003 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_003 router_004 (
.sink_ready (clocks_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (clocks_pll_slave_agent_rp_valid), // .valid
.sink_data (clocks_pll_slave_agent_rp_data), // .data
.sink_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_002 router_005 (
.sink_ready (clock_crossing_io_s0_agent_rp_ready), // sink.ready
.sink_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.sink_data (clock_crossing_io_s0_agent_rp_data), // .data
.sink_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_002 router_006 (
.sink_ready (keycode_s1_agent_rp_ready), // sink.ready
.sink_valid (keycode_s1_agent_rp_valid), // .valid
.sink_data (keycode_s1_agent_rp_data), // .data
.sink_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keycode_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_router_003 router_007 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_cmd_mux_001 cmd_mux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_001_out_ready), // sink1.ready
.sink1_valid (crosser_001_out_valid), // .valid
.sink1_channel (crosser_001_out_channel), // .channel
.sink1_data (crosser_001_out_data), // .data
.sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_demux_001 rsp_demux_005 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (crosser_002_out_ready), // sink5.ready
.sink5_valid (crosser_002_out_valid), // .valid
.sink5_channel (crosser_002_out_channel), // .channel
.sink5_data (crosser_002_out_data), // .data
.sink5_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink5_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
finalproject_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink2_ready (crosser_003_out_ready), // sink2.ready
.sink2_valid (crosser_003_out_valid), // .valid
.sink2_channel (crosser_003_out_channel), // .channel
.sink2_data (crosser_003_out_data), // .data
.sink2_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src5_ready), // in.ready
.in_valid (cmd_demux_src5_valid), // .valid
.in_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.in_channel (cmd_demux_src5_channel), // .channel
.in_data (cmd_demux_src5_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src2_ready), // in.ready
.in_valid (cmd_demux_001_src2_valid), // .valid
.in_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src2_channel), // .channel
.in_data (cmd_demux_001_src2_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src0_ready), // in.ready
.in_valid (rsp_demux_005_src0_valid), // .valid
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_data (rsp_demux_005_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_005_src1_ready), // in.ready
.in_valid (rsp_demux_005_src1_valid), // .valid
.in_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.in_channel (rsp_demux_005_src1_channel), // .channel
.in_data (rsp_demux_005_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t ();
// See also t_math_width
// This shows the uglyness in width warnings across param modules
// TODO: Would be nice to also show relevant parameter settings
p #(.WIDTH(4)) p4 (.in(4'd0));
p #(.WIDTH(5)) p5 (.in(5'd0));
//====
localparam [3:0] XS = 'hx; // User presumably intended to use 'x
//====
wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax
wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is
//====
localparam WIDTH = 6;
wire one_bit;
wire [2:0] shifter = 1;
wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter);
//====
// We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS
wire one = 1;
wire [2:0] cnt = (one + one + one + one);
endmodule
module p
#(parameter WIDTH=64)
(input [WIDTH-1:0] in);
wire [4:0] out = in;
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The 1cyc_sram_ctrl module control the 1 Cycle SRAM access requests
//
// ====================================================================
module sirv_1cyc_sram_ctrl #(
parameter DW = 32,
parameter MW = 4,
parameter AW = 32,
parameter AW_LSB = 3,
parameter USR_W = 3
)(
output sram_ctrl_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// ITCM SRAM clock gating for debugging purpose
input tcm_cgstop,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// * Cmd channel
input uop_cmd_valid, // Handshake valid
output uop_cmd_ready, // Handshake ready
input uop_cmd_read, // Read or write
input [AW-1:0] uop_cmd_addr,
input [DW-1:0] uop_cmd_wdata,
input [MW-1:0] uop_cmd_wmask,
input [USR_W-1:0] uop_cmd_usr,
// * RSP channel
output uop_rsp_valid, // Response valid
input uop_rsp_ready, // Response ready
output [DW-1:0] uop_rsp_rdata,
output [USR_W-1:0] uop_rsp_usr,
output ram_cs,
output ram_we,
output [AW-AW_LSB-1:0] ram_addr,
output [MW-1:0] ram_wem,
output [DW-1:0] ram_din,
input [DW-1:0] ram_dout,
output clk_ram,
input test_mode,
input clk,
input rst_n
);
sirv_gnrl_pipe_stage # (
.CUT_READY(0),
.DP(1),
.DW(USR_W)
) u_e1_stage (
.i_vld(uop_cmd_valid),
.i_rdy(uop_cmd_ready),
.i_dat(uop_cmd_usr),
.o_vld(uop_rsp_valid),
.o_rdy(uop_rsp_ready),
.o_dat(uop_rsp_usr),
.clk (clk ),
.rst_n(rst_n)
);
assign ram_cs = uop_cmd_valid & uop_cmd_ready;
assign ram_we = (~uop_cmd_read);
assign ram_addr= uop_cmd_addr [AW-1:AW_LSB];
assign ram_wem = uop_cmd_wmask[MW-1:0];
assign ram_din = uop_cmd_wdata[DW-1:0];
wire ram_clk_en = ram_cs | tcm_cgstop;
e203_clkgate u_ram_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (ram_clk_en),
.clk_out (clk_ram)
);
assign uop_rsp_rdata = ram_dout;
assign sram_ctrl_active = uop_cmd_valid | uop_rsp_valid;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2016 05:51:29 PM
// Design Name:
// Module Name: Testbench_Barrel_Shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=3;
parameter SWR=8;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
DW_rbsh_inst uut(
.Data_i(Shift_Data_i),
.Shift_Value_i(Shift_Value_i),
.inst_SH_TC(Left_Right_i),
.Data_o(N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(8*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
Left_Right_i = ~Left_Right_i;
#(8*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
#(PERIOD * 1024);
$finish;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2008 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module gpio_input
(input clock, input reset, input enable,
input out_strobe,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
input wire [15:0] io_rx_a_in, input wire [15:0] io_rx_b_in,
//input wire [15:0] io_tx_a_in, input wire [15:0] io_tx_b_in,
output reg rx_dig0_i, output reg rx_dig0_q,
output reg rx_dig1_i, output reg rx_dig1_q );
// Buffer at input to chip
reg rx_dig_rx_a_a,rx_dig_rx_b_a,rx_dig_rx_a_b,rx_dig_rx_b_b;
//TODO possibly use a flancter here
//This code can optionally be extended to do streaming input from gpio of tx boards
//The code can also be extended to input more bits
always @(posedge clock)
begin
//This is the first point where is determined which physical input gpio pins are used for streaming digital input
//The other point is the code which overrides these pins as input (oe = 0)
//rx_dig_tx_a_a <= #1 io_tx_a_in[14];
//rx_dig_tx_b_a <= #1 io_tx_a_in[15];
rx_dig_rx_a_a <= #1 io_rx_a_in[14];
rx_dig_rx_b_a <= #1 io_rx_a_in[15];
//rx_dig_tx_a_b <= #1 io_tx_b_in[14];
//rx_dig_tx_b_b <= #1 io_tx_b_in[15];
rx_dig_rx_a_b <= #1 io_rx_b_in[14];
rx_dig_rx_b_b <= #1 io_rx_b_in[15];
end
// Now mux to the appropriate outputs
wire [3:0] ddc3mux,ddc2mux,ddc1mux,ddc0mux;
wire rx_realsignals;
wire [3:0] rx_numchan;//not used here
//TODO This setting reg readout is a duplicate of the one in adc_interface.v.
// Change code so this is done in only one place, or give this code its own register.
setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),
.in(serial_data),.out({ddc3mux,ddc2mux,ddc1mux,ddc0mux,rx_realsignals,rx_numchan[3:1]}));
//assign rx_numchan[0] = 1'b0;
always @(posedge clock)
if (out_strobe) //out_strobe determines the time at which the digital inputs are sampled (with a delay of one sample)
begin
rx_dig0_i <= #1 ddc0mux[1] ? (ddc0mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
rx_dig0_q <= #1 rx_realsignals ? 1'b0 : ddc0mux[3] ? (ddc0mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc0mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
rx_dig1_i <= #1 ddc1mux[1] ? (ddc1mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
rx_dig1_q <= #1 rx_realsignals ? 1'b0 : ddc1mux[3] ? (ddc1mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc1mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
//rx_dig2_i <= #1 ddc2mux[1] ? (ddc2mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
//rx_dig2_q <= #1 rx_realsignals ? 1'b0 : ddc2mux[3] ? (ddc2mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc2mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
//rx_dig3_i <= #1 ddc3mux[1] ? (ddc3mux[0] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[0] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
//rx_dig3_q <= #1 rx_realsignals ? 1'b0 : ddc3mux[3] ? (ddc3mux[2] ? rx_dig_rx_b_b : rx_dig_rx_a_b) : (ddc3mux[2] ? rx_dig_rx_b_a : rx_dig_rx_a_a);
end
endmodule // gpio_input
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_ck_addr_cmd_delay.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Shift CK/Address/Commands/Controls
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay #
(
parameter TCQ = 100,
parameter tCK = 3636,
parameter DQS_CNT_WIDTH = 3,
parameter N_CTL_LANES = 3,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
// Start only after PO_CIRC_BUF_DELAY decremented
input cmd_delay_start,
// Control lane being shifted using Phaser_Out fine delay taps
output reg [N_CTL_LANES-1:0] ctl_lane_cnt,
// Inc/dec Phaser_Out fine delay line
output reg po_stg2_f_incdec,
output reg po_en_stg2_f,
output reg po_stg2_c_incdec,
output reg po_en_stg2_c,
// Completed delaying CK/Address/Commands/Controls
output po_ck_addr_cmd_delay_done
);
localparam TAP_CNT_LIMIT = 63;
//Calculate the tap resolution of the PHASER based on the clock period
localparam FREQ_REF_DIV = (tCK > 5000 ? 4 :
tCK > 2500 ? 2 : 1);
localparam integer PHASER_TAP_RES = ((tCK/2)/64);
// Determine whether 300 ps or 350 ps delay required
localparam CALC_TAP_CNT = (tCK >= 1250) ? 350 : 300;
// Determine the number of Phaser_Out taps required to delay by 300 ps
// 300 ps is the PCB trace uncertainty between CK and DQS byte groups
// Increment control byte lanes
localparam TAP_CNT = 0;
//localparam TAP_CNT = (CALC_TAP_CNT + PHASER_TAP_RES - 1)/PHASER_TAP_RES;
//Decrement control byte lanes
localparam TAP_DEC = (SIM_CAL_OPTION == "FAST_CAL") ? 0 : 29;
reg delay_dec_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4 /* synthesis syn_maxfan = 10 */;
reg [5:0] delay_cnt_r;
reg [5:0] delaydec_cnt_r;
reg po_cnt_inc;
reg po_cnt_dec;
reg [3:0] wait_cnt_r;
assign po_ck_addr_cmd_delay_done = ((TAP_CNT == 0) && (TAP_DEC == 0)) ? 1'b1 : delay_done_r4;
always @(posedge clk) begin
if (rst || po_cnt_dec || po_cnt_inc)
wait_cnt_r <= #TCQ 'd8;
else if (cmd_delay_start && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst || (delaydec_cnt_r > 6'd0) || (delay_cnt_r == 'd0) || (TAP_DEC == 0))
po_cnt_inc <= #TCQ 1'b0;
else if ((delay_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_inc <= #TCQ 1'b1;
else
po_cnt_inc <= #TCQ 1'b0;
end
//Tap decrement
always @(posedge clk) begin
if (rst || (delaydec_cnt_r == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (cmd_delay_start && (delaydec_cnt_r > 'd0) && (wait_cnt_r == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
//po_stg2_f_incdec and po_en_stg2_f stay asserted HIGH for TAP_COUNT cycles for every control byte lane
//the alignment is started once the
always @(posedge clk) begin
if (rst) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end else begin
if (po_cnt_dec) begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b1;
end else begin
po_stg2_f_incdec <= #TCQ 1'b0;
po_en_stg2_f <= #TCQ 1'b0;
end
if (po_cnt_inc) begin
po_stg2_c_incdec <= #TCQ 1'b1;
po_en_stg2_c <= #TCQ 1'b1;
end else begin
po_stg2_c_incdec <= #TCQ 1'b0;
po_en_stg2_c <= #TCQ 1'b0;
end
end
end
// delay counter to count 2 cycles
// Increment coarse taps by 2 for all control byte lanes
// to mitigate late writes
always @(posedge clk) begin
// load delay counter with init value
if (rst || (tCK > 2500) || (SIM_CAL_OPTION == "FAST_CAL"))
delay_cnt_r <= #TCQ 'd0;
else if ((delaydec_cnt_r > 6'd0) ||((delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delay_cnt_r <= #TCQ 'd1;
else if (po_cnt_inc && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// delay counter to count TAP_DEC cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_DEC
if (rst || ~cmd_delay_start ||((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 6'd0) && (ctl_lane_cnt != N_CTL_LANES-1)))
delaydec_cnt_r <= #TCQ TAP_DEC;
else if (po_cnt_dec && (delaydec_cnt_r > 6'd0))
delaydec_cnt_r <= #TCQ delaydec_cnt_r - 1;
end
//ctl_lane_cnt is used to count the number of CTL_LANES or byte lanes that have the address/command phase shifted by 1/4 mem. cycle
//This ensures all ctrl byte lanes have had their output phase shifted.
always @(posedge clk) begin
if (rst || ~cmd_delay_start )
ctl_lane_cnt <= #TCQ 6'b0;
else if (~delay_dec_done && (ctl_lane_cnt == N_CTL_LANES-1) && (delaydec_cnt_r == 6'd1))
ctl_lane_cnt <= #TCQ ctl_lane_cnt;
else if ((ctl_lane_cnt != N_CTL_LANES-1) && (delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0))
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
end
// All control lanes have decremented to 31 fine taps from 46
always @(posedge clk) begin
if (rst || ~cmd_delay_start) begin
delay_dec_done <= #TCQ 1'b0;
end else if (((TAP_CNT == 0) && (TAP_DEC == 0)) ||
((delaydec_cnt_r == 6'd0) && (delay_cnt_r == 'd0) && (ctl_lane_cnt == N_CTL_LANES-1))) begin
delay_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_dec_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_nvme.vh"
module pcie_cntl_reg # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
output mreq_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_rd_data,
input mreq_fifo_empty_n,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RD_HEAD = 9'b000000010;
localparam S_PCIE_ADDR = 9'b000000100;
localparam S_PCIE_WAIT_WR_DATA = 9'b000001000;
localparam S_PCIE_WR_DATA = 9'b000010000;
localparam S_PCIE_MWR = 9'b000100000;
localparam S_PCIE_MRD = 9'b001000000;
localparam S_PCIE_CPLD_REQ = 9'b010000000;
localparam S_PCIE_CPLD_ACK = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg r_intms_ivms;
reg r_intmc_ivmc;
reg r_cq_irq_status;
reg [23:20] r_cc_iocqes;
reg [19:16] r_cc_iosqes;
reg [15:14] r_cc_shn;
reg [13:11] r_cc_asm;
reg [10:7] r_cc_mps;
reg [6:4] r_cc_ccs;
reg [0:0] r_cc_en;
reg [23:16] r_aqa_acqs;
reg [7:0] r_aqa_asqs;
reg [C_PCIE_ADDR_WIDTH-1:2] r_asq_asqb;
reg [C_PCIE_ADDR_WIDTH-1:2] r_acq_acqb;
reg [7:0] r_reg_sq0tdbl;
reg [7:0] r_reg_sq1tdbl;
reg [7:0] r_reg_sq2tdbl;
reg [7:0] r_reg_sq3tdbl;
reg [7:0] r_reg_sq4tdbl;
reg [7:0] r_reg_sq5tdbl;
reg [7:0] r_reg_sq6tdbl;
reg [7:0] r_reg_sq7tdbl;
reg [7:0] r_reg_sq8tdbl;
reg [7:0] r_reg_cq0hdbl;
reg [7:0] r_reg_cq1hdbl;
reg [7:0] r_reg_cq2hdbl;
reg [7:0] r_reg_cq3hdbl;
reg [7:0] r_reg_cq4hdbl;
reg [7:0] r_reg_cq5hdbl;
reg [7:0] r_reg_cq6hdbl;
reg [7:0] r_reg_cq7hdbl;
reg [7:0] r_reg_cq8hdbl;
reg [8:0] r_cq_head_update;
wire [31:0] w_pcie_head0;
wire [31:0] w_pcie_head1;
wire [31:0] w_pcie_head2;
wire [31:0] w_pcie_head3;
reg [31:0] r_pcie_head2;
reg [31:0] r_pcie_head3;
wire [2:0] w_mreq_head_fmt;
//wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
//wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_attr0;
//wire [1:0] w_mreq_head_at;
wire [9:0] w_mreq_head_len;
wire [7:0] w_mreq_head_req_bus_num;
wire [4:0] w_mreq_head_req_dev_num;
wire [2:0] w_mreq_head_req_func_num;
wire [15:0] w_mreq_head_req_id;
wire [7:0] w_mreq_head_tag;
wire [3:0] w_mreq_head_last_be;
wire [3:0] w_mreq_head_1st_be;
//reg [4:0] r_rx_np_req_cnt;
//reg r_rx_np_req;
wire w_mwr;
wire w_4dw;
reg [2:0] r_mreq_head_fmt;
reg [9:0] r_mreq_head_len;
reg [15:0] r_mreq_head_req_id;
reg [7:0] r_mreq_head_tag;
reg [3:0] r_mreq_head_last_be;
reg [3:0] r_mreq_head_1st_be;
reg [12:0] r_mreq_addr;
reg [63:0] r_mreq_data;
reg [3:0] r_cpld_bc;
reg r_lbytes_en;
reg r_hbytes_en;
reg r_wr_reg;
reg r_wr_doorbell;
reg r_tx_cpld_req;
reg [63:0] r_rd_data;
reg [63:0] r_rd_reg;
reg [63:0] r_rd_doorbell;
reg r_mreq_fifo_rd_en;
wire [8:0] w_sq_rst_n;
wire [8:0] w_cq_rst_n;
//pcie mrd or mwr, memory rd/wr request
assign w_pcie_head0 = mreq_fifo_rd_data[31:0];
assign w_pcie_head1 = mreq_fifo_rd_data[63:32];
assign w_pcie_head2 = mreq_fifo_rd_data[95:64];
assign w_pcie_head3 = mreq_fifo_rd_data[127:96];
assign w_mreq_head_fmt = w_pcie_head0[31:29];
//assign w_mreq_head_type = w_pcie_head0[28:24];
//assign w_mreq_head_tc = w_pcie_head0[22:20];
//assign w_mreq_head_attr1 = w_pcie_head0[18];
//assign w_mreq_head_th = w_pcie_head0[16];
//assign w_mreq_head_td = w_pcie_head0[15];
//assign w_mreq_head_ep = w_pcie_head0[14];
//assign w_mreq_head_attr0 = w_pcie_head0[13:12];
//assign w_mreq_head_at = w_pcie_head0[11:10];
assign w_mreq_head_len = w_pcie_head0[9:0];
assign w_mreq_head_req_bus_num = w_pcie_head1[31:24];
assign w_mreq_head_req_dev_num = w_pcie_head1[23:19];
assign w_mreq_head_req_func_num = w_pcie_head1[18:16];
assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
assign w_mreq_head_tag = w_pcie_head1[15:8];
assign w_mreq_head_last_be = w_pcie_head1[7:4];
assign w_mreq_head_1st_be = w_pcie_head1[3:0];
assign w_mwr = r_mreq_head_fmt[1];
assign w_4dw = r_mreq_head_fmt[0];
assign tx_cpld_req = r_tx_cpld_req;
assign tx_cpld_tag = r_mreq_head_tag;
assign tx_cpld_req_id = r_mreq_head_req_id;
assign tx_cpld_len = {8'b0, r_mreq_head_len[1:0]};
assign tx_cpld_bc = {8'b0, r_cpld_bc};
assign tx_cpld_laddr = r_mreq_addr[6:0];
assign tx_cpld_data = (r_mreq_addr[2] == 1) ? {32'b0, r_rd_data[63:32]} : r_rd_data;
assign rx_np_ok = 1'b1;
assign rx_np_req = 1'b1;
assign mreq_fifo_rd_en = r_mreq_fifo_rd_en;
assign admin_sq_bs_addr = r_asq_asqb;
assign admin_cq_bs_addr = r_acq_acqb;
assign nvme_cc_en = r_cc_en;
assign nvme_cc_shn = r_cc_shn;
assign nvme_intms_ivms = r_intms_ivms;
assign nvme_intmc_ivmc = r_intmc_ivmc;
assign admin_sq_size = r_aqa_asqs;
assign admin_cq_size = r_aqa_acqs;
assign admin_sq_tail_ptr = r_reg_sq0tdbl;
assign io_sq1_tail_ptr = r_reg_sq1tdbl;
assign io_sq2_tail_ptr = r_reg_sq2tdbl;
assign io_sq3_tail_ptr = r_reg_sq3tdbl;
assign io_sq4_tail_ptr = r_reg_sq4tdbl;
assign io_sq5_tail_ptr = r_reg_sq5tdbl;
assign io_sq6_tail_ptr = r_reg_sq6tdbl;
assign io_sq7_tail_ptr = r_reg_sq7tdbl;
assign io_sq8_tail_ptr = r_reg_sq8tdbl;
assign admin_cq_head_ptr = r_reg_cq0hdbl;
assign io_cq1_head_ptr = r_reg_cq1hdbl;
assign io_cq2_head_ptr = r_reg_cq2hdbl;
assign io_cq3_head_ptr = r_reg_cq3hdbl;
assign io_cq4_head_ptr = r_reg_cq4hdbl;
assign io_cq5_head_ptr = r_reg_cq5hdbl;
assign io_cq6_head_ptr = r_reg_cq6hdbl;
assign io_cq7_head_ptr = r_reg_cq7hdbl;
assign io_cq8_head_ptr = r_reg_cq8hdbl;
assign cq_head_update = r_cq_head_update;
always @ (posedge pcie_user_clk)
begin
r_cq_irq_status <= cq_irq_status;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_RD_HEAD;
else
next_state <= S_IDLE;
end
S_PCIE_RD_HEAD: begin
next_state <= S_PCIE_ADDR;
end
S_PCIE_ADDR: begin
if(w_mwr == 1) begin
if(w_4dw == 1 || r_mreq_head_len[1] == 1) begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
else
next_state <= S_PCIE_MWR;
end
else begin
next_state <= S_PCIE_MRD;
end
end
S_PCIE_WAIT_WR_DATA: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
S_PCIE_WR_DATA: begin
next_state <= S_PCIE_MWR;
end
S_PCIE_MWR: begin
next_state <= S_IDLE;
end
S_PCIE_MRD: begin
next_state <= S_PCIE_CPLD_REQ;
end
S_PCIE_CPLD_REQ: begin
next_state <= S_PCIE_CPLD_ACK;
end
S_PCIE_CPLD_ACK: begin
if(tx_cpld_req_ack == 1)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CPLD_ACK;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RD_HEAD: begin
r_mreq_head_fmt <= w_mreq_head_fmt;
r_mreq_head_len <= w_mreq_head_len;
r_mreq_head_req_id <= w_mreq_head_req_id;
r_mreq_head_tag <= w_mreq_head_tag;
r_mreq_head_last_be <= w_mreq_head_last_be;
r_mreq_head_1st_be <= w_mreq_head_1st_be;
r_pcie_head2 <= w_pcie_head2;
r_pcie_head3 <= w_pcie_head3;
end
S_PCIE_ADDR: begin
if(w_4dw == 1) begin
r_mreq_addr[12:2] <= r_pcie_head3[12:2];
r_lbytes_en <= ~r_pcie_head3[2] & (r_pcie_head3[11:7] == 0);
r_hbytes_en <= (r_pcie_head3[2] | r_mreq_head_len[1]) & (r_pcie_head3[11:7] == 0);
end
else begin
r_mreq_addr[12:2] <= r_pcie_head2[12:2];
r_lbytes_en <= ~r_pcie_head2[2] & (r_pcie_head2[11:7] == 0);;
r_hbytes_en <= (r_pcie_head2[2] | r_mreq_head_len[1]) & (r_pcie_head2[11:7] == 0);
if(r_pcie_head2[2] == 1)
r_mreq_data[63:32] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
else
r_mreq_data[31:0] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
end
end
S_PCIE_WAIT_WR_DATA: begin
end
S_PCIE_WR_DATA: begin
if(w_4dw == 1) begin
if(r_mreq_addr[2] == 1)
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
else begin
r_mreq_data[31:0] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
r_mreq_data[63:32] <= {mreq_fifo_rd_data[39:32], mreq_fifo_rd_data[47:40], mreq_fifo_rd_data[55:48], mreq_fifo_rd_data[63:56]};
end
end
else
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
end
S_PCIE_MWR: begin
end
S_PCIE_MRD: begin
if(r_lbytes_en | r_hbytes_en) begin
if(r_mreq_addr[12] == 1) begin
r_rd_data[31:0] <= {r_rd_doorbell[7:0], r_rd_doorbell[15:8], r_rd_doorbell[23:16], r_rd_doorbell[31:24]};
r_rd_data[63:32] <= {r_rd_doorbell[39:32], r_rd_doorbell[47:40], r_rd_doorbell[55:48], r_rd_doorbell[63:56]};
end
else begin
r_rd_data[31:0] <= {r_rd_reg[7:0], r_rd_reg[15:8], r_rd_reg[23:16], r_rd_reg[31:24]};
r_rd_data[63:32] <= {r_rd_reg[39:32], r_rd_reg[47:40], r_rd_reg[55:48], r_rd_reg[63:56]};
end
end
else
r_rd_data <= 64'b0;
if(r_mreq_head_1st_be[0] == 1)
r_mreq_addr[1:0] <= 2'b00;
else if(r_mreq_head_1st_be[1] == 1)
r_mreq_addr[1:0] <= 2'b01;
else if(r_mreq_head_1st_be[2] == 1)
r_mreq_addr[1:0] <= 2'b10;
else
r_mreq_addr[1:0] <= 2'b11;
r_cpld_bc <= ((r_mreq_head_1st_be[0] + r_mreq_head_1st_be[1])
+ (r_mreq_head_1st_be[2] + r_mreq_head_1st_be[3]))
+ ((r_mreq_head_last_be[0] + r_mreq_head_last_be[1])
+ (r_mreq_head_last_be[2] + r_mreq_head_last_be[3]));
end
S_PCIE_CPLD_REQ: begin
end
S_PCIE_CPLD_ACK: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_RD_HEAD: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_ADDR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WAIT_WR_DATA: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WR_DATA: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MWR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= ~r_mreq_addr[12];
r_wr_doorbell <= r_mreq_addr[12];
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MRD: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_CPLD_REQ: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 1;
//r_rx_np_req <= 1;
end
S_PCIE_CPLD_ACK: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
default: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
{r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en} <= 0;
{r_aqa_acqs, r_aqa_asqs} <= 0;
r_asq_asqb <= 0;
r_acq_acqb <= 0;
end
else begin
if(r_wr_reg == 1) begin
if(r_lbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h5: r_asq_asqb[31:2] <= r_mreq_data[31:2];
4'h6: r_acq_acqb[31:2] <= r_mreq_data[31:2];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intmc_ivmc <= r_mreq_data[0];
else
r_intmc_ivmc <= 0;
end
if(r_hbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h2: {r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en}
<= {r_mreq_data[55:52], r_mreq_data[51:48], r_mreq_data[47:46], r_mreq_data[45:43], r_mreq_data[42:39], r_mreq_data[38:36], r_mreq_data[32]};
4'h4: {r_aqa_acqs, r_aqa_asqs} <= {r_mreq_data[55:48], r_mreq_data[39:32]};
4'h5: r_asq_asqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
4'h6: r_acq_acqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intms_ivms <= r_mreq_data[32];
else
r_intms_ivms <= 0;
end
end
else begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
end
end
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_reg_sq0tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1)
r_reg_sq0tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_reg_sq1tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1)
r_reg_sq1tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_reg_sq2tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1)
r_reg_sq2tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_reg_sq3tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1)
r_reg_sq3tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_reg_sq4tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1)
r_reg_sq4tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_reg_sq5tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1)
r_reg_sq5tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_reg_sq6tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1)
r_reg_sq6tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_reg_sq7tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1)
r_reg_sq7tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_reg_sq8tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1)
r_reg_sq8tdbl <= r_mreq_data[7:0];
end
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_reg_cq0hdbl <= 0;
r_cq_head_update[0] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1) begin
r_reg_cq0hdbl <= r_mreq_data[39:32];
r_cq_head_update[0] <= 1;
end
else
r_cq_head_update[0] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_reg_cq1hdbl <= 0;
r_cq_head_update[1] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1) begin
r_reg_cq1hdbl <= r_mreq_data[39:32];
r_cq_head_update[1] <= 1;
end
else
r_cq_head_update[1] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_reg_cq2hdbl <= 0;
r_cq_head_update[2] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1) begin
r_reg_cq2hdbl <= r_mreq_data[39:32];
r_cq_head_update[2] <= 1;
end
else
r_cq_head_update[2] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_reg_cq3hdbl <= 0;
r_cq_head_update[3] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1) begin
r_reg_cq3hdbl <= r_mreq_data[39:32];
r_cq_head_update[3] <= 1;
end
else
r_cq_head_update[3] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_reg_cq4hdbl <= 0;
r_cq_head_update[4] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1) begin
r_reg_cq4hdbl <= r_mreq_data[39:32];
r_cq_head_update[4] <= 1;
end
else
r_cq_head_update[4] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_reg_cq5hdbl <= 0;
r_cq_head_update[5] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1) begin
r_reg_cq5hdbl <= r_mreq_data[39:32];
r_cq_head_update[5] <= 1;
end
else
r_cq_head_update[5] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_reg_cq6hdbl <= 0;
r_cq_head_update[6] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1) begin
r_reg_cq6hdbl <= r_mreq_data[39:32];
r_cq_head_update[6] <= 1;
end
else
r_cq_head_update[6] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_reg_cq7hdbl <= 0;
r_cq_head_update[7] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1) begin
r_reg_cq7hdbl <= r_mreq_data[39:32];
r_cq_head_update[7] <= 1;
end
else
r_cq_head_update[7] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_reg_cq8hdbl <= 0;
r_cq_head_update[8] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1) begin
r_reg_cq8hdbl <= r_mreq_data[39:32];
r_cq_head_update[8] <= 1;
end
else
r_cq_head_update[8] <= 0;
end
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_reg <= {8'h0, `D_CAP_MPSMAX, `D_CAP_MPSMIN, 3'h0, `D_CAP_CSS, `D_CAP_NSSRS, `D_CAP_DSTRD, `D_CAP_TO, 5'h0, `D_CAP_AMS, `D_CAP_CQR, `D_CAP_MQES};
4'h1: r_rd_reg <= {31'b0, r_cq_irq_status, `D_VS_MJR, `D_VS_MNR, 8'b0};
4'h2: r_rd_reg <= {8'b0, r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, 3'b0, r_cc_en, 31'b0, r_cq_irq_status};
4'h3: r_rd_reg <= {28'b0, nvme_csts_shst, 1'b0, nvme_csts_rdy, 32'b0};
4'h4: r_rd_reg <= {8'b0, r_aqa_acqs, 8'b0, r_aqa_asqs, 32'b0};
4'h5: r_rd_reg <= {26'b0, r_asq_asqb, 2'b0};
4'h6: r_rd_reg <= {26'b0, r_acq_acqb, 2'b0};
default: r_rd_reg <= 64'b0;
endcase
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_doorbell <= {24'b0, r_reg_cq0hdbl, 24'b0, r_reg_sq0tdbl};
4'h1: r_rd_doorbell <= {24'b0, r_reg_cq1hdbl, 24'b0, r_reg_sq1tdbl};
4'h2: r_rd_doorbell <= {24'b0, r_reg_cq2hdbl, 24'b0, r_reg_sq2tdbl};
4'h3: r_rd_doorbell <= {24'b0, r_reg_cq3hdbl, 24'b0, r_reg_sq3tdbl};
4'h4: r_rd_doorbell <= {24'b0, r_reg_cq4hdbl, 24'b0, r_reg_sq4tdbl};
4'h5: r_rd_doorbell <= {24'b0, r_reg_cq5hdbl, 24'b0, r_reg_sq5tdbl};
4'h6: r_rd_doorbell <= {24'b0, r_reg_cq6hdbl, 24'b0, r_reg_sq6tdbl};
4'h7: r_rd_doorbell <= {24'b0, r_reg_cq7hdbl, 24'b0, r_reg_sq7tdbl};
4'h8: r_rd_doorbell <= {24'b0, r_reg_cq8hdbl, 24'b0, r_reg_sq8tdbl};
default: r_rd_doorbell <= 64'b0;
endcase
end
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench UART Decoder ////
//// ////
//// Description ////
//// ORPSoC Testbench UART output decoder ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - jb, [email protected] ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
`timescale 1ns/1ns
module uart_decoder(clk, uart_tx);
input clk;
input uart_tx;
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
// Something to trigger the task
always @(posedge clk)
uart_decoder;
task uart_decoder;
reg [7:0] tx_byte;
begin
while (uart_tx !== 1'b1)
@(uart_tx);
// Wait for start bit
while (uart_tx !== 1'b0)
@(uart_tx);
#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
tx_byte[0] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[1] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[2] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[3] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[4] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[5] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[6] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[7] = uart_tx;
#uart_baudrate_period_ns;
//Check for stop bit
if (uart_tx !== 1'b1)
begin
// Wait for return to idle
while (uart_tx !== 1'b1)
@(uart_tx);
end
// display the char
$write("%c", tx_byte);
end
endtask // user_uart_read_byte
endmodule // uart_decoder
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O32AI_TB_V
`define SKY130_FD_SC_HDLL__O32AI_TB_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o32ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hdll__o32ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O32AI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_PP_V |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6,
READ_STATE_PULSE_SE = 7;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [1:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1,
READ_VALID_PRE_READING = 2;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output reg [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg [1:0] avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
flash_addr_wire_neg_reg <= { flash_sector_addr, 1'b0, {(19){1'b1}}};
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire_neg_reg;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
always @(posedge clock) begin
if (~reset_n_w | ~csr_status_r_pass) begin
avmm_readdata <= 32'hffffffff;
end
else begin
avmm_readdata <= flash_drdout;
end
end
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_PULSE_SE;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_PULSE_SE;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
read_wait <= 0;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_PULSE_SE;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_READ;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_PRE_READING;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_BEHAVIORAL_V |
module top;
reg pass = 1'b1;
real in, bin;
wire [7:0] out = in;
wire signed [34:0] big = bin;
initial begin
// $monitor(in,, out,, bin,, big);
bin = 8589934592.5; // 2**33+0.5 overflows a 32 bit long.
#1;
if (big !== 35'sd8589934593) begin
$display("Failed: multiword check, expected 8589934593, got %d", big);
pass = 1'b0;
end
if (out !== 'b0) begin
$display("Failed: initial value, expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.499999;
bin = -25.5; // This test a different branch (small result -> big vec.).
#1;
if (big !== -26) begin
$display("Failed: small value multiword check, expected -26, got %d", out);
pass = 1'b0;
end
if (out !== 8'b0) begin
$display("Failed: rounding value (down, +), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = -0.499999;
#1;
if (out !== 8'b0) begin
$display("Failed: rounding value (down, -), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.5;
#1;
if (out !== 8'b01) begin
$display("Failed: rounding value (up, +), expected 8'b01, got %b", out);
pass = 1'b0;
end
in = -0.5;
#1;
if (out !== 8'b11111111) begin
$display("Failed: rounding value (up, -), expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 256.0;
#1;
if (out !== 8'b0) begin
$display("Failed: overflow expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 511.0;
#1;
if (out !== 8'b11111111) begin
$display("Failed: pruning expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: +inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = -1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: -inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = sqrt(-1.0);
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: nan expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = 8589934720.5;
#1;
if (out !== 129) begin
$display("Failed: overflow value expected 129, got %d", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter nXSDLL = 512,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, insert_maint_r,
// Inputs
clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,
maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,
slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input init_calib_complete;
wire accept_internal_ns = init_calib_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (init_calib_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
reg periodic_rd_cntr_r ;
always @(posedge clk) begin
if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;
else if (periodic_rd_r && periodic_rd_ack_r_lcl)
periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;
end
wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);
// wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Report an overall idle status
output idle;
assign idle = init_calib_complete && &idle_r;
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
mig_7series_v2_3_round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) begin
if (hi_priority)
was_priority <= #TCQ 1'b1;
else
was_priority <= #TCQ 1'b0;
end
// DRAM maintenance (refresh and ZQ) and self-refresh controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input maint_sre_r;
input maint_srx_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
wire start_maint;
wire maint_end;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r || maint_wip_r_lcl);
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer
// below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || maint_req_r);
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ and self-refresh hit on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear;
reg maint_rdy_r1;
reg maint_srx_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;
assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ, SRE or SRX commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, SRE and SRX, each rank present will receive a command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count
or rst or send_cnt_r or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ
// command until the end of the maintenance operation.
// Compute values for RFC, ZQ and XSDLL periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?
nRFC :
(nCK_PER_CLK == 2) ?
((nRFC/2) + (nRFC%2)) :
// (nCK_PER_CLK == 4)
((nRFC/4) + ((nRFC%4) ? 1 : 0));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?
tZQCS :
(nCK_PER_CLK == 2) ?
((tZQCS/2) + (tZQCS%2)) :
// (nCK_PER_CLK == 4)
((tZQCS/4) + ((tZQCS%4) ? 1 : 0));
localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?
nXSDLL :
(nCK_PER_CLK == 2) ?
((nXSDLL/2) + (nXSDLL%2)) :
// (nCK_PER_CLK == 4)
((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));
localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_xsdll_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r
or rfc_zq_xsdll_timer_r or rst) begin
rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;
if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?
nZQCS_CLKS :
maint_sre_r ?
{RFC_ZQ_TIMER_WIDTH{1'b0}} :
maint_srx_r ?
nXSDLL_CLKS :
nRFC_CLKS;
else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =
rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;
// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_xsdll_timer
endgenerate
endmodule // bank_common
|
// -*- Mode: Verilog -*-
// Filename : vgpr_contention_tracker.v
// Description : Implements a contention tracker for the vgpr register file
// Author : Mario Paulo Drumond
// Created On : Sat Aug 31 21:57:26 2013
// Last Modified By: Mario Paulo Drumond
// Last Modified On: Sat Aug 31 21:57:26 2013
// Update Count : 0
// Status : Unknown, Use with caution!
module vgpr_contention_tracker
(/*AUTOARG*/
// Inputs
clk, rst, lsu_source1_rd_en, lsu_source2_rd_en,
simd0_source1_rd_en, simd1_source1_rd_en, simd2_source1_rd_en,
simd3_source1_rd_en, simd0_source2_rd_en, simd1_source2_rd_en,
simd2_source2_rd_en, simd3_source2_rd_en, simd0_source3_rd_en,
simd1_source3_rd_en, simd2_source3_rd_en, simd3_source3_rd_en,
simd0_wr_en, simd1_wr_en, simd2_wr_en, simd3_wr_en,
simf0_source1_rd_en, simf1_source1_rd_en, simf2_source1_rd_en,
simf3_source1_rd_en, simf0_source2_rd_en, simf1_source2_rd_en,
simf2_source2_rd_en, simf3_source2_rd_en, simf0_source3_rd_en,
simf1_source3_rd_en, simf2_source3_rd_en, simf3_source3_rd_en,
simf0_wr_en, simf1_wr_en, simf2_wr_en, simf3_wr_en, lsu_dest_wr_en,
simd0_source1_addr, simd1_source1_addr, simd2_source1_addr,
simd3_source1_addr, simd0_source2_addr, simd1_source2_addr,
simd2_source2_addr, simd3_source2_addr, simd0_source3_addr,
simd1_source3_addr, simd2_source3_addr, simd3_source3_addr,
simd0_dest_addr, simd1_dest_addr, simd2_dest_addr, simd3_dest_addr,
simf0_source1_addr, simf1_source1_addr, simf2_source1_addr,
simf3_source1_addr, simf0_source2_addr, simf1_source2_addr,
simf2_source2_addr, simf3_source2_addr, simf0_source3_addr,
simf1_source3_addr, simf2_source3_addr, simf3_source3_addr,
simf0_dest_addr, simf1_dest_addr, simf2_dest_addr, simf3_dest_addr,
lsu_source1_addr, lsu_source2_addr, lsu_dest_addr, rfa_select_fu,
fetch2tracemon_dispatch, issue2fetchwave_wf_done_en,
issue2fetchwave_wf_done_wf_id, fetch2tracemon_new_wfid
) ;
input clk;
input rst;
input lsu_source1_rd_en, lsu_source2_rd_en;
input simd0_source1_rd_en, simd1_source1_rd_en, simd2_source1_rd_en,
simd3_source1_rd_en, simd0_source2_rd_en, simd1_source2_rd_en,
simd2_source2_rd_en, simd3_source2_rd_en, simd0_source3_rd_en,
simd1_source3_rd_en, simd2_source3_rd_en, simd3_source3_rd_en,
simd0_wr_en, simd1_wr_en, simd2_wr_en, simd3_wr_en, simf0_source1_rd_en,
simf1_source1_rd_en, simf2_source1_rd_en, simf3_source1_rd_en,
simf0_source2_rd_en, simf1_source2_rd_en, simf2_source2_rd_en,
simf3_source2_rd_en, simf0_source3_rd_en, simf1_source3_rd_en,
simf2_source3_rd_en, simf3_source3_rd_en, simf0_wr_en, simf1_wr_en,
simf2_wr_en, simf3_wr_en;
input [3:0] lsu_dest_wr_en;
input [9:0] simd0_source1_addr, simd1_source1_addr, simd2_source1_addr,
simd3_source1_addr, simd0_source2_addr, simd1_source2_addr,
simd2_source2_addr, simd3_source2_addr, simd0_source3_addr,
simd1_source3_addr, simd2_source3_addr, simd3_source3_addr,
simd0_dest_addr, simd1_dest_addr, simd2_dest_addr, simd3_dest_addr,
simf0_source1_addr, simf1_source1_addr, simf2_source1_addr,
simf3_source1_addr, simf0_source2_addr, simf1_source2_addr,
simf2_source2_addr, simf3_source2_addr, simf0_source3_addr,
simf1_source3_addr, simf2_source3_addr, simf3_source3_addr,
simf0_dest_addr, simf1_dest_addr, simf2_dest_addr, simf3_dest_addr,
lsu_source1_addr, lsu_source2_addr, lsu_dest_addr;
input [15:0] rfa_select_fu;
input fetch2tracemon_dispatch; //1
input issue2fetchwave_wf_done_en;
input [5:0] issue2fetchwave_wf_done_wf_id;
input [5:0] fetch2tracemon_new_wfid; //6
wire rd_src1_rd_en, rd_src2_rd_en, rd_src3_rd_en;
wire [9:0] rd_src1_addr, rd_src2_addr, rd_src3_addr;
wire wr_alu_wr_en;
wire [9:0] wr_alu_addr;
reg [39:0] live_wf;
integer contention_access_counter, access_counter;
reg end_of_execution;
localparam BANK_SIZE = 16;
localparam BANK_ADDR_SIZE = 4;
integer curr_bank_access[0:BANK_SIZE-1];
reg [BANK_ADDR_SIZE-1:0] rd_src1_bank_addr, rd_src2_bank_addr, rd_src3_bank_addr,
wr_alu_bank_addr, wr_lsu_bank_addr;
assign rd_src1_rd_en = |{simd0_source1_rd_en, simd1_source1_rd_en,
simd2_source1_rd_en, simd3_source1_rd_en,
simf0_source1_rd_en, simf1_source1_rd_en,
simf2_source1_rd_en, simf3_source1_rd_en};
assign rd_src1_addr = simd0_source1_rd_en? simd0_source1_addr :
simd1_source1_rd_en? simd1_source1_addr :
simd2_source1_rd_en? simd2_source1_addr :
simd3_source1_rd_en? simd3_source1_addr :
simf0_source1_rd_en? simf0_source1_addr :
simf1_source1_rd_en? simf1_source1_addr :
simf2_source1_rd_en? simf2_source1_addr :
simf3_source1_rd_en? simf3_source1_addr :
10'h0;
assign rd_src2_rd_en = |{simd0_source2_rd_en, simd1_source2_rd_en,
simd2_source2_rd_en, simd3_source2_rd_en,
simf0_source2_rd_en, simf1_source2_rd_en,
simf2_source2_rd_en, simf3_source2_rd_en};
assign rd_src2_addr = simd0_source2_rd_en? simd0_source2_addr :
simd1_source2_rd_en? simd1_source2_addr :
simd2_source2_rd_en? simd2_source2_addr :
simd3_source2_rd_en? simd3_source2_addr :
simf0_source2_rd_en? simf0_source2_addr :
simf1_source2_rd_en? simf1_source2_addr :
simf2_source2_rd_en? simf2_source2_addr :
simf3_source2_rd_en? simf3_source2_addr :
10'h0;
assign rd_src3_rd_en = |{simd0_source3_rd_en, simd1_source3_rd_en,
simd2_source3_rd_en, simd3_source3_rd_en,
simf0_source3_rd_en, simf1_source3_rd_en,
simf2_source3_rd_en, simf3_source3_rd_en};
assign rd_src3_addr = simd0_source3_rd_en? simd0_source3_addr :
simd1_source3_rd_en? simd1_source3_addr :
simd2_source3_rd_en? simd2_source3_addr :
simd3_source3_rd_en? simd3_source3_addr :
simf0_source3_rd_en? simf0_source3_addr :
simf1_source3_rd_en? simf1_source3_addr :
simf2_source3_rd_en? simf2_source3_addr :
simf3_source3_rd_en? simf3_source3_addr :
10'h0;
assign wr_alu_wr_en = |rfa_select_fu;
assign wr_alu_addr = rfa_select_fu[0]? simd0_dest_addr :
rfa_select_fu[1]? simd1_dest_addr :
rfa_select_fu[2]? simd2_dest_addr :
rfa_select_fu[3]? simd3_dest_addr :
rfa_select_fu[4]? simf0_dest_addr :
rfa_select_fu[5]? simf1_dest_addr :
rfa_select_fu[6]? simf2_dest_addr :
rfa_select_fu[7]? simf3_dest_addr :
10'h0;
integer i;
assign rd_src1_bank_addr = rd_src1_addr[BANK_ADDR_SIZE-1:0];
assign rd_src2_bank_addr = rd_src2_addr[BANK_ADDR_SIZE-1:0];
assign rd_src3_bank_addr = rd_src3_addr[BANK_ADDR_SIZE-1:0];
assign wr_alu_bank_addr = wr_alu_addr[BANK_ADDR_SIZE-1:0];
assign wr_lsu_bank_addr = lsu_dest_addr[BANK_ADDR_SIZE-1:0];
// Block that keeps track of contention accesses
always @(negedge clk) begin
// Clear the counter for bank access in this cycle
for (i = 0; i<BANK_SIZE; i= i+1) begin
curr_bank_access[i] = 0;
end
// Account for accesses of each port to the respective bank
if(rd_src1_rd_en) begin
curr_bank_access[rd_src1_bank_addr] = curr_bank_access[rd_src1_bank_addr]+1;
access_counter = access_counter + 1;
end
if(rd_src2_rd_en) begin
curr_bank_access[rd_src2_bank_addr] = curr_bank_access[rd_src2_bank_addr]+1;
access_counter = access_counter + 1;
end
if(rd_src3_rd_en) begin
curr_bank_access[rd_src3_bank_addr] = curr_bank_access[rd_src3_bank_addr]+1;
access_counter = access_counter + 1;
end
if(lsu_dest_wr_en[0]) begin
curr_bank_access[wr_lsu_bank_addr] = curr_bank_access[wr_lsu_bank_addr]+1;
access_counter = access_counter + 1;
end
if(lsu_dest_wr_en[1]) begin
curr_bank_access[(wr_lsu_bank_addr+1)%BANK_SIZE]
= curr_bank_access[(wr_lsu_bank_addr+1)%16]+1;
access_counter = access_counter + 1;
end
if(lsu_dest_wr_en[2]) begin
curr_bank_access[(wr_lsu_bank_addr+2)%BANK_SIZE]
= curr_bank_access[(wr_lsu_bank_addr+2)%16]+1;
access_counter = access_counter + 1;
end
if(lsu_dest_wr_en[3]) begin
curr_bank_access[(wr_lsu_bank_addr+3)%BANK_SIZE]
= curr_bank_access[(wr_lsu_bank_addr+3)%16]+1;
access_counter = access_counter + 1;
end
if(wr_alu_wr_en) begin
curr_bank_access[wr_alu_bank_addr]
= curr_bank_access[wr_alu_bank_addr] + 1;
access_counter = access_counter + 1;
end
for (i = 0; i<BANK_SIZE; i= i+1) begin
if(curr_bank_access[i] > 1) begin
contention_access_counter = contention_access_counter+1;
end
end
end
// block that keeps track of live wf
initial begin
access_counter = 0;
contention_access_counter = 0;
// Wait for the first dispach
@( posedge fetch2tracemon_dispatch);
forever begin
@(posedge clk);
if(issue2fetchwave_wf_done_en) begin
$display("Number of accesses: %d\nNumber of access with contention:%d\n",
access_counter,contention_access_counter);
end
end
end
endmodule // vgpr_contention_tracker
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_22ns_30_3_MAC3S_0(clk, ce, a, b, p);
input clk;
input ce;
input[8 - 1 : 0] a; // synthesis attribute keep a "true"
input[22 - 1 : 0] b; // synthesis attribute keep b "true"
output[30 - 1 : 0] p;
reg [8 - 1 : 0] a_reg0;
reg [22 - 1 : 0] b_reg0;
wire [30 - 1 : 0] tmp_product;
reg [30 - 1 : 0] buff0;
assign p = buff0;
assign tmp_product = a_reg0 * b_reg0;
always @ (posedge clk) begin
if (ce) begin
a_reg0 <= a;
b_reg0 <= b;
buff0 <= tmp_product;
end
end
endmodule
`timescale 1 ns / 1 ps
module image_filter_mul_8ns_22ns_30_3(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
image_filter_mul_8ns_22ns_30_3_MAC3S_0 image_filter_mul_8ns_22ns_30_3_MAC3S_0_U(
.clk( clk ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.p( dout ));
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
////////////////////////////////////////////////////////////////////
//
// ALTERA_INT_OSC
//
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
////////////////////////////////////////////////////////////////////
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
`timescale 1 ps / 1 ps
module altera_int_osc
(
clkout,
oscena);
parameter DEVICE_FAMILY = "MAX 10";
parameter DEVICE_ID = "08";
parameter CLOCK_FREQUENCY = "dummy";
output clkout;
input oscena;
wire wire_clkout;
assign clkout = wire_clkout;
// -------------------------------------------------------------------
// Instantiate wysiwyg for chipidblock according to device family
// -------------------------------------------------------------------
generate
if (DEVICE_FAMILY == "MAX 10") begin
fiftyfivenm_oscillator # ( //MAX 10
.device_id(DEVICE_ID),
.clock_frequency(CLOCK_FREQUENCY)
) oscillator_dut (
.clkout(wire_clkout),
.clkout1(),
.oscena(oscena));
end
endgenerate
endmodule //altera_int_osc
//VALID FILE
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Function scope handling
//
// D: Validate scope handling of variables
//
module main ();
reg [3:0] global_reg;
reg [3:0] result;
function [3:0] my_func ;
input [3:0] a;
reg [3:0] global_reg;
begin
global_reg = a + a;
my_func = a + a;
end
endfunction
initial
begin
global_reg = 2;
result = my_func(global_reg);
if(result != 4)
begin
$display("FAILED - function didn't function!\n");
$finish ;
end
if(global_reg != 2)
begin
$display("FAILED - function scope problem!\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:29:11 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/system_ov7670_vga_1_0_stub.v
// Design : system_ov7670_vga_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_1_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
|
module pc_block (
new_pc_init,
wf_id,
wr,
rd_en,
wf_id_rd,
pc_read2ibuff,
clk,
rst
);
parameter BITWIDTH = 32;
input [31:0] new_pc_init;
input [5:0] wf_id;
input wr;
input clk, rst;
input rd_en;
input [5:0] wf_id_rd;
output [32:0]pc_read2ibuff;
wire write;
wire [31:0] pc_read;
wire [32:0] data0, data_flop0;
wire [32:0] data1, data_flop1;
wire [32:0] data2, data_flop2;
wire [32:0] data3, data_flop3;
wire [32:0] data4, data_flop4;
wire [32:0] data5, data_flop5;
wire [32:0] data6, data_flop6;
wire [32:0] data7, data_flop7;
wire [32:0] data8, data_flop8;
wire [32:0] data9, data_flop9;
wire [32:0] data10, data_flop10;
wire [32:0] data11, data_flop11;
wire [32:0] data12, data_flop12;
wire [32:0] data13, data_flop13;
wire [32:0] data14, data_flop14;
wire [32:0] data15, data_flop15;
wire [32:0] data16, data_flop16;
wire [32:0] data17, data_flop17;
wire [32:0] data18, data_flop18;
wire [32:0] data19, data_flop19;
wire [32:0] data20, data_flop20;
wire [32:0] data21, data_flop21;
wire [32:0] data22, data_flop22;
wire [32:0] data23, data_flop23;
wire [32:0] data24, data_flop24;
wire [32:0] data25, data_flop25;
wire [32:0] data26, data_flop26;
wire [32:0] data27, data_flop27;
wire [32:0] data28, data_flop28;
wire [32:0] data29, data_flop29;
wire [32:0] data30, data_flop30;
wire [32:0] data31, data_flop31;
wire [32:0] data32, data_flop32;
wire [32:0] data33, data_flop33;
wire [32:0] data34, data_flop34;
wire [32:0] data35, data_flop35;
wire [32:0] data36, data_flop36;
wire [32:0] data37, data_flop37;
wire [32:0] data38, data_flop38;
wire [32:0] data39, data_flop39;
assign write = 1'b1;
regfile #(33) rfile0 (data0, write, data_flop0, clk, rst);
regfile #(33) rfile1 (data1, write, data_flop1, clk, rst);
regfile #(33) rfile2 (data2, write, data_flop2, clk, rst);
regfile #(33) rfile3 (data3, write, data_flop3, clk, rst);
regfile #(33) rfile4 (data4, write, data_flop4, clk, rst);
regfile #(33) rfile5 (data5, write, data_flop5, clk, rst);
regfile #(33) rfile6 (data6, write, data_flop6, clk, rst);
regfile #(33) rfile7 (data7, write, data_flop7, clk, rst);
regfile #(33) rfile8 (data8, write, data_flop8, clk, rst);
regfile #(33) rfile9 (data9, write, data_flop9, clk, rst);
regfile #(33) rfile10 (data10, write, data_flop10, clk, rst);
regfile #(33) rfile11 (data11, write, data_flop11, clk, rst);
regfile #(33) rfile12 (data12, write, data_flop12, clk, rst);
regfile #(33) rfile13 (data13, write, data_flop13, clk, rst);
regfile #(33) rfile14 (data14, write, data_flop14, clk, rst);
regfile #(33) rfile15 (data15, write, data_flop15, clk, rst);
regfile #(33) rfile16 (data16, write, data_flop16, clk, rst);
regfile #(33) rfile17 (data17, write, data_flop17, clk, rst);
regfile #(33) rfile18 (data18, write, data_flop18, clk, rst);
regfile #(33) rfile19 (data19, write, data_flop19, clk, rst);
regfile #(33) rfile20 (data20, write, data_flop20, clk, rst);
regfile #(33) rfile21 (data21, write, data_flop21, clk, rst);
regfile #(33) rfile22 (data22, write, data_flop22, clk, rst);
regfile #(33) rfile23 (data23, write, data_flop23, clk, rst);
regfile #(33) rfile24 (data24, write, data_flop24, clk, rst);
regfile #(33) rfile25 (data25, write, data_flop25, clk, rst);
regfile #(33) rfile26 (data26, write, data_flop26, clk, rst);
regfile #(33) rfile27 (data27, write, data_flop27, clk, rst);
regfile #(33) rfile28 (data28, write, data_flop28, clk, rst);
regfile #(33) rfile29 (data29, write, data_flop29, clk, rst);
regfile #(33) rfile30 (data30, write, data_flop30, clk, rst);
regfile #(33) rfile31 (data31, write, data_flop31, clk, rst);
regfile #(33) rfile32 (data32, write, data_flop32, clk, rst);
regfile #(33) rfile33 (data33, write, data_flop33, clk, rst);
regfile #(33) rfile34 (data34, write, data_flop34, clk, rst);
regfile #(33) rfile35 (data35, write, data_flop35, clk, rst);
regfile #(33) rfile36 (data36, write, data_flop36, clk, rst);
regfile #(33) rfile37 (data37, write, data_flop37, clk, rst);
regfile #(33) rfile38 (data38, write, data_flop38, clk, rst);
regfile #(33) rfile39 (data39, write, data_flop39, clk, rst);
adder a1(pc_read2ibuff[31:0],pc_read);
assign pc_read2ibuff = (wf_id_rd==6'd0)?data_flop0:
(wf_id_rd==6'd1)?data_flop1:
(wf_id_rd==6'd2)?data_flop2:
(wf_id_rd==6'd3)?data_flop3:
(wf_id_rd==6'd4)?data_flop4:
(wf_id_rd==6'd5)?data_flop5:
(wf_id_rd==6'd6)?data_flop6:
(wf_id_rd==6'd7)?data_flop7:
(wf_id_rd==6'd8)?data_flop8:
(wf_id_rd==6'd9)?data_flop9:
(wf_id_rd==6'd10)?data_flop10:
(wf_id_rd==6'd11)?data_flop11:
(wf_id_rd==6'd12)?data_flop12:
(wf_id_rd==6'd13)?data_flop13:
(wf_id_rd==6'd14)?data_flop14:
(wf_id_rd==6'd15)?data_flop15:
(wf_id_rd==6'd16)?data_flop16:
(wf_id_rd==6'd17)?data_flop17:
(wf_id_rd==6'd18)?data_flop18:
(wf_id_rd==6'd19)?data_flop19:
(wf_id_rd==6'd20)?data_flop20:
(wf_id_rd==6'd21)?data_flop21:
(wf_id_rd==6'd22)?data_flop22:
(wf_id_rd==6'd23)?data_flop23:
(wf_id_rd==6'd24)?data_flop24:
(wf_id_rd==6'd25)?data_flop25:
(wf_id_rd==6'd26)?data_flop26:
(wf_id_rd==6'd27)?data_flop27:
(wf_id_rd==6'd28)?data_flop28:
(wf_id_rd==6'd29)?data_flop29:
(wf_id_rd==6'd30)?data_flop30:
(wf_id_rd==6'd31)?data_flop31:
(wf_id_rd==6'd32)?data_flop32:
(wf_id_rd==6'd33)?data_flop33:
(wf_id_rd==6'd34)?data_flop34:
(wf_id_rd==6'd35)?data_flop35:
(wf_id_rd==6'd36)?data_flop36:
(wf_id_rd==6'd37)?data_flop37:
(wf_id_rd==6'd38)?data_flop38:
(wf_id_rd==6'd39)?data_flop39:
33'd0;
assign data0=(wr & (wf_id==6'd0))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd0))?{1'b0,pc_read}:data_flop0;
assign data1=(wr & (wf_id==6'd1))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd1))?{1'b0,pc_read}:data_flop1;
assign data2=(wr & (wf_id==6'd2))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd2))?{1'b0,pc_read}:data_flop2;
assign data3=(wr & (wf_id==6'd3))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd3))?{1'b0,pc_read}:data_flop3;
assign data4=(wr & (wf_id==6'd4))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd4))?{1'b0,pc_read}:data_flop4;
assign data5=(wr & (wf_id==6'd5))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd5))?{1'b0,pc_read}:data_flop5;
assign data6=(wr & (wf_id==6'd6))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd6))?{1'b0,pc_read}:data_flop6;
assign data7=(wr & (wf_id==6'd7))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd7))?{1'b0,pc_read}:data_flop7;
assign data8=(wr & (wf_id==6'd8))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd8))?{1'b0,pc_read}:data_flop8;
assign data9=(wr & (wf_id==6'd9))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd9))?{1'b0,pc_read}:data_flop9;
assign data10=(wr & (wf_id==6'd10))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd10))?{1'b0,pc_read}:data_flop10;
assign data11=(wr & (wf_id==6'd11))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd11))?{1'b0,pc_read}:data_flop11;
assign data12=(wr & (wf_id==6'd12))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd12))?{1'b0,pc_read}:data_flop12;
assign data13=(wr & (wf_id==6'd13))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd13))?{1'b0,pc_read}:data_flop13;
assign data14=(wr & (wf_id==6'd14))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd14))?{1'b0,pc_read}:data_flop14;
assign data15=(wr & (wf_id==6'd15))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd15))?{1'b0,pc_read}:data_flop15;
assign data16=(wr & (wf_id==6'd16))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd16))?{1'b0,pc_read}:data_flop16;
assign data17=(wr & (wf_id==6'd17))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd17))?{1'b0,pc_read}:data_flop17;
assign data18=(wr & (wf_id==6'd18))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd18))?{1'b0,pc_read}:data_flop18;
assign data19=(wr & (wf_id==6'd19))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd19))?{1'b0,pc_read}:data_flop19;
assign data20=(wr & (wf_id==6'd20))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd20))?{1'b0,pc_read}:data_flop20;
assign data21=(wr & (wf_id==6'd21))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd21))?{1'b0,pc_read}:data_flop21;
assign data22=(wr & (wf_id==6'd22))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd22))?{1'b0,pc_read}:data_flop22;
assign data23=(wr & (wf_id==6'd23))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd23))?{1'b0,pc_read}:data_flop23;
assign data24=(wr & (wf_id==6'd24))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd24))?{1'b0,pc_read}:data_flop24;
assign data25=(wr & (wf_id==6'd25))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd25))?{1'b0,pc_read}:data_flop25;
assign data26=(wr & (wf_id==6'd26))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd26))?{1'b0,pc_read}:data_flop26;
assign data27=(wr & (wf_id==6'd27))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd27))?{1'b0,pc_read}:data_flop27;
assign data28=(wr & (wf_id==6'd28))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd28))?{1'b0,pc_read}:data_flop28;
assign data29=(wr & (wf_id==6'd29))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd29))?{1'b0,pc_read}:data_flop29;
assign data30=(wr & (wf_id==6'd30))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd30))?{1'b0,pc_read}:data_flop30;
assign data31=(wr & (wf_id==6'd31))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd31))?{1'b0,pc_read}:data_flop31;
assign data32=(wr & (wf_id==6'd32))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd32))?{1'b0,pc_read}:data_flop32;
assign data33=(wr & (wf_id==6'd33))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd33))?{1'b0,pc_read}:data_flop33;
assign data34=(wr & (wf_id==6'd34))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd34))?{1'b0,pc_read}:data_flop34;
assign data35=(wr & (wf_id==6'd35))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd35))?{1'b0,pc_read}:data_flop35;
assign data36=(wr & (wf_id==6'd36))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd36))?{1'b0,pc_read}:data_flop36;
assign data37=(wr & (wf_id==6'd37))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd37))?{1'b0,pc_read}:data_flop37;
assign data38=(wr & (wf_id==6'd38))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd38))?{1'b0,pc_read}:data_flop38;
assign data39=(wr & (wf_id==6'd39))? {1'b1,new_pc_init} :(rd_en & (wf_id_rd==6'd39))?{1'b0,pc_read}:data_flop39;
endmodule
|
/////////////////////////////////////////////////////////////////
// MODULE Erosion_system
/////////////////////////////////////////////////////////////////
module Erosion_system
(
input logic clock,
input logic clock2x,
input logic resetn,
// AVS avs_erosion_cra
input logic avs_erosion_cra_read,
input logic avs_erosion_cra_write,
input logic [3:0] avs_erosion_cra_address,
input logic [63:0] avs_erosion_cra_writedata,
input logic [7:0] avs_erosion_cra_byteenable,
output logic avs_erosion_cra_waitrequest,
output logic [63:0] avs_erosion_cra_readdata,
output logic avs_erosion_cra_readdatavalid,
output logic kernel_irq,
// AVM avm_memgmem0_port_0_0_rw
output logic avm_memgmem0_port_0_0_rw_read,
output logic avm_memgmem0_port_0_0_rw_write,
output logic [4:0] avm_memgmem0_port_0_0_rw_burstcount,
output logic [29:0] avm_memgmem0_port_0_0_rw_address,
output logic [255:0] avm_memgmem0_port_0_0_rw_writedata,
output logic [31:0] avm_memgmem0_port_0_0_rw_byteenable,
input logic avm_memgmem0_port_0_0_rw_waitrequest,
input logic [255:0] avm_memgmem0_port_0_0_rw_readdata,
input logic avm_memgmem0_port_0_0_rw_readdatavalid,
input logic avm_memgmem0_port_0_0_rw_writeack
);
genvar i;
logic kernel_irqs;
logic gmem0_global_avm_read [2];
logic gmem0_global_avm_write [2];
logic [4:0] gmem0_global_avm_burstcount [2];
logic [29:0] gmem0_global_avm_address [2];
logic [255:0] gmem0_global_avm_writedata [2];
logic [31:0] gmem0_global_avm_byteenable [2];
logic gmem0_global_avm_waitrequest [2];
logic [255:0] gmem0_global_avm_readdata [2];
logic gmem0_global_avm_readdatavalid [2];
logic gmem0_global_avm_writeack [2];
// INST erosion of erosion_top_wrapper
erosion_top_wrapper erosion
(
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.cra_irq(kernel_irqs),
// AVS avs_cra
.avs_cra_read(avs_erosion_cra_read),
.avs_cra_write(avs_erosion_cra_write),
.avs_cra_address(avs_erosion_cra_address),
.avs_cra_writedata(avs_erosion_cra_writedata),
.avs_cra_byteenable(avs_erosion_cra_byteenable),
.avs_cra_waitrequest(avs_erosion_cra_waitrequest),
.avs_cra_readdata(avs_erosion_cra_readdata),
.avs_cra_readdatavalid(avs_erosion_cra_readdatavalid),
// AVM avm_local_bb1_ld__inst0
.avm_local_bb1_ld__inst0_read(gmem0_global_avm_read[0]),
.avm_local_bb1_ld__inst0_write(gmem0_global_avm_write[0]),
.avm_local_bb1_ld__inst0_burstcount(gmem0_global_avm_burstcount[0]),
.avm_local_bb1_ld__inst0_address(gmem0_global_avm_address[0]),
.avm_local_bb1_ld__inst0_writedata(gmem0_global_avm_writedata[0]),
.avm_local_bb1_ld__inst0_byteenable(gmem0_global_avm_byteenable[0]),
.avm_local_bb1_ld__inst0_waitrequest(gmem0_global_avm_waitrequest[0]),
.avm_local_bb1_ld__inst0_readdata(gmem0_global_avm_readdata[0]),
.avm_local_bb1_ld__inst0_readdatavalid(gmem0_global_avm_readdatavalid[0]),
.avm_local_bb1_ld__inst0_writeack(gmem0_global_avm_writeack[0]),
// AVM avm_local_bb1_st_c0_exe1_inst0
.avm_local_bb1_st_c0_exe1_inst0_read(gmem0_global_avm_read[1]),
.avm_local_bb1_st_c0_exe1_inst0_write(gmem0_global_avm_write[1]),
.avm_local_bb1_st_c0_exe1_inst0_burstcount(gmem0_global_avm_burstcount[1]),
.avm_local_bb1_st_c0_exe1_inst0_address(gmem0_global_avm_address[1]),
.avm_local_bb1_st_c0_exe1_inst0_writedata(gmem0_global_avm_writedata[1]),
.avm_local_bb1_st_c0_exe1_inst0_byteenable(gmem0_global_avm_byteenable[1]),
.avm_local_bb1_st_c0_exe1_inst0_waitrequest(gmem0_global_avm_waitrequest[1]),
.avm_local_bb1_st_c0_exe1_inst0_readdata(gmem0_global_avm_readdata[1]),
.avm_local_bb1_st_c0_exe1_inst0_readdatavalid(gmem0_global_avm_readdatavalid[1]),
.avm_local_bb1_st_c0_exe1_inst0_writeack(gmem0_global_avm_writeack[1])
);
assign kernel_irq = |kernel_irqs;
generate
begin:gmem0_
logic gmem0_icm_in_arb_request [2];
logic gmem0_icm_in_arb_read [2];
logic gmem0_icm_in_arb_write [2];
logic [4:0] gmem0_icm_in_arb_burstcount [2];
logic [24:0] gmem0_icm_in_arb_address [2];
logic [255:0] gmem0_icm_in_arb_writedata [2];
logic [31:0] gmem0_icm_in_arb_byteenable [2];
logic gmem0_icm_in_arb_stall [2];
logic gmem0_icm_in_wrp_ack [2];
logic gmem0_icm_in_rrp_datavalid [2];
logic [255:0] gmem0_icm_in_rrp_data [2];
logic gmem0_icm_preroute_arb_request [2];
logic gmem0_icm_preroute_arb_read [2];
logic gmem0_icm_preroute_arb_write [2];
logic [4:0] gmem0_icm_preroute_arb_burstcount [2];
logic [24:0] gmem0_icm_preroute_arb_address [2];
logic [255:0] gmem0_icm_preroute_arb_writedata [2];
logic [31:0] gmem0_icm_preroute_arb_byteenable [2];
logic gmem0_icm_preroute_arb_stall [2];
logic gmem0_icm_preroute_wrp_ack [2];
logic gmem0_icm_preroute_rrp_datavalid [2];
logic [255:0] gmem0_icm_preroute_rrp_data [2];
logic icm_groupgmem0_router_0_arb_request [1];
logic icm_groupgmem0_router_0_arb_read [1];
logic icm_groupgmem0_router_0_arb_write [1];
logic [4:0] icm_groupgmem0_router_0_arb_burstcount [1];
logic [24:0] icm_groupgmem0_router_0_arb_address [1];
logic [255:0] icm_groupgmem0_router_0_arb_writedata [1];
logic [31:0] icm_groupgmem0_router_0_arb_byteenable [1];
logic icm_groupgmem0_router_0_arb_stall [1];
logic icm_groupgmem0_router_0_wrp_ack [1];
logic icm_groupgmem0_router_0_rrp_datavalid [1];
logic [255:0] icm_groupgmem0_router_0_rrp_data [1];
logic icm_groupgmem0_router_1_arb_request [1];
logic icm_groupgmem0_router_1_arb_read [1];
logic icm_groupgmem0_router_1_arb_write [1];
logic [4:0] icm_groupgmem0_router_1_arb_burstcount [1];
logic [24:0] icm_groupgmem0_router_1_arb_address [1];
logic [255:0] icm_groupgmem0_router_1_arb_writedata [1];
logic [31:0] icm_groupgmem0_router_1_arb_byteenable [1];
logic icm_groupgmem0_router_1_arb_stall [1];
logic icm_groupgmem0_router_1_wrp_ack [1];
logic icm_groupgmem0_router_1_rrp_datavalid [1];
logic [255:0] icm_groupgmem0_router_1_rrp_data [1];
logic icm_out_0_rw_arb_request [1];
logic icm_out_0_rw_arb_read [1];
logic icm_out_0_rw_arb_write [1];
logic [4:0] icm_out_0_rw_arb_burstcount [1];
logic [24:0] icm_out_0_rw_arb_address [1];
logic [255:0] icm_out_0_rw_arb_writedata [1];
logic [31:0] icm_out_0_rw_arb_byteenable [1];
logic icm_out_0_rw_arb_id [1];
logic icm_out_0_rw_arb_stall [1];
logic icm_out_0_rw_wrp_ack [1];
logic icm_out_0_rw_rrp_datavalid [1];
logic [255:0] icm_out_0_rw_rrp_data [1];
logic icm_routedgmem0_port_0_0_rw_arb_request [2];
logic icm_routedgmem0_port_0_0_rw_arb_read [2];
logic icm_routedgmem0_port_0_0_rw_arb_write [2];
logic [4:0] icm_routedgmem0_port_0_0_rw_arb_burstcount [2];
logic [24:0] icm_routedgmem0_port_0_0_rw_arb_address [2];
logic [255:0] icm_routedgmem0_port_0_0_rw_arb_writedata [2];
logic [31:0] icm_routedgmem0_port_0_0_rw_arb_byteenable [2];
logic icm_routedgmem0_port_0_0_rw_arb_stall [2];
logic icm_routedgmem0_port_0_0_rw_wrp_ack [2];
logic icm_routedgmem0_port_0_0_rw_rrp_datavalid [2];
logic [255:0] icm_routedgmem0_port_0_0_rw_rrp_data [2];
for( i = 0; i < 2; i = i + 1 )
begin:t
// INST gmem0_avm_to_ic of acl_avm_to_ic
acl_avm_to_ic
#(
.DATA_W(256),
.WRITEDATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(30),
.BYTEENA_W(32)
)
gmem0_avm_to_ic
(
// AVM avm
.avm_read(gmem0_global_avm_read[i]),
.avm_write(gmem0_global_avm_write[i]),
.avm_burstcount(gmem0_global_avm_burstcount[i]),
.avm_address(gmem0_global_avm_address[i]),
.avm_writedata(gmem0_global_avm_writedata[i]),
.avm_byteenable(gmem0_global_avm_byteenable[i]),
.avm_waitrequest(gmem0_global_avm_waitrequest[i]),
.avm_readdata(gmem0_global_avm_readdata[i]),
.avm_readdatavalid(gmem0_global_avm_readdatavalid[i]),
.avm_writeack(gmem0_global_avm_writeack[i]),
// ICM ic
.ic_arb_request(gmem0_icm_in_arb_request[i]),
.ic_arb_read(gmem0_icm_in_arb_read[i]),
.ic_arb_write(gmem0_icm_in_arb_write[i]),
.ic_arb_burstcount(gmem0_icm_in_arb_burstcount[i]),
.ic_arb_address(gmem0_icm_in_arb_address[i]),
.ic_arb_writedata(gmem0_icm_in_arb_writedata[i]),
.ic_arb_byteenable(gmem0_icm_in_arb_byteenable[i]),
.ic_arb_stall(gmem0_icm_in_arb_stall[i]),
.ic_wrp_ack(gmem0_icm_in_wrp_ack[i]),
.ic_rrp_datavalid(gmem0_icm_in_rrp_datavalid[i]),
.ic_rrp_data(gmem0_icm_in_rrp_data[i])
);
end
assign icm_groupgmem0_router_0_arb_request[0] = gmem0_icm_in_arb_request[1];
assign icm_groupgmem0_router_0_arb_read[0] = gmem0_icm_in_arb_read[1];
assign icm_groupgmem0_router_0_arb_write[0] = gmem0_icm_in_arb_write[1];
assign icm_groupgmem0_router_0_arb_burstcount[0] = gmem0_icm_in_arb_burstcount[1];
assign icm_groupgmem0_router_0_arb_address[0] = gmem0_icm_in_arb_address[1];
assign icm_groupgmem0_router_0_arb_writedata[0] = gmem0_icm_in_arb_writedata[1];
assign icm_groupgmem0_router_0_arb_byteenable[0] = gmem0_icm_in_arb_byteenable[1];
assign gmem0_icm_in_arb_stall[1] = icm_groupgmem0_router_0_arb_stall[0];
assign gmem0_icm_in_wrp_ack[1] = icm_groupgmem0_router_0_wrp_ack[0];
assign gmem0_icm_in_rrp_datavalid[1] = icm_groupgmem0_router_0_rrp_datavalid[0];
assign gmem0_icm_in_rrp_data[1] = icm_groupgmem0_router_0_rrp_data[0];
// INST global_ic_preroutegmem0_router_0 of interconnect_0
interconnect_0 global_ic_preroutegmem0_router_0
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_groupgmem0_router_0_arb_request),
.m_arb_read(icm_groupgmem0_router_0_arb_read),
.m_arb_write(icm_groupgmem0_router_0_arb_write),
.m_arb_burstcount(icm_groupgmem0_router_0_arb_burstcount),
.m_arb_address(icm_groupgmem0_router_0_arb_address),
.m_arb_writedata(icm_groupgmem0_router_0_arb_writedata),
.m_arb_byteenable(icm_groupgmem0_router_0_arb_byteenable),
.m_arb_stall(icm_groupgmem0_router_0_arb_stall),
.m_wrp_ack(icm_groupgmem0_router_0_wrp_ack),
.m_rrp_datavalid(icm_groupgmem0_router_0_rrp_datavalid),
.m_rrp_data(icm_groupgmem0_router_0_rrp_data),
// ICM mout
.mout_arb_request(gmem0_icm_preroute_arb_request[0]),
.mout_arb_read(gmem0_icm_preroute_arb_read[0]),
.mout_arb_write(gmem0_icm_preroute_arb_write[0]),
.mout_arb_burstcount(gmem0_icm_preroute_arb_burstcount[0]),
.mout_arb_address(gmem0_icm_preroute_arb_address[0]),
.mout_arb_writedata(gmem0_icm_preroute_arb_writedata[0]),
.mout_arb_byteenable(gmem0_icm_preroute_arb_byteenable[0]),
.mout_arb_id(),
.mout_arb_stall(gmem0_icm_preroute_arb_stall[0]),
.mout_wrp_ack(gmem0_icm_preroute_wrp_ack[0]),
.mout_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[0]),
.mout_rrp_data(gmem0_icm_preroute_rrp_data[0])
);
assign icm_groupgmem0_router_1_arb_request[0] = gmem0_icm_in_arb_request[0];
assign icm_groupgmem0_router_1_arb_read[0] = gmem0_icm_in_arb_read[0];
assign icm_groupgmem0_router_1_arb_write[0] = gmem0_icm_in_arb_write[0];
assign icm_groupgmem0_router_1_arb_burstcount[0] = gmem0_icm_in_arb_burstcount[0];
assign icm_groupgmem0_router_1_arb_address[0] = gmem0_icm_in_arb_address[0];
assign icm_groupgmem0_router_1_arb_writedata[0] = gmem0_icm_in_arb_writedata[0];
assign icm_groupgmem0_router_1_arb_byteenable[0] = gmem0_icm_in_arb_byteenable[0];
assign gmem0_icm_in_arb_stall[0] = icm_groupgmem0_router_1_arb_stall[0];
assign gmem0_icm_in_wrp_ack[0] = icm_groupgmem0_router_1_wrp_ack[0];
assign gmem0_icm_in_rrp_datavalid[0] = icm_groupgmem0_router_1_rrp_datavalid[0];
assign gmem0_icm_in_rrp_data[0] = icm_groupgmem0_router_1_rrp_data[0];
// INST global_ic_preroutegmem0_router_1 of interconnect_1
interconnect_1 global_ic_preroutegmem0_router_1
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_groupgmem0_router_1_arb_request),
.m_arb_read(icm_groupgmem0_router_1_arb_read),
.m_arb_write(icm_groupgmem0_router_1_arb_write),
.m_arb_burstcount(icm_groupgmem0_router_1_arb_burstcount),
.m_arb_address(icm_groupgmem0_router_1_arb_address),
.m_arb_writedata(icm_groupgmem0_router_1_arb_writedata),
.m_arb_byteenable(icm_groupgmem0_router_1_arb_byteenable),
.m_arb_stall(icm_groupgmem0_router_1_arb_stall),
.m_wrp_ack(icm_groupgmem0_router_1_wrp_ack),
.m_rrp_datavalid(icm_groupgmem0_router_1_rrp_datavalid),
.m_rrp_data(icm_groupgmem0_router_1_rrp_data),
// ICM mout
.mout_arb_request(gmem0_icm_preroute_arb_request[1]),
.mout_arb_read(gmem0_icm_preroute_arb_read[1]),
.mout_arb_write(gmem0_icm_preroute_arb_write[1]),
.mout_arb_burstcount(gmem0_icm_preroute_arb_burstcount[1]),
.mout_arb_address(gmem0_icm_preroute_arb_address[1]),
.mout_arb_writedata(gmem0_icm_preroute_arb_writedata[1]),
.mout_arb_byteenable(gmem0_icm_preroute_arb_byteenable[1]),
.mout_arb_id(),
.mout_arb_stall(gmem0_icm_preroute_arb_stall[1]),
.mout_wrp_ack(gmem0_icm_preroute_wrp_ack[1]),
.mout_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[1]),
.mout_rrp_data(gmem0_icm_preroute_rrp_data[1])
);
for( i = 0; i < 2; i = i + 1 )
begin:router
logic b_arb_request [1];
logic b_arb_read [1];
logic b_arb_write [1];
logic [4:0] b_arb_burstcount [1];
logic [24:0] b_arb_address [1];
logic [255:0] b_arb_writedata [1];
logic [31:0] b_arb_byteenable [1];
logic b_arb_stall [1];
logic b_wrp_ack [1];
logic b_rrp_datavalid [1];
logic [255:0] b_rrp_data [1];
logic bank_select;
// INST router of acl_ic_mem_router
acl_ic_mem_router
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.NUM_BANKS(1)
)
router
(
.clock(clock),
.resetn(resetn),
.bank_select(bank_select),
// ICM m
.m_arb_request(gmem0_icm_preroute_arb_request[i]),
.m_arb_read(gmem0_icm_preroute_arb_read[i]),
.m_arb_write(gmem0_icm_preroute_arb_write[i]),
.m_arb_burstcount(gmem0_icm_preroute_arb_burstcount[i]),
.m_arb_address(gmem0_icm_preroute_arb_address[i]),
.m_arb_writedata(gmem0_icm_preroute_arb_writedata[i]),
.m_arb_byteenable(gmem0_icm_preroute_arb_byteenable[i]),
.m_arb_stall(gmem0_icm_preroute_arb_stall[i]),
.m_wrp_ack(gmem0_icm_preroute_wrp_ack[i]),
.m_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[i]),
.m_rrp_data(gmem0_icm_preroute_rrp_data[i]),
// ICM b
.b_arb_request(b_arb_request),
.b_arb_read(b_arb_read),
.b_arb_write(b_arb_write),
.b_arb_burstcount(b_arb_burstcount),
.b_arb_address(b_arb_address),
.b_arb_writedata(b_arb_writedata),
.b_arb_byteenable(b_arb_byteenable),
.b_arb_stall(b_arb_stall),
.b_wrp_ack(b_wrp_ack),
.b_rrp_datavalid(b_rrp_datavalid),
.b_rrp_data(b_rrp_data)
);
assign bank_select = 1'b1;
end
// INST global_icgmem0_port_0_0_rw of interconnect_2
interconnect_2 global_icgmem0_port_0_0_rw
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_routedgmem0_port_0_0_rw_arb_request),
.m_arb_read(icm_routedgmem0_port_0_0_rw_arb_read),
.m_arb_write(icm_routedgmem0_port_0_0_rw_arb_write),
.m_arb_burstcount(icm_routedgmem0_port_0_0_rw_arb_burstcount),
.m_arb_address(icm_routedgmem0_port_0_0_rw_arb_address),
.m_arb_writedata(icm_routedgmem0_port_0_0_rw_arb_writedata),
.m_arb_byteenable(icm_routedgmem0_port_0_0_rw_arb_byteenable),
.m_arb_stall(icm_routedgmem0_port_0_0_rw_arb_stall),
.m_wrp_ack(icm_routedgmem0_port_0_0_rw_wrp_ack),
.m_rrp_datavalid(icm_routedgmem0_port_0_0_rw_rrp_datavalid),
.m_rrp_data(icm_routedgmem0_port_0_0_rw_rrp_data),
// ICM mout
.mout_arb_request(icm_out_0_rw_arb_request[0]),
.mout_arb_read(icm_out_0_rw_arb_read[0]),
.mout_arb_write(icm_out_0_rw_arb_write[0]),
.mout_arb_burstcount(icm_out_0_rw_arb_burstcount[0]),
.mout_arb_address(icm_out_0_rw_arb_address[0]),
.mout_arb_writedata(icm_out_0_rw_arb_writedata[0]),
.mout_arb_byteenable(icm_out_0_rw_arb_byteenable[0]),
.mout_arb_id(icm_out_0_rw_arb_id[0]),
.mout_arb_stall(icm_out_0_rw_arb_stall[0]),
.mout_wrp_ack(icm_out_0_rw_wrp_ack[0]),
.mout_rrp_datavalid(icm_out_0_rw_rrp_datavalid[0]),
.mout_rrp_data(icm_out_0_rw_rrp_data[0])
);
for( i = 0; i < 2; i = i + 1 )
begin:mgmem0_port_0_0_rw
assign icm_routedgmem0_port_0_0_rw_arb_request[i] = router[i].b_arb_request[0];
assign icm_routedgmem0_port_0_0_rw_arb_read[i] = router[i].b_arb_read[0];
assign icm_routedgmem0_port_0_0_rw_arb_write[i] = router[i].b_arb_write[0];
assign icm_routedgmem0_port_0_0_rw_arb_burstcount[i] = router[i].b_arb_burstcount[0];
assign icm_routedgmem0_port_0_0_rw_arb_address[i] = router[i].b_arb_address[0];
assign icm_routedgmem0_port_0_0_rw_arb_writedata[i] = router[i].b_arb_writedata[0];
assign icm_routedgmem0_port_0_0_rw_arb_byteenable[i] = router[i].b_arb_byteenable[0];
assign router[i].b_arb_stall[0] = icm_routedgmem0_port_0_0_rw_arb_stall[i];
assign router[i].b_wrp_ack[0] = icm_routedgmem0_port_0_0_rw_wrp_ack[i];
assign router[i].b_rrp_datavalid[0] = icm_routedgmem0_port_0_0_rw_rrp_datavalid[i];
assign router[i].b_rrp_data[0] = icm_routedgmem0_port_0_0_rw_rrp_data[i];
end
// INST global_out_ic_to_avmgmem0_port_0_0_rw of acl_ic_to_avm
acl_ic_to_avm
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(30),
.BYTEENA_W(32),
.ID_W(1)
)
global_out_ic_to_avmgmem0_port_0_0_rw
(
// ICM ic
.ic_arb_request(icm_out_0_rw_arb_request[0]),
.ic_arb_read(icm_out_0_rw_arb_read[0]),
.ic_arb_write(icm_out_0_rw_arb_write[0]),
.ic_arb_burstcount(icm_out_0_rw_arb_burstcount[0]),
.ic_arb_address(icm_out_0_rw_arb_address[0]),
.ic_arb_writedata(icm_out_0_rw_arb_writedata[0]),
.ic_arb_byteenable(icm_out_0_rw_arb_byteenable[0]),
.ic_arb_id(icm_out_0_rw_arb_id[0]),
.ic_arb_stall(icm_out_0_rw_arb_stall[0]),
.ic_wrp_ack(icm_out_0_rw_wrp_ack[0]),
.ic_rrp_datavalid(icm_out_0_rw_rrp_datavalid[0]),
.ic_rrp_data(icm_out_0_rw_rrp_data[0]),
// AVM avm
.avm_read(avm_memgmem0_port_0_0_rw_read),
.avm_write(avm_memgmem0_port_0_0_rw_write),
.avm_burstcount(avm_memgmem0_port_0_0_rw_burstcount),
.avm_address(avm_memgmem0_port_0_0_rw_address),
.avm_writedata(avm_memgmem0_port_0_0_rw_writedata),
.avm_byteenable(avm_memgmem0_port_0_0_rw_byteenable),
.avm_waitrequest(avm_memgmem0_port_0_0_rw_waitrequest),
.avm_readdata(avm_memgmem0_port_0_0_rw_readdata),
.avm_readdatavalid(avm_memgmem0_port_0_0_rw_readdatavalid),
.avm_writeack(avm_memgmem0_port_0_0_rw_writeack)
);
end
endgenerate
endmodule
/////////////////////////////////////////////////////////////////
// MODULE erosion_top_wrapper
/////////////////////////////////////////////////////////////////
module erosion_top_wrapper
(
input logic clock,
input logic clock2x,
input logic resetn,
output logic cra_irq,
// AVS avs_cra
input logic avs_cra_read,
input logic avs_cra_write,
input logic [3:0] avs_cra_address,
input logic [63:0] avs_cra_writedata,
input logic [7:0] avs_cra_byteenable,
output logic avs_cra_waitrequest,
output logic [63:0] avs_cra_readdata,
output logic avs_cra_readdatavalid,
// AVM avm_local_bb1_ld__inst0
output logic avm_local_bb1_ld__inst0_read,
output logic avm_local_bb1_ld__inst0_write,
output logic [4:0] avm_local_bb1_ld__inst0_burstcount,
output logic [29:0] avm_local_bb1_ld__inst0_address,
output logic [255:0] avm_local_bb1_ld__inst0_writedata,
output logic [31:0] avm_local_bb1_ld__inst0_byteenable,
input logic avm_local_bb1_ld__inst0_waitrequest,
input logic [255:0] avm_local_bb1_ld__inst0_readdata,
input logic avm_local_bb1_ld__inst0_readdatavalid,
input logic avm_local_bb1_ld__inst0_writeack,
// AVM avm_local_bb1_st_c0_exe1_inst0
output logic avm_local_bb1_st_c0_exe1_inst0_read,
output logic avm_local_bb1_st_c0_exe1_inst0_write,
output logic [4:0] avm_local_bb1_st_c0_exe1_inst0_burstcount,
output logic [29:0] avm_local_bb1_st_c0_exe1_inst0_address,
output logic [255:0] avm_local_bb1_st_c0_exe1_inst0_writedata,
output logic [31:0] avm_local_bb1_st_c0_exe1_inst0_byteenable,
input logic avm_local_bb1_st_c0_exe1_inst0_waitrequest,
input logic [255:0] avm_local_bb1_st_c0_exe1_inst0_readdata,
input logic avm_local_bb1_st_c0_exe1_inst0_readdatavalid,
input logic avm_local_bb1_st_c0_exe1_inst0_writeack
);
logic lmem_invalid_single_bit;
// INST kernel of erosion_function_wrapper
erosion_function_wrapper kernel
(
.local_router_hang(lmem_invalid_single_bit),
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.cra_irq(cra_irq),
// AVS avs_cra
.avs_cra_read(avs_cra_read),
.avs_cra_write(avs_cra_write),
.avs_cra_address(avs_cra_address),
.avs_cra_writedata(avs_cra_writedata),
.avs_cra_byteenable(avs_cra_byteenable),
.avs_cra_waitrequest(avs_cra_waitrequest),
.avs_cra_readdata(avs_cra_readdata),
.avs_cra_readdatavalid(avs_cra_readdatavalid),
// AVM avm_local_bb1_ld__inst0
.avm_local_bb1_ld__inst0_read(avm_local_bb1_ld__inst0_read),
.avm_local_bb1_ld__inst0_write(avm_local_bb1_ld__inst0_write),
.avm_local_bb1_ld__inst0_burstcount(avm_local_bb1_ld__inst0_burstcount),
.avm_local_bb1_ld__inst0_address(avm_local_bb1_ld__inst0_address),
.avm_local_bb1_ld__inst0_writedata(avm_local_bb1_ld__inst0_writedata),
.avm_local_bb1_ld__inst0_byteenable(avm_local_bb1_ld__inst0_byteenable),
.avm_local_bb1_ld__inst0_waitrequest(avm_local_bb1_ld__inst0_waitrequest),
.avm_local_bb1_ld__inst0_readdata(avm_local_bb1_ld__inst0_readdata),
.avm_local_bb1_ld__inst0_readdatavalid(avm_local_bb1_ld__inst0_readdatavalid),
.avm_local_bb1_ld__inst0_writeack(avm_local_bb1_ld__inst0_writeack),
// AVM avm_local_bb1_st_c0_exe1_inst0
.avm_local_bb1_st_c0_exe1_inst0_read(avm_local_bb1_st_c0_exe1_inst0_read),
.avm_local_bb1_st_c0_exe1_inst0_write(avm_local_bb1_st_c0_exe1_inst0_write),
.avm_local_bb1_st_c0_exe1_inst0_burstcount(avm_local_bb1_st_c0_exe1_inst0_burstcount),
.avm_local_bb1_st_c0_exe1_inst0_address(avm_local_bb1_st_c0_exe1_inst0_address),
.avm_local_bb1_st_c0_exe1_inst0_writedata(avm_local_bb1_st_c0_exe1_inst0_writedata),
.avm_local_bb1_st_c0_exe1_inst0_byteenable(avm_local_bb1_st_c0_exe1_inst0_byteenable),
.avm_local_bb1_st_c0_exe1_inst0_waitrequest(avm_local_bb1_st_c0_exe1_inst0_waitrequest),
.avm_local_bb1_st_c0_exe1_inst0_readdata(avm_local_bb1_st_c0_exe1_inst0_readdata),
.avm_local_bb1_st_c0_exe1_inst0_readdatavalid(avm_local_bb1_st_c0_exe1_inst0_readdatavalid),
.avm_local_bb1_st_c0_exe1_inst0_writeack(avm_local_bb1_st_c0_exe1_inst0_writeack)
);
assign lmem_invalid_single_bit = 'b0;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_0
/////////////////////////////////////////////////////////////////
module interconnect_0
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [1],
input logic m_arb_read [1],
input logic m_arb_write [1],
input logic [4:0] m_arb_burstcount [1],
input logic [24:0] m_arb_address [1],
input logic [255:0] m_arb_writedata [1],
input logic [31:0] m_arb_byteenable [1],
output logic m_arb_stall [1],
output logic m_wrp_ack [1],
output logic m_rrp_datavalid [1],
output logic [255:0] m_rrp_data [1],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 1; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(1),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(1),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(64),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
assign m[0].wrp_intf.ack = s.wrp_intf.ack;
assign m[0].wrp_intf.id = s.wrp_intf.id;
end
endgenerate
generate
begin:rrp
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = s.in_arb_intf.stall;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_1
/////////////////////////////////////////////////////////////////
module interconnect_1
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [1],
input logic m_arb_read [1],
input logic m_arb_write [1],
input logic [4:0] m_arb_burstcount [1],
input logic [24:0] m_arb_address [1],
input logic [255:0] m_arb_writedata [1],
input logic [31:0] m_arb_byteenable [1],
output logic m_arb_stall [1],
output logic m_wrp_ack [1],
output logic m_rrp_datavalid [1],
output logic [255:0] m_rrp_data [1],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 1; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(1),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(1),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(64),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
end
endgenerate
generate
begin:rrp
assign m[0].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[0].rrp_intf.data = s.rrp_intf.data;
assign m[0].rrp_intf.id = s.rrp_intf.id;
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = s.in_arb_intf.stall;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_2
/////////////////////////////////////////////////////////////////
module interconnect_2
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [2],
input logic m_arb_read [2],
input logic m_arb_write [2],
input logic [4:0] m_arb_burstcount [2],
input logic [24:0] m_arb_address [2],
input logic [255:0] m_arb_writedata [2],
input logic [31:0] m_arb_byteenable [2],
output logic m_arb_stall [2],
output logic m_wrp_ack [2],
output logic m_rrp_datavalid [2],
output logic [255:0] m_rrp_data [2],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 2; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(2),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(2),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(0),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
assign m[0].wrp_intf.ack = s.wrp_intf.ack;
assign m[0].wrp_intf.id = s.wrp_intf.id;
assign m[1].wrp_intf.ack = s.wrp_intf.ack;
assign m[1].wrp_intf.id = s.wrp_intf.id;
end
endgenerate
generate
begin:rrp
assign m[0].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[0].rrp_intf.data = s.rrp_intf.data;
assign m[0].rrp_intf.id = s.rrp_intf.id;
assign m[1].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[1].rrp_intf.data = s.rrp_intf.data;
assign m[1].rrp_intf.id = s.rrp_intf.id;
end
endgenerate
generate
for( i = 0; i < 1; i = i + 1 )
begin:a
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m0_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m1_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) mout_intf();
// INST a of acl_arb2
acl_arb2
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.PIPELINE("none"),
.KEEP_LAST_GRANT(1),
.NO_STALL_NETWORK(0)
)
a
(
.clock(clock),
.resetn(resetn),
.m0_intf(m0_intf),
.m1_intf(m1_intf),
.mout_intf(mout_intf)
);
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = a[0].mout_intf.req;
assign a[0].mout_intf.stall = s.in_arb_intf.stall;
assign a[0].m0_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = a[0].m0_intf.stall;
assign a[0].m1_intf.req = m[1].arb_intf.req;
assign m[1].arb_intf.stall = a[0].m1_intf.stall;
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export NthDerivative.
Opaque Min Max.
Section Intervals.
(** printing realline %\ensuremath{\RR}% #(-∞,+∞)# *)
(** printing openl %\ensuremath{(\cdot,+\infty)}% #(⋅,+∞)# *)
(** printing openr %\ensuremath{(-\infty,\cdot)}% #(-∞,⋅)# *)
(** printing closel %\ensuremath{[\cdot,+\infty)}% #[⋅,+∞)# *)
(** printing closer %\ensuremath{(-\infty,\cdot]}% #(-∞,⋅]# *)
(** printing olor %\ensuremath{(\cdot,\cdot)}% #(⋅,⋅)# *)
(** printing clor %\ensuremath{[\cdot,\cdot)}% #[⋅,⋅)# *)
(** printing olcr %\ensuremath{(\cdot,\cdot]}% #(⋅,⋅]# *)
(** printing clcr %\ensuremath{[\cdot,\cdot]}% #[⋅,⋅]# *)
(**
* Generalized Intervals
At this stage we have enough material to begin generalizing our
concepts in preparation for the fundamental theorem of calculus and
the definition of the main (non-polynomial) functions of analysis.
In order to define functions via power series (or any other kind of
series) we need to formalize a notion of convergence more general than
the one we already have on compact intervals. This is necessary for
practical reasons: we want to define a single exponential function
with domain [IR], not several exponential functions defined on compact
intervals which we prove to be the same wherever their domains
overlap. In a similar way, we want to define indefinite integrals on
infinite domains and not only on compact intervals.
Unfortunately, proceeding in a way analogous to how we defined the
concept of global continuity will lead us nowhere; the concept turns
out to be to general, and the behaviour on too small domains
(typically intervals [[a,a']] where [a [=] a'] is neither
provably true nor provably false) will be unsatisfactory.
There is a special family of sets, however, where this problems can be
avoided: intervals. Intervals have some nice properties that allow us
to prove good results, namely the facts that if [a] and [b] are
elements of an interval [I] then so are [Min(a,b)] and
[Max(a,b)] (which is in general not true) and also the
compact interval [[a,b]] is included in [I]. Furthermore, all
intervals are characterized by simple, well defined predicates, and
the nonempty and proper concepts become very easy to define.
** Definitions and Basic Results
We define an inductive type of intervals with nine constructors,
corresponding to the nine basic types of intervals. The reason why so
many constructors are needed is that we do not have a notion of real
line, for many reasons which we will not discuss here. Also it seems
simple to directly define finite intervals than to define then later
as intersections of infinite intervals, as it would only mess things
up.
The compact interval which we will define here is obviously the same
that we have been working with all the way through; why, then, the
different formulation? The reason is simple: if we had worked with
intervals from the beginning we would have had case definitions at
every spot, and our lemmas and proofs would have been very awkward.
Also, it seems more natural to characterize a compact interval by two
real numbers (and a proof) than as a particular case of a more general
concept which doesn't have an intuitive interpretation. Finally, the
definitions we will make here will have the elegant consequence that
from this point on we can work with any kind of intervals in exactly
the same way.
*)
Inductive interval : Type :=
| realline : interval
| openl : IR -> interval
| openr : IR -> interval
| closel : IR -> interval
| closer : IR -> interval
| olor : IR -> IR -> interval
| olcr : IR -> IR -> interval
| clor : IR -> IR -> interval
| clcr : IR -> IR -> interval.
(**
To each interval a predicate (set) is assigned by the following map:
*)
Definition iprop (I : interval) (x : IR) : CProp :=
match I with
| realline => True
| openr b => x [<] b
| openl a => a [<] x
| closer b => x [<=] b
| closel a => a [<=] x
| olor a b => a [<] x and x [<] b
| olcr a b => a [<] x and x [<=] b
| clor a b => a [<=] x and x [<] b
| clcr a b => a [<=] x and x [<=] b
end.
(* begin hide *)
Coercion iprop : interval >-> Funclass.
(* end hide *)
(**
This map is made into a coercion, so that intervals
%\emph{%#<i>#are%}%#</i># really subsets of reals.
We now define what it means for an interval to be nonvoid, proper,
finite and compact in the obvious way.
*)
Definition nonvoid (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<=] b
end.
Definition proper (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<] b
end.
Definition finite (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => True
| olcr a b => True
| clor a b => True
| clcr a b => True
end.
Definition compact_ (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => False
| olcr a b => False
| clor a b => False
| clcr a b => a [<=] b
end.
(** Finite intervals have a left end and a right end. *)
Definition left_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c.
apply c.
apply c.
apply c.
Defined.
Definition right_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c0.
apply c0.
apply c0.
apply c0.
Defined.
(**
Some trivia: compact intervals are finite; proper intervals are nonvoid; an interval is nonvoid iff it contains some point.
*)
Lemma compact_finite : forall I : interval, compact_ I -> finite I.
intros; induction I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; auto.
Qed.
Lemma proper_nonvoid : forall I : interval, proper I -> nonvoid I.
Proof.
intro.
elim I; simpl in |- *; intros; auto.
apply less_leEq; auto.
Qed.
Lemma nonvoid_point : forall I : interval, nonvoid I -> {x : IR | I x}.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try rename X into H.
exists ZeroR; auto.
exists (c[+][1]); apply less_plusOne.
exists (c[-][1]); apply shift_minus_less; apply less_plusOne.
exists c; apply leEq_reflexive.
exists c; apply leEq_reflexive.
exists (c[+] (c0[-]c) [/]TwoNZ); split.
astepl (c[+][0]); apply plus_resp_less_lft.
apply div_resp_pos.
apply pos_two.
apply shift_less_minus; astepl c; auto.
rstepr (c[+] (c0[-]c)).
apply plus_resp_less_lft.
apply pos_div_two'.
apply shift_less_minus; astepl c; auto.
exists c0; split; auto; apply leEq_reflexive.
exists c; split; auto; apply leEq_reflexive.
exists c; split; [ apply leEq_reflexive | auto ].
Qed.
Lemma nonvoid_char : forall (I : interval) (x : IR), I x -> nonvoid I.
Proof.
intro; induction I; simpl in |- *; intros x H; auto; inversion_clear H.
apply less_transitive_unfolded with x; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
Qed.
(**
For practical reasons it helps to define left end and right end of compact intervals.
*)
Definition Lend I (H : compact_ I) := left_end I (compact_finite I H).
Definition Rend I (H : compact_ I) := right_end I (compact_finite I H).
(** In a compact interval, the left end is always less than or equal
to the right end.
*)
Lemma Lend_leEq_Rend : forall I cI, Lend I cI [<=] Rend I cI.
Proof.
intro; elim I; simpl in |- *; intros; try inversion cI; auto.
Qed.
(**
Some nice characterizations of inclusion:
*)
Lemma compact_included : forall a b Hab (I : interval),
I a -> I b -> included (compact a b Hab) I.
Proof.
induction I; red in |- *; simpl in |- *; intros X X0 x X1;
try inversion_clear X; try inversion_clear X0; try inversion_clear X1.
auto.
apply less_leEq_trans with a; auto.
apply leEq_less_trans with b; auto.
apply leEq_transitive with a; auto.
apply leEq_transitive with b; auto.
split; [ apply less_leEq_trans with a | apply leEq_less_trans with b ]; auto.
split; [ apply less_leEq_trans with a | apply leEq_transitive with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_less_trans with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_transitive with b ]; auto.
Qed.
Lemma included_interval' : forall (I : interval) x y z w, I x -> I y -> I z -> I w ->
forall H, included (compact (Min x z) (Max y w) H) I.
Proof.
intros I x y z w; induction I; simpl in |- *; intros X X0 X1 X2 H; red in |- *; intros t Ht;
inversion_clear Ht; simpl in |- *; try inversion_clear X;
try inversion_clear X0; try inversion_clear X1; try inversion_clear X2; try split.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
Qed.
Lemma included_interval : forall (I : interval) x y, I x -> I y ->
forall H, included (compact (Min x y) (Max x y) H) I.
Proof.
intros; apply included_interval'; auto.
Qed.
(**
A weirder inclusion result.
*)
Lemma included3_interval : forall (I : interval) x y z Hxyz, I x -> I y -> I z ->
included (compact (Min (Min x y) z) (Max (Max x y) z) Hxyz) I.
Proof.
intros I x y z Hxyz H H0 H1.
apply included_interval'; auto.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_lft.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_rht.
Qed.
(**
Finally, all intervals are characterized by well defined predicates.
*)
Lemma iprop_wd : forall I : interval, pred_wd _ I.
Proof.
induction I; unfold iprop in |- *; red in |- *; intros x y X X0;
try inversion_clear X; try inversion X0.
auto.
astepr x; auto.
astepl x; auto.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
Qed.
End Intervals.
Implicit Arguments Lend [I].
Implicit Arguments Rend [I].
Section Compact_Constructions.
Section Single_Compact_Interval.
(**
** Constructions with Compact Intervals
Several important constructions are now discussed.
We begin by defining the compact interval [[x,x]].
%\begin{convention}% Let [P:IR->CProp] be well defined, and [x:IR]
such that [P(x)] holds.
%\end{convention}%
*)
Variable P : IR -> CProp.
Hypothesis wdP : pred_wd IR P.
Variable x : IR.
Hypothesis Hx : P x.
Definition compact_single := Compact (leEq_reflexive _ x).
(**
This interval contains [x] and only (elements equal to) [x]; furthermore, for every (well-defined) [P], if $x\in P$#x∈P# then $[x,x]\subseteq P$#[x,x]⊆P#.
*)
Lemma compact_single_prop : compact_single x.
Proof.
split; apply leEq_reflexive.
Qed.
Lemma compact_single_pt : forall y : IR, compact_single y -> x [=] y.
Proof.
intros y H.
inversion_clear H; apply leEq_imp_eq; auto.
Qed.
Lemma compact_single_inc : included compact_single P.
Proof.
red in |- *; intros.
apply wdP with x.
auto.
apply compact_single_pt; auto.
Qed.
End Single_Compact_Interval.
(**
The special case of intervals is worth singling out, as one of the hypothesis becomes a theorem.
*)
Definition compact_single_iprop I := compact_single_inc _ (iprop_wd I).
(**
Now for more interesting and important results.
Let [I] be a proper interval and [x] be a point of [I]. Then there is
a proper compact interval [[a,b]] such that $x\in[a,b]\subseteq
I$#x∈[a,b]⊆I#.
*)
Section Proper_Compact_with_One_or_Two_Points.
(* begin hide *)
Let cip1' : forall c x : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq; apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
Qed.
Let cip1'' : forall c x : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less; apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
Qed.
Let cip1''' : forall c0 x : IR, x [<=] c0 -> x [<=] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip1'''' : forall c0 x : IR, x [<] c0 -> x [<] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip2 :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<=] x0.
Proof.
intros.
apply leEq_transitive with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2' : forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply less_leEq_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2'' :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply leEq_less_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply less_wdl.
apply H0.
rational.
Qed.
Let cip2''' :
forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply cip2'' with x.
apply less_leEq; auto.
auto.
Qed.
Let cip3 :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<=] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_transitive.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_less_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip3'' :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply less_leEq_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3''' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
apply cip3'' with x; try apply less_leEq; auto.
Qed.
(* end hide *)
Definition compact_in_interval I (pI : proper I) x (Hx : I x) : interval.
Proof.
intros; destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr x (x[+][1])).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval : forall I pI x Hx,
compact_ (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try apply ts; apply less_leEq.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval : forall I pI x Hx,
proper (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)), Lend H [<] Rend H.
Proof.
do 4 intro.
cut (proper (compact_in_interval I pI x Hx)).
2: apply proper_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval : forall I pI x Hx,
included (compact_in_interval I pI x Hx) I.
Proof.
induction I; simpl in |- *; intros X x X0; try inversion_clear Hx; red in |- *;
simpl in |- *; intros x0 X1; try inversion_clear X; try inversion_clear X0;
try inversion_clear X1; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
apply leEq_transitive with x; auto.
split.
apply cip2' with x; auto.
apply cip3' with x; auto.
split.
apply cip2' with x; auto.
apply cip3 with x; auto.
split.
apply cip2 with x; auto.
apply cip3' with x; auto.
Qed.
Lemma iprop_compact_in_interval : forall I pI x Hx, compact_in_interval I pI x Hx x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; split; auto; try apply leEq_reflexive.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
Qed.
Lemma iprop_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H', compact (Lend H) (Rend H) H' x.
Proof.
do 4 intro.
cut (compact_in_interval I pI x Hx x).
2: apply iprop_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval_inc1 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval I pI x Hx).
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval_inc2 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact_in_interval I pI x Hx) (compact (Lend H) (Rend H) H').
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
(**
If [x [=] y] then the construction yields the same interval whether we
use [x] or [y] in its definition. This property is required at some
stage, which is why we formalized this result as a functional
definition rather than as an existential formula.
*)
Lemma compact_in_interval_wd1 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Lend H [=] Lend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
Lemma compact_in_interval_wd2 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Rend H [=] Rend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
(**
We can make an analogous construction for two points.
*)
Definition compact_in_interval2 I (pI : proper I) x y : I x -> I y -> interval.
Proof.
intros.
set (z1 := Min x y) in *.
set (z2 := Max x y) in *.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr z1 (z2[+][1])).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval2 : forall I pI x y Hx Hy,
compact_ (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
try apply ts; apply less_leEq.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2 : forall I pI x y Hx Hy,
proper (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2' : forall I pI x y Hx Hy H,
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H.
Proof.
do 6 intro.
cut (proper (compact_in_interval2 I pI x y Hx Hy)).
2: apply proper_compact_in_interval2.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval2 : forall I pI x y Hx Hy,
included (compact_in_interval2 I pI x y Hx Hy) I.
Proof.
induction I; simpl in |- *; intros; try inversion_clear Hx as (H,H0);
try inversion_clear Hy as (H1,H2); red in |- *; simpl in |- *;
intros x0 X; try inversion_clear X; auto.
apply less_leEq_trans with (Min x y); try apply less_Min; auto.
apply leEq_less_trans with (Max x y); try apply Max_less; auto.
apply leEq_transitive with (Min x y); try apply leEq_Min; auto.
apply leEq_transitive with (Max x y); try apply Max_leEq; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3 with (Max x y); try apply Max_leEq; auto.
split.
apply cip2 with (Min x y); try apply leEq_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_lft; try apply lft_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply lft_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_lft ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2y : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy y.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_rht; try apply rht_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply rht_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_rht ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' x.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy x).
2: apply iprop_compact_in_interval2x.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2y' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' y.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy y).
2: apply iprop_compact_in_interval2y.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2_inc1 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval2 I pI x y Hx Hy).
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval2_inc2 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact_in_interval2 I pI x y Hx Hy) (compact (Lend H) (Rend H) H').
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma compact_in_interval_x_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI x Hx) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_lft; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (x[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_lft ]).
Qed.
Lemma compact_in_interval_y_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI y Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_rht; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (y[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_rht ]).
Qed.
Lemma compact_in_interval_x_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI x Hx) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply lft_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]x) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply lft_leEq_Max ]).
Qed.
Lemma compact_in_interval_y_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI y Hy) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply rht_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]y) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply rht_leEq_Max ]).
Qed.
End Proper_Compact_with_One_or_Two_Points.
(**
Compact intervals are exactly compact intervals(!).
*)
Lemma interval_compact_inc : forall I (cI : compact_ I) H,
included I (compact (Lend cI) (Rend cI) H).
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0];intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab Hab'.
intros x H.
simpl in H.
inversion_clear H; split; auto.
Qed.
Lemma compact_interval_inc : forall I (cI : compact_ I) H,
included (compact (Lend cI) (Rend cI) H) I.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab.
intros H x H0.
inversion_clear H0; split; auto.
Qed.
(**
A generalization of the previous results: if $[a,b]\subseteq J$#[a,b]⊆J#
and [J] is proper, then we can find a proper interval [[a',b']] such that
$[a,b]\subseteq[a',b']\subseteq J$#[a,b]⊆[a',b']⊆J#.
*)
Lemma compact_proper_in_interval : forall (J : interval) a b Hab,
included (compact a b Hab) J -> proper J -> {a' : IR | {b' : IR | {Hab' : _ |
included (compact a' b' (less_leEq _ _ _ Hab')) J |
included (Compact Hab) (Compact (less_leEq _ _ _ Hab'))}}}.
Proof.
intros J a b Hab H H0.
exists (Lend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (Rend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (proper_compact_in_interval2' _ _ _ _ _ _
(compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
eapply included_trans.
apply compact_interval_inc.
apply included_compact_in_interval2.
apply included_compact.
apply iprop_compact_in_interval2x'.
apply iprop_compact_in_interval2y'.
Qed.
End Compact_Constructions.
Section Functions.
(**
** Properties of Functions in Intervals
We now define notions of continuity, differentiability and so on on
arbitrary intervals. As expected, a function [F] has property [P] in
the (proper) interval [I] iff it has property [P] in every compact
interval included in [I]. We can formalize this in a nice way using
previously defined concepts.
%\begin{convention}% Let [n:nat] and [I:interval].
%\end{convention}%
*)
Variable n : nat.
Variable I : interval.
Definition Continuous F := included I (Dom F) and (forall a b (Hab : a [<=] b),
included (Compact Hab) I -> Continuous_I Hab F).
Definition Derivative (pI : proper I) F G := included I (Dom F) and included I (Dom G) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Derivative_I Hab F G).
Definition Diffble (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I Hab F).
Definition Derivative_n (pI : proper I) F G := included I (Dom F) and included I (Dom G) and
(forall a b Hab, included (Compact (less_leEq _ a b Hab)) I -> Derivative_I_n Hab n F G).
Definition Diffble_n (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I_n Hab n F).
End Functions.
Section Reflexivity_Properties.
(**
In the case of compact intervals, this definitions collapse to the old ones.
*)
Lemma Continuous_Int :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous_I (a:=Lend cI) (b:=Rend cI) H F -> Continuous I F.
Proof.
intros I cI H F H0.
cut (included I (compact (Lend cI) (Rend cI) H)).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) H) I).
2: apply compact_interval_inc; auto.
generalize cI H H0; clear H0 H cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H H0 X X0; clear X0 X H0 H cI c0 c.
simpl in |- *; intros a b Hab Hab' contF inc1 inc2.
split.
apply included_trans with (Compact Hab'); Included.
intros.
apply included_imp_contin with (Hab := Hab'); Included.
Qed.
Lemma Int_Continuous :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous I F -> Continuous_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H F X; clear X F H cI c0 c.
simpl in |- *; intros a b Hab Hab' F contF.
inversion_clear contF.
Contin.
Qed.
Lemma Derivative_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative_I (a:=Lend cI) (b:=Rend cI) H F F' -> Derivative I pI F F'.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H cI pI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F F' X1; clear X1 F' F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F F' derF.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_deriv with (Hab := Hab'); Included.
Qed.
Lemma Int_Derivative :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative I pI F F' -> Derivative_I (a:=Lend cI) (b:=Rend cI) H F F'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F F' X; clear X F' F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F F' derF.
elim derF; intros H H0.
elim H0; intros H1 H2.
Included.
Qed.
Lemma Diffble_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble_I (a:=Lend cI) (b:=Rend cI) H F -> Diffble I pI F.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H pI cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F X1; clear X1 F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F diffF.
red in |- *; simpl in |- *.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_diffble with (Hab := Hab'); auto.
Qed.
Lemma Int_Diffble :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble I pI F -> Diffble_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F X; clear X F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F diffF.
inversion_clear diffF.
Included.
Qed.
End Reflexivity_Properties.
Section Lemmas.
(**
Interestingly, inclusion and equality in an interval are also characterizable in a similar way:
*)
Lemma included_imp_inc : forall (J : interval) P,
(forall a b Hab, included (compact a b Hab) J -> included (compact a b Hab) P) -> included J P.
Proof.
intros J P H x H0.
apply (H _ _ (leEq_reflexive _ _) (compact_single_iprop J x H0)).
apply compact_inc_lft.
Qed.
Lemma included_Feq'' : forall I F G, proper I -> (forall a b Hab (Hab':=(less_leEq _ a b Hab)),
included (Compact Hab') I -> Feq (Compact Hab') F G) -> Feq I F G.
Proof.
intros I F G H H0.
apply eq_imp_Feq.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
apply a0; apply H3; apply compact_single_prop.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply X; apply H3; apply compact_single_prop.
intros x H1 Hx Hx'.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply H4; apply H3; apply compact_single_prop.
Qed.
Lemma included_Feq' : forall (I : interval) F G,
(forall a b Hab, included (compact a b Hab) I -> Feq (Compact Hab) F G) -> Feq I F G.
Proof.
intros I F G H.
apply eq_imp_Feq.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
apply a; apply compact_single_prop.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply X; apply compact_single_prop.
intros x H0 Hx Hx'.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply H1; apply compact_single_prop.
Qed.
End Lemmas.
Hint Resolve included_interval included_interval' included3_interval
compact_single_inc compact_single_iprop included_compact_in_interval
iprop_compact_in_interval_inc1 iprop_compact_in_interval_inc2
included_compact_in_interval2 iprop_compact_in_interval2_inc1
iprop_compact_in_interval2_inc2 interval_compact_inc compact_interval_inc
iprop_wd: included.
|
module top_tb;
reg clk_i = 0;
reg rst_i = 1;
reg [4:0] rx_i_ctr = 0;
reg [19:0] rx_tmp = 20'b10100011101010010000;
reg tmp_rx_bit = 1;
wire clk_uart_rx, clk_uart_tx;
wire [7:0] led_o;
wire rs232_tx_o;
wire rs232_rx_i;
initial
begin
$dumpfile("./build/iverilog/uart.vcd");
$dumpvars(0,top_tb);
# 1250 rst_i <= 0;
# 200000 $finish;
end
top tb (
.ice_clk_i (clk_i),
.rstn_i(rst_i),
.rs232_rx_i(rs232_rx_i),
.led_o (led_o),
.rs232_tx_o(rs232_tx_o)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
always #1 clk_i = ~clk_i;
assign rs232_rx_i =tmp_rx_bit;
always @ (posedge (clk_uart_tx))
begin
tmp_rx_bit <= rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
end
always @ (posedge clk_uart_tx)
begin
if (rx_i_ctr == 19 | rst_i)
begin
rx_i_ctr <= 0;
end
else
begin
rx_i_ctr <= rx_i_ctr + 1;
end
end
endmodule // top
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t;
`ifdef T_GEN_MISSING_BAD
foobar #(.FOO_TYPE(1)) foobar; // This means we should instatiate missing module
`elsif T_GEN_MISSING
foobar #(.FOO_TYPE(0)) foobar; // This means we should instatiate foo0
`else
`error "Bad Test"
`endif
endmodule
module foobar
#( parameter
FOO_START = 0,
FOO_NUM = 2,
FOO_TYPE = 1
)
(
input wire[FOO_NUM-1:0] foo,
output wire[FOO_NUM-1:0] bar);
generate
begin: g
genvar j;
for (j = FOO_START; j < FOO_NUM+FOO_START; j = j + 1)
begin: foo_inst;
if (FOO_TYPE == 0)
begin: foo_0
// instatiate foo0
foo0 i_foo(.x(foo[j]), .y(bar[j]));
end
if (FOO_TYPE == 1)
begin: foo_1
// instatiate foo1
foo_not_needed i_foo(.x(foo[j]), .y(bar[j]));
end
end
end
endgenerate
endmodule
module foo0(input wire x, output wire y);
assign y = ~x;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_AXIvideo2Mat (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_din,
img_data_stream_0_V_full_n,
img_data_stream_0_V_write,
img_data_stream_1_V_din,
img_data_stream_1_V_full_n,
img_data_stream_1_V_write,
img_data_stream_2_V_din,
img_data_stream_2_V_full_n,
img_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 7'b1;
parameter ap_ST_st2_fsm_1 = 7'b10;
parameter ap_ST_st3_fsm_2 = 7'b100;
parameter ap_ST_st4_fsm_3 = 7'b1000;
parameter ap_ST_pp1_stg0_fsm_4 = 7'b10000;
parameter ap_ST_st7_fsm_5 = 7'b100000;
parameter ap_ST_st8_fsm_6 = 7'b1000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [31:0] INPUT_STREAM_TDATA;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [0:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [0:0] INPUT_STREAM_TID;
input [0:0] INPUT_STREAM_TDEST;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
output [7:0] img_data_stream_0_V_din;
input img_data_stream_0_V_full_n;
output img_data_stream_0_V_write;
output [7:0] img_data_stream_1_V_din;
input img_data_stream_1_V_full_n;
output img_data_stream_1_V_write;
output [7:0] img_data_stream_2_V_din;
input img_data_stream_2_V_full_n;
output img_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg INPUT_STREAM_TREADY;
reg img_data_stream_0_V_write;
reg img_data_stream_1_V_write;
reg img_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [6:0] ap_CS_fsm = 7'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_26;
reg [0:0] eol_1_reg_184;
reg [31:0] axi_data_V_1_reg_195;
reg [11:0] p_1_reg_206;
reg [0:0] eol_reg_217;
reg [0:0] axi_last_V_2_reg_229;
reg [31:0] p_Val2_s_reg_241;
reg [0:0] eol_2_reg_253;
reg ap_sig_bdd_75;
reg [31:0] tmp_data_V_reg_402;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_87;
reg [0:0] tmp_last_V_reg_410;
wire [0:0] exitcond1_fu_319_p2;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_101;
wire [11:0] i_V_fu_324_p2;
reg [11:0] i_V_reg_426;
wire [0:0] exitcond2_fu_330_p2;
reg [0:0] exitcond2_reg_431;
reg ap_sig_cseq_ST_pp1_stg0_fsm_4;
reg ap_sig_bdd_112;
wire [0:0] brmerge_fu_344_p2;
reg ap_sig_bdd_120;
reg ap_reg_ppiten_pp1_it0 = 1'b0;
reg ap_sig_bdd_133;
reg ap_reg_ppiten_pp1_it1 = 1'b0;
wire [11:0] j_V_fu_335_p2;
wire [7:0] tmp_34_fu_363_p1;
reg [7:0] tmp_34_reg_444;
reg [7:0] tmp_6_reg_449;
reg [7:0] tmp_7_reg_454;
reg ap_sig_cseq_ST_st7_fsm_5;
reg ap_sig_bdd_158;
reg ap_sig_bdd_163;
reg [0:0] axi_last_V_3_reg_264;
reg [0:0] axi_last_V1_reg_153;
reg ap_sig_cseq_ST_st8_fsm_6;
reg ap_sig_bdd_181;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_188;
reg [31:0] axi_data_V_3_reg_276;
reg [31:0] axi_data_V1_reg_163;
reg [11:0] p_s_reg_173;
reg [0:0] eol_1_phi_fu_187_p4;
reg [31:0] axi_data_V_1_phi_fu_198_p4;
reg [0:0] eol_phi_fu_221_p4;
wire [0:0] ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
wire [31:0] ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
reg [31:0] p_Val2_s_phi_fu_245_p4;
wire [0:0] ap_reg_phiprechg_eol_2_reg_253pp1_it0;
wire [0:0] axi_last_V_1_mux_fu_356_p2;
reg [0:0] eol_3_reg_288;
reg [0:0] sof_1_fu_98;
wire [0:0] not_sof_2_fu_350_p2;
wire [0:0] tmp_user_V_fu_310_p1;
reg [6:0] ap_NS_fsm;
reg ap_sig_bdd_119;
reg ap_sig_bdd_211;
reg ap_sig_bdd_144;
reg ap_sig_bdd_229;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp1_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp1_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
end else if (ap_sig_bdd_119) begin
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
end else if ((ap_true == ap_true)) begin
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
eol_1_reg_184 <= axi_last_V_2_reg_229;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
eol_1_reg_184 <= axi_last_V1_reg_153;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
end else if (ap_sig_bdd_119) begin
eol_2_reg_253 <= INPUT_STREAM_TLAST;
end else if ((ap_true == ap_true)) begin
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
eol_3_reg_288 <= eol_phi_fu_221_p4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
eol_reg_217 <= eol_2_reg_253;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
eol_reg_217 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
p_1_reg_206 <= j_V_fu_335_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
p_1_reg_206 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (ap_sig_bdd_144) begin
if (ap_sig_bdd_211) begin
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
end else if (ap_sig_bdd_119) begin
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
end else if ((ap_true == ap_true)) begin
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
p_s_reg_173 <= ap_const_lv12_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_6)) begin
p_s_reg_173 <= i_V_reg_426;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
sof_1_fu_98 <= ap_const_lv1_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
sof_1_fu_98 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
i_V_reg_426 <= i_V_fu_324_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
tmp_34_reg_444 <= tmp_34_fu_363_p1;
tmp_6_reg_449 <= {{p_Val2_s_phi_fu_245_p4[ap_const_lv32_F : ap_const_lv32_8]}};
tmp_7_reg_454 <= {{p_Val2_s_phi_fu_245_p4[ap_const_lv32_17 : ap_const_lv32_10]}};
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(INPUT_STREAM_TVALID == ap_const_logic_0))) begin
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end
end
/// INPUT_STREAM_TREADY assign process. ///
always @ (INPUT_STREAM_TVALID or ap_sig_cseq_ST_st2_fsm_1 or exitcond2_fu_330_p2 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or brmerge_fu_344_p2 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1 or ap_sig_cseq_ST_st7_fsm_5 or ap_sig_bdd_163 or eol_3_reg_288)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(INPUT_STREAM_TVALID == ap_const_logic_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_5) & (ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1)))))) begin
INPUT_STREAM_TREADY = ap_const_logic_1;
end else begin
INPUT_STREAM_TREADY = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond1_fu_319_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond1_fu_319_p2 or ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(exitcond1_fu_319_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. ///
always @ (ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp1_stg0_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_5 assign process. ///
always @ (ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st8_fsm_6 assign process. ///
always @ (ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st8_fsm_6 = ap_const_logic_0;
end
end
/// axi_data_V_1_phi_fu_198_p4 assign process. ///
always @ (axi_data_V_1_reg_195 or p_Val2_s_reg_241 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
axi_data_V_1_phi_fu_198_p4 = p_Val2_s_reg_241;
end else begin
axi_data_V_1_phi_fu_198_p4 = axi_data_V_1_reg_195;
end
end
/// eol_1_phi_fu_187_p4 assign process. ///
always @ (eol_1_reg_184 or axi_last_V_2_reg_229 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
eol_1_phi_fu_187_p4 = axi_last_V_2_reg_229;
end else begin
eol_1_phi_fu_187_p4 = eol_1_reg_184;
end
end
/// eol_phi_fu_221_p4 assign process. ///
always @ (eol_reg_217 or eol_2_reg_253 or exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) begin
eol_phi_fu_221_p4 = eol_2_reg_253;
end else begin
eol_phi_fu_221_p4 = eol_reg_217;
end
end
/// img_data_stream_0_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_0_V_write = ap_const_logic_1;
end else begin
img_data_stream_0_V_write = ap_const_logic_0;
end
end
/// img_data_stream_1_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_1_V_write = ap_const_logic_1;
end else begin
img_data_stream_1_V_write = ap_const_logic_0;
end
end
/// img_data_stream_2_V_write assign process. ///
always @ (exitcond2_reg_431 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_reg_431 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))))) begin
img_data_stream_2_V_write = ap_const_logic_1;
end else begin
img_data_stream_2_V_write = ap_const_logic_0;
end
end
/// p_Val2_s_phi_fu_245_p4 assign process. ///
always @ (INPUT_STREAM_TDATA or brmerge_fu_344_p2 or axi_data_V_1_phi_fu_198_p4 or ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 or ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) begin
if (~(ap_const_lv1_0 == brmerge_fu_344_p2)) begin
p_Val2_s_phi_fu_245_p4 = axi_data_V_1_phi_fu_198_p4;
end else if ((ap_const_lv1_0 == brmerge_fu_344_p2)) begin
p_Val2_s_phi_fu_245_p4 = INPUT_STREAM_TDATA;
end else begin
p_Val2_s_phi_fu_245_p4 = ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end else begin
p_Val2_s_phi_fu_245_p4 = ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or INPUT_STREAM_TVALID or ap_sig_bdd_75 or exitcond1_fu_319_p2 or exitcond2_fu_330_p2 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1 or ap_sig_bdd_163 or eol_3_reg_288 or tmp_user_V_fu_310_p1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_75) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if ((~(INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == tmp_user_V_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~(INPUT_STREAM_TVALID == ap_const_logic_0) & ~(ap_const_lv1_0 == tmp_user_V_fu_310_p1))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
ap_ST_st4_fsm_3 :
begin
if (~(exitcond1_fu_319_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_pp1_stg0_fsm_4 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))) & ~(exitcond2_fu_330_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else begin
ap_NS_fsm = ap_ST_pp1_stg0_fsm_4;
end
end
ap_ST_st7_fsm_5 :
begin
if (((ap_const_lv1_0 == eol_3_reg_288) & ~ap_sig_bdd_163)) begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end else if ((~ap_sig_bdd_163 & ~(ap_const_lv1_0 == eol_3_reg_288))) begin
ap_NS_fsm = ap_ST_st8_fsm_6;
end else begin
ap_NS_fsm = ap_ST_st7_fsm_5;
end
end
ap_ST_st8_fsm_6 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 = 'bx;
assign ap_reg_phiprechg_eol_2_reg_253pp1_it0 = 'bx;
assign ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 = 'bx;
/// ap_sig_bdd_101 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_101 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_112 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_112 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_119 assign process. ///
always @ (exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_119 = ((exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_120 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_120 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_133 assign process. ///
always @ (img_data_stream_0_V_full_n or img_data_stream_1_V_full_n or img_data_stream_2_V_full_n or exitcond2_reg_431)
begin
ap_sig_bdd_133 = (((img_data_stream_0_V_full_n == ap_const_logic_0) & (exitcond2_reg_431 == ap_const_lv1_0)) | ((exitcond2_reg_431 == ap_const_lv1_0) & (img_data_stream_1_V_full_n == ap_const_logic_0)) | ((exitcond2_reg_431 == ap_const_lv1_0) & (img_data_stream_2_V_full_n == ap_const_logic_0)));
end
/// ap_sig_bdd_144 assign process. ///
always @ (ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_sig_bdd_120 or ap_reg_ppiten_pp1_it0 or ap_sig_bdd_133 or ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0) & ~((ap_sig_bdd_120 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0)) | (ap_sig_bdd_133 & (ap_const_logic_1 == ap_reg_ppiten_pp1_it1))));
end
/// ap_sig_bdd_158 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_158 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_163 assign process. ///
always @ (INPUT_STREAM_TVALID or eol_3_reg_288)
begin
ap_sig_bdd_163 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == eol_3_reg_288));
end
/// ap_sig_bdd_181 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_181 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_188 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_188 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_211 assign process. ///
always @ (exitcond2_fu_330_p2 or brmerge_fu_344_p2)
begin
ap_sig_bdd_211 = ((exitcond2_fu_330_p2 == ap_const_lv1_0) & ~(ap_const_lv1_0 == brmerge_fu_344_p2));
end
/// ap_sig_bdd_229 assign process. ///
always @ (exitcond2_fu_330_p2 or ap_sig_cseq_ST_pp1_stg0_fsm_4 or ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 = ((ap_const_logic_1 == ap_sig_cseq_ST_pp1_stg0_fsm_4) & (exitcond2_fu_330_p2 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp1_it0));
end
/// ap_sig_bdd_26 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_26 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_75 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_75 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_87 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_87 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
assign axi_last_V_1_mux_fu_356_p2 = (eol_1_phi_fu_187_p4 | not_sof_2_fu_350_p2);
assign brmerge_fu_344_p2 = (sof_1_fu_98 | eol_phi_fu_221_p4);
assign exitcond1_fu_319_p2 = (p_s_reg_173 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond2_fu_330_p2 = (p_1_reg_206 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_324_p2 = (p_s_reg_173 + ap_const_lv12_1);
assign img_data_stream_0_V_din = tmp_34_reg_444;
assign img_data_stream_1_V_din = tmp_6_reg_449;
assign img_data_stream_2_V_din = tmp_7_reg_454;
assign j_V_fu_335_p2 = (p_1_reg_206 + ap_const_lv12_1);
assign not_sof_2_fu_350_p2 = (sof_1_fu_98 ^ ap_const_lv1_1);
assign tmp_34_fu_363_p1 = p_Val2_s_phi_fu_245_p4[7:0];
assign tmp_user_V_fu_310_p1 = INPUT_STREAM_TUSER;
endmodule //image_filter_AXIvideo2Mat
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v4_0_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v4_0_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v4_0_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:55:37 06/19/2014
// Design Name:
// Module Name: CAR_CTR
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CAR_CTR(
output reg md1,
output reg md2,
output reg md3,
output reg md4,
input infL,
input infR,
input clk,
input reset_n
);
parameter FWD = 2'b00;
parameter STOP = 2'b01;
parameter RIGHT = 2'b10;
parameter LEFT = 2'b11;
parameter HIGH = 1'b1;
parameter LOW = 1'b0;
always @(*) begin
if (infL == LOW && infR == LOW) begin
// fwd
md1 = HIGH;
md2 = LOW;
md3 = HIGH;
md4 = LOW;
end else if (infL == HIGH && infR == LOW) begin
// right acc
md1 = LOW;
md2 = LOW;
md3 = HIGH;
md4 = LOW;
end else if (infL == LOW && infR == HIGH) begin
// left acc
md1 = HIGH;
md2 = LOW;
md3 = LOW;
md4 = LOW;
end else begin
// stop
md1 = LOW;
md2 = LOW;
md3 = LOW;
md4 = LOW;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;
// The instantiation will Z extend, not sign extend
// verilator lint_off WIDTH
sub sub (.clk,
.sgn(sgn_wide), .unsgn(unsgn_wide),
.iss(3'sh7), .isu(3'h7),
.ius(3'sh7), .iuu(3'h7));
// verilator lint_on WIDTH
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
`endif
if (sgn_wide[2:0] != 3'sh7) $stop;
if (unsgn_wide[2:0] != 3'h7) $stop;
// Simulators differ here.
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
if (unsgn_wide !== 8'sbzzzzz111
&& unsgn_wide!== 8'sb00000111) $stop;
cyc <= cyc + 1;
if (cyc==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input clk,
output wire signed [2:0] sgn,
output wire [2:0] unsgn,
input signed [7:0] iss,
input signed [7:0] isu,
input [7:0] ius,
input [7:0] iuu);
assign sgn = 3'sh7;
assign unsgn = 3'h7;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
if (iss != 8'hff) $stop;
if (isu != 8'h07) $stop;
if (ius != 8'hff) $stop;
if (iuu != 8'h07) $stop;
`endif
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module implements exponent extraction and returns the adjusted exponent as integer.
// Adjusted means that we remove the bias implicit in the FP numbers. That is exp=127 that represents exponent of 0
// is returned as 0.
module acl_fp_extract_exp( clock, resetn, enable, valid_in, valid_out, stall_in, stall_out, dataa, result);
parameter WIDTH = 32;
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input enable, valid_in, stall_in;
output valid_out, stall_out;
input [WIDTH-1:0] dataa;
output [31:0] result;
// Simply extract the mantissa and at the most shift it to the right by one position.
reg c1_valid;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
reg [31:0] c1_exponent;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 32'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (WIDTH==32)
begin
if ((~(|dataa[WIDTH-2:WIDTH-9])) || (&dataa[WIDTH-2:WIDTH-9]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-9]} - 9'd127;
end
end
else
begin
if ((~(|dataa[WIDTH-2:WIDTH-12])) || (&dataa[WIDTH-2:WIDTH-12]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-12]} - 12'd1023;
end
end
end
end
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign result = c1_exponent;
endmodule
|