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///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRC Generator.
// File : crcx.v
// Author : Jim Macleod
// Created : 11-March-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//CRC over 24-bit characters, using generator polynomial
//
// g(x) = x*24 + x*7 + x*2 + x + 1
//
// The shift register formulas are shown below. Ci is bit i of the 24-bit shift
// register; Di is bit i of the 24-bit data word.
//
// Generation process:
// - Load the shift register with all-1's
// - XOR 24 bits of data with the register contents and shift once according to
// g(x)
// - Repeat data entry and shifting until end of data
//
/////////////////////////////////////////////////////////////////////////////////
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crcx
(
input pixclk,
input rstn,
input enable_crc,
input init_crc,
input [7:0] red,
input [7:0] grn,
input [7:0] blu,
output [7:0] misr_red,
output [7:0] misr_grn,
output [7:0] misr_blu
);
reg[23:0] crc_out;
wire[23:0] crc_in ;
assign crc_in[23:16] = red[7:0] ;
assign crc_in[15: 8] = grn[7:0] ;
assign crc_in[ 7: 0] = blu[7:0] ;
always @(posedge pixclk or negedge rstn)
if (!rstn)
begin crc_out[23:0] <= 24'hFFFFFF; end
else begin
if (init_crc)
crc_out[23:0] <= 24'hFFFFFF;
else if (enable_crc)
begin
crc_out[0] <= crc_out[1] ^ crc_in[1];
crc_out[1] <= crc_out[2] ^ crc_in[2];
crc_out[2] <= crc_out[3] ^ crc_in[3];
crc_out[3] <= crc_out[4] ^ crc_in[4];
crc_out[4] <= crc_out[5] ^ crc_in[5];
crc_out[5] <= crc_out[6] ^ crc_in[6];
crc_out[6] <= crc_out[7] ^ crc_in[7];
crc_out[7] <= crc_out[8] ^ crc_in[8];
crc_out[8] <= crc_out[9] ^ crc_in[9];
crc_out[9] <= crc_out[10] ^ crc_in[10];
crc_out[10] <= crc_out[11] ^ crc_in[11];
crc_out[11] <= crc_out[12] ^ crc_in[12];
crc_out[12] <= crc_out[13] ^ crc_in[13];
crc_out[13] <= crc_out[14] ^ crc_in[14];
crc_out[14] <= crc_out[15] ^ crc_in[15];
crc_out[15] <= crc_out[16] ^ crc_in[16];
crc_out[16] <= crc_out[17] ^ crc_in[17] ^ crc_out[0] ^crc_in[0];
crc_out[17] <= crc_out[18] ^ crc_in[18];
crc_out[18] <= crc_out[19] ^ crc_in[19];
crc_out[19] <= crc_out[20] ^ crc_in[20];
crc_out[20] <= crc_out[21] ^ crc_in[21];
crc_out[21] <= crc_out[22] ^ crc_in[22] ^ crc_out[0] ^ crc_in[0];
crc_out[22] <= crc_out[23] ^ crc_in[23] ^ crc_out[0] ^ crc_in[0];
crc_out[23] <= crc_out[0] ^ crc_in[0];
end
end
assign misr_red[7:0] = crc_out[23:16];
assign misr_grn[7:0] = crc_out[15:8];
assign misr_blu[7:0] = crc_out[7:0];
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zybo_zynq_design_processing_system7_0_0_stub.v
// Design : zybo_zynq_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 05-13-2005
//
// Six input three output compressor (non-carry adder)
//
// Maps to 3 Stratix II six luts. Use optimize = speed
//
module six_three_comp (data,sum);
input [5:0] data;
output [2:0] sum;
reg [2:0] sum /* synthesis keep */;
always @(data) begin
case (data)
0: sum=0;
1: sum=1;
2: sum=1;
3: sum=2;
4: sum=1;
5: sum=2;
6: sum=2;
7: sum=3;
8: sum=1;
9: sum=2;
10: sum=2;
11: sum=3;
12: sum=2;
13: sum=3;
14: sum=3;
15: sum=4;
16: sum=1;
17: sum=2;
18: sum=2;
19: sum=3;
20: sum=2;
21: sum=3;
22: sum=3;
23: sum=4;
24: sum=2;
25: sum=3;
26: sum=3;
27: sum=4;
28: sum=3;
29: sum=4;
30: sum=4;
31: sum=5;
32: sum=1;
33: sum=2;
34: sum=2;
35: sum=3;
36: sum=2;
37: sum=3;
38: sum=3;
39: sum=4;
40: sum=2;
41: sum=3;
42: sum=3;
43: sum=4;
44: sum=3;
45: sum=4;
46: sum=4;
47: sum=5;
48: sum=2;
49: sum=3;
50: sum=3;
51: sum=4;
52: sum=3;
53: sum=4;
54: sum=4;
55: sum=5;
56: sum=3;
57: sum=4;
58: sum=4;
59: sum=5;
60: sum=4;
61: sum=5;
62: sum=5;
63: sum=6;
default: sum=0;
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_r_message_buffer_X.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder (page decoder) BRAM buffer
// Module Name: d_r_message_buffer_X
// File Name: d_r_message_buffer_X.v
//
// Version: v1.0.0
//
// Description: Data buffer array for BCH decoder
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_r_message_buffer_X
#(
parameter Multi = 2,
parameter AddressWidth = 8,
parameter DataWidth = 16
)
(
i_clk,
i_RESET,
i_ena,
i_wea,
i_addra,
i_dina,
i_clkb,
i_enb,
i_addrb,
o_doutb,
i_ELP_search_stage_end,
i_c_message_output_cmplt,
i_error_detection_stage_end
);
input i_clk;
input i_RESET;
input [Multi-1:0] i_ena;
input [Multi-1:0] i_wea;
input [AddressWidth*Multi-1:0] i_addra;
input [DataWidth-1:0] i_dina;
input i_clkb;
input [Multi-1:0] i_enb;
input [AddressWidth*Multi-1:0] i_addrb;
output [DataWidth-1:0] o_doutb;
input i_ELP_search_stage_end;
input i_c_message_output_cmplt;
input i_error_detection_stage_end;
wire w_BRAM_write_enable;
wire w_BRAM_read_enable;
wire [DataWidth-1:0] w_BRAM_write_data;
wire [DataWidth-1:0] w_BRAM_read_data;
wire [AddressWidth-1:0] w_BRAM_write_address;
wire [AddressWidth-1:0] w_BRAM_read_address;
wire [AddressWidth+3-1:0] w_BRAM_write_access_address;
wire [AddressWidth+3-1:0] w_BRAM_read_access_address;
reg [2:0] r_BRAM_write_sel;
reg [2:0] r_BRAM_read_sel;
assign w_BRAM_write_enable = i_ena[0];
assign w_BRAM_read_enable = i_enb[0];
assign w_BRAM_write_data = i_dina;
assign o_doutb = w_BRAM_read_data;
assign w_BRAM_write_address = i_addra[AddressWidth-1:0];
assign w_BRAM_read_address = i_addrb[AddressWidth-1:0];
assign w_BRAM_write_access_address = {r_BRAM_write_sel, w_BRAM_write_address};
assign w_BRAM_read_access_address = {r_BRAM_read_sel, w_BRAM_read_address};
always @ (posedge i_clk) begin
if (i_RESET)
r_BRAM_write_sel <= 0;
else begin
if (i_error_detection_stage_end)
r_BRAM_write_sel <= (r_BRAM_write_sel == 3'b100) ? 3'b000 : r_BRAM_write_sel + 1'b1;
else
r_BRAM_write_sel <= r_BRAM_write_sel;
end
end
always @ (posedge i_clk) begin
if (i_RESET)
r_BRAM_read_sel <= 0;
else begin
if (i_c_message_output_cmplt)
r_BRAM_read_sel <= (r_BRAM_read_sel == 3'b100) ? 3'b000 : r_BRAM_read_sel + 1'b1;
else
r_BRAM_read_sel <= r_BRAM_read_sel;
end
end
DCDPRAM16x1280WC
Inst_DCDPRAM
(
.clka (i_clk ),
.ena (w_BRAM_write_enable ),
.wea (w_BRAM_write_enable ),
.addra (w_BRAM_write_access_address ),
.dina (w_BRAM_write_data ),
.clkb (i_clk ),
.enb (w_BRAM_read_enable ),
.addrb (w_BRAM_read_access_address ),
.doutb (w_BRAM_read_data )
);
endmodule |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module defines the LDEXP function, which multiplies a floating point number by 2^(shift_in).
// The result is a valid floating point number within single-precision range, +/- INF or 0.
// If a denormalized number is supplied as input, the result will be zero (until we add denormalized
// number support).
//
module acl_fp_ldexp_double_hc(clock, resetn, dataa, datab, valid_in, valid_out, stall_in, stall_out, result);
input clock, resetn;
input [63:0] dataa;
input [31:0] datab;
input valid_in, stall_in;
output valid_out, stall_out;
output [63:0] result;
// Cycle 1: Test inputs and compute resulting exponents.
wire [10:0] exponent_in = dataa[62:52];
wire [51:0] mantissa_in = dataa[51:0];
wire sign_in = dataa[63];
wire [31:0] shift_in = datab;
wire [31:0] intermediate_exp = shift_in + {1'b0, exponent_in};
reg [10:0] exp_stage_1;
reg [51:0] man_stage_1;
reg sign_stage_1;
reg stage_1_valid;
wire enable_stage_1;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
exp_stage_1 <= 11'dx;
man_stage_1 <= 52'dx;
sign_stage_1 <= 1'bx;
stage_1_valid <= 1'b0;
end
else if (enable_stage_1)
begin
stage_1_valid <= valid_in;
sign_stage_1 <= sign_in;
if (exponent_in == 11'h7ff)
begin
// NaN / Inf input, so produce an NaN / Inf output.
man_stage_1 <= mantissa_in;
exp_stage_1 <= exponent_in;
end
else
if (intermediate_exp[31] | (exponent_in == 11'd0))
begin
// This flushes denorms to zero, even is a denorm is an input to this module.
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'd0;
end
else if ({1'b0, intermediate_exp[30:0]} >= 12'h7ff)
begin
// infinity
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'h7ff;
end
else if (intermediate_exp[10:0] == 11'd0)
begin
// If exponent ends up at 0, then flush the result to 0.
// This is the flushing of a denorm to zero after the ldexp operation.
man_stage_1 <= 52'd0;
exp_stage_1 <= 11'd0;
end
else
begin
man_stage_1 <= mantissa_in;
exp_stage_1 <= intermediate_exp[10:0];
end
end
end
assign enable_stage_1 = ~stage_1_valid | ~stall_in;
assign valid_out = stage_1_valid;
assign stall_out = stage_1_valid & stall_in;
assign result = {sign_stage_1, exp_stage_1, man_stage_1};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`include "verilated.v"
`define STRINGIFY(x) `"x`"
`define ratio_error(a,b) (((a)>(b) ? ((a)-(b)) : ((b)-(a))) /(a))
`define checkr(gotv,expv) do if (`ratio_error((gotv),(expv))>0.0001) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t;
integer file;
integer file_a[0];
integer chars;
reg [1*8:1] letterl;
reg [8*8:1] letterq;
reg signed [8*8:1] letterqs;
reg [16*8:1] letterw;
reg [16*8:1] letterz;
real r;
string s;
integer i;
reg [7:0] v_a,v_b,v_c,v_d;
reg [31:0] v_worda;
reg [31:0] v_wordb;
integer v_length, v_off;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
`define verbose 1'b0
`endif
initial begin
// Display formatting
`ifdef verilator
if (file != 0) $stop;
$fwrite(file, "Never printed, file closed\n");
if (!$feof(file)) $stop;
`endif
`ifdef AUTOFLUSH
// The "w" is required so we get a FD not a MFD
file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_autoflush.log"},"w");
`else
// The "w" is required so we get a FD not a MFD
file = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_basic_test.log"},"w");
`endif
if ($feof(file)) $stop;
$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
$fwrite(file, "[%0t] %s\n", $time, "Hello2");
i = 12;
$fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i);
$fdisplay(file);
$fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i);
$fdisplayh(file);
$fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i);
$fdisplayo(file);
$fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i);
$fdisplayb(file);
$fflush(file);
$fflush();
$fflush;
$fclose(file);
`ifdef verilator
if (file != 0) $stop(1); // Also test arguments to stop
$fwrite(file, "Never printed, file closed\n");
`endif
begin
// Check for opening errors
// The "r" is required so we get a FD not a MFD
file = $fopen("DOES_NOT_EXIST","r");
if (|file) $stop; // Should not exist, IE must return 0
// Check error function
s = "";
i = $ferror(file, s);
`checkh(i, 2);
`checks(s, "No such file or directory");
end
begin
// Check quadword access; a little strange, but it's legal to open "."
// Also checks using array reference
file_a[0] = $fopen(".","r");
if (file_a[0] == 0) $stop;
$fclose(file_a[0]);
end
begin
// Check read functions w/string
s = "t/t_sys_file_basic_input.dat";
file = $fopen(s,"r");
if ($feof(file)) $stop;
$fclose(file);
end
begin
// Check read functions
file = $fopen("t/t_sys_file_basic_input.dat","r");
if ($feof(file)) $stop;
// $fgetc
if ($fgetc(file) != "h") $stop;
if ($fgetc(file) != "i") $stop;
if ($fgetc(file) != "\n") $stop;
// $ungetc
if ($ungetc("x", file) != 0) $stop;
if ($fgetc(file) != "x") $stop;
// $fgets
chars = $fgets(letterl, file);
if (`verbose) $write("c=%0d l=%s\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "l") $stop;
chars = $fgets(letterq, file);
if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline
if (chars != 5) $stop;
if (letterq != "\0\0\0quad\n") $stop;
letterw = "5432109876543210";
chars = $fgets(letterw, file);
if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline
if (chars != 10) $stop;
if (letterw != "\0\0\0\0\0\0widestuff\n") $stop;
s = "";
chars = $fgets(s, file);
if (`verbose) $write("c=%0d w=%s", chars, s); // Output includes newline
if (chars != 7) $stop;
if (s != "string\n") $stop;
// $sscanf
if ($sscanf("x","")!=0) $stop;
if ($sscanf("z","z")!=0) $stop;
chars = $sscanf("blabcdefghijklmnop",
"%s", letterq);
if (`verbose) $write("c=%0d sa=%s\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != "ijklmnop") $stop;
chars = $sscanf("xa=1f ign=22 xb=12898971238912389712783490823_abcdef689_02348923",
"xa=%x ign=%*d xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h389712783490823_abcdef689_02348923) $stop;
chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ",
"ba=%b bb=%b%s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop;
chars = $sscanf("oa=23 oi=11 ob=125634123615234123681236",
"oa=%o oi=%*o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h55ce14f1a9c29e) $stop;
chars = $sscanf("r=0.1 d=-236123",
"r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
`checkr(r, 0.1);
if (letterq != 64'hfffffffffffc65a5) $stop;
chars = $sscanf("scan from string",
"scan %s string", s);
if (`verbose) $write("c=%0d s=%s\n", chars, s);
if (chars != 1) $stop;
if (s != "from") $stop;
// Cover quad and %e/%f
chars = $sscanf("r=0.2",
"r=%e", r);
if (`verbose) $write("c=%0d r=%e\n", chars, r);
`checkr(r, 0.2);
chars = $sscanf("r=0.3",
"r=%f", r);
if (`verbose) $write("c=%0d r=%f\n", chars, r);
`checkr(r, 0.3);
s = "r=0.2 d=-236124";
chars = $sscanf(s, "r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
`checkr(r, 0.2);
if (letterq != 64'hfffffffffffc65a4) $stop;
// $fscanf
if ($fscanf(file,"")!=0) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h23790468902348923) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != "\0\0\0\0note_the_two") $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h1573) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "d=%d", letterq);
if (`verbose) $write("c=%0d d=%0x\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "u=%d", letterqs);
if (`verbose) $write("c=%0d u=%0x\n", chars, letterqs);
if (chars != 1) $stop;
if (letterqs != -236124) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "%c%s", letterl, letterw);
if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw);
if (chars != 2) $stop;
if (letterl != "f") $stop;
if (letterw != "\0\0\0\0\0redfishblah") $stop;
chars = $fscanf(file, "%c", letterl);
if (`verbose) $write("c=%0d l=%x\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "\n") $stop;
chars = $fscanf(file, "%c%s not_included\n", letterl, s);
if (`verbose) $write("c=%0d l=%s\n", chars, s);
if (chars != 2) $stop;
if (s != "BCD") $stop;
// msg1229
v_a = $fgetc(file);
v_b = $fgetc(file);
v_c = $fgetc(file);
v_d = $fgetc(file);
v_worda = { v_d, v_c, v_b, v_a };
if (v_worda != "4321") $stop;
v_wordb[7:0] = $fgetc(file);
v_wordb[15:8] = $fgetc(file);
v_wordb[23:16] = $fgetc(file);
v_wordb[31:24] = $fgetc(file);
if (v_wordb != "9876") $stop;
if ($fgetc(file) != "\n") $stop;
v_length = $ftell(file);
$frewind(file);
v_off = $ftell(file);
if (v_off != 0) $stop;
$fseek(file, 10, 0);
v_off = $ftell(file);
if (v_off != 10) $stop;
$fseek(file, 1, 1);
v_off = $ftell(file);
if (v_off != 11) $stop;
$fseek(file, -1, 1);
v_off = $ftell(file);
if (v_off != 10) $stop;
$fseek(file, v_length, 0);
v_off = $ftell(file);
if (v_off != v_length) $stop;
if ($fseek(file, 0, 2) != 0) $stop;
v_off = $ftell(file);
if (v_off < v_length) $stop;
if ($rewind(file) != 0) $stop;
v_off = $ftell(file);
if (v_off != 0) $stop;
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
function sync;
input [7:0] cexp;
reg [7:0] cgot;
begin
cgot = $fgetc(file);
if (`verbose) $write("sync=%x='%c'\n", cgot,cgot);
sync = (cgot == cexp);
end
endfunction
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [2:0] mcu_mapper,
output mcu_rrq,
output mcu_write,
output mcu_wrq,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
// feature enable
output reg [7:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// debug
output DBG_mcu_nextaddr
);
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [2:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf;
reg MSU_RESET_OUT_BUF;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 1;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[2:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
dac_reset_out <= 1'b1; // reset by default value, see above
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
32'h4:
MSU_RESET_OUT_BUF <= 1'b0;
endcase
8'hec: // set DAC properties
begin
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
8'hed:
featurebits_out <= param_data;
8'hee:
region_out <= param_data[0];
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
MSU_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
parameter ST_RQ = 2'b01;
parameter ST_IDLE = 2'b10;
reg [1:0] rrq_state;
initial rrq_state = ST_IDLE;
reg mcu_rrq_r;
reg [1:0] wrq_state;
initial wrq_state = ST_IDLE;
reg mcu_wrq_r;
always @(posedge clk) begin
case(rrq_state)
ST_IDLE: begin
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq_r <= 1'b1;
rrq_state <= ST_RQ;
end else
rrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_rrq_r <= 1'b0;
rrq_state <= ST_IDLE;
end
endcase
end
always @(posedge clk) begin
case(wrq_state)
ST_IDLE: begin
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq_r <= 1'b1;
wrq_state <= ST_RQ;
end else
wrq_state <= ST_IDLE;
end
ST_RQ: begin
mcu_wrq_r <= 1'b0;
wrq_state <= ST_IDLE;
end
endcase
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_rrq = mcu_rrq_r;
assign mcu_wrq = mcu_wrq_r;
assign mcu_write = SD_DMA_STATUS
? (SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:02:30 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_33 ( CLK, EN, ENCLK, TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff1_shift_region_flag_out_0_, d_ff3_sign_out,
enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_31_, ITER_CONT_net3611507,
ITER_CONT_N5, ITER_CONT_N4, ITER_CONT_N3, d_ff5_data_out_net3611471,
reg_Z0_net3611471, reg_val_muxZ_2stage_net3611471,
reg_shift_y_net3611471, d_ff4_Xn_net3611471, d_ff4_Yn_net3611471,
d_ff4_Zn_net3611471, n154, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n531, n532, n533, n534, n535, n536,
n537, intadd_423_CI, intadd_423_n3, intadd_423_n2, intadd_423_n1,
intadd_424_CI, intadd_424_n3, intadd_424_n2, intadd_424_n1, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_33 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3611507), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3611471),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3611471), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3611471), .TE(1'b0) );
DFFRXLTS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n780), .QN(n606) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3611471), .RN(n782), .Q(d_ff1_shift_region_flag_out_0_),
.QN(n612) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3611471), .RN(n783), .QN(n608) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(reg_shift_y_net3611471), .RN(n783),
.Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n534), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n528), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n536), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3611471),
.RN(n787), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n525), .CK(reg_shift_y_net3611471), .RN(n780),
.Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n527), .CK(reg_shift_y_net3611471), .RN(n785),
.Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n531), .CK(reg_shift_y_net3611471), .RN(n784),
.Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n756), .CK(reg_shift_y_net3611471), .RN(n780),
.Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n533), .CK(reg_shift_y_net3611471), .RN(n788),
.Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n526), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n532), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n523), .CK(reg_shift_y_net3611471), .RN(n783), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n535), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n537), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n522), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n521), .CK(reg_shift_y_net3611471), .RN(n783), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n520), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n529), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3611471), .RN(n769),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3611471), .RN(n786),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3611471), .RN(n778),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3611471), .RN(n779),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3611471), .RN(n781),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3611471), .RN(n789),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3611471), .RN(n154),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3611471), .RN(n786),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3611471), .RN(n778),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3611471), .RN(n779),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3611471), .RN(
n788), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3611471), .RN(
n780), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3611471), .RN(
n788), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3611471), .RN(
n780), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3611471), .RN(
n783), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3611471), .RN(
n787), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3611471), .RN(
n782), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3611471), .RN(
n785), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3611471), .RN(
n784), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3611471), .RN(n787), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3611471), .RN(n787), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3611471), .RN(n784), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3611471), .RN(n782), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3611471), .RN(n787), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n783), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3611471),
.RN(n785), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n780), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3611471),
.RN(n782), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3611471), .RN(n783), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n787), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3611471),
.RN(n782), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3611471), .RN(n785), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3611471),
.RN(n789), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3611471), .RN(n154), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3611471),
.RN(n778), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3611471),
.RN(n789), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3611471), .RN(n154), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3611471),
.RN(n778), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n784), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3611471),
.RN(n780), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3611471), .RN(n788), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n787), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3611471),
.RN(n787), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3611471), .RN(n788), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n785), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3611471),
.RN(n784), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3611471), .RN(n780), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n783), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3611471), .RN(n788), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3611471), .RN(n787), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3611471), .RN(n786), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n778), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3611471), .RN(n779), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3611471), .RN(n781), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n789), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3611471), .RN(n778), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n779), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3611471), .RN(n781), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3611471), .RN(n789), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n786), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3611471), .RN(n778), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3611471), .RN(n779), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n781), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3611471), .RN(n789), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3611471), .RN(n786), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n778), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3611471), .RN(n779), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3611471), .RN(n781), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n789), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3611471), .RN(n786), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3611471), .RN(n778), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n788), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3611471), .RN(n775), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3611471), .RN(n767), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3611471), .RN(n768), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3611471), .RN(n775), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3611471), .RN(n784), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_X[23]), .QN(n614)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3611471), .RN(n774), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3611471), .RN(n774), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3611471), .RN(n776), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[28]), .QN(n762)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3611471), .RN(n771), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3611471), .RN(n773), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3611471), .RN(n777), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3611471), .RN(n777), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3611471), .RN(n777), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3611471),
.RN(n773), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3611471), .RN(n776), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3611471),
.RN(n773), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3611471), .RN(n765), .Q(data_output[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3611471),
.RN(n776), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3611471), .RN(n785), .Q(data_output[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3611471), .RN(n780), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3611471),
.RN(n775), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3611471), .RN(n784), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3611471),
.RN(n770), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3611471),
.RN(n771), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3611471), .RN(n771), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3611471),
.RN(n774), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n770), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3611471),
.RN(n776), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3611471), .RN(n771), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3611471),
.RN(n771), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3611471),
.RN(n777), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3611471), .RN(n774), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3611471), .RN(n772), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3611471), .RN(n771), .Q(data_output[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3611471), .RN(n777), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3611471), .RN(n774), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3611471), .RN(n770), .Q(data_output[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3611471), .RN(n776), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3611471), .RN(n770), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3611471), .RN(n772), .Q(data_output[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3611471), .RN(n776), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3611471), .RN(n773), .Q(data_output[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3611471), .RN(n771), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3611471), .RN(n772), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3611471), .RN(n773), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n772), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3611471), .RN(n780), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3611471), .RN(n767), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3611471), .RN(n775), .Q(data_output[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3611471), .RN(n767), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n784), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3611471), .RN(n785), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3611471), .RN(n773), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3611471), .RN(n774), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3611471), .RN(n774), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3611471), .RN(n770), .Q(data_output[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3611471), .RN(n773), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n771), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3611471), .RN(n772), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3611471), .RN(n770), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3611471), .RN(n769), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3611471), .RN(n776), .Q(data_output[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3611471), .RN(n769), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[23]), .QN(n613)
);
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3611471), .RN(n765), .Q(data_output[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3611471), .RN(n765), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3611471), .RN(n780), .Q(data_output[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3611471), .RN(n785), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3611471), .RN(n774), .Q(data_output[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3611471), .RN(n768), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Y[28]), .QN(n763)
);
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3611471), .RN(n769), .Q(data_output[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3611471), .RN(n775), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3611471), .RN(n777), .Q(data_output[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3611471), .RN(n765), .Q(d_ff_Yn[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3611471), .RN(n768), .Q(d_ff_Yn[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3611471), .RN(n768), .Q(data_output[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3611471), .RN(n768), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3611471), .RN(n768), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3611471), .RN(n767), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n767), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3611471), .RN(n765), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n765), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3611471), .RN(n154), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3611471), .RN(n790), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n764), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3611471), .RN(n766), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n790), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3611471), .RN(n764), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n766), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3611471),
.RN(n790), .Q(d_ff3_sign_out) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n790), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3611471), .RN(n764), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n519), .CK(clk), .RN(n781), .Q(
cont_var_out[1]), .QN(n760) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n518), .CK(clk), .RN(n786), .Q(
cont_var_out[0]), .QN(n759) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n758), .CK(ITER_CONT_net3611507), .RN(
n778), .Q(cont_iter_out[0]), .QN(n758) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3611507),
.RN(n781), .Q(cont_iter_out[3]), .QN(n757) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3611507),
.RN(n779), .Q(cont_iter_out[2]), .QN(n756) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n779), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n785), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n778), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n154), .Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3611471),
.RN(n784), .Q(d_ff1_operation_out) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n773), .Q(d_ff2_Y[29]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n154), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3611507),
.RN(n789), .Q(cont_iter_out[1]), .QN(n761) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n774), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n776), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n777), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n785), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n775), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n769), .Q(d_ff2_Y[24]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n788), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n154), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
ADDFX1TS intadd_423_U4 ( .A(n761), .B(d_ff2_X[24]), .CI(intadd_423_CI), .CO(
intadd_423_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_424_U4 ( .A(d_ff2_Y[24]), .B(n761), .CI(intadd_424_CI), .CO(
intadd_424_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_424_U3 ( .A(d_ff2_Y[25]), .B(n756), .CI(intadd_424_n3), .CO(
intadd_424_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_423_U3 ( .A(d_ff2_X[25]), .B(n756), .CI(intadd_423_n3), .CO(
intadd_423_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_423_U2 ( .A(d_ff2_X[26]), .B(n757), .CI(intadd_423_n2), .CO(
intadd_423_n1), .S(sh_exp_x[3]) );
ADDFX1TS intadd_424_U2 ( .A(d_ff2_Y[26]), .B(n757), .CI(intadd_424_n2), .CO(
intadd_424_n1), .S(sh_exp_y[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3611471), .RN(n768), .Q(d_ff2_Y[30]) );
AOI222X1TS U407 ( .A0(n739), .A1(d_ff2_X[30]), .B0(n691), .B1(d_ff2_Y[30]),
.C0(n741), .C1(d_ff2_Z[30]), .Y(n680) );
NAND3BX1TS U408 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(n628), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n721) );
CLKINVX6TS U409 ( .A(n708), .Y(n605) );
OR2X4TS U410 ( .A(cont_iter_out[2]), .B(n698), .Y(n615) );
OR2X2TS U411 ( .A(n760), .B(cont_var_out[0]), .Y(n659) );
CLKINVX6TS U412 ( .A(rst), .Y(n154) );
NAND2BXLTS U413 ( .AN(n611), .B(n635), .Y(n623) );
NAND3XLTS U414 ( .A(n721), .B(n694), .C(n697), .Y(n748) );
AOI222X1TS U415 ( .A0(n734), .A1(d_ff3_sh_y_out[0]), .B0(n691), .B1(
d_ff3_sh_x_out[0]), .C0(n741), .C1(d_ff3_LUT_out[0]), .Y(n682) );
AOI222X1TS U416 ( .A0(n739), .A1(d_ff3_sh_y_out[1]), .B0(n691), .B1(
d_ff3_sh_x_out[1]), .C0(n736), .C1(d_ff3_LUT_out[1]), .Y(n675) );
AOI222X1TS U417 ( .A0(n725), .A1(d_ff3_sh_y_out[2]), .B0(n691), .B1(
d_ff3_sh_x_out[2]), .C0(n741), .C1(d_ff3_LUT_out[2]), .Y(n676) );
AOI222X1TS U418 ( .A0(n734), .A1(d_ff3_sh_y_out[4]), .B0(n691), .B1(
d_ff3_sh_x_out[4]), .C0(n736), .C1(d_ff3_LUT_out[4]), .Y(n670) );
AOI222X1TS U419 ( .A0(n739), .A1(d_ff2_X[0]), .B0(n691), .B1(d_ff2_Y[0]),
.C0(n736), .C1(d_ff2_Z[0]), .Y(n684) );
AOI222X1TS U420 ( .A0(n734), .A1(d_ff2_X[11]), .B0(n687), .B1(d_ff2_Y[11]),
.C0(n741), .C1(d_ff2_Z[11]), .Y(n645) );
AOI222X1TS U421 ( .A0(n734), .A1(d_ff2_X[14]), .B0(n687), .B1(d_ff2_Y[14]),
.C0(n736), .C1(d_ff2_Z[14]), .Y(n643) );
AOI222X1TS U422 ( .A0(n739), .A1(d_ff2_X[16]), .B0(n687), .B1(d_ff2_Y[16]),
.C0(n690), .C1(d_ff2_Z[16]), .Y(n644) );
AOI222X1TS U423 ( .A0(n739), .A1(d_ff2_X[18]), .B0(n687), .B1(d_ff2_Y[18]),
.C0(n741), .C1(d_ff2_Z[18]), .Y(n646) );
AOI222X1TS U424 ( .A0(n734), .A1(d_ff2_X[20]), .B0(n687), .B1(d_ff2_Y[20]),
.C0(n736), .C1(d_ff2_Z[20]), .Y(n652) );
AOI222X1TS U425 ( .A0(n725), .A1(d_ff2_X[22]), .B0(n687), .B1(d_ff2_Y[22]),
.C0(n690), .C1(d_ff2_Z[22]), .Y(n651) );
AOI222X1TS U426 ( .A0(n739), .A1(d_ff2_X[24]), .B0(n691), .B1(d_ff2_Y[24]),
.C0(n741), .C1(d_ff2_Z[24]), .Y(n672) );
AOI222X1TS U427 ( .A0(n734), .A1(d_ff2_X[25]), .B0(n691), .B1(d_ff2_Y[25]),
.C0(n690), .C1(d_ff2_Z[25]), .Y(n689) );
AOI222X1TS U428 ( .A0(n725), .A1(d_ff2_X[26]), .B0(n691), .B1(d_ff2_Y[26]),
.C0(n690), .C1(d_ff2_Z[26]), .Y(n693) );
AOI222X1TS U429 ( .A0(n739), .A1(d_ff2_X[27]), .B0(n691), .B1(d_ff2_Y[27]),
.C0(n736), .C1(d_ff2_Z[27]), .Y(n685) );
AOI222X1TS U430 ( .A0(n734), .A1(d_ff2_X[29]), .B0(n691), .B1(d_ff2_Y[29]),
.C0(n690), .C1(d_ff2_Z[29]), .Y(n673) );
OR4X2TS U431 ( .A(n611), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(
inst_CORDIC_FSM_v3_state_reg[0]), .D(inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n607) );
INVX2TS U432 ( .A(n607), .Y(n609) );
NAND3X2TS U433 ( .A(n757), .B(n758), .C(n761), .Y(n698) );
NOR2X2TS U434 ( .A(n697), .B(n659), .Y(enab_d_ff4_Zn) );
BUFX4TS U435 ( .A(n766), .Y(n768) );
BUFX6TS U436 ( .A(n154), .Y(n769) );
BUFX4TS U437 ( .A(n771), .Y(n788) );
BUFX4TS U438 ( .A(n789), .Y(n785) );
BUFX4TS U439 ( .A(n781), .Y(n784) );
BUFX4TS U440 ( .A(n779), .Y(n780) );
BUFX4TS U441 ( .A(n769), .Y(n776) );
BUFX4TS U442 ( .A(n769), .Y(n777) );
BUFX4TS U443 ( .A(n769), .Y(n774) );
BUFX4TS U444 ( .A(n770), .Y(n773) );
NOR2X4TS U445 ( .A(n756), .B(n757), .Y(n742) );
BUFX6TS U446 ( .A(n642), .Y(n741) );
BUFX6TS U447 ( .A(n642), .Y(n690) );
BUFX4TS U448 ( .A(n642), .Y(n736) );
INVX2TS U449 ( .A(n608), .Y(n610) );
INVX2TS U450 ( .A(n606), .Y(n611) );
CLKINVX3TS U451 ( .A(n615), .Y(n710) );
CLKINVX6TS U452 ( .A(n708), .Y(n707) );
INVX2TS U453 ( .A(n708), .Y(n706) );
INVX4TS U454 ( .A(n696), .Y(n692) );
CLKINVX6TS U455 ( .A(n696), .Y(n734) );
CLKINVX3TS U456 ( .A(n696), .Y(n725) );
CLKINVX6TS U457 ( .A(n696), .Y(n739) );
CLKINVX6TS U458 ( .A(n659), .Y(n738) );
CLKINVX6TS U459 ( .A(n659), .Y(n733) );
AOI222X1TS U460 ( .A0(n734), .A1(d_ff2_X[28]), .B0(n691), .B1(d_ff2_Y[28]),
.C0(n690), .C1(d_ff2_Z[28]), .Y(n686) );
INVX3TS U461 ( .A(n659), .Y(n691) );
NOR3BX2TS U462 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n621), .Y(ready_cordic) );
NOR3BX2TS U463 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n621), .Y(
inst_CORDIC_FSM_v3_state_next[3]) );
NOR2X4TS U464 ( .A(n758), .B(n761), .Y(n724) );
BUFX4TS U465 ( .A(n764), .Y(n765) );
BUFX4TS U466 ( .A(n790), .Y(n767) );
BUFX3TS U467 ( .A(n154), .Y(n790) );
OAI32X4TS U468 ( .A0(n612), .A1(d_ff1_operation_out), .A2(n610), .B0(
d_ff1_shift_region_flag_out_0_), .B1(n701), .Y(n702) );
AOI21X2TS U469 ( .A0(cont_iter_out[2]), .A1(n757), .B0(n616), .Y(n637) );
NAND4BXLTS U470 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(n611), .C(n636),
.D(n635), .Y(n638) );
INVX4TS U471 ( .A(n714), .Y(n713) );
CLKINVX3TS U472 ( .A(n700), .Y(n714) );
INVX3TS U473 ( .A(n659), .Y(n687) );
NOR2XLTS U474 ( .A(n697), .B(n696), .Y(enab_d_ff4_Yn) );
OR2X1TS U475 ( .A(d_ff_Xn[28]), .B(n710), .Y(first_mux_X[28]) );
OR2X1TS U476 ( .A(d_ff_Xn[20]), .B(n706), .Y(first_mux_X[20]) );
OR2X1TS U477 ( .A(d_ff_Xn[14]), .B(n605), .Y(first_mux_X[14]) );
OR2X1TS U478 ( .A(d_ff_Xn[1]), .B(n707), .Y(first_mux_X[1]) );
OAI21XLTS U479 ( .A0(n755), .A1(n762), .B0(n754), .Y(sh_exp_x[5]) );
OAI21XLTS U480 ( .A0(cont_iter_out[0]), .A1(n537), .B0(n747), .Y(n521) );
OAI21XLTS U481 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n637), .Y(n534) );
NOR2X1TS U482 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .Y(n622) );
NAND2X1TS U483 ( .A(n609), .B(n622), .Y(n621) );
INVX2TS U484 ( .A(ready_add_subt), .Y(n697) );
NAND2X1TS U485 ( .A(n724), .B(n756), .Y(n630) );
OAI31X1TS U486 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n756),
.B0(n630), .Y(n528) );
INVX2TS U487 ( .A(n742), .Y(n537) );
OAI31X4TS U488 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n758),
.B0(n537), .Y(n744) );
NAND2X1TS U489 ( .A(n756), .B(cont_iter_out[3]), .Y(n631) );
OAI21XLTS U490 ( .A0(n761), .A1(n744), .B0(n631), .Y(n532) );
INVX2TS U491 ( .A(n631), .Y(n616) );
NAND2X1TS U492 ( .A(n537), .B(cont_iter_out[0]), .Y(n747) );
INVX2TS U493 ( .A(n747), .Y(n746) );
NOR2X1TS U494 ( .A(n616), .B(n746), .Y(n743) );
OAI211X1TS U495 ( .A0(cont_iter_out[3]), .A1(n758), .B0(n756), .C0(n761),
.Y(n745) );
OAI21XLTS U496 ( .A0(n743), .A1(n761), .B0(n745), .Y(n526) );
BUFX3TS U497 ( .A(n154), .Y(n775) );
BUFX3TS U498 ( .A(n769), .Y(n772) );
BUFX3TS U499 ( .A(n769), .Y(n771) );
BUFX3TS U500 ( .A(n790), .Y(n778) );
BUFX3TS U501 ( .A(n764), .Y(n779) );
BUFX3TS U502 ( .A(n770), .Y(n781) );
BUFX3TS U503 ( .A(n772), .Y(n782) );
BUFX3TS U504 ( .A(n771), .Y(n789) );
BUFX3TS U505 ( .A(n154), .Y(n764) );
BUFX3TS U506 ( .A(n154), .Y(n766) );
BUFX3TS U507 ( .A(n772), .Y(n786) );
BUFX3TS U508 ( .A(n769), .Y(n770) );
BUFX3TS U509 ( .A(n766), .Y(n783) );
BUFX3TS U510 ( .A(n769), .Y(n787) );
BUFX3TS U511 ( .A(n615), .Y(n709) );
INVX4TS U512 ( .A(n709), .Y(n718) );
BUFX3TS U513 ( .A(n615), .Y(n708) );
AO22XLTS U514 ( .A0(n718), .A1(d_ff1_Z[0]), .B0(n708), .B1(d_ff_Zn[0]), .Y(
first_mux_Z[0]) );
AO22XLTS U515 ( .A0(n718), .A1(d_ff1_Z[29]), .B0(n708), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U516 ( .A0(n718), .A1(d_ff1_Z[30]), .B0(n708), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U517 ( .A0(n718), .A1(d_ff1_Z[31]), .B0(n708), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U518 ( .A0(n718), .A1(d_ff1_Z[28]), .B0(n615), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
NAND2X1TS U519 ( .A(n637), .B(n747), .Y(n523) );
OR2X2TS U520 ( .A(n759), .B(cont_var_out[1]), .Y(n696) );
AOI22X1TS U521 ( .A0(n739), .A1(d_ff3_sh_y_out[20]), .B0(n733), .B1(
d_ff3_sh_x_out[20]), .Y(n617) );
NAND2X1TS U522 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n720) );
INVX2TS U523 ( .A(n720), .Y(n642) );
NAND2X1TS U524 ( .A(n741), .B(d_ff3_LUT_out[15]), .Y(n619) );
NAND2X1TS U525 ( .A(n617), .B(n619), .Y(add_subt_dataB[20]) );
AOI22X1TS U526 ( .A0(n734), .A1(d_ff3_sh_y_out[15]), .B0(n733), .B1(
d_ff3_sh_x_out[15]), .Y(n618) );
NAND2X1TS U527 ( .A(n618), .B(n619), .Y(add_subt_dataB[15]) );
AOI22X1TS U528 ( .A0(n739), .A1(d_ff3_sh_y_out[17]), .B0(n733), .B1(
d_ff3_sh_x_out[17]), .Y(n620) );
NAND2X1TS U529 ( .A(n620), .B(n619), .Y(add_subt_dataB[17]) );
NOR3BX1TS U530 ( .AN(n622), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n635) );
NOR2X1TS U531 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n636) );
NAND3BXLTS U532 ( .AN(n623), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(n636),
.Y(n633) );
NOR2X1TS U533 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n623), .Y(n629) );
NAND3BX1TS U534 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n629), .Y(n719) );
NAND2X1TS U535 ( .A(n633), .B(n719), .Y(enab_d_ff_RB1) );
AOI22X1TS U536 ( .A0(n725), .A1(d_ff3_sh_y_out[28]), .B0(n733), .B1(
d_ff3_sh_x_out[28]), .Y(n624) );
NAND2X1TS U537 ( .A(n690), .B(d_ff3_LUT_out[27]), .Y(n626) );
NAND2X1TS U538 ( .A(n624), .B(n626), .Y(add_subt_dataB[28]) );
AOI22X1TS U539 ( .A0(n734), .A1(d_ff3_sh_y_out[29]), .B0(n733), .B1(
d_ff3_sh_x_out[29]), .Y(n625) );
NAND2X1TS U540 ( .A(n625), .B(n626), .Y(add_subt_dataB[29]) );
AOI22X1TS U541 ( .A0(n739), .A1(d_ff3_sh_y_out[27]), .B0(n733), .B1(
d_ff3_sh_x_out[27]), .Y(n627) );
NAND2X1TS U542 ( .A(n627), .B(n626), .Y(add_subt_dataB[27]) );
NOR3BX1TS U543 ( .AN(n609), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n628) );
NAND3BX1TS U544 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n628), .Y(n694) );
INVX2TS U545 ( .A(n694), .Y(enab_cont_iter) );
NAND3BX1TS U546 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n629), .Y(n722) );
NAND2X1TS U547 ( .A(n721), .B(n722), .Y(beg_add_subt) );
NAND2X1TS U548 ( .A(n613), .B(cont_iter_out[0]), .Y(intadd_424_CI) );
OAI21XLTS U549 ( .A0(cont_iter_out[0]), .A1(n613), .B0(intadd_424_CI), .Y(
sh_exp_y[0]) );
NAND2X1TS U550 ( .A(n614), .B(cont_iter_out[0]), .Y(intadd_423_CI) );
OAI21XLTS U551 ( .A0(cont_iter_out[0]), .A1(n614), .B0(intadd_423_CI), .Y(
sh_exp_x[0]) );
NOR2X1TS U552 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n632) );
NOR2XLTS U553 ( .A(n724), .B(n632), .Y(ITER_CONT_N3) );
OAI21XLTS U554 ( .A0(n742), .A1(cont_iter_out[1]), .B0(n637), .Y(n536) );
OAI211XLTS U555 ( .A0(n632), .A1(n631), .B0(n630), .C0(n698), .Y(n527) );
NOR2X1TS U556 ( .A(d_ff2_Y[27]), .B(intadd_424_n1), .Y(n752) );
OR3X1TS U557 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_424_n1), .Y(n751)
);
OAI21XLTS U558 ( .A0(n752), .A1(n763), .B0(n751), .Y(sh_exp_y[5]) );
NOR2X1TS U559 ( .A(d_ff2_X[27]), .B(intadd_423_n1), .Y(n755) );
OR3X1TS U560 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_423_n1), .Y(n754)
);
NAND2X1TS U561 ( .A(cont_iter_out[2]), .B(n724), .Y(n723) );
CLKAND2X2TS U562 ( .A(n723), .B(n757), .Y(n529) );
NOR2X1TS U563 ( .A(n757), .B(n723), .Y(n634) );
NOR2XLTS U564 ( .A(n634), .B(n529), .Y(ITER_CONT_N5) );
OR2X1TS U565 ( .A(d_ff_Xn[24]), .B(n710), .Y(first_mux_X[24]) );
OR2X1TS U566 ( .A(d_ff_Xn[27]), .B(n710), .Y(first_mux_X[27]) );
OR2X1TS U567 ( .A(d_ff_Xn[25]), .B(n710), .Y(first_mux_X[25]) );
OR2X1TS U568 ( .A(d_ff_Xn[29]), .B(n710), .Y(first_mux_X[29]) );
OR2X1TS U569 ( .A(d_ff_Xn[26]), .B(n710), .Y(first_mux_X[26]) );
OR2X1TS U570 ( .A(d_ff_Xn[7]), .B(n710), .Y(first_mux_X[7]) );
OR2X1TS U571 ( .A(d_ff_Xn[13]), .B(n710), .Y(first_mux_X[13]) );
OAI21XLTS U572 ( .A0(n634), .A1(n694), .B0(n633), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OR2X1TS U573 ( .A(d_ff_Xn[2]), .B(n707), .Y(first_mux_X[2]) );
OR2X1TS U574 ( .A(d_ff_Xn[5]), .B(n706), .Y(first_mux_X[5]) );
OR2X1TS U575 ( .A(d_ff_Xn[17]), .B(n605), .Y(first_mux_X[17]) );
OR2X1TS U576 ( .A(d_ff_Xn[3]), .B(n707), .Y(first_mux_X[3]) );
OR2X1TS U577 ( .A(d_ff_Xn[10]), .B(n707), .Y(first_mux_X[10]) );
OR2X1TS U578 ( .A(d_ff_Xn[6]), .B(n706), .Y(first_mux_X[6]) );
OR2X1TS U579 ( .A(d_ff_Xn[16]), .B(n605), .Y(first_mux_X[16]) );
OR2X1TS U580 ( .A(d_ff_Xn[12]), .B(n707), .Y(first_mux_X[12]) );
OR2X1TS U581 ( .A(d_ff_Xn[19]), .B(n707), .Y(first_mux_X[19]) );
OAI21XLTS U582 ( .A0(n741), .A1(n721), .B0(n638), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
OAI21X1TS U583 ( .A0(n742), .A1(n761), .B0(n637), .Y(n535) );
OR2X1TS U584 ( .A(n535), .B(n746), .Y(n522) );
INVX2TS U585 ( .A(ready_cordic), .Y(n705) );
NAND3XLTS U586 ( .A(enab_cont_iter), .B(n742), .C(n724), .Y(n704) );
OAI21XLTS U587 ( .A0(ack_cordic), .A1(n705), .B0(n704), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
INVX2TS U588 ( .A(n638), .Y(enab_RB3) );
NOR4X1TS U589 ( .A(enab_cont_iter), .B(enab_RB3), .C(enab_d_ff_RB1), .D(
beg_add_subt), .Y(n640) );
INVX2TS U590 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .Y(n639) );
AOI32X1TS U591 ( .A0(n640), .A1(n705), .A2(n639), .B0(ready_cordic), .B1(
ack_cordic), .Y(n641) );
OAI21XLTS U592 ( .A0(beg_fsm_cordic), .A1(n719), .B0(n641), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
INVX2TS U593 ( .A(n643), .Y(add_subt_dataA[14]) );
INVX2TS U594 ( .A(n644), .Y(add_subt_dataA[16]) );
INVX2TS U595 ( .A(n645), .Y(add_subt_dataA[11]) );
INVX2TS U596 ( .A(n646), .Y(add_subt_dataA[18]) );
AOI222X1TS U597 ( .A0(n734), .A1(d_ff2_X[4]), .B0(n738), .B1(d_ff2_Y[4]),
.C0(n741), .C1(d_ff2_Z[4]), .Y(n647) );
INVX2TS U598 ( .A(n647), .Y(add_subt_dataA[4]) );
AOI222X1TS U599 ( .A0(n739), .A1(d_ff2_X[2]), .B0(n738), .B1(d_ff2_Y[2]),
.C0(n736), .C1(d_ff2_Z[2]), .Y(n648) );
INVX2TS U600 ( .A(n648), .Y(add_subt_dataA[2]) );
AOI222X1TS U601 ( .A0(n734), .A1(d_ff2_X[9]), .B0(n738), .B1(d_ff2_Y[9]),
.C0(n690), .C1(d_ff2_Z[9]), .Y(n649) );
INVX2TS U602 ( .A(n649), .Y(add_subt_dataA[9]) );
AOI222X1TS U603 ( .A0(n739), .A1(d_ff2_X[10]), .B0(n738), .B1(d_ff2_Y[10]),
.C0(n690), .C1(d_ff2_Z[10]), .Y(n650) );
INVX2TS U604 ( .A(n650), .Y(add_subt_dataA[10]) );
INVX2TS U605 ( .A(n651), .Y(add_subt_dataA[22]) );
INVX2TS U606 ( .A(n652), .Y(add_subt_dataA[20]) );
AOI222X1TS U607 ( .A0(n734), .A1(d_ff2_X[1]), .B0(n738), .B1(d_ff2_Y[1]),
.C0(n741), .C1(d_ff2_Z[1]), .Y(n653) );
INVX2TS U608 ( .A(n653), .Y(add_subt_dataA[1]) );
AOI222X1TS U609 ( .A0(n725), .A1(d_ff2_X[7]), .B0(n738), .B1(d_ff2_Y[7]),
.C0(n736), .C1(d_ff2_Z[7]), .Y(n654) );
INVX2TS U610 ( .A(n654), .Y(add_subt_dataA[7]) );
AOI222X1TS U611 ( .A0(n739), .A1(d_ff2_X[6]), .B0(n738), .B1(d_ff2_Y[6]),
.C0(n736), .C1(d_ff2_Z[6]), .Y(n655) );
INVX2TS U612 ( .A(n655), .Y(add_subt_dataA[6]) );
AOI222X1TS U613 ( .A0(n734), .A1(d_ff2_X[3]), .B0(n738), .B1(d_ff2_Y[3]),
.C0(n736), .C1(d_ff2_Z[3]), .Y(n656) );
INVX2TS U614 ( .A(n656), .Y(add_subt_dataA[3]) );
AOI222X1TS U615 ( .A0(n725), .A1(d_ff2_X[8]), .B0(n738), .B1(d_ff2_Y[8]),
.C0(n690), .C1(d_ff2_Z[8]), .Y(n657) );
INVX2TS U616 ( .A(n657), .Y(add_subt_dataA[8]) );
AOI222X1TS U617 ( .A0(n739), .A1(d_ff2_X[5]), .B0(n738), .B1(d_ff2_Y[5]),
.C0(n690), .C1(d_ff2_Z[5]), .Y(n658) );
INVX2TS U618 ( .A(n658), .Y(add_subt_dataA[5]) );
AOI222X1TS U619 ( .A0(n692), .A1(d_ff3_sh_y_out[24]), .B0(n738), .B1(
d_ff3_sh_x_out[24]), .C0(n690), .C1(d_ff3_LUT_out[24]), .Y(n660) );
INVX2TS U620 ( .A(n660), .Y(add_subt_dataB[24]) );
AOI222X1TS U621 ( .A0(n692), .A1(d_ff3_sh_y_out[21]), .B0(n738), .B1(
d_ff3_sh_x_out[21]), .C0(n741), .C1(d_ff3_LUT_out[21]), .Y(n661) );
INVX2TS U622 ( .A(n661), .Y(add_subt_dataB[21]) );
AOI222X1TS U623 ( .A0(n692), .A1(d_ff3_sh_y_out[9]), .B0(n738), .B1(
d_ff3_sh_x_out[9]), .C0(n736), .C1(d_ff3_LUT_out[9]), .Y(n662) );
INVX2TS U624 ( .A(n662), .Y(add_subt_dataB[9]) );
AOI222X1TS U625 ( .A0(n692), .A1(d_ff3_sh_y_out[26]), .B0(n738), .B1(
d_ff3_sh_x_out[26]), .C0(n741), .C1(d_ff3_LUT_out[26]), .Y(n663) );
INVX2TS U626 ( .A(n663), .Y(add_subt_dataB[26]) );
AOI222X1TS U627 ( .A0(n692), .A1(d_ff3_sh_y_out[6]), .B0(n738), .B1(
d_ff3_sh_x_out[6]), .C0(n690), .C1(d_ff3_LUT_out[6]), .Y(n664) );
INVX2TS U628 ( .A(n664), .Y(add_subt_dataB[6]) );
AOI222X1TS U629 ( .A0(n692), .A1(d_ff3_sh_y_out[23]), .B0(n738), .B1(
d_ff3_sh_x_out[23]), .C0(n741), .C1(d_ff3_LUT_out[23]), .Y(n665) );
INVX2TS U630 ( .A(n665), .Y(add_subt_dataB[23]) );
AOI222X1TS U631 ( .A0(n692), .A1(d_ff3_sh_y_out[10]), .B0(n738), .B1(
d_ff3_sh_x_out[10]), .C0(n736), .C1(d_ff3_LUT_out[10]), .Y(n666) );
INVX2TS U632 ( .A(n666), .Y(add_subt_dataB[10]) );
AOI222X1TS U633 ( .A0(n692), .A1(d_ff3_sh_y_out[12]), .B0(n738), .B1(
d_ff3_sh_x_out[12]), .C0(n690), .C1(d_ff3_LUT_out[12]), .Y(n667) );
INVX2TS U634 ( .A(n667), .Y(add_subt_dataB[12]) );
AOI222X1TS U635 ( .A0(n692), .A1(d_ff3_sh_y_out[25]), .B0(n738), .B1(
d_ff3_sh_x_out[25]), .C0(n741), .C1(d_ff3_LUT_out[25]), .Y(n668) );
INVX2TS U636 ( .A(n668), .Y(add_subt_dataB[25]) );
AOI222X1TS U637 ( .A0(n692), .A1(d_ff3_sh_y_out[8]), .B0(n738), .B1(
d_ff3_sh_x_out[8]), .C0(n736), .C1(d_ff3_LUT_out[8]), .Y(n669) );
INVX2TS U638 ( .A(n669), .Y(add_subt_dataB[8]) );
INVX2TS U639 ( .A(n670), .Y(add_subt_dataB[4]) );
AOI222X1TS U640 ( .A0(n692), .A1(d_ff2_X[19]), .B0(n687), .B1(d_ff2_Y[19]),
.C0(n736), .C1(d_ff2_Z[19]), .Y(n671) );
INVX2TS U641 ( .A(n671), .Y(add_subt_dataA[19]) );
INVX2TS U642 ( .A(n672), .Y(add_subt_dataA[24]) );
INVX2TS U643 ( .A(n673), .Y(add_subt_dataA[29]) );
AOI222X1TS U644 ( .A0(n692), .A1(d_ff2_X[23]), .B0(n687), .B1(d_ff2_Y[23]),
.C0(n741), .C1(d_ff2_Z[23]), .Y(n674) );
INVX2TS U645 ( .A(n674), .Y(add_subt_dataA[23]) );
INVX2TS U646 ( .A(n675), .Y(add_subt_dataB[1]) );
INVX2TS U647 ( .A(n676), .Y(add_subt_dataB[2]) );
AOI222X1TS U648 ( .A0(n692), .A1(d_ff2_X[13]), .B0(n687), .B1(d_ff2_Y[13]),
.C0(n741), .C1(d_ff2_Z[13]), .Y(n677) );
INVX2TS U649 ( .A(n677), .Y(add_subt_dataA[13]) );
AOI222X1TS U650 ( .A0(n692), .A1(d_ff2_X[12]), .B0(n687), .B1(d_ff2_Y[12]),
.C0(n690), .C1(d_ff2_Z[12]), .Y(n678) );
INVX2TS U651 ( .A(n678), .Y(add_subt_dataA[12]) );
AOI222X1TS U652 ( .A0(n739), .A1(d_ff2_X[31]), .B0(n691), .B1(d_ff2_Y[31]),
.C0(n736), .C1(d_ff2_Z[31]), .Y(n679) );
INVX2TS U653 ( .A(n679), .Y(add_subt_dataA[31]) );
INVX2TS U654 ( .A(n680), .Y(add_subt_dataA[30]) );
AOI222X1TS U655 ( .A0(n692), .A1(d_ff2_X[15]), .B0(n687), .B1(d_ff2_Y[15]),
.C0(n736), .C1(d_ff2_Z[15]), .Y(n681) );
INVX2TS U656 ( .A(n681), .Y(add_subt_dataA[15]) );
INVX2TS U657 ( .A(n682), .Y(add_subt_dataB[0]) );
AOI222X1TS U658 ( .A0(n692), .A1(d_ff2_X[17]), .B0(n687), .B1(d_ff2_Y[17]),
.C0(n741), .C1(d_ff2_Z[17]), .Y(n683) );
INVX2TS U659 ( .A(n683), .Y(add_subt_dataA[17]) );
INVX2TS U660 ( .A(n684), .Y(add_subt_dataA[0]) );
INVX2TS U661 ( .A(n685), .Y(add_subt_dataA[27]) );
INVX2TS U662 ( .A(n686), .Y(add_subt_dataA[28]) );
AOI222X1TS U663 ( .A0(n725), .A1(d_ff2_X[21]), .B0(n687), .B1(d_ff2_Y[21]),
.C0(n690), .C1(d_ff2_Z[21]), .Y(n688) );
INVX2TS U664 ( .A(n688), .Y(add_subt_dataA[21]) );
INVX2TS U665 ( .A(n689), .Y(add_subt_dataA[25]) );
INVX2TS U666 ( .A(n693), .Y(add_subt_dataA[26]) );
INVX2TS U667 ( .A(n748), .Y(n749) );
NAND2X1TS U668 ( .A(n749), .B(cont_var_out[1]), .Y(n695) );
OAI211XLTS U669 ( .A0(n749), .A1(n696), .B0(n659), .C0(n695), .Y(n519) );
OAI21XLTS U670 ( .A0(n742), .A1(n761), .B0(n744), .Y(n531) );
NOR3XLTS U671 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n697), .Y(
enab_d_ff4_Xn) );
AOI32X1TS U673 ( .A0(cont_iter_out[3]), .A1(n698), .A2(n761), .B0(
cont_iter_out[2]), .B1(n698), .Y(data_out_LUT[4]) );
OAI22X1TS U674 ( .A0(cont_iter_out[3]), .A1(n723), .B0(cont_iter_out[2]),
.B1(n724), .Y(data_out_LUT[25]) );
NAND2X1TS U675 ( .A(d_ff1_operation_out), .B(n610), .Y(n701) );
OAI21XLTS U676 ( .A0(d_ff1_operation_out), .A1(n610), .B0(n701), .Y(n699) );
XOR2X1TS U677 ( .A(n612), .B(n699), .Y(n700) );
BUFX3TS U678 ( .A(n714), .Y(n712) );
AOI22X1TS U679 ( .A0(n715), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n712),
.Y(n703) );
XNOR2X1TS U680 ( .A(n703), .B(n702), .Y(fmtted_Result_31_) );
NAND2X1TS U681 ( .A(n705), .B(n704), .Y(enab_d_ff5_data_out) );
NOR2BX1TS U682 ( .AN(d_ff_Yn[0]), .B(n605), .Y(first_mux_Y[0]) );
NOR2BX1TS U683 ( .AN(d_ff_Yn[1]), .B(n706), .Y(first_mux_Y[1]) );
NOR2BX1TS U684 ( .AN(d_ff_Yn[2]), .B(n707), .Y(first_mux_Y[2]) );
NOR2BX1TS U685 ( .AN(d_ff_Yn[3]), .B(n707), .Y(first_mux_Y[3]) );
NOR2BX1TS U686 ( .AN(d_ff_Yn[4]), .B(n605), .Y(first_mux_Y[4]) );
NOR2BX1TS U687 ( .AN(d_ff_Yn[5]), .B(n706), .Y(first_mux_Y[5]) );
NOR2BX1TS U688 ( .AN(d_ff_Yn[6]), .B(n707), .Y(first_mux_Y[6]) );
NOR2BX1TS U689 ( .AN(d_ff_Yn[7]), .B(n707), .Y(first_mux_Y[7]) );
NOR2BX1TS U690 ( .AN(d_ff_Yn[8]), .B(n706), .Y(first_mux_Y[8]) );
NOR2BX1TS U691 ( .AN(d_ff_Yn[9]), .B(n605), .Y(first_mux_Y[9]) );
NOR2BX1TS U692 ( .AN(d_ff_Yn[10]), .B(n707), .Y(first_mux_Y[10]) );
NOR2BX1TS U693 ( .AN(d_ff_Yn[11]), .B(n707), .Y(first_mux_Y[11]) );
NOR2BX1TS U694 ( .AN(d_ff_Yn[12]), .B(n707), .Y(first_mux_Y[12]) );
NOR2BX1TS U695 ( .AN(d_ff_Yn[13]), .B(n605), .Y(first_mux_Y[13]) );
NOR2BX1TS U696 ( .AN(d_ff_Yn[14]), .B(n706), .Y(first_mux_Y[14]) );
NOR2BX1TS U697 ( .AN(d_ff_Yn[15]), .B(n707), .Y(first_mux_Y[15]) );
NOR2BX1TS U698 ( .AN(d_ff_Yn[16]), .B(n707), .Y(first_mux_Y[16]) );
NOR2BX1TS U699 ( .AN(d_ff_Yn[17]), .B(n605), .Y(first_mux_Y[17]) );
NOR2BX1TS U700 ( .AN(d_ff_Yn[18]), .B(n706), .Y(first_mux_Y[18]) );
NOR2BX1TS U701 ( .AN(d_ff_Yn[19]), .B(n707), .Y(first_mux_Y[19]) );
NOR2BX1TS U702 ( .AN(d_ff_Yn[20]), .B(n707), .Y(first_mux_Y[20]) );
NOR2BX1TS U703 ( .AN(d_ff_Yn[21]), .B(n706), .Y(first_mux_Y[21]) );
NOR2BX1TS U704 ( .AN(d_ff_Yn[22]), .B(n605), .Y(first_mux_Y[22]) );
NOR2BX1TS U705 ( .AN(d_ff_Yn[23]), .B(n707), .Y(first_mux_Y[23]) );
NOR2BX1TS U706 ( .AN(d_ff_Yn[24]), .B(n605), .Y(first_mux_Y[24]) );
NOR2BX1TS U707 ( .AN(d_ff_Yn[25]), .B(n605), .Y(first_mux_Y[25]) );
NOR2BX1TS U708 ( .AN(d_ff_Yn[26]), .B(n605), .Y(first_mux_Y[26]) );
NOR2BX1TS U709 ( .AN(d_ff_Yn[27]), .B(n605), .Y(first_mux_Y[27]) );
NOR2BX1TS U710 ( .AN(d_ff_Yn[28]), .B(n605), .Y(first_mux_Y[28]) );
NOR2BX1TS U711 ( .AN(d_ff_Yn[29]), .B(n605), .Y(first_mux_Y[29]) );
NOR2BX1TS U712 ( .AN(d_ff_Yn[30]), .B(n605), .Y(first_mux_Y[30]) );
NOR2BX1TS U713 ( .AN(d_ff_Yn[31]), .B(n605), .Y(first_mux_Y[31]) );
INVX4TS U714 ( .A(n709), .Y(n711) );
AO22XLTS U715 ( .A0(n718), .A1(d_ff1_Z[1]), .B0(n615), .B1(d_ff_Zn[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U716 ( .A0(n605), .A1(d_ff1_Z[2]), .B0(n708), .B1(d_ff_Zn[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U717 ( .A0(n718), .A1(d_ff1_Z[3]), .B0(n708), .B1(d_ff_Zn[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U718 ( .A0(n718), .A1(d_ff1_Z[4]), .B0(n708), .B1(d_ff_Zn[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U719 ( .A0(n718), .A1(d_ff1_Z[5]), .B0(n708), .B1(d_ff_Zn[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U720 ( .A0(n718), .A1(d_ff1_Z[6]), .B0(n709), .B1(d_ff_Zn[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U721 ( .A0(n718), .A1(d_ff1_Z[7]), .B0(n709), .B1(d_ff_Zn[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U722 ( .A0(n711), .A1(d_ff1_Z[8]), .B0(n709), .B1(d_ff_Zn[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U723 ( .A0(n711), .A1(d_ff1_Z[9]), .B0(n709), .B1(d_ff_Zn[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U724 ( .A0(n711), .A1(d_ff1_Z[10]), .B0(n709), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U725 ( .A0(n711), .A1(d_ff1_Z[11]), .B0(n709), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U726 ( .A0(n711), .A1(d_ff1_Z[12]), .B0(n709), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U727 ( .A0(n711), .A1(d_ff1_Z[13]), .B0(n709), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U728 ( .A0(n711), .A1(d_ff1_Z[14]), .B0(n709), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U729 ( .A0(n718), .A1(d_ff1_Z[15]), .B0(n709), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U730 ( .A0(n718), .A1(d_ff1_Z[16]), .B0(n709), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U731 ( .A0(n718), .A1(d_ff1_Z[17]), .B0(n615), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U732 ( .A0(n710), .A1(d_ff1_Z[18]), .B0(n615), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U733 ( .A0(n718), .A1(d_ff1_Z[19]), .B0(n615), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U734 ( .A0(n718), .A1(d_ff1_Z[20]), .B0(n615), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U735 ( .A0(n710), .A1(d_ff1_Z[21]), .B0(n615), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U736 ( .A0(n718), .A1(d_ff1_Z[22]), .B0(n615), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U737 ( .A0(n710), .A1(d_ff1_Z[23]), .B0(n615), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U738 ( .A0(n718), .A1(d_ff1_Z[24]), .B0(n615), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U739 ( .A0(n710), .A1(d_ff1_Z[25]), .B0(n615), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U740 ( .A0(n711), .A1(d_ff1_Z[26]), .B0(n615), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U741 ( .A0(n711), .A1(d_ff1_Z[27]), .B0(n615), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
BUFX3TS U742 ( .A(n712), .Y(n716) );
AO22XLTS U743 ( .A0(n713), .A1(d_ff_Yn[0]), .B0(n716), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
AO22XLTS U744 ( .A0(n713), .A1(d_ff_Yn[1]), .B0(n712), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U745 ( .A0(n713), .A1(d_ff_Yn[2]), .B0(n712), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U746 ( .A0(n713), .A1(d_ff_Yn[3]), .B0(n712), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U747 ( .A0(n713), .A1(d_ff_Yn[4]), .B0(n712), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U748 ( .A0(n713), .A1(d_ff_Yn[5]), .B0(n712), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U749 ( .A0(n713), .A1(d_ff_Yn[6]), .B0(n712), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U750 ( .A0(n713), .A1(d_ff_Yn[7]), .B0(n712), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U751 ( .A0(n713), .A1(d_ff_Yn[8]), .B0(n712), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U752 ( .A0(n713), .A1(d_ff_Yn[9]), .B0(n712), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U753 ( .A0(n713), .A1(d_ff_Yn[10]), .B0(n712), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U754 ( .A0(n713), .A1(d_ff_Yn[11]), .B0(n714), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U755 ( .A0(n713), .A1(d_ff_Yn[12]), .B0(n714), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
INVX2TS U756 ( .A(n714), .Y(n715) );
AO22XLTS U757 ( .A0(n713), .A1(d_ff_Yn[13]), .B0(n714), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U758 ( .A0(n713), .A1(d_ff_Yn[14]), .B0(n714), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U759 ( .A0(n713), .A1(d_ff_Yn[15]), .B0(n714), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U760 ( .A0(n713), .A1(d_ff_Yn[16]), .B0(n714), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U761 ( .A0(n713), .A1(d_ff_Yn[17]), .B0(n714), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U762 ( .A0(n715), .A1(d_ff_Yn[18]), .B0(n712), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U763 ( .A0(n715), .A1(d_ff_Yn[19]), .B0(n716), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U764 ( .A0(n715), .A1(d_ff_Yn[20]), .B0(n716), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U765 ( .A0(n715), .A1(d_ff_Yn[21]), .B0(n716), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U766 ( .A0(n715), .A1(d_ff_Yn[22]), .B0(n716), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U767 ( .A0(n715), .A1(d_ff_Yn[23]), .B0(n716), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U768 ( .A0(n715), .A1(d_ff_Yn[24]), .B0(n716), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U769 ( .A0(n715), .A1(d_ff_Yn[25]), .B0(n716), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U770 ( .A0(n715), .A1(d_ff_Yn[26]), .B0(n716), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
INVX2TS U771 ( .A(n712), .Y(n717) );
AO22XLTS U772 ( .A0(n717), .A1(d_ff_Yn[27]), .B0(n716), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U773 ( .A0(n717), .A1(d_ff_Yn[28]), .B0(n716), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U774 ( .A0(n717), .A1(d_ff_Yn[29]), .B0(n716), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U775 ( .A0(n717), .A1(d_ff_Yn[30]), .B0(n716), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
NOR2BX1TS U776 ( .AN(d_ff_Xn[0]), .B(n711), .Y(first_mux_X[0]) );
NOR2BX1TS U777 ( .AN(d_ff_Xn[4]), .B(n711), .Y(first_mux_X[4]) );
NOR2BX1TS U778 ( .AN(d_ff_Xn[8]), .B(n711), .Y(first_mux_X[8]) );
NOR2BX1TS U779 ( .AN(d_ff_Xn[9]), .B(n711), .Y(first_mux_X[9]) );
NOR2BX1TS U780 ( .AN(d_ff_Xn[11]), .B(n711), .Y(first_mux_X[11]) );
NOR2BX1TS U781 ( .AN(d_ff_Xn[15]), .B(n711), .Y(first_mux_X[15]) );
NOR2BX1TS U782 ( .AN(d_ff_Xn[18]), .B(n711), .Y(first_mux_X[18]) );
NOR2BX1TS U783 ( .AN(d_ff_Xn[21]), .B(n707), .Y(first_mux_X[21]) );
NOR2BX1TS U784 ( .AN(d_ff_Xn[22]), .B(n605), .Y(first_mux_X[22]) );
NOR2BX1TS U785 ( .AN(d_ff_Xn[23]), .B(n706), .Y(first_mux_X[23]) );
NOR2BX1TS U786 ( .AN(d_ff_Xn[30]), .B(n707), .Y(first_mux_X[30]) );
NOR2BX1TS U787 ( .AN(d_ff_Xn[31]), .B(n711), .Y(first_mux_X[31]) );
NOR2BX1TS U788 ( .AN(beg_fsm_cordic), .B(n719), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U789 ( .A0(enab_d_ff4_Zn), .A1(n722), .B0(n721), .B1(n720), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U790 ( .AN(enab_d_ff4_Zn), .B(n722), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U791 ( .A0(cont_iter_out[2]), .A1(n724), .B0(n723), .Y(ITER_CONT_N4) );
XOR2XLTS U792 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U793 ( .A0(n725), .A1(d_ff3_sh_y_out[31]), .B0(n733), .B1(
d_ff3_sh_x_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U794 ( .A0(n734), .A1(d_ff3_sh_y_out[30]), .B0(n733), .B1(
d_ff3_sh_x_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U795 ( .A0(n739), .A1(d_ff3_sh_y_out[22]), .B0(n733), .B1(
d_ff3_sh_x_out[22]), .Y(n726) );
OAI2BB1X1TS U796 ( .A0N(n736), .A1N(d_ff3_LUT_out[19]), .B0(n726), .Y(
add_subt_dataB[22]) );
AOI22X1TS U797 ( .A0(n734), .A1(d_ff3_sh_y_out[19]), .B0(n733), .B1(
d_ff3_sh_x_out[19]), .Y(n727) );
OAI2BB1X1TS U798 ( .A0N(n690), .A1N(d_ff3_LUT_out[19]), .B0(n727), .Y(
add_subt_dataB[19]) );
AOI22X1TS U799 ( .A0(n725), .A1(d_ff3_sh_y_out[18]), .B0(n733), .B1(
d_ff3_sh_x_out[18]), .Y(n728) );
OAI2BB1X1TS U800 ( .A0N(n690), .A1N(d_ff3_LUT_out[13]), .B0(n728), .Y(
add_subt_dataB[18]) );
AOI22X1TS U801 ( .A0(n739), .A1(d_ff3_sh_y_out[16]), .B0(n733), .B1(
d_ff3_sh_x_out[16]), .Y(n729) );
OAI2BB1X1TS U802 ( .A0N(n741), .A1N(d_ff3_LUT_out[3]), .B0(n729), .Y(
add_subt_dataB[16]) );
AOI22X1TS U803 ( .A0(n734), .A1(d_ff3_sh_y_out[14]), .B0(n733), .B1(
d_ff3_sh_x_out[14]), .Y(n730) );
OAI2BB1X1TS U804 ( .A0N(n741), .A1N(d_ff3_LUT_out[5]), .B0(n730), .Y(
add_subt_dataB[14]) );
AOI22X1TS U805 ( .A0(n725), .A1(d_ff3_sh_y_out[13]), .B0(n733), .B1(
d_ff3_sh_x_out[13]), .Y(n731) );
OAI2BB1X1TS U806 ( .A0N(n736), .A1N(d_ff3_LUT_out[13]), .B0(n731), .Y(
add_subt_dataB[13]) );
AOI22X1TS U807 ( .A0(n739), .A1(d_ff3_sh_y_out[11]), .B0(n733), .B1(
d_ff3_sh_x_out[11]), .Y(n732) );
OAI2BB1X1TS U808 ( .A0N(n741), .A1N(d_ff3_LUT_out[7]), .B0(n732), .Y(
add_subt_dataB[11]) );
AOI22X1TS U809 ( .A0(n734), .A1(d_ff3_sh_y_out[7]), .B0(n733), .B1(
d_ff3_sh_x_out[7]), .Y(n735) );
OAI2BB1X1TS U810 ( .A0N(n690), .A1N(d_ff3_LUT_out[7]), .B0(n735), .Y(
add_subt_dataB[7]) );
AOI22X1TS U811 ( .A0(n739), .A1(d_ff3_sh_y_out[5]), .B0(n733), .B1(
d_ff3_sh_x_out[5]), .Y(n737) );
OAI2BB1X1TS U812 ( .A0N(n690), .A1N(d_ff3_LUT_out[5]), .B0(n737), .Y(
add_subt_dataB[5]) );
AOI22X1TS U813 ( .A0(n734), .A1(d_ff3_sh_y_out[3]), .B0(n733), .B1(
d_ff3_sh_x_out[3]), .Y(n740) );
OAI2BB1X1TS U814 ( .A0N(n736), .A1N(d_ff3_LUT_out[3]), .B0(n740), .Y(
add_subt_dataB[3]) );
AOI22X1TS U815 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n742), .B1(n761), .Y(
n533) );
AOI22X1TS U816 ( .A0(cont_iter_out[1]), .A1(n744), .B0(n743), .B1(n761), .Y(
n525) );
OAI2BB1X1TS U817 ( .A0N(cont_iter_out[1]), .A1N(n523), .B0(n745), .Y(n524)
);
AOI22X1TS U818 ( .A0(cont_iter_out[1]), .A1(n747), .B0(n746), .B1(n761), .Y(
n520) );
AOI22X1TS U819 ( .A0(n749), .A1(n759), .B0(cont_var_out[0]), .B1(n748), .Y(
n518) );
NOR2XLTS U821 ( .A(d_ff2_Y[29]), .B(n751), .Y(n750) );
XOR2XLTS U822 ( .A(d_ff2_Y[30]), .B(n750), .Y(sh_exp_y[7]) );
XNOR2X1TS U823 ( .A(d_ff2_Y[29]), .B(n751), .Y(sh_exp_y[6]) );
AO21XLTS U824 ( .A0(intadd_424_n1), .A1(d_ff2_Y[27]), .B0(n752), .Y(
sh_exp_y[4]) );
NOR2XLTS U825 ( .A(d_ff2_X[29]), .B(n754), .Y(n753) );
XOR2XLTS U826 ( .A(d_ff2_X[30]), .B(n753), .Y(sh_exp_x[7]) );
XNOR2X1TS U827 ( .A(d_ff2_X[29]), .B(n754), .Y(sh_exp_x[6]) );
AO21XLTS U828 ( .A0(intadd_423_n1), .A1(d_ff2_X[27]), .B0(n755), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire monclk = ~clk;
int in;
int fr_a;
int fr_b;
int fr_chk;
sub sub (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x fr_a=%x b=%x fr_chk=%x\n",$time, cyc, in, fr_a, fr_b, fr_chk);
`endif
cyc <= cyc + 1;
in <= {in[30:0], in[31]^in[2]^in[0]};
if (cyc==0) begin
// Setup
in <= 32'hd70a4497;
end
else if (cyc<3) begin
end
else if (cyc<10) begin
if (fr_chk != fr_a) $stop;
if (fr_chk != fr_b) $stop;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
always @(posedge t.monclk) begin
mon_eval();
end
endmodule
import "DPI-C" context function void mon_scope_name (input string formatted /*verilator sformat*/ );
import "DPI-C" context function void mon_register_b(string name, int isOut);
import "DPI-C" context function void mon_register_done();
import "DPI-C" context function void mon_eval();
module sub (/*AUTOARG*/
// Outputs
fr_a, fr_b, fr_chk,
// Inputs
in
);
`systemc_imp_header
void mon_class_name(const char* namep);
void mon_register_a(const char* namep, void* sigp, bool isOut);
`verilog
input int in /*verilator public_flat_rd*/;
output int fr_a /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_b /*verilator public_flat_rw @(posedge t.monclk)*/;
output int fr_chk;
always @* fr_chk = in + 1;
initial begin
// Test the naming
$c("mon_class_name(name());");
mon_scope_name("%m");
// Scheme A - pass pointer directly
$c("mon_register_a(\"in\",&",in,",false);");
$c("mon_register_a(\"fr_a\",&",fr_a,",true);");
// Scheme B - use VPIish callbacks to see what signals exist
mon_register_b("in", 0);
mon_register_b("fr_b", 1);
mon_register_done();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_4_V
`define SKY130_FD_SC_LP__SDFXTP_4_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfxtp_4 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_4_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// A simple asymetric memory. The write and read memory space must have the same size.
// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH
`timescale 1ns/100ps
module ad_mem_asym #(
parameter A_ADDRESS_WIDTH = 8,
parameter A_DATA_WIDTH = 256,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 64) (
input clka,
input wea,
input [A_ADDRESS_WIDTH-1:0] addra,
input [A_DATA_WIDTH-1:0] dina,
input clkb,
input reb,
input [B_ADDRESS_WIDTH-1:0] addrb,
output reg [B_DATA_WIDTH-1:0] doutb);
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer clog2;
input integer value;
begin
if (value < 2)
clog2 = value;
else begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1)
value = value >> 1;
end
end
endfunction
localparam MEM_ADDRESS_WIDTH = `max(A_ADDRESS_WIDTH, B_ADDRESS_WIDTH);
localparam MIN_WIDTH = `min(A_DATA_WIDTH, B_DATA_WIDTH);
localparam MAX_WIDTH = `max(A_DATA_WIDTH, B_DATA_WIDTH);
localparam MEM_DATA_WIDTH = MIN_WIDTH;
localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH;
localparam MEM_RATIO = MAX_WIDTH / MIN_WIDTH;
localparam MEM_RATIO_LOG2 = clog2(MEM_RATIO);
// internal registers
reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1];
//---------------------------------------------------------------------------
// write interface
//---------------------------------------------------------------------------
// write data width is narrower than read data width
generate if (A_DATA_WIDTH <= B_DATA_WIDTH) begin
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
end
endgenerate
// write data width is wider than read data width
generate if (A_DATA_WIDTH > B_DATA_WIDTH) begin
always @(posedge clka) begin : memwrite
integer i;
reg [MEM_RATIO_LOG2-1:0] lsb;
for (i = 0; i < MEM_RATIO; i = i + 1) begin : awrite
lsb = i;
if (wea) begin
m_ram[{addra, lsb}] <= dina[i * MIN_WIDTH +: MIN_WIDTH];
end
end
end
end
endgenerate
//---------------------------------------------------------------------------
// read interface
//---------------------------------------------------------------------------
// read data width is narrower than write data width
generate if (A_DATA_WIDTH >= B_DATA_WIDTH) begin
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
end
endgenerate
// read data width is wider than write data width
generate if (A_DATA_WIDTH < B_DATA_WIDTH) begin
always @(posedge clkb) begin : memread
integer i;
reg [MEM_RATIO_LOG2-1:0] lsb;
for (i = 0; i < MEM_RATIO; i = i + 1) begin : aread
lsb = i;
if (reb == 1'b1) begin
doutb[i*MIN_WIDTH +: MIN_WIDTH] <= m_ram[{addrb, lsb}];
end
end
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_wr.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 write requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_wr(
rstn,
sw_clk,
qos1,
qos2,
prt_dv1,
prt_dv2,
prt_data1,
prt_data2,
prt_addr1,
prt_addr2,
prt_bytes1,
prt_bytes2,
prt_ack1,
prt_ack2,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input [max_burst_bits-1:0] prt_data1,prt_data2;
input [addr_width-1:0] prt_addr1,prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2;
input prt_dv1, prt_dv2, prt_ack;
output reg prt_ack1,prt_ack2,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_ack_low = 2'b11;
reg [1:0] state,temp_state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_req = 1'b0;
if(prt_dv1 && !prt_dv2) begin
state = serv_req1;
prt_req = 1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
prt_qos = qos1;
end else if(!prt_dv1 && prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv1 && prt_dv2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
if(prt_ack) begin
prt_ack1 = 1'b1;
prt_req = 0;
if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
// state = wait_req;
state = wait_ack_low;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
if(prt_ack) begin
prt_ack2 = 1'b1;
prt_req = 0;
if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_ack_low;
// state = wait_req;
end
end
end
wait_ack_low:begin
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
state = wait_ack_low;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// EE 471 Lab 3, Beck Pang, Spring 2015
// combine SRAM and ALU together
// @require:
// Instruction formula is formed by 3 bit control, 5 bit for address of A
// 5 bit for address of B
// fetch instructions and data into SRAM, and then move to register file
module DE1_SoCPhaseII (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
reg [2:0] ps, ns;
wire [15:0] data;
reg [7:0] count; // 0~255
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
reg [2:0] control;
wire rst, fetchStart;
reg [4:0] readAdx0, readAdx1, writeAdx;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
wire [2:0] opcode;
wire [4:0] regAdx0, regAdx1;
reg [31:0] busA, busB;
wire [31:0] busOut;
wire zero, overflow, carryout, negative;
assign fetchStart = SW[6]; // fetch starts when SW[6] turns on
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store; // control the tri-state
assign LEDR[3:0] = {zero, overflow, carryout, negative};
SRAM2Kby16 memory(CLOCK_50, adx, WrEn, data);
registerFile regs(CLOCK_50, readAdx0, readAdx1, writeAdx, regWR, writeData, readOutput0, readOutput1);
ALUnit logicUnit(CLOCK_50, control, busA, busB, busOut, zero, overflow, carryout, negative);
InstrucDecoder getInstruc(data, opcode, regAdx0, regAdx1);
parameter loadData = 3'b000, loadInstr = 3'b001, transfer = 3'b010,
fetch = 3'b011, decode = 3'b100, execute = 3'b101, writeBack = 3'b110, nul = 3'bx;
always @(posedge CLOCK_50)
case (SW[6:4])
loadData : begin // write data into SRAM. Active low Write Enable
WrEn = 0;
regWR = 1;
writeAdx = 0;
writeData = 0;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
adx = count[6:0] + 8'h80;
store = 7'b1111111 - count[6:0];
// if (fetchStart)
// ps = fetch;
// else if (count[6:0] == 7'b1111111)
// ps = loadInstr;
// else
// ps = loadData;
end
loadInstr: begin // create instruction and data address using counter
WrEn = 0;
regWR = 1;
adx = count[6:0];
// count[6:4] is opcode, {1'b0, count[3:0]} the address of A, {1'b1, count[3:0]} the address of B,
store = {count[6:4], {1'b0, count[3:0]}, {1'b1, count[3:0]}, 3'b0};
// if (fetchStart)
// ns = fetch;
// else if (count[6:0] == 7'b1111111)
// ns = transfer;
// else
// ns = loadInstr;
end
transfer : begin // write data into register file
WrEn = 1;
regWR = 0;
adx = count[4:0] + 8'h80;
readAdx0 = 0;
readAdx1 = 16;
control = 0;
writeAdx = count[4:0];
writeData= {{16{data[15]}}, data};
// if (fetchStart)
// ns = fetch;
// else
// ns = transfer;
end
fetch : begin // read from register file to ALU
if(count[0]) begin
WrEn = 1;
regWR = 1;
adx = count[7:1];
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
//ns = writeBack;
//end
/*decode : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
ns = execute;
end
execute : begin
WrEn = 1;
regWR = 1;
adx = adx;
readAdx0 = regAdx0;
readAdx1 = regAdx1;
control = opcode;
busA = readOutput0;
busB = readOutput1;
ns = writeBack;
end*/
//writeBack: begin
end else begin
WrEn = 1;
regWR = 0;
writeAdx = regAdx0;
writeData= busOut;
//if (fetchStart)
//ns= fetch;
//else
//ns= execute;
end
// execute:begin
// WrEn = 1;
// regWR = 0;
// readAdx0 = count[4:0];
// readAdx1 = 5'h10 + count[4:0];
// adx = 8'h80 + count[3:0];
// if(!fetchStart)
// ns = loadData;
// else
// ns = execute;
end
default : begin
WrEn = 1'bx;
regWR = 1'bx;
ns = nul;
end
endcase
always @(posedge CLOCK_50) begin
if (rst) begin
//ps <= loadData;
count <= 8'b0;
end
else begin
//ps <= ns;
count <= count + 1'b1;
end
end
endmodule
// vlog "./sourceCode/DE1_SoCPhaseII.v"
// vlog "./sourceCode/Implementation/mux2_1.sv"
// vlog "./sourceCode/Implementation/mux4_1.sv"
// vlog "./sourceCode/Implementation/mux8_1.sv"
// vlog "./sourceCode/Implementation/mux32_1.sv"
// vlog "./sourceCode/Implementation/register.sv"
// vlog "./sourceCode/Implementation/registerSingle.sv"
// vlog "./sourceCode/Implementation/DFlipFlop.sv"
// vlog "./sourceCode/Implementation/counter.v"
// vlog "./sourceCode/Implementation/decoder5_32.sv"
// vlog "./sourceCode/Implementation/decoder8_256.sv"
// vlog "./sourceCode/Implementation/decoder11_2048.sv"
// vlog "./sourceCode/InstrucDecoder.v"
// vlog "./sourceCode/SRAM2Kby16.v"
// vlog "./sourceCode/registerFile.sv"
// vlog "./sourceCode/ALUnit.sv"
// vlog "./sourceCode/addition.v"
// vlog "./sourceCode/subtract.v"
// vlog "./sourceCode/andGate.v"
// vlog "./sourceCode/orGate.v"
// vlog "./sourceCode/xorGate.v"
// vlog "./sourceCode/setLT.v"
// vlog "./sourceCode/shiftll.v"
// vlog "./sourceCode/adder_subtractor.v"
// vlog "./sourceCode/flag.v"
// vlog "./sourceCode/adder16b.v"
// vlog "./sourceCode/adder4b.v"
// vlog "./sourceCode/fullAdder1b.v"
// vlog "./sourceCode/lookAhead4b.v"
module DE1_SoCPhaseII_Testbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoCPhaseII dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter CLOCK_PERIOD = 100;
initial CLOCK_50 = 1;
always begin
#(CLOCK_PERIOD / 2);
CLOCK_50 = ~CLOCK_50;
end
// Set up the inputs to the design
integer i;
initial begin
@(posedge CLOCK_50);
SW[9] <= 1; @(posedge CLOCK_50);
SW[8:0] <= 9'b0; @(posedge CLOCK_50);
SW[9] <= 0; @(posedge CLOCK_50);
@(posedge CLOCK_50);
for (i = 0; i < 300; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 19; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 18; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 17; i = i + 1) begin
@(posedge CLOCK_50);
end
SW[6] <= 0; @(posedge CLOCK_50);
SW[6] <= 1; @(posedge CLOCK_50);
for (i = 0; i < 16; i = i + 1) begin
@(posedge CLOCK_50);
end
$stop;
end
endmodule |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// ncverilog only
//`include "~/ee577b/syn/src/control.h"
// synthesis only
// Behavioral model for the ALU
module alu(reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// PARAMETERS
parameter zero = 1'b0;
parameter one = 1'b1;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
endcase
end
endcase
end
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
endcase
end
endcase
end
// ================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
default: // aluwprm PRM Default
result<=128'd0;
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
/*
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
*/
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/11/2016 11:27:29 AM
// Design Name:
// Module Name: Barrel_shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Barrel_Shifter
#(parameter SWR=26, parameter EWR=5) //Implicit bit + Significand Width (23 bits for simple format, 52 bits for Double format)
//+ guard Bit + round bit
/*#(parameter SWR=55, parameter EWR=6)*/
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Shift_Data_i,
input wire Left_Right_i,
input wire Bit_Shift_i,
/////////////////////////////////////////////7
output wire [SWR-1:0] N_mant_o
);
wire [SWR-1:0] Data_Reg;
////////////////////////////////////////////////////7
Mux_Array #(.SWR(SWR),.EWR(EWR)) Mux_Array(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Data_i(Shift_Data_i),
.FSM_left_right_i(Left_Right_i),
.Shift_Value_i(Shift_Value_i),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_Reg)
);
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_hp0_1.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_hp0_1(
sw_clk,
rstn,
w_qos_hp0,
r_qos_hp0,
w_qos_hp1,
r_qos_hp1,
wr_ack_ddr_hp0,
wr_data_hp0,
wr_addr_hp0,
wr_bytes_hp0,
wr_dv_ddr_hp0,
rd_req_ddr_hp0,
rd_addr_hp0,
rd_bytes_hp0,
rd_data_ddr_hp0,
rd_dv_ddr_hp0,
wr_ack_ddr_hp1,
wr_data_hp1,
wr_addr_hp1,
wr_bytes_hp1,
wr_dv_ddr_hp1,
rd_req_ddr_hp1,
rd_addr_hp1,
rd_bytes_hp1,
rd_data_ddr_hp1,
rd_dv_ddr_hp1,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp0;
input [axi_qos_width-1:0] r_qos_hp0;
input [axi_qos_width-1:0] w_qos_hp1;
input [axi_qos_width-1:0] r_qos_hp1;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp0;
input [max_burst_bits-1:0] wr_data_hp0;
input [addr_width-1:0] wr_addr_hp0;
input [max_burst_bytes_width:0] wr_bytes_hp0;
output wr_dv_ddr_hp0;
input rd_req_ddr_hp0;
input [addr_width-1:0] rd_addr_hp0;
input [max_burst_bytes_width:0] rd_bytes_hp0;
output [max_burst_bits-1:0] rd_data_ddr_hp0;
output rd_dv_ddr_hp0;
output wr_ack_ddr_hp1;
input [max_burst_bits-1:0] wr_data_hp1;
input [addr_width-1:0] wr_addr_hp1;
input [max_burst_bytes_width:0] wr_bytes_hp1;
output wr_dv_ddr_hp1;
input rd_req_ddr_hp1;
input [addr_width-1:0] rd_addr_hp1;
input [max_burst_bytes_width:0] rd_bytes_hp1;
output [max_burst_bits-1:0] rd_data_ddr_hp1;
output rd_dv_ddr_hp1;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_5_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp0),
.qos2(w_qos_hp1),
.prt_dv1(wr_dv_ddr_hp0),
.prt_dv2(wr_dv_ddr_hp1),
.prt_data1(wr_data_hp0),
.prt_data2(wr_data_hp1),
.prt_addr1(wr_addr_hp0),
.prt_addr2(wr_addr_hp1),
.prt_bytes1(wr_bytes_hp0),
.prt_bytes2(wr_bytes_hp1),
.prt_ack1(wr_ack_ddr_hp0),
.prt_ack2(wr_ack_ddr_hp1),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_5_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp0),
.qos2(r_qos_hp1),
.prt_req1(rd_req_ddr_hp0),
.prt_req2(rd_req_ddr_hp1),
.prt_data1(rd_data_ddr_hp0),
.prt_data2(rd_data_ddr_hp1),
.prt_addr1(rd_addr_hp0),
.prt_addr2(rd_addr_hp1),
.prt_bytes1(rd_bytes_hp0),
.prt_bytes2(rd_bytes_hp1),
.prt_dv1(rd_dv_ddr_hp0),
.prt_dv2(rd_dv_ddr_hp1),
.prt_qos(ddr_rd_qos),
.prt_req(ddr_rd_req),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_BEHAVIORAL_V |
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:48 01/05/2015
// Design Name:
// Module Name: db_rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dp_rom #(
parameter aw = 5,
parameter memfile = ""
) (
input clk1,
input en1,
input [aw - 1:0] adr1,
output reg [31:0] dat1,
input clk2,
input en2,
input [aw - 1:0] adr2,
output reg [31:0] dat2
);
reg [31:0] rom_data[2**aw - 1:0];
initial
$readmemh(memfile, rom_data);
always @(posedge clk1)
begin
if(en1)
dat1 <= rom_data[adr1];
end
always @(posedge clk2)
begin
if(en2)
dat2 <= rom_data[adr2];
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized 16/32 word deep FIFO.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_aw_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Write Address Ports
input wire [C_ID_WIDTH-1:0] s_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr ,
input wire [7:0] s_awlen ,
input wire [2:0] s_awsize ,
input wire [1:0] s_awburst ,
input wire s_awvalid ,
output wire s_awready ,
output wire m_awvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_awaddr ,
input wire m_awready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_b_channel module
output wire b_push ,
output wire [C_ID_WIDTH-1:0] b_awid ,
output wire [7:0] b_awlen ,
input wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_awid_r;
reg [7:0] s_awlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_awaddr ) ,
.s_axlen ( s_awlen ) ,
.s_axsize ( s_awsize ) ,
.s_axburst ( s_awburst ) ,
.s_axhandshake ( s_awvalid & a_push ) ,
.m_axaddr ( m_awaddr ) ,
.incr_burst ( incr_burst ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_b2s_wr_cmd_fsm aw_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_awready ( s_awready ) ,
.s_awvalid ( s_awvalid ) ,
.m_awvalid ( m_awvalid ) ,
.m_awready ( m_awready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.b_push ( b_push ) ,
.b_full ( b_full ) ,
.a_push ( a_push )
);
assign b_awid = s_awid_r;
assign b_awlen = s_awlen_r;
always @(posedge clk) begin
s_awid_r <= s_awid ;
s_awlen_r <= s_awlen ;
end
endmodule
`default_nettype wire
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* "is_last" == 0 means byte number is 8, no matter what value "byte_num" is. */
/* if "in_ready" == 0, then "is_last" should be 0. */
/* the user switch to next "in" only if "ack" == 1. */
`define low_pos(w,b) ((w)*64 + (b)*8)
`define low_pos2(w,b) `low_pos(w,7-b)
`define high_pos(w,b) (`low_pos(w,b) + 7)
`define high_pos2(w,b) (`low_pos2(w,b) + 7)
module keccak(clk, reset, in, in_ready, is_last, byte_num, buffer_full, out, out_ready);
input clk, reset;
input [31:0] in;
input in_ready, is_last;
input [1:0] byte_num;
output buffer_full; /* to "user" module */
output [511:0] out;
output reg out_ready;
reg state; /* state == 0: user will send more input data
* state == 1: user will not send any data */
wire [575:0] padder_out,
padder_out_1; /* before reorder byte */
wire padder_out_ready;
wire f_ack;
wire [1599:0] f_out;
wire f_out_ready;
wire [511:0] out1; /* before reorder byte */
reg [22:0] i; /* gen "out_ready" */
genvar w, b;
assign out1 = f_out[1599:1599-511];
always @ (posedge clk)
if (reset)
i <= 0;
else
i <= {i[21:0], state & f_ack};
always @ (posedge clk)
if (reset)
state <= 0;
else if (is_last)
state <= 1;
/* reorder byte ~ ~ */
generate
for(w=0; w<8; w=w+1)
begin : L0
for(b=0; b<8; b=b+1)
begin : L1
assign out[`high_pos(w,b):`low_pos(w,b)] = out1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
/* reorder byte ~ ~ */
generate
for(w=0; w<9; w=w+1)
begin : L2
for(b=0; b<8; b=b+1)
begin : L3
assign padder_out[`high_pos(w,b):`low_pos(w,b)] = padder_out_1[`high_pos2(w,b):`low_pos2(w,b)];
end
end
endgenerate
always @ (posedge clk)
if (reset)
out_ready <= 0;
else if (i[22])
out_ready <= 1;
padder
padder_ (clk, reset, in, in_ready, is_last, byte_num, buffer_full, padder_out_1, padder_out_ready, f_ack);
f_permutation
f_permutation_ (clk, reset, padder_out, padder_out_ready, f_ack, f_out, f_out_ready);
endmodule
`undef low_pos
`undef low_pos2
`undef high_pos
`undef high_pos2
|
//
// Take a 32 bit number in and distribute it's bits over a 1024 bit output bus
// in some randomish pattern.
//
`include "timescale.vh"
module shuff
(
input wire [62 : 0] x,
output wire [32*16 - 1 : 0] out
);
assign out = {
{!x[00], x[62],!x[02], x[28],!x[09], x[55], x[03],!x[34], x[45], x[37],!x[11], x[07],!x[41],!x[50],!x[52],!x[59],!x[27],!x[40], x[01], x[57], x[17],!x[53],!x[24],!x[22],!x[58], x[25], x[16],!x[29],!x[43], x[32],!x[14], x[30]},
{!x[47], x[49],!x[35],!x[38], x[33],!x[31], x[44], x[13], x[06], x[54],!x[05],!x[10],!x[23],!x[19],!x[51], x[20],!x[39],!x[18],!x[46],!x[42], x[36], x[08], x[04], x[60],!x[48],!x[56],!x[26], x[21],!x[12], x[61],!x[15], x[16]},
{!x[23],!x[21],!x[20],!x[47], x[10], x[48], x[51], x[07],!x[19], x[03],!x[50], x[60],!x[36], x[38],!x[33],!x[06],!x[28], x[27], x[00], x[53], x[24], x[52],!x[14],!x[29],!x[04], x[08], x[42],!x[13],!x[45],!x[56],!x[54], x[61]},
{!x[22], x[15], x[41],!x[05], x[59], x[58],!x[35],!x[26],!x[11],!x[12], x[31],!x[01], x[39],!x[43],!x[62],!x[25],!x[55],!x[32],!x[44],!x[02],!x[46],!x[37], x[09], x[17], x[49],!x[18],!x[34], x[40],!x[57], x[30],!x[56],!x[08]},
{!x[37],!x[42],!x[33], x[35], x[39], x[17],!x[10], x[09], x[23],!x[02],!x[60],!x[36], x[18],!x[00], x[32],!x[21],!x[27], x[34], x[20], x[53], x[48], x[15], x[55],!x[14], x[19],!x[62], x[04],!x[29], x[22],!x[28],!x[06], x[03]},
{!x[45], x[26], x[47],!x[43],!x[50],!x[11], x[57],!x[44], x[31],!x[12],!x[41], x[58],!x[13], x[25], x[07],!x[30], x[05],!x[61],!x[49],!x[59], x[46], x[01], x[52],!x[51],!x[32],!x[16],!x[24],!x[38],!x[54],!x[21], x[37], x[40]},
{ x[44],!x[30], x[52], x[62],!x[58], x[45], x[38],!x[55], x[00],!x[12], x[14], x[47],!x[13], x[39], x[53], x[40],!x[18], x[31],!x[03], x[41],!x[48],!x[27], x[09],!x[07],!x[17],!x[15],!x[56], x[20], x[16], x[51],!x[59],!x[11]},
{ x[04], x[06], x[22], x[26],!x[50], x[29],!x[34], x[19], x[60], x[05],!x[49], x[57],!x[33], x[10],!x[01], x[46], x[24],!x[08], x[25], x[23], x[35],!x[42], x[54], x[43],!x[36],!x[02],!x[31],!x[28], x[13],!x[15],!x[61],!x[53]},
{!x[27], x[44],!x[33], x[52],!x[34], x[29],!x[20],!x[35], x[01], x[11], x[60],!x[14],!x[45], x[10],!x[36], x[22],!x[21],!x[55], x[62],!x[46],!x[16],!x[26],!x[07],!x[30],!x[17], x[51], x[02],!x[48],!x[42], x[43],!x[08], x[19]},
{!x[38], x[49], x[05], x[28],!x[39], x[23],!x[57],!x[25],!x[18],!x[54],!x[61],!x[24],!x[09],!x[03], x[56], x[04], x[41], x[37], x[40],!x[47],!x[00],!x[06],!x[59],!x[50], x[51],!x[26],!x[22], x[32],!x[58], x[27],!x[12], x[48]},
{ x[12],!x[17], x[04],!x[54],!x[18], x[02],!x[35], x[44],!x[40], x[50], x[21], x[37], x[15], x[58],!x[19],!x[42], x[41], x[00],!x[47],!x[56], x[46], x[20], x[34], x[11], x[45], x[32],!x[10],!x[60], x[23],!x[62],!x[61], x[13]},
{ x[03], x[53],!x[08], x[33], x[29],!x[01], x[07],!x[28],!x[31],!x[24],!x[57], x[25], x[43],!x[49], x[55],!x[38],!x[06],!x[09], x[05],!x[59],!x[30], x[39], x[16],!x[52], x[14], x[21],!x[20],!x[36], x[13],!x[04],!x[37],!x[34]},
{!x[14],!x[36],!x[35],!x[05], x[45],!x[06],!x[54],!x[41], x[23],!x[15],!x[26],!x[49],!x[39], x[30], x[29],!x[38], x[22],!x[01], x[55],!x[43],!x[46], x[52],!x[53], x[40],!x[16], x[27],!x[00],!x[57],!x[18], x[62], x[28],!x[58]},
{ x[07], x[10], x[32], x[50], x[03],!x[12], x[59], x[09],!x[19], x[56],!x[44], x[25], x[47],!x[08], x[31],!x[51], x[17], x[42],!x[61],!x[02],!x[33], x[24], x[30], x[04],!x[43], x[48],!x[49],!x[11],!x[22],!x[29],!x[60],!x[38]},
{ x[42], x[37], x[10], x[08], x[61], x[21],!x[00], x[20], x[51], x[57],!x[33],!x[01],!x[03],!x[26],!x[32],!x[05],!x[13], x[19],!x[48],!x[31],!x[02],!x[60],!x[07],!x[36],!x[62], x[27],!x[34],!x[14], x[50],!x[16],!x[17], x[11]},
{!x[56],!x[23],!x[28], x[15], x[45], x[09],!x[24],!x[46],!x[53],!x[25],!x[52],!x[39],!x[40], x[44],!x[55], x[54], x[59],!x[21],!x[06], x[08],!x[18],!x[01],!x[11],!x[61], x[47],!x[41], x[12], x[49],!x[20],!x[29], x[35],!x[58]}
};
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.3
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="dut_inst,dut,{component_name=dut_inst,HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.789000,HLS_SYN_LAT=12,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=11,HLS_SYN_FF=593,HLS_SYN_LUT=750}" *)
module dut (
ap_clk,
ap_rst,
in_fifo_V_dout,
in_fifo_V_empty_n,
in_fifo_V_read,
out_fifo_V_din,
out_fifo_V_full_n,
out_fifo_V_write
);
input ap_clk;
input ap_rst;
input [31:0] in_fifo_V_dout;
input in_fifo_V_empty_n;
output in_fifo_V_read;
output [31:0] out_fifo_V_din;
input out_fifo_V_full_n;
output out_fifo_V_write;
reg in_fifo_V_read;
reg[31:0] out_fifo_V_din;
reg out_fifo_V_write;
reg [31:0] tmp_2_reg_115;
reg [3:0] ap_CS_fsm = 4'b0000;
reg [31:0] tmp_6_reg_120;
reg [31:0] tmp_7_reg_125;
wire [63:0] full_fu_60_p2;
reg [63:0] full_reg_130;
wire [63:0] full_1_fu_79_p2;
reg [63:0] full_1_reg_135;
reg [31:0] data1_reg_150;
wire [15:0] data2_2_fu_107_p1;
reg [15:0] data2_2_reg_155;
wire [31:0] tmp_1_fu_111_p1;
wire [63:0] grp_fu_44_p0;
wire [63:0] grp_fu_44_p1;
wire [63:0] tmp_3_fu_48_p1;
wire [63:0] tmp_4_fu_51_p2;
wire [63:0] full_fu_60_p1;
wire [63:0] tmp_9_fu_66_p1;
wire [63:0] tmp_s_fu_69_p2;
wire [63:0] full_1_fu_79_p1;
wire [63:0] grp_fu_44_p2;
wire [63:0] ret_fu_93_p1;
wire grp_fu_44_ce;
reg [3:0] ap_NS_fsm;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b0000;
parameter ap_ST_st2_fsm_1 = 4'b0001;
parameter ap_ST_st3_fsm_2 = 4'b0010;
parameter ap_ST_st4_fsm_3 = 4'b0011;
parameter ap_ST_st5_fsm_4 = 4'b0100;
parameter ap_ST_st6_fsm_5 = 4'b0101;
parameter ap_ST_st7_fsm_6 = 4'b0110;
parameter ap_ST_st8_fsm_7 = 4'b0111;
parameter ap_ST_st9_fsm_8 = 4'b1000;
parameter ap_ST_st10_fsm_9 = 4'b1001;
parameter ap_ST_st11_fsm_10 = 4'b1010;
parameter ap_ST_st12_fsm_11 = 4'b1011;
parameter ap_ST_st13_fsm_12 = 4'b1100;
parameter ap_const_lv64_20 = 64'b0000000000000000000000000000000000000000000000000000000000100000;
parameter ap_const_lv32_20 = 32'b00000000000000000000000000100000;
parameter ap_const_lv32_3F = 32'b00000000000000000000000000111111;
parameter ap_true = 1'b1;
dut_grp_fu_44_ACMP_dmul_1 #(
.ID( 1 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
dut_grp_fu_44_ACMP_dmul_1_U(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_44_p0 ),
.din1( grp_fu_44_p1 ),
.ce( grp_fu_44_ce ),
.dout( grp_fu_44_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
data1_reg_150 <= {{ret_fu_93_p1[ap_const_lv32_3F : ap_const_lv32_20]}};
end
if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
data2_2_reg_155 <= data2_2_fu_107_p1;
end
if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
full_1_reg_135 <= full_1_fu_79_p2;
end
if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
full_reg_130 <= full_fu_60_p2;
end
if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0))) begin
tmp_2_reg_115 <= in_fifo_V_dout;
end
if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm))) begin
tmp_6_reg_120 <= in_fifo_V_dout;
end
if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
tmp_7_reg_125 <= in_fifo_V_dout;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (in_fifo_V_empty_n or out_fifo_V_full_n or ap_CS_fsm)
begin
if ((~(out_fifo_V_full_n == ap_const_logic_0) & (ap_ST_st13_fsm_12 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else if (((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(out_fifo_V_full_n == ap_const_logic_0))) begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end else if ((ap_ST_st11_fsm_10 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end else if ((ap_ST_st10_fsm_9 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end else if ((ap_ST_st9_fsm_8 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end else if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end else if ((ap_ST_st7_fsm_6 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end else if ((ap_ST_st6_fsm_5 == ap_CS_fsm)) begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else if (((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else if ((~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_CS_fsm;
end
end
/// in_fifo_V_read assign process. ///
always @ (in_fifo_V_empty_n or ap_CS_fsm)
begin
if ((((ap_ST_st2_fsm_1 == ap_CS_fsm) & ~(in_fifo_V_empty_n == ap_const_logic_0)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st3_fsm_2 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st4_fsm_3 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st5_fsm_4 == ap_CS_fsm)) | (~(in_fifo_V_empty_n == ap_const_logic_0) & (ap_ST_st1_fsm_0 == ap_CS_fsm)))) begin
in_fifo_V_read = ap_const_logic_1;
end else begin
in_fifo_V_read = ap_const_logic_0;
end
end
/// out_fifo_V_din assign process. ///
always @ (ap_CS_fsm or data1_reg_150 or tmp_1_fu_111_p1)
begin
if ((ap_ST_st13_fsm_12 == ap_CS_fsm)) begin
out_fifo_V_din = tmp_1_fu_111_p1;
end else if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
out_fifo_V_din = data1_reg_150;
end else begin
out_fifo_V_din = tmp_1_fu_111_p1;
end
end
/// out_fifo_V_write assign process. ///
always @ (out_fifo_V_full_n or ap_CS_fsm)
begin
if ((((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(out_fifo_V_full_n == ap_const_logic_0)) | (~(out_fifo_V_full_n == ap_const_logic_0) & (ap_ST_st13_fsm_12 == ap_CS_fsm)))) begin
out_fifo_V_write = ap_const_logic_1;
end else begin
out_fifo_V_write = ap_const_logic_0;
end
end
assign data2_2_fu_107_p1 = ret_fu_93_p1[15:0];
assign full_1_fu_79_p1 = $signed(in_fifo_V_dout);
assign full_1_fu_79_p2 = (tmp_s_fu_69_p2 + full_1_fu_79_p1);
assign full_fu_60_p1 = $signed(tmp_6_reg_120);
assign full_fu_60_p2 = (tmp_4_fu_51_p2 + full_fu_60_p1);
assign grp_fu_44_ce = ap_const_logic_1;
assign grp_fu_44_p0 = full_reg_130;
assign grp_fu_44_p1 = full_1_reg_135;
assign ret_fu_93_p1 = grp_fu_44_p2;
assign tmp_1_fu_111_p1 = $unsigned(data2_2_reg_155);
assign tmp_3_fu_48_p1 = $unsigned(tmp_2_reg_115);
assign tmp_4_fu_51_p2 = tmp_3_fu_48_p1 << ap_const_lv64_20;
assign tmp_9_fu_66_p1 = $unsigned(tmp_7_reg_125);
assign tmp_s_fu_69_p2 = tmp_9_fu_66_p1 << ap_const_lv64_20;
endmodule //dut
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// CONFIG:
// NUM_COEFF = 36
// PIPLINED = 0
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 18)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 36;
parameter N_UNIQ = 18; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 37;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 36;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
reg [dw-1:0] COEFFICIENT_9;
reg [dw-1:0] COEFFICIENT_10;
reg [dw-1:0] COEFFICIENT_11;
reg [dw-1:0] COEFFICIENT_12;
reg [dw-1:0] COEFFICIENT_13;
reg [dw-1:0] COEFFICIENT_14;
reg [dw-1:0] COEFFICIENT_15;
reg [dw-1:0] COEFFICIENT_16;
reg [dw-1:0] COEFFICIENT_17;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
COEFFICIENT_9 <= -18'd481;
COEFFICIENT_10 <= -18'd420;
COEFFICIENT_11 <= -18'd319;
COEFFICIENT_12 <= -18'd178;
COEFFICIENT_13 <= 18'd0;
COEFFICIENT_14 <= 18'd212;
COEFFICIENT_15 <= 18'd451;
COEFFICIENT_16 <= 18'd710;
COEFFICIENT_17 <= 18'd980;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
wire [dw-1:0] INPUT_PIPELINE_REG_17;
wire [dw-1:0] INPUT_PIPELINE_REG_18;
wire [dw-1:0] INPUT_PIPELINE_REG_19;
wire [dw-1:0] INPUT_PIPELINE_REG_20;
wire [dw-1:0] INPUT_PIPELINE_REG_21;
wire [dw-1:0] INPUT_PIPELINE_REG_22;
wire [dw-1:0] INPUT_PIPELINE_REG_23;
wire [dw-1:0] INPUT_PIPELINE_REG_24;
wire [dw-1:0] INPUT_PIPELINE_REG_25;
wire [dw-1:0] INPUT_PIPELINE_REG_26;
wire [dw-1:0] INPUT_PIPELINE_REG_27;
wire [dw-1:0] INPUT_PIPELINE_REG_28;
wire [dw-1:0] INPUT_PIPELINE_REG_29;
wire [dw-1:0] INPUT_PIPELINE_REG_30;
wire [dw-1:0] INPUT_PIPELINE_REG_31;
wire [dw-1:0] INPUT_PIPELINE_REG_32;
wire [dw-1:0] INPUT_PIPELINE_REG_33;
wire [dw-1:0] INPUT_PIPELINE_REG_34;
wire [dw-1:0] INPUT_PIPELINE_REG_35;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.pipeline_reg_17(INPUT_PIPELINE_REG_17),
.pipeline_reg_18(INPUT_PIPELINE_REG_18),
.pipeline_reg_19(INPUT_PIPELINE_REG_19),
.pipeline_reg_20(INPUT_PIPELINE_REG_20),
.pipeline_reg_21(INPUT_PIPELINE_REG_21),
.pipeline_reg_22(INPUT_PIPELINE_REG_22),
.pipeline_reg_23(INPUT_PIPELINE_REG_23),
.pipeline_reg_24(INPUT_PIPELINE_REG_24),
.pipeline_reg_25(INPUT_PIPELINE_REG_25),
.pipeline_reg_26(INPUT_PIPELINE_REG_26),
.pipeline_reg_27(INPUT_PIPELINE_REG_27),
.pipeline_reg_28(INPUT_PIPELINE_REG_28),
.pipeline_reg_29(INPUT_PIPELINE_REG_29),
.pipeline_reg_30(INPUT_PIPELINE_REG_30),
.pipeline_reg_31(INPUT_PIPELINE_REG_31),
.pipeline_reg_32(INPUT_PIPELINE_REG_32),
.pipeline_reg_33(INPUT_PIPELINE_REG_33),
.pipeline_reg_34(INPUT_PIPELINE_REG_34),
.pipeline_reg_35(INPUT_PIPELINE_REG_35),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
wire [dw-1:0] L0_output_wires_9;
wire [dw-1:0] L0_output_wires_10;
wire [dw-1:0] L0_output_wires_11;
wire [dw-1:0] L0_output_wires_12;
wire [dw-1:0] L0_output_wires_13;
wire [dw-1:0] L0_output_wires_14;
wire [dw-1:0] L0_output_wires_15;
wire [dw-1:0] L0_output_wires_16;
wire [dw-1:0] L0_output_wires_17;
adder_with_1_reg L0_adder_0and35(
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_35),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and34(
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_34),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and33(
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_33),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and32(
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_32),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and31(
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_31),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and30(
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_30),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and29(
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_29),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and28(
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_28),
.result(L0_output_wires_7)
);
adder_with_1_reg L0_adder_8and27(
.dataa (INPUT_PIPELINE_REG_8),
.datab (INPUT_PIPELINE_REG_27),
.result(L0_output_wires_8)
);
adder_with_1_reg L0_adder_9and26(
.dataa (INPUT_PIPELINE_REG_9),
.datab (INPUT_PIPELINE_REG_26),
.result(L0_output_wires_9)
);
adder_with_1_reg L0_adder_10and25(
.dataa (INPUT_PIPELINE_REG_10),
.datab (INPUT_PIPELINE_REG_25),
.result(L0_output_wires_10)
);
adder_with_1_reg L0_adder_11and24(
.dataa (INPUT_PIPELINE_REG_11),
.datab (INPUT_PIPELINE_REG_24),
.result(L0_output_wires_11)
);
adder_with_1_reg L0_adder_12and23(
.dataa (INPUT_PIPELINE_REG_12),
.datab (INPUT_PIPELINE_REG_23),
.result(L0_output_wires_12)
);
adder_with_1_reg L0_adder_13and22(
.dataa (INPUT_PIPELINE_REG_13),
.datab (INPUT_PIPELINE_REG_22),
.result(L0_output_wires_13)
);
adder_with_1_reg L0_adder_14and21(
.dataa (INPUT_PIPELINE_REG_14),
.datab (INPUT_PIPELINE_REG_21),
.result(L0_output_wires_14)
);
adder_with_1_reg L0_adder_15and20(
.dataa (INPUT_PIPELINE_REG_15),
.datab (INPUT_PIPELINE_REG_20),
.result(L0_output_wires_15)
);
adder_with_1_reg L0_adder_16and19(
.dataa (INPUT_PIPELINE_REG_16),
.datab (INPUT_PIPELINE_REG_19),
.result(L0_output_wires_16)
);
adder_with_1_reg L0_adder_17and18(
.dataa (INPUT_PIPELINE_REG_17),
.datab (INPUT_PIPELINE_REG_18),
.result(L0_output_wires_17)
);
// (18 main tree Adders)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
wire [dw-1:0] L1_mult_wires_9;
wire [dw-1:0] L1_mult_wires_10;
wire [dw-1:0] L1_mult_wires_11;
wire [dw-1:0] L1_mult_wires_12;
wire [dw-1:0] L1_mult_wires_13;
wire [dw-1:0] L1_mult_wires_14;
wire [dw-1:0] L1_mult_wires_15;
wire [dw-1:0] L1_mult_wires_16;
wire [dw-1:0] L1_mult_wires_17;
multiplier_with_reg L1_mul_0(
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
multiplier_with_reg L1_mul_9(
.dataa (L0_output_wires_9),
.datab (COEFFICIENT_9),
.result(L1_mult_wires_9)
);
multiplier_with_reg L1_mul_10(
.dataa (L0_output_wires_10),
.datab (COEFFICIENT_10),
.result(L1_mult_wires_10)
);
multiplier_with_reg L1_mul_11(
.dataa (L0_output_wires_11),
.datab (COEFFICIENT_11),
.result(L1_mult_wires_11)
);
multiplier_with_reg L1_mul_12(
.dataa (L0_output_wires_12),
.datab (COEFFICIENT_12),
.result(L1_mult_wires_12)
);
multiplier_with_reg L1_mul_13(
.dataa (L0_output_wires_13),
.datab (COEFFICIENT_13),
.result(L1_mult_wires_13)
);
multiplier_with_reg L1_mul_14(
.dataa (L0_output_wires_14),
.datab (COEFFICIENT_14),
.result(L1_mult_wires_14)
);
multiplier_with_reg L1_mul_15(
.dataa (L0_output_wires_15),
.datab (COEFFICIENT_15),
.result(L1_mult_wires_15)
);
multiplier_with_reg L1_mul_16(
.dataa (L0_output_wires_16),
.datab (COEFFICIENT_16),
.result(L1_mult_wires_16)
);
multiplier_with_reg L1_mul_17(
.dataa (L0_output_wires_17),
.datab (COEFFICIENT_17),
.result(L1_mult_wires_17)
);
// (18 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
wire [dw-1:0] L1_output_wires_5;
wire [dw-1:0] L1_output_wires_6;
wire [dw-1:0] L1_output_wires_7;
wire [dw-1:0] L1_output_wires_8;
adder_with_1_reg L1_adder_0and1(
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
adder_with_1_reg L1_adder_8and9(
.dataa (L1_mult_wires_8),
.datab (L1_mult_wires_9),
.result(L1_output_wires_4)
);
adder_with_1_reg L1_adder_10and11(
.dataa (L1_mult_wires_10),
.datab (L1_mult_wires_11),
.result(L1_output_wires_5)
);
adder_with_1_reg L1_adder_12and13(
.dataa (L1_mult_wires_12),
.datab (L1_mult_wires_13),
.result(L1_output_wires_6)
);
adder_with_1_reg L1_adder_14and15(
.dataa (L1_mult_wires_14),
.datab (L1_mult_wires_15),
.result(L1_output_wires_7)
);
adder_with_1_reg L1_adder_16and17(
.dataa (L1_mult_wires_16),
.datab (L1_mult_wires_17),
.result(L1_output_wires_8)
);
// (9 main tree Adders)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
wire [dw-1:0] L2_output_wires_3;
wire [dw-1:0] L2_output_wires_4;
adder_with_1_reg L2_adder_0and1(
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
adder_with_1_reg L2_adder_4and5(
.dataa (L1_output_wires_4),
.datab (L1_output_wires_5),
.result(L2_output_wires_2)
);
adder_with_1_reg L2_adder_6and7(
.dataa (L1_output_wires_6),
.datab (L1_output_wires_7),
.result(L2_output_wires_3)
);
// (4 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_8(
.dataa (L1_output_wires_8),
.result(L2_output_wires_4)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
wire [dw-1:0] L3_output_wires_2;
adder_with_1_reg L3_adder_0and1(
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
adder_with_1_reg L3_adder_2and3(
.dataa (L2_output_wires_2),
.datab (L2_output_wires_3),
.result(L3_output_wires_1)
);
// (2 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_4(
.dataa (L2_output_wires_4),
.result(L3_output_wires_2)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
wire [dw-1:0] L4_output_wires_1;
adder_with_1_reg L4_adder_0and1(
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L4_byereg_for_2(
.dataa (L3_output_wires_2),
.result(L4_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 5 ************************* \\
wire [dw-1:0] L5_output_wires_0;
adder_with_1_reg L5_adder_0and1(
.dataa (L4_output_wires_0),
.datab (L4_output_wires_1),
.result(L5_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
reg [17:0] o_out;
always @(posedge clk) begin
if(clk_ena) begin
o_out <= L5_output_wires_0;
end
end
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
pipeline_reg_17,
pipeline_reg_18,
pipeline_reg_19,
pipeline_reg_20,
pipeline_reg_21,
pipeline_reg_22,
pipeline_reg_23,
pipeline_reg_24,
pipeline_reg_25,
pipeline_reg_26,
pipeline_reg_27,
pipeline_reg_28,
pipeline_reg_29,
pipeline_reg_30,
pipeline_reg_31,
pipeline_reg_32,
pipeline_reg_33,
pipeline_reg_34,
pipeline_reg_35,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
output [WIDTH-1:0] pipeline_reg_17;
output [WIDTH-1:0] pipeline_reg_18;
output [WIDTH-1:0] pipeline_reg_19;
output [WIDTH-1:0] pipeline_reg_20;
output [WIDTH-1:0] pipeline_reg_21;
output [WIDTH-1:0] pipeline_reg_22;
output [WIDTH-1:0] pipeline_reg_23;
output [WIDTH-1:0] pipeline_reg_24;
output [WIDTH-1:0] pipeline_reg_25;
output [WIDTH-1:0] pipeline_reg_26;
output [WIDTH-1:0] pipeline_reg_27;
output [WIDTH-1:0] pipeline_reg_28;
output [WIDTH-1:0] pipeline_reg_29;
output [WIDTH-1:0] pipeline_reg_30;
output [WIDTH-1:0] pipeline_reg_31;
output [WIDTH-1:0] pipeline_reg_32;
output [WIDTH-1:0] pipeline_reg_33;
output [WIDTH-1:0] pipeline_reg_34;
output [WIDTH-1:0] pipeline_reg_35;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_17;
reg [WIDTH-1:0] pipeline_reg_18;
reg [WIDTH-1:0] pipeline_reg_19;
reg [WIDTH-1:0] pipeline_reg_20;
reg [WIDTH-1:0] pipeline_reg_21;
reg [WIDTH-1:0] pipeline_reg_22;
reg [WIDTH-1:0] pipeline_reg_23;
reg [WIDTH-1:0] pipeline_reg_24;
reg [WIDTH-1:0] pipeline_reg_25;
reg [WIDTH-1:0] pipeline_reg_26;
reg [WIDTH-1:0] pipeline_reg_27;
reg [WIDTH-1:0] pipeline_reg_28;
reg [WIDTH-1:0] pipeline_reg_29;
reg [WIDTH-1:0] pipeline_reg_30;
reg [WIDTH-1:0] pipeline_reg_31;
reg [WIDTH-1:0] pipeline_reg_32;
reg [WIDTH-1:0] pipeline_reg_33;
reg [WIDTH-1:0] pipeline_reg_34;
reg [WIDTH-1:0] pipeline_reg_35;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
pipeline_reg_17 <= 0;
pipeline_reg_18 <= 0;
pipeline_reg_19 <= 0;
pipeline_reg_20 <= 0;
pipeline_reg_21 <= 0;
pipeline_reg_22 <= 0;
pipeline_reg_23 <= 0;
pipeline_reg_24 <= 0;
pipeline_reg_25 <= 0;
pipeline_reg_26 <= 0;
pipeline_reg_27 <= 0;
pipeline_reg_28 <= 0;
pipeline_reg_29 <= 0;
pipeline_reg_30 <= 0;
pipeline_reg_31 <= 0;
pipeline_reg_32 <= 0;
pipeline_reg_33 <= 0;
pipeline_reg_34 <= 0;
pipeline_reg_35 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
pipeline_reg_17 <= pipeline_reg_16;
pipeline_reg_18 <= pipeline_reg_17;
pipeline_reg_19 <= pipeline_reg_18;
pipeline_reg_20 <= pipeline_reg_19;
pipeline_reg_21 <= pipeline_reg_20;
pipeline_reg_22 <= pipeline_reg_21;
pipeline_reg_23 <= pipeline_reg_22;
pipeline_reg_24 <= pipeline_reg_23;
pipeline_reg_25 <= pipeline_reg_24;
pipeline_reg_26 <= pipeline_reg_25;
pipeline_reg_27 <= pipeline_reg_26;
pipeline_reg_28 <= pipeline_reg_27;
pipeline_reg_29 <= pipeline_reg_28;
pipeline_reg_30 <= pipeline_reg_29;
pipeline_reg_31 <= pipeline_reg_30;
pipeline_reg_32 <= pipeline_reg_31;
pipeline_reg_33 <= pipeline_reg_32;
pipeline_reg_34 <= pipeline_reg_33;
pipeline_reg_35 <= pipeline_reg_34;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//pipeline_reg_17 <= pipeline_reg_17;
//pipeline_reg_18 <= pipeline_reg_18;
//pipeline_reg_19 <= pipeline_reg_19;
//pipeline_reg_20 <= pipeline_reg_20;
//pipeline_reg_21 <= pipeline_reg_21;
//pipeline_reg_22 <= pipeline_reg_22;
//pipeline_reg_23 <= pipeline_reg_23;
//pipeline_reg_24 <= pipeline_reg_24;
//pipeline_reg_25 <= pipeline_reg_25;
//pipeline_reg_26 <= pipeline_reg_26;
//pipeline_reg_27 <= pipeline_reg_27;
//pipeline_reg_28 <= pipeline_reg_28;
//pipeline_reg_29 <= pipeline_reg_29;
//pipeline_reg_30 <= pipeline_reg_30;
//pipeline_reg_31 <= pipeline_reg_31;
//pipeline_reg_32 <= pipeline_reg_32;
//pipeline_reg_33 <= pipeline_reg_33;
//pipeline_reg_34 <= pipeline_reg_34;
//pipeline_reg_35 <= pipeline_reg_35;
//end
end
end
endmodule
module adder_with_1_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa + datab;
endmodule
module multiplier_with_reg (
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
assign result = dataa * datab;
endmodule
module one_register (
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
assign result = dataa;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
real n0; initial n0 = 0.0;
real n1; initial n1 = 1.0;
real n2; initial n2 = 0.1;
real n3; initial n3 = 1.2345e-15;
real n4; initial n4 = 2.579e+15;
reg [7:0] r8; initial r8 = 3;
initial begin
// Display formatting
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n0,n0,n0,n0);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n0,n0,n0,n0);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n1,n1,n1,n1);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n1,n1,n1,n1);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n2,n2,n2,n2);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n2,n2,n2,n2);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n3,n3,n3,n3);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n3,n3,n3,n3);
$display;
$display("[%0t] e=%e e1=%1e e30=%3.0e e32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] f=%f f1=%1e f30=%3.0e f32=%3.2e", $time, n4,n4,n4,n4);
$display("[%0t] g=%g g1=%1e g30=%3.0e g32=%3.2e", $time, n4,n4,n4,n4);
$display;
$display("r8=%d n1=%g n2=%g", r8, n1, n2);
$display("n1=%g n2=%g r8=%d", n1, n2, r8);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module tx(output wire ALERT_TransmitSOP_MessageFailed,
output wire ALERT_TransmitSuccessful,
output wire MessageID_mismatch,
output wire SOP_mismatch,
output wire MessageID_SOP_match,
output wire [7:0] TRANSMIT_BYTE_COUNT,
output wire [7:0] TRANSMIT_HEADER_LOW,
output wire [7:0] TRANSMIT_HEADER_HIGH,
output wire [7:0] TRANSMIT_DATA_OBJECTS,
output wire Start_CRCReceiveTimer,
output wire Stop_CRCReceiverTimer,
output wire MessageIDCounter,
output wire MessageID,
input wire [2:0] TRANSMIT,
input wire PRL_Rx_Message_Discard,
input wire Hard_Reset_received,
input wire Cable_Reset_received,
input wire RetryCounter,
input wire CRCReceiveTimer_Timeout,
input wire GoodCRC_Response_from_PHY,
input wire Message_discarded_bus_Idle,
input wire [7:0] TX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_FRAME_TYPE,
input wire CLK,
input wire RESET);
wire RetryCounter_bigger;
wire RetryCounter_smaller;
reg [7:0] CurrentState;
reg [7:0] NextState;
reg [8:0] CRCReceive_timer;
localparam Wait_for_Transmit_Request = 8'b00000001;
localparam Reset_RetryCounter = 8'b00000010;
localparam Construct_Message = 8'b00000100;
localparam Wait_for_PHY_response = 8'b00001000;
localparam Match_MessageID = 8'b00010000;
localparam Check_RetryCounter = 8'b00100000;
localparam Report_Failure = 8'b01000000;
localparam Report_Success = 8'b10000000;
localparam nRetryCounter = 2'b10; //definir el valor maximo
// Logica prox estado
always@( * )
begin
NextState = CurrentState;
case(CurrentState)
Wait_for_Transmit_Request:
begin
if(PRL_Rx_Message_Discard || Hard_Reset_received || Cable_Reset_received) begin NextState = Reset_RetryCounter; end
end
Reset_RetryCounter:
begin
NextState = Construct_Message;
end
Construct_Message:
begin
NextState = Wait_for_PHY_response;
end
Wait_for_PHY_response:
begin
if (GoodCRC_Response_from_PHY) NextState = Match_MessageID;
else if(Message_discarded_bus_Idle || CRCReceiveTimer_Timeout) NextState= Check_RetryCounter;
end
Match_MessageID:
begin
if(MessageID_mismatch || SOP_mismatch) NextState = Check_RetryCounter;
else if(MessageID_SOP_match) NextState = Report_Success;
end
Check_RetryCounter:
begin
if(RetryCounter_bigger) NextState = Report_Failure;
else if(RetryCounter_smaller) NextState = Construct_Message;
end
Report_Success:
begin
NextState = Wait_for_Transmit_Request;
end
Report_Failure:
begin
NextState = Wait_for_Transmit_Request;
end
endcase
// if (CurrentState==Reset_RetryCounter) RetryCounter=0;
//else if (CurrentState==Check_RetryCounter) RetryCounter = RetryCounter+1;
end
// Logica de salidas
assign TRANSMIT_BYTE_COUNT = CurrentState==0;
assign TRANSMIT_HEADER_LOW=0;
assign TRANSMIT_HEADER_HIGH=0;
assign TRANSMIT_DATA_OBJECTS=0;
assign Start_CRCReceiveTimer = CurrentState==Wait_for_PHY_response;
assign Stop_CRCReceiverTimer = CurrentState== Match_MessageID;
assign MessageIDCounter = CurrentState==Match_MessageID;
assign MessageID_mismatch = (CurrentState==Match_MessageID) && (TX_BUF_HEADER_BYTE_1 != RX_BUF_HEADER_BYTE_1);
assign SOP_mismatch = (CurrentState==Match_MessageID) && (TRANSMIT[2:0] != RX_BUF_FRAME_TYPE);
assign MessageID_SOP_match = !MessageID_mismatch && !SOP_mismatch;
assign RetryCounter_bigger = RetryCounter>=nRetryCounter && CurrentState==Check_RetryCounter;
assign RetryCounter_smaller = RetryCounter<nRetryCounter && CurrentState==Check_RetryCounter;
assign ALERT_TransmitSOP_MessageFailed= CurrentState==Report_Failure;
assign ALERT_TransmitSuccessful= CurrentState==Report_Success;
// Cambio de estado
always@(posedge CLK)
begin
if(RESET) CurrentState <= Wait_for_Transmit_Request;
else CurrentState <= NextState;
end
endmodule
|
module helloworld_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
);
// make reset active high
wire rst = ~rst_n;
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
// LEDs 7 is rst, 6:0 is off
assign led[7] = rst;
assign led[6:0] = 7'b0;
// AVR Serial Interface
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx), // FPGA tx goes to AVR rx
.rx(avr_tx),
.channel(4'd15), // invalid channel disables the ADC
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
helloworld helloworld (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v1_9_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v1_9_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v1_9_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
module emesh_mux (/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
access_in, packet_in, wait_in
);
//#####################################################################
//# PARAMETERS
//#####################################################################
parameter AW = 32;
parameter PW = 2 * AW + 40;
parameter N = 99;
parameter CFG = "STATIC"; //Arbitration configuration
//"STATIC" fixed priority
//"DYNAMIC" round robin priority
//#####################################################################
//# INTERFACE
//#####################################################################
//Incoming transaction
input [N-1:0] access_in;
input [N*PW-1:0] packet_in;
output [N-1:0] wait_out;
//Outgoing transaction
output access_out;
output [PW-1:0] packet_out;
input wait_in;
//#####################################################################
//# BODY
//#####################################################################
//local variables
wire [N-1:0] grants;
reg [PW-1:0] packet_out;
integer i;
//arbiter
generate
if(CFG=="STATIC")
begin : arbiter_static
oh_arbiter #(.N(N))
arbiter(// Outputs
.grants (grants[N-1:0]),
// Inputs
.requests (access_in[N-1:0])
);
end
else if (CFG=="DYNAMIC")
begin : arbiter_dynamic
`ifdef TARGET_SIM
initial
$display("ROUND ROBIN ARBITER NOT IMPLEMENTED\n");
`endif
end
endgenerate
//access signal
assign access_out = |(access_in[N-1:0]);
//raise wait signals
assign wait_out[N-1:0] = access_in[N-1:0] & (~grants[N-1:0] | {(N){wait_in}});
//parametrized mux
always @*
begin
packet_out[PW-1:0] = 'b0;
for(i=0;i<N;i=i+1)
packet_out[PW-1:0] = packet_out[PW-1:0] | {(PW){grants[i]}} & packet_in[((i+1)*PW-1)-:PW];
end
endmodule // mesh_mux
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "../../vtr/dff/dff.sim.v"
`include "../dsp_combinational/dsp_combinational.sim.v"
/* DSP Block with register on both the inputs and the output */
module DSP_INOUT_REGISTERED (clk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire clk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Input registers */
(* pack = "DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_a;
(* pack = "DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_b;
(* pack = "DFF-DSP" *)
wire q_m;
genvar i;
for (i=0; i<DATA_WIDTH/2; i=i+1) begin: input_dffs_gen
DFF q_a_ff(.D(a[i]), .Q(q_a[i]), .CLK(clk));
DFF q_b_ff(.D(b[i]), .Q(q_b[i]), .CLK(clk));
end
DFF m_ff(.D(m), .Q(q_m), .CLK(clk));
/* Combinational logic */
(* pack = "DFF-DSP" *)
wire [DATA_WIDTH-1:0] c_out;
DSP_COMBINATIONAL comb (.a(q_a), .b(q_b), .m(q_m), .out(c_out));
/* Output register */
wire [DATA_WIDTH-1:0] q_out;
genvar j;
for (j=0; j<DATA_WIDTH; j=j+1) begin: output_dffs_gen
DFF q_out_ff(.D(c_out[j]), .Q(out[j]), .CLK(clk));
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_FUNCTIONAL_V |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: testIm_rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module testIm_rom (
address,
clock,
q);
input [9:0] address;
input clock;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({9{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../Software/testIm6.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../Software/testIm.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "9"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../Software/testIm.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL testIm_rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: addr_arbiter_sasd.v
//
// Description:
// Hybrid priority + round-robin arbiter.
// Read & write requests combined (read preferred) at each slot
// Muxes AR and AW channel payload inputs based on arbitration results.
//-----------------------------------------------------------------------------
//
// Structure:
// addr_arbiter_sasd
// mux_enc
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_addr_arbiter_sasd #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 1,
parameter integer C_NUM_S_LOG = 1,
parameter integer C_AMESG_WIDTH = 1,
parameter C_GRANT_ENC = 0,
parameter [C_NUM_S*32-1:0] C_ARB_PRIORITY = {C_NUM_S{32'h00000000}}
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 'h0-'hF.
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_AWMESG,
input wire [C_NUM_S*C_AMESG_WIDTH-1:0] S_ARMESG,
input wire [C_NUM_S-1:0] S_AWVALID,
output wire [C_NUM_S-1:0] S_AWREADY,
input wire [C_NUM_S-1:0] S_ARVALID,
output wire [C_NUM_S-1:0] S_ARREADY,
// Master Ports
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC,
output wire [C_NUM_S-1:0] M_GRANT_HOT,
output wire M_GRANT_RNW,
output wire M_GRANT_ANY,
output wire M_AWVALID,
input wire M_AWREADY,
output wire M_ARVALID,
input wire M_ARREADY
);
// Generates a mask for all input slots that are priority based
function [C_NUM_S-1:0] f_prio_mask
(
input integer null_arg
);
reg [C_NUM_S-1:0] mask;
integer i;
begin
mask = 0;
for (i=0; i < C_NUM_S; i=i+1) begin
mask[i] = (C_ARB_PRIORITY[i*32+:32] != 0);
end
f_prio_mask = mask;
end
endfunction
// Convert 16-bit one-hot to 4-bit binary
function [3:0] f_hot2enc
(
input [15:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 16'b1010101010101010);
f_hot2enc[1] = |(one_hot & 16'b1100110011001100);
f_hot2enc[2] = |(one_hot & 16'b1111000011110000);
f_hot2enc[3] = |(one_hot & 16'b1111111100000000);
end
endfunction
localparam [C_NUM_S-1:0] P_PRIO_MASK = f_prio_mask(0);
reg m_valid_i;
reg [C_NUM_S-1:0] s_ready_i;
reg [C_NUM_S-1:0] s_awvalid_reg;
reg [C_NUM_S-1:0] s_arvalid_reg;
wire [15:0] s_avalid;
wire m_aready;
wire [C_NUM_S-1:0] rnw;
reg grant_rnw;
reg [C_NUM_S_LOG-1:0] m_grant_enc_i;
reg [C_NUM_S-1:0] m_grant_hot_i;
reg [C_NUM_S-1:0] last_rr_hot;
reg any_grant;
reg any_prio;
reg [C_NUM_S-1:0] which_prio_hot;
reg [C_NUM_S_LOG-1:0] which_prio_enc;
reg [4:0] current_highest;
reg [15:0] next_prio_hot;
reg [C_NUM_S_LOG-1:0] next_prio_enc;
reg found_prio;
wire [C_NUM_S-1:0] valid_rr;
reg [15:0] next_rr_hot;
reg [C_NUM_S_LOG-1:0] next_rr_enc;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
reg found_rr;
wire [C_NUM_S-1:0] next_hot;
wire [C_NUM_S_LOG-1:0] next_enc;
integer i;
wire [C_AMESG_WIDTH-1:0] amesg_mux;
reg [C_AMESG_WIDTH-1:0] m_amesg_i;
wire [C_NUM_S*C_AMESG_WIDTH-1:0] s_amesg;
genvar gen_si;
always @(posedge ACLK) begin
if (ARESET) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else if (|s_ready_i) begin
s_awvalid_reg <= 0;
s_arvalid_reg <= 0;
end else begin
s_arvalid_reg <= S_ARVALID & ~s_awvalid_reg;
s_awvalid_reg <= S_AWVALID & ~s_arvalid_reg & (~S_ARVALID | s_awvalid_reg);
end
end
assign s_avalid = S_AWVALID | S_ARVALID;
assign M_AWVALID = m_valid_i & ~grant_rnw;
assign M_ARVALID = m_valid_i & grant_rnw;
assign S_AWREADY = s_ready_i & {C_NUM_S{~grant_rnw}};
assign S_ARREADY = s_ready_i & {C_NUM_S{grant_rnw}};
assign M_GRANT_ENC = C_GRANT_ENC ? m_grant_enc_i : 0;
assign M_GRANT_HOT = m_grant_hot_i;
assign M_GRANT_RNW = grant_rnw;
assign rnw = S_ARVALID & ~s_awvalid_reg;
assign M_AMESG = m_amesg_i;
assign m_aready = grant_rnw ? M_ARREADY : M_AWREADY;
generate
for (gen_si=0; gen_si<C_NUM_S; gen_si=gen_si+1) begin : gen_mesg_mux
assign s_amesg[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] = rnw[gen_si] ? S_ARMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH] : S_AWMESG[C_AMESG_WIDTH*gen_si +: C_AMESG_WIDTH];
end // gen_mesg_mux
if (C_NUM_S>1) begin : gen_arbiter
/////////////////////////////////////////////////////////////////////////////
// Grant a new request when there is none still pending.
// If no qualified requests found, de-assert M_VALID.
/////////////////////////////////////////////////////////////////////////////
assign M_GRANT_ANY = any_grant;
assign next_hot = found_prio ? next_prio_hot : next_rr_hot;
assign next_enc = found_prio ? next_prio_enc : next_rr_enc;
always @(posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 0;
s_ready_i <= 0;
m_grant_hot_i <= 0;
m_grant_enc_i <= 0;
any_grant <= 1'b0;
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 0;
if (m_valid_i) begin
// Stall 1 cycle after each master-side completion.
if (m_aready) begin // Master-side completion
m_valid_i <= 1'b0;
m_grant_hot_i <= 0;
any_grant <= 1'b0;
end
end else if (any_grant) begin
m_valid_i <= 1'b1;
s_ready_i <= m_grant_hot_i; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else begin
if (found_prio | found_rr) begin
m_grant_hot_i <= next_hot;
m_grant_enc_i <= next_enc;
any_grant <= 1'b1;
grant_rnw <= |(rnw & next_hot);
if (~found_prio) begin
last_rr_hot <= next_rr_hot;
end
end
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Fixed Priority arbiter
// Selects next request to grant from among inputs with PRIO > 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin : ALG_PRIO
integer ip;
any_prio = 1'b0;
which_prio_hot = 0;
which_prio_enc = 0;
current_highest = 0;
for (ip=0; ip < C_NUM_S; ip=ip+1) begin
if (P_PRIO_MASK[ip] & ({1'b0, C_ARB_PRIORITY[ip*32+:4]} > current_highest)) begin
if (s_avalid[ip]) begin
current_highest[0+:4] = C_ARB_PRIORITY[ip*32+:4];
any_prio = 1'b1;
which_prio_hot = 1'b1 << ip;
which_prio_enc = ip;
end
end
end
found_prio = any_prio;
next_prio_hot = which_prio_hot;
next_prio_enc = which_prio_enc;
end
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
assign valid_rr = ~P_PRIO_MASK & s_avalid;
always @ * begin : ALG_RR
integer ir, jr, nr;
next_rr_hot = 0;
for (ir=0;ir<C_NUM_S;ir=ir+1) begin
nr = (ir>0) ? (ir-1) : (C_NUM_S-1);
carry_rr[ir*C_NUM_S] = last_rr_hot[nr];
mask_rr[ir*C_NUM_S] = ~valid_rr[nr];
for (jr=1;jr<C_NUM_S;jr=jr+1) begin
nr = (ir-jr > 0) ? (ir-jr-1) : (C_NUM_S+ir-jr-1);
carry_rr[ir*C_NUM_S+jr] = carry_rr[ir*C_NUM_S+jr-1] | (last_rr_hot[nr] & mask_rr[ir*C_NUM_S+jr-1]);
if (jr < C_NUM_S-1) begin
mask_rr[ir*C_NUM_S+jr] = mask_rr[ir*C_NUM_S+jr-1] & ~valid_rr[nr];
end
end
next_rr_hot[ir] = valid_rr[ir] & carry_rr[(ir+1)*C_NUM_S-1];
end
next_rr_enc = f_hot2enc(next_rr_hot);
found_rr = |(next_rr_hot);
end
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY ("rtl"),
.C_RATIO (C_NUM_S),
.C_SEL_WIDTH (C_NUM_S_LOG),
.C_DATA_WIDTH (C_AMESG_WIDTH)
) si_amesg_mux_inst
(
.S (next_enc),
.A (s_amesg),
.O (amesg_mux),
.OE (1'b1)
);
always @(posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~any_grant) begin
m_amesg_i <= amesg_mux;
end
end
end else begin : gen_no_arbiter
assign M_GRANT_ANY = m_grant_hot_i;
always @ (posedge ACLK) begin
if (ARESET) begin
m_valid_i <= 1'b0;
s_ready_i <= 1'b0;
m_grant_enc_i <= 0;
m_grant_hot_i <= 1'b0;
grant_rnw <= 1'b0;
end else begin
s_ready_i <= 1'b0;
if (m_valid_i) begin
if (m_aready) begin
m_valid_i <= 1'b0;
m_grant_hot_i <= 1'b0;
end
end else if (m_grant_hot_i) begin
m_valid_i <= 1'b1;
s_ready_i[0] <= 1'b1; // Assert S_AW/READY for 1 cycle to complete SI address transfer
end else if (s_avalid[0]) begin
m_grant_hot_i <= 1'b1;
grant_rnw <= rnw[0];
end
end
end
always @ (posedge ACLK) begin
if (ARESET) begin
m_amesg_i <= 0;
end else if (~m_grant_hot_i) begin
m_amesg_i <= s_amesg;
end
end
end // gen_arbiter
endgenerate
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI_MASTER
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_MASTER#
(
parameter integer m = 15 // Data packet size
)
(
input clk,
input wire RST,
output reg EN_TX=0,
input ce,
output wire LOAD,
input st,
output wire SCLK,
input MISO,
output wire MOSI,
input [m-1:0] TX_MD,
output reg [m-1:0] RX_SD=0,
input LEFT,
output wire CEfront,
output wire CEspad
);
reg [m-1:0] MQ=0 ; //Ðåãèñòð ñäâèãà âûõîäíûõ äàííûõ MASTER-à
reg [m-1:0] MRX=0 ; //Ðåãèñòð ñäâèãà âõîäíûõ äàííûõ MASTER-à
reg ss = 0;
reg [5:0] T_del = 0;
reg [3:0] cb_bit=0; //Ñ÷åò÷èê áèò
assign MOSI = LEFT ? MQ[m-1] : MQ[0] ; // Âûõîäíûå äàííûå MASTER-à
assign LOAD = !EN_TX; // Èíòåðâàë ïåðåäà÷è/ïðèåìà
assign SCLK = EN_TX & ce;
reg st_buf = 1'b0;
always @(posedge ce) begin
if (!EN_TX & st) begin
st_buf <= 1'b1;
end
else begin
st_buf <= 1'b0;
end
end
always @(negedge ce) begin
MQ <= st_buf? TX_MD : LEFT ? MQ<<1 : MQ>>1;
EN_TX <= (cb_bit == (m-1))? 0 : st_buf? 1'b1 : EN_TX;
cb_bit <= st_buf? 0 : cb_bit + 4'd1 ;
end
reg wready = 1'b0;
always @(posedge ce) begin
MRX <= (EN_TX == 1'b1) ? MRX<<1 | MISO : 0;
if (RST == 1'b1) begin
RX_SD <= 0;
wready <= 1'b0;
end
else if (EN_TX == 1'b0) begin
if (wready == 1'b0) begin
RX_SD <= MRX;
end
wready <= 1'b1;
end
else begin
wready <= 1'b0;
RX_SD <= RX_SD;
end
end
//always @(posedge LOAD) begin
//end
endmodule |
/*
* LCD controller for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* Portions of code borrowed from Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_lcd_fml #(
parameter fml_depth = 20 // 1MB Video Memory
) (
input clk, // 100 Mhz clock
input rst,
input shift_reg1, // if set: 320x200
input graphics_alpha, // if not set: 640x400 text mode
// VGA LCD FML master interface
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_we,
input fml_ack,
output [1:0] fml_sel,
output [15:0] fml_do,
input [15:0] fml_di,
// VGA LCD Direct Cache Bus
output reg dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [15:0] dcb_dat,
input dcb_hit,
// attribute_ctrl
input [3:0] pal_addr,
input pal_we,
output [7:0] pal_read,
input [7:0] pal_write,
// dac_regs
input dac_we,
input [1:0] dac_read_data_cycle,
input [7:0] dac_read_data_register,
output [3:0] dac_read_data,
input [1:0] dac_write_data_cycle,
input [7:0] dac_write_data_register,
input [3:0] dac_write_data,
// VGA pad signals
output [3:0] vga_red_o,
output [3:0] vga_green_o,
output [3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// Base address of video memory
input [15:0] start_addr,
// CRTC
input [5:0] cur_start,
input [5:0] cur_end,
input [4:0] vcursor,
input [6:0] hcursor,
input [6:0] horiz_total,
input [6:0] end_horiz,
input [6:0] st_hor_retr,
input [4:0] end_hor_retr,
input [9:0] vert_total,
input [9:0] end_vert,
input [9:0] st_ver_retr,
input [3:0] end_ver_retr,
input x_dotclockdiv2,
// retrace signals
output v_retrace,
output vh_retrace,
output vga_clk
);
// Registers and nets
// Hookup crtc output stage to sequencer input stage
wire [9:0] h_count; // Horizontal pipeline delay is 2 cycles
wire horiz_sync_i;
wire [9:0] v_count; // 0 to VER_SCAN_END
wire vert_sync_crtc_o;
wire video_on_h_i;
wire video_on_v;
// Hookup sequencer output stage to fifo input stage
wire [11:0] fb_dat_i;
wire horiz_sync_seq_o;
wire vert_sync_seq_o;
wire video_on_h_seq_o;
wire video_on_v_seq_o;
wire [7:0] character_seq_o;
// Hookup fifo output stage to pal_dac input stage
wire [11:0] fb_dat_o;
wire fb_horiz_sync_seq_o;
wire fb_vert_sync_seq_o;
wire fb_video_on_h_seq_o;
wire fb_video_on_v_seq_o;
wire [7:0] fb_character_seq_o;
// Pixel buffer control
wire read_fifo;
wire fill_fifo;
// Number of words stored in the FIFO, 0-63 (64 possible values)
wire [9:0] fifo_level;
wire fifo_empty;
wire fifo_full;
// Each stage is controlled by enable signals
wire en_crtc;
wire en_sequencer;
wire en_pal_dac;
reg next_crtc_seq_cyc;
reg next_pal_dac_cyc;
// Pixel clock counter
reg [1:0] pixel_clk_counter;
// LCD FSM Registers
reg fifo_source_cache;
wire can_burst;
wire [17:1] lcd_adr;
wire lcd_stb;
// Module instances
vga_crtc_fml crtc (
.clk (clk), // 100 Mhz clock
.rst (rst),
.enable_crtc (en_crtc),
// CRTC configuration signals
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
// CRTC output signals
.h_count (h_count),
.horiz_sync_i (horiz_sync_i),
.v_count (v_count),
.vert_sync (vert_sync_crtc_o),
.video_on_h_i (video_on_h_i),
.video_on_v (video_on_v)
);
vga_sequencer_fml sequencer (
.clk (clk), // 100 Mhz clock
.rst (rst),
.enable_sequencer (en_sequencer),
// Sequencer input signals
.h_count (h_count),
.horiz_sync_i (horiz_sync_i),
.v_count (v_count),
.vert_sync (vert_sync_crtc_o),
.video_on_h_i (video_on_h_i),
.video_on_v (video_on_v),
// Sequencer configuration signals
.shift_reg1 (shift_reg1), // if set: 320x200
.graphics_alpha (graphics_alpha), // if not set: 640x400 text mode
// CSR slave interface for reading
.fml_adr_o (lcd_adr),
.fml_dat_i (fifo_source_cache ? dcb_dat : fml_di),
.fml_stb_o (lcd_stb),
// CRTC
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.x_dotclockdiv2 (x_dotclockdiv2),
// Sequencer output signals
.horiz_sync_seq_o (horiz_sync_seq_o),
.vert_sync_seq_o (vert_sync_seq_o),
.video_on_h_seq_o (video_on_h_seq_o),
.video_on_v_seq_o (video_on_v_seq_o),
.character_seq_o (character_seq_o)
);
// video-data buffer (temporary store data read from video memory)
// We want to store at least one scan line (512 pixels x 12 bits per pixel) in the buffer
vga_fifo #(9, 12) data_fifo (
.clk ( clk ),
.aclr ( 1'b1 ),
.sclr ( rst ),
.d ( fb_dat_i ),
.wreq ( fill_fifo ),
.q ( fb_dat_o ),
.rreq ( read_fifo ),
.nword ( fifo_level ),
.empty ( fifo_empty ),
.full ( fifo_full ),
.aempty ( ),
.afull ( )
);
vga_pal_dac_fml pal_dac (
.clk (clk), // 100 Mhz clock
.rst (rst),
.enable_pal_dac (en_pal_dac),
// VGA PAL/DAC input signals
.horiz_sync_pal_dac_i (fb_horiz_sync_seq_o),
.vert_sync_pal_dac_i (fb_vert_sync_seq_o),
.video_on_h_pal_dac_i (fb_video_on_h_seq_o),
.video_on_v_pal_dac_i (fb_video_on_v_seq_o),
.character_pal_dac_i (fb_character_seq_o),
// VGA PAL/DAC configuration signals
.shift_reg1 (shift_reg1), // if set: 320x200
.graphics_alpha (graphics_alpha), // if not set: 640x400 text mode
// attribute_ctrl
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
// dac_regs
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
// VGA PAL/DAC output signals
// VGA pad signals
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (vert_sync),
// retrace signals
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
// Continuous assignments
// The lcd is read only device and these control signals are not used
assign fml_sel = 2'b11;
assign fml_do = 16'b0;
// Pack sequencer stage output into one wire group
assign fb_dat_i = { horiz_sync_seq_o,
vert_sync_seq_o,
video_on_h_seq_o,
video_on_v_seq_o,
character_seq_o[7:0] };
// Unpack fb_dat_o back into seperate wires
assign fb_horiz_sync_seq_o = fb_dat_o [11];
assign fb_vert_sync_seq_o = fb_dat_o [10];
assign fb_video_on_h_seq_o = fb_dat_o [9];
assign fb_video_on_v_seq_o = fb_dat_o [8];
assign fb_character_seq_o = fb_dat_o [7:0];
// Wait until the fifo level is <= 300 (enough room for a 212 pixel burst)
assign can_burst = fifo_level <= 10'd300;
// These signals enable and control when the next crtc/sequencer cycle should occur
assign en_crtc = next_crtc_seq_cyc;
assign en_sequencer = next_crtc_seq_cyc;
// When the next_crtc_seq_cyc occurs we should place another pixel in fifo
assign fill_fifo = next_crtc_seq_cyc;
// This signal enables and controls when we should read from the fifo
// We must first wait until something is in the fifo!!!
assign read_fifo = next_pal_dac_cyc & !fifo_empty;
// This signal enables and controls when the next pal_dac cycle should occure
// We must first wait until something is in the fifo!!!
assign en_pal_dac = next_pal_dac_cyc & !fifo_empty; // 100 Mhz version
// This is the vga_clk signal
// No matter what happens, we must keep the vga_clk going!!!
assign vga_clk = next_pal_dac_cyc;
// Behaviour
/* FML ADDRESS GENERATOR */
wire next_address;
always @(posedge clk) begin
if(rst) begin
fml_adr <= {fml_depth{1'b0}};
end else begin
if(next_address) begin
fml_adr[19:0] <= { (lcd_adr + { start_addr[15:1], 2'b00 }), 1'b0 };
end
end
end
/* DCB ADDRESS GENERATOR */
reg [2:0] dcb_index;
always @(posedge clk) begin
if(dcb_stb)
dcb_index <= dcb_index + 3'd1;
else
dcb_index <= fml_adr[2:0];
end
assign dcb_adr = { fml_adr + ( { dcb_index, 1'b0 } ) };
/* CONTROLLER */
reg [4:0] state;
reg [4:0] next_state;
localparam [4:0]
IDLE = 5'd0,
DELAY = 5'b1,
TRYCACHE = 5'd2,
CACHE1 = 5'd3,
CACHE2 = 5'd4,
CACHE3 = 5'd5,
CACHE4 = 5'd6,
CACHE5 = 5'd7,
CACHE6 = 5'd8,
CACHE7 = 5'd9,
CACHE8 = 5'd10,
FML1 = 5'd11,
FML2 = 5'd12,
FML3 = 5'd13,
FML4 = 5'd14,
FML5 = 5'd15,
FML6 = 5'd16,
FML7 = 5'd17,
FML8 = 5'd18;
always @(posedge clk) begin
if(rst)
state <= IDLE;
else
state <= next_state;
end
reg next_burst;
assign next_address = next_burst;
always @(*) begin
next_state = state;
next_crtc_seq_cyc = 1'b0;
next_burst = 1'b0;
fml_stb = 1'b0;
dcb_stb = 1'b0;
fifo_source_cache = 1'b0;
case(state)
IDLE: begin
if (can_burst & !fifo_full) begin
if (lcd_stb) begin
/* LCD is requesting another fml burst ! */
next_burst = 1'b1; // This also calculates final address
next_crtc_seq_cyc = 1'b1;
next_state = DELAY;
end else
next_crtc_seq_cyc = 1'b1;
end
end
DELAY: begin
next_crtc_seq_cyc = 1'b1;
next_state = TRYCACHE;
end
/* Try to fetch from L2 first */
TRYCACHE: begin
dcb_stb = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE1;
end
CACHE1: begin
fifo_source_cache = 1'b1;
if(dcb_hit) begin
dcb_stb = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE2;
end else
next_state = FML1; /* Not in L2 cache, fetch from DRAM */
end
/* No need to check for cache hits anymore:
* - we fetched from the beginning of a line
* - we fetch exactly a line
* - we do not release dcb_stb so the cache controller locks the line
* Therefore, next 7 fetchs always are cache hits.
*/
CACHE2: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE3;
end
CACHE3: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE4;
end
CACHE4: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE5;
end
CACHE5: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE6;
end
CACHE6: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE7;
end
CACHE7: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = CACHE8;
end
CACHE8: begin
fifo_source_cache = 1'b1;
next_crtc_seq_cyc = 1'b1;
next_state = IDLE;
end
FML1: begin
fml_stb = 1'b1;
if(fml_ack) begin
next_crtc_seq_cyc = 1'b1;
next_state = FML2;
end
end
FML2: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML3;
end
FML3: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML4;
end
FML4: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML5;
end
FML5: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML6;
end
FML6: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML7;
end
FML7: begin
next_crtc_seq_cyc = 1'b1;
next_state = FML8;
end
FML8: begin
next_crtc_seq_cyc = 1'b1;
next_state = IDLE;
end
endcase
end
// Provide counter for pal_dac stage
always @(posedge clk)
if (rst)
begin
pixel_clk_counter <= 2'b00;
end
else
begin
if (pixel_clk_counter == 2'd00) // Toggle next_pal_dac_cyc
next_pal_dac_cyc <=1'b1;
else next_pal_dac_cyc <= 1'b0;
pixel_clk_counter <= pixel_clk_counter + 2'b01; // Roll over every four cycles
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_TB_V
`define SKY130_FD_SC_HS__A22OI_TB_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A1 = 1'b1;
#160 A2 = 1'b1;
#180 B1 = 1'b1;
#200 B2 = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A1 = 1'b0;
#280 A2 = 1'b0;
#300 B1 = 1'b0;
#320 B2 = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 B2 = 1'b1;
#440 B1 = 1'b1;
#460 A2 = 1'b1;
#480 A1 = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 B2 = 1'bx;
#560 B1 = 1'bx;
#580 A2 = 1'bx;
#600 A1 = 1'bx;
end
sky130_fd_sc_hs__a22oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_TB_V
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 06/29/2009
This block is responsible for accepting 128/256 bit descriptors and
buffering them in descriptor FIFOs. Each bytelane of the descriptor
can be written to individually and writing ot the descriptor 'go' bit
commits the data into the FIFO. Reading that data out of the FIFO
occurs two cycles after the read is asserted as the FIFOs do not support
lookahead mode.
This block must keep local copies of per descriptor information like
the optional sequence number or interrupt masks. When parked mode
is set in the descriptor the same will transfer multiple times when
the descriptor FIFO only contains one descriptor (and this descriptor
will not be popped). Parked mode is useful for video frame buffering.
1.0 - The on-chip memory in the FIFOs are not inferred so there may
be some extra unused bits. In a later Quartus II release the
on-chip memory will be replaced with inferred memory.
1.1 - Shifted all descriptor registers into this block (from the dispatcher
block). Added breakout blocks responsible for re-packing the
information for use by each master.
1.2 - Added the read_early_done_enable bit to the breakout (for debug)
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_buffers (
clk,
reset,
writedata,
write,
byteenable,
waitrequest,
read_command_valid,
read_command_ready,
read_command_data,
read_command_empty,
read_command_full,
read_command_used,
write_command_valid,
write_command_ready,
write_command_data,
write_command_empty,
write_command_full,
write_command_used,
stop_issuing_commands,
stop,
sw_reset,
sequence_number,
transfer_complete_IRQ_mask,
early_termination_IRQ_mask,
error_IRQ_mask
);
parameter MODE = 0;
parameter DATA_WIDTH = 256;
parameter BYTE_ENABLE_WIDTH = 32;
parameter FIFO_DEPTH = 128;
parameter FIFO_DEPTH_LOG2 = 7; // top level module can figure this out
input clk;
input reset;
input [DATA_WIDTH-1:0] writedata;
input write;
input [BYTE_ENABLE_WIDTH-1:0] byteenable;
output wire waitrequest;
output wire read_command_valid;
input read_command_ready;
output wire [255:0] read_command_data;
output wire read_command_empty;
output wire read_command_full;
output wire [FIFO_DEPTH_LOG2:0] read_command_used;
output wire write_command_valid;
input write_command_ready;
output wire [255:0] write_command_data;
output wire write_command_empty;
output wire write_command_full;
output wire [FIFO_DEPTH_LOG2:0] write_command_used;
input stop_issuing_commands;
input stop;
input sw_reset;
output wire [31:0] sequence_number;
output wire transfer_complete_IRQ_mask;
output wire early_termination_IRQ_mask;
output wire [7:0] error_IRQ_mask;
/* Internal wires and registers */
reg write_command_empty_d1;
reg write_command_empty_d2;
reg read_command_empty_d1;
reg read_command_empty_d2;
wire push_write_fifo;
wire pop_write_fifo;
wire push_read_fifo;
wire pop_read_fifo;
wire go_bit;
wire read_park;
wire read_park_enable; // park is enabled when read_park is enabled and the read FIFO is empty
wire write_park;
wire write_park_enable; // park is enabled when write_park is enabled and the write FIFO is empty
wire [DATA_WIDTH-1:0] write_fifo_output;
wire [DATA_WIDTH-1:0] read_fifo_output;
wire [15:0] write_sequence_number;
reg [15:0] write_sequence_number_d1;
wire [15:0] read_sequence_number;
reg [15:0] read_sequence_number_d1;
wire read_transfer_complete_IRQ_mask;
reg read_transfer_complete_IRQ_mask_d1;
wire write_transfer_complete_IRQ_mask;
reg write_transfer_complete_IRQ_mask_d1;
wire write_early_termination_IRQ_mask;
reg write_early_termination_IRQ_mask_d1;
wire [7:0] write_error_IRQ_mask;
reg [7:0] write_error_IRQ_mask_d1;
wire issue_write_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
wire issue_read_descriptor; // one cycle strobe used to indicate when there is a valid write descriptor ready to be sent to the write master
/* Unused signals that are provided for debug convenience */
wire [31:0] read_address;
wire [31:0] read_length;
wire [7:0] read_transmit_channel;
wire read_generate_sop;
wire read_generate_eop;
wire [7:0] read_burst_count;
wire [15:0] read_stride;
wire [7:0] read_transmit_error;
wire read_early_done_enable;
wire [31:0] write_address;
wire [31:0] write_length;
wire write_end_on_eop;
wire [7:0] write_burst_count;
wire [15:0] write_stride;
/************************************************* Registers *******************************************************/
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_sequence_number_d1 <= 0;
write_transfer_complete_IRQ_mask_d1 <= 0;
write_early_termination_IRQ_mask_d1 <= 0;
write_error_IRQ_mask_d1 <= 0;
end
else if (issue_write_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
write_sequence_number_d1 <= write_sequence_number;
write_transfer_complete_IRQ_mask_d1 <= write_transfer_complete_IRQ_mask;
write_early_termination_IRQ_mask_d1 <= write_early_termination_IRQ_mask;
write_error_IRQ_mask_d1 <= write_error_IRQ_mask;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
read_sequence_number_d1 <= 0;
read_transfer_complete_IRQ_mask_d1 <= 0;
end
else if (issue_read_descriptor) // if parked mode is enabled and there are no more descriptors buffered then this will not fire when the command is sent out
begin
read_sequence_number_d1 <= read_sequence_number;
read_transfer_complete_IRQ_mask_d1 <= read_transfer_complete_IRQ_mask;
end
end
// need to use a delayed valid signal since the commmand buffers have two cycles of latency
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
write_command_empty_d1 <= 0;
write_command_empty_d2 <= 0;
read_command_empty_d1 <= 0;
read_command_empty_d2 <= 0;
end
else
begin
write_command_empty_d1 <= write_command_empty;
write_command_empty_d2 <= write_command_empty_d1;
read_command_empty_d1 <= read_command_empty;
read_command_empty_d2 <= read_command_empty_d1;
end
end
/*********************************************** End Registers *****************************************************/
/****************************************** Module Instantiations **************************************************/
/* the write_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
write_signal_breakout the_write_signal_breakout (
.write_command_data_in (write_fifo_output),
.write_command_data_out (write_command_data),
.write_address (write_address),
.write_length (write_length),
.write_park (write_park),
.write_end_on_eop (write_end_on_eop),
.write_transfer_complete_IRQ_mask (write_transfer_complete_IRQ_mask),
.write_early_termination_IRQ_mask (write_early_termination_IRQ_mask),
.write_error_IRQ_mask (write_error_IRQ_mask),
.write_burst_count (write_burst_count),
.write_stride (write_stride),
.write_sequence_number (write_sequence_number),
.write_stop (stop),
.write_sw_reset (sw_reset)
);
defparam the_write_signal_breakout.DATA_WIDTH = DATA_WIDTH;
/* the read_signal_break module simply takes the output of the descriptor buffer and reformats the data
* to be sent in the command format needed by the master command port. If new features are added to the
* descriptor format then add it to this block. This block also provides the descriptor information
* using a naming convention isn't of bit indexes in a 256 bit wide command signal.
*/
read_signal_breakout the_read_signal_breakout (
.read_command_data_in (read_fifo_output),
.read_command_data_out (read_command_data),
.read_address (read_address),
.read_length (read_length),
.read_transmit_channel (read_transmit_channel),
.read_generate_sop (read_generate_sop),
.read_generate_eop (read_generate_eop),
.read_park (read_park),
.read_transfer_complete_IRQ_mask (read_transfer_complete_IRQ_mask),
.read_burst_count (read_burst_count),
.read_stride (read_stride),
.read_sequence_number (read_sequence_number),
.read_transmit_error (read_transmit_error),
.read_early_done_enable (read_early_done_enable),
.read_stop (stop),
.read_sw_reset (sw_reset)
);
defparam the_read_signal_breakout.DATA_WIDTH = DATA_WIDTH;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_read_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_read_fifo),
.read_data (read_fifo_output),
.pop (pop_read_fifo),
.used (read_command_used), // this is a 'true used' signal with the full bit accounted for
.full (read_command_full),
.empty (read_command_empty)
);
defparam the_read_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_read_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_read_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_read_command_FIFO.LATENCY = 2;
// Descriptor FIFO allows for each byte lane to be written to and the data is not committed to the FIFO until the 'push' signal is asserted.
// This differs from scfifo which commits the data any time the write signal is asserted.
fifo_with_byteenables the_write_command_FIFO (
.clk (clk),
.areset (reset),
.sreset (sw_reset),
.write_data (writedata),
.write_byteenables (byteenable),
.write (write),
.push (push_write_fifo),
.read_data (write_fifo_output),
.pop (pop_write_fifo),
.used (write_command_used), // this is a 'true used' signal with the full bit accounted for
.full (write_command_full),
.empty (write_command_empty)
);
defparam the_write_command_FIFO.DATA_WIDTH = DATA_WIDTH; // we are not actually going to use all these bits and byte lanes left unconnected at the output will get optimized away
defparam the_write_command_FIFO.FIFO_DEPTH = FIFO_DEPTH;
defparam the_write_command_FIFO.FIFO_DEPTH_LOG2 = FIFO_DEPTH_LOG2;
defparam the_write_command_FIFO.LATENCY = 2;
/**************************************** End Module Instantiations ************************************************/
/****************************************** Combinational Signals **************************************************/
generate // all unnecessary signals and drivers will be optimized away
if (MODE == 0) // MM-->MM
begin
assign waitrequest = (read_command_full == 1) | (write_command_full == 1);
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
else if (MODE == 1) // MM-->ST
begin
// information for the CSR or response blocks to use
assign sequence_number = {16'h0000, read_sequence_number_d1};
assign transfer_complete_IRQ_mask = read_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = 1'b0;
assign error_IRQ_mask = 8'h00;
assign waitrequest = (read_command_full == 1);
// read buffer flow control
assign push_read_fifo = go_bit;
assign read_park_enable = (read_park == 1) & (read_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign read_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(read_command_empty == 0) & (read_command_empty_d1 == 0) & (read_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_read_descriptor = (read_command_valid == 1) & (read_command_ready == 1);
assign pop_read_fifo = (issue_read_descriptor == 1) & (read_park_enable == 0); // don't want to pop the fifo if we are in parked mode
// write buffer flow control
assign push_write_fifo = 0;
assign write_park_enable = 0;
assign write_command_valid = 0;
assign issue_write_descriptor = 0;
assign pop_write_fifo = 0;
end
else // ST-->MM
begin
// information for the CSR or response blocks to use
assign sequence_number = {write_sequence_number_d1, 16'h0000};
assign transfer_complete_IRQ_mask = write_transfer_complete_IRQ_mask_d1;
assign early_termination_IRQ_mask = write_early_termination_IRQ_mask_d1;
assign error_IRQ_mask = write_error_IRQ_mask_d1;
assign waitrequest = (write_command_full == 1);
// read buffer flow control
assign push_read_fifo = 0;
assign read_park_enable = 0;
assign read_command_valid = 0;
assign issue_read_descriptor = 0;
assign pop_read_fifo = 0;
// write buffer flow control
assign push_write_fifo = go_bit;
assign write_park_enable = (write_park == 1) & (write_command_used == 1); // we want to keep the descriptor in the FIFO when the park bit is set
assign write_command_valid = (stop == 0) & (sw_reset == 0) & (stop_issuing_commands == 0) &
(write_command_empty == 0) & (write_command_empty_d1 == 0) & (write_command_empty_d2 == 0); // command buffer has two cycles of latency so the empty deassertion need to delayed two cycles but asserted in zero cycles, the time between commands will be at least 2 cycles so this delay is only needed coming out of the empty condition
assign issue_write_descriptor = (write_command_valid == 1) & (write_command_ready == 1);
assign pop_write_fifo = (issue_write_descriptor == 1) & (write_park_enable == 0); // don't want to pop the fifo if we are in parked mode
end
endgenerate
generate // go bit is in a different location depending on the width of the slave port
if (DATA_WIDTH == 256)
begin
assign go_bit = (writedata[255] == 1) & (write == 1) & (byteenable[31] == 1) & (waitrequest == 0);
end
else
begin
assign go_bit = (writedata[127] == 1) & (write == 1) & (byteenable[15] == 1) & (waitrequest == 0);
end
endgenerate
/**************************************** End Combinational Signals ************************************************/
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_wbs (
input wire clk_50,
input wire reset_n,
// slave wishbone interface (from SDHC)
input wire wbs_clk_i,
input wire [31:0] wbs_adr_i,
output wire [31:0] wbs_dat_o,
input wire [31:0] wbs_dat_i,
input wire [3:0] wbs_sel_i,
input wire wbs_cyc_i,
input wire wbs_stb_i,
input wire wbs_we_i,
output wire wbs_ack_o,
// port to cached block ram
output wire bram_wbs_clk,
output wire [15:0] bram_wbs_addr,
output reg bram_wbs_wren,
output reg [31:0] bram_wbs_data,
input wire [31:0] bram_wbs_q,
input wire logical_init_done,
output reg wb_read,
output reg wb_write,
output reg [9:0] wb_block,
input wire wb_ack,
input wire wb_done
);
`include "ftl_const.vh"
assign bram_wbs_clk = wbs_clk_i;
assign bram_wbs_addr = (wbs_adr_i % NAND_BLOCK_SIZE) / 4;
assign wbs_ack_o = wbs_ack & wbs_stb_i;
assign wbs_dat_o = bram_wbs_q;
reg wbs_ack;
reg wbs_stb_i_1;
reg wb_done_s_1;
wire reset_s;
wire logical_init_done_s;
wire wb_ack_s;
wire wb_done_s;
synch_3 a(reset_n, reset_s, wbs_clk_i);
synch_3 b(logical_init_done, logical_init_done_s, wbs_clk_i);
synch_3 c(wb_ack, wb_ack_s, wbs_clk_i);
synch_3 d(wb_done, wb_done_s, wbs_clk_i);
wire [9:0] req_block = wbs_adr_i / NAND_BLOCK_SIZE;
reg [9:0] req_block_latch;
reg [9:0] cached_block;
reg modified;
reg [3:0] state;
wire ftl_valid = wbs_adr_i >= 32'h200000;
parameter [3:0] ST_RESET = 'd0,
ST_IDLE = 'd1,
ST_READ = 'd2,
ST_WRITE = 'd3,
ST_IDLE_WAIT = 'd5,
ST_READ_DELAY = 'd6;
always @(posedge wbs_clk_i) begin
wbs_ack <= 0;
wbs_stb_i_1 <= wbs_stb_i;
wb_done_s_1 <= wb_done_s;
wb_read <= 0;
wb_write <= 0;
bram_wbs_wren <= 0;
case(state)
ST_RESET: begin
cached_block <= -1;
modified <= 0;
if(logical_init_done_s) state <= ST_IDLE;
end
ST_IDLE: begin
// on rising edge of WBS_STB_I
if(wbs_cyc_i & wbs_stb_i & ~wbs_stb_i_1 & ftl_valid) begin
if(wbs_we_i) begin
if((cached_block == req_block) && modified) begin
// write to bram
bram_wbs_data <= wbs_dat_i;
bram_wbs_wren <= 1;
wbs_ack <= 1;
end else begin
// switch blocks and mark modified
state <= ST_WRITE;
req_block_latch <= req_block;
end
//wbs_ack <= 1;
end else begin
if(cached_block == req_block) begin
// read from bram
state <= ST_READ_DELAY;
end else begin
// switch blocks and mark unmodified
state <= ST_READ;
req_block_latch <= req_block;
end
end
end
end
ST_IDLE_WAIT: begin
wbs_stb_i_1 <= 0; // make idle state fire again
if(~wb_ack_s) state <= ST_IDLE;
end
ST_WRITE: begin
modified <= 1;
wb_block <= req_block_latch;
wb_write <= 1;
if(wb_done_s & ~wb_done_s_1) begin
cached_block <= req_block_latch;
state <= ST_IDLE_WAIT;
end
end
ST_READ: begin
modified <= 0;
wb_block <= req_block_latch;
wb_read <= 1;
if(wb_done_s & ~wb_done_s_1) begin
cached_block <= req_block_latch;
state <= ST_IDLE_WAIT;
end
end
ST_READ_DELAY: begin
// delay for bram
wbs_ack <= 1;
state <= ST_IDLE;
end
endcase
if(~reset_s) begin
state <= ST_RESET;
end
end
endmodule
|
`timescale 1ns / 1ps
/*
* File : uart_clock.v
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* Generate synchronous pulses for 115200 baud and 16x 115200 baud (synchronized)
* from an uncorrelated input clock.
*
* This timing can be adjusted to allow for other baud rates.
*/
module uart_clock(
input clock,
output uart_tick,
output uart_tick_16x
);
/* Goal: Generate a pulse at 115200 Hz using an input clock
* that is not an even multiple of 115200.
*
* Method: Find constants 'a', 'b' such that clock / (2^a / b) ~= 115200.
* Accumulate 'b' each cycle and use the overflow bit 'a' for the pulse.
*
* 66 MHz: 66 MHz / (2^18 / 453) = 115203.857 Hz
* 100 MHz: 100 MHz / (2^17 / 151) = 115203.857 Hz
*
* We also need to extend this for a 16x pulse to over-sample:
*
* 66 MHz: 66 MHz / (2^14 / 453) = 115203.857 Hz * 16
* 100 MHz: 100 MHz / (2^13 / 151) = 115203.857 Hz * 16
*/
// 16x Pulse Generation
// 66 MHz version
reg [14:0] accumulator = 15'h0000;
always @(posedge clock) begin
accumulator <= accumulator[13:0] + 453;
end
assign uart_tick_16x = accumulator[14];
/*
// 100 MHz version
reg [13:0] accumulator = 14'h0000;
always @(posedge clock) begin
accumulator <= accumulator[12:0] + 151;
end
assign uart_tick_16x = accumulator[13];
*/
// 1x Pulse Generation (115200 Hz)
reg [3:0] uart_16x_count = 4'h0;
always @(posedge clock) begin
uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1'b1 : uart_16x_count;
end
assign uart_tick = (uart_tick_16x==1'b1 && (uart_16x_count == 4'b1111));
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_generator_0 (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 core_clk CLK" *)
input wire clk;
input wire srst;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [63 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [63 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v13_1_2 #(
.C_COMMON_CLOCK(1),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(0),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(clk),
.rst(1'D0),
.srst(srst),
.wr_clk(1'D0),
.wr_rst(1'D0),
.rd_clk(1'D0),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
module lsu_non_aligned_write
(
clk, clk2x, reset, o_stall, i_valid, i_address, i_writedata, i_stall, i_byteenable, o_valid,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount, i_nop
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // Memory latency in threads
parameter MEMORY_SIDE_MEM_LATENCY=32;
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USE_WRITE_ACK=0; // Wait till the write has actually made it to global memory
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam NUM_OUTPUT_WORD = MWIDTH_BYTES/WIDTH_BYTES;
localparam NUM_OUTPUT_WORD_W = $clog2(NUM_OUTPUT_WORD);
localparam UNALIGNED_BITS=$clog2(WIDTH_BYTES)-ALIGNMENT_ABITS;
/********
* Ports *
********/
// Standard global signals
input clk;
input clk2x;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Byte enable control
input [WIDTH_BYTES-1:0] i_byteenable;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
input i_nop;
reg reg_lsu_i_valid;
reg [AWIDTH-BYTE_SELECT_BITS-1:0] page_addr_next;
reg [AWIDTH-1:0] reg_lsu_i_address;
reg [WIDTH-1:0] reg_lsu_i_writedata;
reg reg_nop;
reg reg_consecutive;
reg [WIDTH_BYTES-1:0] reg_word_byte_enable;
reg [UNALIGNED_BITS-1:0] shift = 0;
wire stall_int;
assign o_stall = reg_lsu_i_valid & stall_int;
// --------------- Pipeline stage : Consecutive Address Checking --------------------
always@(posedge clk or posedge reset)
begin
if (reset) reg_lsu_i_valid <= 1'b0;
else if (~o_stall) reg_lsu_i_valid <= i_valid;
end
always@(posedge clk) begin
if (~o_stall & i_valid & ~i_nop) begin
reg_lsu_i_address <= i_address;
page_addr_next <= i_address[AWIDTH-1:BYTE_SELECT_BITS] + 1'b1;
shift <= i_address[ALIGNMENT_ABITS+UNALIGNED_BITS-1:ALIGNMENT_ABITS];
reg_lsu_i_writedata <= i_writedata;
reg_word_byte_enable <= USE_BYTE_EN? (i_nop? '0 : i_byteenable) : '1;
end
if (~o_stall) begin
reg_nop <= i_nop;
reg_consecutive <= !i_nop & page_addr_next === i_address[AWIDTH-1:BYTE_SELECT_BITS]
// to simplify logic in lsu_bursting_write
// the new writedata does not overlap with the previous one
& i_address[ALIGNMENT_ABITS+UNALIGNED_BITS-1:ALIGNMENT_ABITS] > shift;
end
end
// -------------------------------------------------------------------
lsu_non_aligned_write_internal #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(1),
.HIGH_FMAX(HIGH_FMAX)
) non_aligned_write (
.clk(clk),
.clk2x(clk2x),
.reset(reset),
.o_stall(stall_int),
.i_valid(reg_lsu_i_valid),
.i_address(reg_lsu_i_address),
.i_writedata(reg_lsu_i_writedata),
.i_stall(i_stall),
.i_byteenable(reg_word_byte_enable),
.o_valid(o_valid),
.o_active(o_active),
.avm_address(avm_address),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest),
.i_nop(reg_nop),
.consecutive(reg_consecutive)
);
endmodule
//
// Non-aligned write wrapper for LSUs
//
module lsu_non_aligned_write_internal
(
clk, clk2x, reset, o_stall, i_valid, i_address, i_writedata, i_stall, i_byteenable, o_valid,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest,
avm_burstcount,
i_nop,
consecutive
);
// Paramaters to pass down to lsu_top
//
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=160; // Determines the max number of live requests.
parameter MEMORY_SIDE_MEM_LATENCY=0; // Determines the max number of live requests.
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USECACHING=0;
parameter USE_WRITE_ACK=0;
parameter TIMEOUT=8;
parameter HIGH_FMAX=1;
parameter USE_BYTE_EN=0;
localparam WIDTH=WIDTH_BYTES*8;
localparam MWIDTH=MWIDTH_BYTES*8;
localparam TRACKING_FIFO_DEPTH=KERNEL_SIDE_MEM_LATENCY+1;
localparam WIDTH_ABITS=$clog2(WIDTH_BYTES);
localparam TIMEOUTBITS=$clog2(TIMEOUT);
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
//
// Suppose that we vectorize 4 ways and are accessing a float4 but are only guaranteed float alignment
//
// WIDTH_BYTES=16 --> $clog2(WIDTH_BYTES) = 4
// ALIGNMENT_ABITS --> 2
// UNALIGNED_BITS --> 2
//
// +----+----+----+----+----+----+
// | X | Y | Z | W | A | B |
// +----+----+----+----+----+----+
// 0000 0100 1000 1100 ...
//
// float4 access at 1000
// requires two aligned access
// 0000 -> mux out Z , W
// 10000 -> mux out A , B
//
localparam UNALIGNED_BITS=$clog2(WIDTH_BYTES)-ALIGNMENT_ABITS;
// How much alignment are we guaranteed in terms of bits
// float -> ALIGNMENT_ABITS=2 -> 4 bytes -> 32 bits
localparam ALIGNMENT_DBYTES=2**ALIGNMENT_ABITS;
localparam ALIGNMENT_DBITS=8*ALIGNMENT_DBYTES;
localparam NUM_WORD = MWIDTH_BYTES/ALIGNMENT_DBYTES;
// -------- Interface Declarations ------------
// Standard global signals
input clk;
input clk2x;
input reset;
input i_nop;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
// Downstream interface
input i_stall;
output o_valid;
output o_active;
// Byte enable control
input [WIDTH_BYTES-1:0] i_byteenable;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output [MWIDTH-1:0] avm_writedata;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// help from outside to track addresses
input consecutive;
// ------- Bursting LSU instantiation ---------
wire lsu_o_stall;
wire lsu_i_valid;
wire [AWIDTH-1:0] lsu_i_address;
wire [2*WIDTH-1:0] lsu_i_writedata;
wire [2*WIDTH_BYTES-1:0] lsu_i_byte_enable;
wire [AWIDTH-BYTE_SELECT_BITS-1:0] i_page_addr = i_address[AWIDTH-1:BYTE_SELECT_BITS];
wire [BYTE_SELECT_BITS-1:0] i_byte_offset=i_address[BYTE_SELECT_BITS-1:0];
reg reg_lsu_i_valid, reg_lsu_i_nop, thread_valid;
reg [AWIDTH-1:0] reg_lsu_i_address;
reg [WIDTH-1:0] reg_lsu_i_writedata, data_2nd;
reg [WIDTH_BYTES-1:0] reg_lsu_i_byte_enable, byte_en_2nd;
wire [UNALIGNED_BITS-1:0] shift;
wire is_access_aligned;
logic issue_2nd_word;
wire stall_int;
assign lsu_o_stall = reg_lsu_i_valid & stall_int;
// Stall out if we
// 1. can't accept the request right now because of fifo fullness or lsu stalls
// 2. we need to issue the 2nd word from previous requests before proceeding to this one
assign o_stall = lsu_o_stall | issue_2nd_word & !i_nop & !consecutive;
// --------- Module Internal State -------------
reg [AWIDTH-BYTE_SELECT_BITS-1:0] next_page_addr;
// The actual requested address going into the LSU
assign lsu_i_address[AWIDTH-1:BYTE_SELECT_BITS] = issue_2nd_word? next_page_addr : i_page_addr;
assign lsu_i_address[BYTE_SELECT_BITS-1:0] = issue_2nd_word? '0 : is_access_aligned? i_address[BYTE_SELECT_BITS-1:0] : {i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS] - shift, {ALIGNMENT_ABITS{1'b0}}};
// The actual data to be written and corresponding byte/bit enables
assign shift = i_address[ALIGNMENT_ABITS+UNALIGNED_BITS-1:ALIGNMENT_ABITS];
assign lsu_i_byte_enable = {{WIDTH_BYTES{1'b0}},i_byteenable} << {shift, {ALIGNMENT_ABITS{1'b0}}};
assign lsu_i_writedata = {{WIDTH{1'b0}},i_writedata} << {shift, {ALIGNMENT_ABITS{1'b0}}, 3'd0};
// Is this request access already aligned .. then no need to do anything special
assign is_access_aligned = (i_address[BYTE_SELECT_BITS-1:0]+ WIDTH_BYTES) <= MWIDTH_BYTES;
assign request = issue_2nd_word | i_valid;
assign lsu_i_valid = i_valid | issue_2nd_word;
// When do we need to issue the 2nd word?
// The previous address needed a 2nd word and the current requested address isn't
// consecutive with the previous
// --- Pipeline before going into the LSU ---
always@(posedge clk or posedge reset)
begin
if (reset) begin
reg_lsu_i_valid <= 1'b0;
thread_valid <= 1'b0;
issue_2nd_word <= 1'b0;
end
else begin
if (~lsu_o_stall) begin
reg_lsu_i_valid <= lsu_i_valid;
thread_valid <= i_valid & (!issue_2nd_word | i_nop | consecutive); // issue_2nd_word should not generate o_valid
issue_2nd_word <= i_valid & !o_stall & !i_nop & !is_access_aligned;
end
else if(!stall_int) issue_2nd_word <= 1'b0;
end
end
// --- -------------------------------------
reg [BYTE_SELECT_BITS-1-ALIGNMENT_ABITS:0]i_2nd_offset;
reg [WIDTH-1:0] i_2nd_data;
reg [WIDTH_BYTES-1:0] i_2nd_byte_en;
reg i_2nd_en;
always @(posedge clk) begin
if(i_valid & ~i_nop & ~o_stall) next_page_addr <= i_page_addr + 1'b1;
if(~lsu_o_stall) begin
reg_lsu_i_address <= lsu_i_address;
reg_lsu_i_nop <= issue_2nd_word? 1'b0 : i_nop;
data_2nd <= lsu_i_writedata[2*WIDTH-1:WIDTH];
byte_en_2nd <= lsu_i_byte_enable[2*WIDTH_BYTES-1:WIDTH_BYTES];
reg_lsu_i_writedata <= issue_2nd_word ? data_2nd: is_access_aligned? i_writedata : lsu_i_writedata[WIDTH-1:0];
reg_lsu_i_byte_enable <= issue_2nd_word ? byte_en_2nd: is_access_aligned? i_byteenable : lsu_i_byte_enable[WIDTH_BYTES-1:0];
i_2nd_en <= issue_2nd_word & consecutive;
i_2nd_offset <= i_address[BYTE_SELECT_BITS-1:ALIGNMENT_ABITS];
i_2nd_data <= i_writedata;
i_2nd_byte_en <= i_byteenable;
end
end
lsu_bursting_write #(
.KERNEL_SIDE_MEM_LATENCY(KERNEL_SIDE_MEM_LATENCY),
.MEMORY_SIDE_MEM_LATENCY(MEMORY_SIDE_MEM_LATENCY),
.AWIDTH(AWIDTH),
.WIDTH_BYTES(WIDTH_BYTES),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURSTCOUNT_WIDTH(BURSTCOUNT_WIDTH),
.ALIGNMENT_ABITS(ALIGNMENT_ABITS),
.USE_WRITE_ACK(USE_WRITE_ACK),
.USE_BYTE_EN(1'b1),
.UNALIGN(1),
.HIGH_FMAX(HIGH_FMAX)
) bursting_write (
.clk(clk),
.clk2x(clk2x),
.reset(reset),
.i_nop(reg_lsu_i_nop),
.o_stall(stall_int),
.i_valid(reg_lsu_i_valid),
.i_thread_valid(thread_valid),
.i_address(reg_lsu_i_address),
.i_writedata(reg_lsu_i_writedata),
.i_2nd_offset(i_2nd_offset),
.i_2nd_data(i_2nd_data),
.i_2nd_byte_en(i_2nd_byte_en),
.i_2nd_en(i_2nd_en),
.i_stall(i_stall),
.o_valid(o_valid),
.o_active(o_active),
.i_byteenable(reg_lsu_i_byte_enable),
.avm_address(avm_address),
.avm_write(avm_write),
.avm_writeack(avm_writeack),
.avm_writedata(avm_writedata),
.avm_byteenable(avm_byteenable),
.avm_burstcount(avm_burstcount),
.avm_waitrequest(avm_waitrequest)
);
endmodule
|
module wr_port_mux_9to1
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_mask, muxed_port_wr_addr,
muxed_port_wr_data,
// Inputs
wr_port_select, port0_wr_en, port0_wr_mask, port0_wr_addr,
port0_wr_data, port1_wr_en, port1_wr_mask, port1_wr_addr,
port1_wr_data, port2_wr_en, port2_wr_mask, port2_wr_addr,
port2_wr_data, port3_wr_en, port3_wr_mask, port3_wr_addr,
port3_wr_data, port4_wr_en, port4_wr_mask, port4_wr_addr,
port4_wr_data, port5_wr_en, port5_wr_mask, port5_wr_addr,
port5_wr_data, port6_wr_en, port6_wr_mask, port6_wr_addr,
port6_wr_data, port7_wr_en, port7_wr_mask, port7_wr_addr,
port7_wr_data, port8_wr_en, port8_wr_mask, port8_wr_addr,
port8_wr_data
);
output[3:0] muxed_port_wr_en;
output [63:0] muxed_port_wr_mask;
output [9:0] muxed_port_wr_addr;
output [8191:0] muxed_port_wr_data;
input [15:0] wr_port_select;
input[3:0] port0_wr_en;
input [63:0] port0_wr_mask;
input [9:0] port0_wr_addr;
input [2047:0] port0_wr_data;
input[3:0] port1_wr_en;
input [63:0] port1_wr_mask;
input [9:0] port1_wr_addr;
input [2047:0] port1_wr_data;
input[3:0] port2_wr_en;
input [63:0] port2_wr_mask;
input [9:0] port2_wr_addr;
input [2047:0] port2_wr_data;
input[3:0] port3_wr_en;
input [63:0] port3_wr_mask;
input [9:0] port3_wr_addr;
input [2047:0] port3_wr_data;
input[3:0] port4_wr_en;
input [63:0] port4_wr_mask;
input [9:0] port4_wr_addr;
input [2047:0] port4_wr_data;
input[3:0] port5_wr_en;
input [63:0] port5_wr_mask;
input [9:0] port5_wr_addr;
input [2047:0] port5_wr_data;
input[3:0] port6_wr_en;
input [63:0] port6_wr_mask;
input [9:0] port6_wr_addr;
input [2047:0] port6_wr_data;
input[3:0] port7_wr_en;
input [63:0] port7_wr_mask;
input [9:0] port7_wr_addr;
input [2047:0] port7_wr_data;
input[3:0] port8_wr_en;
input [63:0] port8_wr_mask;
input [9:0] port8_wr_addr;
input [8191:0] port8_wr_data;
wire [8191:0] port0_wr_data_i, port1_wr_data_i, port2_wr_data_i,
port3_wr_data_i, port4_wr_data_i, port5_wr_data_i,
port6_wr_data_i, port7_wr_data_i;
genvar i;
generate
for (i = 0; i<64; i=i+1) begin
assign port0_wr_data_i[i*128+:128] = {{96{1'bx}}, port0_wr_data[i*32+:32]};
assign port1_wr_data_i[i*128+:128] = {{96{1'bx}}, port1_wr_data[i*32+:32]};
assign port2_wr_data_i[i*128+:128] = {{96{1'bx}}, port2_wr_data[i*32+:32]};
assign port3_wr_data_i[i*128+:128] = {{96{1'bx}}, port3_wr_data[i*32+:32]};
assign port4_wr_data_i[i*128+:128] = {{96{1'bx}}, port4_wr_data[i*32+:32]};
assign port5_wr_data_i[i*128+:128] = {{96{1'bx}}, port5_wr_data[i*32+:32]};
assign port6_wr_data_i[i*128+:128] = {{96{1'bx}}, port6_wr_data[i*32+:32]};
assign port7_wr_data_i[i*128+:128] = {{96{1'bx}}, port7_wr_data[i*32+:32]};
end
endgenerate
reg [3:0] muxed_port_wr_en;
reg [63:0] muxed_port_wr_mask;
reg [9:0] muxed_port_wr_addr;
reg [8191:0] muxed_port_wr_data;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_mask or
port0_wr_addr or
port0_wr_data_i or
port1_wr_en or
port1_wr_mask or
port1_wr_addr or
port1_wr_data_i or
port2_wr_en or
port2_wr_mask or
port2_wr_addr or
port2_wr_data_i or
port3_wr_en or
port3_wr_mask or
port3_wr_addr or
port3_wr_data_i or
port4_wr_en or
port4_wr_mask or
port4_wr_addr or
port4_wr_data_i or
port5_wr_en or
port5_wr_mask or
port5_wr_addr or
port5_wr_data_i or
port6_wr_en or
port6_wr_mask or
port6_wr_addr or
port6_wr_data_i or
port7_wr_en or
port7_wr_mask or
port7_wr_addr or
port7_wr_data_i or
port8_wr_en or
port8_wr_mask or
port8_wr_addr or
port8_wr_data
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_mask <= port0_wr_mask;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data_i;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_mask <= port1_wr_mask;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data_i;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_mask <= port2_wr_mask;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data_i;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_mask <= port3_wr_mask;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data_i;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_mask <= port4_wr_mask;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data_i;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_mask <= port5_wr_mask;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data_i;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_mask <= port6_wr_mask;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data_i;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_mask <= port7_wr_mask;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data_i;
end
16'h0100:
begin
muxed_port_wr_en <= port8_wr_en;
muxed_port_wr_mask <= port8_wr_mask;
muxed_port_wr_addr <= port8_wr_addr;
muxed_port_wr_data <= port8_wr_data;
end
16'b0000:
begin
muxed_port_wr_en <= 4'b0;
muxed_port_wr_mask <= 64'b0;
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {8192{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_mask <= {64{1'bx}};
muxed_port_wr_addr <= {10{1'bx}};
muxed_port_wr_data <= {8192{1'bx}};
end
endcase
end
endmodule
|
/**
* $Id: axi_slave.v 961 2014-01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya symplified AXI slave.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/**
* GENERAL DESCRIPTION:
*
* AXI slave used also for simple bus master.
*
*
* /------\
* WR ADDRESS ----> | WR |
* WR DATA ----> | | -----------
* WR RESPONSE <---- | CH | |
* \------/ /--------\
* | SIMPLE | ---> WR/RD ADDRRESS
* AXI | | ---> WR DATA
* | RP | <--- RD DATA
* | BUS | <--- ACKNOWLEDGE
* /------\ \--------/
* RD ADDRESS ----> | RD | |
* RD DATA <---- | CH | -----------
* \------/
*
*
* Because AXI bus is quite complex simplier bus was created.
*
* It combines write and read channel, where write has bigger priority. Command
* is then send forward to red pitaya bus. When wite or read acknowledge is
* received AXI response is created and new AXI is accepted.
*
* To prevent AXI lockups because no response is received, this slave creates its
* own after 32 cycles (ack_cnt).
*
*/
module axi_slave
#(
parameter AXI_DW = 64 , // data width (8,16,...,1024)
parameter AXI_AW = 32 , // address width
parameter AXI_IW = 8 , // ID width
parameter AXI_SW = AXI_DW >> 3 // strobe width - 1 bit for every data byte
)
(
// global signals
input axi_clk_i , //!< AXI global clock
input axi_rstn_i , //!< AXI global reset
// axi write address channel
input [ AXI_IW-1: 0] axi_awid_i , //!< AXI write address ID
input [ AXI_AW-1: 0] axi_awaddr_i , //!< AXI write address
input [ 4-1: 0] axi_awlen_i , //!< AXI write burst length
input [ 3-1: 0] axi_awsize_i , //!< AXI write burst size
input [ 2-1: 0] axi_awburst_i , //!< AXI write burst type
input [ 2-1: 0] axi_awlock_i , //!< AXI write lock type
input [ 4-1: 0] axi_awcache_i , //!< AXI write cache type
input [ 3-1: 0] axi_awprot_i , //!< AXI write protection type
input axi_awvalid_i , //!< AXI write address valid
output axi_awready_o , //!< AXI write ready
// axi write data channel
input [ AXI_IW-1: 0] axi_wid_i , //!< AXI write data ID
input [ AXI_DW-1: 0] axi_wdata_i , //!< AXI write data
input [ AXI_SW-1: 0] axi_wstrb_i , //!< AXI write strobes
input axi_wlast_i , //!< AXI write last
input axi_wvalid_i , //!< AXI write valid
output axi_wready_o , //!< AXI write ready
// axi write response channel
output [ AXI_IW-1: 0] axi_bid_o , //!< AXI write response ID
output reg [ 2-1: 0] axi_bresp_o , //!< AXI write response
output reg axi_bvalid_o , //!< AXI write response valid
input axi_bready_i , //!< AXI write response ready
// axi read address channel
input [ AXI_IW-1: 0] axi_arid_i , //!< AXI read address ID
input [ AXI_AW-1: 0] axi_araddr_i , //!< AXI read address
input [ 4-1: 0] axi_arlen_i , //!< AXI read burst length
input [ 3-1: 0] axi_arsize_i , //!< AXI read burst size
input [ 2-1: 0] axi_arburst_i , //!< AXI read burst type
input [ 2-1: 0] axi_arlock_i , //!< AXI read lock type
input [ 4-1: 0] axi_arcache_i , //!< AXI read cache type
input [ 3-1: 0] axi_arprot_i , //!< AXI read protection type
input axi_arvalid_i , //!< AXI read address valid
output axi_arready_o , //!< AXI read address ready
// axi read data channel
output [ AXI_IW-1: 0] axi_rid_o , //!< AXI read response ID
output reg [ AXI_DW-1: 0] axi_rdata_o , //!< AXI read data
output reg [ 2-1: 0] axi_rresp_o , //!< AXI read response
output reg axi_rlast_o , //!< AXI read last
output reg axi_rvalid_o , //!< AXI read response valid
input axi_rready_i , //!< AXI read response ready
// RP system read/write channel
output [ AXI_AW-1: 0] sys_addr_o , //!< system bus read/write address.
output [ AXI_DW-1: 0] sys_wdata_o , //!< system bus write data.
output reg [ AXI_SW-1: 0] sys_sel_o , //!< system bus write byte select.
output reg sys_wen_o , //!< system bus write enable.
output reg sys_ren_o , //!< system bus read enable.
input [ AXI_DW-1: 0] sys_rdata_i , //!< system bus read data.
input sys_err_i , //!< system bus error indicator.
input sys_ack_i //!< system bus acknowledge signal.
);
//---------------------------------------------------------------------------------
//
// AXI slave Module
wire ack ;
reg [ 6-1: 0] ack_cnt ;
reg rd_do ;
reg [ AXI_IW-1: 0] rd_arid ;
reg [ AXI_AW-1: 0] rd_araddr ;
reg rd_error ;
wire rd_errorw ;
reg wr_do ;
reg [ AXI_IW-1: 0] wr_awid ;
reg [ AXI_AW-1: 0] wr_awaddr ;
reg [ AXI_IW-1: 0] wr_wid ;
reg [ AXI_DW-1: 0] wr_wdata ;
reg wr_error ;
wire wr_errorw ;
assign wr_errorw = (axi_awlen_i != 4'h0) || (axi_awsize_i != 3'b010); // error if write burst and more/less than 4B transfer
assign rd_errorw = (axi_arlen_i != 4'h0) || (axi_arsize_i != 3'b010); // error if read burst and more/less than 4B transfer
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
rd_do <= 1'b0 ;
rd_error <= 1'b0 ;
end
else begin
if (axi_arvalid_i && !rd_do && !axi_awvalid_i && !wr_do) // accept just one read request - write has priority
rd_do <= 1'b1 ;
else if (axi_rready_i && rd_do && ack)
rd_do <= 1'b0 ;
if (axi_arvalid_i && axi_arready_o) begin // latch ID and address
rd_arid <= axi_arid_i ;
rd_araddr <= axi_araddr_i ;
rd_error <= rd_errorw ;
end
end
end
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
wr_do <= 1'b0 ;
wr_error <= 1'b0 ;
end
else begin
if (axi_awvalid_i && !wr_do && !rd_do) // accept just one write request - if idle
wr_do <= 1'b1 ;
else if (axi_bready_i && wr_do && ack)
wr_do <= 1'b0 ;
if (axi_awvalid_i && axi_awready_o) begin // latch ID and address
wr_awid <= axi_awid_i ;
wr_awaddr <= axi_awaddr_i ;
wr_error <= wr_errorw ;
end
if (axi_wvalid_i && wr_do) begin // latch ID and write data
wr_wid <= axi_wid_i ;
wr_wdata <= axi_wdata_i ;
end
end
end
assign axi_awready_o = !wr_do && !rd_do ;
assign axi_wready_o = (wr_do && axi_wvalid_i) || (wr_errorw && axi_wvalid_i) ;
assign axi_bid_o = wr_awid ;
//assign axi_bresp_o = {wr_error,1'b0} ; // 2'b10 SLVERR
//assign axi_bvalid_o = (sys_wen_o && axi_bready_i) || (wr_error && axi_bready_i) ;
assign axi_arready_o = !rd_do && !wr_do && !axi_awvalid_i ;
assign axi_rid_o = rd_arid ;
//assign axi_rdata_o = sys_rdata_i ;
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
axi_bvalid_o <= 1'b0 ;
axi_bresp_o <= 2'h0 ;
axi_rlast_o <= 1'b0 ;
axi_rvalid_o <= 1'b0 ;
axi_rresp_o <= 2'h0 ;
end
else begin
axi_bvalid_o <= wr_do && ack ;
axi_bresp_o <= {(wr_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rlast_o <= rd_do && ack ;
axi_rvalid_o <= rd_do && ack ;
axi_rresp_o <= {(rd_error || ack_cnt[5]),1'b0} ; // 2'b10 SLVERR 2'b00 OK
axi_rdata_o <= sys_rdata_i ;
end
end
// acknowledge protection
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
ack_cnt <= 6'h0 ;
end
else begin
if ((axi_arvalid_i && axi_arready_o) || (axi_awvalid_i && axi_awready_o)) // rd || wr request
ack_cnt <= 6'h1 ;
else if (ack)
ack_cnt <= 6'h0 ;
else if (|ack_cnt)
ack_cnt <= ack_cnt + 6'h1 ;
end
end
assign ack = sys_ack_i || ack_cnt[5] || (rd_do && rd_errorw) || (wr_do && wr_errorw); // bus acknowledge or timeout or error
//------------------------------------------
// Simple slave interface
always @(posedge axi_clk_i) begin
if (axi_rstn_i == 1'b0) begin
sys_wen_o <= 1'b0 ;
sys_ren_o <= 1'b0 ;
sys_sel_o <= {AXI_SW{1'b0}} ;
end
else begin
sys_wen_o <= wr_do && axi_wvalid_i && !wr_errorw ;
sys_ren_o <= axi_arvalid_i && axi_arready_o && !rd_errorw ;
sys_sel_o <= {AXI_SW{1'b1}} ;
end
end
assign sys_addr_o = rd_do ? rd_araddr : wr_awaddr ;
assign sys_wdata_o = wr_wdata ;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charFromReceiver (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_2_0_bhv_ver_as
* |
* +-fifo_generator_v13_2_0_bhv_ver_ss
* |
* +-fifo_generator_v13_2_0_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_2_0_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_2_0_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_2_0_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_2_0_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_2_0_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_2_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_2_0_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_2_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_2_0
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_2_0_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 1'b0;
reg rd_rst_asreg_d1 = 1'b0;
reg rd_rst_asreg_d2 = 1'b0;
reg rd_rst_asreg_d3 = 1'b0;
reg rd_rst_reg = 1'b0;
reg rd_rst_comb = 1'b1;
reg rd_rst_comb_d1 = 1'b0;
reg wr_rst_d0 = 1'b0;
reg wr_rst_d1 = 1'b0;
reg wr_rst_d2 = 1'b0;
reg rd_rst_d0 = 1'b0;
reg rd_rst_d1 = 1'b0;
reg rd_rst_d2 = 1'b0;
reg rd_rst_d3 = 1'b0;
reg wrrst_done = 1'b0;
reg rdrst_done = 1'b0;
reg wr_rst_asreg = 1'b0;
reg wr_rst_asreg_d1 = 1'b0;
reg wr_rst_asreg_d2 = 1'b0;
reg wr_rst_asreg_d3 = 1'b0;
reg rd_rst_wr_d0 = 1'b0;
reg rd_rst_wr_d1 = 1'b0;
reg rd_rst_wr_d2 = 1'b0;
reg wr_rst_reg = 1'b0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
reg wr_rst_comb = 1'b1;
reg wr_rst_comb_d1 = 1'b0;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 1'b0;
reg srst_asreg = 1'b0;
reg rst_asreg_d1 = 1'b0;
reg rst_asreg_d2 = 1'b0;
reg srst_asreg_d1 = 1'b0;
reg srst_asreg_d2 = 1'b0;
reg rst_reg = 1'b0;
reg srst_reg = 1'b0;
reg rst_comb = 1'b1;
reg rst_comb_d1 = 1'b0;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire sckt_wr_rst_i;
wire sckt_rd_rst_i;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1_ss
//Common Clock Behavioral Model
fifo_generator_v13_2_0_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST),
.C_HAS_SRST (C_EN_SAFETY_CKT?1:C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (sckt_wr_rst_i),
.CLK (CLK),
.RST (C_EN_SAFETY_CKT?1'b0:rst_i),
.SRST (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1_as
//Independent Clocks Behavioral Model
fifo_generator_v13_2_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (sckt_wr_rst_i),
.SAFETY_CKT_RD_RST (sckt_rd_rst_i),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_2_0_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1_as
//Independent Clocks Behavioral Model
fifo_generator_v13_2_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (sckt_wr_rst_i),
.SAFETY_CKT_RD_RST (sckt_rd_rst_i),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft
fifo_generator_v13_2_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_2_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate //: gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0;
assign rst_i = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0;
wire rst_2_sync;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5;
localparam RST_BUSY_LEN = 4;
reg wr_rst_busy_i = 0;
reg rd_rst_busy_i = 0;
generate
if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = 1'b0;
assign wr_rst_busy_o = 1'b0;
assign rd_rst_busy = 1'b0;
assign sckt_wr_rst_i = 1'b0;
end // gnrst_sync
else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt
reg [1:0] arst_sync_wr = 2'b11;
reg [1:0] arst_sync_rd = 2'b11;
reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;
reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;
reg [3:0] rd_rst_wr_ext = 0;
reg [1:0] wr_rst_rd_ext = 0;
reg sckt_wr_rst_ic = 0;
reg sckt_rd_rst_ic = 0;
assign rst_2_sync = arst_sync_wr[1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
arst_sync_wr <= #`TCQ 2'b11;
else
arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed};
end
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
arst_sync_rd <= #`TCQ 2'b11;
else
arst_sync_rd <= #`TCQ {arst_sync_rd[0], rst_delayed};
end
always @(posedge WR_CLK) begin
sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};
end
always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin
if (arst_sync_wr[1]) begin
sckt_wr_rst_ic <= #`TCQ 1'b1;
wr_rst_busy_i <= #`TCQ 1'b1;
rd_rst_wr_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}};
end else begin
rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};
if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])
sckt_wr_rst_ic <= #`TCQ 1'b0;
else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])
wr_rst_busy_i <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK) begin
sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic};
end
always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin
if (arst_sync_rd[1]) begin
sckt_rd_rst_ic <= #`TCQ 1'b1;
rd_rst_busy_i <= #`TCQ 1'b1;
wr_rst_rd_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}};
end else begin
wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};
if (wr_rst_rd_ext[1]) begin
sckt_rd_rst_ic <= #`TCQ 1'b0;
rd_rst_busy_i <= #`TCQ 1'b0;
end
end
end
assign rd_rst_busy = rd_rst_busy_i;
assign wr_rst_busy = wr_rst_busy_i;
assign wr_rst_busy_o = wr_rst_busy_i;
assign sckt_wr_rst_i = sckt_wr_rst_ic|arst_sync_wr[1];
assign sckt_rd_rst_i = sckt_rd_rst_ic|arst_sync_rd[1];
end // g7s_ic_rst_nsckt
else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt
reg [RST_SYNC_STAGES-1:0] arst_sync_wr = {RST_SYNC_STAGES{1'b1}};
reg [RST_SYNC_STAGES-1:0] arst_sync_rd = {RST_SYNC_STAGES{1'b1}};
reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0;
reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0;
reg [3:0] rd_rst_wr_ext = 0;
reg [1:0] wr_rst_rd_ext = 0;
reg sckt_wr_rst_ic = 0;
reg sckt_rd_rst_ic = 0;
always @(posedge WR_CLK) begin
arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};
sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic};
rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]};
if (arst_sync_wr[RST_SYNC_STAGES-1]) begin
sckt_wr_rst_ic <= #`TCQ 1'b1;
wr_rst_busy_i <= #`TCQ 1'b1;
end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0])
sckt_wr_rst_ic <= #`TCQ 1'b0;
else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2])
wr_rst_busy_i <= #`TCQ 1'b0;
end
always @(posedge RD_CLK) begin
arst_sync_rd <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed};
sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]};
if (arst_sync_rd[RST_SYNC_STAGES-1]) begin
sckt_rd_rst_ic <= #`TCQ 1'b1;
rd_rst_busy_i <= #`TCQ 1'b1;
end else if (wr_rst_rd_ext[1]) begin
sckt_rd_rst_ic <= #`TCQ 1'b0;
rd_rst_busy_i <= #`TCQ 1'b0;
end
end
assign rd_rst_busy = rd_rst_busy_i;
assign wr_rst_busy = wr_rst_busy_i;
assign wr_rst_busy_o = wr_rst_busy_i;
assign sckt_wr_rst_i = sckt_wr_rst_ic;
assign sckt_rd_rst_i = sckt_rd_rst_ic;
end // g7s_ic_rst_sckt
else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt
reg [1:0] arst_sync_wr = 0;
reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
assign rst_2_sync = arst_sync_wr[1];
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
arst_sync_wr <= #`TCQ 2'b11;
else
arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed};
end
always @(posedge CLK) begin
sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
end
assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1];
assign sckt_rd_rst_i = sckt_wr_rst_i;
assign wr_rst_busy = |sckt_wr_rst_cc | arst_sync_wr[1];
assign rd_rst_busy = |sckt_wr_rst_cc;
assign wr_rst_busy_o = |sckt_wr_rst_cc;
end // g7s_cc_rst_nsckt
else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt
reg [RST_SYNC_STAGES-1:0] arst_sync_wr = 0;
reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
always @(posedge CLK) begin
arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed};
sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]};
end
assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0];
assign sckt_rd_rst_i = sckt_wr_rst_i;
assign wr_rst_busy = |sckt_wr_rst_cc;
assign rd_rst_busy = |sckt_wr_rst_cc;
assign wr_rst_busy_o = |sckt_wr_rst_cc;
end // g7s_cc_rst_sckt
else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
assign sckt_wr_rst_i = rst_reg;
always @* rst_full_ff_i <= 1'b0;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
end // g8s_cc_rst
else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst
assign wr_rst_busy = srst_delayed;
assign rd_rst_busy = srst_delayed;
assign rst_2_sync = srst_delayed;
assign sckt_wr_rst_i = srst_delayed;
always @* rst_full_ff_i <= 1'b0;
end // g7s_cc_srst
endgenerate
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b0;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b0;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;//1'b0;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | sckt_wr_rst_i;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i;
always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3;
end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt
always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
always @* rst_full_gen_i <= 1'b0;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
always @* rst_full_gen_i <= 1'b0;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_2_0_CONV_VER
module fifo_generator_v13_2_0_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_2_0_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_2_0_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF & C_HAS_RST) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_2_0_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_2_0_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF & C_HAS_RST) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i & C_HAS_RST) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i & C_HAS_RST) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_2_0_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_2_0_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_2_0_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_2_0_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
generate if (C_HAS_RST == 1) begin : grst_full
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF & C_HAS_RST)
full_i <= C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
end endgenerate
generate if (C_HAS_SRST == 1) begin : gsrst_full
always @(posedge CLK) begin
if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
end endgenerate
generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full
always @(posedge CLK) begin
full_i <= #`TCQ ram_full_comb;
end
end endgenerate
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
generate if (C_HAS_RST == 1) begin : grst_afull
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF & C_HAS_RST)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
end endgenerate
generate if (C_HAS_SRST == 1) begin : gsrst_afull
always @(posedge CLK) begin
if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
end endgenerate
generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull
always @(posedge CLK) begin
almost_full_i <= #`TCQ ram_afull_comb;
end
end endgenerate
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_2_0_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_2_0_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_2_0_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_2_0_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
localparam RST_SYNC_STAGES = 5;
localparam RST_BUSY_LEN = 6;
reg [1:0] arst_sync_wr = 2'b11;
reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0;
wire sync_reset;
wire extnd_reset;
always @(posedge ARESET or posedge ACLK) begin
if (ARESET)
arst_sync_wr <= 2'b11;
else
arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0};
end
always @(posedge ACLK) begin
sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]};
end
assign sync_reset = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1];
assign extnd_reset = |sckt_wr_rst_cc | arst_sync_wr[1];
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= extnd_reset;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (sync_reset || extnd_reset) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1 && ~extnd_reset) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= extnd_reset;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (sync_reset || extnd_reset) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1 && ~extnd_reset) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
module sgpr_simx_rd_port_mux (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
port_rd_data,
rd_addr,
rd_en,
rd_data
);
input port0_rd_en;
input [8:0] port0_rd_addr;
input port1_rd_en;
input [8:0] port1_rd_addr;
input port2_rd_en;
input [8:0] port2_rd_addr;
input port3_rd_en;
input [8:0] port3_rd_addr;
input port4_rd_en;
input [8:0] port4_rd_addr;
input port5_rd_en;
input [8:0] port5_rd_addr;
input port6_rd_en;
input [8:0] port6_rd_addr;
input port7_rd_en;
input [8:0] port7_rd_addr;
input [31:0] rd_data;
output [31:0] port_rd_data;
output [8:0] rd_addr;
output rd_en;
reg [8:0] rd_addr;
reg rd_en;
assign port_rd_data = rd_data;
always @ (
port0_rd_en or
port1_rd_en or
port2_rd_en or
port3_rd_en or
port4_rd_en or
port5_rd_en or
port6_rd_en or
port7_rd_en or
port0_rd_addr or
port1_rd_addr or
port2_rd_addr or
port3_rd_addr or
port4_rd_addr or
port5_rd_addr or
port6_rd_addr or
port7_rd_addr
) begin
casex({port7_rd_en,port6_rd_en,port5_rd_en,port4_rd_en,port3_rd_en,port2_rd_en,port1_rd_en,port0_rd_en})
8'b0000_0001:
begin
rd_addr <= port0_rd_addr;
rd_en <= 1'b1;
end
8'b0000_0010:
begin
rd_addr <= port1_rd_addr;
rd_en <= 1'b1;
end
8'b0000_0100:
begin
rd_addr <= port2_rd_addr;
rd_en <= 1'b1;
end
8'b0000_1000:
begin
rd_addr <= port3_rd_addr;
rd_en <= 1'b1;
end
8'b0001_0000:
begin
rd_addr <= port4_rd_addr;
rd_en <= 1'b1;
end
8'b0010_0000:
begin
rd_addr <= port5_rd_addr;
rd_en <= 1'b1;
end
8'b0100_0000:
begin
rd_addr <= port6_rd_addr;
rd_en <= 1'b1;
end
8'b1000_0000:
begin
rd_addr <= port7_rd_addr;
rd_en <= 1'b1;
end
8'b0000_0000:
begin
rd_addr <= {9{1'bx}};
rd_en <= 1'b0;
end
default:
begin
rd_addr <= {9{1'bx}};
rd_en <= 1'bx;
end
endcase
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier boolean_expression
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n");
#10 ;
if(value1 != 4'b1)
$display("FAILED - always reg_lvalue = @ event_identifier boolean_expression\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = @ event_ident 1'b1 && 1'b1 ;
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: RX Engine Wrapper file. Connects all of the individual modules
// and FIFOs that interface between the Block Plus LogiCore and the DMA-DDR
// Interface Block (dma_ddr2_if)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// modified by Jiansong Zhang:
// (1)add 1 bit to differentiate TX descriptor from normal data ---- done
// (2)TX des parser ------------------------------------------------ done
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_engine(
input wire clk,
input wire rst,
//interface to dma_ddr2_if
output wire [127:0] ingress_data,
output wire [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
output wire [2:0] ingress_xfer_size,
output wire [27:6] ingress_start_addr,
output wire ingress_data_req,
input wire ingress_data_ack,
//interface to dma_ctrl_wrapper
input wire rd_dma_start, //indicates the start of a read dma xfer
input wire [31:0] dmarad, //destination addres(ddr2) only 13 bits used /// why put destination here?
input wire [31:0] dmarxs,
output wire rd_dma_done, //dma transfer complete /// Jiansong: it's fake? not fake
///Jiansong: interface to dma control wrapper
output new_des_one,
output wire [31:0] SourceAddr_L,
output wire [31:0] SourceAddr_H,
output wire [31:0] DestAddr,
output wire [23:0] FrameSize,
output wire [7:0] FrameControl,
/// Jiansong: interface from dma control wrapper
input wire Wait_for_TX_desc,
input wire transferstart, // control signal for transfer recovering
//interface to read_request_wrapper
output [4:0] rx_waddr,
output [31:0] rx_wdata,
output rx_we,
output [4:0] rx_raddr,
input [31:0] rx_rdata,
output pending_comp_done,
input [31:0] completion_pending,
//interface from PCIe Endpoint Block Plus - RX TRN
input wire [63:0] trn_rd,
input wire [7:0] trn_rrem_n,
input wire trn_rsof_n,
input wire trn_reof_n,
input wire trn_rsrc_rdy_n,
input wire trn_rsrc_dsc_n,
output wire trn_rdst_rdy_n,
input wire trn_rerrfwd_n,
output wire trn_rnp_ok_n,
input wire [6:0] trn_rbar_hit_n,
input wire [11:0] trn_rfc_npd_av,
input wire [7:0] trn_rfc_nph_av,
input wire [11:0] trn_rfc_pd_av,
input wire [7:0] trn_rfc_ph_av,
input wire [11:0] trn_rfc_cpld_av,
input wire [7:0] trn_rfc_cplh_av,
output wire trn_rcpl_streaming_n,
//interface to TX Engine (completer_pkt_gen)
output wire [6:0] bar_hit_o,
output wire MRd_o,
output wire MWr_o,
output wire [31:0] MEM_addr_o,
output wire [15:0] MEM_req_id_o,
output wire [7:0] MEM_tag_o,
output wire header_fields_valid_o,
output wire [31:0] write_data,
output wire write_data_wren,
input wire read_last,
/// Jiansong: output to tx_sm
output wire [9:0] np_rx_cnt_qw,
/// Jiansong: debug register
output [9:0] Debug30RXEngine,
output reg [11:0] Debug31RXDataFIFOfullcnt,
output reg [11:0] Debug32RXXferFIFOfullcnt,
output reg [23:0] Debug33RXDataFIFOWRcnt,
output reg [23:0] Debug34RXDataFIFORDcnt,
output reg [23:0] Debug35RXXferFIFOWRcnt,
output reg [23:0] Debug36RXXferFIFORDcnt
);
wire [27:6] mem_dest_addr;
wire [10:0] mem_dma_size;
wire mem_dma_start;
wire [63:0] write_data_fifo_data;
wire write_data_fifo_cntrl;
wire write_data_fifo_status;
wire [127:0] read_data_fifo_data;
wire read_data_fifo_cntrl;
wire read_data_fifo_status;
wire fourdw_n_threedw; //fourdw = 1'b1; 3dw = 1'b0;
wire payload;
wire [2:0] tc;
wire td;
wire ep;
wire [1:0] attr;
wire [9:0] dw_length;
wire [15:0] MEM_req_id;
wire [7:0] MEM_tag;
wire [15:0] CMP_comp_id;
wire [2:0] CMP_compl_stat;
wire CMP_bcm;
wire [11:0] CMP_byte_count;
wire [63:0] MEM_addr;
wire [15:0] CMP_req_id;
wire [7:0] CMP_tag;
wire [6:0] CMP_lower_addr;
wire MRd;
wire MWr;
wire CplD;
reg CplD_r; // Jiansong: pipeline register to solve Mrd write to fifo bug
wire Msg;
wire UR;
wire [6:0] bar_hit;
wire header_fields_valid;
reg [63:0] trn_rd_reg;
reg [7:0] trn_rrem_reg_n;
reg trn_rsof_reg_n;
reg trn_reof_reg_n;
reg trn_rsrc_rdy_reg_n;
reg trn_rsrc_dsc_reg_n;
reg trn_rerrfwd_reg_n;
reg [6:0] trn_rbar_hit_reg_n;
reg [11:0] trn_rfc_npd_av_reg;
reg [7:0] trn_rfc_nph_av_reg;
reg [11:0] trn_rfc_pd_av_reg;
reg [7:0] trn_rfc_ph_av_reg;
reg [11:0] trn_rfc_cpld_av_reg;
reg [7:0] trn_rfc_cplh_av_reg;
wire read_xfer_fifo_status;
wire write_xfer_fifo_status;
wire xfer_trn_mem_fifo_rden;
wire [27:6] mem_dest_addr_fifo;
wire [10:0] mem_dma_size_fifo;
/// Jiansong: added for TX des
wire isDes;
wire isDes_fifo;
//assign some outputs
assign bar_hit_o[6:0] = bar_hit[6:0];
assign MRd_o = MRd;
assign MWr_o = MWr;
assign MEM_addr_o[31:0] = MEM_addr[31:0];
assign MEM_req_id_o[15:0] = MEM_req_id[15:0];
assign MEM_tag_o[7:0] = MEM_tag[7:0];
assign header_fields_valid_o = header_fields_valid;
//send the write data info and wren enable signal out to write Posted MemWr
//data to the dma_ctrl_wrapper (or any other target block for that matter)
assign write_data[31:0] = write_data_fifo_data[31:0];
assign write_data_wren = write_data_fifo_cntrl;
//all the outputs of the endpoint need to be pipelined
//to meet 250 MHz timing of an 8 lane design
always @ (posedge clk)
begin
trn_rd_reg[63:0] <= trn_rd[63:0] ;
trn_rrem_reg_n[7:0] <= trn_rrem_n[7:0] ;
trn_rsof_reg_n <= trn_rsof_n ;
trn_reof_reg_n <= trn_reof_n ;
trn_rsrc_rdy_reg_n <= trn_rsrc_rdy_n ;
trn_rsrc_dsc_reg_n <= trn_rsrc_dsc_n ;
trn_rerrfwd_reg_n <= trn_rerrfwd_n ;
trn_rbar_hit_reg_n[6:0] <= trn_rbar_hit_n[6:0] ;
trn_rfc_npd_av_reg[11:0] <= trn_rfc_npd_av[11:0] ;
trn_rfc_nph_av_reg[7:0] <= trn_rfc_nph_av[7:0] ;
trn_rfc_pd_av_reg[11:0] <= trn_rfc_pd_av[11:0] ;
trn_rfc_ph_av_reg[7:0] <= trn_rfc_ph_av[7:0] ;
trn_rfc_cpld_av_reg[11:0] <= trn_rfc_cpld_av[11:0];
trn_rfc_cplh_av_reg[7:0] <= trn_rfc_cplh_av[7:0] ;
end
//Instantiate the Receive TRN Monitor block
//This module interfaces to the DMA
//Control/Status Register File and the Read Request Fifo to determine when a
//DMA transfer has completed fully.
rx_trn_monitor rx_trn_monitor_inst(
.clk (clk),
.rst (rst),
// interface to dma_ctrl_wrapper
.rd_dma_start (rd_dma_start),
.dmarad (dmarad[31:0]),
.dmarxs (dmarxs[31:0]),
.rd_dma_done (rd_dma_done),
.read_last (read_last),
///Jiansong: signal from dma control wrapper
.Wait_for_TX_desc (Wait_for_TX_desc),
.transferstart (transferstart),
//interface to read_request_wrapper
.rx_waddr (rx_waddr[4:0]),
.rx_wdata (rx_wdata[31:0]),
.rx_we (rx_we),
.rx_raddr (rx_raddr[4:0]),
.rx_rdata(rx_rdata[31:0]),
.pending_comp_done(pending_comp_done),
.completion_pending(completion_pending[31:0]),
//PCIe Endpoint Block Plus interface
// RX TRN
.trn_rd (trn_rd_reg), // I [63/31:0]
.trn_rrem_n (trn_rrem_reg_n), // I [7:0]
.trn_rsof_n (trn_rsof_reg_n), // I
.trn_reof_n (trn_reof_reg_n), // I
.trn_rsrc_rdy_n (trn_rsrc_rdy_reg_n), // I
.trn_rsrc_dsc_n (trn_rsrc_dsc_reg_n), // I
.trn_rerrfwd_n (trn_rerrfwd_reg_n), // I
.trn_rbar_hit_n (trn_rbar_hit_reg_n), // I [6:0]
.trn_rfc_npd_av (trn_rfc_npd_av_reg), // I [11:0]
.trn_rfc_nph_av (trn_rfc_nph_av_reg), // I [7:0]
.trn_rfc_pd_av (trn_rfc_pd_av_reg), // I [11:0]
.trn_rfc_ph_av (trn_rfc_ph_av_reg), // I [7:0]
.trn_rfc_cpld_av (trn_rfc_cpld_av_reg),// I [11:0]
.trn_rfc_cplh_av (trn_rfc_cplh_av_reg),// I [7:0]
//interface from rx_trn_data_fsm
.fourdw_n_threedw (fourdw_n_threedw),
.payload (payload),
.tc (tc[2:0]),
.td (td),
.ep (ep),
.attr (attr[1:0]),
.dw_length (dw_length[9:0]),
.MEM_req_id (MEM_req_id[15:0]),
.MEM_tag (MEM_tag[7:0]),
.CMP_comp_id (CMP_comp_id[15:0]),
.CMP_compl_stat (CMP_compl_stat[2:0]),
.CMP_bcm (CMP_bcm),
.CMP_byte_count (CMP_byte_count[11:0]),
.MEM_addr (MEM_addr[63:0]),
.CMP_req_id (CMP_req_id[15:0]),
.CMP_tag (CMP_tag[7:0]),
.CMP_lower_addr (CMP_lower_addr[6:0]),
.MRd (MRd),
.MWr (MWr),
.CplD (CplD),
.Msg (Msg),
.UR (UR),
.header_fields_valid(header_fields_valid),
.data_valid (write_data_fifo_cntrl),
//Outputs to xfer_trn_mem_fifo
.isDes (isDes), ///Jiansong: added for TX des
.mem_dest_addr (mem_dest_addr),
.mem_dma_size (mem_dma_size),
.mem_dma_start (mem_dma_start),
// Jiansong: output to tx_sm
.np_rx_cnt_qw (np_rx_cnt_qw),
// Debug output
.Debug30RXEngine (Debug30RXEngine)
);
//Instantiate the Recieve TRN State Machine
//This module interfaces to the Block Plus RX
//TRN. It presents the 64-bit data from completer and and forwards that
//data with a data_valid signal. This block also decodes packet header info
//and forwards it to the rx_trn_monitor block.
rx_trn_data_fsm rx_trn_data_fsm_inst(
.clk (clk),
.rst (rst),
// Rx Local-Link from PCIe Endpoint Block Plus
.trn_rd (trn_rd_reg), // I [63/31:0]
.trn_rrem_n (trn_rrem_reg_n), // I [7:0]
.trn_rsof_n (trn_rsof_reg_n), // I
.trn_reof_n (trn_reof_reg_n), // I
.trn_rsrc_rdy_n (trn_rsrc_rdy_reg_n), // I
.trn_rsrc_dsc_n (trn_rsrc_dsc_reg_n), // I
.trn_rdst_rdy_n (trn_rdst_rdy_n), // O
.trn_rerrfwd_n (trn_rerrfwd_reg_n), // I
.trn_rnp_ok_n (trn_rnp_ok_n), // O
.trn_rbar_hit_n (trn_rbar_hit_reg_n), // I [6:0]
.trn_rfc_npd_av (trn_rfc_npd_av_reg), // I [11:0]
.trn_rfc_nph_av (trn_rfc_nph_av_reg), // I [7:0]
.trn_rfc_pd_av (trn_rfc_pd_av_reg), // I [11:0]
.trn_rfc_ph_av (trn_rfc_ph_av_reg), // I [7:0]
.trn_rfc_cpld_av (trn_rfc_cpld_av_reg), // I [11:0]
.trn_rfc_cplh_av (trn_rfc_cplh_av_reg), // I [7:0]
.trn_rcpl_streaming_n(trn_rcpl_streaming_n), // O
//Data write signals for writing completion data to the data_trn_mem_fifo
//or for writing data to targets memories. Could easily demux using bar_hit
//signals to steer the data to different locations
.data_out (write_data_fifo_data[63:0]),
.data_out_be (),
.data_valid (write_data_fifo_cntrl),
.data_fifo_status (write_data_fifo_status),
//Header field signals
//interfaced to rx_trn_monitor
.fourdw_n_threedw (fourdw_n_threedw),
.payload (payload),
.tc (tc[2:0]),
.td (td),
.ep (ep),
.attr (attr[1:0]),
.dw_length (dw_length[9:0]),
.MEM_req_id (MEM_req_id[15:0]),
.MEM_tag (MEM_tag[7:0]),
.CMP_comp_id (CMP_comp_id[15:0]),
.CMP_compl_stat (CMP_compl_stat[2:0]),
.CMP_bcm (CMP_bcm),
.CMP_byte_count (CMP_byte_count[11:0]),
.MEM_addr (MEM_addr[63:0]),
.CMP_req_id (CMP_req_id[15:0]),
.CMP_tag (CMP_tag[7:0]),
.CMP_lower_addr (CMP_lower_addr[6:0]),
.MRd (MRd),
.MWr (MWr),
.CplD (CplD),
.Msg (Msg),
.UR (UR),
.bar_hit (bar_hit[6:0]),
.header_fields_valid(header_fields_valid)
);
always@(posedge clk) CplD_r <= CplD;
//Instantiate the Data TRN Mem FIFO
//This is an 8KB FIFO constructed of BRAM
//Provides additional buffering in case the dma_ddr2_if is busy with
//egress. Also, converts the datapath from 64-bit to 128 bit
data_trn_mem_fifo data_trn_mem_fifo_inst(
.din (write_data_fifo_data[63:0]),
.rd_clk (clk),
.rd_en (read_data_fifo_cntrl),
.rst (rst),
.wr_clk (clk),
// .wr_en (write_data_fifo_cntrl & CplD),
.wr_en (write_data_fifo_cntrl & CplD_r), // Jiansong: slove Mrd write to data fifo bug
//by swapping the DWORD order on dout we get /// Jiansong: swapping is necessary?
// read_data_fifo_data[127:0] =
// B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0
.dout ({read_data_fifo_data[63:0],read_data_fifo_data[127:64]}),
.empty (read_data_fifo_status),
.full (write_data_fifo_status) /// Jiansong: no control here
);
//Instantiate the Xfer TRN Mem FIFO
//This is an 34X128 FIFO constructed of Distributed RAM
xfer_trn_mem_fifo xfer_trn_mem_fifo_inst(
.din ({isDes,mem_dest_addr[27:6],mem_dma_size[10:0]}),
.clk (clk),
.rd_en (xfer_trn_mem_fifo_rden),
.rst (rst),
.wr_en (mem_dma_start),
.dout ({isDes_fifo,mem_dest_addr_fifo[27:6],mem_dma_size_fifo[10:0]}),
.empty (read_xfer_fifo_status),
.full (write_xfer_fifo_status) /// Jiansong: no control here
);
// Jiansong: Debug register out
always@(posedge clk)begin
if (rst)
Debug31RXDataFIFOfullcnt <= 32'h0000_0000;
else if (write_data_fifo_status)
Debug31RXDataFIFOfullcnt <= Debug31RXDataFIFOfullcnt + 1'b1;
else
Debug31RXDataFIFOfullcnt <= Debug31RXDataFIFOfullcnt;
end
always@(posedge clk)begin
if (rst)
Debug32RXXferFIFOfullcnt <= 32'h0000_0000;
else if (write_xfer_fifo_status)
Debug32RXXferFIFOfullcnt <= Debug32RXXferFIFOfullcnt + 1'b1;
else
Debug32RXXferFIFOfullcnt <= Debug32RXXferFIFOfullcnt;
end
always@(posedge clk)begin
if (rst)
Debug33RXDataFIFOWRcnt <= 32'h0000_0000;
else if (write_data_fifo_cntrl & CplD)
Debug33RXDataFIFOWRcnt <= Debug33RXDataFIFOWRcnt + 1'b1;
else
Debug33RXDataFIFOWRcnt <= Debug33RXDataFIFOWRcnt;
end
always@(posedge clk)begin
if (rst)
Debug34RXDataFIFORDcnt <= 32'h0000_0000;
else if (read_data_fifo_cntrl)
Debug34RXDataFIFORDcnt <= Debug34RXDataFIFORDcnt + 1'b1;
else
Debug34RXDataFIFORDcnt <= Debug34RXDataFIFORDcnt;
end
always@(posedge clk)begin
if (rst)
Debug35RXXferFIFOWRcnt <= 32'h0000_0000;
else if (mem_dma_start)
Debug35RXXferFIFOWRcnt <= Debug35RXXferFIFOWRcnt + 1'b1;
else
Debug35RXXferFIFOWRcnt <= Debug35RXXferFIFOWRcnt;
end
always@(posedge clk)begin
if (rst)
Debug36RXXferFIFORDcnt <= 32'h0000_0000;
else if (xfer_trn_mem_fifo_rden)
Debug36RXXferFIFORDcnt <= Debug36RXXferFIFORDcnt + 1'b1;
else
Debug36RXXferFIFORDcnt <= Debug36RXXferFIFORDcnt;
end
//Instantiate the Receive Memory Data State Machine
rx_mem_data_fsm rx_mem_data_fsm_inst(
.clk (clk),
.rst (rst),
//interface to dma_ddr2_if block
.ingress_data (ingress_data),
.ingress_fifo_ctrl (ingress_fifo_ctrl),
.ingress_fifo_status (ingress_fifo_status),
.ingress_xfer_size (ingress_xfer_size),
.ingress_start_addr (ingress_start_addr),
.ingress_data_req (ingress_data_req),
.ingress_data_ack (ingress_data_ack),
//interface to xfer_trn_mem_fifo
.isDes_fifo(isDes_fifo), /// Jiansong: added for TX des
.mem_dest_addr_fifo (mem_dest_addr_fifo),
.mem_dma_size_fifo (mem_dma_size_fifo),
.mem_dma_start (1'b0),
.mem_trn_fifo_empty (read_xfer_fifo_status),
.mem_trn_fifo_rden (xfer_trn_mem_fifo_rden),
//interface to data_trn_mem_fifo
.data_fifo_data (read_data_fifo_data[127:0]),
.data_fifo_cntrl (read_data_fifo_cntrl),
.data_fifo_status (read_data_fifo_status),
///Jiansong: interface to dma control wrapper
.new_des_one(new_des_one),
.SourceAddr_L(SourceAddr_L),
.SourceAddr_H(SourceAddr_H),
.DestAddr(DestAddr),
.FrameSize(FrameSize),
.FrameControl(FrameControl)
);
endmodule
|
//
// Conformal-LEC Version 14.20-d237 ( 26-Mar-2015) ( 64 bit executable)
//
module top ( PI_clock , PI_reset , n0 , n1 , n2 , n3 , n4 , n5 , n6 ,
n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 ,
n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 ,
n27 , n28 , n29 , n30 , n31 , DFF_state_reg_Q , n32 , n33 , n34 , n35 ,
n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 ,
n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 ,
n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 ,
n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 ,
n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 ,
n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 ,
n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 ,
n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 ,
n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 ,
n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 ,
n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 ,
n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 ,
n156 , n157 , n158 , DFF_B_reg_Q , n159 , n160 , n161 , n162 , n163 , n164 ,
n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 ,
n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 ,
n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 ,
n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 ,
n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 ,
n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 ,
n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 ,
n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , DFF_rd_reg_Q , DFF_wr_reg_Q ,
n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 ,
n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 ,
n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 ,
n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 ,
n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 ,
n293 , n294 , PO_rd , PO_wr , DFF_state_reg_S , DFF_state_reg_R , DFF_state_reg_CK , DFF_state_reg_D , n295 , n296 ,
n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 ,
n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 ,
n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 ,
n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 ,
n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 ,
n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 ,
n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 ,
n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 ,
n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 ,
n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 ,
n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 ,
n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 ,
n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 ,
n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 ,
n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 ,
n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 ,
n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 ,
n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 ,
n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 ,
n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 ,
n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 ,
n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 ,
n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 , n526 ,
n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 , n536 ,
n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 , n546 ,
n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 , n556 ,
n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 , n566 ,
n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 , n576 ,
n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 , n586 ,
n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 , n596 ,
n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 , n606 ,
n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 , n616 ,
n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 , n626 ,
n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 , n636 ,
n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 , n646 ,
n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 , n656 ,
n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 , n666 ,
n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 , n676 ,
n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 , n686 ,
n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 , n696 ,
n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 , n706 ,
n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 , n716 ,
n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 , n726 ,
n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 , n736 ,
n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 , n746 ,
n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 , n756 ,
n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 , n766 ,
n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 , n776 ,
n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 , n786 ,
n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 , n796 ,
n797 , n798 , n799 , n800 , n801 , n802 , DFF_B_reg_S , DFF_B_reg_R , DFF_B_reg_CK , DFF_B_reg_D ,
n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 ,
n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 ,
n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 ,
n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 ,
n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 ,
n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 ,
n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 ,
n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 ,
n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 ,
n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 ,
n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 ,
n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 ,
n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 ,
n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 ,
n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 ,
n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 ,
n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 ,
n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 ,
n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 ,
n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 ,
n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 ,
n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 ,
n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 ,
n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 ,
n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 ,
n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 ,
n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 ,
n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 ,
n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 ,
n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 ,
n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 ,
n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 ,
n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 ,
n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , DFF_rd_reg_S , DFF_rd_reg_R , DFF_rd_reg_CK , DFF_rd_reg_D ,
DFF_wr_reg_S , DFF_wr_reg_R , DFF_wr_reg_CK , DFF_wr_reg_D);
input PI_clock , PI_reset , n0 , n1 , n2 , n3 , n4 , n5 , n6 ,
n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 ,
n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 ,
n27 , n28 , n29 , n30 , n31 , DFF_state_reg_Q , n32 , n33 , n34 , n35 ,
n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 ,
n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 ,
n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 ,
n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 ,
n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 ,
n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 ,
n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 ,
n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 ,
n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 ,
n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 ,
n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 ,
n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 ,
n156 , n157 , n158 , DFF_B_reg_Q , n159 , n160 , n161 , n162 , n163 , n164 ,
n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 ,
n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 ,
n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 ,
n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 ,
n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 ,
n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 ,
n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 ,
n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , DFF_rd_reg_Q , DFF_wr_reg_Q;
output n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 ,
n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 ,
n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 ,
n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 ,
n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 ,
n292 , n293 , n294 , PO_rd , PO_wr , DFF_state_reg_S , DFF_state_reg_R , DFF_state_reg_CK , DFF_state_reg_D , n295 ,
n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 ,
n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 ,
n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 ,
n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 ,
n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 ,
n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 ,
n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 ,
n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 ,
n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 ,
n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 ,
n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 ,
n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 ,
n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 ,
n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 ,
n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 ,
n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 ,
n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 ,
n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 ,
n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 ,
n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 ,
n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 ,
n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 ,
n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 , n525 ,
n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 , n535 ,
n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 , n545 ,
n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 , n555 ,
n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 , n565 ,
n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 , n575 ,
n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 , n585 ,
n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 , n595 ,
n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 , n605 ,
n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 , n615 ,
n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 , n625 ,
n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 , n635 ,
n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 , n645 ,
n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 , n655 ,
n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 , n665 ,
n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 , n675 ,
n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 , n685 ,
n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 , n695 ,
n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 , n705 ,
n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 , n715 ,
n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 , n725 ,
n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 , n735 ,
n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 , n745 ,
n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 , n755 ,
n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 , n765 ,
n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 , n775 ,
n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 , n785 ,
n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 , n795 ,
n796 , n797 , n798 , n799 , n800 , n801 , n802 , DFF_B_reg_S , DFF_B_reg_R , DFF_B_reg_CK ,
DFF_B_reg_D , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 , n811 ,
n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 , n821 ,
n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 , n831 ,
n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 , n841 ,
n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 , n851 ,
n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 , n861 ,
n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 , n871 ,
n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 , n881 ,
n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 , n891 ,
n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 , n901 ,
n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 , n911 ,
n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 , n921 ,
n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 , n931 ,
n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 , n941 ,
n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 , n951 ,
n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 , n961 ,
n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 , n971 ,
n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 , n981 ,
n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 , n991 ,
n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 , n1001 ,
n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 ,
n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 ,
n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 ,
n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 ,
n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 ,
n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 ,
n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 ,
n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 ,
n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 ,
n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 ,
n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 ,
n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 ,
n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 ,
n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , DFF_rd_reg_S , DFF_rd_reg_R , DFF_rd_reg_CK ,
DFF_rd_reg_D , DFF_wr_reg_S , DFF_wr_reg_R , DFF_wr_reg_CK , DFF_wr_reg_D;
wire n68417 , n68418 , n68419 , n68420 , n68421 , n68422 , n68423 , n68424 , n68425 ,
n68426 , n68427 , n68428 , n68429 , n68430 , n68431 , n68432 , n68433 , n68434 , n68435 ,
n68436 , n68437 , n68438 , n68439 , n68440 , n68441 , n68442 , n68443 , n68444 , n68445 ,
n68446 , n68447 , n68448 , n68449 , n68450 , n68451 , n68452 , n68453 , n68454 , n68455 ,
n68456 , n68457 , n68458 , n68459 , n68460 , n68461 , n68462 , n68463 , n68464 , n68465 ,
n68466 , n68467 , n68468 , n68469 , n68470 , n68471 , n68472 , n68473 , n68474 , n68475 ,
n68476 , n68477 , n68478 , n68479 , n68480 , n68481 , n68482 , n68483 , n68484 , n68485 ,
n68486 , n68487 , n68488 , n68489 , n68490 , n68491 , n68492 , n68493 , n68494 , n68495 ,
n68496 , n68497 , n68498 , n68499 , n68500 , n68501 , n68502 , n68503 , n68504 , n68505 ,
n68506 , n68507 , n68508 , n68509 , n68510 , n68511 , n68512 , n68513 , n68514 , n68515 ,
n68516 , n68517 , n68518 , n68519 , n68520 , n68521 , n68522 , n68523 , n68524 , n68525 ,
n68526 , n68527 , n68528 , n68529 , n68530 , n68531 , n68532 , n68533 , n68534 , n68535 ,
n68536 , n68537 , n68538 , n68539 , n68540 , n68541 , n68542 , n68543 , n68544 , n68545 ,
n68546 , n68547 , n68548 , n68549 , n68550 , n68551 , n68552 , n68553 , n68554 , n68555 ,
n68556 , n68557 , n68558 , n68559 , n68560 , n68561 , n68562 , n68563 , n68564 , n68565 ,
n68566 , n68567 , n68568 , n68569 , n68570 , n68571 , n68572 , n68573 , n68574 , n68575 ,
n68576 , n68577 , n68578 , n68579 , n68580 , n68581 , n68582 , n68583 , n68584 , n68585 ,
n68586 , n68587 , n68588 , n68589 , n68590 , n68591 , n68592 , n68593 , n68594 , n68595 ,
n68596 , n68597 , n68598 , n68599 , n68600 , n68601 , n68602 , n68603 , n68604 , n68605 ,
n68606 , n68607 , n68608 , n68609 , n68610 , n68611 , n68612 , n68613 , n68614 , n68615 ,
n68616 , n68617 , n68618 , n68619 , n68620 , n68621 , n68622 , n68623 , n68624 , n68625 ,
n68626 , n68627 , n68628 , n68629 , n68630 , n68631 , n68632 , n68633 , n68634 , n68635 ,
n68636 , n2498 , n2499 , n2500 , n2501 , n2502 , n2503 , n2504 , n68644 , n68645 ,
n68646 , n2508 , n2509 , n68649 , n68650 , n68651 , n2513 , n2514 , n2515 , n2516 ,
n2517 , n2518 , n2519 , n68659 , n68660 , n68661 , n2523 , n2524 , n68664 , n68665 ,
n68666 , n2528 , n2529 , n68669 , n68670 , n2532 , n2533 , n2534 , n68674 , n68675 ,
n68676 , n2538 , n2539 , n68679 , n68680 , n68681 , n2543 , n2544 , n68684 , n68685 ,
n2547 , n2548 , n2549 , n68689 , n68690 , n68691 , n2553 , n2554 , n68694 , n68695 ,
n68696 , n2558 , n2559 , n68699 , n68700 , n2562 , n2563 , n2564 , n68704 , n68705 ,
n68706 , n2568 , n2569 , n68709 , n68710 , n68711 , n2573 , n2574 , n68714 , n68715 ,
n2577 , n2578 , n2579 , n68719 , n68720 , n68721 , n2583 , n2584 , n68724 , n68725 ,
n68726 , n2588 , n2589 , n68729 , n68730 , n2592 , n2593 , n2594 , n68734 , n68735 ,
n68736 , n2598 , n2599 , n68739 , n68740 , n68741 , n2603 , n2604 , n2605 , n2606 ,
n68746 , n68747 , n2609 , n68749 , n68750 , n68751 , n2613 , n68753 , n68754 , n68755 ,
n68756 , n2618 , n68758 , n68759 , n2621 , n2622 , n2623 , n2624 , n68764 , n68765 ,
n68766 , n2628 , n2629 , n68769 , n68770 , n68771 , n2633 , n2634 , n2635 , n2636 ,
n2637 , n2638 , n2639 , n68779 , n68780 , n68781 , n2643 , n2644 , n68784 , n68785 ,
n68786 , n2648 , n2649 , n2650 , n2651 , n2652 , n2653 , n2654 , n68794 , n68795 ,
n68796 , n2658 , n2659 , n68799 , n68800 , n68801 , n2663 , n2664 , n2665 , n2666 ,
n2667 , n2668 , n2669 , n68809 , n68810 , n68811 , n2673 , n2674 , n68814 , n68815 ,
n68816 , n68817 , n68818 , n2680 , n2681 , n2682 , n68822 , n68823 , n68824 , n68825 ,
n68826 , n2688 , n2689 , n68829 , n68830 , n68831 , n2693 , n2694 , n2695 , n2696 ,
n2697 , n2698 , n68838 , n68839 , n68840 , n68841 , n2703 , n68843 , n68844 , n68845 ,
n68846 , n68847 , n68848 , n2710 , n68850 , n68851 , n68852 , n68853 , n68854 , n68855 ,
n68856 , n68857 , n68858 , n68859 , n68860 , n68861 , n68862 , n68863 , n68864 , n68865 ,
n68866 , n2728 , n68868 , n68869 , n68870 , n68871 , n68872 , n2734 , n68874 , n68875 ,
n68876 , n68877 , n68878 , n68879 , n68880 , n68881 , n68882 , n2744 , n68884 , n68885 ,
n68886 , n68887 , n68888 , n68889 , n68890 , n68891 , n2753 , n68893 , n68894 , n68895 ,
n68896 , n2758 , n68898 , n68899 , n68900 , n68901 , n68902 , n68903 , n68904 , n68905 ,
n68906 , n68907 , n68908 , n68909 , n68910 , n68911 , n68912 , n2774 , n68914 , n68915 ,
n68916 , n68917 , n68918 , n68919 , n68920 , n68921 , n68922 , n2784 , n68924 , n68925 ,
n68926 , n68927 , n68928 , n68929 , n68930 , n68931 , n68932 , n68933 , n68934 , n68935 ,
n68936 , n68937 , n68938 , n68939 , n68940 , n68941 , n68942 , n68943 , n68944 , n68945 ,
n68946 , n68947 , n68948 , n68949 , n68950 , n68951 , n68952 , n68953 , n68954 , n68955 ,
n68956 , n68957 , n68958 , n68959 , n68960 , n68961 , n68962 , n68963 , n68964 , n68965 ,
n68966 , n68967 , n68968 , n68969 , n68970 , n68971 , n68972 , n68973 , n68974 , n68975 ,
n68976 , n68977 , n68978 , n68979 , n68980 , n68981 , n68982 , n68983 , n68984 , n68985 ,
n68986 , n68987 , n68988 , n68989 , n68990 , n68991 , n68992 , n68993 , n68994 , n68995 ,
n68996 , n68997 , n68998 , n68999 , n69000 , n69001 , n69002 , n69003 , n69004 , n69005 ,
n69006 , n69007 , n69008 , n69009 , n69010 , n69011 , n69012 , n69013 , n69014 , n69015 ,
n69016 , n69017 , n69018 , n69019 , n69020 , n69021 , n69022 , n69023 , n69024 , n69025 ,
n69026 , n69027 , n69028 , n69029 , n69030 , n69031 , n69032 , n69033 , n69034 , n69035 ,
n69036 , n69037 , n69038 , n69039 , n69040 , n69041 , n69042 , n69043 , n69044 , n69045 ,
n69046 , n69047 , n69048 , n69049 , n69050 , n69051 , n69052 , n69053 , n69054 , n69055 ,
n69056 , n69057 , n69058 , n69059 , n69060 , n69061 , n69062 , n69063 , n69064 , n69065 ,
n69066 , n69067 , n69068 , n69069 , n69070 , n69071 , n69072 , n69073 , n69074 , n69075 ,
n69076 , n69077 , n69078 , n69079 , n69080 , n69081 , n69082 , n69083 , n69084 , n69085 ,
n69086 , n69087 , n69088 , n69089 , n69090 , n69091 , n69092 , n69093 , n69094 , n69095 ,
n69096 , n69097 , n69098 , n69099 , n69100 , n69101 , n69102 , n69103 , n69104 , n69105 ,
n69106 , n69107 , n69108 , n69109 , n69110 , n69111 , n69112 , n69113 , n69114 , n69115 ,
n69116 , n69117 , n69118 , n69119 , n69120 , n69121 , n69122 , n69123 , n69124 , n69125 ,
n69126 , n69127 , n69128 , n69129 , n69130 , n69131 , n69132 , n69133 , n69134 , n69135 ,
n69136 , n69137 , n69138 , n3000 , n69140 , n69141 , n69142 , n69143 , n69144 , n69145 ,
n69146 , n69147 , n69148 , n69149 , n69150 , n69151 , n69152 , n69153 , n69154 , n69155 ,
n69156 , n69157 , n69158 , n69159 , n69160 , n69161 , n69162 , n69163 , n69164 , n69165 ,
n69166 , n69167 , n69168 , n69169 , n69170 , n69171 , n69172 , n69173 , n69174 , n69175 ,
n69176 , n69177 , n69178 , n69179 , n69180 , n69181 , n69182 , n69183 , n69184 , n69185 ,
n69186 , n69187 , n69188 , n69189 , n69190 , n69191 , n69192 , n69193 , n69194 , n69195 ,
n69196 , n3058 , n3059 , n69199 , n69200 , n69201 , n69202 , n69203 , n69204 , n3066 ,
n69206 , n69207 , n69208 , n69209 , n69210 , n69211 , n69212 , n69213 , n69214 , n69215 ,
n69216 , n69217 , n69218 , n69219 , n69220 , n69221 , n69222 , n69223 , n69224 , n69225 ,
n69226 , n69227 , n69228 , n69229 , n69230 , n69231 , n69232 , n69233 , n69234 , n69235 ,
n69236 , n69237 , n69238 , n69239 , n69240 , n69241 , n69242 , n69243 , n69244 , n69245 ,
n69246 , n69247 , n69248 , n69249 , n69250 , n69251 , n69252 , n69253 , n69254 , n69255 ,
n69256 , n69257 , n69258 , n69259 , n69260 , n69261 , n69262 , n69263 , n69264 , n69265 ,
n69266 , n69267 , n69268 , n69269 , n69270 , n69271 , n69272 , n69273 , n69274 , n69275 ,
n69276 , n69277 , n69278 , n69279 , n69280 , n69281 , n69282 , n69283 , n69284 , n69285 ,
n69286 , n69287 , n69288 , n69289 , n69290 , n69291 , n69292 , n69293 , n69294 , n69295 ,
n69296 , n69297 , n69298 , n69299 , n69300 , n69301 , n69302 , n69303 , n69304 , n69305 ,
n69306 , n69307 , n69308 , n69309 , n69310 , n69311 , n69312 , n69313 , n69314 , n69315 ,
n69316 , n69317 , n69318 , n69319 , n69320 , n69321 , n69322 , n69323 , n69324 , n69325 ,
n69326 , n69327 , n69328 , n69329 , n69330 , n69331 , n69332 , n69333 , n69334 , n69335 ,
n69336 , n69337 , n69338 , n69339 , n69340 , n69341 , n69342 , n69343 , n69344 , n69345 ,
n69346 , n69347 , n69348 , n69349 , n69350 , n69351 , n69352 , n69353 , n69354 , n69355 ,
n69356 , n69357 , n69358 , n69359 , n69360 , n69361 , n69362 , n69363 , n69364 , n69365 ,
n69366 , n69367 , n69368 , n69369 , n69370 , n69371 , n69372 , n69373 , n69374 , n69375 ,
n69376 , n69377 , n69378 , n69379 , n69380 , n69381 , n69382 , n69383 , n69384 , n69385 ,
n69386 , n69387 , n69388 , n69389 , n69390 , n69391 , n69392 , n69393 , n69394 , n69395 ,
n69396 , n69397 , n69398 , n69399 , n69400 , n69401 , n69402 , n69403 , n69404 , n69405 ,
n69406 , n69407 , n69408 , n69409 , n69410 , n69411 , n69412 , n69413 , n69414 , n3276 ,
n69416 , n69417 , n69418 , n69419 , n69420 , n3282 , n69422 , n69423 , n69424 , n69425 ,
n69426 , n3288 , n69428 , n69429 , n69430 , n3292 , n69432 , n69433 , n69434 , n69435 ,
n69436 , n69437 , n69438 , n69439 , n3301 , n69441 , n69442 , n3304 , n69444 , n69445 ,
n69446 , n69447 , n69448 , n69449 , n69450 , n69451 , n69452 , n69453 , n69454 , n3316 ,
n69456 , n69457 , n69458 , n3320 , n69460 , n69461 , n69462 , n3324 , n69464 , n69465 ,
n3327 , n69467 , n69468 , n69469 , n69470 , n69471 , n69472 , n69473 , n69474 , n3336 ,
n69476 , n69477 , n69478 , n69479 , n69480 , n3342 , n69482 , n3344 , n69484 , n3346 ,
n69486 , n69487 , n69488 , n3350 , n69490 , n69491 , n69492 , n69493 , n69494 , n3356 ,
n69496 , n69497 , n3359 , n69499 , n69500 , n69501 , n69502 , n69503 , n69504 , n69505 ,
n69506 , n69507 , n69508 , n69509 , n69510 , n69511 , n69512 , n69513 , n69514 , n69515 ,
n69516 , n69517 , n69518 , n69519 , n69520 , n69521 , n69522 , n69523 , n69524 , n69525 ,
n69526 , n69527 , n69528 , n69529 , n69530 , n69531 , n69532 , n69533 , n69534 , n69535 ,
n69536 , n69537 , n69538 , n69539 , n69540 , n69541 , n69542 , n69543 , n3405 , n69545 ,
n69546 , n69547 , n69548 , n69549 , n69550 , n3412 , n69552 , n69553 , n69554 , n69555 ,
n69556 , n69557 , n69558 , n69559 , n69560 , n69561 , n69562 , n69563 , n69564 , n69565 ,
n69566 , n69567 , n69568 , n69569 , n69570 , n69571 , n69572 , n69573 , n69574 , n69575 ,
n69576 , n69577 , n69578 , n69579 , n69580 , n3442 , n69582 , n69583 , n69584 , n69585 ,
n69586 , n69587 , n69588 , n3450 , n69590 , n69591 , n69592 , n3454 , n69594 , n69595 ,
n69596 , n69597 , n69598 , n69599 , n69600 , n69601 , n69602 , n69603 , n69604 , n3466 ,
n69606 , n69607 , n69608 , n3470 , n69610 , n69611 , n69612 , n69613 , n69614 , n69615 ,
n69616 , n69617 , n69618 , n69619 , n69620 , n69621 , n69622 , n69623 , n69624 , n69625 ,
n69626 , n69627 , n3489 , n69629 , n69630 , n69631 , n69632 , n69633 , n69634 , n69635 ,
n69636 , n3498 , n69638 , n69639 , n69640 , n69641 , n69642 , n69643 , n69644 , n69645 ,
n69646 , n69647 , n69648 , n3510 , n69650 , n69651 , n69652 , n3514 , n69654 , n69655 ,
n69656 , n69657 , n69658 , n69659 , n69660 , n69661 , n69662 , n69663 , n69664 , n69665 ,
n69666 , n69667 , n3529 , n69669 , n69670 , n69671 , n69672 , n69673 , n69674 , n69675 ,
n69676 , n69677 , n69678 , n69679 , n69680 , n69681 , n69682 , n69683 , n69684 , n69685 ,
n69686 , n69687 , n69688 , n69689 , n69690 , n3552 , n69692 , n69693 , n69694 , n69695 ,
n69696 , n69697 , n69698 , n69699 , n3561 , n69701 , n69702 , n69703 , n69704 , n69705 ,
n69706 , n69707 , n3569 , n69709 , n69710 , n69711 , n69712 , n69713 , n69714 , n69715 ,
n69716 , n69717 , n69718 , n3580 , n69720 , n69721 , n69722 , n3584 , n69724 , n69725 ,
n69726 , n69727 , n69728 , n69729 , n3591 , n69731 , n69732 , n69733 , n69734 , n69735 ,
n69736 , n69737 , n69738 , n69739 , n69740 , n69741 , n69742 , n69743 , n69744 , n69745 ,
n69746 , n69747 , n69748 , n69749 , n69750 , n69751 , n69752 , n69753 , n69754 , n69755 ,
n69756 , n69757 , n69758 , n3620 , n69760 , n69761 , n69762 , n69763 , n69764 , n69765 ,
n69766 , n69767 , n69768 , n69769 , n69770 , n69771 , n69772 , n69773 , n69774 , n3636 ,
n69776 , n69777 , n69778 , n69779 , n69780 , n69781 , n69782 , n69783 , n69784 , n69785 ,
n69786 , n69787 , n69788 , n69789 , n69790 , n69791 , n69792 , n69793 , n69794 , n69795 ,
n69796 , n69797 , n69798 , n69799 , n69800 , n69801 , n69802 , n69803 , n69804 , n69805 ,
n69806 , n69807 , n69808 , n69809 , n69810 , n69811 , n69812 , n69813 , n69814 , n69815 ,
n69816 , n69817 , n69818 , n69819 , n69820 , n69821 , n69822 , n69823 , n69824 , n69825 ,
n69826 , n69827 , n69828 , n69829 , n69830 , n69831 , n69832 , n69833 , n69834 , n69835 ,
n69836 , n69837 , n69838 , n69839 , n69840 , n69841 , n69842 , n69843 , n69844 , n69845 ,
n3707 , n69847 , n69848 , n69849 , n69850 , n69851 , n69852 , n69853 , n69854 , n69855 ,
n69856 , n69857 , n69858 , n69859 , n3721 , n69861 , n69862 , n69863 , n69864 , n69865 ,
n69866 , n69867 , n69868 , n69869 , n69870 , n69871 , n69872 , n69873 , n69874 , n69875 ,
n69876 , n69877 , n69878 , n69879 , n69880 , n69881 , n69882 , n69883 , n69884 , n69885 ,
n69886 , n69887 , n69888 , n69889 , n69890 , n69891 , n69892 , n69893 , n69894 , n69895 ,
n69896 , n69897 , n69898 , n69899 , n69900 , n69901 , n69902 , n69903 , n69904 , n69905 ,
n69906 , n69907 , n69908 , n69909 , n3771 , n69911 , n69912 , n69913 , n69914 , n69915 ,
n69916 , n69917 , n69918 , n69919 , n69920 , n69921 , n69922 , n69923 , n69924 , n69925 ,
n69926 , n69927 , n69928 , n69929 , n69930 , n69931 , n69932 , n69933 , n69934 , n69935 ,
n69936 , n69937 , n3799 , n69939 , n69940 , n69941 , n69942 , n69943 , n69944 , n69945 ,
n69946 , n69947 , n69948 , n69949 , n69950 , n69951 , n69952 , n69953 , n3815 , n69955 ,
n69956 , n69957 , n69958 , n69959 , n69960 , n69961 , n69962 , n69963 , n69964 , n69965 ,
n69966 , n69967 , n69968 , n69969 , n69970 , n69971 , n69972 , n69973 , n69974 , n69975 ,
n69976 , n69977 , n69978 , n69979 , n69980 , n69981 , n69982 , n69983 , n69984 , n69985 ,
n69986 , n69987 , n69988 , n69989 , n69990 , n69991 , n69992 , n69993 , n69994 , n69995 ,
n69996 , n69997 , n69998 , n69999 , n70000 , n70001 , n70002 , n70003 , n70004 , n70005 ,
n70006 , n70007 , n70008 , n70009 , n70010 , n70011 , n70012 , n70013 , n70014 , n70015 ,
n70016 , n70017 , n70018 , n70019 , n70020 , n70021 , n70022 , n70023 , n70024 , n70025 ,
n70026 , n70027 , n70028 , n70029 , n70030 , n70031 , n70032 , n70033 , n70034 , n70035 ,
n70036 , n70037 , n70038 , n70039 , n70040 , n70041 , n70042 , n70043 , n70044 , n70045 ,
n70046 , n70047 , n70048 , n70049 , n70050 , n70051 , n70052 , n70053 , n3915 , n70055 ,
n70056 , n70057 , n70058 , n70059 , n70060 , n70061 , n70062 , n70063 , n70064 , n70065 ,
n70066 , n70067 , n70068 , n70069 , n70070 , n70071 , n70072 , n70073 , n70074 , n70075 ,
n70076 , n70077 , n70078 , n70079 , n70080 , n70081 , n70082 , n70083 , n70084 , n70085 ,
n70086 , n70087 , n70088 , n70089 , n70090 , n70091 , n70092 , n70093 , n70094 , n70095 ,
n70096 , n70097 , n70098 , n70099 , n70100 , n70101 , n70102 , n70103 , n70104 , n70105 ,
n70106 , n70107 , n70108 , n70109 , n70110 , n70111 , n70112 , n70113 , n70114 , n70115 ,
n70116 , n70117 , n70118 , n70119 , n70120 , n70121 , n70122 , n70123 , n70124 , n70125 ,
n70126 , n70127 , n70128 , n70129 , n70130 , n70131 , n70132 , n70133 , n70134 , n70135 ,
n70136 , n70137 , n70138 , n70139 , n70140 , n70141 , n70142 , n70143 , n70144 , n70145 ,
n70146 , n70147 , n70148 , n70149 , n70150 , n70151 , n70152 , n70153 , n70154 , n70155 ,
n70156 , n70157 , n70158 , n70159 , n70160 , n70161 , n70162 , n70163 , n70164 , n70165 ,
n70166 , n70167 , n70168 , n70169 , n70170 , n70171 , n70172 , n70173 , n70174 , n70175 ,
n70176 , n70177 , n70178 , n70179 , n70180 , n70181 , n70182 , n70183 , n70184 , n70185 ,
n70186 , n70187 , n70188 , n70189 , n70190 , n70191 , n70192 , n70193 , n70194 , n70195 ,
n70196 , n70197 , n70198 , n70199 , n70200 , n70201 , n70202 , n70203 , n70204 , n70205 ,
n70206 , n70207 , n70208 , n70209 , n70210 , n70211 , n70212 , n70213 , n70214 , n70215 ,
n70216 , n70217 , n70218 , n70219 , n70220 , n70221 , n70222 , n70223 , n70224 , n70225 ,
n70226 , n70227 , n70228 , n70229 , n70230 , n70231 , n70232 , n70233 , n70234 , n70235 ,
n70236 , n70237 , n70238 , n70239 , n70240 , n70241 , n70242 , n70243 , n70244 , n70245 ,
n70246 , n70247 , n70248 , n70249 , n70250 , n70251 , n70252 , n70253 , n70254 , n70255 ,
n70256 , n70257 , n70258 , n70259 , n70260 , n70261 , n70262 , n70263 , n70264 , n70265 ,
n70266 , n70267 , n70268 , n70269 , n70270 , n70271 , n70272 , n70273 , n70274 , n70275 ,
n70276 , n70277 , n70278 , n70279 , n70280 , n70281 , n70282 , n70283 , n70284 , n70285 ,
n70286 , n70287 , n70288 , n70289 , n70290 , n70291 , n70292 , n70293 , n70294 , n70295 ,
n70296 , n70297 , n70298 , n70299 , n70300 , n70301 , n70302 , n70303 , n70304 , n70305 ,
n70306 , n70307 , n70308 , n70309 , n70310 , n70311 , n70312 , n70313 , n70314 , n70315 ,
n70316 , n70317 , n70318 , n70319 , n70320 , n70321 , n70322 , n70323 , n70324 , n70325 ,
n70326 , n70327 , n70328 , n70329 , n70330 , n70331 , n70332 , n70333 , n70334 , n70335 ,
n70336 , n70337 , n70338 , n70339 , n70340 , n70341 , n70342 , n70343 , n70344 , n70345 ,
n70346 , n70347 , n70348 , n70349 , n70350 , n70351 , n70352 , n70353 , n70354 , n70355 ,
n70356 , n70357 , n70358 , n70359 , n70360 , n70361 , n70362 , n70363 , n70364 , n70365 ,
n70366 , n70367 , n70368 , n70369 , n70370 , n70371 , n70372 , n70373 , n70374 , n70375 ,
n70376 , n70377 , n70378 , n70379 , n70380 , n70381 , n70382 , n70383 , n70384 , n70385 ,
n70386 , n70387 , n70388 , n70389 , n70390 , n70391 , n70392 , n70393 , n70394 , n70395 ,
n70396 , n70397 , n70398 , n70399 , n70400 , n70401 , n70402 , n70403 , n70404 , n70405 ,
n70406 , n70407 , n70408 , n70409 , n70410 , n70411 , n70412 , n70413 , n70414 , n70415 ,
n70416 , n70417 , n70418 , n70419 , n70420 , n70421 , n70422 , n70423 , n70424 , n70425 ,
n70426 , n70427 , n70428 , n70429 , n70430 , n70431 , n70432 , n70433 , n70434 , n70435 ,
n70436 , n70437 , n70438 , n70439 , n70440 , n70441 , n70442 , n70443 , n70444 , n70445 ,
n70446 , n70447 , n70448 , n70449 , n70450 , n70451 , n70452 , n70453 , n70454 , n70455 ,
n70456 , n70457 , n70458 , n70459 , n70460 , n70461 , n70462 , n70463 , n70464 , n70465 ,
n70466 , n70467 , n70468 , n70469 , n70470 , n70471 , n70472 , n70473 , n70474 , n70475 ,
n70476 , n70477 , n70478 , n70479 , n70480 , n70481 , n70482 , n70483 , n70484 , n70485 ,
n70486 , n70487 , n70488 , n70489 , n70490 , n70491 , n70492 , n70493 , n70494 , n70495 ,
n70496 , n70497 , n70498 , n70499 , n70500 , n70501 , n70502 , n70503 , n70504 , n70505 ,
n70506 , n70507 , n70508 , n70509 , n70510 , n70511 , n70512 , n70513 , n70514 , n70515 ,
n70516 , n70517 , n70518 , n70519 , n70520 , n70521 , n70522 , n70523 , n70524 , n70525 ,
n70526 , n70527 , n70528 , n70529 , n70530 , n70531 , n70532 , n70533 , n70534 , n70535 ,
n70536 , n70537 , n70538 , n70539 , n70540 , n70541 , n70542 , n70543 , n70544 , n70545 ,
n70546 , n70547 , n70548 , n70549 , n70550 , n70551 , n70552 , n70553 , n70554 , n70555 ,
n70556 , n70557 , n70558 , n70559 , n70560 , n70561 , n70562 , n70563 , n70564 , n70565 ,
n70566 , n70567 , n70568 , n70569 , n70570 , n70571 , n70572 , n70573 , n70574 , n70575 ,
n70576 , n70577 , n70578 , n70579 , n70580 , n70581 , n70582 , n70583 , n70584 , n70585 ,
n70586 , n70587 , n70588 , n70589 , n70590 , n70591 , n70592 , n70593 , n70594 , n70595 ,
n70596 , n70597 , n70598 , n70599 , n70600 , n70601 , n70602 , n70603 , n70604 , n70605 ,
n70606 , n70607 , n70608 , n70609 , n70610 , n70611 , n70612 , n70613 , n70614 , n70615 ,
n70616 , n70617 , n70618 , n70619 , n70620 , n70621 , n70622 , n70623 , n70624 , n70625 ,
n70626 , n70627 , n70628 , n70629 , n70630 , n70631 , n70632 , n70633 , n70634 , n70635 ,
n70636 , n70637 , n70638 , n70639 , n70640 , n70641 , n70642 , n70643 , n70644 , n70645 ,
n70646 , n70647 , n70648 , n70649 , n70650 , n70651 , n70652 , n70653 , n70654 , n70655 ,
n70656 , n70657 , n70658 , n70659 , n70660 , n70661 , n70662 , n70663 , n70664 , n70665 ,
n70666 , n70667 , n70668 , n70669 , n70670 , n70671 , n70672 , n70673 , n70674 , n70675 ,
n70676 , n70677 , n70678 , n70679 , n70680 , n70681 , n70682 , n70683 , n70684 , n70685 ,
n70686 , n70687 , n70688 , n70689 , n70690 , n70691 , n70692 , n70693 , n70694 , n70695 ,
n70696 , n70697 , n70698 , n70699 , n70700 , n70701 , n70702 , n70703 , n70704 , n70705 ,
n70706 , n70707 , n70708 , n70709 , n70710 , n70711 , n70712 , n70713 , n70714 , n70715 ,
n70716 , n70717 , n70718 , n70719 , n70720 , n70721 , n70722 , n70723 , n70724 , n70725 ,
n70726 , n70727 , n70728 , n70729 , n70730 , n70731 , n70732 , n70733 , n70734 , n70735 ,
n70736 , n70737 , n70738 , n70739 , n70740 , n70741 , n70742 , n70743 , n70744 , n70745 ,
n70746 , n70747 , n70748 , n70749 , n70750 , n70751 , n70752 , n70753 , n70754 , n70755 ,
n70756 , n70757 , n70758 , n70759 , n70760 , n70761 , n70762 , n70763 , n70764 , n70765 ,
n70766 , n70767 , n70768 , n70769 , n70770 , n70771 , n70772 , n70773 , n70774 , n70775 ,
n70776 , n70777 , n70778 , n70779 , n70780 , n70781 , n70782 , n70783 , n70784 , n70785 ,
n70786 , n70787 , n70788 , n70789 , n70790 , n70791 , n70792 , n70793 , n70794 , n70795 ,
n70796 , n70797 , n70798 , n70799 , n70800 , n70801 , n70802 , n70803 , n70804 , n70805 ,
n70806 , n70807 , n70808 , n70809 , n70810 , n70811 , n70812 , n70813 , n70814 , n70815 ,
n70816 , n70817 , n70818 , n70819 , n70820 , n70821 , n70822 , n70823 , n70824 , n70825 ,
n70826 , n70827 , n70828 , n70829 , n70830 , n70831 , n70832 , n70833 , n70834 , n70835 ,
n70836 , n70837 , n70838 , n70839 , n70840 , n70841 , n70842 , n70843 , n70844 , n70845 ,
n70846 , n70847 , n70848 , n70849 , n70850 , n70851 , n70852 , n70853 , n70854 , n70855 ,
n70856 , n70857 , n70858 , n70859 , n70860 , n70861 , n70862 , n70863 , n70864 , n70865 ,
n70866 , n70867 , n70868 , n70869 , n70870 , n70871 , n70872 , n70873 , n70874 , n70875 ,
n70876 , n70877 , n70878 , n70879 , n70880 , n70881 , n70882 , n70883 , n70884 , n70885 ,
n70886 , n70887 , n70888 , n70889 , n70890 , n70891 , n70892 , n70893 , n70894 , n70895 ,
n70896 , n70897 , n70898 , n70899 , n70900 , n70901 , n70902 , n70903 , n70904 , n70905 ,
n70906 , n70907 , n4769 , n4770 , n70910 , n70911 , n70912 , n70913 , n70914 , n70915 ,
n70916 , n70917 , n70918 , n70919 , n70920 , n70921 , n70922 , n70923 , n70924 , n70925 ,
n70926 , n70927 , n70928 , n70929 , n70930 , n70931 , n70932 , n70933 , n70934 , n70935 ,
n70936 , n70937 , n70938 , n70939 , n70940 , n70941 , n70942 , n70943 , n70944 , n70945 ,
n70946 , n70947 , n70948 , n70949 , n70950 , n70951 , n70952 , n70953 , n70954 , n70955 ,
n70956 , n70957 , n70958 , n70959 , n70960 , n70961 , n70962 , n70963 , n70964 , n70965 ,
n70966 , n70967 , n70968 , n70969 , n70970 , n70971 , n70972 , n70973 , n70974 , n70975 ,
n70976 , n70977 , n70978 , n70979 , n70980 , n70981 , n70982 , n70983 , n70984 , n70985 ,
n70986 , n70987 , n70988 , n70989 , n70990 , n70991 , n70992 , n70993 , n70994 , n70995 ,
n70996 , n70997 , n70998 , n70999 , n71000 , n71001 , n71002 , n71003 , n71004 , n71005 ,
n71006 , n71007 , n71008 , n71009 , n71010 , n71011 , n71012 , n71013 , n71014 , n71015 ,
n71016 , n71017 , n71018 , n71019 , n4881 , n71021 , n71022 , n4884 , n4885 , n71025 ,
n71026 , n71027 , n71028 , n71029 , n71030 , n71031 , n71032 , n71033 , n71034 , n71035 ,
n71036 , n71037 , n71038 , n71039 , n71040 , n71041 , n71042 , n71043 , n71044 , n71045 ,
n71046 , n71047 , n71048 , n71049 , n71050 , n71051 , n71052 , n71053 , n71054 , n71055 ,
n71056 , n71057 , n71058 , n71059 , n71060 , n71061 , n71062 , n71063 , n71064 , n71065 ,
n71066 , n71067 , n71068 , n71069 , n71070 , n71071 , n71072 , n71073 , n71074 , n71075 ,
n71076 , n71077 , n71078 , n71079 , n71080 , n71081 , n71082 , n71083 , n71084 , n71085 ,
n71086 , n71087 , n71088 , n71089 , n71090 , n71091 , n71092 , n71093 , n71094 , n71095 ,
n71096 , n71097 , n71098 , n71099 , n71100 , n71101 , n71102 , n71103 , n71104 , n71105 ,
n71106 , n71107 , n71108 , n71109 , n71110 , n71111 , n71112 , n71113 , n71114 , n71115 ,
n71116 , n71117 , n71118 , n71119 , n71120 , n71121 , n71122 , n71123 , n71124 , n71125 ,
n71126 , n71127 , n71128 , n71129 , n71130 , n71131 , n71132 , n71133 , n71134 , n71135 ,
n71136 , n71137 , n71138 , n71139 , n71140 , n71141 , n71142 , n71143 , n71144 , n71145 ,
n71146 , n71147 , n71148 , n71149 , n71150 , n71151 , n71152 , n71153 , n71154 , n71155 ,
n71156 , n71157 , n71158 , n71159 , n71160 , n71161 , n71162 , n71163 , n71164 , n71165 ,
n71166 , n71167 , n71168 , n71169 , n71170 , n71171 , n71172 , n71173 , n71174 , n71175 ,
n71176 , n71177 , n71178 , n71179 , n71180 , n71181 , n71182 , n71183 , n71184 , n71185 ,
n71186 , n71187 , n71188 , n71189 , n71190 , n71191 , n71192 , n71193 , n71194 , n71195 ,
n71196 , n71197 , n71198 , n71199 , n71200 , n71201 , n71202 , n71203 , n71204 , n71205 ,
n71206 , n71207 , n71208 , n71209 , n5071 , n5072 , n71212 , n5074 , n5075 , n71215 ,
n71216 , n71217 , n71218 , n71219 , n71220 , n71221 , n71222 , n71223 , n71224 , n71225 ,
n71226 , n71227 , n71228 , n71229 , n71230 , n71231 , n71232 , n71233 , n71234 , n71235 ,
n71236 , n71237 , n71238 , n71239 , n71240 , n71241 , n71242 , n71243 , n71244 , n71245 ,
n71246 , n71247 , n71248 , n71249 , n71250 , n71251 , n71252 , n71253 , n71254 , n71255 ,
n71256 , n71257 , n71258 , n71259 , n71260 , n71261 , n71262 , n71263 , n71264 , n71265 ,
n71266 , n5128 , n71268 , n71269 , n71270 , n5132 , n71272 , n71273 , n71274 , n71275 ,
n71276 , n71277 , n71278 , n71279 , n71280 , n71281 , n71282 , n71283 , n71284 , n71285 ,
n71286 , n71287 , n71288 , n71289 , n71290 , n71291 , n71292 , n71293 , n71294 , n71295 ,
n71296 , n71297 , n71298 , n71299 , n71300 , n71301 , n71302 , n71303 , n71304 , n71305 ,
n71306 , n71307 , n71308 , n71309 , n71310 , n71311 , n71312 , n71313 , n71314 , n71315 ,
n71316 , n71317 , n71318 , n71319 , n71320 , n71321 , n71322 , n71323 , n71324 , n71325 ,
n71326 , n71327 , n71328 , n71329 , n71330 , n71331 , n71332 , n71333 , n71334 , n71335 ,
n71336 , n71337 , n71338 , n71339 , n71340 , n71341 , n71342 , n71343 , n71344 , n71345 ,
n71346 , n71347 , n71348 , n71349 , n71350 , n71351 , n71352 , n71353 , n71354 , n71355 ,
n71356 , n71357 , n71358 , n71359 , n71360 , n71361 , n71362 , n71363 , n71364 , n71365 ,
n71366 , n71367 , n71368 , n71369 , n71370 , n71371 , n71372 , n71373 , n71374 , n71375 ,
n71376 , n71377 , n71378 , n71379 , n71380 , n71381 , n71382 , n71383 , n71384 , n71385 ,
n71386 , n71387 , n71388 , n71389 , n71390 , n71391 , n71392 , n71393 , n71394 , n71395 ,
n71396 , n71397 , n71398 , n71399 , n71400 , n71401 , n71402 , n71403 , n71404 , n71405 ,
n71406 , n71407 , n71408 , n71409 , n71410 , n71411 , n71412 , n71413 , n71414 , n71415 ,
n71416 , n71417 , n71418 , n71419 , n71420 , n71421 , n71422 , n71423 , n71424 , n71425 ,
n71426 , n71427 , n71428 , n71429 , n71430 , n71431 , n71432 , n71433 , n71434 , n71435 ,
n71436 , n71437 , n71438 , n5300 , n71440 , n71441 , n71442 , n5304 , n71444 , n71445 ,
n71446 , n71447 , n71448 , n71449 , n71450 , n71451 , n71452 , n71453 , n71454 , n71455 ,
n71456 , n71457 , n71458 , n71459 , n71460 , n71461 , n71462 , n71463 , n71464 , n71465 ,
n71466 , n71467 , n71468 , n71469 , n71470 , n71471 , n71472 , n71473 , n71474 , n71475 ,
n71476 , n71477 , n71478 , n71479 , n71480 , n71481 , n71482 , n71483 , n71484 , n71485 ,
n71486 , n71487 , n71488 , n71489 , n71490 , n71491 , n71492 , n71493 , n71494 , n71495 ,
n71496 , n71497 , n71498 , n71499 , n71500 , n71501 , n71502 , n71503 , n71504 , n71505 ,
n71506 , n71507 , n71508 , n71509 , n71510 , n71511 , n71512 , n5374 , n71514 , n71515 ,
n71516 , n71517 , n71518 , n71519 , n71520 , n71521 , n71522 , n71523 , n71524 , n71525 ,
n71526 , n71527 , n71528 , n71529 , n71530 , n71531 , n71532 , n71533 , n71534 , n71535 ,
n71536 , n71537 , n71538 , n71539 , n71540 , n71541 , n71542 , n71543 , n71544 , n71545 ,
n71546 , n71547 , n71548 , n71549 , n71550 , n71551 , n71552 , n71553 , n71554 , n71555 ,
n71556 , n71557 , n71558 , n71559 , n71560 , n71561 , n71562 , n71563 , n71564 , n71565 ,
n71566 , n71567 , n71568 , n71569 , n71570 , n71571 , n71572 , n71573 , n71574 , n71575 ,
n71576 , n71577 , n5439 , n5440 , n71580 , n71581 , n71582 , n71583 , n71584 , n71585 ,
n71586 , n71587 , n71588 , n71589 , n71590 , n71591 , n71592 , n71593 , n71594 , n71595 ,
n71596 , n71597 , n71598 , n71599 , n71600 , n71601 , n71602 , n71603 , n71604 , n71605 ,
n71606 , n71607 , n71608 , n71609 , n71610 , n71611 , n71612 , n71613 , n71614 , n71615 ,
n71616 , n71617 , n71618 , n71619 , n71620 , n71621 , n71622 , n71623 , n71624 , n71625 ,
n71626 , n71627 , n71628 , n71629 , n71630 , n71631 , n71632 , n71633 , n71634 , n71635 ,
n71636 , n71637 , n71638 , n71639 , n71640 , n71641 , n71642 , n71643 , n71644 , n71645 ,
n71646 , n71647 , n71648 , n71649 , n71650 , n71651 , n71652 , n71653 , n71654 , n71655 ,
n71656 , n71657 , n71658 , n71659 , n71660 , n71661 , n71662 , n71663 , n71664 , n71665 ,
n71666 , n71667 , n71668 , n71669 , n71670 , n71671 , n71672 , n71673 , n71674 , n71675 ,
n71676 , n71677 , n71678 , n71679 , n71680 , n71681 , n71682 , n71683 , n71684 , n71685 ,
n71686 , n71687 , n71688 , n71689 , n71690 , n71691 , n71692 , n71693 , n71694 , n71695 ,
n71696 , n71697 , n71698 , n71699 , n71700 , n71701 , n71702 , n71703 , n71704 , n71705 ,
n71706 , n71707 , n71708 , n71709 , n71710 , n71711 , n71712 , n71713 , n71714 , n71715 ,
n71716 , n71717 , n71718 , n71719 , n71720 , n5582 , n71722 , n71723 , n71724 , n71725 ,
n71726 , n71727 , n71728 , n71729 , n5591 , n5592 , n71732 , n5594 , n5595 , n71735 ,
n71736 , n71737 , n71738 , n71739 , n5601 , n71741 , n71742 , n5604 , n71744 , n71745 ,
n71746 , n71747 , n71748 , n71749 , n71750 , n71751 , n71752 , n71753 , n71754 , n71755 ,
n71756 , n71757 , n71758 , n71759 , n71760 , n71761 , n71762 , n71763 , n71764 , n71765 ,
n71766 , n71767 , n71768 , n71769 , n5631 , n71771 , n71772 , n71773 , n71774 , n71775 ,
n71776 , n71777 , n71778 , n71779 , n71780 , n71781 , n71782 , n5644 , n5645 , n71785 ,
n71786 , n71787 , n71788 , n71789 , n71790 , n71791 , n71792 , n71793 , n71794 , n71795 ,
n71796 , n71797 , n71798 , n71799 , n71800 , n71801 , n71802 , n5664 , n71804 , n71805 ,
n71806 , n71807 , n71808 , n71809 , n71810 , n71811 , n71812 , n71813 , n71814 , n71815 ,
n71816 , n71817 , n71818 , n71819 , n5681 , n5682 , n71822 , n71823 , n71824 , n71825 ,
n71826 , n71827 , n71828 , n71829 , n71830 , n71831 , n71832 , n71833 , n71834 , n71835 ,
n71836 , n71837 , n71838 , n71839 , n5701 , n5702 , n71842 , n71843 , n71844 , n71845 ,
n71846 , n71847 , n71848 , n71849 , n71850 , n71851 , n71852 , n71853 , n71854 , n71855 ,
n71856 , n71857 , n71858 , n71859 , n71860 , n71861 , n71862 , n71863 , n71864 , n71865 ,
n71866 , n71867 , n71868 , n71869 , n71870 , n71871 , n71872 , n5734 , n71874 , n71875 ,
n71876 , n71877 , n71878 , n71879 , n71880 , n5742 , n71882 , n71883 , n5745 , n71885 ,
n71886 , n71887 , n71888 , n71889 , n5751 , n5752 , n71892 , n5754 , n5755 , n71895 ,
n71896 , n71897 , n71898 , n71899 , n71900 , n71901 , n71902 , n71903 , n71904 , n71905 ,
n71906 , n71907 , n71908 , n71909 , n71910 , n71911 , n71912 , n71913 , n71914 , n71915 ,
n71916 , n71917 , n71918 , n71919 , n71920 , n71921 , n71922 , n71923 , n71924 , n71925 ,
n71926 , n71927 , n71928 , n71929 , n71930 , n71931 , n71932 , n71933 , n71934 , n71935 ,
n71936 , n71937 , n71938 , n71939 , n71940 , n71941 , n71942 , n71943 , n71944 , n71945 ,
n71946 , n71947 , n71948 , n71949 , n71950 , n71951 , n71952 , n71953 , n71954 , n71955 ,
n71956 , n71957 , n71958 , n71959 , n71960 , n71961 , n71962 , n71963 , n71964 , n71965 ,
n71966 , n71967 , n71968 , n71969 , n71970 , n71971 , n71972 , n71973 , n71974 , n71975 ,
n71976 , n71977 , n71978 , n71979 , n71980 , n71981 , n71982 , n71983 , n71984 , n71985 ,
n71986 , n71987 , n71988 , n71989 , n71990 , n71991 , n71992 , n71993 , n71994 , n71995 ,
n71996 , n71997 , n71998 , n71999 , n72000 , n72001 , n72002 , n72003 , n72004 , n72005 ,
n72006 , n72007 , n72008 , n72009 , n72010 , n72011 , n72012 , n72013 , n72014 , n72015 ,
n72016 , n72017 , n72018 , n72019 , n72020 , n72021 , n72022 , n72023 , n72024 , n72025 ,
n72026 , n72027 , n5889 , n72029 , n72030 , n72031 , n72032 , n72033 , n72034 , n72035 ,
n72036 , n72037 , n72038 , n72039 , n72040 , n72041 , n72042 , n72043 , n72044 , n72045 ,
n72046 , n72047 , n72048 , n72049 , n72050 , n72051 , n72052 , n72053 , n72054 , n72055 ,
n72056 , n72057 , n72058 , n72059 , n72060 , n72061 , n72062 , n72063 , n72064 , n72065 ,
n72066 , n72067 , n72068 , n72069 , n72070 , n72071 , n72072 , n72073 , n72074 , n72075 ,
n72076 , n72077 , n72078 , n72079 , n72080 , n72081 , n72082 , n72083 , n72084 , n72085 ,
n72086 , n72087 , n72088 , n72089 , n72090 , n72091 , n72092 , n72093 , n72094 , n72095 ,
n72096 , n72097 , n72098 , n72099 , n72100 , n72101 , n72102 , n72103 , n72104 , n72105 ,
n72106 , n72107 , n72108 , n72109 , n72110 , n72111 , n72112 , n72113 , n72114 , n72115 ,
n72116 , n72117 , n72118 , n72119 , n72120 , n72121 , n72122 , n72123 , n72124 , n72125 ,
n72126 , n72127 , n72128 , n72129 , n72130 , n72131 , n72132 , n72133 , n72134 , n72135 ,
n72136 , n72137 , n72138 , n72139 , n72140 , n72141 , n72142 , n72143 , n72144 , n72145 ,
n72146 , n72147 , n72148 , n72149 , n72150 , n72151 , n72152 , n72153 , n72154 , n72155 ,
n6017 , n72157 , n72158 , n72159 , n6021 , n72161 , n72162 , n72163 , n72164 , n72165 ,
n72166 , n72167 , n72168 , n72169 , n72170 , n72171 , n72172 , n72173 , n72174 , n72175 ,
n72176 , n72177 , n72178 , n72179 , n72180 , n72181 , n72182 , n72183 , n72184 , n72185 ,
n72186 , n72187 , n72188 , n72189 , n72190 , n72191 , n72192 , n72193 , n72194 , n72195 ,
n72196 , n72197 , n72198 , n72199 , n72200 , n72201 , n72202 , n72203 , n72204 , n72205 ,
n72206 , n72207 , n72208 , n72209 , n72210 , n72211 , n72212 , n72213 , n72214 , n72215 ,
n6077 , n72217 , n72218 , n72219 , n72220 , n72221 , n72222 , n72223 , n72224 , n72225 ,
n72226 , n72227 , n72228 , n72229 , n72230 , n72231 , n72232 , n72233 , n72234 , n72235 ,
n72236 , n72237 , n72238 , n72239 , n72240 , n72241 , n72242 , n72243 , n72244 , n72245 ,
n72246 , n72247 , n72248 , n72249 , n72250 , n72251 , n72252 , n72253 , n72254 , n72255 ,
n72256 , n72257 , n72258 , n72259 , n72260 , n72261 , n72262 , n72263 , n72264 , n72265 ,
n72266 , n72267 , n72268 , n72269 , n72270 , n72271 , n72272 , n72273 , n72274 , n6136 ,
n6137 , n72277 , n72278 , n72279 , n72280 , n72281 , n72282 , n72283 , n72284 , n72285 ,
n72286 , n72287 , n72288 , n72289 , n72290 , n72291 , n72292 , n72293 , n72294 , n72295 ,
n72296 , n72297 , n72298 , n72299 , n72300 , n72301 , n72302 , n72303 , n72304 , n72305 ,
n72306 , n72307 , n72308 , n72309 , n72310 , n72311 , n72312 , n72313 , n72314 , n72315 ,
n72316 , n72317 , n72318 , n72319 , n72320 , n72321 , n72322 , n6184 , n6185 , n72325 ,
n72326 , n72327 , n72328 , n72329 , n72330 , n72331 , n72332 , n72333 , n72334 , n72335 ,
n72336 , n72337 , n72338 , n72339 , n72340 , n72341 , n72342 , n72343 , n72344 , n72345 ,
n72346 , n72347 , n72348 , n72349 , n72350 , n72351 , n72352 , n72353 , n72354 , n72355 ,
n72356 , n72357 , n72358 , n72359 , n72360 , n72361 , n72362 , n72363 , n72364 , n72365 ,
n72366 , n72367 , n72368 , n72369 , n72370 , n72371 , n72372 , n72373 , n72374 , n72375 ,
n72376 , n72377 , n72378 , n72379 , n72380 , n72381 , n72382 , n72383 , n72384 , n72385 ,
n72386 , n72387 , n72388 , n72389 , n72390 , n72391 , n72392 , n72393 , n72394 , n72395 ,
n72396 , n72397 , n72398 , n72399 , n72400 , n72401 , n72402 , n72403 , n72404 , n72405 ,
n72406 , n72407 , n72408 , n72409 , n72410 , n72411 , n72412 , n72413 , n72414 , n72415 ,
n72416 , n72417 , n72418 , n72419 , n72420 , n72421 , n72422 , n72423 , n72424 , n72425 ,
n72426 , n72427 , n72428 , n72429 , n72430 , n72431 , n72432 , n72433 , n72434 , n72435 ,
n72436 , n72437 , n72438 , n72439 , n72440 , n72441 , n72442 , n72443 , n72444 , n72445 ,
n72446 , n72447 , n72448 , n72449 , n72450 , n72451 , n72452 , n72453 , n72454 , n72455 ,
n72456 , n72457 , n72458 , n72459 , n72460 , n72461 , n72462 , n72463 , n72464 , n72465 ,
n72466 , n72467 , n72468 , n72469 , n72470 , n72471 , n72472 , n72473 , n72474 , n72475 ,
n72476 , n72477 , n72478 , n72479 , n72480 , n72481 , n72482 , n72483 , n72484 , n72485 ,
n72486 , n72487 , n72488 , n72489 , n72490 , n72491 , n72492 , n72493 , n72494 , n72495 ,
n72496 , n72497 , n72498 , n72499 , n72500 , n72501 , n72502 , n72503 , n72504 , n72505 ,
n72506 , n72507 , n72508 , n72509 , n72510 , n72511 , n72512 , n72513 , n72514 , n72515 ,
n72516 , n72517 , n72518 , n72519 , n72520 , n72521 , n72522 , n72523 , n72524 , n72525 ,
n72526 , n72527 , n72528 , n72529 , n72530 , n72531 , n72532 , n72533 , n72534 , n72535 ,
n72536 , n72537 , n72538 , n72539 , n72540 , n72541 , n72542 , n72543 , n72544 , n72545 ,
n72546 , n72547 , n72548 , n72549 , n72550 , n72551 , n72552 , n72553 , n72554 , n72555 ,
n72556 , n72557 , n72558 , n72559 , n72560 , n72561 , n72562 , n72563 , n72564 , n72565 ,
n72566 , n72567 , n72568 , n72569 , n72570 , n72571 , n72572 , n72573 , n72574 , n72575 ,
n72576 , n72577 , n72578 , n72579 , n72580 , n72581 , n72582 , n72583 , n72584 , n72585 ,
n72586 , n72587 , n72588 , n72589 , n72590 , n72591 , n72592 , n72593 , n72594 , n72595 ,
n72596 , n72597 , n72598 , n72599 , n72600 , n72601 , n72602 , n72603 , n72604 , n72605 ,
n72606 , n72607 , n72608 , n72609 , n72610 , n72611 , n72612 , n72613 , n72614 , n72615 ,
n72616 , n72617 , n72618 , n72619 , n72620 , n72621 , n72622 , n72623 , n72624 , n72625 ,
n72626 , n72627 , n72628 , n72629 , n72630 , n72631 , n72632 , n72633 , n72634 , n72635 ,
n72636 , n72637 , n72638 , n72639 , n72640 , n72641 , n72642 , n72643 , n72644 , n72645 ,
n72646 , n72647 , n72648 , n72649 , n72650 , n72651 , n72652 , n72653 , n72654 , n72655 ,
n72656 , n72657 , n72658 , n72659 , n72660 , n72661 , n72662 , n72663 , n72664 , n72665 ,
n72666 , n72667 , n72668 , n72669 , n72670 , n72671 , n72672 , n72673 , n72674 , n72675 ,
n72676 , n72677 , n72678 , n72679 , n72680 , n72681 , n72682 , n72683 , n72684 , n72685 ,
n72686 , n72687 , n72688 , n72689 , n72690 , n72691 , n72692 , n72693 , n72694 , n72695 ,
n72696 , n72697 , n72698 , n72699 , n72700 , n72701 , n72702 , n72703 , n72704 , n72705 ,
n72706 , n72707 , n72708 , n72709 , n72710 , n72711 , n72712 , n72713 , n72714 , n72715 ,
n72716 , n72717 , n72718 , n72719 , n72720 , n72721 , n72722 , n72723 , n72724 , n72725 ,
n72726 , n72727 , n72728 , n72729 , n72730 , n72731 , n72732 , n72733 , n72734 , n72735 ,
n72736 , n72737 , n72738 , n72739 , n72740 , n72741 , n72742 , n72743 , n72744 , n72745 ,
n72746 , n72747 , n72748 , n72749 , n72750 , n72751 , n72752 , n72753 , n72754 , n72755 ,
n72756 , n72757 , n72758 , n72759 , n72760 , n72761 , n72762 , n72763 , n72764 , n72765 ,
n72766 , n72767 , n72768 , n72769 , n72770 , n72771 , n72772 , n72773 , n72774 , n72775 ,
n72776 , n72777 , n72778 , n72779 , n72780 , n72781 , n72782 , n72783 , n72784 , n72785 ,
n72786 , n72787 , n72788 , n72789 , n72790 , n72791 , n72792 , n72793 , n72794 , n72795 ,
n72796 , n72797 , n72798 , n72799 , n72800 , n72801 , n72802 , n72803 , n72804 , n72805 ,
n72806 , n72807 , n72808 , n72809 , n72810 , n72811 , n72812 , n72813 , n72814 , n72815 ,
n72816 , n72817 , n72818 , n72819 , n72820 , n72821 , n72822 , n72823 , n72824 , n72825 ,
n72826 , n72827 , n72828 , n72829 , n72830 , n72831 , n72832 , n72833 , n72834 , n6696 ,
n72836 , n72837 , n72838 , n72839 , n72840 , n72841 , n72842 , n72843 , n72844 , n72845 ,
n72846 , n72847 , n72848 , n72849 , n72850 , n72851 , n72852 , n72853 , n72854 , n72855 ,
n72856 , n72857 , n72858 , n72859 , n72860 , n72861 , n72862 , n72863 , n72864 , n72865 ,
n72866 , n72867 , n72868 , n72869 , n72870 , n72871 , n72872 , n72873 , n72874 , n72875 ,
n72876 , n72877 , n72878 , n72879 , n72880 , n72881 , n72882 , n72883 , n72884 , n72885 ,
n72886 , n72887 , n72888 , n72889 , n72890 , n72891 , n72892 , n72893 , n72894 , n72895 ,
n72896 , n72897 , n72898 , n72899 , n72900 , n72901 , n72902 , n72903 , n72904 , n72905 ,
n72906 , n72907 , n72908 , n72909 , n72910 , n72911 , n72912 , n72913 , n72914 , n6776 ,
n6777 , n72917 , n72918 , n72919 , n72920 , n72921 , n72922 , n72923 , n72924 , n72925 ,
n72926 , n72927 , n72928 , n72929 , n72930 , n72931 , n72932 , n72933 , n72934 , n72935 ,
n72936 , n72937 , n72938 , n72939 , n72940 , n72941 , n72942 , n72943 , n72944 , n72945 ,
n72946 , n72947 , n72948 , n72949 , n72950 , n72951 , n72952 , n72953 , n72954 , n72955 ,
n72956 , n72957 , n72958 , n72959 , n72960 , n72961 , n72962 , n72963 , n72964 , n72965 ,
n72966 , n72967 , n72968 , n72969 , n72970 , n72971 , n72972 , n72973 , n72974 , n72975 ,
n72976 , n72977 , n72978 , n72979 , n72980 , n72981 , n72982 , n72983 , n72984 , n72985 ,
n72986 , n72987 , n72988 , n72989 , n72990 , n6852 , n72992 , n72993 , n72994 , n6856 ,
n72996 , n72997 , n72998 , n72999 , n73000 , n73001 , n73002 , n73003 , n73004 , n73005 ,
n73006 , n73007 , n73008 , n73009 , n73010 , n73011 , n73012 , n73013 , n73014 , n73015 ,
n73016 , n73017 , n73018 , n73019 , n73020 , n73021 , n73022 , n73023 , n73024 , n73025 ,
n73026 , n73027 , n73028 , n73029 , n73030 , n73031 , n73032 , n73033 , n73034 , n73035 ,
n73036 , n73037 , n73038 , n73039 , n73040 , n73041 , n73042 , n73043 , n73044 , n73045 ,
n73046 , n73047 , n73048 , n73049 , n73050 , n73051 , n73052 , n73053 , n73054 , n73055 ,
n73056 , n73057 , n73058 , n73059 , n73060 , n73061 , n73062 , n73063 , n73064 , n6926 ,
n6927 , n73067 , n73068 , n73069 , n73070 , n73071 , n73072 , n73073 , n73074 , n73075 ,
n73076 , n73077 , n73078 , n73079 , n73080 , n73081 , n73082 , n73083 , n73084 , n73085 ,
n73086 , n73087 , n73088 , n73089 , n73090 , n73091 , n73092 , n73093 , n73094 , n73095 ,
n73096 , n73097 , n73098 , n73099 , n73100 , n73101 , n73102 , n73103 , n73104 , n73105 ,
n73106 , n73107 , n73108 , n73109 , n73110 , n73111 , n73112 , n73113 , n73114 , n73115 ,
n73116 , n73117 , n73118 , n73119 , n73120 , n73121 , n73122 , n73123 , n73124 , n73125 ,
n6987 , n73127 , n73128 , n73129 , n6991 , n73131 , n73132 , n73133 , n73134 , n73135 ,
n73136 , n73137 , n73138 , n73139 , n73140 , n73141 , n73142 , n73143 , n73144 , n73145 ,
n73146 , n73147 , n73148 , n73149 , n73150 , n73151 , n73152 , n73153 , n73154 , n73155 ,
n73156 , n73157 , n73158 , n73159 , n73160 , n73161 , n73162 , n73163 , n73164 , n73165 ,
n73166 , n73167 , n73168 , n73169 , n73170 , n73171 , n73172 , n73173 , n73174 , n73175 ,
n73176 , n73177 , n73178 , n73179 , n73180 , n73181 , n73182 , n73183 , n73184 , n73185 ,
n73186 , n73187 , n73188 , n73189 , n73190 , n73191 , n73192 , n73193 , n73194 , n73195 ,
n73196 , n73197 , n73198 , n73199 , n73200 , n73201 , n73202 , n73203 , n73204 , n73205 ,
n73206 , n73207 , n73208 , n73209 , n73210 , n73211 , n73212 , n73213 , n73214 , n73215 ,
n73216 , n73217 , n73218 , n73219 , n73220 , n73221 , n73222 , n73223 , n73224 , n73225 ,
n73226 , n73227 , n73228 , n73229 , n73230 , n73231 , n73232 , n73233 , n73234 , n73235 ,
n73236 , n73237 , n73238 , n73239 , n73240 , n73241 , n73242 , n73243 , n73244 , n73245 ,
n73246 , n73247 , n73248 , n73249 , n73250 , n73251 , n73252 , n73253 , n73254 , n73255 ,
n73256 , n73257 , n73258 , n73259 , n73260 , n73261 , n73262 , n73263 , n73264 , n73265 ,
n73266 , n73267 , n73268 , n73269 , n73270 , n73271 , n73272 , n73273 , n73274 , n73275 ,
n73276 , n73277 , n7139 , n73279 , n73280 , n73281 , n73282 , n73283 , n73284 , n73285 ,
n73286 , n73287 , n73288 , n73289 , n73290 , n73291 , n73292 , n73293 , n73294 , n73295 ,
n73296 , n73297 , n73298 , n73299 , n73300 , n73301 , n73302 , n73303 , n73304 , n73305 ,
n73306 , n73307 , n73308 , n73309 , n73310 , n73311 , n73312 , n73313 , n73314 , n73315 ,
n73316 , n73317 , n73318 , n73319 , n73320 , n73321 , n73322 , n73323 , n73324 , n73325 ,
n73326 , n73327 , n73328 , n73329 , n73330 , n73331 , n73332 , n73333 , n73334 , n73335 ,
n73336 , n73337 , n73338 , n73339 , n73340 , n73341 , n73342 , n73343 , n73344 , n73345 ,
n7207 , n7208 , n73348 , n73349 , n73350 , n73351 , n73352 , n73353 , n73354 , n73355 ,
n73356 , n73357 , n73358 , n73359 , n73360 , n73361 , n73362 , n73363 , n73364 , n73365 ,
n73366 , n73367 , n73368 , n73369 , n73370 , n73371 , n73372 , n73373 , n73374 , n73375 ,
n73376 , n73377 , n73378 , n73379 , n73380 , n73381 , n73382 , n73383 , n73384 , n73385 ,
n73386 , n73387 , n73388 , n73389 , n73390 , n73391 , n73392 , n73393 , n73394 , n73395 ,
n73396 , n73397 , n73398 , n73399 , n73400 , n73401 , n73402 , n73403 , n73404 , n73405 ,
n73406 , n73407 , n73408 , n73409 , n73410 , n73411 , n73412 , n73413 , n73414 , n73415 ,
n73416 , n73417 , n73418 , n73419 , n73420 , n73421 , n73422 , n73423 , n73424 , n73425 ,
n73426 , n73427 , n73428 , n73429 , n73430 , n73431 , n73432 , n73433 , n73434 , n73435 ,
n73436 , n73437 , n73438 , n73439 , n73440 , n73441 , n73442 , n73443 , n7305 , n73445 ,
n73446 , n73447 , n73448 , n73449 , n73450 , n73451 , n73452 , n73453 , n73454 , n73455 ,
n73456 , n73457 , n73458 , n73459 , n73460 , n73461 , n73462 , n73463 , n73464 , n73465 ,
n7327 , n7328 , n73468 , n73469 , n73470 , n73471 , n73472 , n73473 , n73474 , n73475 ,
n73476 , n73477 , n73478 , n73479 , n73480 , n73481 , n73482 , n73483 , n73484 , n73485 ,
n73486 , n73487 , n7349 , n7350 , n73490 , n73491 , n73492 , n73493 , n73494 , n73495 ,
n73496 , n73497 , n73498 , n73499 , n73500 , n73501 , n73502 , n73503 , n73504 , n73505 ,
n73506 , n73507 , n73508 , n73509 , n73510 , n73511 , n73512 , n73513 , n73514 , n73515 ,
n73516 , n73517 , n73518 , n73519 , n73520 , n73521 , n73522 , n73523 , n73524 , n73525 ,
n73526 , n7388 , n7389 , n73529 , n7391 , n7392 , n73532 , n73533 , n73534 , n73535 ,
n73536 , n73537 , n73538 , n73539 , n73540 , n73541 , n73542 , n73543 , n73544 , n73545 ,
n73546 , n73547 , n73548 , n73549 , n73550 , n73551 , n73552 , n73553 , n73554 , n73555 ,
n73556 , n73557 , n73558 , n73559 , n73560 , n73561 , n73562 , n73563 , n73564 , n73565 ,
n73566 , n73567 , n73568 , n73569 , n73570 , n73571 , n73572 , n73573 , n73574 , n73575 ,
n73576 , n73577 , n73578 , n73579 , n73580 , n73581 , n73582 , n73583 , n73584 , n73585 ,
n73586 , n73587 , n73588 , n73589 , n73590 , n73591 , n73592 , n73593 , n73594 , n73595 ,
n73596 , n73597 , n73598 , n73599 , n73600 , n73601 , n73602 , n73603 , n73604 , n73605 ,
n73606 , n73607 , n73608 , n73609 , n73610 , n73611 , n73612 , n73613 , n73614 , n73615 ,
n73616 , n73617 , n73618 , n73619 , n73620 , n73621 , n73622 , n73623 , n73624 , n73625 ,
n73626 , n73627 , n73628 , n73629 , n73630 , n73631 , n73632 , n73633 , n73634 , n73635 ,
n73636 , n73637 , n73638 , n73639 , n73640 , n73641 , n73642 , n73643 , n73644 , n73645 ,
n73646 , n73647 , n73648 , n73649 , n73650 , n73651 , n73652 , n73653 , n73654 , n73655 ,
n73656 , n73657 , n73658 , n73659 , n73660 , n73661 , n73662 , n73663 , n73664 , n73665 ,
n73666 , n73667 , n73668 , n73669 , n73670 , n73671 , n73672 , n73673 , n73674 , n7536 ,
n7537 , n73677 , n7539 , n7540 , n73680 , n73681 , n73682 , n73683 , n73684 , n73685 ,
n73686 , n73687 , n73688 , n73689 , n73690 , n73691 , n73692 , n73693 , n73694 , n73695 ,
n73696 , n73697 , n73698 , n73699 , n73700 , n73701 , n73702 , n73703 , n73704 , n73705 ,
n73706 , n73707 , n73708 , n73709 , n73710 , n73711 , n73712 , n73713 , n73714 , n73715 ,
n73716 , n73717 , n73718 , n73719 , n73720 , n73721 , n73722 , n73723 , n73724 , n73725 ,
n73726 , n73727 , n73728 , n73729 , n73730 , n73731 , n73732 , n73733 , n73734 , n73735 ,
n73736 , n73737 , n73738 , n73739 , n73740 , n73741 , n73742 , n73743 , n73744 , n73745 ,
n73746 , n73747 , n73748 , n73749 , n73750 , n73751 , n73752 , n73753 , n73754 , n73755 ,
n73756 , n73757 , n7619 , n73759 , n73760 , n7622 , n7623 , n73763 , n73764 , n73765 ,
n73766 , n73767 , n73768 , n73769 , n73770 , n73771 , n73772 , n73773 , n73774 , n73775 ,
n73776 , n73777 , n73778 , n7640 , n7641 , n73781 , n73782 , n73783 , n73784 , n73785 ,
n73786 , n73787 , n73788 , n73789 , n73790 , n73791 , n73792 , n73793 , n73794 , n73795 ,
n73796 , n73797 , n73798 , n73799 , n73800 , n73801 , n73802 , n73803 , n73804 , n73805 ,
n73806 , n73807 , n73808 , n73809 , n73810 , n73811 , n73812 , n73813 , n73814 , n7676 ,
n7677 , n73817 , n73818 , n73819 , n73820 , n73821 , n73822 , n73823 , n73824 , n73825 ,
n73826 , n73827 , n73828 , n73829 , n73830 , n7692 , n7693 , n73833 , n73834 , n7696 ,
n73836 , n73837 , n73838 , n73839 , n73840 , n73841 , n73842 , n73843 , n73844 , n73845 ,
n73846 , n73847 , n73848 , n73849 , n73850 , n73851 , n73852 , n7714 , n73854 , n73855 ,
n73856 , n73857 , n73858 , n73859 , n73860 , n73861 , n73862 , n73863 , n73864 , n73865 ,
n73866 , n73867 , n73868 , n73869 , n73870 , n73871 , n73872 , n73873 , n73874 , n73875 ,
n73876 , n73877 , n73878 , n73879 , n73880 , n73881 , n73882 , n73883 , n73884 , n73885 ,
n73886 , n73887 , n7749 , n7750 , n73890 , n73891 , n73892 , n73893 , n73894 , n73895 ,
n73896 , n73897 , n73898 , n73899 , n73900 , n73901 , n73902 , n73903 , n73904 , n73905 ,
n73906 , n73907 , n73908 , n73909 , n73910 , n73911 , n73912 , n73913 , n73914 , n73915 ,
n73916 , n73917 , n73918 , n73919 , n73920 , n73921 , n73922 , n73923 , n73924 , n73925 ,
n73926 , n73927 , n73928 , n73929 , n73930 , n73931 , n7793 , n73933 , n73934 , n73935 ,
n73936 , n73937 , n73938 , n73939 , n73940 , n73941 , n73942 , n73943 , n73944 , n73945 ,
n73946 , n73947 , n73948 , n73949 , n73950 , n73951 , n73952 , n73953 , n73954 , n73955 ,
n73956 , n73957 , n73958 , n73959 , n73960 , n73961 , n73962 , n73963 , n73964 , n73965 ,
n73966 , n73967 , n7829 , n7830 , n73970 , n7832 , n7833 , n73973 , n73974 , n73975 ,
n73976 , n73977 , n73978 , n73979 , n73980 , n73981 , n73982 , n73983 , n73984 , n73985 ,
n73986 , n73987 , n73988 , n73989 , n73990 , n73991 , n73992 , n73993 , n73994 , n73995 ,
n73996 , n73997 , n73998 , n73999 , n74000 , n74001 , n74002 , n74003 , n74004 , n74005 ,
n74006 , n74007 , n74008 , n74009 , n74010 , n74011 , n74012 , n74013 , n74014 , n74015 ,
n74016 , n74017 , n74018 , n74019 , n74020 , n74021 , n74022 , n74023 , n74024 , n74025 ,
n74026 , n74027 , n74028 , n74029 , n74030 , n74031 , n74032 , n74033 , n74034 , n74035 ,
n74036 , n74037 , n74038 , n74039 , n74040 , n74041 , n74042 , n74043 , n74044 , n74045 ,
n74046 , n74047 , n74048 , n74049 , n74050 , n74051 , n74052 , n74053 , n74054 , n74055 ,
n74056 , n74057 , n74058 , n7920 , n7921 , n74061 , n74062 , n74063 , n74064 , n74065 ,
n74066 , n74067 , n74068 , n74069 , n74070 , n74071 , n74072 , n74073 , n74074 , n7936 ,
n7937 , n74077 , n74078 , n74079 , n74080 , n74081 , n74082 , n74083 , n74084 , n74085 ,
n74086 , n74087 , n74088 , n74089 , n74090 , n74091 , n7953 , n74093 , n74094 , n74095 ,
n74096 , n74097 , n74098 , n74099 , n74100 , n74101 , n74102 , n74103 , n74104 , n74105 ,
n74106 , n74107 , n74108 , n74109 , n7971 , n7972 , n74112 , n74113 , n74114 , n74115 ,
n74116 , n74117 , n74118 , n74119 , n74120 , n74121 , n74122 , n74123 , n74124 , n74125 ,
n74126 , n7988 , n7989 , n74129 , n74130 , n7992 , n74132 , n74133 , n74134 , n74135 ,
n74136 , n74137 , n74138 , n74139 , n74140 , n74141 , n74142 , n74143 , n74144 , n74145 ,
n74146 , n74147 , n74148 , n8010 , n8011 , n74151 , n74152 , n74153 , n74154 , n74155 ,
n74156 , n74157 , n74158 , n74159 , n74160 , n74161 , n74162 , n74163 , n74164 , n8026 ,
n8027 , n74167 , n74168 , n74169 , n74170 , n74171 , n74172 , n74173 , n74174 , n74175 ,
n74176 , n74177 , n74178 , n74179 , n74180 , n74181 , n74182 , n74183 , n8045 , n8046 ,
n74186 , n74187 , n74188 , n74189 , n74190 , n74191 , n74192 , n74193 , n74194 , n74195 ,
n74196 , n74197 , n74198 , n74199 , n74200 , n74201 , n74202 , n74203 , n74204 , n74205 ,
n8067 , n8068 , n74208 , n74209 , n74210 , n74211 , n74212 , n74213 , n74214 , n74215 ,
n74216 , n74217 , n74218 , n74219 , n74220 , n74221 , n74222 , n8084 , n74224 , n74225 ,
n74226 , n74227 , n74228 , n74229 , n74230 , n74231 , n74232 , n74233 , n74234 , n74235 ,
n74236 , n74237 , n74238 , n74239 , n74240 , n74241 , n74242 , n74243 , n74244 , n74245 ,
n74246 , n74247 , n74248 , n74249 , n74250 , n74251 , n74252 , n74253 , n74254 , n74255 ,
n74256 , n74257 , n74258 , n74259 , n74260 , n74261 , n74262 , n74263 , n74264 , n8126 ,
n8127 , n74267 , n74268 , n74269 , n74270 , n74271 , n74272 , n74273 , n74274 , n74275 ,
n74276 , n74277 , n74278 , n74279 , n74280 , n8142 , n8143 , n74283 , n74284 , n74285 ,
n74286 , n74287 , n74288 , n74289 , n74290 , n74291 , n74292 , n74293 , n74294 , n74295 ,
n74296 , n74297 , n74298 , n74299 , n74300 , n74301 , n8163 , n8164 , n74304 , n74305 ,
n74306 , n74307 , n74308 , n74309 , n74310 , n74311 , n74312 , n74313 , n74314 , n74315 ,
n74316 , n74317 , n74318 , n74319 , n74320 , n74321 , n74322 , n74323 , n74324 , n74325 ,
n74326 , n74327 , n74328 , n74329 , n74330 , n74331 , n74332 , n74333 , n74334 , n74335 ,
n74336 , n74337 , n8199 , n74339 , n8201 , n8202 , n74342 , n74343 , n74344 , n74345 ,
n74346 , n74347 , n74348 , n74349 , n74350 , n74351 , n74352 , n74353 , n74354 , n74355 ,
n8217 , n74357 , n74358 , n74359 , n8221 , n74361 , n74362 , n74363 , n74364 , n74365 ,
n74366 , n74367 , n74368 , n74369 , n74370 , n74371 , n74372 , n74373 , n74374 , n74375 ,
n8237 , n74377 , n74378 , n74379 , n74380 , n74381 , n74382 , n74383 , n74384 , n74385 ,
n74386 , n74387 , n74388 , n74389 , n74390 , n74391 , n74392 , n74393 , n74394 , n74395 ,
n74396 , n74397 , n74398 , n74399 , n74400 , n74401 , n74402 , n74403 , n74404 , n74405 ,
n74406 , n74407 , n74408 , n74409 , n74410 , n74411 , n74412 , n8274 , n8275 , n74415 ,
n8277 , n74417 , n74418 , n74419 , n74420 , n74421 , n74422 , n74423 , n74424 , n74425 ,
n74426 , n74427 , n74428 , n74429 , n74430 , n74431 , n74432 , n74433 , n8295 , n8296 ,
n74436 , n74437 , n74438 , n74439 , n74440 , n74441 , n74442 , n74443 , n74444 , n74445 ,
n74446 , n74447 , n74448 , n74449 , n8311 , n74451 , n74452 , n74453 , n74454 , n74455 ,
n74456 , n74457 , n74458 , n74459 , n74460 , n74461 , n74462 , n74463 , n74464 , n74465 ,
n74466 , n74467 , n74468 , n74469 , n74470 , n74471 , n74472 , n74473 , n74474 , n74475 ,
n74476 , n74477 , n74478 , n74479 , n74480 , n74481 , n74482 , n74483 , n74484 , n74485 ,
n74486 , n74487 , n74488 , n74489 , n74490 , n74491 , n8353 , n74493 , n74494 , n74495 ,
n74496 , n74497 , n74498 , n74499 , n74500 , n74501 , n74502 , n74503 , n74504 , n74505 ,
n74506 , n74507 , n74508 , n74509 , n74510 , n74511 , n74512 , n74513 , n74514 , n74515 ,
n74516 , n74517 , n74518 , n74519 , n74520 , n74521 , n74522 , n74523 , n74524 , n74525 ,
n74526 , n74527 , n74528 , n74529 , n74530 , n74531 , n74532 , n74533 , n74534 , n8396 ,
n8397 , n74537 , n74538 , n74539 , n74540 , n74541 , n74542 , n74543 , n74544 , n74545 ,
n74546 , n74547 , n74548 , n74549 , n74550 , n74551 , n74552 , n74553 , n74554 , n74555 ,
n8417 , n74557 , n74558 , n74559 , n8421 , n74561 , n74562 , n74563 , n74564 , n74565 ,
n8427 , n74567 , n74568 , n74569 , n74570 , n74571 , n74572 , n74573 , n74574 , n8436 ,
n74576 , n8438 , n8439 , n74579 , n74580 , n74581 , n74582 , n74583 , n74584 , n74585 ,
n74586 , n74587 , n74588 , n74589 , n74590 , n74591 , n74592 , n74593 , n8455 , n74595 ,
n74596 , n74597 , n8459 , n74599 , n74600 , n74601 , n74602 , n74603 , n74604 , n74605 ,
n74606 , n74607 , n74608 , n74609 , n74610 , n74611 , n74612 , n74613 , n74614 , n74615 ,
n74616 , n74617 , n74618 , n74619 , n74620 , n74621 , n74622 , n74623 , n74624 , n74625 ,
n74626 , n74627 , n74628 , n74629 , n74630 , n74631 , n74632 , n74633 , n74634 , n74635 ,
n74636 , n74637 , n8499 , n74639 , n74640 , n8502 , n74642 , n74643 , n74644 , n74645 ,
n74646 , n74647 , n74648 , n74649 , n74650 , n74651 , n74652 , n74653 , n74654 , n74655 ,
n74656 , n74657 , n8519 , n8520 , n74660 , n74661 , n74662 , n74663 , n74664 , n74665 ,
n74666 , n74667 , n74668 , n74669 , n74670 , n74671 , n74672 , n74673 , n74674 , n74675 ,
n74676 , n74677 , n8539 , n8540 , n74680 , n74681 , n74682 , n74683 , n74684 , n74685 ,
n74686 , n74687 , n74688 , n74689 , n74690 , n74691 , n74692 , n74693 , n74694 , n74695 ,
n74696 , n74697 , n74698 , n74699 , n74700 , n74701 , n8563 , n74703 , n74704 , n74705 ,
n74706 , n74707 , n74708 , n74709 , n74710 , n74711 , n74712 , n74713 , n74714 , n74715 ,
n74716 , n74717 , n74718 , n8580 , n74720 , n74721 , n74722 , n74723 , n74724 , n74725 ,
n74726 , n74727 , n74728 , n74729 , n74730 , n74731 , n74732 , n74733 , n74734 , n74735 ,
n74736 , n74737 , n74738 , n74739 , n74740 , n8602 , n8603 , n74743 , n74744 , n74745 ,
n74746 , n74747 , n74748 , n74749 , n74750 , n74751 , n74752 , n74753 , n74754 , n74755 ,
n74756 , n74757 , n8619 , n74759 , n74760 , n74761 , n74762 , n74763 , n74764 , n74765 ,
n74766 , n74767 , n74768 , n74769 , n74770 , n74771 , n74772 , n74773 , n74774 , n74775 ,
n74776 , n74777 , n8639 , n74779 , n74780 , n74781 , n8643 , n74783 , n74784 , n74785 ,
n74786 , n74787 , n74788 , n74789 , n74790 , n74791 , n74792 , n74793 , n74794 , n74795 ,
n74796 , n74797 , n74798 , n74799 , n8661 , n74801 , n74802 , n74803 , n8665 , n74805 ,
n74806 , n74807 , n74808 , n74809 , n74810 , n74811 , n74812 , n74813 , n74814 , n74815 ,
n74816 , n74817 , n74818 , n74819 , n8681 , n74821 , n74822 , n74823 , n74824 , n74825 ,
n74826 , n74827 , n74828 , n74829 , n74830 , n74831 , n74832 , n74833 , n74834 , n74835 ,
n74836 , n74837 , n74838 , n74839 , n74840 , n74841 , n74842 , n74843 , n74844 , n74845 ,
n74846 , n74847 , n74848 , n74849 , n74850 , n74851 , n74852 , n74853 , n74854 , n74855 ,
n74856 , n74857 , n74858 , n74859 , n8721 , n74861 , n74862 , n8724 , n74864 , n74865 ,
n74866 , n74867 , n74868 , n74869 , n74870 , n8732 , n8733 , n74873 , n8735 , n74875 ,
n74876 , n74877 , n74878 , n8740 , n8741 , n74881 , n74882 , n74883 , n74884 , n74885 ,
n74886 , n74887 , n74888 , n74889 , n8751 , n74891 , n74892 , n74893 , n74894 , n8756 ,
n74896 , n74897 , n74898 , n74899 , n74900 , n74901 , n74902 , n74903 , n74904 , n74905 ,
n8767 , n74907 , n74908 , n74909 , n74910 , n74911 , n74912 , n74913 , n74914 , n74915 ,
n74916 , n74917 , n74918 , n74919 , n74920 , n74921 , n74922 , n74923 , n8785 , n74925 ,
n74926 , n74927 , n74928 , n74929 , n8791 , n74931 , n8793 , n8794 , n74934 , n74935 ,
n74936 , n8798 , n74938 , n74939 , n74940 , n8802 , n74942 , n74943 , n74944 , n8806 ,
n8807 , n74947 , n8809 , n74949 , n74950 , n74951 , n74952 , n8814 , n8815 , n74955 ,
n74956 , n74957 , n74958 , n74959 , n74960 , n74961 , n74962 , n74963 , n8825 , n74965 ,
n74966 , n74967 , n74968 , n74969 , n74970 , n74971 , n74972 , n74973 , n8835 , n8836 ,
n74976 , n74977 , n74978 , n8840 , n8841 , n74981 , n74982 , n74983 , n74984 , n74985 ,
n74986 , n74987 , n74988 , n74989 , n74990 , n74991 , n74992 , n74993 , n74994 , n74995 ,
n74996 , n74997 , n8859 , n8860 , n75000 , n75001 , n75002 , n75003 , n8865 , n75005 ,
n8867 , n8868 , n75008 , n75009 , n75010 , n8872 , n75012 , n75013 , n75014 , n8876 ,
n75016 , n75017 , n75018 , n8880 , n8881 , n75021 , n8883 , n75023 , n75024 , n75025 ,
n75026 , n8888 , n8889 , n75029 , n75030 , n75031 , n75032 , n75033 , n75034 , n75035 ,
n75036 , n75037 , n8899 , n75039 , n75040 , n75041 , n75042 , n8904 , n75044 , n75045 ,
n75046 , n75047 , n75048 , n75049 , n75050 , n75051 , n75052 , n75053 , n8915 , n75055 ,
n75056 , n75057 , n75058 , n75059 , n75060 , n75061 , n75062 , n75063 , n75064 , n75065 ,
n75066 , n75067 , n75068 , n75069 , n75070 , n75071 , n75072 , n75073 , n75074 , n75075 ,
n75076 , n75077 , n8939 , n8940 , n75080 , n75081 , n75082 , n75083 , n8945 , n75085 ,
n75086 , n75087 , n75088 , n75089 , n75090 , n75091 , n75092 , n75093 , n8955 , n8956 ,
n75096 , n75097 , n75098 , n75099 , n8961 , n75101 , n8963 , n8964 , n75104 , n75105 ,
n75106 , n75107 , n75108 , n75109 , n75110 , n8972 , n75112 , n75113 , n75114 , n75115 ,
n8977 , n75117 , n75118 , n75119 , n75120 , n75121 , n75122 , n8984 , n75124 , n75125 ,
n75126 , n8988 , n75128 , n75129 , n75130 , n75131 , n75132 , n75133 , n75134 , n75135 ,
n75136 , n75137 , n75138 , n75139 , n75140 , n75141 , n75142 , n75143 , n75144 , n75145 ,
n75146 , n75147 , n75148 , n75149 , n75150 , n75151 , n75152 , n9014 , n9015 , n75155 ,
n75156 , n75157 , n75158 , n9020 , n75160 , n75161 , n75162 , n9024 , n75164 , n75165 ,
n75166 , n75167 , n9029 , n9030 , n75170 , n75171 , n75172 , n75173 , n75174 , n75175 ,
n75176 , n75177 , n75178 , n75179 , n75180 , n75181 , n75182 , n75183 , n75184 , n75185 ,
n75186 , n75187 , n75188 , n75189 , n75190 , n9052 , n75192 , n75193 , n75194 , n75195 ,
n75196 , n75197 , n75198 , n75199 , n75200 , n9062 , n75202 , n75203 , n75204 , n75205 ,
n75206 , n75207 , n75208 , n75209 , n75210 , n75211 , n75212 , n75213 , n75214 , n75215 ,
n75216 , n75217 , n75218 , n75219 , n75220 , n9082 , n9083 , n75223 , n75224 , n75225 ,
n75226 , n75227 , n75228 , n75229 , n9091 , n75231 , n75232 , n75233 , n75234 , n75235 ,
n75236 , n75237 , n75238 , n75239 , n75240 , n75241 , n75242 , n75243 , n75244 , n75245 ,
n75246 , n75247 , n75248 , n75249 , n75250 , n75251 , n75252 , n75253 , n75254 , n75255 ,
n75256 , n75257 , n75258 , n75259 , n75260 , n75261 , n75262 , n75263 , n9125 , n9126 ,
n75266 , n75267 , n75268 , n75269 , n75270 , n75271 , n75272 , n75273 , n75274 , n75275 ,
n75276 , n75277 , n75278 , n75279 , n75280 , n75281 , n75282 , n75283 , n75284 , n75285 ,
n75286 , n75287 , n75288 , n75289 , n75290 , n75291 , n75292 , n75293 , n75294 , n75295 ,
n75296 , n75297 , n75298 , n75299 , n75300 , n75301 , n75302 , n75303 , n75304 , n75305 ,
n75306 , n75307 , n75308 , n75309 , n75310 , n75311 , n75312 , n75313 , n75314 , n75315 ,
n75316 , n75317 , n75318 , n75319 , n75320 , n75321 , n75322 , n75323 , n75324 , n75325 ,
n75326 , n75327 , n75328 , n75329 , n75330 , n75331 , n75332 , n75333 , n75334 , n75335 ,
n75336 , n75337 , n75338 , n75339 , n75340 , n75341 , n75342 , n75343 , n75344 , n75345 ,
n75346 , n75347 , n75348 , n75349 , n75350 , n75351 , n75352 , n75353 , n75354 , n75355 ,
n75356 , n75357 , n75358 , n75359 , n75360 , n75361 , n75362 , n75363 , n75364 , n75365 ,
n75366 , n75367 , n75368 , n75369 , n75370 , n75371 , n75372 , n75373 , n75374 , n75375 ,
n75376 , n75377 , n75378 , n75379 , n75380 , n75381 , n75382 , n75383 , n75384 , n75385 ,
n75386 , n75387 , n75388 , n75389 , n75390 , n75391 , n75392 , n75393 , n75394 , n9256 ,
n75396 , n9258 , n9259 , n75399 , n75400 , n75401 , n75402 , n75403 , n75404 , n75405 ,
n75406 , n75407 , n75408 , n75409 , n75410 , n75411 , n75412 , n75413 , n75414 , n75415 ,
n75416 , n75417 , n75418 , n75419 , n75420 , n75421 , n9283 , n9284 , n75424 , n75425 ,
n75426 , n75427 , n75428 , n75429 , n75430 , n75431 , n75432 , n75433 , n75434 , n75435 ,
n75436 , n75437 , n75438 , n75439 , n75440 , n75441 , n75442 , n75443 , n75444 , n75445 ,
n75446 , n75447 , n75448 , n75449 , n75450 , n75451 , n75452 , n75453 , n75454 , n75455 ,
n9317 , n9318 , n75458 , n75459 , n75460 , n75461 , n75462 , n75463 , n75464 , n75465 ,
n75466 , n75467 , n75468 , n75469 , n75470 , n75471 , n75472 , n75473 , n75474 , n75475 ,
n75476 , n75477 , n75478 , n75479 , n75480 , n75481 , n75482 , n75483 , n75484 , n75485 ,
n75486 , n75487 , n75488 , n75489 , n75490 , n75491 , n75492 , n75493 , n75494 , n75495 ,
n75496 , n75497 , n75498 , n75499 , n75500 , n75501 , n75502 , n75503 , n75504 , n75505 ,
n75506 , n75507 , n75508 , n75509 , n75510 , n75511 , n75512 , n75513 , n75514 , n75515 ,
n75516 , n75517 , n75518 , n75519 , n75520 , n75521 , n75522 , n75523 , n75524 , n75525 ,
n75526 , n75527 , n75528 , n75529 , n75530 , n75531 , n75532 , n75533 , n75534 , n75535 ,
n75536 , n75537 , n75538 , n75539 , n75540 , n75541 , n75542 , n75543 , n75544 , n75545 ,
n75546 , n75547 , n75548 , n75549 , n75550 , n75551 , n75552 , n75553 , n9415 , n75555 ,
n75556 , n75557 , n75558 , n75559 , n75560 , n75561 , n75562 , n75563 , n75564 , n75565 ,
n75566 , n75567 , n75568 , n75569 , n75570 , n75571 , n75572 , n75573 , n75574 , n75575 ,
n75576 , n75577 , n75578 , n75579 , n75580 , n75581 , n75582 , n75583 , n75584 , n75585 ,
n75586 , n75587 , n75588 , n75589 , n75590 , n75591 , n75592 , n75593 , n75594 , n75595 ,
n75596 , n75597 , n75598 , n75599 , n75600 , n75601 , n75602 , n75603 , n75604 , n75605 ,
n75606 , n75607 , n75608 , n75609 , n75610 , n75611 , n75612 , n75613 , n75614 , n75615 ,
n75616 , n75617 , n75618 , n75619 , n75620 , n75621 , n75622 , n75623 , n75624 , n75625 ,
n9487 , n9488 , n75628 , n75629 , n75630 , n75631 , n75632 , n75633 , n75634 , n75635 ,
n75636 , n75637 , n75638 , n75639 , n75640 , n75641 , n75642 , n75643 , n75644 , n75645 ,
n75646 , n75647 , n75648 , n75649 , n75650 , n75651 , n75652 , n75653 , n75654 , n75655 ,
n75656 , n75657 , n75658 , n75659 , n75660 , n75661 , n75662 , n75663 , n75664 , n75665 ,
n75666 , n75667 , n75668 , n75669 , n75670 , n75671 , n75672 , n75673 , n75674 , n75675 ,
n75676 , n75677 , n75678 , n75679 , n75680 , n75681 , n75682 , n75683 , n75684 , n75685 ,
n75686 , n75687 , n75688 , n75689 , n75690 , n75691 , n75692 , n75693 , n75694 , n75695 ,
n75696 , n75697 , n75698 , n75699 , n75700 , n75701 , n75702 , n75703 , n75704 , n75705 ,
n75706 , n75707 , n75708 , n75709 , n75710 , n75711 , n75712 , n75713 , n75714 , n75715 ,
n75716 , n75717 , n75718 , n75719 , n75720 , n75721 , n75722 , n75723 , n75724 , n75725 ,
n75726 , n75727 , n75728 , n75729 , n75730 , n75731 , n75732 , n75733 , n75734 , n75735 ,
n75736 , n75737 , n75738 , n75739 , n75740 , n75741 , n75742 , n75743 , n75744 , n75745 ,
n75746 , n75747 , n75748 , n75749 , n75750 , n75751 , n75752 , n75753 , n75754 , n75755 ,
n75756 , n75757 , n9619 , n9620 , n75760 , n9622 , n9623 , n75763 , n75764 , n75765 ,
n75766 , n75767 , n75768 , n75769 , n75770 , n75771 , n75772 , n75773 , n75774 , n75775 ,
n75776 , n75777 , n75778 , n75779 , n75780 , n75781 , n75782 , n75783 , n75784 , n75785 ,
n75786 , n75787 , n75788 , n75789 , n75790 , n75791 , n75792 , n75793 , n75794 , n9656 ,
n75796 , n75797 , n75798 , n75799 , n75800 , n75801 , n75802 , n75803 , n75804 , n75805 ,
n75806 , n75807 , n75808 , n75809 , n75810 , n75811 , n75812 , n75813 , n75814 , n75815 ,
n75816 , n75817 , n75818 , n75819 , n75820 , n75821 , n75822 , n75823 , n75824 , n75825 ,
n75826 , n75827 , n9689 , n75829 , n75830 , n75831 , n75832 , n75833 , n75834 , n75835 ,
n75836 , n75837 , n75838 , n75839 , n75840 , n75841 , n75842 , n75843 , n75844 , n75845 ,
n75846 , n75847 , n75848 , n75849 , n75850 , n75851 , n75852 , n75853 , n75854 , n75855 ,
n75856 , n75857 , n75858 , n9720 , n9721 , n75861 , n75862 , n75863 , n75864 , n75865 ,
n75866 , n75867 , n75868 , n75869 , n75870 , n75871 , n75872 , n75873 , n75874 , n75875 ,
n75876 , n75877 , n75878 , n75879 , n75880 , n75881 , n75882 , n75883 , n75884 , n75885 ,
n75886 , n75887 , n75888 , n75889 , n75890 , n75891 , n75892 , n75893 , n75894 , n75895 ,
n75896 , n75897 , n75898 , n75899 , n75900 , n75901 , n75902 , n75903 , n75904 , n75905 ,
n75906 , n75907 , n75908 , n75909 , n75910 , n75911 , n75912 , n75913 , n75914 , n75915 ,
n75916 , n75917 , n75918 , n75919 , n75920 , n75921 , n75922 , n75923 , n75924 , n75925 ,
n75926 , n75927 , n75928 , n75929 , n75930 , n75931 , n75932 , n75933 , n75934 , n75935 ,
n75936 , n75937 , n75938 , n75939 , n75940 , n75941 , n75942 , n75943 , n75944 , n75945 ,
n75946 , n75947 , n75948 , n75949 , n75950 , n75951 , n75952 , n75953 , n75954 , n75955 ,
n75956 , n75957 , n75958 , n75959 , n75960 , n75961 , n75962 , n75963 , n75964 , n75965 ,
n75966 , n75967 , n75968 , n75969 , n75970 , n75971 , n75972 , n75973 , n75974 , n75975 ,
n75976 , n75977 , n75978 , n75979 , n75980 , n75981 , n75982 , n75983 , n75984 , n75985 ,
n75986 , n75987 , n75988 , n75989 , n75990 , n75991 , n75992 , n75993 , n75994 , n75995 ,
n75996 , n75997 , n75998 , n75999 , n76000 , n76001 , n76002 , n76003 , n76004 , n76005 ,
n76006 , n76007 , n76008 , n76009 , n76010 , n76011 , n76012 , n76013 , n76014 , n76015 ,
n76016 , n76017 , n76018 , n76019 , n76020 , n76021 , n76022 , n76023 , n76024 , n76025 ,
n76026 , n76027 , n76028 , n76029 , n76030 , n76031 , n76032 , n76033 , n76034 , n76035 ,
n76036 , n76037 , n76038 , n76039 , n76040 , n76041 , n76042 , n76043 , n76044 , n76045 ,
n76046 , n76047 , n76048 , n76049 , n76050 , n76051 , n76052 , n76053 , n76054 , n76055 ,
n76056 , n76057 , n76058 , n76059 , n76060 , n76061 , n76062 , n76063 , n76064 , n76065 ,
n76066 , n76067 , n76068 , n76069 , n76070 , n76071 , n76072 , n76073 , n76074 , n76075 ,
n76076 , n76077 , n76078 , n76079 , n76080 , n76081 , n9943 , n9944 , n76084 , n76085 ,
n76086 , n76087 , n9949 , n9950 , n76090 , n9952 , n9953 , n76093 , n76094 , n76095 ,
n76096 , n76097 , n76098 , n76099 , n76100 , n76101 , n76102 , n76103 , n76104 , n76105 ,
n76106 , n76107 , n76108 , n76109 , n76110 , n76111 , n76112 , n76113 , n76114 , n76115 ,
n76116 , n76117 , n76118 , n76119 , n76120 , n9982 , n9983 , n76123 , n76124 , n76125 ,
n76126 , n76127 , n76128 , n76129 , n76130 , n76131 , n76132 , n76133 , n76134 , n76135 ,
n76136 , n76137 , n76138 , n76139 , n76140 , n76141 , n76142 , n76143 , n76144 , n76145 ,
n76146 , n76147 , n10009 , n10010 , n76150 , n76151 , n76152 , n76153 , n76154 , n76155 ,
n76156 , n10018 , n10019 , n76159 , n76160 , n76161 , n76162 , n76163 , n76164 , n76165 ,
n76166 , n76167 , n76168 , n76169 , n76170 , n76171 , n76172 , n76173 , n76174 , n76175 ,
n76176 , n76177 , n76178 , n76179 , n76180 , n76181 , n76182 , n76183 , n76184 , n76185 ,
n76186 , n76187 , n10049 , n10050 , n76190 , n76191 , n76192 , n76193 , n76194 , n76195 ,
n76196 , n76197 , n10059 , n76199 , n76200 , n76201 , n76202 , n76203 , n76204 , n10066 ,
n10067 , n76207 , n10069 , n10070 , n76210 , n76211 , n76212 , n76213 , n76214 , n76215 ,
n76216 , n76217 , n76218 , n76219 , n76220 , n76221 , n76222 , n76223 , n76224 , n76225 ,
n76226 , n76227 , n10089 , n76229 , n76230 , n76231 , n76232 , n76233 , n76234 , n76235 ,
n76236 , n76237 , n10099 , n10100 , n76240 , n76241 , n76242 , n76243 , n76244 , n76245 ,
n76246 , n76247 , n76248 , n76249 , n76250 , n76251 , n76252 , n76253 , n76254 , n76255 ,
n76256 , n76257 , n10119 , n10120 , n76260 , n76261 , n76262 , n76263 , n76264 , n10126 ,
n10127 , n76267 , n10129 , n10130 , n76270 , n76271 , n76272 , n76273 , n76274 , n10136 ,
n10137 , n76277 , n76278 , n10140 , n76280 , n76281 , n76282 , n76283 , n76284 , n76285 ,
n76286 , n76287 , n76288 , n76289 , n76290 , n76291 , n76292 , n76293 , n76294 , n10156 ,
n76296 , n76297 , n76298 , n76299 , n76300 , n76301 , n76302 , n76303 , n76304 , n76305 ,
n76306 , n76307 , n76308 , n76309 , n76310 , n76311 , n76312 , n76313 , n76314 , n76315 ,
n76316 , n76317 , n76318 , n76319 , n76320 , n76321 , n76322 , n76323 , n76324 , n76325 ,
n76326 , n76327 , n76328 , n10190 , n10191 , n76331 , n76332 , n76333 , n76334 , n10196 ,
n10197 , n76337 , n76338 , n76339 , n76340 , n76341 , n76342 , n76343 , n76344 , n76345 ,
n76346 , n76347 , n76348 , n76349 , n76350 , n76351 , n76352 , n76353 , n76354 , n76355 ,
n76356 , n76357 , n76358 , n76359 , n76360 , n76361 , n10223 , n10224 , n76364 , n76365 ,
n76366 , n76367 , n76368 , n76369 , n76370 , n10232 , n10233 , n76373 , n76374 , n76375 ,
n76376 , n76377 , n76378 , n76379 , n76380 , n76381 , n76382 , n76383 , n76384 , n76385 ,
n76386 , n76387 , n76388 , n76389 , n76390 , n76391 , n76392 , n76393 , n76394 , n76395 ,
n76396 , n76397 , n76398 , n76399 , n76400 , n76401 , n76402 , n76403 , n76404 , n76405 ,
n76406 , n76407 , n76408 , n76409 , n76410 , n76411 , n76412 , n76413 , n76414 , n76415 ,
n76416 , n76417 , n76418 , n76419 , n76420 , n76421 , n76422 , n76423 , n76424 , n76425 ,
n76426 , n76427 , n76428 , n76429 , n76430 , n76431 , n76432 , n76433 , n76434 , n76435 ,
n76436 , n76437 , n76438 , n76439 , n76440 , n76441 , n76442 , n76443 , n76444 , n76445 ,
n76446 , n76447 , n76448 , n76449 , n76450 , n76451 , n76452 , n76453 , n76454 , n76455 ,
n76456 , n76457 , n76458 , n76459 , n76460 , n76461 , n76462 , n76463 , n76464 , n76465 ,
n76466 , n76467 , n76468 , n76469 , n76470 , n76471 , n76472 , n76473 , n76474 , n76475 ,
n76476 , n76477 , n76478 , n76479 , n76480 , n76481 , n76482 , n76483 , n76484 , n76485 ,
n76486 , n76487 , n76488 , n76489 , n76490 , n76491 , n76492 , n76493 , n76494 , n76495 ,
n76496 , n76497 , n76498 , n76499 , n76500 , n76501 , n76502 , n76503 , n76504 , n76505 ,
n76506 , n76507 , n76508 , n76509 , n76510 , n76511 , n76512 , n76513 , n76514 , n76515 ,
n76516 , n76517 , n76518 , n76519 , n76520 , n76521 , n76522 , n76523 , n76524 , n76525 ,
n76526 , n76527 , n76528 , n76529 , n76530 , n76531 , n76532 , n76533 , n76534 , n76535 ,
n76536 , n76537 , n76538 , n76539 , n76540 , n76541 , n76542 , n76543 , n76544 , n76545 ,
n76546 , n76547 , n76548 , n76549 , n76550 , n76551 , n76552 , n76553 , n76554 , n76555 ,
n76556 , n76557 , n76558 , n76559 , n76560 , n76561 , n76562 , n76563 , n76564 , n76565 ,
n76566 , n76567 , n76568 , n76569 , n76570 , n76571 , n76572 , n76573 , n76574 , n76575 ,
n76576 , n76577 , n76578 , n76579 , n76580 , n76581 , n76582 , n76583 , n76584 , n76585 ,
n76586 , n76587 , n76588 , n76589 , n76590 , n76591 , n76592 , n76593 , n76594 , n76595 ,
n76596 , n76597 , n76598 , n76599 , n76600 , n76601 , n76602 , n76603 , n76604 , n76605 ,
n76606 , n76607 , n76608 , n76609 , n76610 , n76611 , n76612 , n76613 , n76614 , n76615 ,
n76616 , n76617 , n76618 , n76619 , n76620 , n76621 , n76622 , n76623 , n76624 , n76625 ,
n76626 , n76627 , n76628 , n76629 , n76630 , n76631 , n76632 , n76633 , n76634 , n76635 ,
n76636 , n76637 , n76638 , n76639 , n76640 , n76641 , n76642 , n76643 , n76644 , n76645 ,
n76646 , n76647 , n76648 , n76649 , n76650 , n76651 , n76652 , n76653 , n76654 , n76655 ,
n76656 , n76657 , n76658 , n76659 , n76660 , n76661 , n76662 , n76663 , n76664 , n76665 ,
n76666 , n76667 , n76668 , n76669 , n76670 , n76671 , n76672 , n76673 , n76674 , n76675 ,
n76676 , n76677 , n76678 , n76679 , n76680 , n76681 , n76682 , n76683 , n76684 , n76685 ,
n76686 , n76687 , n76688 , n76689 , n76690 , n76691 , n76692 , n76693 , n76694 , n76695 ,
n76696 , n76697 , n76698 , n76699 , n76700 , n76701 , n76702 , n76703 , n76704 , n76705 ,
n76706 , n76707 , n76708 , n76709 , n76710 , n76711 , n76712 , n76713 , n76714 , n76715 ,
n76716 , n76717 , n76718 , n76719 , n76720 , n76721 , n76722 , n76723 , n76724 , n76725 ,
n76726 , n76727 , n76728 , n76729 , n76730 , n76731 , n76732 , n76733 , n76734 , n76735 ,
n76736 , n76737 , n76738 , n76739 , n76740 , n76741 , n76742 , n76743 , n76744 , n76745 ,
n76746 , n76747 , n76748 , n76749 , n76750 , n76751 , n76752 , n76753 , n76754 , n76755 ,
n76756 , n76757 , n76758 , n76759 , n76760 , n76761 , n76762 , n76763 , n76764 , n76765 ,
n76766 , n76767 , n76768 , n76769 , n76770 , n76771 , n76772 , n76773 , n76774 , n76775 ,
n76776 , n76777 , n76778 , n76779 , n76780 , n76781 , n76782 , n76783 , n76784 , n76785 ,
n76786 , n76787 , n76788 , n76789 , n76790 , n76791 , n76792 , n76793 , n76794 , n76795 ,
n76796 , n76797 , n76798 , n76799 , n76800 , n76801 , n76802 , n76803 , n76804 , n76805 ,
n76806 , n76807 , n76808 , n76809 , n76810 , n76811 , n76812 , n76813 , n76814 , n76815 ,
n76816 , n76817 , n76818 , n76819 , n76820 , n76821 , n76822 , n76823 , n76824 , n76825 ,
n76826 , n76827 , n76828 , n76829 , n76830 , n76831 , n76832 , n76833 , n76834 , n76835 ,
n76836 , n76837 , n76838 , n76839 , n76840 , n76841 , n76842 , n76843 , n76844 , n76845 ,
n76846 , n76847 , n76848 , n76849 , n76850 , n76851 , n76852 , n76853 , n76854 , n76855 ,
n76856 , n76857 , n76858 , n76859 , n76860 , n76861 , n76862 , n76863 , n76864 , n76865 ,
n76866 , n76867 , n76868 , n76869 , n76870 , n76871 , n76872 , n76873 , n76874 , n76875 ,
n76876 , n76877 , n76878 , n76879 , n76880 , n76881 , n76882 , n76883 , n76884 , n76885 ,
n76886 , n76887 , n76888 , n76889 , n76890 , n76891 , n76892 , n76893 , n76894 , n76895 ,
n76896 , n76897 , n76898 , n76899 , n76900 , n76901 , n76902 , n76903 , n76904 , n76905 ,
n76906 , n76907 , n76908 , n76909 , n76910 , n76911 , n76912 , n76913 , n76914 , n76915 ,
n76916 , n76917 , n76918 , n76919 , n76920 , n76921 , n76922 , n76923 , n76924 , n76925 ,
n76926 , n76927 , n76928 , n76929 , n76930 , n76931 , n76932 , n76933 , n76934 , n76935 ,
n76936 , n76937 , n76938 , n76939 , n76940 , n76941 , n76942 , n76943 , n76944 , n76945 ,
n76946 , n76947 , n76948 , n76949 , n76950 , n76951 , n76952 , n76953 , n76954 , n76955 ,
n76956 , n76957 , n76958 , n76959 , n76960 , n76961 , n76962 , n76963 , n76964 , n76965 ,
n76966 , n76967 , n76968 , n76969 , n76970 , n76971 , n76972 , n76973 , n76974 , n76975 ,
n76976 , n76977 , n76978 , n76979 , n76980 , n76981 , n76982 , n76983 , n76984 , n76985 ,
n76986 , n76987 , n76988 , n76989 , n76990 , n76991 , n76992 , n76993 , n76994 , n76995 ,
n76996 , n76997 , n76998 , n76999 , n77000 , n77001 , n77002 , n77003 , n77004 , n77005 ,
n77006 , n77007 , n77008 , n77009 , n77010 , n77011 , n77012 , n77013 , n77014 , n77015 ,
n77016 , n77017 , n77018 , n77019 , n77020 , n77021 , n77022 , n77023 , n77024 , n77025 ,
n77026 , n77027 , n77028 , n77029 , n77030 , n77031 , n77032 , n77033 , n77034 , n77035 ,
n77036 , n77037 , n77038 , n77039 , n77040 , n77041 , n77042 , n77043 , n77044 , n77045 ,
n77046 , n77047 , n77048 , n77049 , n77050 , n77051 , n77052 , n77053 , n77054 , n77055 ,
n77056 , n77057 , n77058 , n77059 , n77060 , n77061 , n77062 , n77063 , n77064 , n77065 ,
n77066 , n77067 , n77068 , n77069 , n77070 , n77071 , n77072 , n77073 , n77074 , n77075 ,
n77076 , n77077 , n77078 , n77079 , n77080 , n77081 , n77082 , n77083 , n77084 , n77085 ,
n77086 , n77087 , n77088 , n77089 , n77090 , n77091 , n77092 , n77093 , n77094 , n77095 ,
n77096 , n77097 , n77098 , n77099 , n77100 , n77101 , n77102 , n77103 , n77104 , n77105 ,
n77106 , n77107 , n77108 , n77109 , n77110 , n77111 , n77112 , n77113 , n77114 , n77115 ,
n77116 , n77117 , n77118 , n77119 , n77120 , n77121 , n77122 , n77123 , n77124 , n77125 ,
n77126 , n77127 , n77128 , n77129 , n77130 , n77131 , n77132 , n77133 , n77134 , n77135 ,
n77136 , n77137 , n77138 , n77139 , n77140 , n77141 , n77142 , n77143 , n77144 , n77145 ,
n77146 , n77147 , n77148 , n77149 , n77150 , n77151 , n77152 , n77153 , n77154 , n77155 ,
n77156 , n77157 , n77158 , n77159 , n77160 , n77161 , n77162 , n77163 , n77164 , n77165 ,
n77166 , n77167 , n77168 , n77169 , n77170 , n77171 , n77172 , n77173 , n77174 , n77175 ,
n77176 , n77177 , n77178 , n77179 , n77180 , n77181 , n77182 , n77183 , n77184 , n77185 ,
n77186 , n77187 , n77188 , n77189 , n77190 , n77191 , n77192 , n77193 , n77194 , n77195 ,
n77196 , n77197 , n77198 , n77199 , n77200 , n77201 , n77202 , n77203 , n77204 , n77205 ,
n77206 , n77207 , n77208 , n77209 , n77210 , n77211 , n77212 , n77213 , n77214 , n77215 ,
n77216 , n77217 , n77218 , n77219 , n77220 , n77221 , n77222 , n77223 , n77224 , n77225 ,
n77226 , n77227 , n77228 , n77229 , n77230 , n77231 , n77232 , n77233 , n77234 , n77235 ,
n77236 , n77237 , n77238 , n77239 , n77240 , n77241 , n77242 , n77243 , n77244 , n77245 ,
n77246 , n77247 , n77248 , n77249 , n77250 , n77251 , n77252 , n77253 , n77254 , n77255 ,
n77256 , n77257 , n77258 , n77259 , n77260 , n77261 , n77262 , n77263 , n77264 , n77265 ,
n77266 , n77267 , n77268 , n77269 , n77270 , n77271 , n77272 , n77273 , n77274 , n77275 ,
n77276 , n77277 , n77278 , n77279 , n77280 , n77281 , n77282 , n77283 , n77284 , n77285 ,
n77286 , n77287 , n77288 , n77289 , n77290 , n77291 , n77292 , n77293 , n77294 , n77295 ,
n77296 , n77297 , n77298 , n77299 , n77300 , n77301 , n77302 , n77303 , n77304 , n77305 ,
n77306 , n77307 , n77308 , n77309 , n77310 , n77311 , n77312 , n77313 , n77314 , n77315 ,
n77316 , n77317 , n77318 , n77319 , n77320 , n77321 , n77322 , n77323 , n77324 , n77325 ,
n77326 , n77327 , n77328 , n77329 , n77330 , n77331 , n77332 , n77333 , n77334 , n77335 ,
n77336 , n77337 , n77338 , n77339 , n77340 , n77341 , n77342 , n77343 , n77344 , n77345 ,
n77346 , n77347 , n77348 , n77349 , n77350 , n77351 , n77352 , n77353 , n77354 , n77355 ,
n77356 , n77357 , n77358 , n77359 , n77360 , n77361 , n77362 , n77363 , n77364 , n77365 ,
n77366 , n77367 , n77368 , n77369 , n77370 , n77371 , n77372 , n77373 , n77374 , n77375 ,
n77376 , n77377 , n77378 , n77379 , n77380 , n77381 , n77382 , n77383 , n77384 , n77385 ,
n77386 , n77387 , n77388 , n77389 , n77390 , n77391 , n77392 , n77393 , n77394 , n77395 ,
n77396 , n77397 , n77398 , n77399 , n77400 , n77401 , n77402 , n77403 , n77404 , n77405 ,
n77406 , n77407 , n77408 , n77409 , n77410 , n77411 , n77412 , n77413 , n77414 , n77415 ,
n77416 , n77417 , n77418 , n77419 , n77420 , n77421 , n77422 , n77423 , n77424 , n77425 ,
n77426 , n77427 , n77428 , n77429 , n77430 , n77431 , n77432 , n77433 , n77434 , n77435 ,
n77436 , n77437 , n77438 , n77439 , n77440 , n77441 , n77442 , n77443 , n77444 , n77445 ,
n77446 , n77447 , n77448 , n77449 , n77450 , n77451 , n77452 , n77453 , n77454 , n77455 ,
n77456 , n77457 , n77458 , n77459 , n77460 , n77461 , n77462 , n77463 , n77464 , n77465 ,
n77466 , n77467 , n77468 , n77469 , n77470 , n77471 , n77472 , n77473 , n77474 , n77475 ,
n77476 , n77477 , n77478 , n77479 , n77480 , n77481 , n77482 , n77483 , n77484 , n77485 ,
n77486 , n77487 , n77488 , n77489 , n77490 , n77491 , n77492 , n77493 , n77494 , n77495 ,
n77496 , n77497 , n77498 , n77499 , n77500 , n77501 , n77502 , n77503 , n77504 , n77505 ,
n77506 , n77507 , n77508 , n77509 , n77510 , n77511 , n77512 , n77513 , n77514 , n77515 ,
n77516 , n77517 , n77518 , n77519 , n77520 , n77521 , n77522 , n77523 , n77524 , n77525 ,
n77526 , n77527 , n77528 , n77529 , n77530 , n77531 , n77532 , n77533 , n77534 , n77535 ,
n77536 , n77537 , n77538 , n77539 , n77540 , n77541 , n77542 , n77543 , n77544 , n77545 ,
n77546 , n77547 , n77548 , n77549 , n77550 , n77551 , n77552 , n77553 , n77554 , n77555 ,
n77556 , n77557 , n77558 , n77559 , n77560 , n77561 , n77562 , n77563 , n77564 , n77565 ,
n77566 , n77567 , n77568 , n77569 , n77570 , n77571 , n77572 , n77573 , n77574 , n77575 ,
n77576 , n77577 , n77578 , n77579 , n77580 , n77581 , n77582 , n77583 , n77584 , n77585 ,
n77586 , n77587 , n77588 , n77589 , n77590 , n77591 , n77592 , n77593 , n77594 , n77595 ,
n77596 , n77597 , n77598 , n77599 , n77600 , n77601 , n77602 , n77603 , n77604 , n77605 ,
n77606 , n77607 , n77608 , n77609 , n77610 , n77611 , n77612 , n77613 , n77614 , n77615 ,
n77616 , n77617 , n77618 , n77619 , n77620 , n77621 , n77622 , n77623 , n77624 , n77625 ,
n77626 , n77627 , n77628 , n77629 , n77630 , n77631 , n77632 , n77633 , n77634 , n77635 ,
n77636 , n77637 , n77638 , n77639 , n77640 , n77641 , n77642 , n77643 , n77644 , n77645 ,
n77646 , n77647 , n77648 , n77649 , n77650 , n77651 , n77652 , n77653 , n77654 , n77655 ,
n77656 , n77657 , n77658 , n77659 , n77660 , n77661 , n77662 , n77663 , n77664 , n77665 ,
n77666 , n77667 , n77668 , n77669 , n77670 , n77671 , n77672 , n77673 , n77674 , n77675 ,
n77676 , n77677 , n77678 , n77679 , n77680 , n77681 , n77682 , n77683 , n77684 , n77685 ,
n77686 , n77687 , n77688 , n77689 , n77690 , n77691 , n77692 , n77693 , n77694 , n77695 ,
n77696 , n77697 , n77698 , n77699 , n77700 , n77701 , n77702 , n77703 , n77704 , n77705 ,
n77706 , n77707 , n77708 , n77709 , n77710 , n77711 , n77712 , n77713 , n77714 , n77715 ,
n77716 , n77717 , n77718 , n77719 , n77720 , n77721 , n77722 , n77723 , n77724 , n77725 ,
n77726 , n77727 , n77728 , n77729 , n77730 , n77731 , n77732 , n77733 , n77734 , n77735 ,
n77736 , n77737 , n77738 , n77739 , n77740 , n77741 , n77742 , n77743 , n77744 , n77745 ,
n77746 , n77747 , n77748 , n77749 , n77750 , n77751 , n77752 , n77753 , n77754 , n77755 ,
n77756 , n77757 , n77758 , n77759 , n77760 , n77761 , n77762 , n77763 , n77764 , n77765 ,
n77766 , n77767 , n77768 , n77769 , n77770 , n77771 , n77772 , n77773 , n77774 , n77775 ,
n77776 , n77777 , n77778 , n77779 , n77780 , n77781 , n77782 ;
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buf ( n844 , n74397 );
buf ( n845 , n74398 );
buf ( n846 , n8274 );
buf ( n847 , n8237 );
buf ( n848 , n74378 );
buf ( n849 , n74379 );
buf ( n850 , n74394 );
buf ( n851 , n74357 );
buf ( n852 , n74359 );
buf ( n853 , n8221 );
buf ( n854 , n74375 );
buf ( n855 , n8199 );
buf ( n856 , n8201 );
buf ( n857 , n8202 );
buf ( n858 , n8217 );
buf ( n859 , n74319 );
buf ( n860 , n74321 );
buf ( n861 , n74322 );
buf ( n862 , n74337 );
buf ( n863 , n74300 );
buf ( n864 , n8163 );
buf ( n865 , n8164 );
buf ( n866 , n74318 );
buf ( n867 , n2698 );
buf ( n868 , n68840 );
buf ( n869 , n68841 );
buf ( n870 , n70905 );
buf ( n871 , n8143 );
buf ( n872 , n74284 );
buf ( n873 , n74285 );
buf ( n874 , n74299 );
buf ( n875 , n74263 );
buf ( n876 , n8126 );
buf ( n877 , n8127 );
buf ( n878 , n8142 );
buf ( n879 , n74244 );
buf ( n880 , n74246 );
buf ( n881 , n74247 );
buf ( n882 , n74262 );
buf ( n883 , n74204 );
buf ( n884 , n8067 );
buf ( n885 , n8068 );
buf ( n886 , n74222 );
buf ( n887 , n8046 );
buf ( n888 , n74187 );
buf ( n889 , n74188 );
buf ( n890 , n74203 );
buf ( n891 , n8027 );
buf ( n892 , n74168 );
buf ( n893 , n74169 );
buf ( n894 , n8045 );
buf ( n895 , n74147 );
buf ( n896 , n8010 );
buf ( n897 , n8011 );
buf ( n898 , n8026 );
buf ( n899 , n7989 );
buf ( n900 , n74130 );
buf ( n901 , n7992 );
buf ( n902 , n74146 );
buf ( n903 , n7972 );
buf ( n904 , n74113 );
buf ( n905 , n74114 );
buf ( n906 , n7988 );
buf ( n907 , n74093 );
buf ( n908 , n74095 );
buf ( n909 , n74096 );
buf ( n910 , n7971 );
buf ( n911 , n7937 );
buf ( n912 , n74078 );
buf ( n913 , n74079 );
buf ( n914 , n7953 );
buf ( n915 , n7921 );
buf ( n916 , n74062 );
buf ( n917 , n74063 );
buf ( n918 , n7936 );
buf ( n919 , n7830 );
buf ( n920 , n7832 );
buf ( n921 , n7833 );
buf ( n922 , n7920 );
buf ( n923 , n7793 );
buf ( n924 , n73934 );
buf ( n925 , n73935 );
buf ( n926 , n73951 );
buf ( n927 , n7750 );
buf ( n928 , n73891 );
buf ( n929 , n73892 );
buf ( n930 , n73931 );
buf ( n931 , n76066 );
buf ( n932 , n76068 );
buf ( n933 , n76069 );
buf ( n934 , n76079 );
buf ( n935 , n75608 );
buf ( n936 , n75610 );
buf ( n937 , n75611 );
buf ( n938 , n75623 );
buf ( n939 , n75578 );
buf ( n940 , n75580 );
buf ( n941 , n75581 );
buf ( n942 , n75607 );
buf ( n943 , n75551 );
buf ( n944 , n75553 );
buf ( n945 , n9415 );
buf ( n946 , n75577 );
buf ( n947 , n75515 );
buf ( n948 , n75517 );
buf ( n949 , n75518 );
buf ( n950 , n75550 );
buf ( n951 , n75484 );
buf ( n952 , n75486 );
buf ( n953 , n75487 );
buf ( n954 , n75514 );
buf ( n955 , n9318 );
buf ( n956 , n75459 );
buf ( n957 , n75460 );
buf ( n958 , n75483 );
buf ( n959 , n75420 );
buf ( n960 , n9283 );
buf ( n961 , n9284 );
buf ( n962 , n9317 );
buf ( n963 , n9256 );
buf ( n964 , n9258 );
buf ( n965 , n9259 );
buf ( n966 , n75419 );
buf ( n967 , n75262 );
buf ( n968 , n9125 );
buf ( n969 , n9126 );
buf ( n970 , n75394 );
buf ( n971 , n76038 );
buf ( n972 , n76040 );
buf ( n973 , n76041 );
buf ( n974 , n76065 );
buf ( n975 , n76000 );
buf ( n976 , n76002 );
buf ( n977 , n76003 );
buf ( n978 , n76037 );
buf ( n979 , n75974 );
buf ( n980 , n75976 );
buf ( n981 , n75977 );
buf ( n982 , n75999 );
buf ( n983 , n75940 );
buf ( n984 , n75942 );
buf ( n985 , n75943 );
buf ( n986 , n75973 );
buf ( n987 , n75910 );
buf ( n988 , n75912 );
buf ( n989 , n75913 );
buf ( n990 , n75939 );
buf ( n991 , n9721 );
buf ( n992 , n75862 );
buf ( n993 , n75863 );
buf ( n994 , n75909 );
buf ( n995 , n75829 );
buf ( n996 , n75831 );
buf ( n997 , n75832 );
buf ( n998 , n9720 );
buf ( n999 , n75796 );
buf ( n1000 , n75798 );
buf ( n1001 , n75799 );
buf ( n1002 , n9689 );
buf ( n1003 , n9620 );
buf ( n1004 , n9622 );
buf ( n1005 , n9623 );
buf ( n1006 , n9656 );
buf ( n1007 , n75624 );
buf ( n1008 , n9487 );
buf ( n1009 , n9488 );
buf ( n1010 , n9619 );
buf ( n1011 , n75231 );
buf ( n1012 , n75233 );
buf ( n1013 , n75234 );
buf ( n1014 , n75242 );
buf ( n1015 , n75219 );
buf ( n1016 , n9082 );
buf ( n1017 , n9083 );
buf ( n1018 , n9091 );
buf ( n1019 , n75189 );
buf ( n1020 , n9052 );
buf ( n1021 , n75192 );
buf ( n1022 , n75200 );
buf ( n1023 , n9030 );
buf ( n1024 , n75171 );
buf ( n1025 , n75172 );
buf ( n1026 , n75179 );
buf ( n1027 , n75160 );
buf ( n1028 , n75162 );
buf ( n1029 , n9024 );
buf ( n1030 , n9029 );
buf ( n1031 , n75151 );
buf ( n1032 , n9014 );
buf ( n1033 , n9015 );
buf ( n1034 , n9020 );
buf ( n1035 , n75142 );
buf ( n1036 , n75144 );
buf ( n1037 , n75145 );
buf ( n1038 , n75150 );
buf ( n1039 , n75133 );
buf ( n1040 , n75135 );
buf ( n1041 , n75136 );
buf ( n1042 , n75141 );
buf ( n1043 , n75124 );
buf ( n1044 , n75126 );
buf ( n1045 , n8988 );
buf ( n1046 , n75132 );
buf ( n1047 , n71719 );
buf ( n1048 , n5582 );
buf ( n1049 , n71722 );
buf ( n1050 , n5591 );
buf ( n1051 , n71963 );
buf ( n1052 , n71965 );
buf ( n1053 , n71966 );
buf ( n1054 , n71971 );
buf ( n1055 , n71954 );
buf ( n1056 , n71956 );
buf ( n1057 , n71957 );
buf ( n1058 , n71962 );
buf ( n1059 , n71945 );
buf ( n1060 , n71947 );
buf ( n1061 , n71948 );
buf ( n1062 , n71953 );
buf ( n1063 , n71936 );
buf ( n1064 , n71938 );
buf ( n1065 , n71939 );
buf ( n1066 , n71944 );
buf ( n1067 , n71927 );
buf ( n1068 , n71929 );
buf ( n1069 , n71930 );
buf ( n1070 , n71935 );
buf ( n1071 , n71918 );
buf ( n1072 , n71920 );
buf ( n1073 , n71921 );
buf ( n1074 , n71926 );
buf ( n1075 , n71909 );
buf ( n1076 , n71911 );
buf ( n1077 , n71912 );
buf ( n1078 , n71917 );
buf ( n1079 , n71900 );
buf ( n1080 , n71902 );
buf ( n1081 , n71903 );
buf ( n1082 , n71908 );
buf ( n1083 , n5752 );
buf ( n1084 , n5754 );
buf ( n1085 , n5755 );
buf ( n1086 , n71899 );
buf ( n1087 , n71882 );
buf ( n1088 , n5745 );
buf ( n1089 , n71885 );
buf ( n1090 , n5751 );
buf ( n1091 , n5734 );
buf ( n1092 , n71875 );
buf ( n1093 , n71876 );
buf ( n1094 , n5742 );
buf ( n1095 , n71856 );
buf ( n1096 , n71858 );
buf ( n1097 , n71859 );
buf ( n1098 , n71872 );
buf ( n1099 , n71838 );
buf ( n1100 , n5701 );
buf ( n1101 , n5702 );
buf ( n1102 , n71855 );
buf ( n1103 , n71818 );
buf ( n1104 , n5681 );
buf ( n1105 , n5682 );
buf ( n1106 , n71837 );
buf ( n1107 , n5664 );
buf ( n1108 , n71805 );
buf ( n1109 , n71806 );
buf ( n1110 , n71817 );
buf ( n1111 , n5645 );
buf ( n1112 , n71786 );
buf ( n1113 , n71787 );
buf ( n1114 , n71802 );
buf ( n1115 , n71767 );
buf ( n1116 , n71769 );
buf ( n1117 , n5631 );
buf ( n1118 , n5644 );
buf ( n1119 , n5601 );
buf ( n1120 , n71742 );
buf ( n1121 , n5604 );
buf ( n1122 , n71766 );
buf ( n1123 , n75210 );
buf ( n1124 , n75212 );
buf ( n1125 , n75213 );
buf ( n1126 , n75218 );
buf ( n1127 , n9062 );
buf ( n1128 , n75203 );
buf ( n1129 , n75204 );
buf ( n1130 , n75209 );
buf ( n1131 , n75180 );
buf ( n1132 , n75182 );
buf ( n1133 , n75183 );
buf ( n1134 , n75188 );
buf ( n1135 , n5592 );
buf ( n1136 , n5594 );
buf ( n1137 , n5595 );
buf ( n1138 , n71739 );
buf ( DFF_rd_reg_S , n77772 );
buf ( DFF_rd_reg_R , n77774 );
buf ( DFF_rd_reg_CK , n77775 );
buf ( DFF_rd_reg_D , n77782 );
buf ( DFF_wr_reg_S , n77766 );
buf ( DFF_wr_reg_R , n77769 );
buf ( DFF_wr_reg_CK , n77770 );
buf ( DFF_wr_reg_D , n77771 );
buf ( n68634 , PI_clock);
buf ( n68635 , PI_reset);
buf ( n68636 , n0 );
buf ( n2498 , n1 );
buf ( n2499 , n2 );
buf ( n2500 , n3 );
buf ( n2501 , n4 );
buf ( n2502 , n5 );
buf ( n2503 , n6 );
buf ( n2504 , n7 );
buf ( n68644 , n8 );
buf ( n68645 , n9 );
buf ( n68646 , n10 );
buf ( n2508 , n11 );
buf ( n2509 , n12 );
buf ( n68649 , n13 );
buf ( n68650 , n14 );
buf ( n68651 , n15 );
buf ( n2513 , n16 );
buf ( n2514 , n17 );
buf ( n2515 , n18 );
buf ( n2516 , n19 );
buf ( n2517 , n20 );
buf ( n2518 , n21 );
buf ( n2519 , n22 );
buf ( n68659 , n23 );
buf ( n68660 , n24 );
buf ( n68661 , n25 );
buf ( n2523 , n26 );
buf ( n2524 , n27 );
buf ( n68664 , n28 );
buf ( n68665 , n29 );
buf ( n68666 , n30 );
buf ( n2528 , n31 );
buf ( n2529 , n210 );
not ( n68669 , n2529 );
not ( n68670 , n68669 );
buf ( n2532 , n68670 );
buf ( n2533 , n2532 );
buf ( n2534 , n209 );
not ( n68674 , n2534 );
not ( n68675 , n68674 );
buf ( n68676 , n68675 );
buf ( n2538 , n68676 );
buf ( n2539 , n208 );
not ( n68679 , n2539 );
not ( n68680 , n68679 );
buf ( n68681 , n68680 );
buf ( n2543 , n68681 );
buf ( n2544 , n207 );
not ( n68684 , n2544 );
not ( n68685 , n68684 );
buf ( n2547 , n68685 );
buf ( n2548 , n2547 );
buf ( n2549 , n206 );
not ( n68689 , n2549 );
not ( n68690 , n68689 );
buf ( n68691 , n68690 );
buf ( n2553 , n68691 );
buf ( n2554 , n205 );
not ( n68694 , n2554 );
not ( n68695 , n68694 );
buf ( n68696 , n68695 );
buf ( n2558 , n68696 );
buf ( n2559 , n204 );
not ( n68699 , n2559 );
not ( n68700 , n68699 );
buf ( n2562 , n68700 );
buf ( n2563 , n2562 );
buf ( n2564 , n203 );
not ( n68704 , n2564 );
not ( n68705 , n68704 );
buf ( n68706 , n68705 );
buf ( n2568 , n68706 );
buf ( n2569 , n202 );
not ( n68709 , n2569 );
not ( n68710 , n68709 );
buf ( n68711 , n68710 );
buf ( n2573 , n68711 );
buf ( n2574 , n201 );
not ( n68714 , n2574 );
not ( n68715 , n68714 );
buf ( n2577 , n68715 );
buf ( n2578 , n2577 );
buf ( n2579 , n200 );
not ( n68719 , n2579 );
not ( n68720 , n68719 );
buf ( n68721 , n68720 );
buf ( n2583 , n68721 );
buf ( n2584 , n199 );
not ( n68724 , n2584 );
not ( n68725 , n68724 );
buf ( n68726 , n68725 );
buf ( n2588 , n68726 );
buf ( n2589 , n198 );
not ( n68729 , n2589 );
not ( n68730 , n68729 );
buf ( n2592 , n68730 );
buf ( n2593 , n2592 );
buf ( n2594 , n197 );
not ( n68734 , n2594 );
not ( n68735 , n68734 );
buf ( n68736 , n68735 );
buf ( n2598 , n68736 );
buf ( n2599 , n196 );
not ( n68739 , n2599 );
not ( n68740 , n68739 );
buf ( n68741 , n68740 );
buf ( n2603 , n68741 );
buf ( n2604 , n195 );
buf ( n2605 , n2604 );
buf ( n2606 , n194 );
not ( n68746 , n2606 );
not ( n68747 , n68746 );
buf ( n2609 , n68747 );
buf ( n68749 , n2609 );
buf ( n68750 , n193 );
buf ( n68751 , n68750 );
buf ( n2613 , n192 );
not ( n68753 , n2613 );
not ( n68754 , n68753 );
buf ( n68755 , n68754 );
buf ( n68756 , n68755 );
buf ( n2618 , n191 );
not ( n68758 , n2618 );
not ( n68759 , n68758 );
buf ( n2621 , n68759 );
buf ( n2622 , n2621 );
buf ( n2623 , n242 );
buf ( n2624 , n2623 );
buf ( n68764 , n241 );
buf ( n68765 , n68764 );
buf ( n68766 , n240 );
buf ( n2628 , n68766 );
buf ( n2629 , n239 );
buf ( n68769 , n2629 );
buf ( n68770 , n238 );
buf ( n68771 , n68770 );
buf ( n2633 , n237 );
buf ( n2634 , n2633 );
buf ( n2635 , n236 );
buf ( n2636 , n2635 );
buf ( n2637 , n235 );
buf ( n2638 , n2637 );
buf ( n2639 , n234 );
buf ( n68779 , n2639 );
buf ( n68780 , n233 );
buf ( n68781 , n68780 );
buf ( n2643 , n232 );
buf ( n2644 , n2643 );
buf ( n68784 , n231 );
buf ( n68785 , n68784 );
buf ( n68786 , n230 );
buf ( n2648 , n68786 );
buf ( n2649 , n229 );
buf ( n2650 , n2649 );
buf ( n2651 , n228 );
buf ( n2652 , n2651 );
buf ( n2653 , n227 );
buf ( n2654 , n2653 );
buf ( n68794 , n226 );
buf ( n68795 , n68794 );
buf ( n68796 , n225 );
buf ( n2658 , n68796 );
buf ( n2659 , n224 );
buf ( n68799 , n2659 );
buf ( n68800 , n223 );
buf ( n68801 , n68800 );
buf ( n2663 , n222 );
buf ( n2664 , n2663 );
buf ( n2665 , n221 );
buf ( n2666 , n2665 );
buf ( n2667 , n220 );
buf ( n2668 , n2667 );
buf ( n2669 , n219 );
buf ( n68809 , n2669 );
buf ( n68810 , n218 );
buf ( n68811 , n68810 );
buf ( n2673 , n217 );
buf ( n2674 , n2673 );
buf ( n68814 , n216 );
buf ( n68815 , n68814 );
buf ( n68816 , n215 );
not ( n68817 , n68816 );
not ( n68818 , n68817 );
buf ( n2680 , n68818 );
buf ( n2681 , n2680 );
buf ( n2682 , n214 );
not ( n68822 , n2682 );
not ( n68823 , n68822 );
buf ( n68824 , n68823 );
buf ( n68825 , n68824 );
buf ( n68826 , n213 );
buf ( n2688 , n68826 );
buf ( n2689 , n212 );
buf ( n68829 , n2689 );
buf ( n68830 , n211 );
buf ( n68831 , n68830 );
buf ( n2693 , DFF_rd_reg_Q);
buf ( n2694 , n2693 );
buf ( n2695 , DFF_wr_reg_Q);
buf ( n2696 , n2695 );
buf ( n2697 , n175 );
buf ( n2698 , 1'b0 );
not ( n68838 , n68635 );
not ( n68839 , n68838 );
buf ( n68840 , n68839 );
buf ( n68841 , n68634 );
buf ( n2703 , n63 );
not ( n68843 , n2703 );
not ( n68844 , n68843 );
not ( n68845 , n68844 );
buf ( n68846 , n36 );
not ( n68847 , n68846 );
not ( n68848 , n68847 );
buf ( n2710 , n37 );
not ( n68850 , n2710 );
not ( n68851 , n68850 );
not ( n68852 , n68851 );
not ( n68853 , n68852 );
nor ( n68854 , n68848 , n68853 );
buf ( n68855 , n39 );
not ( n68856 , n68855 );
not ( n68857 , n68856 );
not ( n68858 , n68857 );
not ( n68859 , n68858 );
buf ( n68860 , n38 );
not ( n68861 , n68860 );
not ( n68862 , n68861 );
not ( n68863 , n68862 );
not ( n68864 , n68863 );
nor ( n68865 , n68859 , n68864 );
nand ( n68866 , n68854 , n68865 );
buf ( n2728 , n32 );
not ( n68868 , n2728 );
buf ( n68869 , n33 );
not ( n68870 , n68869 );
nand ( n68871 , n68868 , n68870 );
not ( n68872 , n68871 );
buf ( n2734 , n34 );
not ( n68874 , n2734 );
not ( n68875 , n68874 );
buf ( n68876 , n35 );
not ( n68877 , n68876 );
not ( n68878 , n68877 );
nor ( n68879 , n68875 , n68878 );
nand ( n68880 , n68872 , n68879 );
or ( n68881 , n68866 , n68880 );
not ( n68882 , n68881 );
buf ( n2744 , n41 );
not ( n68884 , n2744 );
buf ( n68885 , n40 );
not ( n68886 , n68885 );
not ( n68887 , n68886 );
not ( n68888 , n68887 );
nand ( n68889 , n68884 , n68888 );
buf ( n68890 , n43 );
not ( n68891 , n68890 );
buf ( n2753 , n42 );
not ( n68893 , n2753 );
nand ( n68894 , n68891 , n68893 );
nor ( n68895 , n68889 , n68894 );
nand ( n68896 , n68882 , n68895 );
buf ( n2758 , n44 );
and ( n68898 , n68896 , n2758 );
not ( n68899 , n68896 );
not ( n68900 , n2758 );
and ( n68901 , n68899 , n68900 );
nor ( n68902 , n68898 , n68901 );
not ( n68903 , n68902 );
not ( n68904 , n68903 );
not ( n68905 , n68904 );
or ( n68906 , n68845 , n68905 );
nand ( n68907 , n68843 , n2758 );
nand ( n68908 , n68906 , n68907 );
not ( n68909 , n68908 );
not ( n68910 , n68909 );
not ( n68911 , n68843 );
not ( n68912 , n68911 );
buf ( n2774 , n47 );
not ( n68914 , n2774 );
not ( n68915 , n68914 );
not ( n68916 , n68880 );
not ( n68917 , n68866 );
nand ( n68918 , n68916 , n68917 );
not ( n68919 , n68918 );
buf ( n68920 , n45 );
not ( n68921 , n68920 );
nand ( n68922 , n68921 , n68900 );
buf ( n2784 , n46 );
nor ( n68924 , n68922 , n2784 );
and ( n68925 , n68895 , n68924 );
nand ( n68926 , n68919 , n68925 );
not ( n68927 , n68926 );
or ( n68928 , n68915 , n68927 );
or ( n68929 , n68926 , n68914 );
nand ( n68930 , n68928 , n68929 );
not ( n68931 , n68930 );
or ( n68932 , n68912 , n68931 );
nand ( n68933 , n68843 , n2774 );
nand ( n68934 , n68932 , n68933 );
nor ( n68935 , n68910 , n68934 );
not ( n68936 , n68844 );
not ( n68937 , n68895 );
nor ( n68938 , n68937 , n2758 );
nand ( n68939 , n68919 , n68938 );
and ( n68940 , n68939 , n68920 );
not ( n68941 , n68939 );
and ( n68942 , n68941 , n68921 );
nor ( n68943 , n68940 , n68942 );
not ( n68944 , n68943 );
or ( n68945 , n68936 , n68944 );
nand ( n68946 , n68843 , n68920 );
nand ( n68947 , n68945 , n68946 );
not ( n68948 , n68947 );
not ( n68949 , n68948 );
not ( n68950 , n68844 );
nor ( n68951 , n68937 , n68922 );
nand ( n68952 , n68919 , n68951 );
and ( n68953 , n68952 , n2784 );
not ( n68954 , n68952 );
not ( n68955 , n2784 );
and ( n68956 , n68954 , n68955 );
nor ( n68957 , n68953 , n68956 );
not ( n68958 , n68957 );
or ( n68959 , n68950 , n68958 );
nand ( n68960 , n68843 , n2784 );
nand ( n68961 , n68959 , n68960 );
nor ( n68962 , n68949 , n68961 );
not ( n68963 , n68844 );
not ( n68964 , n68893 );
nor ( n68965 , n68964 , n68889 );
nand ( n68966 , n68882 , n68965 );
not ( n68967 , n68891 );
and ( n68968 , n68966 , n68967 );
not ( n68969 , n68966 );
and ( n68970 , n68969 , n68891 );
nor ( n68971 , n68968 , n68970 );
not ( n68972 , n68971 );
not ( n68973 , n68972 );
not ( n68974 , n68973 );
or ( n68975 , n68963 , n68974 );
nand ( n68976 , n68843 , n68890 );
nand ( n68977 , n68975 , n68976 );
not ( n68978 , n68977 );
not ( n68979 , n68887 );
not ( n68980 , n68843 );
or ( n68981 , n68979 , n68980 );
not ( n68982 , n68887 );
not ( n68983 , n68882 );
or ( n68984 , n68982 , n68983 );
or ( n68985 , n68919 , n68887 );
nand ( n68986 , n68984 , n68985 );
nand ( n68987 , n68986 , n2703 );
nand ( n68988 , n68981 , n68987 );
and ( n68989 , n68843 , n68857 );
not ( n68990 , n68843 );
not ( n68991 , n68859 );
not ( n68992 , n68991 );
not ( n68993 , n68852 );
nor ( n68994 , n68993 , n68848 );
not ( n68995 , n68994 );
nor ( n68996 , n68995 , n68864 );
not ( n68997 , n68878 );
not ( n68998 , n68869 );
not ( n68999 , n2728 );
not ( n69000 , n68875 );
and ( n69001 , n68997 , n68998 , n68999 , n69000 );
nand ( n69002 , n68996 , n69001 );
not ( n69003 , n69002 );
or ( n69004 , n68992 , n69003 );
nand ( n69005 , n69001 , n68996 );
or ( n69006 , n69005 , n68991 );
nand ( n69007 , n69004 , n69006 );
and ( n69008 , n68990 , n69007 );
nor ( n69009 , n68989 , n69008 );
not ( n69010 , n69009 );
not ( n69011 , n69010 );
and ( n69012 , n68843 , n68851 );
not ( n69013 , n68843 );
not ( n69014 , n68993 );
not ( n69015 , n69014 );
not ( n69016 , n68848 );
nand ( n69017 , n69001 , n69016 );
not ( n69018 , n69017 );
or ( n69019 , n69015 , n69018 );
nand ( n69020 , n69001 , n69016 );
or ( n69021 , n69020 , n69014 );
nand ( n69022 , n69019 , n69021 );
and ( n69023 , n69013 , n69022 );
nor ( n69024 , n69012 , n69023 );
not ( n69025 , n69024 );
not ( n69026 , n69025 );
nand ( n69027 , n69011 , n69026 );
nor ( n69028 , n68988 , n69027 );
and ( n69029 , n68978 , n69028 );
nand ( n69030 , n68935 , n68962 , n69029 );
not ( n69031 , n69030 );
not ( n69032 , n68844 );
not ( n69033 , n68893 );
not ( n69034 , n68889 );
nand ( n69035 , n69034 , n68882 );
not ( n69036 , n69035 );
or ( n69037 , n69033 , n69036 );
or ( n69038 , n69035 , n68893 );
nand ( n69039 , n69037 , n69038 );
not ( n69040 , n69039 );
not ( n69041 , n69040 );
not ( n69042 , n69041 );
or ( n69043 , n69032 , n69042 );
nand ( n69044 , n68843 , n2753 );
nand ( n69045 , n69043 , n69044 );
not ( n69046 , n69045 );
and ( n69047 , n68843 , n68862 );
not ( n69048 , n68843 );
not ( n69049 , n68864 );
not ( n69050 , n69049 );
nand ( n69051 , n69001 , n68994 );
not ( n69052 , n69051 );
or ( n69053 , n69050 , n69052 );
nand ( n69054 , n69001 , n68994 );
or ( n69055 , n69054 , n69049 );
nand ( n69056 , n69053 , n69055 );
and ( n69057 , n69048 , n69056 );
nor ( n69058 , n69047 , n69057 );
not ( n69059 , n69058 );
not ( n69060 , n2703 );
and ( n69061 , n69060 , n68878 );
not ( n69062 , n69060 );
not ( n69063 , n69000 );
nor ( n69064 , n69063 , n68871 );
and ( n69065 , n69064 , n68997 );
not ( n69066 , n69064 );
not ( n69067 , n68997 );
and ( n69068 , n69066 , n69067 );
nor ( n69069 , n69065 , n69068 );
and ( n69070 , n69062 , n69069 );
nor ( n69071 , n69061 , n69070 );
not ( n69072 , n69071 );
not ( n69073 , n69072 );
not ( n69074 , n69016 );
not ( n69075 , n68880 );
or ( n69076 , n69074 , n69075 );
or ( n69077 , n69016 , n68880 );
nand ( n69078 , n69076 , n69077 );
and ( n69079 , n2703 , n69078 );
not ( n69080 , n2703 );
and ( n69081 , n69080 , n68848 );
nor ( n69082 , n69079 , n69081 );
not ( n69083 , n69082 );
not ( n69084 , n69083 );
not ( n69085 , n2703 );
not ( n69086 , n69000 );
not ( n69087 , n68871 );
or ( n69088 , n69086 , n69087 );
or ( n69089 , n68871 , n69000 );
nand ( n69090 , n69088 , n69089 );
not ( n69091 , n69090 );
or ( n69092 , n69085 , n69091 );
not ( n69093 , n2703 );
nand ( n69094 , n69093 , n68875 );
nand ( n69095 , n69092 , n69094 );
not ( n69096 , n2703 );
not ( n69097 , n68998 );
not ( n69098 , n69097 );
not ( n69099 , n68999 );
or ( n69100 , n69098 , n69099 );
or ( n69101 , n69097 , n68999 );
nand ( n69102 , n69100 , n69101 );
not ( n69103 , n69102 );
or ( n69104 , n69096 , n69103 );
nand ( n69105 , n69093 , n68869 );
nand ( n69106 , n69104 , n69105 );
not ( n69107 , n69106 );
not ( n69108 , n2728 );
nand ( n69109 , n69107 , n69108 );
nor ( n69110 , n69095 , n69109 );
nand ( n69111 , n69073 , n69084 , n69110 );
nor ( n69112 , n69059 , n69111 );
and ( n69113 , n69046 , n69112 );
not ( n69114 , n68844 );
nand ( n69115 , n68919 , n68888 );
and ( n69116 , n69115 , n2744 );
not ( n69117 , n69115 );
and ( n69118 , n69117 , n68884 );
nor ( n69119 , n69116 , n69118 );
not ( n69120 , n69119 );
or ( n69121 , n69114 , n69120 );
nand ( n69122 , n68843 , n2744 );
nand ( n69123 , n69121 , n69122 );
not ( n69124 , n69123 );
not ( n69125 , n68844 );
nand ( n69126 , n68893 , n68863 );
nand ( n69127 , n68891 , n68858 );
nor ( n69128 , n69126 , n69127 );
not ( n69129 , n68871 );
nor ( n69130 , n68887 , n68848 );
nand ( n69131 , n69128 , n69129 , n69130 );
nor ( n69132 , n68875 , n2758 );
nor ( n69133 , n68920 , n68878 );
nor ( n69134 , n2774 , n2784 );
nor ( n69135 , n2744 , n68851 );
nand ( n69136 , n69132 , n69133 , n69134 , n69135 );
nor ( n69137 , n69131 , n69136 );
buf ( n69138 , n49 );
buf ( n3000 , n48 );
not ( n69140 , n3000 );
not ( n69141 , n69140 );
nor ( n69142 , n69138 , n69141 );
not ( n69143 , n69142 );
not ( n69144 , n69143 );
nand ( n69145 , n69137 , n69144 );
buf ( n69146 , n50 );
not ( n69147 , n69146 );
not ( n69148 , n69147 );
and ( n69149 , n69145 , n69148 );
not ( n69150 , n69145 );
not ( n69151 , n69148 );
and ( n69152 , n69150 , n69151 );
nor ( n69153 , n69149 , n69152 );
not ( n69154 , n69153 );
or ( n69155 , n69125 , n69154 );
nand ( n69156 , n68843 , n69148 );
nand ( n69157 , n69155 , n69156 );
not ( n69158 , n69157 );
and ( n69159 , n69124 , n69158 );
not ( n69160 , n68844 );
not ( n69161 , n69137 );
nor ( n69162 , n69161 , n69141 );
or ( n69163 , n69162 , n69138 );
nand ( n69164 , n69133 , n69134 , n69130 , n69135 );
not ( n69165 , n69164 );
not ( n69166 , n69128 );
not ( n69167 , n69141 );
nand ( n69168 , n69167 , n68999 , n68998 , n69138 );
not ( n69169 , n69132 );
nor ( n69170 , n69166 , n69168 , n69169 );
nand ( n69171 , n69165 , n69170 );
nand ( n69172 , n69163 , n69171 );
not ( n69173 , n69172 );
or ( n69174 , n69160 , n69173 );
nand ( n69175 , n68843 , n69138 );
nand ( n69176 , n69174 , n69175 );
not ( n69177 , n69176 );
not ( n69178 , n69141 );
not ( n69179 , n68843 );
or ( n69180 , n69178 , n69179 );
not ( n69181 , n69141 );
not ( n69182 , n69137 );
or ( n69183 , n69181 , n69182 );
or ( n69184 , n69137 , n69141 );
nand ( n69185 , n69183 , n69184 );
nand ( n69186 , n69185 , n2703 );
nand ( n69187 , n69180 , n69186 );
not ( n69188 , n69187 );
and ( n69189 , n69177 , n69188 );
nand ( n69190 , n69113 , n69159 , n69189 );
not ( n69191 , n69190 );
and ( n69192 , n69031 , n69191 );
not ( n69193 , n69161 );
buf ( n69194 , n57 );
buf ( n69195 , n56 );
nor ( n69196 , n69194 , n69195 );
buf ( n3058 , n58 );
buf ( n3059 , n59 );
nor ( n69199 , n3058 , n3059 );
nand ( n69200 , n69196 , n69199 );
not ( n69201 , n69200 );
buf ( n69202 , n61 );
buf ( n69203 , n60 );
or ( n69204 , n69202 , n69203 );
buf ( n3066 , n62 );
nor ( n69206 , n69204 , n3066 );
nand ( n69207 , n69201 , n69206 );
buf ( n69208 , n53 );
not ( n69209 , n69208 );
not ( n69210 , n69209 );
buf ( n69211 , n51 );
nor ( n69212 , n69210 , n69211 );
buf ( n69213 , n54 );
nor ( n69214 , n69213 , n69141 );
buf ( n69215 , n55 );
nor ( n69216 , n69215 , n69138 );
buf ( n69217 , n52 );
not ( n69218 , n69217 );
not ( n69219 , n69218 );
nor ( n69220 , n69219 , n69148 );
nand ( n69221 , n69212 , n69214 , n69216 , n69220 );
nor ( n69222 , n69207 , n69221 );
nand ( n69223 , n69193 , n69222 );
and ( n69224 , n69223 , n2703 );
not ( n69225 , n69223 );
not ( n69226 , n2703 );
and ( n69227 , n69225 , n69226 );
nor ( n69228 , n69224 , n69227 );
nand ( n69229 , n69228 , n68844 );
not ( n69230 , n69229 );
not ( n69231 , n69230 );
nor ( n69232 , n69192 , n69231 );
not ( n69233 , n69211 );
not ( n69234 , n68843 );
or ( n69235 , n69233 , n69234 );
nor ( n69236 , n69143 , n69148 );
nand ( n69237 , n69137 , n69236 );
xor ( n69238 , n69237 , n69211 );
nand ( n69239 , n69238 , n68844 );
nand ( n69240 , n69235 , n69239 );
not ( n69241 , n69240 );
not ( n69242 , n68911 );
nor ( n69243 , n69148 , n69211 );
nand ( n69244 , n69142 , n69243 );
not ( n69245 , n69244 );
nand ( n69246 , n69245 , n69137 );
and ( n69247 , n69246 , n69219 );
not ( n69248 , n69246 );
not ( n69249 , n69219 );
and ( n69250 , n69248 , n69249 );
nor ( n69251 , n69247 , n69250 );
not ( n69252 , n69251 );
or ( n69253 , n69242 , n69252 );
not ( n69254 , n68844 );
nand ( n69255 , n69254 , n69219 );
nand ( n69256 , n69253 , n69255 );
not ( n69257 , n69256 );
not ( n69258 , n68911 );
nor ( n69259 , n69244 , n69219 );
nand ( n69260 , n69137 , n69259 );
xor ( n69261 , n69260 , n69210 );
not ( n69262 , n69261 );
or ( n69263 , n69258 , n69262 );
nand ( n69264 , n68843 , n69210 );
nand ( n69265 , n69263 , n69264 );
not ( n69266 , n69265 );
not ( n69267 , n68911 );
nor ( n69268 , n69210 , n69219 );
not ( n69269 , n69268 );
nor ( n69270 , n69269 , n69244 );
nand ( n69271 , n69137 , n69270 );
not ( n69272 , n69213 );
xnor ( n69273 , n69271 , n69272 );
not ( n69274 , n69273 );
or ( n69275 , n69267 , n69274 );
nand ( n69276 , n68843 , n69213 );
nand ( n69277 , n69275 , n69276 );
not ( n69278 , n69277 );
and ( n69279 , n69241 , n69257 , n69266 , n69278 );
not ( n69280 , n68844 );
nand ( n69281 , n69268 , n69272 );
nor ( n69282 , n69244 , n69281 );
nand ( n69283 , n69137 , n69282 );
not ( n69284 , n69215 );
xnor ( n69285 , n69283 , n69284 );
not ( n69286 , n69285 );
or ( n69287 , n69280 , n69286 );
nand ( n69288 , n69254 , n69215 );
nand ( n69289 , n69287 , n69288 );
not ( n69290 , n68911 );
nor ( n69291 , n69221 , n69195 );
nand ( n69292 , n69137 , n69291 );
not ( n69293 , n69194 );
xnor ( n69294 , n69292 , n69293 );
not ( n69295 , n69294 );
or ( n69296 , n69290 , n69295 );
nand ( n69297 , n68843 , n69194 );
nand ( n69298 , n69296 , n69297 );
not ( n69299 , n68911 );
not ( n69300 , n69195 );
not ( n69301 , n69300 );
not ( n69302 , n69221 );
nand ( n69303 , n69302 , n69137 );
not ( n69304 , n69303 );
or ( n69305 , n69301 , n69304 );
or ( n69306 , n69303 , n69300 );
nand ( n69307 , n69305 , n69306 );
not ( n69308 , n69307 );
or ( n69309 , n69299 , n69308 );
nand ( n69310 , n68843 , n69195 );
nand ( n69311 , n69309 , n69310 );
or ( n69312 , n69289 , n69298 , n69311 );
not ( n69313 , n68844 );
not ( n69314 , n69196 );
nor ( n69315 , n69314 , n69221 );
nand ( n69316 , n69137 , n69315 );
not ( n69317 , n3058 );
xnor ( n69318 , n69316 , n69317 );
not ( n69319 , n69318 );
not ( n69320 , n69319 );
not ( n69321 , n69320 );
or ( n69322 , n69313 , n69321 );
nand ( n69323 , n68843 , n3058 );
nand ( n69324 , n69322 , n69323 );
nor ( n69325 , n69312 , n69324 );
and ( n69326 , n69279 , n69325 );
nor ( n69327 , n69326 , n69231 );
nor ( n69328 , n69232 , n69327 );
not ( n69329 , n69328 );
not ( n69330 , n3059 );
not ( n69331 , n69254 );
or ( n69332 , n69330 , n69331 );
nand ( n69333 , n69196 , n69317 );
nor ( n69334 , n69221 , n69333 );
nand ( n69335 , n69137 , n69334 );
xor ( n69336 , n69335 , n3059 );
nand ( n69337 , n69336 , n68844 );
nand ( n69338 , n69332 , n69337 );
nand ( n69339 , n69329 , n69338 );
and ( n69340 , n68843 , n69203 );
not ( n69341 , n68843 );
nor ( n69342 , n69221 , n69200 );
nand ( n69343 , n69137 , n69342 );
not ( n69344 , n69203 );
not ( n69345 , n69344 );
and ( n69346 , n69343 , n69345 );
not ( n69347 , n69343 );
and ( n69348 , n69347 , n69344 );
nor ( n69349 , n69346 , n69348 );
and ( n69350 , n69341 , n69349 );
nor ( n69351 , n69340 , n69350 );
not ( n69352 , n69351 );
not ( n69353 , n69352 );
and ( n69354 , n69339 , n69353 );
not ( n69355 , n69339 );
and ( n69356 , n69355 , n69352 );
nor ( n69357 , n69354 , n69356 );
not ( n69358 , n69357 );
not ( n69359 , n69358 );
nand ( n69360 , n69186 , n69009 );
not ( n69361 , n69360 );
not ( n69362 , n68987 );
nand ( n69363 , n69058 , n69024 );
nor ( n69364 , n69362 , n69363 );
nor ( n69365 , n68930 , n69294 );
nand ( n69366 , n69361 , n69364 , n69365 );
nor ( n69367 , n69285 , n2728 );
nand ( n69368 , n69367 , n69319 , n69040 , n68903 );
nor ( n69369 , n69366 , n69368 );
nor ( n69370 , n69307 , n69261 );
nor ( n69371 , n69251 , n69153 );
nand ( n69372 , n69351 , n69337 , n69370 , n69371 );
not ( n69373 , n69372 );
not ( n69374 , n69119 );
nor ( n69375 , n69095 , n69106 );
and ( n69376 , n69082 , n69071 , n69375 );
nand ( n69377 , n69239 , n69374 , n68972 , n69376 );
nor ( n69378 , n68943 , n68957 );
nor ( n69379 , n69273 , n69172 );
nand ( n69380 , n69378 , n69379 );
nor ( n69381 , n69377 , n69380 );
nand ( n69382 , n69369 , n69373 , n69381 );
nand ( n69383 , n69201 , n69344 );
nor ( n69384 , n69383 , n69221 );
nand ( n69385 , n69193 , n69384 );
xor ( n69386 , n69385 , n69202 );
and ( n69387 , n69386 , n68911 );
and ( n69388 , n68843 , n69202 );
nor ( n69389 , n69387 , n69388 );
nor ( n69390 , n69389 , n69229 );
nand ( n69391 , n69382 , n69390 );
not ( n69392 , n69391 );
not ( n69393 , n69204 );
nand ( n69394 , n69393 , n69201 );
nor ( n69395 , n69394 , n69221 );
nand ( n69396 , n69193 , n69395 );
xor ( n69397 , n69396 , n3066 );
nand ( n69398 , n69397 , n68911 );
nand ( n69399 , n68843 , n3066 );
nand ( n69400 , n69398 , n69399 );
not ( n69401 , n69400 );
and ( n69402 , n69392 , n69401 );
and ( n69403 , n69391 , n69400 );
nor ( n69404 , n69402 , n69403 );
not ( n69405 , n69404 );
nand ( n69406 , n69382 , n69230 );
and ( n69407 , n69406 , n69389 );
not ( n69408 , n69406 );
not ( n69409 , n69389 );
and ( n69410 , n69408 , n69409 );
nor ( n69411 , n69407 , n69410 );
not ( n69412 , n69411 );
nand ( n69413 , n69405 , n69412 );
not ( n69414 , n69413 );
buf ( n3276 , n165 );
nand ( n69416 , n69414 , n3276 );
not ( n69417 , n69404 );
nor ( n69418 , n69412 , n69417 );
not ( n69419 , n69418 );
not ( n69420 , n69419 );
buf ( n3282 , n101 );
nand ( n69422 , n69420 , n3282 );
not ( n69423 , n69411 );
not ( n69424 , n69423 );
nand ( n69425 , n69405 , n69424 );
not ( n69426 , n69425 );
buf ( n3288 , n72 );
nand ( n69428 , n69426 , n3288 );
nand ( n69429 , n69404 , n69423 );
not ( n69430 , n69429 );
buf ( n3292 , n133 );
not ( n69432 , n3292 );
not ( n69433 , n69432 );
nand ( n69434 , n69430 , n69433 );
nand ( n69435 , n69416 , n69422 , n69428 , n69434 );
not ( n69436 , n69413 );
buf ( n69437 , n162 );
nand ( n69438 , n69436 , n69437 );
not ( n69439 , n69419 );
buf ( n3301 , n98 );
nand ( n69441 , n69439 , n3301 );
not ( n69442 , n69425 );
buf ( n3304 , n69 );
nand ( n69444 , n69442 , n3304 );
nand ( n69445 , n69404 , n69412 );
not ( n69446 , n69445 );
buf ( n69447 , n130 );
not ( n69448 , n69447 );
not ( n69449 , n69448 );
nand ( n69450 , n69446 , n69449 );
nand ( n69451 , n69438 , n69441 , n69444 , n69450 );
nand ( n69452 , n69435 , n69451 );
not ( n69453 , n69404 );
nor ( n69454 , n69453 , n69412 );
buf ( n3316 , n102 );
nand ( n69456 , n69454 , n3316 );
nand ( n69457 , n69417 , n69423 );
not ( n69458 , n69457 );
buf ( n3320 , n166 );
nand ( n69460 , n69458 , n3320 );
nand ( n69461 , n69424 , n69453 );
not ( n69462 , n69461 );
buf ( n3324 , n73 );
nand ( n69464 , n69462 , n3324 );
not ( n69465 , n69429 );
buf ( n3327 , n134 );
not ( n69467 , n3327 );
not ( n69468 , n69467 );
nand ( n69469 , n69465 , n69468 );
nand ( n69470 , n69456 , n69460 , n69464 , n69469 );
not ( n69471 , n69461 );
nand ( n69472 , n69470 , n69471 );
nor ( n69473 , n69452 , n69472 );
not ( n69474 , n69445 );
buf ( n3336 , n131 );
not ( n69476 , n3336 );
not ( n69477 , n69476 );
nand ( n69478 , n69474 , n69477 );
not ( n69479 , n69418 );
not ( n69480 , n69479 );
buf ( n3342 , n99 );
nand ( n69482 , n69480 , n3342 );
buf ( n3344 , n70 );
nand ( n69484 , n69426 , n3344 );
buf ( n3346 , n163 );
nand ( n69486 , n69414 , n3346 );
nand ( n69487 , n69478 , n69482 , n69484 , n69486 );
not ( n69488 , n69413 );
buf ( n3350 , n164 );
nand ( n69490 , n69488 , n3350 );
not ( n69491 , n69479 );
buf ( n69492 , n100 );
nand ( n69493 , n69491 , n69492 );
not ( n69494 , n69425 );
buf ( n3356 , n71 );
nand ( n69496 , n69494 , n3356 );
not ( n69497 , n69445 );
buf ( n3359 , n132 );
not ( n69499 , n3359 );
not ( n69500 , n69499 );
nand ( n69501 , n69497 , n69500 );
nand ( n69502 , n69490 , n69493 , n69496 , n69501 );
and ( n69503 , n69487 , n69502 );
nand ( n69504 , n69473 , n69503 );
not ( n69505 , n69504 );
not ( n69506 , n69457 );
buf ( n69507 , n170 );
nand ( n69508 , n69506 , n69507 );
buf ( n69509 , n106 );
nand ( n69510 , n69454 , n69509 );
not ( n69511 , n69461 );
buf ( n69512 , n77 );
nand ( n69513 , n69511 , n69512 );
not ( n69514 , n69429 );
buf ( n69515 , n138 );
not ( n69516 , n69515 );
not ( n69517 , n69516 );
nand ( n69518 , n69514 , n69517 );
nand ( n69519 , n69508 , n69510 , n69513 , n69518 );
buf ( n69520 , n76 );
nand ( n69521 , n69511 , n69520 );
buf ( n69522 , n169 );
nand ( n69523 , n69506 , n69522 );
buf ( n69524 , n105 );
nand ( n69525 , n69454 , n69524 );
not ( n69526 , n69429 );
buf ( n69527 , n137 );
not ( n69528 , n69527 );
not ( n69529 , n69528 );
nand ( n69530 , n69526 , n69529 );
nand ( n69531 , n69521 , n69523 , n69525 , n69530 );
nand ( n69532 , n69519 , n69531 );
buf ( n69533 , n168 );
nand ( n69534 , n69458 , n69533 );
buf ( n69535 , n104 );
nand ( n69536 , n69454 , n69535 );
buf ( n69537 , n75 );
nand ( n69538 , n69462 , n69537 );
buf ( n69539 , n136 );
not ( n69540 , n69539 );
not ( n69541 , n69540 );
nand ( n69542 , n69430 , n69541 );
nand ( n69543 , n69534 , n69536 , n69538 , n69542 );
buf ( n3405 , n167 );
nand ( n69545 , n69458 , n3405 );
buf ( n69546 , n103 );
nand ( n69547 , n69454 , n69546 );
not ( n69548 , n69461 );
buf ( n69549 , n74 );
nand ( n69550 , n69548 , n69549 );
buf ( n3412 , n135 );
nand ( n69552 , n69430 , n3412 );
nand ( n69553 , n69545 , n69547 , n69550 , n69552 );
nand ( n69554 , n69543 , n69553 );
nor ( n69555 , n69532 , n69554 );
not ( n69556 , n69457 );
not ( n69557 , n69556 );
buf ( n69558 , n172 );
not ( n69559 , n69558 );
nor ( n69560 , n69557 , n69559 );
not ( n69561 , n69454 );
buf ( n69562 , n108 );
not ( n69563 , n69562 );
nor ( n69564 , n69561 , n69563 );
nor ( n69565 , n69560 , n69564 );
not ( n69566 , n69461 );
buf ( n69567 , n79 );
and ( n69568 , n69566 , n69567 );
not ( n69569 , n69430 );
buf ( n69570 , n140 );
not ( n69571 , n69570 );
not ( n69572 , n69571 );
not ( n69573 , n69572 );
nor ( n69574 , n69569 , n69573 );
nor ( n69575 , n69568 , n69574 );
nand ( n69576 , n69565 , n69575 );
buf ( n69577 , n171 );
nand ( n69578 , n69506 , n69577 );
buf ( n69579 , n107 );
nand ( n69580 , n69454 , n69579 );
buf ( n3442 , n78 );
nand ( n69582 , n69511 , n3442 );
buf ( n69583 , n139 );
not ( n69584 , n69583 );
not ( n69585 , n69584 );
nand ( n69586 , n69526 , n69585 );
nand ( n69587 , n69578 , n69580 , n69582 , n69586 );
nand ( n69588 , n69576 , n69587 );
buf ( n3450 , n173 );
nand ( n69590 , n69556 , n3450 );
buf ( n69591 , n109 );
nand ( n69592 , n69454 , n69591 );
buf ( n3454 , n80 );
nand ( n69594 , n69426 , n3454 );
buf ( n69595 , n141 );
not ( n69596 , n69595 );
not ( n69597 , n69596 );
nand ( n69598 , n69474 , n69597 );
nand ( n69599 , n69590 , n69592 , n69594 , n69598 );
not ( n69600 , n69599 );
nor ( n69601 , n69588 , n69600 );
nand ( n69602 , n69505 , n69555 , n69601 );
buf ( n69603 , n81 );
nand ( n69604 , n69471 , n69603 );
buf ( n3466 , n174 );
nand ( n69606 , n69414 , n3466 );
buf ( n69607 , n110 );
nand ( n69608 , n69420 , n69607 );
buf ( n3470 , n142 );
not ( n69610 , n3470 );
not ( n69611 , n69610 );
nand ( n69612 , n69474 , n69611 );
nand ( n69613 , n69604 , n69606 , n69608 , n69612 );
not ( n69614 , n69613 );
and ( n69615 , n69602 , n69614 );
not ( n69616 , n69602 );
and ( n69617 , n69616 , n69613 );
nor ( n69618 , n69615 , n69617 );
not ( n69619 , n69618 );
not ( n69620 , n69619 );
and ( n69621 , n69359 , n69620 );
not ( n69622 , n69359 );
nand ( n69623 , n69502 , n69553 , n69487 , n69543 );
nor ( n69624 , n69623 , n69588 );
nand ( n69625 , n69613 , n69599 );
nor ( n69626 , n69532 , n69625 );
and ( n69627 , n69624 , n69626 , n69473 );
buf ( n3489 , n143 );
not ( n69629 , n3489 );
not ( n69630 , n69629 );
nand ( n69631 , n69526 , n69630 );
not ( n69632 , n69458 );
not ( n69633 , n69632 );
nand ( n69634 , n69633 , n2697 );
not ( n69635 , n69454 );
not ( n69636 , n69635 );
buf ( n3498 , n111 );
nand ( n69638 , n69636 , n3498 );
buf ( n69639 , n82 );
nand ( n69640 , n69471 , n69639 );
nand ( n69641 , n69631 , n69634 , n69638 , n69640 );
nand ( n69642 , n69627 , n69641 );
buf ( n69643 , n144 );
not ( n69644 , n69643 );
not ( n69645 , n69644 );
nand ( n69646 , n69526 , n69645 );
not ( n69647 , n69454 );
not ( n69648 , n69647 );
buf ( n3510 , n112 );
nand ( n69650 , n69648 , n3510 );
buf ( n69651 , n176 );
nand ( n69652 , n69633 , n69651 );
buf ( n3514 , n83 );
nand ( n69654 , n69471 , n3514 );
nand ( n69655 , n69646 , n69650 , n69652 , n69654 );
not ( n69656 , n69655 );
and ( n69657 , n69642 , n69656 );
not ( n69658 , n69642 );
and ( n69659 , n69658 , n69655 );
nor ( n69660 , n69657 , n69659 );
not ( n69661 , n69660 );
not ( n69662 , n69561 );
buf ( n69663 , n121 );
not ( n69664 , n69663 );
not ( n69665 , n69664 );
and ( n69666 , n69662 , n69665 );
not ( n69667 , n69506 );
buf ( n3529 , n185 );
not ( n69669 , n3529 );
not ( n69670 , n69669 );
not ( n69671 , n69670 );
nor ( n69672 , n69667 , n69671 );
nor ( n69673 , n69666 , n69672 );
buf ( n69674 , n92 );
not ( n69675 , n69674 );
not ( n69676 , n69675 );
and ( n69677 , n69566 , n69676 );
not ( n69678 , n69430 );
buf ( n69679 , n153 );
not ( n69680 , n69679 );
not ( n69681 , n69680 );
not ( n69682 , n69681 );
nor ( n69683 , n69678 , n69682 );
nor ( n69684 , n69677 , n69683 );
nand ( n69685 , n69673 , n69684 );
buf ( n69686 , n186 );
not ( n69687 , n69686 );
not ( n69688 , n69687 );
not ( n69689 , n69688 );
nor ( n69690 , n69457 , n69689 );
buf ( n3552 , n122 );
not ( n69692 , n3552 );
not ( n69693 , n69692 );
not ( n69694 , n69693 );
nor ( n69695 , n69561 , n69694 );
nor ( n69696 , n69690 , n69695 );
buf ( n69697 , n154 );
not ( n69698 , n69697 );
nor ( n69699 , n69569 , n69698 );
buf ( n3561 , n93 );
not ( n69701 , n3561 );
not ( n69702 , n69701 );
not ( n69703 , n69702 );
nor ( n69704 , n69461 , n69703 );
nor ( n69705 , n69699 , n69704 );
nand ( n69706 , n69696 , n69705 );
nand ( n69707 , n69685 , n69706 );
buf ( n3569 , n187 );
not ( n69709 , n3569 );
not ( n69710 , n69709 );
not ( n69711 , n69710 );
nor ( n69712 , n69457 , n69711 );
buf ( n69713 , n123 );
not ( n69714 , n69713 );
not ( n69715 , n69714 );
not ( n69716 , n69715 );
nor ( n69717 , n69561 , n69716 );
nor ( n69718 , n69712 , n69717 );
buf ( n3580 , n94 );
not ( n69720 , n3580 );
not ( n69721 , n69720 );
and ( n69722 , n69566 , n69721 );
buf ( n3584 , n155 );
not ( n69724 , n3584 );
not ( n69725 , n69724 );
not ( n69726 , n69725 );
nor ( n69727 , n69678 , n69726 );
nor ( n69728 , n69722 , n69727 );
nand ( n69729 , n69718 , n69728 );
buf ( n3591 , n156 );
not ( n69731 , n3591 );
not ( n69732 , n69731 );
nand ( n69733 , n69526 , n69732 );
not ( n69734 , n69561 );
buf ( n69735 , n124 );
not ( n69736 , n69735 );
not ( n69737 , n69736 );
nand ( n69738 , n69734 , n69737 );
buf ( n69739 , n188 );
not ( n69740 , n69739 );
not ( n69741 , n69740 );
nand ( n69742 , n69506 , n69741 );
nand ( n69743 , n69733 , n69738 , n69742 );
nand ( n69744 , n69729 , n69743 );
nor ( n69745 , n69707 , n69744 );
not ( n69746 , n69557 );
buf ( n69747 , n182 );
not ( n69748 , n69747 );
not ( n69749 , n69748 );
not ( n69750 , n69749 );
not ( n69751 , n69750 );
and ( n69752 , n69746 , n69751 );
buf ( n69753 , n118 );
not ( n69754 , n69753 );
not ( n69755 , n69754 );
and ( n69756 , n69636 , n69755 );
nor ( n69757 , n69752 , n69756 );
not ( n69758 , n69429 );
buf ( n3620 , n150 );
not ( n69760 , n3620 );
not ( n69761 , n69760 );
not ( n69762 , n69761 );
not ( n69763 , n69762 );
and ( n69764 , n69758 , n69763 );
not ( n69765 , n69461 );
buf ( n69766 , n89 );
and ( n69767 , n69765 , n69766 );
nor ( n69768 , n69764 , n69767 );
nand ( n69769 , n69757 , n69768 );
buf ( n69770 , n88 );
not ( n69771 , n69770 );
not ( n69772 , n69771 );
not ( n69773 , n69772 );
nor ( n69774 , n69461 , n69773 );
buf ( n3636 , n117 );
not ( n69776 , n3636 );
not ( n69777 , n69776 );
not ( n69778 , n69777 );
nor ( n69779 , n69647 , n69778 );
nor ( n69780 , n69774 , n69779 );
buf ( n69781 , n181 );
not ( n69782 , n69781 );
not ( n69783 , n69782 );
not ( n69784 , n69783 );
nor ( n69785 , n69457 , n69784 );
buf ( n69786 , n149 );
not ( n69787 , n69786 );
not ( n69788 , n69787 );
not ( n69789 , n69788 );
nor ( n69790 , n69429 , n69789 );
nor ( n69791 , n69785 , n69790 );
nand ( n69792 , n69780 , n69791 );
nand ( n69793 , n69769 , n69792 );
buf ( n69794 , n146 );
not ( n69795 , n69794 );
not ( n69796 , n69795 );
nand ( n69797 , n69430 , n69796 );
buf ( n69798 , n178 );
nand ( n69799 , n69556 , n69798 );
buf ( n69800 , n114 );
nand ( n69801 , n69636 , n69800 );
buf ( n69802 , n85 );
nand ( n69803 , n69566 , n69802 );
nand ( n69804 , n69797 , n69799 , n69801 , n69803 );
not ( n69805 , n69632 );
buf ( n69806 , n177 );
not ( n69807 , n69806 );
not ( n69808 , n69807 );
and ( n69809 , n69805 , n69808 );
buf ( n69810 , n113 );
and ( n69811 , n69648 , n69810 );
nor ( n69812 , n69809 , n69811 );
buf ( n69813 , n145 );
not ( n69814 , n69813 );
not ( n69815 , n69814 );
not ( n69816 , n69815 );
nor ( n69817 , n69429 , n69816 );
buf ( n69818 , n84 );
not ( n69819 , n69818 );
nor ( n69820 , n69461 , n69819 );
nor ( n69821 , n69817 , n69820 );
nand ( n69822 , n69812 , n69821 );
nand ( n69823 , n69804 , n69822 );
nor ( n69824 , n69793 , n69823 );
nand ( n69825 , n69745 , n69824 );
nand ( n69826 , n69655 , n69641 );
not ( n69827 , n69826 );
not ( n69828 , n69457 );
buf ( n69829 , n184 );
not ( n69830 , n69829 );
not ( n69831 , n69830 );
not ( n69832 , n69831 );
not ( n69833 , n69832 );
and ( n69834 , n69828 , n69833 );
buf ( n69835 , n120 );
not ( n69836 , n69835 );
not ( n69837 , n69836 );
and ( n69838 , n69662 , n69837 );
nor ( n69839 , n69834 , n69838 );
buf ( n69840 , n152 );
not ( n69841 , n69840 );
not ( n69842 , n69841 );
not ( n69843 , n69842 );
nor ( n69844 , n69569 , n69843 );
not ( n69845 , n69566 );
buf ( n3707 , n91 );
not ( n69847 , n3707 );
nor ( n69848 , n69845 , n69847 );
nor ( n69849 , n69844 , n69848 );
nand ( n69850 , n69839 , n69849 );
buf ( n69851 , n86 );
not ( n69852 , n69851 );
nor ( n69853 , n69461 , n69852 );
buf ( n69854 , n115 );
not ( n69855 , n69854 );
not ( n69856 , n69855 );
not ( n69857 , n69856 );
nor ( n69858 , n69635 , n69857 );
nor ( n69859 , n69853 , n69858 );
buf ( n3721 , n179 );
not ( n69861 , n3721 );
not ( n69862 , n69861 );
not ( n69863 , n69862 );
nor ( n69864 , n69457 , n69863 );
buf ( n69865 , n147 );
not ( n69866 , n69865 );
not ( n69867 , n69866 );
not ( n69868 , n69867 );
nor ( n69869 , n69429 , n69868 );
nor ( n69870 , n69864 , n69869 );
nand ( n69871 , n69859 , n69870 );
and ( n69872 , n69850 , n69871 );
not ( n69873 , n69457 );
buf ( n69874 , n180 );
not ( n69875 , n69874 );
not ( n69876 , n69875 );
not ( n69877 , n69876 );
not ( n69878 , n69877 );
and ( n69879 , n69873 , n69878 );
buf ( n69880 , n116 );
not ( n69881 , n69880 );
not ( n69882 , n69881 );
and ( n69883 , n69636 , n69882 );
nor ( n69884 , n69879 , n69883 );
buf ( n69885 , n87 );
not ( n69886 , n69885 );
not ( n69887 , n69886 );
not ( n69888 , n69887 );
nor ( n69889 , n69461 , n69888 );
buf ( n69890 , n148 );
not ( n69891 , n69890 );
not ( n69892 , n69891 );
not ( n69893 , n69892 );
nor ( n69894 , n69429 , n69893 );
nor ( n69895 , n69889 , n69894 );
nand ( n69896 , n69884 , n69895 );
buf ( n69897 , n125 );
not ( n69898 , n69897 );
not ( n69899 , n69898 );
nand ( n69900 , n69662 , n69899 );
not ( n69901 , n69457 );
buf ( n69902 , n189 );
nand ( n69903 , n69901 , n69902 );
buf ( n69904 , n157 );
not ( n69905 , n69904 );
not ( n69906 , n69905 );
nand ( n69907 , n69526 , n69906 );
nand ( n69908 , n69900 , n69903 , n69907 );
and ( n69909 , n69896 , n69908 );
buf ( n3771 , n119 );
not ( n69911 , n3771 );
not ( n69912 , n69911 );
and ( n69913 , n69734 , n69912 );
buf ( n69914 , n183 );
not ( n69915 , n69914 );
not ( n69916 , n69915 );
not ( n69917 , n69916 );
nor ( n69918 , n69667 , n69917 );
nor ( n69919 , n69913 , n69918 );
not ( n69920 , n69526 );
buf ( n69921 , n151 );
not ( n69922 , n69921 );
not ( n69923 , n69922 );
not ( n69924 , n69923 );
nor ( n69925 , n69920 , n69924 );
buf ( n69926 , n90 );
not ( n69927 , n69926 );
not ( n69928 , n69927 );
not ( n69929 , n69928 );
nor ( n69930 , n69461 , n69929 );
nor ( n69931 , n69925 , n69930 );
nand ( n69932 , n69919 , n69931 );
nand ( n69933 , n69827 , n69872 , n69909 , n69932 );
nor ( n69934 , n69825 , n69933 );
nand ( n69935 , n69627 , n69934 );
buf ( n69936 , n126 );
nand ( n69937 , n69734 , n69936 );
buf ( n3799 , n158 );
nand ( n69939 , n69526 , n3799 );
buf ( n69940 , n190 );
nand ( n69941 , n69506 , n69940 );
nand ( n69942 , n69937 , n69939 , n69941 );
not ( n69943 , n69942 );
and ( n69944 , n69935 , n69943 );
not ( n69945 , n69935 );
and ( n69946 , n69945 , n69942 );
nor ( n69947 , n69944 , n69946 );
buf ( n69948 , n66 );
not ( n69949 , n69948 );
not ( n69950 , n69949 );
not ( n69951 , n69950 );
not ( n69952 , n69471 );
or ( n69953 , n69951 , n69952 );
buf ( n3815 , n159 );
nand ( n69955 , n69901 , n3815 );
nand ( n69956 , n69953 , n69955 );
buf ( n69957 , n95 );
not ( n69958 , n69957 );
not ( n69959 , n69636 );
or ( n69960 , n69958 , n69959 );
buf ( n69961 , n127 );
not ( n69962 , n69961 );
not ( n69963 , n69962 );
nand ( n69964 , n69430 , n69963 );
nand ( n69965 , n69960 , n69964 );
nor ( n69966 , n69956 , n69965 );
not ( n69967 , n69966 );
nand ( n69968 , n69947 , n69967 );
not ( n69969 , n69968 );
not ( n69970 , n69969 );
not ( n69971 , n69970 );
not ( n69972 , n69641 );
not ( n69973 , n69627 );
not ( n69974 , n69973 );
or ( n69975 , n69972 , n69974 );
or ( n69976 , n69973 , n69641 );
nand ( n69977 , n69975 , n69976 );
not ( n69978 , n69977 );
not ( n69979 , n69588 );
nand ( n69980 , n69979 , n69505 , n69555 );
xor ( n69981 , n69980 , n69600 );
nand ( n69982 , n69618 , n69981 );
nor ( n69983 , n69978 , n69982 );
not ( n69984 , n69983 );
nand ( n69985 , n69505 , n69555 );
not ( n69986 , n69587 );
and ( n69987 , n69985 , n69986 );
not ( n69988 , n69985 );
and ( n69989 , n69988 , n69587 );
nor ( n69990 , n69987 , n69989 );
not ( n69991 , n69554 );
not ( n69992 , n69991 );
not ( n69993 , n69531 );
nor ( n69994 , n69992 , n69993 );
nand ( n69995 , n69505 , n69994 );
not ( n69996 , n69519 );
and ( n69997 , n69995 , n69996 );
not ( n69998 , n69995 );
and ( n69999 , n69998 , n69519 );
nor ( n70000 , n69997 , n69999 );
nand ( n70001 , n69990 , n70000 );
nand ( n70002 , n69505 , n69553 );
not ( n70003 , n69543 );
and ( n70004 , n70002 , n70003 );
not ( n70005 , n70002 );
and ( n70006 , n70005 , n69543 );
nor ( n70007 , n70004 , n70006 );
nand ( n70008 , n69505 , n69991 );
not ( n70009 , n69531 );
and ( n70010 , n70008 , n70009 );
not ( n70011 , n70008 );
and ( n70012 , n70011 , n69531 );
nor ( n70013 , n70010 , n70012 );
and ( n70014 , n70007 , n70013 );
not ( n70015 , n70014 );
nor ( n70016 , n70001 , n70015 );
nand ( n70017 , n69451 , n69471 );
not ( n70018 , n69487 );
or ( n70019 , n70017 , n70018 );
not ( n70020 , n69502 );
and ( n70021 , n70019 , n70020 );
not ( n70022 , n70019 );
and ( n70023 , n70022 , n69502 );
nor ( n70024 , n70021 , n70023 );
not ( n70025 , n69503 );
or ( n70026 , n70017 , n70025 );
not ( n70027 , n69435 );
and ( n70028 , n70026 , n70027 );
not ( n70029 , n70026 );
and ( n70030 , n70029 , n69435 );
nor ( n70031 , n70028 , n70030 );
nand ( n70032 , n70024 , n70031 );
not ( n70033 , n69487 );
nand ( n70034 , n69451 , n69471 );
not ( n70035 , n70034 );
or ( n70036 , n70033 , n70035 );
or ( n70037 , n70034 , n69487 );
nand ( n70038 , n70036 , n70037 );
or ( n70039 , n69451 , n69471 );
and ( n70040 , n70034 , n70039 );
buf ( n70041 , n67 );
nand ( n70042 , n69471 , n70041 );
buf ( n70043 , n128 );
not ( n70044 , n70043 );
not ( n70045 , n70044 );
nand ( n70046 , n69430 , n70045 );
buf ( n70047 , n96 );
not ( n70048 , n70047 );
not ( n70049 , n70048 );
nand ( n70050 , n69636 , n70049 );
buf ( n70051 , n160 );
nand ( n70052 , n69901 , n70051 );
nand ( n70053 , n70042 , n70046 , n70050 , n70052 );
buf ( n3915 , n68 );
not ( n70055 , n3915 );
not ( n70056 , n69471 );
or ( n70057 , n70055 , n70056 );
buf ( n70058 , n161 );
nand ( n70059 , n69901 , n70058 );
nand ( n70060 , n70057 , n70059 );
buf ( n70061 , n129 );
not ( n70062 , n70061 );
not ( n70063 , n70062 );
not ( n70064 , n70063 );
not ( n70065 , n69430 );
or ( n70066 , n70064 , n70065 );
buf ( n70067 , n97 );
not ( n70068 , n70067 );
not ( n70069 , n70068 );
nand ( n70070 , n69636 , n70069 );
nand ( n70071 , n70066 , n70070 );
nor ( n70072 , n70060 , n70071 );
not ( n70073 , n70072 );
and ( n70074 , n70053 , n70073 );
nand ( n70075 , n70038 , n70040 , n70074 );
nor ( n70076 , n70032 , n70075 );
not ( n70077 , n69553 );
not ( n70078 , n69505 );
not ( n70079 , n70078 );
or ( n70080 , n70077 , n70079 );
or ( n70081 , n70078 , n69553 );
nand ( n70082 , n70080 , n70081 );
not ( n70083 , n69470 );
not ( n70084 , n70034 );
nor ( n70085 , n70025 , n70027 );
nand ( n70086 , n70084 , n70085 );
not ( n70087 , n70086 );
or ( n70088 , n70083 , n70087 );
or ( n70089 , n70086 , n69470 );
nand ( n70090 , n70088 , n70089 );
nand ( n70091 , n70076 , n70082 , n70090 );
not ( n70092 , n70091 );
nand ( n70093 , n69505 , n69555 , n69587 );
not ( n70094 , n69576 );
and ( n70095 , n70093 , n70094 );
not ( n70096 , n70093 );
and ( n70097 , n70096 , n69576 );
nor ( n70098 , n70095 , n70097 );
nand ( n70099 , n70016 , n70092 , n70098 );
not ( n70100 , n70099 );
not ( n70101 , n70100 );
nor ( n70102 , n69984 , n70101 );
nand ( n70103 , n69971 , n70102 );
not ( n70104 , n70103 );
or ( n70105 , n69661 , n70104 );
or ( n70106 , n70103 , n69660 );
nand ( n70107 , n70105 , n70106 );
and ( n70108 , n69622 , n70107 );
nor ( n70109 , n69621 , n70108 );
not ( n70110 , n69298 );
not ( n70111 , n69289 );
not ( n70112 , n69230 );
or ( n70113 , n70111 , n70112 );
not ( n70114 , n69030 );
not ( n70115 , n69190 );
and ( n70116 , n70114 , n70115 );
nor ( n70117 , n70116 , n69231 );
nor ( n70118 , n69279 , n69231 );
nor ( n70119 , n70117 , n70118 );
nand ( n70120 , n70113 , n70119 );
nand ( n70121 , n70120 , n69311 );
nor ( n70122 , n70110 , n70121 );
xor ( n70123 , n70122 , n69324 );
not ( n70124 , n70121 );
not ( n70125 , n69298 );
and ( n70126 , n70124 , n70125 );
and ( n70127 , n70121 , n69298 );
nor ( n70128 , n70126 , n70127 );
and ( n70129 , n70120 , n69311 );
not ( n70130 , n70120 );
not ( n70131 , n69311 );
and ( n70132 , n70130 , n70131 );
nor ( n70133 , n70129 , n70132 );
not ( n70134 , n70133 );
nor ( n70135 , n70128 , n70134 );
nand ( n70136 , n70123 , n70135 );
buf ( n70137 , DFF_state_reg_Q);
not ( n70138 , n70137 );
not ( n70139 , n70138 );
and ( n70140 , n70136 , n70139 );
not ( n70141 , n70140 );
not ( n70142 , n70119 );
not ( n70143 , n69289 );
and ( n70144 , n70142 , n70143 );
and ( n70145 , n70119 , n69289 );
nor ( n70146 , n70144 , n70145 );
not ( n70147 , n70146 );
nor ( n70148 , n70141 , n70147 );
not ( n70149 , n70128 );
not ( n70150 , n70149 );
buf ( n70151 , DFF_B_reg_Q);
not ( n70152 , n70151 );
nand ( n70153 , n70150 , n70152 );
not ( n70154 , n70153 );
not ( n70155 , n70123 );
or ( n70156 , n70154 , n70155 );
nand ( n70157 , n70156 , n70133 );
not ( n70158 , n70133 );
nand ( n70159 , n70158 , n70151 );
nor ( n70160 , n70149 , n70159 );
buf ( n70161 , n64 );
or ( n70162 , n70160 , n70161 );
nand ( n70163 , n70162 , n70123 );
nand ( n70164 , n70157 , n70163 );
not ( n70165 , n70149 );
not ( n70166 , n70123 );
not ( n70167 , n70166 );
or ( n70168 , n70165 , n70167 );
buf ( n70169 , n65 );
not ( n70170 , n70169 );
not ( n70171 , n70170 );
nand ( n70172 , n70133 , n70152 );
not ( n70173 , n70172 );
not ( n70174 , n70159 );
or ( n70175 , n70173 , n70174 );
nand ( n70176 , n70175 , n70150 );
not ( n70177 , n70176 );
or ( n70178 , n70171 , n70177 );
nand ( n70179 , n70178 , n70123 );
nand ( n70180 , n70168 , n70179 );
not ( n70181 , n70180 );
nor ( n70182 , n70164 , n70181 );
nand ( n70183 , n70148 , n70182 );
not ( n70184 , n69241 );
nand ( n70185 , n70117 , n70184 );
nor ( n70186 , n70185 , n69257 );
nand ( n70187 , n70186 , n69265 );
xor ( n70188 , n70187 , n69278 );
not ( n70189 , n69265 );
nor ( n70190 , n70189 , n70186 );
not ( n70191 , n70190 );
not ( n70192 , n69265 );
nand ( n70193 , n70192 , n70186 );
nand ( n70194 , n70191 , n70193 );
nand ( n70195 , n70188 , n70194 );
not ( n70196 , n70195 );
not ( n70197 , n69257 );
not ( n70198 , n70197 );
not ( n70199 , n70185 );
or ( n70200 , n70198 , n70199 );
or ( n70201 , n70185 , n70197 );
nand ( n70202 , n70200 , n70201 );
and ( n70203 , n70117 , n70184 );
not ( n70204 , n70117 );
and ( n70205 , n70204 , n69241 );
nor ( n70206 , n70203 , n70205 );
nor ( n70207 , n70202 , n70206 );
nand ( n70208 , n70196 , n70207 );
nor ( n70209 , n70183 , n70208 );
not ( n70210 , n70209 );
or ( n70211 , n70109 , n70210 );
not ( n70212 , n69641 );
not ( n70213 , n69328 );
not ( n70214 , n69338 );
and ( n70215 , n70213 , n70214 );
and ( n70216 , n69328 , n69338 );
nor ( n70217 , n70215 , n70216 );
and ( n70218 , n69338 , n69353 );
not ( n70219 , n69338 );
and ( n70220 , n70219 , n69352 );
nor ( n70221 , n70218 , n70220 );
nand ( n70222 , n70217 , n70221 );
or ( n70223 , n70222 , n69188 );
nand ( n70224 , n70222 , n68651 );
nand ( n70225 , n70223 , n70224 );
not ( n70226 , n70225 );
or ( n70227 , n70212 , n70226 );
not ( n70228 , n69641 );
not ( n70229 , n70225 );
nand ( n70230 , n70228 , n70229 );
nand ( n70231 , n70227 , n70230 );
not ( n70232 , n70222 );
not ( n70233 , n68934 );
not ( n70234 , n70233 );
and ( n70235 , n70232 , n70234 );
and ( n70236 , n70222 , n2513 );
nor ( n70237 , n70235 , n70236 );
not ( n70238 , n70237 );
not ( n70239 , n70238 );
and ( n70240 , n70239 , n69613 );
nor ( n70241 , n70231 , n70240 );
not ( n70242 , n70241 );
nand ( n70243 , n70231 , n70240 );
nand ( n70244 , n70242 , n70243 );
not ( n70245 , n70244 );
not ( n70246 , n69531 );
not ( n70247 , n70222 );
not ( n70248 , n69045 );
not ( n70249 , n70248 );
and ( n70250 , n70247 , n70249 );
and ( n70251 , n70222 , n2518 );
nor ( n70252 , n70250 , n70251 );
not ( n70253 , n70252 );
not ( n70254 , n70253 );
or ( n70255 , n70246 , n70254 );
not ( n70256 , n70253 );
not ( n70257 , n69531 );
nand ( n70258 , n70256 , n70257 );
nand ( n70259 , n70255 , n70258 );
nor ( n70260 , n70222 , n69124 );
not ( n70261 , n70260 );
nand ( n70262 , n70222 , n2519 );
nand ( n70263 , n70261 , n70262 );
not ( n70264 , n70263 );
and ( n70265 , n69543 , n70264 );
and ( n70266 , n70259 , n70265 );
not ( n70267 , n70266 );
not ( n70268 , n70222 );
not ( n70269 , n68978 );
and ( n70270 , n70268 , n70269 );
and ( n70271 , n70222 , n2517 );
nor ( n70272 , n70270 , n70271 );
not ( n70273 , n70272 );
not ( n70274 , n70273 );
not ( n70275 , n69519 );
or ( n70276 , n70274 , n70275 );
not ( n70277 , n70273 );
not ( n70278 , n69519 );
nand ( n70279 , n70277 , n70278 );
nand ( n70280 , n70276 , n70279 );
nor ( n70281 , n70253 , n70257 );
nor ( n70282 , n70280 , n70281 );
not ( n70283 , n70282 );
not ( n70284 , n70283 );
or ( n70285 , n70267 , n70284 );
nand ( n70286 , n70280 , n70281 );
nand ( n70287 , n70285 , n70286 );
not ( n70288 , n70287 );
not ( n70289 , n69576 );
not ( n70290 , n70289 );
not ( n70291 , n70222 );
not ( n70292 , n68948 );
and ( n70293 , n70291 , n70292 );
and ( n70294 , n70222 , n2515 );
nor ( n70295 , n70293 , n70294 );
not ( n70296 , n70295 );
not ( n70297 , n70296 );
not ( n70298 , n70297 );
or ( n70299 , n70290 , n70298 );
nand ( n70300 , n69576 , n70296 );
nand ( n70301 , n70299 , n70300 );
not ( n70302 , n69587 );
not ( n70303 , n70222 );
not ( n70304 , n68909 );
and ( n70305 , n70303 , n70304 );
and ( n70306 , n70222 , n2516 );
nor ( n70307 , n70305 , n70306 );
not ( n70308 , n70307 );
nor ( n70309 , n70302 , n70308 );
nor ( n70310 , n70301 , n70309 );
not ( n70311 , n69587 );
not ( n70312 , n70308 );
or ( n70313 , n70311 , n70312 );
not ( n70314 , n70308 );
not ( n70315 , n69587 );
nand ( n70316 , n70314 , n70315 );
nand ( n70317 , n70313 , n70316 );
nand ( n70318 , n69519 , n70277 );
not ( n70319 , n70318 );
nor ( n70320 , n70317 , n70319 );
nor ( n70321 , n70310 , n70320 );
not ( n70322 , n69599 );
not ( n70323 , n68961 );
nor ( n70324 , n70222 , n70323 );
not ( n70325 , n70324 );
nand ( n70326 , n70222 , n2514 );
nand ( n70327 , n70325 , n70326 );
not ( n70328 , n70327 );
or ( n70329 , n70322 , n70328 );
not ( n70330 , n69599 );
not ( n70331 , n70327 );
nand ( n70332 , n70330 , n70331 );
nand ( n70333 , n70329 , n70332 );
not ( n70334 , n69576 );
nor ( n70335 , n70334 , n70296 );
nor ( n70336 , n70333 , n70335 );
not ( n70337 , n69613 );
not ( n70338 , n70238 );
or ( n70339 , n70337 , n70338 );
not ( n70340 , n69613 );
nand ( n70341 , n70340 , n70239 );
nand ( n70342 , n70339 , n70341 );
nand ( n70343 , n70331 , n69599 );
not ( n70344 , n70343 );
nor ( n70345 , n70342 , n70344 );
nor ( n70346 , n70336 , n70345 );
and ( n70347 , n70321 , n70346 );
not ( n70348 , n70347 );
or ( n70349 , n70288 , n70348 );
not ( n70350 , n70346 );
nand ( n70351 , n70317 , n70319 );
not ( n70352 , n70351 );
not ( n70353 , n70352 );
not ( n70354 , n70310 );
not ( n70355 , n70354 );
or ( n70356 , n70353 , n70355 );
nand ( n70357 , n70301 , n70309 );
nand ( n70358 , n70356 , n70357 );
not ( n70359 , n70358 );
or ( n70360 , n70350 , n70359 );
not ( n70361 , n70345 );
nand ( n70362 , n70333 , n70335 );
not ( n70363 , n70362 );
and ( n70364 , n70361 , n70363 );
nand ( n70365 , n70342 , n70344 );
not ( n70366 , n70365 );
nor ( n70367 , n70364 , n70366 );
nand ( n70368 , n70360 , n70367 );
not ( n70369 , n70368 );
nand ( n70370 , n70349 , n70369 );
not ( n70371 , n70370 );
nor ( n70372 , n70259 , n70265 );
nor ( n70373 , n70372 , n70282 );
not ( n70374 , n69553 );
not ( n70375 , n68988 );
or ( n70376 , n70222 , n70375 );
nand ( n70377 , n70222 , n68659 );
nand ( n70378 , n70376 , n70377 );
not ( n70379 , n70378 );
or ( n70380 , n70374 , n70379 );
not ( n70381 , n70378 );
not ( n70382 , n69553 );
nand ( n70383 , n70381 , n70382 );
nand ( n70384 , n70380 , n70383 );
not ( n70385 , n70384 );
or ( n70386 , n70222 , n69011 );
nand ( n70387 , n70222 , n68660 );
nand ( n70388 , n70386 , n70387 );
not ( n70389 , n69470 );
nor ( n70390 , n70388 , n70389 );
not ( n70391 , n70390 );
nand ( n70392 , n70385 , n70391 );
xor ( n70393 , n69543 , n70264 );
not ( n70394 , n70393 );
nor ( n70395 , n70378 , n70382 );
not ( n70396 , n70395 );
nand ( n70397 , n70394 , n70396 );
and ( n70398 , n70392 , n70397 );
not ( n70399 , n69487 );
not ( n70400 , n70222 );
not ( n70401 , n69084 );
and ( n70402 , n70400 , n70401 );
and ( n70403 , n70222 , n2524 );
nor ( n70404 , n70402 , n70403 );
not ( n70405 , n70404 );
not ( n70406 , n70405 );
or ( n70407 , n70399 , n70406 );
or ( n70408 , n70405 , n69487 );
nand ( n70409 , n70407 , n70408 );
not ( n70410 , n69471 );
not ( n70411 , n70410 );
not ( n70412 , n69451 );
not ( n70413 , n70412 );
or ( n70414 , n70411 , n70413 );
not ( n70415 , n69072 );
not ( n70416 , n70222 );
not ( n70417 , n70416 );
or ( n70418 , n70415 , n70417 );
nand ( n70419 , n70222 , n68664 );
nand ( n70420 , n70418 , n70419 );
not ( n70421 , n70420 );
nand ( n70422 , n70414 , n70421 );
not ( n70423 , n70412 );
nand ( n70424 , n70423 , n69471 );
nand ( n70425 , n70422 , n70424 );
nor ( n70426 , n70409 , n70425 );
not ( n70427 , n69502 );
not ( n70428 , n69025 );
not ( n70429 , n70416 );
or ( n70430 , n70428 , n70429 );
nand ( n70431 , n70222 , n2523 );
nand ( n70432 , n70430 , n70431 );
not ( n70433 , n70432 );
or ( n70434 , n70427 , n70433 );
not ( n70435 , n70432 );
not ( n70436 , n69502 );
nand ( n70437 , n70435 , n70436 );
nand ( n70438 , n70434 , n70437 );
not ( n70439 , n69487 );
nor ( n70440 , n70439 , n70405 );
nor ( n70441 , n70438 , n70440 );
nor ( n70442 , n70426 , n70441 );
not ( n70443 , n69471 );
not ( n70444 , n69451 );
not ( n70445 , n70444 );
or ( n70446 , n70443 , n70445 );
nand ( n70447 , n69451 , n70410 );
nand ( n70448 , n70446 , n70447 );
and ( n70449 , n70448 , n70421 );
not ( n70450 , n70448 );
and ( n70451 , n70450 , n70420 );
nor ( n70452 , n70449 , n70451 );
not ( n70453 , n70222 );
not ( n70454 , n69095 );
not ( n70455 , n70454 );
and ( n70456 , n70453 , n70455 );
and ( n70457 , n70222 , n68665 );
nor ( n70458 , n70456 , n70457 );
not ( n70459 , n70458 );
not ( n70460 , n70459 );
and ( n70461 , n70073 , n70460 );
nor ( n70462 , n70452 , n70461 );
not ( n70463 , n70462 );
and ( n70464 , n70373 , n70398 , n70442 , n70463 );
not ( n70465 , n70389 );
not ( n70466 , n70388 );
not ( n70467 , n70466 );
or ( n70468 , n70465 , n70467 );
nand ( n70469 , n70388 , n69470 );
nand ( n70470 , n70468 , n70469 );
not ( n70471 , n70222 );
not ( n70472 , n69059 );
not ( n70473 , n70472 );
and ( n70474 , n70471 , n70473 );
and ( n70475 , n70222 , n68661 );
nor ( n70476 , n70474 , n70475 );
not ( n70477 , n70476 );
not ( n70478 , n69435 );
nor ( n70479 , n70477 , n70478 );
nor ( n70480 , n70470 , n70479 );
not ( n70481 , n69435 );
not ( n70482 , n70477 );
or ( n70483 , n70481 , n70482 );
not ( n70484 , n70477 );
nand ( n70485 , n70484 , n70478 );
nand ( n70486 , n70483 , n70485 );
nor ( n70487 , n70432 , n70436 );
nand ( n70488 , n70486 , n70487 );
nor ( n70489 , n70480 , n70488 );
and ( n70490 , n70470 , n70479 );
nor ( n70491 , n70489 , n70490 );
or ( n70492 , n70470 , n70479 );
not ( n70493 , n70486 );
not ( n70494 , n70487 );
nand ( n70495 , n70493 , n70494 );
nand ( n70496 , n70492 , n70495 );
nand ( n70497 , n70491 , n70496 );
not ( n70498 , n70222 );
not ( n70499 , n69107 );
and ( n70500 , n70498 , n70499 );
and ( n70501 , n70222 , n68666 );
nor ( n70502 , n70500 , n70501 );
not ( n70503 , n70502 );
or ( n70504 , n70503 , n70053 );
nand ( n70505 , n70053 , n70503 );
nand ( n70506 , n70504 , n70505 );
nor ( n70507 , n70506 , n69967 );
not ( n70508 , n70460 );
not ( n70509 , n70073 );
not ( n70510 , n70509 );
or ( n70511 , n70508 , n70510 );
nand ( n70512 , n70073 , n70459 );
nand ( n70513 , n70511 , n70512 );
not ( n70514 , n70053 );
nor ( n70515 , n70514 , n70503 );
nor ( n70516 , n70513 , n70515 );
nor ( n70517 , n70507 , n70516 );
nand ( n70518 , n70506 , n69967 );
not ( n70519 , n69967 );
or ( n70520 , n70222 , n69108 );
nand ( n70521 , n70222 , n2528 );
nand ( n70522 , n70520 , n70521 );
not ( n70523 , n70522 );
nand ( n70524 , n70519 , n70523 );
nand ( n70525 , n70518 , n70524 );
nand ( n70526 , n70517 , n70525 );
nand ( n70527 , n70452 , n70461 );
nand ( n70528 , n70513 , n70515 );
and ( n70529 , n70527 , n70528 );
nand ( n70530 , n70526 , n70529 );
nand ( n70531 , n70464 , n70497 , n70347 , n70530 );
not ( n70532 , n70372 );
and ( n70533 , n70532 , n70283 , n70392 , n70397 );
not ( n70534 , n70489 );
nand ( n70535 , n70425 , n70409 );
not ( n70536 , n70535 );
not ( n70537 , n70438 );
not ( n70538 , n70440 );
nand ( n70539 , n70537 , n70538 );
nand ( n70540 , n70536 , n70539 );
not ( n70541 , n70490 );
nand ( n70542 , n70438 , n70440 );
nand ( n70543 , n70534 , n70540 , n70541 , n70542 );
nand ( n70544 , n70347 , n70497 , n70533 , n70543 );
and ( n70545 , n70384 , n70390 );
not ( n70546 , n70545 );
not ( n70547 , n70397 );
or ( n70548 , n70546 , n70547 );
or ( n70549 , n70394 , n70396 );
nand ( n70550 , n70548 , n70549 );
and ( n70551 , n70550 , n70373 );
nand ( n70552 , n70347 , n70551 );
nand ( n70553 , n70371 , n70531 , n70544 , n70552 );
not ( n70554 , n70553 );
or ( n70555 , n70245 , n70554 );
or ( n70556 , n70553 , n70244 );
nand ( n70557 , n70555 , n70556 );
not ( n70558 , n70188 );
not ( n70559 , n70194 );
nand ( n70560 , n70558 , n70559 );
nand ( n70561 , n70560 , n70195 );
and ( n70562 , n70188 , n70206 );
not ( n70563 , n70188 );
and ( n70564 , n70563 , n70202 );
nor ( n70565 , n70562 , n70564 );
nor ( n70566 , n70561 , n70565 );
not ( n70567 , n70566 );
nor ( n70568 , n70567 , n70183 );
and ( n70569 , n70557 , n70568 );
not ( n70570 , n70565 );
nor ( n70571 , n70570 , n70561 );
not ( n70572 , n70571 );
nor ( n70573 , n70572 , n70183 );
not ( n70574 , n70573 );
not ( n70575 , n70225 );
not ( n70576 , n69641 );
not ( n70577 , n70576 );
or ( n70578 , n70575 , n70577 );
not ( n70579 , n70225 );
nand ( n70580 , n70579 , n69641 );
nand ( n70581 , n70578 , n70580 );
not ( n70582 , n70581 );
and ( n70583 , n69613 , n70238 );
not ( n70584 , n70583 );
nand ( n70585 , n70582 , n70584 );
nand ( n70586 , n70581 , n70583 );
and ( n70587 , n70585 , n70586 );
not ( n70588 , n70587 );
not ( n70589 , n69435 );
not ( n70590 , n70477 );
not ( n70591 , n70590 );
or ( n70592 , n70589 , n70591 );
not ( n70593 , n69435 );
nand ( n70594 , n70593 , n70477 );
nand ( n70595 , n70592 , n70594 );
and ( n70596 , n70432 , n69502 );
nand ( n70597 , n70595 , n70596 );
not ( n70598 , n70597 );
not ( n70599 , n69470 );
not ( n70600 , n70388 );
not ( n70601 , n70600 );
or ( n70602 , n70599 , n70601 );
not ( n70603 , n69470 );
nand ( n70604 , n70603 , n70388 );
nand ( n70605 , n70602 , n70604 );
nand ( n70606 , n70477 , n69435 );
not ( n70607 , n70606 );
nor ( n70608 , n70605 , n70607 );
not ( n70609 , n70608 );
and ( n70610 , n70598 , n70609 );
nand ( n70611 , n70605 , n70607 );
not ( n70612 , n70611 );
nor ( n70613 , n70610 , n70612 );
not ( n70614 , n70595 );
not ( n70615 , n70596 );
nand ( n70616 , n70614 , n70615 );
not ( n70617 , n70608 );
nand ( n70618 , n70616 , n70617 );
nand ( n70619 , n70613 , n70618 );
not ( n70620 , n69543 );
not ( n70621 , n70620 );
not ( n70622 , n70263 );
or ( n70623 , n70621 , n70622 );
not ( n70624 , n70263 );
nand ( n70625 , n70624 , n69543 );
nand ( n70626 , n70623 , n70625 );
not ( n70627 , n70626 );
and ( n70628 , n70378 , n69553 );
not ( n70629 , n70628 );
nand ( n70630 , n70627 , n70629 );
not ( n70631 , n69553 );
not ( n70632 , n70378 );
not ( n70633 , n70632 );
or ( n70634 , n70631 , n70633 );
not ( n70635 , n69553 );
nand ( n70636 , n70378 , n70635 );
nand ( n70637 , n70634 , n70636 );
not ( n70638 , n70637 );
and ( n70639 , n70388 , n69470 );
not ( n70640 , n70639 );
nand ( n70641 , n70638 , n70640 );
nand ( n70642 , n70630 , n70641 );
not ( n70643 , n70273 );
not ( n70644 , n69519 );
not ( n70645 , n70644 );
or ( n70646 , n70643 , n70645 );
not ( n70647 , n70273 );
nand ( n70648 , n69519 , n70647 );
nand ( n70649 , n70646 , n70648 );
not ( n70650 , n70649 );
and ( n70651 , n70253 , n69531 );
not ( n70652 , n70651 );
nand ( n70653 , n70650 , n70652 );
xor ( n70654 , n69531 , n70253 );
not ( n70655 , n70654 );
and ( n70656 , n69543 , n70263 );
not ( n70657 , n70656 );
nand ( n70658 , n70655 , n70657 );
nand ( n70659 , n70653 , n70658 );
nor ( n70660 , n70642 , n70659 );
not ( n70661 , n69576 );
not ( n70662 , n70296 );
not ( n70663 , n70662 );
or ( n70664 , n70661 , n70663 );
not ( n70665 , n69576 );
nand ( n70666 , n70665 , n70296 );
nand ( n70667 , n70664 , n70666 );
nand ( n70668 , n70308 , n69587 );
not ( n70669 , n70668 );
nor ( n70670 , n70667 , n70669 );
not ( n70671 , n70308 );
not ( n70672 , n69587 );
not ( n70673 , n70672 );
or ( n70674 , n70671 , n70673 );
not ( n70675 , n70308 );
nand ( n70676 , n70675 , n69587 );
nand ( n70677 , n70674 , n70676 );
and ( n70678 , n70273 , n69519 );
nor ( n70679 , n70677 , n70678 );
nor ( n70680 , n70670 , n70679 );
not ( n70681 , n70238 );
not ( n70682 , n70681 );
not ( n70683 , n69613 );
or ( n70684 , n70682 , n70683 );
not ( n70685 , n69613 );
nand ( n70686 , n70685 , n70238 );
nand ( n70687 , n70684 , n70686 );
nand ( n70688 , n69599 , n70327 );
not ( n70689 , n70688 );
nor ( n70690 , n70687 , n70689 );
not ( n70691 , n69599 );
not ( n70692 , n70691 );
not ( n70693 , n70327 );
or ( n70694 , n70692 , n70693 );
not ( n70695 , n70327 );
nand ( n70696 , n70695 , n69599 );
nand ( n70697 , n70694 , n70696 );
and ( n70698 , n69576 , n70296 );
nor ( n70699 , n70697 , n70698 );
nor ( n70700 , n70690 , n70699 );
nand ( n70701 , n70619 , n70660 , n70680 , n70700 );
not ( n70702 , n70701 );
not ( n70703 , n70702 );
not ( n70704 , n70459 );
not ( n70705 , n70073 );
not ( n70706 , n70705 );
or ( n70707 , n70704 , n70706 );
not ( n70708 , n70459 );
nand ( n70709 , n70708 , n70073 );
nand ( n70710 , n70707 , n70709 );
not ( n70711 , n70710 );
not ( n70712 , n70053 );
not ( n70713 , n70503 );
nor ( n70714 , n70712 , n70713 );
not ( n70715 , n70714 );
nand ( n70716 , n70711 , n70715 );
not ( n70717 , n70503 );
not ( n70718 , n70053 );
not ( n70719 , n70718 );
or ( n70720 , n70717 , n70719 );
nand ( n70721 , n70053 , n70713 );
nand ( n70722 , n70720 , n70721 );
not ( n70723 , n69967 );
not ( n70724 , n70522 );
nor ( n70725 , n70723 , n70724 );
nand ( n70726 , n70722 , n70725 );
not ( n70727 , n70726 );
nand ( n70728 , n70716 , n70727 );
xor ( n70729 , n69471 , n69451 );
xor ( n70730 , n70729 , n70420 );
and ( n70731 , n70073 , n70459 );
nand ( n70732 , n70730 , n70731 );
nand ( n70733 , n70710 , n70714 );
nand ( n70734 , n70728 , n70732 , n70733 );
not ( n70735 , n69502 );
not ( n70736 , n70432 );
not ( n70737 , n70736 );
or ( n70738 , n70735 , n70737 );
not ( n70739 , n69502 );
nand ( n70740 , n70432 , n70739 );
nand ( n70741 , n70738 , n70740 );
not ( n70742 , n70741 );
and ( n70743 , n70405 , n69487 );
not ( n70744 , n70743 );
nand ( n70745 , n70742 , n70744 );
xor ( n70746 , n69471 , n69451 );
and ( n70747 , n70746 , n70420 );
and ( n70748 , n69471 , n69451 );
or ( n70749 , n70747 , n70748 );
not ( n70750 , n70749 );
not ( n70751 , n69487 );
not ( n70752 , n70405 );
not ( n70753 , n70752 );
or ( n70754 , n70751 , n70753 );
not ( n70755 , n69487 );
nand ( n70756 , n70755 , n70405 );
nand ( n70757 , n70754 , n70756 );
not ( n70758 , n70757 );
nand ( n70759 , n70750 , n70758 );
and ( n70760 , n70745 , n70759 );
or ( n70761 , n70730 , n70731 );
nand ( n70762 , n70734 , n70760 , n70761 );
and ( n70763 , n70749 , n70757 );
not ( n70764 , n70763 );
not ( n70765 , n70745 );
or ( n70766 , n70764 , n70765 );
not ( n70767 , n70744 );
nand ( n70768 , n70767 , n70741 );
nand ( n70769 , n70766 , n70768 );
not ( n70770 , n70613 );
nor ( n70771 , n70769 , n70770 );
nand ( n70772 , n70762 , n70771 );
not ( n70773 , n70772 );
or ( n70774 , n70703 , n70773 );
not ( n70775 , n70697 );
not ( n70776 , n70698 );
nor ( n70777 , n70775 , n70776 );
not ( n70778 , n70777 );
not ( n70779 , n70690 );
not ( n70780 , n70779 );
or ( n70781 , n70778 , n70780 );
nand ( n70782 , n70687 , n70689 );
nand ( n70783 , n70781 , n70782 );
nand ( n70784 , n70677 , n70678 );
or ( n70785 , n70670 , n70784 );
nand ( n70786 , n70667 , n70669 );
nand ( n70787 , n70785 , n70786 );
nor ( n70788 , n70783 , n70787 );
not ( n70789 , n70788 );
nand ( n70790 , n70649 , n70651 );
nand ( n70791 , n70659 , n70790 );
nand ( n70792 , n70654 , n70656 );
nand ( n70793 , n70626 , n70628 );
nand ( n70794 , n70792 , n70790 , n70793 );
not ( n70795 , n70794 );
and ( n70796 , n70637 , n70639 );
nand ( n70797 , n70630 , n70796 );
nand ( n70798 , n70795 , n70797 );
nand ( n70799 , n70791 , n70798 , n70680 );
not ( n70800 , n70799 );
or ( n70801 , n70789 , n70800 );
or ( n70802 , n70783 , n70700 );
nand ( n70803 , n70801 , n70802 );
nand ( n70804 , n70774 , n70803 );
not ( n70805 , n70804 );
not ( n70806 , n70805 );
or ( n70807 , n70588 , n70806 );
nand ( n70808 , n70702 , n70772 );
nand ( n70809 , n70803 , n70808 );
not ( n70810 , n70809 );
or ( n70811 , n70810 , n70587 );
nand ( n70812 , n70807 , n70811 );
not ( n70813 , n70812 );
or ( n70814 , n70574 , n70813 );
not ( n70815 , n70225 );
nor ( n70816 , n70388 , n70432 );
not ( n70817 , n70405 );
not ( n70818 , n70817 );
nor ( n70819 , n70477 , n70818 );
nor ( n70820 , n70327 , n70238 );
nor ( n70821 , n70420 , n70459 );
nand ( n70822 , n70816 , n70819 , n70820 , n70821 );
not ( n70823 , n70822 );
nor ( n70824 , n70263 , n70378 );
not ( n70825 , n70253 );
not ( n70826 , n70273 );
and ( n70827 , n70824 , n70825 , n70826 );
nor ( n70828 , n70296 , n70308 );
not ( n70829 , n70503 );
not ( n70830 , n70829 );
nor ( n70831 , n70830 , n70522 );
nand ( n70832 , n70823 , n70827 , n70828 , n70831 );
not ( n70833 , n70832 );
not ( n70834 , n70833 );
or ( n70835 , n70815 , n70834 );
or ( n70836 , n70833 , n70225 );
nand ( n70837 , n70835 , n70836 );
nor ( n70838 , n70188 , n70194 );
nand ( n70839 , n70838 , n70207 );
nor ( n70840 , n70183 , n70839 );
nand ( n70841 , n70837 , n70840 );
not ( n70842 , n70183 );
not ( n70843 , n70194 );
not ( n70844 , n70202 );
nor ( n70845 , n70844 , n70188 );
nand ( n70846 , n70843 , n70845 );
not ( n70847 , n70846 );
nand ( n70848 , n70842 , n70847 );
not ( n70849 , n70848 );
nand ( n70850 , n70849 , n70225 );
not ( n70851 , n70845 );
nor ( n70852 , n70202 , n70206 );
not ( n70853 , n70852 );
nand ( n70854 , n70561 , n70851 , n70853 );
not ( n70855 , n70854 );
not ( n70856 , n70164 );
or ( n70857 , n70855 , n70856 );
or ( n70858 , n70195 , n70207 );
not ( n70859 , n70139 );
not ( n70860 , n70859 );
nand ( n70861 , n70136 , n70860 );
not ( n70862 , n70861 );
not ( n70863 , n70147 );
nand ( n70864 , n70858 , n70862 , n70863 );
not ( n70865 , n70206 );
nor ( n70866 , n70202 , n70865 );
and ( n70867 , n70838 , n70866 );
nor ( n70868 , n70867 , n70180 );
nor ( n70869 , n70864 , n70868 );
nand ( n70870 , n70857 , n70869 );
and ( n70871 , n70870 , n2697 );
not ( n70872 , n70560 );
nand ( n70873 , n70866 , n70139 );
not ( n70874 , n70873 );
nand ( n70875 , n70136 , n70872 , n70874 , n70863 );
not ( n70876 , n70875 );
not ( n70877 , n3356 );
nand ( n70878 , n3304 , n3344 );
nor ( n70879 , n70877 , n70878 );
nand ( n70880 , n70879 , n3288 );
not ( n70881 , n3324 );
nor ( n70882 , n70880 , n70881 );
nand ( n70883 , n70882 , n69549 );
not ( n70884 , n69537 );
nor ( n70885 , n70883 , n70884 );
nand ( n70886 , n70885 , n69520 );
not ( n70887 , n69512 );
nor ( n70888 , n70886 , n70887 );
and ( n70889 , n70888 , n3442 );
nand ( n70890 , n70889 , n69567 );
not ( n70891 , n3454 );
nor ( n70892 , n70890 , n70891 );
nand ( n70893 , n70892 , n69603 );
not ( n70894 , n69639 );
and ( n70895 , n70893 , n70894 );
not ( n70896 , n70893 );
and ( n70897 , n70896 , n69639 );
nor ( n70898 , n70895 , n70897 );
and ( n70899 , n70876 , n70898 );
nor ( n70900 , n70871 , n70899 );
and ( n70901 , n70841 , n70850 , n70900 );
nand ( n70902 , n70814 , n70901 );
nor ( n70903 , n70569 , n70902 );
nand ( n70904 , n70211 , n70903 );
buf ( n70905 , n70904 );
buf ( n70906 , 1'b0 );
not ( n70907 , n68838 );
buf ( n4769 , n70907 );
buf ( n4770 , n68634 );
not ( n70910 , n69358 );
not ( n70911 , n70013 );
nand ( n70912 , n69969 , n70092 );
not ( n70913 , n70912 );
nand ( n70914 , n70913 , n70007 );
not ( n70915 , n70914 );
or ( n70916 , n70911 , n70915 );
or ( n70917 , n70914 , n70013 );
nand ( n70918 , n70916 , n70917 );
not ( n70919 , n70918 );
or ( n70920 , n70910 , n70919 );
nand ( n70921 , n70082 , n69359 );
nand ( n70922 , n70920 , n70921 );
not ( n70923 , n70195 );
and ( n70924 , n70922 , n70923 );
not ( n70925 , n70206 );
not ( n70926 , n70188 );
or ( n70927 , n70925 , n70926 );
or ( n70928 , n70872 , n70851 );
nand ( n70929 , n70927 , n70928 );
not ( n70930 , n70929 );
not ( n70931 , n70930 );
not ( n70932 , n70931 );
nand ( n70933 , n70397 , n70549 );
not ( n70934 , n70933 );
not ( n70935 , n70392 );
not ( n70936 , n70442 );
nor ( n70937 , n70496 , n70936 );
not ( n70938 , n70937 );
not ( n70939 , n70463 );
not ( n70940 , n70526 );
not ( n70941 , n70940 );
or ( n70942 , n70939 , n70941 );
not ( n70943 , n70528 );
and ( n70944 , n70463 , n70943 );
not ( n70945 , n70527 );
nor ( n70946 , n70944 , n70945 );
nand ( n70947 , n70942 , n70946 );
not ( n70948 , n70947 );
or ( n70949 , n70938 , n70948 );
nand ( n70950 , n70540 , n70542 );
not ( n70951 , n70950 );
not ( n70952 , n70496 );
not ( n70953 , n70952 );
or ( n70954 , n70951 , n70953 );
nand ( n70955 , n70954 , n70491 );
not ( n70956 , n70955 );
nand ( n70957 , n70949 , n70956 );
not ( n70958 , n70957 );
or ( n70959 , n70935 , n70958 );
not ( n70960 , n70545 );
nand ( n70961 , n70959 , n70960 );
not ( n70962 , n70961 );
or ( n70963 , n70934 , n70962 );
or ( n70964 , n70961 , n70933 );
nand ( n70965 , n70963 , n70964 );
not ( n70966 , n70965 );
or ( n70967 , n70932 , n70966 );
nand ( n70968 , n70630 , n70793 );
not ( n70969 , n70968 );
not ( n70970 , n70641 );
not ( n70971 , n70760 );
nor ( n70972 , n70971 , n70618 );
not ( n70973 , n70972 );
not ( n70974 , n70728 );
nand ( n70975 , n70974 , n70761 );
not ( n70976 , n70733 );
nand ( n70977 , n70761 , n70976 );
nand ( n70978 , n70975 , n70977 , n70732 );
not ( n70979 , n70978 );
or ( n70980 , n70973 , n70979 );
not ( n70981 , n70618 );
and ( n70982 , n70769 , n70981 );
nor ( n70983 , n70982 , n70770 );
nand ( n70984 , n70980 , n70983 );
not ( n70985 , n70984 );
or ( n70986 , n70970 , n70985 );
not ( n70987 , n70796 );
nand ( n70988 , n70986 , n70987 );
not ( n70989 , n70988 );
or ( n70990 , n70969 , n70989 );
or ( n70991 , n70988 , n70968 );
nand ( n70992 , n70990 , n70991 );
and ( n70993 , n70992 , n70571 );
not ( n70994 , n70852 );
nor ( n70995 , n70994 , n70560 );
not ( n70996 , n70995 );
not ( n70997 , n70263 );
not ( n70998 , n70997 );
not ( n70999 , n70378 );
and ( n71000 , n70831 , n70821 );
and ( n71001 , n70819 , n70816 );
nand ( n71002 , n71000 , n71001 );
not ( n71003 , n71002 );
nand ( n71004 , n70999 , n71003 );
not ( n71005 , n71004 );
or ( n71006 , n70998 , n71005 );
or ( n71007 , n71004 , n70997 );
nand ( n71008 , n71006 , n71007 );
not ( n71009 , n71008 );
or ( n71010 , n70996 , n71009 );
nand ( n71011 , n70847 , n70263 );
nand ( n71012 , n71010 , n71011 );
nor ( n71013 , n70993 , n71012 );
nand ( n71014 , n70967 , n71013 );
nor ( n71015 , n70924 , n71014 );
nand ( n71016 , n70148 , n70164 , n70181 , n70854 );
or ( n71017 , n71015 , n71016 );
nand ( n71018 , n71016 , n69535 );
nand ( n71019 , n71017 , n71018 );
buf ( n4881 , n71019 );
buf ( n71021 , 1'b0 );
not ( n71022 , n68838 );
buf ( n4884 , n71022 );
buf ( n4885 , n68634 );
not ( n71025 , n71016 );
not ( n71026 , n69800 );
or ( n71027 , n71025 , n71026 );
not ( n71028 , n69358 );
nor ( n71029 , n69823 , n69826 );
not ( n71030 , n71029 );
not ( n71031 , n71030 );
nand ( n71032 , n71031 , n69627 );
not ( n71033 , n69871 );
and ( n71034 , n71032 , n71033 );
not ( n71035 , n71032 );
and ( n71036 , n71035 , n69871 );
nor ( n71037 , n71034 , n71036 );
not ( n71038 , n71037 );
nand ( n71039 , n69983 , n69660 );
nor ( n71040 , n70099 , n71039 );
nand ( n71041 , n69971 , n71040 );
nand ( n71042 , n69627 , n69827 );
not ( n71043 , n69822 );
and ( n71044 , n71042 , n71043 );
not ( n71045 , n71042 );
and ( n71046 , n71045 , n69822 );
nor ( n71047 , n71044 , n71046 );
not ( n71048 , n71047 );
nor ( n71049 , n71041 , n71048 );
not ( n71050 , n69804 );
not ( n71051 , n69827 );
nor ( n71052 , n71051 , n71043 );
nand ( n71053 , n69627 , n71052 );
not ( n71054 , n71053 );
or ( n71055 , n71050 , n71054 );
nand ( n71056 , n69627 , n71052 );
or ( n71057 , n71056 , n69804 );
nand ( n71058 , n71055 , n71057 );
nand ( n71059 , n71049 , n71058 );
not ( n71060 , n71059 );
or ( n71061 , n71038 , n71060 );
or ( n71062 , n71059 , n71037 );
nand ( n71063 , n71061 , n71062 );
not ( n71064 , n71063 );
or ( n71065 , n71028 , n71064 );
nand ( n71066 , n71047 , n69359 );
nand ( n71067 , n71065 , n71066 );
and ( n71068 , n71067 , n70923 );
not ( n71069 , n69176 );
not ( n71070 , n70222 );
not ( n71071 , n71070 );
or ( n71072 , n71069 , n71071 );
nand ( n71073 , n70222 , n68650 );
nand ( n71074 , n71072 , n71073 );
not ( n71075 , n71074 );
not ( n71076 , n71075 );
not ( n71077 , n69655 );
not ( n71078 , n71077 );
or ( n71079 , n71076 , n71078 );
nand ( n71080 , n69655 , n71074 );
nand ( n71081 , n71079 , n71080 );
nand ( n71082 , n70229 , n69641 );
not ( n71083 , n71082 );
nor ( n71084 , n71081 , n71083 );
nor ( n71085 , n71084 , n70241 );
not ( n71086 , n71085 );
not ( n71087 , n69822 );
not ( n71088 , n69157 );
not ( n71089 , n71070 );
or ( n71090 , n71088 , n71089 );
nand ( n71091 , n70222 , n68649 );
nand ( n71092 , n71090 , n71091 );
not ( n71093 , n71092 );
or ( n71094 , n71087 , n71093 );
not ( n71095 , n71092 );
not ( n71096 , n69822 );
nand ( n71097 , n71095 , n71096 );
nand ( n71098 , n71094 , n71097 );
and ( n71099 , n71075 , n69655 );
nor ( n71100 , n71098 , n71099 );
nor ( n71101 , n71086 , n71100 );
not ( n71102 , n71101 );
not ( n71103 , n70553 );
or ( n71104 , n71102 , n71103 );
not ( n71105 , n71100 );
not ( n71106 , n71105 );
or ( n71107 , n70243 , n71084 );
nand ( n71108 , n71081 , n71083 );
nand ( n71109 , n71107 , n71108 );
not ( n71110 , n71109 );
or ( n71111 , n71106 , n71110 );
nand ( n71112 , n71098 , n71099 );
nand ( n71113 , n71111 , n71112 );
not ( n71114 , n71113 );
nand ( n71115 , n71104 , n71114 );
not ( n71116 , n69804 );
not ( n71117 , n70222 );
not ( n71118 , n69241 );
and ( n71119 , n71117 , n71118 );
and ( n71120 , n70222 , n2509 );
nor ( n71121 , n71119 , n71120 );
not ( n71122 , n71121 );
not ( n71123 , n71122 );
or ( n71124 , n71116 , n71123 );
not ( n71125 , n71122 );
not ( n71126 , n69804 );
nand ( n71127 , n71125 , n71126 );
nand ( n71128 , n71124 , n71127 );
not ( n71129 , n69822 );
nor ( n71130 , n71129 , n71092 );
nor ( n71131 , n71128 , n71130 );
and ( n71132 , n71128 , n71130 );
or ( n71133 , n71131 , n71132 );
xnor ( n71134 , n71115 , n71133 );
nand ( n71135 , n71134 , n70929 );
not ( n71136 , n71122 );
not ( n71137 , n71136 );
not ( n71138 , n69804 );
or ( n71139 , n71137 , n71138 );
not ( n71140 , n69804 );
nand ( n71141 , n71140 , n71122 );
nand ( n71142 , n71139 , n71141 );
nand ( n71143 , n71092 , n69822 );
not ( n71144 , n71143 );
and ( n71145 , n71142 , n71144 );
nor ( n71146 , n71142 , n71144 );
or ( n71147 , n71145 , n71146 );
not ( n71148 , n71147 );
not ( n71149 , n69655 );
not ( n71150 , n71074 );
not ( n71151 , n71150 );
or ( n71152 , n71149 , n71151 );
not ( n71153 , n69655 );
nand ( n71154 , n71153 , n71074 );
nand ( n71155 , n71152 , n71154 );
nand ( n71156 , n69641 , n70225 );
not ( n71157 , n71156 );
nor ( n71158 , n71155 , n71157 );
not ( n71159 , n71158 );
nand ( n71160 , n71159 , n70585 );
not ( n71161 , n69822 );
not ( n71162 , n71092 );
not ( n71163 , n71162 );
or ( n71164 , n71161 , n71163 );
not ( n71165 , n69822 );
nand ( n71166 , n71092 , n71165 );
nand ( n71167 , n71164 , n71166 );
and ( n71168 , n69655 , n71074 );
nor ( n71169 , n71167 , n71168 );
nor ( n71170 , n71160 , n71169 );
not ( n71171 , n71170 );
not ( n71172 , n70804 );
or ( n71173 , n71171 , n71172 );
not ( n71174 , n71169 );
not ( n71175 , n71174 );
or ( n71176 , n71158 , n70586 );
nand ( n71177 , n71155 , n71157 );
nand ( n71178 , n71176 , n71177 );
not ( n71179 , n71178 );
or ( n71180 , n71175 , n71179 );
nand ( n71181 , n71167 , n71168 );
nand ( n71182 , n71180 , n71181 );
not ( n71183 , n71182 );
nand ( n71184 , n71173 , n71183 );
not ( n71185 , n71184 );
or ( n71186 , n71148 , n71185 );
or ( n71187 , n71184 , n71147 );
nand ( n71188 , n71186 , n71187 );
and ( n71189 , n71188 , n70571 );
not ( n71190 , n70995 );
not ( n71191 , n71122 );
not ( n71192 , n70225 );
not ( n71193 , n71074 );
nand ( n71194 , n71192 , n71193 );
or ( n71195 , n71194 , n71092 );
nor ( n71196 , n70832 , n71195 );
not ( n71197 , n71196 );
or ( n71198 , n71191 , n71197 );
or ( n71199 , n71196 , n71122 );
nand ( n71200 , n71198 , n71199 );
not ( n71201 , n71200 );
or ( n71202 , n71190 , n71201 );
nand ( n71203 , n70847 , n71122 );
nand ( n71204 , n71202 , n71203 );
nor ( n71205 , n71189 , n71204 );
nand ( n71206 , n71135 , n71205 );
nor ( n71207 , n71068 , n71206 );
or ( n71208 , n71207 , n71016 );
nand ( n71209 , n71027 , n71208 );
buf ( n5071 , n71209 );
buf ( n5072 , 1'b0 );
not ( n71212 , n68838 );
buf ( n5074 , n71212 );
buf ( n5075 , n68634 );
not ( n71215 , n69358 );
not ( n71216 , n71058 );
not ( n71217 , n71216 );
not ( n71218 , n71049 );
or ( n71219 , n71217 , n71218 );
or ( n71220 , n71049 , n71216 );
nand ( n71221 , n71219 , n71220 );
not ( n71222 , n71221 );
or ( n71223 , n71215 , n71222 );
nand ( n71224 , n69660 , n69359 );
nand ( n71225 , n71223 , n71224 );
and ( n71226 , n71225 , n70923 );
not ( n71227 , n71085 );
not ( n71228 , n70553 );
or ( n71229 , n71227 , n71228 );
not ( n71230 , n71109 );
nand ( n71231 , n71229 , n71230 );
nand ( n71232 , n71105 , n71112 );
xnor ( n71233 , n71231 , n71232 );
not ( n71234 , n71233 );
not ( n71235 , n70929 );
or ( n71236 , n71234 , n71235 );
nand ( n71237 , n71174 , n71181 );
not ( n71238 , n71237 );
not ( n71239 , n71160 );
not ( n71240 , n71239 );
not ( n71241 , n70804 );
or ( n71242 , n71240 , n71241 );
not ( n71243 , n71178 );
nand ( n71244 , n71242 , n71243 );
not ( n71245 , n71244 );
or ( n71246 , n71238 , n71245 );
or ( n71247 , n71244 , n71237 );
nand ( n71248 , n71246 , n71247 );
and ( n71249 , n71248 , n70571 );
not ( n71250 , n70995 );
not ( n71251 , n71092 );
nor ( n71252 , n70832 , n71194 );
not ( n71253 , n71252 );
or ( n71254 , n71251 , n71253 );
or ( n71255 , n71252 , n71092 );
nand ( n71256 , n71254 , n71255 );
not ( n71257 , n71256 );
or ( n71258 , n71250 , n71257 );
nand ( n71259 , n70847 , n71092 );
nand ( n71260 , n71258 , n71259 );
nor ( n71261 , n71249 , n71260 );
nand ( n71262 , n71236 , n71261 );
nor ( n71263 , n71226 , n71262 );
or ( n71264 , n71263 , n71016 );
nand ( n71265 , n71016 , n69810 );
nand ( n71266 , n71264 , n71265 );
buf ( n5128 , n71266 );
buf ( n71268 , 1'b0 );
not ( n71269 , n68838 );
buf ( n71270 , n71269 );
buf ( n5132 , n68634 );
not ( n71272 , n69358 );
and ( n71273 , n71272 , n69977 );
not ( n71274 , n71272 );
not ( n71275 , n71047 );
not ( n71276 , n71041 );
or ( n71277 , n71275 , n71276 );
or ( n71278 , n71041 , n71047 );
nand ( n71279 , n71277 , n71278 );
and ( n71280 , n71274 , n71279 );
nor ( n71281 , n71273 , n71280 );
not ( n71282 , n71281 );
and ( n71283 , n71282 , n70923 );
not ( n71284 , n70929 );
not ( n71285 , n70242 );
not ( n71286 , n70553 );
or ( n71287 , n71285 , n71286 );
nand ( n71288 , n71287 , n70243 );
not ( n71289 , n71084 );
nand ( n71290 , n71289 , n71108 );
xnor ( n71291 , n71288 , n71290 );
not ( n71292 , n71291 );
or ( n71293 , n71284 , n71292 );
not ( n71294 , n71158 );
nand ( n71295 , n71294 , n71177 );
not ( n71296 , n71295 );
not ( n71297 , n70585 );
not ( n71298 , n70804 );
or ( n71299 , n71297 , n71298 );
nand ( n71300 , n71299 , n70586 );
not ( n71301 , n71300 );
or ( n71302 , n71296 , n71301 );
or ( n71303 , n71300 , n71295 );
nand ( n71304 , n71302 , n71303 );
and ( n71305 , n71304 , n70571 );
not ( n71306 , n70995 );
not ( n71307 , n71074 );
nor ( n71308 , n70832 , n70225 );
not ( n71309 , n71308 );
or ( n71310 , n71307 , n71309 );
or ( n71311 , n71308 , n71074 );
nand ( n71312 , n71310 , n71311 );
not ( n71313 , n71312 );
or ( n71314 , n71306 , n71313 );
nand ( n71315 , n70847 , n71074 );
nand ( n71316 , n71314 , n71315 );
nor ( n71317 , n71305 , n71316 );
nand ( n71318 , n71293 , n71317 );
nor ( n71319 , n71283 , n71318 );
or ( n71320 , n71319 , n71016 );
nand ( n71321 , n71016 , n3510 );
nand ( n71322 , n71320 , n71321 );
buf ( n71323 , n71322 );
buf ( n71324 , 1'b0 );
not ( n71325 , n68838 );
buf ( n71326 , n71325 );
buf ( n71327 , n68634 );
not ( n71328 , n70109 );
and ( n71329 , n71328 , n70196 );
not ( n71330 , n70931 );
not ( n71331 , n70557 );
or ( n71332 , n71330 , n71331 );
and ( n71333 , n70812 , n70571 );
not ( n71334 , n70995 );
not ( n71335 , n70837 );
or ( n71336 , n71334 , n71335 );
nand ( n71337 , n70225 , n70847 );
nand ( n71338 , n71336 , n71337 );
nor ( n71339 , n71333 , n71338 );
nand ( n71340 , n71332 , n71339 );
nor ( n71341 , n71329 , n71340 );
or ( n71342 , n71341 , n71016 );
not ( n71343 , n71016 );
not ( n71344 , n71343 );
nand ( n71345 , n71344 , n3498 );
nand ( n71346 , n71342 , n71345 );
buf ( n71347 , n71346 );
buf ( n71348 , 1'b0 );
not ( n71349 , n68838 );
buf ( n71350 , n71349 );
buf ( n71351 , n68634 );
not ( n71352 , n69358 );
not ( n71353 , n69978 );
not ( n71354 , n71353 );
nor ( n71355 , n70101 , n69982 );
nand ( n71356 , n69969 , n71355 );
not ( n71357 , n71356 );
or ( n71358 , n71354 , n71357 );
or ( n71359 , n71356 , n71353 );
nand ( n71360 , n71358 , n71359 );
not ( n71361 , n71360 );
or ( n71362 , n71352 , n71361 );
nand ( n71363 , n69981 , n71272 );
nand ( n71364 , n71362 , n71363 );
and ( n71365 , n71364 , n70196 );
not ( n71366 , n70931 );
not ( n71367 , n70345 );
nand ( n71368 , n71367 , n70365 );
not ( n71369 , n71368 );
not ( n71370 , n70336 );
nand ( n71371 , n70321 , n71370 );
not ( n71372 , n70533 );
nor ( n71373 , n71371 , n71372 );
not ( n71374 , n71373 );
not ( n71375 , n70957 );
or ( n71376 , n71374 , n71375 );
nor ( n71377 , n70287 , n70551 );
not ( n71378 , n71377 );
not ( n71379 , n71371 );
and ( n71380 , n71378 , n71379 );
not ( n71381 , n71370 );
not ( n71382 , n70358 );
or ( n71383 , n71381 , n71382 );
nand ( n71384 , n71383 , n70362 );
nor ( n71385 , n71380 , n71384 );
nand ( n71386 , n71376 , n71385 );
not ( n71387 , n71386 );
or ( n71388 , n71369 , n71387 );
or ( n71389 , n71386 , n71368 );
nand ( n71390 , n71388 , n71389 );
not ( n71391 , n71390 );
or ( n71392 , n71366 , n71391 );
nand ( n71393 , n70779 , n70782 );
not ( n71394 , n71393 );
not ( n71395 , n70699 );
nand ( n71396 , n70680 , n71395 );
not ( n71397 , n70660 );
nor ( n71398 , n71396 , n71397 );
not ( n71399 , n71398 );
not ( n71400 , n70984 );
or ( n71401 , n71399 , n71400 );
nand ( n71402 , n70798 , n70791 );
not ( n71403 , n71402 );
not ( n71404 , n71396 );
and ( n71405 , n71403 , n71404 );
not ( n71406 , n71395 );
not ( n71407 , n70787 );
or ( n71408 , n71406 , n71407 );
not ( n71409 , n70777 );
nand ( n71410 , n71408 , n71409 );
nor ( n71411 , n71405 , n71410 );
nand ( n71412 , n71401 , n71411 );
not ( n71413 , n71412 );
or ( n71414 , n71394 , n71413 );
or ( n71415 , n71412 , n71393 );
nand ( n71416 , n71414 , n71415 );
and ( n71417 , n71416 , n70571 );
not ( n71418 , n70995 );
not ( n71419 , n70238 );
not ( n71420 , n71419 );
not ( n71421 , n70327 );
nand ( n71422 , n70827 , n70828 , n71421 );
not ( n71423 , n71422 );
nand ( n71424 , n71423 , n71003 );
not ( n71425 , n71424 );
or ( n71426 , n71420 , n71425 );
or ( n71427 , n71424 , n71419 );
nand ( n71428 , n71426 , n71427 );
not ( n71429 , n71428 );
or ( n71430 , n71418 , n71429 );
nand ( n71431 , n70238 , n70847 );
nand ( n71432 , n71430 , n71431 );
nor ( n71433 , n71417 , n71432 );
nand ( n71434 , n71392 , n71433 );
nor ( n71435 , n71365 , n71434 );
or ( n71436 , n71435 , n71016 );
nand ( n71437 , n71016 , n69607 );
nand ( n71438 , n71436 , n71437 );
buf ( n5300 , n71438 );
buf ( n71440 , 1'b0 );
not ( n71441 , n68838 );
buf ( n71442 , n71441 );
buf ( n5304 , n68634 );
not ( n71444 , n69358 );
not ( n71445 , n69618 );
not ( n71446 , n71445 );
nand ( n71447 , n69969 , n70100 );
not ( n71448 , n69981 );
nor ( n71449 , n71447 , n71448 );
not ( n71450 , n71449 );
or ( n71451 , n71446 , n71450 );
or ( n71452 , n71449 , n71445 );
nand ( n71453 , n71451 , n71452 );
not ( n71454 , n71453 );
or ( n71455 , n71444 , n71454 );
nand ( n71456 , n70098 , n69359 );
nand ( n71457 , n71455 , n71456 );
and ( n71458 , n71457 , n70923 );
not ( n71459 , n70929 );
nand ( n71460 , n71370 , n70362 );
not ( n71461 , n71460 );
not ( n71462 , n70321 );
nor ( n71463 , n71372 , n71462 );
not ( n71464 , n71463 );
not ( n71465 , n70957 );
or ( n71466 , n71464 , n71465 );
or ( n71467 , n71377 , n71462 );
not ( n71468 , n70358 );
nand ( n71469 , n71467 , n71468 );
not ( n71470 , n71469 );
nand ( n71471 , n71466 , n71470 );
not ( n71472 , n71471 );
or ( n71473 , n71461 , n71472 );
or ( n71474 , n71471 , n71460 );
nand ( n71475 , n71473 , n71474 );
not ( n71476 , n71475 );
or ( n71477 , n71459 , n71476 );
nand ( n71478 , n71395 , n71409 );
not ( n71479 , n71478 );
not ( n71480 , n70680 );
nor ( n71481 , n71480 , n71397 );
not ( n71482 , n71481 );
not ( n71483 , n70984 );
or ( n71484 , n71482 , n71483 );
not ( n71485 , n70799 );
nor ( n71486 , n71485 , n70787 );
nand ( n71487 , n71484 , n71486 );
not ( n71488 , n71487 );
or ( n71489 , n71479 , n71488 );
or ( n71490 , n71487 , n71478 );
nand ( n71491 , n71489 , n71490 );
and ( n71492 , n71491 , n70571 );
not ( n71493 , n70995 );
not ( n71494 , n71421 );
nand ( n71495 , n70827 , n70828 );
not ( n71496 , n71495 );
nand ( n71497 , n71496 , n71003 );
not ( n71498 , n71497 );
or ( n71499 , n71494 , n71498 );
or ( n71500 , n71497 , n71421 );
nand ( n71501 , n71499 , n71500 );
not ( n71502 , n71501 );
or ( n71503 , n71493 , n71502 );
nand ( n71504 , n70327 , n70847 );
nand ( n71505 , n71503 , n71504 );
nor ( n71506 , n71492 , n71505 );
nand ( n71507 , n71477 , n71506 );
nor ( n71508 , n71458 , n71507 );
or ( n71509 , n71508 , n71016 );
nand ( n71510 , n71016 , n69591 );
nand ( n71511 , n71509 , n71510 );
buf ( n71512 , n71511 );
buf ( n5374 , 1'b0 );
not ( n71514 , n68838 );
buf ( n71515 , n71514 );
buf ( n71516 , n68634 );
not ( n71517 , n69358 );
not ( n71518 , n70098 );
not ( n71519 , n70015 );
not ( n71520 , n70001 );
and ( n71521 , n70092 , n71519 , n71520 );
nand ( n71522 , n69971 , n71521 );
not ( n71523 , n71522 );
or ( n71524 , n71518 , n71523 );
or ( n71525 , n71522 , n70098 );
nand ( n71526 , n71524 , n71525 );
not ( n71527 , n71526 );
or ( n71528 , n71517 , n71527 );
not ( n71529 , n70000 );
not ( n71530 , n71529 );
nand ( n71531 , n71530 , n69359 );
nand ( n71532 , n71528 , n71531 );
and ( n71533 , n71532 , n70923 );
not ( n71534 , n70931 );
not ( n71535 , n70320 );
nand ( n71536 , n71535 , n70351 );
not ( n71537 , n71536 );
not ( n71538 , n70533 );
not ( n71539 , n70957 );
or ( n71540 , n71538 , n71539 );
nand ( n71541 , n71540 , n71377 );
not ( n71542 , n71541 );
or ( n71543 , n71537 , n71542 );
or ( n71544 , n71541 , n71536 );
nand ( n71545 , n71543 , n71544 );
not ( n71546 , n71545 );
or ( n71547 , n71534 , n71546 );
not ( n71548 , n70679 );
nand ( n71549 , n71548 , n70784 );
not ( n71550 , n71549 );
not ( n71551 , n70660 );
not ( n71552 , n70984 );
or ( n71553 , n71551 , n71552 );
nand ( n71554 , n71553 , n71402 );
not ( n71555 , n71554 );
or ( n71556 , n71550 , n71555 );
or ( n71557 , n71554 , n71549 );
nand ( n71558 , n71556 , n71557 );
and ( n71559 , n71558 , n70571 );
not ( n71560 , n70995 );
not ( n71561 , n70308 );
not ( n71562 , n71561 );
nand ( n71563 , n71003 , n70827 );
not ( n71564 , n71563 );
or ( n71565 , n71562 , n71564 );
or ( n71566 , n71563 , n71561 );
nand ( n71567 , n71565 , n71566 );
not ( n71568 , n71567 );
or ( n71569 , n71560 , n71568 );
nand ( n71570 , n70308 , n70847 );
nand ( n71571 , n71569 , n71570 );
nor ( n71572 , n71559 , n71571 );
nand ( n71573 , n71547 , n71572 );
nor ( n71574 , n71533 , n71573 );
or ( n71575 , n71574 , n71016 );
nand ( n71576 , n71016 , n69579 );
nand ( n71577 , n71575 , n71576 );
buf ( n5439 , n71577 );
buf ( n5440 , 1'b0 );
not ( n71580 , n68838 );
buf ( n71581 , n71580 );
buf ( n71582 , n68634 );
not ( n71583 , n69358 );
not ( n71584 , n69990 );
not ( n71585 , n71584 );
not ( n71586 , n70091 );
and ( n71587 , n71586 , n70014 );
nand ( n71588 , n69969 , n71587 );
not ( n71589 , n70000 );
nor ( n71590 , n71588 , n71589 );
not ( n71591 , n71590 );
or ( n71592 , n71585 , n71591 );
or ( n71593 , n71590 , n71584 );
nand ( n71594 , n71592 , n71593 );
not ( n71595 , n71594 );
or ( n71596 , n71583 , n71595 );
nand ( n71597 , n70013 , n69359 );
nand ( n71598 , n71596 , n71597 );
and ( n71599 , n71598 , n70196 );
not ( n71600 , n70931 );
nand ( n71601 , n70283 , n70286 );
not ( n71602 , n71601 );
not ( n71603 , n70398 );
nor ( n71604 , n71603 , n70372 );
not ( n71605 , n71604 );
not ( n71606 , n70957 );
or ( n71607 , n71605 , n71606 );
not ( n71608 , n70532 );
not ( n71609 , n70550 );
or ( n71610 , n71608 , n71609 );
not ( n71611 , n70266 );
nand ( n71612 , n71610 , n71611 );
not ( n71613 , n71612 );
nand ( n71614 , n71607 , n71613 );
not ( n71615 , n71614 );
or ( n71616 , n71602 , n71615 );
or ( n71617 , n71614 , n71601 );
nand ( n71618 , n71616 , n71617 );
not ( n71619 , n71618 );
or ( n71620 , n71600 , n71619 );
nand ( n71621 , n70653 , n70790 );
not ( n71622 , n71621 );
not ( n71623 , n70658 );
nor ( n71624 , n71623 , n70642 );
not ( n71625 , n71624 );
not ( n71626 , n70984 );
or ( n71627 , n71625 , n71626 );
not ( n71628 , n70658 );
nand ( n71629 , n70797 , n70793 );
not ( n71630 , n71629 );
or ( n71631 , n71628 , n71630 );
nand ( n71632 , n71631 , n70792 );
not ( n71633 , n71632 );
nand ( n71634 , n71627 , n71633 );
not ( n71635 , n71634 );
or ( n71636 , n71622 , n71635 );
or ( n71637 , n71634 , n71621 );
nand ( n71638 , n71636 , n71637 );
and ( n71639 , n71638 , n70571 );
not ( n71640 , n70995 );
not ( n71641 , n70826 );
and ( n71642 , n70824 , n70825 );
nand ( n71643 , n71003 , n71642 );
not ( n71644 , n71643 );
or ( n71645 , n71641 , n71644 );
or ( n71646 , n71643 , n70826 );
nand ( n71647 , n71645 , n71646 );
not ( n71648 , n71647 );
or ( n71649 , n71640 , n71648 );
nand ( n71650 , n70273 , n70847 );
nand ( n71651 , n71649 , n71650 );
nor ( n71652 , n71639 , n71651 );
nand ( n71653 , n71620 , n71652 );
nor ( n71654 , n71599 , n71653 );
or ( n71655 , n71654 , n71016 );
nand ( n71656 , n71016 , n69509 );
nand ( n71657 , n71655 , n71656 );
buf ( n71658 , n71657 );
buf ( n71659 , 1'b0 );
not ( n71660 , n68838 );
buf ( n71661 , n71660 );
buf ( n71662 , n68634 );
not ( n71663 , n69358 );
not ( n71664 , n70000 );
not ( n71665 , n71588 );
or ( n71666 , n71664 , n71665 );
or ( n71667 , n71588 , n70000 );
nand ( n71668 , n71666 , n71667 );
not ( n71669 , n71668 );
or ( n71670 , n71663 , n71669 );
nand ( n71671 , n70007 , n69359 );
nand ( n71672 , n71670 , n71671 );
and ( n71673 , n71672 , n70196 );
not ( n71674 , n70929 );
nand ( n71675 , n70532 , n71611 );
not ( n71676 , n71675 );
not ( n71677 , n70398 );
not ( n71678 , n70957 );
or ( n71679 , n71677 , n71678 );
not ( n71680 , n70550 );
nand ( n71681 , n71679 , n71680 );
not ( n71682 , n71681 );
or ( n71683 , n71676 , n71682 );
or ( n71684 , n71681 , n71675 );
nand ( n71685 , n71683 , n71684 );
not ( n71686 , n71685 );
or ( n71687 , n71674 , n71686 );
nand ( n71688 , n70658 , n70792 );
not ( n71689 , n71688 );
not ( n71690 , n70642 );
not ( n71691 , n71690 );
not ( n71692 , n70984 );
or ( n71693 , n71691 , n71692 );
not ( n71694 , n71629 );
nand ( n71695 , n71693 , n71694 );
not ( n71696 , n71695 );
or ( n71697 , n71689 , n71696 );
or ( n71698 , n71695 , n71688 );
nand ( n71699 , n71697 , n71698 );
and ( n71700 , n71699 , n70571 );
not ( n71701 , n70995 );
not ( n71702 , n70825 );
nand ( n71703 , n71003 , n70824 );
not ( n71704 , n71703 );
or ( n71705 , n71702 , n71704 );
or ( n71706 , n71703 , n70825 );
nand ( n71707 , n71705 , n71706 );
not ( n71708 , n71707 );
or ( n71709 , n71701 , n71708 );
nand ( n71710 , n70253 , n70847 );
nand ( n71711 , n71709 , n71710 );
nor ( n71712 , n71700 , n71711 );
nand ( n71713 , n71687 , n71712 );
nor ( n71714 , n71673 , n71713 );
or ( n71715 , n71714 , n71016 );
nand ( n71716 , n71016 , n69524 );
nand ( n71717 , n71715 , n71716 );
buf ( n71718 , n71717 );
buf ( n71719 , 1'b0 );
not ( n71720 , n68838 );
buf ( n5582 , n71720 );
buf ( n71722 , n68634 );
nand ( n71723 , n70146 , n70860 );
nor ( n71724 , n70136 , n71723 );
not ( n71725 , n71724 );
and ( n71726 , n71725 , n2667 );
not ( n71727 , n71725 );
and ( n71728 , n71727 , n70007 );
or ( n71729 , n71726 , n71728 );
buf ( n5591 , n71729 );
buf ( n5592 , 1'b0 );
not ( n71732 , n68838 );
buf ( n5594 , n71732 );
buf ( n5595 , n68634 );
and ( n71735 , n71725 , n2623 );
not ( n71736 , n71725 );
and ( n71737 , n71736 , n69947 );
or ( n71738 , n71735 , n71737 );
buf ( n71739 , n71738 );
buf ( n5601 , 1'b0 );
not ( n71741 , n68838 );
buf ( n71742 , n71741 );
buf ( n5604 , n68634 );
and ( n71744 , n71725 , n68770 );
not ( n71745 , n71725 );
not ( n71746 , n69627 );
not ( n71747 , n71746 );
nand ( n71748 , n69896 , n69871 );
nor ( n71749 , n71748 , n69793 );
nand ( n71750 , n71029 , n71749 );
not ( n71751 , n71750 );
not ( n71752 , n69932 );
not ( n71753 , n69850 );
nor ( n71754 , n71752 , n71753 );
not ( n71755 , n71754 );
not ( n71756 , n69685 );
nor ( n71757 , n71755 , n71756 );
nand ( n71758 , n71747 , n71751 , n71757 );
not ( n71759 , n69706 );
and ( n71760 , n71758 , n71759 );
not ( n71761 , n71758 );
and ( n71762 , n71761 , n69706 );
nor ( n71763 , n71760 , n71762 );
and ( n71764 , n71745 , n71763 );
or ( n71765 , n71744 , n71764 );
buf ( n71766 , n71765 );
buf ( n71767 , 1'b0 );
not ( n71768 , n68838 );
buf ( n71769 , n71768 );
buf ( n5631 , n68634 );
and ( n71771 , n71725 , n2633 );
not ( n71772 , n71725 );
not ( n71773 , n71755 );
nand ( n71774 , n71773 , n71751 , n69627 );
and ( n71775 , n71774 , n71756 );
not ( n71776 , n71774 );
and ( n71777 , n71776 , n69685 );
nor ( n71778 , n71775 , n71777 );
not ( n71779 , n71778 );
not ( n71780 , n71779 );
and ( n71781 , n71772 , n71780 );
or ( n71782 , n71771 , n71781 );
buf ( n5644 , n71782 );
buf ( n5645 , 1'b0 );
not ( n71785 , n68838 );
buf ( n71786 , n71785 );
buf ( n71787 , n68634 );
and ( n71788 , n71725 , n2635 );
not ( n71789 , n71725 );
not ( n71790 , n69627 );
not ( n71791 , n71790 );
nand ( n71792 , n71791 , n71751 , n69932 );
and ( n71793 , n71792 , n71753 );
not ( n71794 , n71792 );
not ( n71795 , n71753 );
and ( n71796 , n71794 , n71795 );
nor ( n71797 , n71793 , n71796 );
not ( n71798 , n71797 );
not ( n71799 , n71798 );
and ( n71800 , n71789 , n71799 );
or ( n71801 , n71788 , n71800 );
buf ( n71802 , n71801 );
buf ( n5664 , 1'b0 );
not ( n71804 , n68838 );
buf ( n71805 , n71804 );
buf ( n71806 , n68634 );
and ( n71807 , n71725 , n2637 );
not ( n71808 , n71725 );
nand ( n71809 , n71751 , n69627 );
not ( n71810 , n69932 );
and ( n71811 , n71809 , n71810 );
not ( n71812 , n71809 );
and ( n71813 , n71812 , n69932 );
nor ( n71814 , n71811 , n71813 );
and ( n71815 , n71808 , n71814 );
or ( n71816 , n71807 , n71815 );
buf ( n71817 , n71816 );
buf ( n71818 , 1'b0 );
not ( n71819 , n68838 );
buf ( n5681 , n71819 );
buf ( n5682 , n68634 );
and ( n71822 , n71725 , n2639 );
not ( n71823 , n71725 );
not ( n71824 , n71748 );
nand ( n71825 , n71824 , n69792 );
nor ( n71826 , n71030 , n71825 );
nand ( n71827 , n69627 , n71826 );
not ( n71828 , n69769 );
and ( n71829 , n71827 , n71828 );
not ( n71830 , n71827 );
and ( n71831 , n71830 , n69769 );
nor ( n71832 , n71829 , n71831 );
not ( n71833 , n71832 );
not ( n71834 , n71833 );
and ( n71835 , n71823 , n71834 );
or ( n71836 , n71822 , n71835 );
buf ( n71837 , n71836 );
buf ( n71838 , 1'b0 );
not ( n71839 , n68838 );
buf ( n5701 , n71839 );
buf ( n5702 , n68634 );
not ( n71842 , n71725 );
not ( n71843 , n71842 );
and ( n71844 , n71843 , n68780 );
not ( n71845 , n71843 );
nor ( n71846 , n71030 , n71748 );
nand ( n71847 , n69627 , n71846 );
not ( n71848 , n69792 );
and ( n71849 , n71847 , n71848 );
not ( n71850 , n71847 );
and ( n71851 , n71850 , n69792 );
nor ( n71852 , n71849 , n71851 );
and ( n71853 , n71845 , n71852 );
or ( n71854 , n71844 , n71853 );
buf ( n71855 , n71854 );
buf ( n71856 , 1'b0 );
not ( n71857 , n68838 );
buf ( n71858 , n71857 );
buf ( n71859 , n68634 );
and ( n71860 , n71725 , n2643 );
not ( n71861 , n71725 );
not ( n71862 , n69896 );
and ( n71863 , n71029 , n69871 );
nand ( n71864 , n71863 , n69627 );
not ( n71865 , n71864 );
or ( n71866 , n71862 , n71865 );
nand ( n71867 , n69627 , n71863 );
or ( n71868 , n71867 , n69896 );
nand ( n71869 , n71866 , n71868 );
and ( n71870 , n71861 , n71869 );
or ( n71871 , n71860 , n71870 );
buf ( n71872 , n71871 );
buf ( n5734 , 1'b0 );
not ( n71874 , n68838 );
buf ( n71875 , n71874 );
buf ( n71876 , n68634 );
and ( n71877 , n71843 , n68784 );
not ( n71878 , n71843 );
and ( n71879 , n71878 , n71037 );
or ( n71880 , n71877 , n71879 );
buf ( n5742 , n71880 );
buf ( n71882 , 1'b0 );
not ( n71883 , n68838 );
buf ( n5745 , n71883 );
buf ( n71885 , n68634 );
and ( n71886 , n71843 , n68786 );
not ( n71887 , n71843 );
and ( n71888 , n71887 , n71058 );
or ( n71889 , n71886 , n71888 );
buf ( n5751 , n71889 );
buf ( n5752 , 1'b0 );
not ( n71892 , n68838 );
buf ( n5754 , n71892 );
buf ( n5755 , n68634 );
and ( n71895 , n71843 , n2649 );
not ( n71896 , n71843 );
and ( n71897 , n71896 , n71047 );
or ( n71898 , n71895 , n71897 );
buf ( n71899 , n71898 );
buf ( n71900 , 1'b0 );
not ( n71901 , n68838 );
buf ( n71902 , n71901 );
buf ( n71903 , n68634 );
and ( n71904 , n71843 , n2651 );
not ( n71905 , n71843 );
and ( n71906 , n71905 , n69660 );
or ( n71907 , n71904 , n71906 );
buf ( n71908 , n71907 );
buf ( n71909 , 1'b0 );
not ( n71910 , n68838 );
buf ( n71911 , n71910 );
buf ( n71912 , n68634 );
and ( n71913 , n71843 , n2653 );
not ( n71914 , n71843 );
and ( n71915 , n71914 , n69977 );
or ( n71916 , n71913 , n71915 );
buf ( n71917 , n71916 );
buf ( n71918 , 1'b0 );
not ( n71919 , n68838 );
buf ( n71920 , n71919 );
buf ( n71921 , n68634 );
and ( n71922 , n71725 , n68794 );
not ( n71923 , n71725 );
and ( n71924 , n71923 , n69620 );
or ( n71925 , n71922 , n71924 );
buf ( n71926 , n71925 );
buf ( n71927 , 1'b0 );
not ( n71928 , n68838 );
buf ( n71929 , n71928 );
buf ( n71930 , n68634 );
and ( n71931 , n71725 , n68796 );
not ( n71932 , n71725 );
and ( n71933 , n71932 , n69981 );
or ( n71934 , n71931 , n71933 );
buf ( n71935 , n71934 );
buf ( n71936 , 1'b0 );
not ( n71937 , n68838 );
buf ( n71938 , n71937 );
buf ( n71939 , n68634 );
and ( n71940 , n71725 , n2659 );
not ( n71941 , n71725 );
and ( n71942 , n71941 , n70098 );
or ( n71943 , n71940 , n71942 );
buf ( n71944 , n71943 );
buf ( n71945 , 1'b0 );
not ( n71946 , n68838 );
buf ( n71947 , n71946 );
buf ( n71948 , n68634 );
and ( n71949 , n71725 , n68800 );
not ( n71950 , n71725 );
and ( n71951 , n71950 , n69990 );
or ( n71952 , n71949 , n71951 );
buf ( n71953 , n71952 );
buf ( n71954 , 1'b0 );
not ( n71955 , n68838 );
buf ( n71956 , n71955 );
buf ( n71957 , n68634 );
and ( n71958 , n71725 , n2663 );
not ( n71959 , n71725 );
and ( n71960 , n71959 , n71530 );
or ( n71961 , n71958 , n71960 );
buf ( n71962 , n71961 );
buf ( n71963 , 1'b0 );
not ( n71964 , n68838 );
buf ( n71965 , n71964 );
buf ( n71966 , n68634 );
and ( n71967 , n71725 , n2665 );
not ( n71968 , n71725 );
and ( n71969 , n71968 , n70013 );
or ( n71970 , n71967 , n71969 );
buf ( n71971 , n71970 );
buf ( n71972 , 1'b0 );
not ( n71973 , n68838 );
buf ( n71974 , n71973 );
buf ( n71975 , n68634 );
buf ( n71976 , n70859 );
buf ( n71977 , 1'b0 );
not ( n71978 , n68838 );
buf ( n71979 , n71978 );
buf ( n71980 , n68634 );
not ( n71981 , n70922 );
nand ( n71982 , n70164 , n70180 , n70863 );
and ( n71983 , n70207 , n70139 );
nand ( n71984 , n70136 , n70196 , n71983 );
nor ( n71985 , n71982 , n71984 );
not ( n71986 , n71985 );
or ( n71987 , n71981 , n71986 );
not ( n71988 , n70862 );
nor ( n71989 , n71988 , n71982 );
nand ( n71990 , n71989 , n70571 );
nand ( n71991 , n71989 , n70566 );
not ( n71992 , n70139 );
nor ( n71993 , n71985 , n71992 );
nand ( n71994 , n71990 , n71991 , n71993 );
not ( n71995 , n71994 );
not ( n71996 , n70847 );
not ( n71997 , n71989 );
or ( n71998 , n71996 , n71997 );
nand ( n71999 , n71998 , n70875 );
nand ( n72000 , n70136 , n70872 , n71983 );
nor ( n72001 , n71982 , n72000 );
nor ( n72002 , n71999 , n72001 );
nand ( n72003 , n71995 , n72002 );
not ( n72004 , n72003 );
and ( n72005 , n70883 , n69537 );
not ( n72006 , n70883 );
and ( n72007 , n72006 , n70884 );
nor ( n72008 , n72005 , n72007 );
not ( n72009 , n72008 );
and ( n72010 , n72004 , n72009 );
not ( n72011 , n71991 );
and ( n72012 , n70965 , n72011 );
nor ( n72013 , n72010 , n72012 );
not ( n72014 , n71990 );
and ( n72015 , n70992 , n72014 );
not ( n72016 , n72001 );
not ( n72017 , n72016 );
nand ( n72018 , n71008 , n72017 );
nand ( n72019 , n71999 , n70263 );
nand ( n72020 , n69537 , n70859 );
nand ( n72021 , n72018 , n72019 , n72020 );
nor ( n72022 , n72015 , n72021 );
and ( n72023 , n72013 , n72022 );
nand ( n72024 , n71987 , n72023 );
buf ( n72025 , n72024 );
buf ( n72026 , 1'b0 );
not ( n72027 , n68838 );
buf ( n5889 , n72027 );
buf ( n72029 , n68634 );
not ( n72030 , n69358 );
not ( n72031 , n70007 );
nand ( n72032 , n69971 , n70092 );
not ( n72033 , n72032 );
or ( n72034 , n72031 , n72033 );
or ( n72035 , n72032 , n70007 );
nand ( n72036 , n72034 , n72035 );
not ( n72037 , n72036 );
or ( n72038 , n72030 , n72037 );
nand ( n72039 , n70090 , n71272 );
nand ( n72040 , n72038 , n72039 );
not ( n72041 , n72040 );
or ( n72042 , n72041 , n71986 );
nand ( n72043 , n70641 , n70987 );
not ( n72044 , n72043 );
not ( n72045 , n70984 );
or ( n72046 , n72044 , n72045 );
or ( n72047 , n70984 , n72043 );
nand ( n72048 , n72046 , n72047 );
nand ( n72049 , n72048 , n72014 );
nand ( n72050 , n70392 , n70960 );
not ( n72051 , n72050 );
not ( n72052 , n70957 );
or ( n72053 , n72051 , n72052 );
or ( n72054 , n70957 , n72050 );
nand ( n72055 , n72053 , n72054 );
nand ( n72056 , n72055 , n72011 );
not ( n72057 , n72003 );
and ( n72058 , n70882 , n69549 );
not ( n72059 , n70882 );
not ( n72060 , n69549 );
and ( n72061 , n72059 , n72060 );
nor ( n72062 , n72058 , n72061 );
nand ( n72063 , n72057 , n72062 );
nand ( n72064 , n71999 , n70378 );
not ( n72065 , n70378 );
not ( n72066 , n71003 );
or ( n72067 , n72065 , n72066 );
or ( n72068 , n71003 , n70378 );
nand ( n72069 , n72067 , n72068 );
nand ( n72070 , n72069 , n72017 );
not ( n72071 , n70859 );
nor ( n72072 , n72060 , n72071 );
not ( n72073 , n72072 );
and ( n72074 , n72064 , n72070 , n72073 );
and ( n72075 , n72049 , n72056 , n72063 , n72074 );
nand ( n72076 , n72042 , n72075 );
buf ( n72077 , n72076 );
buf ( n72078 , 1'b0 );
not ( n72079 , n68838 );
buf ( n72080 , n72079 );
buf ( n72081 , n68634 );
and ( n72082 , n71272 , n70031 );
not ( n72083 , n71272 );
not ( n72084 , n70082 );
not ( n72085 , n72084 );
nand ( n72086 , n69971 , n70076 );
not ( n72087 , n70090 );
nor ( n72088 , n72086 , n72087 );
not ( n72089 , n72088 );
or ( n72090 , n72085 , n72089 );
or ( n72091 , n72088 , n72084 );
nand ( n72092 , n72090 , n72091 );
and ( n72093 , n72083 , n72092 );
nor ( n72094 , n72082 , n72093 );
or ( n72095 , n72094 , n71986 );
not ( n72096 , n70480 );
nand ( n72097 , n72096 , n70541 );
not ( n72098 , n72097 );
not ( n72099 , n70495 );
nor ( n72100 , n70936 , n72099 );
not ( n72101 , n72100 );
not ( n72102 , n70947 );
or ( n72103 , n72101 , n72102 );
not ( n72104 , n70950 );
or ( n72105 , n72104 , n72099 );
nand ( n72106 , n72105 , n70488 );
not ( n72107 , n72106 );
nand ( n72108 , n72103 , n72107 );
not ( n72109 , n72108 );
or ( n72110 , n72098 , n72109 );
or ( n72111 , n72108 , n72097 );
nand ( n72112 , n72110 , n72111 );
nand ( n72113 , n72112 , n72011 );
nand ( n72114 , n70617 , n70611 );
not ( n72115 , n72114 );
not ( n72116 , n70616 );
nor ( n72117 , n72116 , n70971 );
not ( n72118 , n72117 );
not ( n72119 , n70978 );
or ( n72120 , n72118 , n72119 );
not ( n72121 , n70616 );
not ( n72122 , n70769 );
or ( n72123 , n72121 , n72122 );
nand ( n72124 , n72123 , n70597 );
not ( n72125 , n72124 );
nand ( n72126 , n72120 , n72125 );
not ( n72127 , n72126 );
or ( n72128 , n72115 , n72127 );
or ( n72129 , n72126 , n72114 );
nand ( n72130 , n72128 , n72129 );
nand ( n72131 , n72130 , n72014 );
and ( n72132 , n70880 , n70881 );
not ( n72133 , n70880 );
and ( n72134 , n72133 , n3324 );
nor ( n72135 , n72132 , n72134 );
nand ( n72136 , n72057 , n72135 );
and ( n72137 , n71999 , n70388 );
nor ( n72138 , n70881 , n72071 );
not ( n72139 , n72138 );
not ( n72140 , n70388 );
not ( n72141 , n71000 );
not ( n72142 , n70432 );
not ( n72143 , n70818 );
nand ( n72144 , n72142 , n72143 );
or ( n72145 , n72144 , n70477 );
nor ( n72146 , n72141 , n72145 );
not ( n72147 , n72146 );
or ( n72148 , n72140 , n72147 );
or ( n72149 , n72146 , n70388 );
nand ( n72150 , n72148 , n72149 );
nand ( n72151 , n72150 , n72017 );
nand ( n72152 , n72139 , n72151 );
nor ( n72153 , n72137 , n72152 );
and ( n72154 , n72113 , n72131 , n72136 , n72153 );
nand ( n72155 , n72095 , n72154 );
buf ( n6017 , n72155 );
buf ( n72157 , 1'b0 );
not ( n72158 , n68838 );
buf ( n72159 , n72158 );
buf ( n6021 , n68634 );
and ( n72161 , n69359 , n70024 );
not ( n72162 , n69359 );
not ( n72163 , n70090 );
not ( n72164 , n72086 );
or ( n72165 , n72163 , n72164 );
or ( n72166 , n72086 , n70090 );
nand ( n72167 , n72165 , n72166 );
and ( n72168 , n72162 , n72167 );
nor ( n72169 , n72161 , n72168 );
or ( n72170 , n72169 , n71986 );
nand ( n72171 , n70616 , n70597 );
not ( n72172 , n72171 );
not ( n72173 , n70769 );
nand ( n72174 , n72173 , n70762 );
not ( n72175 , n72174 );
or ( n72176 , n72172 , n72175 );
or ( n72177 , n72174 , n72171 );
nand ( n72178 , n72176 , n72177 );
nand ( n72179 , n72178 , n72014 );
not ( n72180 , n72099 );
nand ( n72181 , n72180 , n70488 );
not ( n72182 , n72181 );
nor ( n72183 , n70936 , n70462 );
not ( n72184 , n72183 );
not ( n72185 , n70530 );
or ( n72186 , n72184 , n72185 );
nand ( n72187 , n72186 , n72104 );
not ( n72188 , n72187 );
or ( n72189 , n72182 , n72188 );
or ( n72190 , n72187 , n72181 );
nand ( n72191 , n72189 , n72190 );
nand ( n72192 , n72191 , n72011 );
and ( n72193 , n70879 , n3288 );
not ( n72194 , n70879 );
not ( n72195 , n3288 );
and ( n72196 , n72194 , n72195 );
nor ( n72197 , n72193 , n72196 );
nand ( n72198 , n72057 , n72197 );
and ( n72199 , n71999 , n70477 );
nor ( n72200 , n72195 , n72071 );
not ( n72201 , n72200 );
not ( n72202 , n70477 );
nor ( n72203 , n72141 , n72144 );
not ( n72204 , n72203 );
or ( n72205 , n72202 , n72204 );
or ( n72206 , n72203 , n70477 );
nand ( n72207 , n72205 , n72206 );
nand ( n72208 , n72207 , n72017 );
nand ( n72209 , n72201 , n72208 );
nor ( n72210 , n72199 , n72209 );
and ( n72211 , n72179 , n72192 , n72198 , n72210 );
nand ( n72212 , n72170 , n72211 );
buf ( n72213 , n72212 );
buf ( n72214 , 1'b0 );
not ( n72215 , n68838 );
buf ( n6077 , n72215 );
buf ( n72217 , n68634 );
and ( n72218 , n71272 , n70038 );
not ( n72219 , n71272 );
not ( n72220 , n70031 );
not ( n72221 , n70075 );
nand ( n72222 , n72221 , n69971 );
not ( n72223 , n72222 );
nand ( n72224 , n72223 , n70024 );
not ( n72225 , n72224 );
or ( n72226 , n72220 , n72225 );
or ( n72227 , n72224 , n70031 );
nand ( n72228 , n72226 , n72227 );
and ( n72229 , n72219 , n72228 );
nor ( n72230 , n72218 , n72229 );
or ( n72231 , n72230 , n71986 );
nand ( n72232 , n70539 , n70542 );
not ( n72233 , n72232 );
not ( n72234 , n70426 );
not ( n72235 , n72234 );
not ( n72236 , n70947 );
or ( n72237 , n72235 , n72236 );
nand ( n72238 , n72237 , n70535 );
not ( n72239 , n72238 );
or ( n72240 , n72233 , n72239 );
or ( n72241 , n72238 , n72232 );
nand ( n72242 , n72240 , n72241 );
nand ( n72243 , n72242 , n72011 );
nand ( n72244 , n70745 , n70768 );
not ( n72245 , n72244 );
not ( n72246 , n70759 );
not ( n72247 , n70978 );
or ( n72248 , n72246 , n72247 );
not ( n72249 , n70763 );
nand ( n72250 , n72248 , n72249 );
not ( n72251 , n72250 );
or ( n72252 , n72245 , n72251 );
or ( n72253 , n72250 , n72244 );
nand ( n72254 , n72252 , n72253 );
nand ( n72255 , n72254 , n72014 );
and ( n72256 , n70878 , n70877 );
not ( n72257 , n70878 );
and ( n72258 , n72257 , n3356 );
nor ( n72259 , n72256 , n72258 );
nand ( n72260 , n72057 , n72259 );
and ( n72261 , n71999 , n70432 );
nor ( n72262 , n70877 , n72071 );
not ( n72263 , n72262 );
not ( n72264 , n70432 );
nor ( n72265 , n72141 , n70818 );
not ( n72266 , n72265 );
or ( n72267 , n72264 , n72266 );
or ( n72268 , n72265 , n70432 );
nand ( n72269 , n72267 , n72268 );
nand ( n72270 , n72269 , n72017 );
nand ( n72271 , n72263 , n72270 );
nor ( n72272 , n72261 , n72271 );
and ( n72273 , n72243 , n72255 , n72260 , n72272 );
nand ( n72274 , n72231 , n72273 );
buf ( n6136 , n72274 );
buf ( n6137 , 1'b0 );
not ( n72277 , n68838 );
buf ( n72278 , n72277 );
buf ( n72279 , n68634 );
not ( n72280 , n69358 );
not ( n72281 , n70024 );
not ( n72282 , n72222 );
or ( n72283 , n72281 , n72282 );
or ( n72284 , n72222 , n70024 );
nand ( n72285 , n72283 , n72284 );
not ( n72286 , n72285 );
or ( n72287 , n72280 , n72286 );
nand ( n72288 , n70040 , n71272 );
nand ( n72289 , n72287 , n72288 );
not ( n72290 , n72289 );
or ( n72291 , n72290 , n71986 );
nand ( n72292 , n72234 , n70535 );
xnor ( n72293 , n70947 , n72292 );
nand ( n72294 , n72293 , n72011 );
nand ( n72295 , n70759 , n72249 );
not ( n72296 , n72295 );
not ( n72297 , n70978 );
or ( n72298 , n72296 , n72297 );
or ( n72299 , n70978 , n72295 );
nand ( n72300 , n72298 , n72299 );
nand ( n72301 , n72300 , n72014 );
not ( n72302 , n70817 );
and ( n72303 , n71999 , n72302 );
and ( n72304 , n71000 , n72143 );
not ( n72305 , n71000 );
and ( n72306 , n72305 , n70818 );
nor ( n72307 , n72304 , n72306 );
not ( n72308 , n72307 );
not ( n72309 , n72017 );
or ( n72310 , n72308 , n72309 );
nand ( n72311 , n3344 , n70859 );
nand ( n72312 , n72310 , n72311 );
nor ( n72313 , n72303 , n72312 );
nand ( n72314 , n72294 , n72301 , n72313 );
not ( n72315 , n3344 );
and ( n72316 , n72315 , n3304 );
not ( n72317 , n3304 );
and ( n72318 , n72317 , n3344 );
nor ( n72319 , n72316 , n72318 );
nor ( n72320 , n72003 , n72319 );
nor ( n72321 , n72314 , n72320 );
nand ( n72322 , n72291 , n72321 );
buf ( n6184 , n72322 );
buf ( n6185 , 1'b0 );
not ( n72325 , n68838 );
buf ( n72326 , n72325 );
buf ( n72327 , n68634 );
and ( n72328 , n69359 , n70073 );
not ( n72329 , n69359 );
not ( n72330 , n70073 );
nand ( n72331 , n69969 , n70053 );
nor ( n72332 , n72330 , n72331 );
nand ( n72333 , n72332 , n70040 );
not ( n72334 , n70038 );
and ( n72335 , n72333 , n72334 );
not ( n72336 , n72333 );
and ( n72337 , n72336 , n70038 );
nor ( n72338 , n72335 , n72337 );
and ( n72339 , n72329 , n72338 );
nor ( n72340 , n72328 , n72339 );
or ( n72341 , n72340 , n71986 );
not ( n72342 , n70940 );
nand ( n72343 , n72342 , n70528 );
nand ( n72344 , n70463 , n70527 );
xnor ( n72345 , n72343 , n72344 );
and ( n72346 , n72345 , n72011 );
and ( n72347 , n71999 , n70420 );
nor ( n72348 , n72346 , n72347 );
not ( n72349 , n70974 );
nand ( n72350 , n72349 , n70733 );
not ( n72351 , n72350 );
nand ( n72352 , n70761 , n70732 );
not ( n72353 , n72352 );
or ( n72354 , n72351 , n72353 );
or ( n72355 , n72352 , n72350 );
nand ( n72356 , n72354 , n72355 );
and ( n72357 , n72356 , n72014 );
not ( n72358 , n72017 );
not ( n72359 , n70420 );
not ( n72360 , n70831 );
nor ( n72361 , n72360 , n70459 );
not ( n72362 , n72361 );
or ( n72363 , n72359 , n72362 );
or ( n72364 , n72361 , n70420 );
nand ( n72365 , n72363 , n72364 );
not ( n72366 , n72365 );
or ( n72367 , n72358 , n72366 );
nor ( n72368 , n72317 , n72071 );
not ( n72369 , n72368 );
nand ( n72370 , n72367 , n72369 );
nor ( n72371 , n72357 , n72370 );
nand ( n72372 , n72057 , n72317 );
and ( n72373 , n72348 , n72371 , n72372 );
nand ( n72374 , n72341 , n72373 );
buf ( n72375 , n72374 );
buf ( n72376 , 1'b0 );
not ( n72377 , n68838 );
buf ( n72378 , n72377 );
buf ( n72379 , n68634 );
and ( n72380 , n71272 , n70053 );
not ( n72381 , n71272 );
xor ( n72382 , n70040 , n72332 );
and ( n72383 , n72381 , n72382 );
nor ( n72384 , n72380 , n72383 );
or ( n72385 , n72384 , n71986 );
nand ( n72386 , n72003 , n72071 );
and ( n72387 , n72386 , n3915 );
not ( n72388 , n72016 );
not ( n72389 , n70459 );
not ( n72390 , n70831 );
or ( n72391 , n72389 , n72390 );
or ( n72392 , n70831 , n70459 );
nand ( n72393 , n72391 , n72392 );
not ( n72394 , n72393 );
not ( n72395 , n72394 );
and ( n72396 , n72388 , n72395 );
not ( n72397 , n70516 );
nand ( n72398 , n72397 , n70528 );
not ( n72399 , n72398 );
or ( n72400 , n70507 , n70524 );
nand ( n72401 , n72400 , n70518 );
not ( n72402 , n72401 );
or ( n72403 , n72399 , n72402 );
or ( n72404 , n72398 , n72401 );
nand ( n72405 , n72403 , n72404 );
and ( n72406 , n72405 , n72011 );
nor ( n72407 , n72396 , n72406 );
not ( n72408 , n71999 );
not ( n72409 , n72408 );
not ( n72410 , n70459 );
not ( n72411 , n72410 );
and ( n72412 , n72409 , n72411 );
not ( n72413 , n70727 );
nand ( n72414 , n70716 , n70733 );
not ( n72415 , n72414 );
or ( n72416 , n72413 , n72415 );
or ( n72417 , n72414 , n70727 );
nand ( n72418 , n72416 , n72417 );
and ( n72419 , n72418 , n72014 );
nor ( n72420 , n72412 , n72419 );
nand ( n72421 , n72407 , n72420 );
nor ( n72422 , n72387 , n72421 );
nand ( n72423 , n72385 , n72422 );
buf ( n72424 , n72423 );
buf ( n72425 , 1'b0 );
not ( n72426 , n68838 );
buf ( n72427 , n72426 );
buf ( n72428 , n68634 );
and ( n72429 , n71272 , n71763 );
not ( n72430 , n71272 );
not ( n72431 , n71814 );
nand ( n72432 , n71852 , n71832 );
nor ( n72433 , n72431 , n72432 );
and ( n72434 , n71587 , n72433 , n71520 );
nand ( n72435 , n71037 , n71869 );
not ( n72436 , n72435 );
nand ( n72437 , n69660 , n71058 );
not ( n72438 , n72437 );
nand ( n72439 , n69977 , n70098 );
nor ( n72440 , n69982 , n72439 );
nand ( n72441 , n72436 , n72438 , n72440 , n71047 );
nor ( n72442 , n69970 , n72441 );
not ( n72443 , n71763 );
nand ( n72444 , n71797 , n71778 );
nor ( n72445 , n72443 , n72444 );
nand ( n72446 , n72434 , n72442 , n72445 );
not ( n72447 , n71746 );
not ( n72448 , n69707 );
nand ( n72449 , n72448 , n71754 );
not ( n72450 , n72449 );
nand ( n72451 , n72447 , n71751 , n72450 );
xnor ( n72452 , n72451 , n69729 );
not ( n72453 , n72452 );
nor ( n72454 , n72446 , n72453 );
not ( n72455 , n72454 );
not ( n72456 , n69743 );
not ( n72457 , n69729 );
nor ( n72458 , n72457 , n72449 );
nand ( n72459 , n72447 , n71751 , n72458 );
not ( n72460 , n72459 );
or ( n72461 , n72456 , n72460 );
or ( n72462 , n72459 , n69743 );
nand ( n72463 , n72461 , n72462 );
not ( n72464 , n72463 );
and ( n72465 , n72455 , n72464 );
not ( n72466 , n72455 );
and ( n72467 , n72466 , n72463 );
nor ( n72468 , n72465 , n72467 );
and ( n72469 , n72430 , n72468 );
nor ( n72470 , n72429 , n72469 );
or ( n72471 , n72470 , n71986 );
nor ( n72472 , n71131 , n71100 );
and ( n72473 , n72472 , n71085 );
nand ( n72474 , n70222 , n68646 );
not ( n72475 , n72474 );
not ( n72476 , n72475 );
not ( n72477 , n72476 );
not ( n72478 , n69896 );
not ( n72479 , n72478 );
or ( n72480 , n72477 , n72479 );
nand ( n72481 , n69896 , n72475 );
nand ( n72482 , n72480 , n72481 );
not ( n72483 , n69871 );
nand ( n72484 , n70222 , n2508 );
not ( n72485 , n72484 );
nor ( n72486 , n72483 , n72485 );
nor ( n72487 , n72482 , n72486 );
not ( n72488 , n72485 );
not ( n72489 , n69871 );
or ( n72490 , n72488 , n72489 );
not ( n72491 , n72485 );
not ( n72492 , n69871 );
nand ( n72493 , n72491 , n72492 );
nand ( n72494 , n72490 , n72493 );
nor ( n72495 , n71126 , n71122 );
nor ( n72496 , n72494 , n72495 );
nor ( n72497 , n72487 , n72496 );
nand ( n72498 , n70222 , n68645 );
not ( n72499 , n72498 );
not ( n72500 , n72499 );
not ( n72501 , n69792 );
or ( n72502 , n72500 , n72501 );
not ( n72503 , n72499 );
not ( n72504 , n69792 );
nand ( n72505 , n72503 , n72504 );
nand ( n72506 , n72502 , n72505 );
and ( n72507 , n69896 , n72476 );
nor ( n72508 , n72506 , n72507 );
nand ( n72509 , n70222 , n68644 );
not ( n72510 , n72509 );
not ( n72511 , n72510 );
not ( n72512 , n69769 );
or ( n72513 , n72511 , n72512 );
not ( n72514 , n69769 );
not ( n72515 , n72510 );
nand ( n72516 , n72514 , n72515 );
nand ( n72517 , n72513 , n72516 );
nor ( n72518 , n72504 , n72499 );
nor ( n72519 , n72517 , n72518 );
nor ( n72520 , n72508 , n72519 );
and ( n72521 , n72497 , n72520 );
nand ( n72522 , n72473 , n72521 );
and ( n72523 , n70222 , n2501 );
not ( n72524 , n72523 );
not ( n72525 , n69706 );
or ( n72526 , n72524 , n72525 );
not ( n72527 , n72523 );
not ( n72528 , n69706 );
nand ( n72529 , n72527 , n72528 );
nand ( n72530 , n72526 , n72529 );
not ( n72531 , n69685 );
not ( n72532 , n71070 );
nand ( n72533 , n72532 , n2502 );
not ( n72534 , n72533 );
nor ( n72535 , n72531 , n72534 );
nor ( n72536 , n72530 , n72535 );
not ( n72537 , n72534 );
not ( n72538 , n69685 );
or ( n72539 , n72537 , n72538 );
not ( n72540 , n72534 );
not ( n72541 , n69685 );
nand ( n72542 , n72540 , n72541 );
nand ( n72543 , n72539 , n72542 );
and ( n72544 , n70222 , n2503 );
not ( n72545 , n72544 );
and ( n72546 , n69850 , n72545 );
nor ( n72547 , n72543 , n72546 );
nor ( n72548 , n72536 , n72547 );
not ( n72549 , n72544 );
not ( n72550 , n69850 );
or ( n72551 , n72549 , n72550 );
not ( n72552 , n69850 );
nand ( n72553 , n72552 , n72545 );
nand ( n72554 , n72551 , n72553 );
not ( n72555 , n69932 );
nand ( n72556 , n72532 , n2504 );
not ( n72557 , n72556 );
nor ( n72558 , n72555 , n72557 );
nor ( n72559 , n72554 , n72558 );
not ( n72560 , n72557 );
not ( n72561 , n69932 );
or ( n72562 , n72560 , n72561 );
not ( n72563 , n72557 );
not ( n72564 , n69932 );
nand ( n72565 , n72563 , n72564 );
nand ( n72566 , n72562 , n72565 );
and ( n72567 , n69769 , n72515 );
nor ( n72568 , n72566 , n72567 );
nor ( n72569 , n72559 , n72568 );
nand ( n72570 , n72548 , n72569 );
nor ( n72571 , n72522 , n72570 );
not ( n72572 , n72571 );
not ( n72573 , n70553 );
or ( n72574 , n72572 , n72573 );
not ( n72575 , n72570 );
not ( n72576 , n72575 );
not ( n72577 , n72521 );
not ( n72578 , n71109 );
not ( n72579 , n72472 );
or ( n72580 , n72578 , n72579 );
not ( n72581 , n71131 );
not ( n72582 , n71112 );
and ( n72583 , n72581 , n72582 );
nor ( n72584 , n72583 , n71132 );
nand ( n72585 , n72580 , n72584 );
not ( n72586 , n72585 );
or ( n72587 , n72577 , n72586 );
not ( n72588 , n72520 );
and ( n72589 , n72494 , n72495 );
not ( n72590 , n72589 );
not ( n72591 , n72487 );
not ( n72592 , n72591 );
or ( n72593 , n72590 , n72592 );
nand ( n72594 , n72482 , n72486 );
nand ( n72595 , n72593 , n72594 );
not ( n72596 , n72595 );
or ( n72597 , n72588 , n72596 );
nand ( n72598 , n72506 , n72507 );
nor ( n72599 , n72519 , n72598 );
and ( n72600 , n72517 , n72518 );
nor ( n72601 , n72599 , n72600 );
nand ( n72602 , n72597 , n72601 );
not ( n72603 , n72602 );
nand ( n72604 , n72587 , n72603 );
not ( n72605 , n72604 );
or ( n72606 , n72576 , n72605 );
not ( n72607 , n72548 );
nand ( n72608 , n72566 , n72567 );
or ( n72609 , n72559 , n72608 );
nand ( n72610 , n72554 , n72558 );
nand ( n72611 , n72609 , n72610 );
not ( n72612 , n72611 );
or ( n72613 , n72607 , n72612 );
not ( n72614 , n72536 );
nand ( n72615 , n72543 , n72546 );
not ( n72616 , n72615 );
and ( n72617 , n72614 , n72616 );
and ( n72618 , n72530 , n72535 );
nor ( n72619 , n72617 , n72618 );
nand ( n72620 , n72613 , n72619 );
not ( n72621 , n72620 );
nand ( n72622 , n72606 , n72621 );
not ( n72623 , n72622 );
nand ( n72624 , n72574 , n72623 );
nand ( n72625 , n70222 , n2500 );
not ( n72626 , n72625 );
not ( n72627 , n72626 );
not ( n72628 , n69729 );
not ( n72629 , n72628 );
not ( n72630 , n72629 );
or ( n72631 , n72627 , n72630 );
not ( n72632 , n72626 );
not ( n72633 , n72629 );
nand ( n72634 , n72632 , n72633 );
nand ( n72635 , n72631 , n72634 );
not ( n72636 , n69706 );
nor ( n72637 , n72636 , n72523 );
nor ( n72638 , n72635 , n72637 );
not ( n72639 , n72638 );
nand ( n72640 , n72635 , n72637 );
nand ( n72641 , n72639 , n72640 );
not ( n72642 , n72641 );
and ( n72643 , n72624 , n72642 );
not ( n72644 , n72624 );
and ( n72645 , n72644 , n72641 );
nor ( n72646 , n72643 , n72645 );
nand ( n72647 , n72646 , n72011 );
xor ( n72648 , n72523 , n69706 );
and ( n72649 , n69685 , n72534 );
nor ( n72650 , n72648 , n72649 );
not ( n72651 , n69685 );
not ( n72652 , n72534 );
not ( n72653 , n72652 );
or ( n72654 , n72651 , n72653 );
not ( n72655 , n69685 );
nand ( n72656 , n72655 , n72534 );
nand ( n72657 , n72654 , n72656 );
and ( n72658 , n72544 , n69850 );
nor ( n72659 , n72657 , n72658 );
nor ( n72660 , n72650 , n72659 );
xor ( n72661 , n72544 , n69850 );
and ( n72662 , n69932 , n72557 );
nor ( n72663 , n72661 , n72662 );
not ( n72664 , n72557 );
not ( n72665 , n72664 );
not ( n72666 , n69932 );
or ( n72667 , n72665 , n72666 );
not ( n72668 , n69932 );
nand ( n72669 , n72668 , n72557 );
nand ( n72670 , n72667 , n72669 );
and ( n72671 , n69769 , n72510 );
nor ( n72672 , n72670 , n72671 );
nor ( n72673 , n72663 , n72672 );
and ( n72674 , n72660 , n72673 );
not ( n72675 , n72674 );
not ( n72676 , n72475 );
not ( n72677 , n69896 );
not ( n72678 , n72677 );
or ( n72679 , n72676 , n72678 );
not ( n72680 , n72475 );
nand ( n72681 , n72680 , n69896 );
nand ( n72682 , n72679 , n72681 );
and ( n72683 , n69871 , n72485 );
nor ( n72684 , n72682 , n72683 );
not ( n72685 , n72684 );
not ( n72686 , n72485 );
not ( n72687 , n69871 );
not ( n72688 , n72687 );
or ( n72689 , n72686 , n72688 );
not ( n72690 , n72485 );
nand ( n72691 , n72690 , n69871 );
nand ( n72692 , n72689 , n72691 );
not ( n72693 , n72692 );
and ( n72694 , n69804 , n71122 );
not ( n72695 , n72694 );
nand ( n72696 , n72693 , n72695 );
nand ( n72697 , n72685 , n72696 );
not ( n72698 , n72697 );
not ( n72699 , n72499 );
not ( n72700 , n69792 );
not ( n72701 , n72700 );
or ( n72702 , n72699 , n72701 );
not ( n72703 , n72499 );
nand ( n72704 , n69792 , n72703 );
nand ( n72705 , n72702 , n72704 );
and ( n72706 , n69896 , n72475 );
nor ( n72707 , n72705 , n72706 );
not ( n72708 , n72510 );
not ( n72709 , n72708 );
not ( n72710 , n69769 );
or ( n72711 , n72709 , n72710 );
not ( n72712 , n69769 );
nand ( n72713 , n72712 , n72510 );
nand ( n72714 , n72711 , n72713 );
nand ( n72715 , n69792 , n72499 );
not ( n72716 , n72715 );
nor ( n72717 , n72714 , n72716 );
nor ( n72718 , n72707 , n72717 );
nand ( n72719 , n72698 , n72718 );
not ( n72720 , n72719 );
nor ( n72721 , n71169 , n71146 );
not ( n72722 , n72721 );
nor ( n72723 , n72722 , n71160 );
nand ( n72724 , n72720 , n72723 );
nor ( n72725 , n72675 , n72724 );
not ( n72726 , n72725 );
not ( n72727 , n70809 );
or ( n72728 , n72726 , n72727 );
nand ( n72729 , n72705 , n72706 );
or ( n72730 , n72717 , n72729 );
nand ( n72731 , n72714 , n72716 );
nand ( n72732 , n72730 , n72731 );
not ( n72733 , n72732 );
not ( n72734 , n72718 );
and ( n72735 , n72733 , n72734 );
nand ( n72736 , n72692 , n72694 );
or ( n72737 , n72684 , n72736 );
nand ( n72738 , n72682 , n72683 );
nand ( n72739 , n72737 , n72738 );
nor ( n72740 , n72732 , n72739 );
and ( n72741 , n72740 , n72697 );
nor ( n72742 , n72735 , n72741 );
nand ( n72743 , n71178 , n72721 );
not ( n72744 , n71146 );
not ( n72745 , n71181 );
and ( n72746 , n72744 , n72745 );
nor ( n72747 , n72746 , n71145 );
nand ( n72748 , n72740 , n72743 , n72747 );
nand ( n72749 , n72742 , n72748 );
not ( n72750 , n72749 );
and ( n72751 , n72750 , n72674 );
not ( n72752 , n72660 );
nand ( n72753 , n72670 , n72671 );
or ( n72754 , n72663 , n72753 );
nand ( n72755 , n72661 , n72662 );
nand ( n72756 , n72754 , n72755 );
not ( n72757 , n72756 );
or ( n72758 , n72752 , n72757 );
not ( n72759 , n72650 );
nand ( n72760 , n72657 , n72658 );
not ( n72761 , n72760 );
and ( n72762 , n72759 , n72761 );
nand ( n72763 , n72648 , n72649 );
not ( n72764 , n72763 );
nor ( n72765 , n72762 , n72764 );
nand ( n72766 , n72758 , n72765 );
nor ( n72767 , n72751 , n72766 );
nand ( n72768 , n72728 , n72767 );
xor ( n72769 , n72626 , n69729 );
and ( n72770 , n72523 , n69706 );
or ( n72771 , n72769 , n72770 );
nand ( n72772 , n72769 , n72770 );
nand ( n72773 , n72771 , n72772 );
not ( n72774 , n72773 );
and ( n72775 , n72768 , n72774 );
not ( n72776 , n72768 );
and ( n72777 , n72776 , n72773 );
nor ( n72778 , n72775 , n72777 );
and ( n72779 , n72778 , n72014 );
not ( n72780 , n69720 );
not ( n72781 , n69702 );
nor ( n72782 , n70893 , n70894 );
nand ( n72783 , n72782 , n3514 );
not ( n72784 , n69818 );
nor ( n72785 , n72783 , n72784 );
nand ( n72786 , n72785 , n69802 );
not ( n72787 , n69851 );
nor ( n72788 , n72786 , n72787 );
and ( n72789 , n72788 , n69887 );
nand ( n72790 , n72789 , n69772 );
not ( n72791 , n69766 );
nor ( n72792 , n72790 , n72791 );
nand ( n72793 , n72792 , n69928 );
not ( n72794 , n3707 );
nor ( n72795 , n72793 , n72794 );
nand ( n72796 , n72795 , n69676 );
nor ( n72797 , n72781 , n72796 );
not ( n72798 , n72797 );
or ( n72799 , n72780 , n72798 );
or ( n72800 , n72797 , n69720 );
nand ( n72801 , n72799 , n72800 );
not ( n72802 , n72801 );
or ( n72803 , n72802 , n72003 );
not ( n72804 , n72626 );
not ( n72805 , n71092 );
not ( n72806 , n71122 );
nand ( n72807 , n72805 , n72806 );
nor ( n72808 , n72807 , n71194 );
nor ( n72809 , n72499 , n72510 );
nor ( n72810 , n72485 , n72475 );
and ( n72811 , n72809 , n72810 );
and ( n72812 , n72808 , n72811 );
nor ( n72813 , n72557 , n72544 );
not ( n72814 , n72523 );
not ( n72815 , n72814 );
nor ( n72816 , n72815 , n72534 );
and ( n72817 , n72813 , n72816 );
nand ( n72818 , n72812 , n72817 );
nor ( n72819 , n70832 , n72818 );
not ( n72820 , n72819 );
or ( n72821 , n72804 , n72820 );
or ( n72822 , n72819 , n72626 );
nand ( n72823 , n72821 , n72822 );
nand ( n72824 , n72823 , n72017 );
nand ( n72825 , n71999 , n72626 );
nand ( n72826 , n69721 , n70859 );
and ( n72827 , n72824 , n72825 , n72826 );
nand ( n72828 , n72803 , n72827 );
nor ( n72829 , n72779 , n72828 );
and ( n72830 , n72647 , n72829 );
nand ( n72831 , n72471 , n72830 );
buf ( n72832 , n72831 );
buf ( n72833 , 1'b0 );
not ( n72834 , n68838 );
buf ( n6696 , n72834 );
buf ( n72836 , n68634 );
and ( n72837 , n69359 , n71780 );
not ( n72838 , n69359 );
and ( n72839 , n72446 , n72453 );
not ( n72840 , n72446 );
not ( n72841 , n72453 );
and ( n72842 , n72840 , n72841 );
nor ( n72843 , n72839 , n72842 );
and ( n72844 , n72838 , n72843 );
nor ( n72845 , n72837 , n72844 );
or ( n72846 , n72845 , n71986 );
not ( n72847 , n72547 );
and ( n72848 , n72569 , n72847 );
not ( n72849 , n72848 );
nor ( n72850 , n72522 , n72849 );
not ( n72851 , n72850 );
not ( n72852 , n70553 );
or ( n72853 , n72851 , n72852 );
not ( n72854 , n72848 );
not ( n72855 , n72604 );
or ( n72856 , n72854 , n72855 );
not ( n72857 , n72847 );
not ( n72858 , n72611 );
or ( n72859 , n72857 , n72858 );
nand ( n72860 , n72859 , n72615 );
not ( n72861 , n72860 );
nand ( n72862 , n72856 , n72861 );
not ( n72863 , n72862 );
nand ( n72864 , n72853 , n72863 );
or ( n72865 , n72536 , n72618 );
xnor ( n72866 , n72864 , n72865 );
nand ( n72867 , n72866 , n72011 );
not ( n72868 , n72650 );
nand ( n72869 , n72868 , n72763 );
not ( n72870 , n72869 );
not ( n72871 , n72659 );
nand ( n72872 , n72673 , n72871 );
nor ( n72873 , n72724 , n72872 );
not ( n72874 , n72873 );
not ( n72875 , n70804 );
or ( n72876 , n72874 , n72875 );
not ( n72877 , n72749 );
not ( n72878 , n72872 );
and ( n72879 , n72877 , n72878 );
not ( n72880 , n72871 );
not ( n72881 , n72756 );
or ( n72882 , n72880 , n72881 );
nand ( n72883 , n72882 , n72760 );
nor ( n72884 , n72879 , n72883 );
nand ( n72885 , n72876 , n72884 );
not ( n72886 , n72885 );
or ( n72887 , n72870 , n72886 );
or ( n72888 , n72885 , n72869 );
nand ( n72889 , n72887 , n72888 );
and ( n72890 , n72889 , n72014 );
and ( n72891 , n72796 , n69702 );
not ( n72892 , n72796 );
and ( n72893 , n72892 , n69701 );
nor ( n72894 , n72891 , n72893 );
or ( n72895 , n72003 , n72894 );
not ( n72896 , n72815 );
not ( n72897 , n72557 );
nor ( n72898 , n72807 , n70225 );
nor ( n72899 , n72544 , n72534 );
and ( n72900 , n72809 , n72899 , n71193 );
nand ( n72901 , n72897 , n72898 , n72900 , n72810 );
nor ( n72902 , n70832 , n72901 );
not ( n72903 , n72902 );
or ( n72904 , n72896 , n72903 );
or ( n72905 , n72902 , n72815 );
nand ( n72906 , n72904 , n72905 );
and ( n72907 , n72906 , n72017 );
nor ( n72908 , n69701 , n72071 );
nor ( n72909 , n72907 , n72908 );
nand ( n72910 , n71999 , n72815 );
nand ( n72911 , n72895 , n72909 , n72910 );
nor ( n72912 , n72890 , n72911 );
and ( n72913 , n72867 , n72912 );
nand ( n72914 , n72846 , n72913 );
buf ( n6776 , n72914 );
buf ( n6777 , 1'b0 );
not ( n72917 , n68838 );
buf ( n72918 , n72917 );
buf ( n72919 , n68634 );
and ( n72920 , n71272 , n71799 );
not ( n72921 , n71272 );
not ( n72922 , n72441 );
nand ( n72923 , n72922 , n72434 );
not ( n72924 , n72923 );
not ( n72925 , n72444 );
nand ( n72926 , n72924 , n69969 , n72925 );
not ( n72927 , n71763 );
and ( n72928 , n72926 , n72927 );
not ( n72929 , n72926 );
and ( n72930 , n72929 , n71763 );
nor ( n72931 , n72928 , n72930 );
and ( n72932 , n72921 , n72931 );
nor ( n72933 , n72920 , n72932 );
or ( n72934 , n72933 , n71986 );
not ( n72935 , n72569 );
nor ( n72936 , n72935 , n72522 );
not ( n72937 , n72936 );
not ( n72938 , n70553 );
or ( n72939 , n72937 , n72938 );
not ( n72940 , n72569 );
not ( n72941 , n72604 );
or ( n72942 , n72940 , n72941 );
not ( n72943 , n72611 );
nand ( n72944 , n72942 , n72943 );
not ( n72945 , n72944 );
nand ( n72946 , n72939 , n72945 );
nand ( n72947 , n72847 , n72615 );
not ( n72948 , n72947 );
and ( n72949 , n72946 , n72948 );
not ( n72950 , n72946 );
and ( n72951 , n72950 , n72947 );
nor ( n72952 , n72949 , n72951 );
nand ( n72953 , n72952 , n72011 );
not ( n72954 , n72673 );
nor ( n72955 , n72724 , n72954 );
not ( n72956 , n72955 );
not ( n72957 , n70804 );
or ( n72958 , n72956 , n72957 );
and ( n72959 , n72750 , n72673 );
nor ( n72960 , n72959 , n72756 );
nand ( n72961 , n72958 , n72960 );
nand ( n72962 , n72871 , n72760 );
not ( n72963 , n72962 );
and ( n72964 , n72961 , n72963 );
not ( n72965 , n72961 );
and ( n72966 , n72965 , n72962 );
nor ( n72967 , n72964 , n72966 );
and ( n72968 , n72967 , n72014 );
and ( n72969 , n72795 , n69675 );
not ( n72970 , n72795 );
and ( n72971 , n72970 , n69676 );
nor ( n72972 , n72969 , n72971 );
or ( n72973 , n72003 , n72972 );
not ( n72974 , n72534 );
not ( n72975 , n72807 );
not ( n72976 , n71194 );
nand ( n72977 , n72975 , n72976 , n72811 , n72813 );
nor ( n72978 , n70832 , n72977 );
not ( n72979 , n72978 );
or ( n72980 , n72974 , n72979 );
or ( n72981 , n72978 , n72534 );
nand ( n72982 , n72980 , n72981 );
and ( n72983 , n72982 , n72017 );
nor ( n72984 , n69675 , n72071 );
nor ( n72985 , n72983 , n72984 );
nand ( n72986 , n71999 , n72534 );
nand ( n72987 , n72973 , n72985 , n72986 );
nor ( n72988 , n72968 , n72987 );
and ( n72989 , n72953 , n72988 );
nand ( n72990 , n72934 , n72989 );
buf ( n6852 , n72990 );
buf ( n72992 , 1'b0 );
not ( n72993 , n68838 );
buf ( n72994 , n72993 );
buf ( n6856 , n68634 );
and ( n72996 , n69359 , n71814 );
not ( n72997 , n69359 );
not ( n72998 , n69969 );
nor ( n72999 , n72923 , n72998 );
nand ( n73000 , n72999 , n71797 );
not ( n73001 , n71778 );
and ( n73002 , n73000 , n73001 );
not ( n73003 , n73000 );
and ( n73004 , n73003 , n71778 );
nor ( n73005 , n73002 , n73004 );
and ( n73006 , n72997 , n73005 );
nor ( n73007 , n72996 , n73006 );
or ( n73008 , n73007 , n71986 );
nor ( n73009 , n72522 , n72568 );
not ( n73010 , n73009 );
not ( n73011 , n70553 );
or ( n73012 , n73010 , n73011 );
not ( n73013 , n72568 );
not ( n73014 , n73013 );
not ( n73015 , n72604 );
or ( n73016 , n73014 , n73015 );
nand ( n73017 , n73016 , n72608 );
not ( n73018 , n73017 );
nand ( n73019 , n73012 , n73018 );
not ( n73020 , n72559 );
nand ( n73021 , n73020 , n72610 );
xnor ( n73022 , n73019 , n73021 );
nand ( n73023 , n73022 , n72011 );
not ( n73024 , n72663 );
nand ( n73025 , n73024 , n72755 );
not ( n73026 , n73025 );
nor ( n73027 , n72724 , n72672 );
not ( n73028 , n73027 );
not ( n73029 , n70804 );
or ( n73030 , n73028 , n73029 );
not ( n73031 , n72749 );
not ( n73032 , n72672 );
and ( n73033 , n73031 , n73032 );
not ( n73034 , n72753 );
nor ( n73035 , n73033 , n73034 );
nand ( n73036 , n73030 , n73035 );
not ( n73037 , n73036 );
or ( n73038 , n73026 , n73037 );
or ( n73039 , n73036 , n73025 );
nand ( n73040 , n73038 , n73039 );
and ( n73041 , n73040 , n72014 );
and ( n73042 , n72793 , n3707 );
not ( n73043 , n72793 );
and ( n73044 , n73043 , n72794 );
nor ( n73045 , n73042 , n73044 );
or ( n73046 , n72003 , n73045 );
not ( n73047 , n72544 );
not ( n73048 , n72499 );
and ( n73049 , n72810 , n73048 );
nor ( n73050 , n71074 , n72557 , n72510 );
nand ( n73051 , n72898 , n73049 , n73050 );
nor ( n73052 , n70832 , n73051 );
not ( n73053 , n73052 );
or ( n73054 , n73047 , n73053 );
or ( n73055 , n73052 , n72544 );
nand ( n73056 , n73054 , n73055 );
and ( n73057 , n73056 , n72017 );
nor ( n73058 , n72794 , n72071 );
nor ( n73059 , n73057 , n73058 );
nand ( n73060 , n71999 , n72544 );
nand ( n73061 , n73046 , n73059 , n73060 );
nor ( n73062 , n73041 , n73061 );
and ( n73063 , n73023 , n73062 );
nand ( n73064 , n73008 , n73063 );
buf ( n6926 , n73064 );
buf ( n6927 , 1'b0 );
not ( n73067 , n68838 );
buf ( n73068 , n73067 );
buf ( n73069 , n68634 );
and ( n73070 , n71272 , n71834 );
not ( n73071 , n71272 );
not ( n73072 , n72999 );
not ( n73073 , n71797 );
and ( n73074 , n73072 , n73073 );
not ( n73075 , n73072 );
and ( n73076 , n73075 , n71797 );
nor ( n73077 , n73074 , n73076 );
and ( n73078 , n73071 , n73077 );
nor ( n73079 , n73070 , n73078 );
or ( n73080 , n73079 , n71986 );
not ( n73081 , n72522 );
not ( n73082 , n73081 );
not ( n73083 , n70553 );
or ( n73084 , n73082 , n73083 );
not ( n73085 , n72604 );
nand ( n73086 , n73084 , n73085 );
nand ( n73087 , n73013 , n72608 );
not ( n73088 , n73087 );
and ( n73089 , n73086 , n73088 );
not ( n73090 , n73086 );
and ( n73091 , n73090 , n73087 );
nor ( n73092 , n73089 , n73091 );
nand ( n73093 , n73092 , n72011 );
not ( n73094 , n72724 );
not ( n73095 , n73094 );
not ( n73096 , n70809 );
or ( n73097 , n73095 , n73096 );
nand ( n73098 , n73097 , n72749 );
nor ( n73099 , n73034 , n72672 );
and ( n73100 , n73098 , n73099 );
not ( n73101 , n73098 );
not ( n73102 , n73099 );
and ( n73103 , n73101 , n73102 );
nor ( n73104 , n73100 , n73103 );
and ( n73105 , n73104 , n72014 );
and ( n73106 , n72792 , n69927 );
not ( n73107 , n72792 );
and ( n73108 , n73107 , n69928 );
nor ( n73109 , n73106 , n73108 );
or ( n73110 , n72003 , n73109 );
not ( n73111 , n72557 );
not ( n73112 , n72812 );
nor ( n73113 , n73112 , n70832 );
not ( n73114 , n73113 );
or ( n73115 , n73111 , n73114 );
or ( n73116 , n73113 , n72557 );
nand ( n73117 , n73115 , n73116 );
and ( n73118 , n73117 , n72017 );
nor ( n73119 , n69927 , n72071 );
nor ( n73120 , n73118 , n73119 );
nand ( n73121 , n71999 , n72557 );
nand ( n73122 , n73110 , n73120 , n73121 );
nor ( n73123 , n73105 , n73122 );
and ( n73124 , n73093 , n73123 );
nand ( n73125 , n73080 , n73124 );
buf ( n6987 , n73125 );
buf ( n73127 , 1'b0 );
not ( n73128 , n68838 );
buf ( n73129 , n73128 );
buf ( n6991 , n68634 );
and ( n73131 , n69359 , n71852 );
not ( n73132 , n69359 );
nor ( n73133 , n72441 , n71522 );
nand ( n73134 , n73133 , n71852 );
not ( n73135 , n73134 );
nand ( n73136 , n73135 , n71832 );
not ( n73137 , n71814 );
and ( n73138 , n73136 , n73137 );
not ( n73139 , n73136 );
and ( n73140 , n73139 , n71814 );
nor ( n73141 , n73138 , n73140 );
and ( n73142 , n73132 , n73141 );
nor ( n73143 , n73131 , n73142 );
or ( n73144 , n73143 , n71986 );
not ( n73145 , n72473 );
not ( n73146 , n72508 );
and ( n73147 , n72497 , n73146 );
not ( n73148 , n73147 );
nor ( n73149 , n73145 , n73148 );
not ( n73150 , n73149 );
not ( n73151 , n70553 );
or ( n73152 , n73150 , n73151 );
and ( n73153 , n73147 , n72585 );
not ( n73154 , n73146 );
not ( n73155 , n72595 );
or ( n73156 , n73154 , n73155 );
nand ( n73157 , n73156 , n72598 );
nor ( n73158 , n73153 , n73157 );
nand ( n73159 , n73152 , n73158 );
or ( n73160 , n72600 , n72519 );
xnor ( n73161 , n73159 , n73160 );
nand ( n73162 , n73161 , n72011 );
not ( n73163 , n72717 );
nand ( n73164 , n73163 , n72731 );
not ( n73165 , n73164 );
nor ( n73166 , n72697 , n72707 );
not ( n73167 , n73166 );
not ( n73168 , n72723 );
nor ( n73169 , n73167 , n73168 );
not ( n73170 , n73169 );
not ( n73171 , n70809 );
or ( n73172 , n73170 , n73171 );
not ( n73173 , n73166 );
nand ( n73174 , n72743 , n72747 );
not ( n73175 , n73174 );
or ( n73176 , n73173 , n73175 );
not ( n73177 , n72707 );
not ( n73178 , n73177 );
not ( n73179 , n72739 );
or ( n73180 , n73178 , n73179 );
nand ( n73181 , n73180 , n72729 );
not ( n73182 , n73181 );
nand ( n73183 , n73176 , n73182 );
not ( n73184 , n73183 );
nand ( n73185 , n73172 , n73184 );
not ( n73186 , n73185 );
or ( n73187 , n73165 , n73186 );
or ( n73188 , n73185 , n73164 );
nand ( n73189 , n73187 , n73188 );
and ( n73190 , n73189 , n72014 );
and ( n73191 , n72790 , n69766 );
not ( n73192 , n72790 );
and ( n73193 , n73192 , n72791 );
nor ( n73194 , n73191 , n73193 );
or ( n73195 , n72003 , n73194 );
not ( n73196 , n72510 );
nand ( n73197 , n72808 , n73049 );
nor ( n73198 , n70832 , n73197 );
not ( n73199 , n73198 );
or ( n73200 , n73196 , n73199 );
or ( n73201 , n73198 , n72510 );
nand ( n73202 , n73200 , n73201 );
and ( n73203 , n73202 , n72017 );
nor ( n73204 , n72791 , n72071 );
nor ( n73205 , n73203 , n73204 );
nand ( n73206 , n71999 , n72510 );
nand ( n73207 , n73195 , n73205 , n73206 );
nor ( n73208 , n73190 , n73207 );
and ( n73209 , n73162 , n73208 );
nand ( n73210 , n73144 , n73209 );
buf ( n73211 , n73210 );
buf ( n73212 , 1'b0 );
not ( n73213 , n68838 );
buf ( n73214 , n73213 );
buf ( n73215 , n68634 );
and ( n73216 , n71272 , n71869 );
not ( n73217 , n71272 );
not ( n73218 , n71832 );
and ( n73219 , n73134 , n73218 );
not ( n73220 , n73134 );
and ( n73221 , n73220 , n71832 );
nor ( n73222 , n73219 , n73221 );
and ( n73223 , n73217 , n73222 );
nor ( n73224 , n73216 , n73223 );
or ( n73225 , n73224 , n71986 );
not ( n73226 , n72497 );
nor ( n73227 , n73145 , n73226 );
not ( n73228 , n73227 );
not ( n73229 , n70553 );
or ( n73230 , n73228 , n73229 );
and ( n73231 , n72497 , n72585 );
nor ( n73232 , n73231 , n72595 );
nand ( n73233 , n73230 , n73232 );
nand ( n73234 , n73146 , n72598 );
not ( n73235 , n73234 );
and ( n73236 , n73233 , n73235 );
not ( n73237 , n73233 );
and ( n73238 , n73237 , n73234 );
nor ( n73239 , n73236 , n73238 );
nand ( n73240 , n73239 , n72011 );
nor ( n73241 , n73168 , n72697 );
not ( n73242 , n73241 );
not ( n73243 , n70809 );
or ( n73244 , n73242 , n73243 );
and ( n73245 , n72698 , n73174 );
nor ( n73246 , n73245 , n72739 );
nand ( n73247 , n73244 , n73246 );
nand ( n73248 , n73177 , n72729 );
not ( n73249 , n73248 );
and ( n73250 , n73247 , n73249 );
not ( n73251 , n73247 );
and ( n73252 , n73251 , n73248 );
nor ( n73253 , n73250 , n73252 );
and ( n73254 , n73253 , n72014 );
and ( n73255 , n72789 , n69771 );
not ( n73256 , n72789 );
and ( n73257 , n73256 , n69772 );
nor ( n73258 , n73255 , n73257 );
or ( n73259 , n72003 , n73258 );
not ( n73260 , n72499 );
nand ( n73261 , n72808 , n72810 );
nor ( n73262 , n70832 , n73261 );
not ( n73263 , n73262 );
or ( n73264 , n73260 , n73263 );
or ( n73265 , n73262 , n72499 );
nand ( n73266 , n73264 , n73265 );
and ( n73267 , n73266 , n72017 );
nor ( n73268 , n69771 , n72071 );
nor ( n73269 , n73267 , n73268 );
nand ( n73270 , n71999 , n72499 );
nand ( n73271 , n73259 , n73269 , n73270 );
nor ( n73272 , n73254 , n73271 );
and ( n73273 , n73240 , n73272 );
nand ( n73274 , n73225 , n73273 );
buf ( n73275 , n73274 );
buf ( n73276 , 1'b0 );
not ( n73277 , n68838 );
buf ( n7139 , n73277 );
buf ( n73279 , n68634 );
and ( n73280 , n69359 , n71037 );
not ( n73281 , n69359 );
not ( n73282 , n71852 );
not ( n73283 , n73133 );
not ( n73284 , n73283 );
or ( n73285 , n73282 , n73284 );
or ( n73286 , n71852 , n73283 );
nand ( n73287 , n73285 , n73286 );
and ( n73288 , n73281 , n73287 );
nor ( n73289 , n73280 , n73288 );
or ( n73290 , n73289 , n71986 );
nor ( n73291 , n73145 , n72496 );
not ( n73292 , n73291 );
not ( n73293 , n70553 );
or ( n73294 , n73292 , n73293 );
not ( n73295 , n72496 );
not ( n73296 , n73295 );
not ( n73297 , n72585 );
or ( n73298 , n73296 , n73297 );
not ( n73299 , n72589 );
nand ( n73300 , n73298 , n73299 );
not ( n73301 , n73300 );
nand ( n73302 , n73294 , n73301 );
nand ( n73303 , n72591 , n72594 );
xnor ( n73304 , n73302 , n73303 );
nand ( n73305 , n73304 , n72011 );
not ( n73306 , n72684 );
nand ( n73307 , n73306 , n72738 );
not ( n73308 , n73307 );
not ( n73309 , n72696 );
nor ( n73310 , n73309 , n73168 );
not ( n73311 , n73310 );
not ( n73312 , n70809 );
or ( n73313 , n73311 , n73312 );
not ( n73314 , n72696 );
not ( n73315 , n73174 );
or ( n73316 , n73314 , n73315 );
nand ( n73317 , n73316 , n72736 );
not ( n73318 , n73317 );
nand ( n73319 , n73313 , n73318 );
not ( n73320 , n73319 );
or ( n73321 , n73308 , n73320 );
or ( n73322 , n73319 , n73307 );
nand ( n73323 , n73321 , n73322 );
and ( n73324 , n72014 , n73323 );
and ( n73325 , n72788 , n69886 );
not ( n73326 , n72788 );
and ( n73327 , n73326 , n69887 );
nor ( n73328 , n73325 , n73327 );
or ( n73329 , n72003 , n73328 );
not ( n73330 , n72475 );
not ( n73331 , n72485 );
nand ( n73332 , n73331 , n72808 );
nor ( n73333 , n70832 , n73332 );
not ( n73334 , n73333 );
or ( n73335 , n73330 , n73334 );
or ( n73336 , n73333 , n72475 );
nand ( n73337 , n73335 , n73336 );
and ( n73338 , n73337 , n72017 );
nor ( n73339 , n69886 , n72071 );
nor ( n73340 , n73338 , n73339 );
nand ( n73341 , n71999 , n72475 );
nand ( n73342 , n73329 , n73340 , n73341 );
nor ( n73343 , n73324 , n73342 );
and ( n73344 , n73305 , n73343 );
nand ( n73345 , n73290 , n73344 );
buf ( n7207 , n73345 );
buf ( n7208 , 1'b0 );
not ( n73348 , n68838 );
buf ( n73349 , n73348 );
buf ( n73350 , n68634 );
and ( n73351 , n71272 , n71058 );
not ( n73352 , n71272 );
not ( n73353 , n71059 );
nand ( n73354 , n73353 , n71037 );
not ( n73355 , n71869 );
and ( n73356 , n73354 , n73355 );
not ( n73357 , n73354 );
and ( n73358 , n73357 , n71869 );
nor ( n73359 , n73356 , n73358 );
and ( n73360 , n73352 , n73359 );
nor ( n73361 , n73351 , n73360 );
or ( n73362 , n73361 , n71986 );
not ( n73363 , n72473 );
not ( n73364 , n70553 );
or ( n73365 , n73363 , n73364 );
not ( n73366 , n72585 );
nand ( n73367 , n73365 , n73366 );
nand ( n73368 , n73295 , n73299 );
xnor ( n73369 , n73367 , n73368 );
nand ( n73370 , n73369 , n72011 );
nand ( n73371 , n72696 , n72736 );
not ( n73372 , n73371 );
not ( n73373 , n72723 );
not ( n73374 , n70809 );
or ( n73375 , n73373 , n73374 );
not ( n73376 , n73174 );
nand ( n73377 , n73375 , n73376 );
not ( n73378 , n73377 );
or ( n73379 , n73372 , n73378 );
or ( n73380 , n73377 , n73371 );
nand ( n73381 , n73379 , n73380 );
and ( n73382 , n73381 , n72014 );
and ( n73383 , n72786 , n69851 );
not ( n73384 , n72786 );
and ( n73385 , n73384 , n72787 );
nor ( n73386 , n73383 , n73385 );
or ( n73387 , n72003 , n73386 );
not ( n73388 , n72485 );
not ( n73389 , n72808 );
nor ( n73390 , n70832 , n73389 );
not ( n73391 , n73390 );
or ( n73392 , n73388 , n73391 );
or ( n73393 , n73390 , n72485 );
nand ( n73394 , n73392 , n73393 );
and ( n73395 , n73394 , n72017 );
nor ( n73396 , n72787 , n72071 );
nor ( n73397 , n73395 , n73396 );
nand ( n73398 , n71999 , n72485 );
nand ( n73399 , n73387 , n73397 , n73398 );
nor ( n73400 , n73382 , n73399 );
and ( n73401 , n73370 , n73400 );
nand ( n73402 , n73362 , n73401 );
buf ( n73403 , n73402 );
buf ( n73404 , 1'b0 );
not ( n73405 , n68838 );
buf ( n73406 , n73405 );
buf ( n73407 , n68634 );
and ( n73408 , n71272 , n69967 );
not ( n73409 , n71272 );
not ( n73410 , n70073 );
not ( n73411 , n72331 );
or ( n73412 , n73410 , n73411 );
or ( n73413 , n72331 , n70073 );
nand ( n73414 , n73412 , n73413 );
and ( n73415 , n73409 , n73414 );
nor ( n73416 , n73408 , n73415 );
or ( n73417 , n73416 , n71986 );
and ( n73418 , n72386 , n70041 );
not ( n73419 , n70524 );
not ( n73420 , n73419 );
not ( n73421 , n70507 );
nand ( n73422 , n73421 , n70518 );
not ( n73423 , n73422 );
or ( n73424 , n73420 , n73423 );
or ( n73425 , n73422 , n73419 );
nand ( n73426 , n73424 , n73425 );
nand ( n73427 , n73426 , n72011 );
xor ( n73428 , n70722 , n70725 );
nand ( n73429 , n72014 , n73428 );
nand ( n73430 , n71999 , n70503 );
not ( n73431 , n70829 );
not ( n73432 , n70522 );
or ( n73433 , n73431 , n73432 );
or ( n73434 , n70522 , n70829 );
nand ( n73435 , n73433 , n73434 );
nand ( n73436 , n72017 , n73435 );
nand ( n73437 , n73427 , n73429 , n73430 , n73436 );
nor ( n73438 , n73418 , n73437 );
nand ( n73439 , n73417 , n73438 );
buf ( n73440 , n73439 );
buf ( n73441 , 1'b0 );
not ( n73442 , n68838 );
buf ( n73443 , n73442 );
buf ( n7305 , n68634 );
not ( n73445 , n71067 );
or ( n73446 , n73445 , n71986 );
nand ( n73447 , n71134 , n72011 );
and ( n73448 , n71188 , n72014 );
not ( n73449 , n69802 );
and ( n73450 , n72785 , n73449 );
not ( n73451 , n72785 );
and ( n73452 , n73451 , n69802 );
nor ( n73453 , n73450 , n73452 );
or ( n73454 , n72003 , n73453 );
and ( n73455 , n71200 , n72017 );
nor ( n73456 , n73449 , n72071 );
nor ( n73457 , n73455 , n73456 );
nand ( n73458 , n71999 , n71122 );
nand ( n73459 , n73454 , n73457 , n73458 );
nor ( n73460 , n73448 , n73459 );
and ( n73461 , n73447 , n73460 );
nand ( n73462 , n73446 , n73461 );
buf ( n73463 , n73462 );
buf ( n73464 , 1'b0 );
not ( n73465 , n68838 );
buf ( n7327 , n73465 );
buf ( n7328 , n68634 );
not ( n73468 , n71225 );
or ( n73469 , n73468 , n71986 );
nand ( n73470 , n71233 , n72011 );
and ( n73471 , n71248 , n72014 );
and ( n73472 , n72783 , n69818 );
not ( n73473 , n72783 );
and ( n73474 , n73473 , n72784 );
nor ( n73475 , n73472 , n73474 );
or ( n73476 , n72003 , n73475 );
and ( n73477 , n71256 , n72017 );
nor ( n73478 , n72784 , n72071 );
nor ( n73479 , n73477 , n73478 );
nand ( n73480 , n71999 , n71092 );
nand ( n73481 , n73476 , n73479 , n73480 );
nor ( n73482 , n73471 , n73481 );
and ( n73483 , n73470 , n73482 );
nand ( n73484 , n73469 , n73483 );
buf ( n73485 , n73484 );
buf ( n73486 , 1'b0 );
not ( n73487 , n68838 );
buf ( n7349 , n73487 );
buf ( n7350 , n68634 );
or ( n73490 , n71281 , n71986 );
nand ( n73491 , n71291 , n72011 );
and ( n73492 , n71304 , n72014 );
not ( n73493 , n3514 );
and ( n73494 , n72782 , n73493 );
not ( n73495 , n72782 );
and ( n73496 , n73495 , n3514 );
nor ( n73497 , n73494 , n73496 );
or ( n73498 , n72003 , n73497 );
and ( n73499 , n71312 , n72017 );
nor ( n73500 , n73493 , n72071 );
nor ( n73501 , n73499 , n73500 );
nand ( n73502 , n71999 , n71074 );
nand ( n73503 , n73498 , n73501 , n73502 );
nor ( n73504 , n73492 , n73503 );
and ( n73505 , n73491 , n73504 );
nand ( n73506 , n73490 , n73505 );
buf ( n73507 , n73506 );
buf ( n73508 , 1'b0 );
not ( n73509 , n68838 );
buf ( n73510 , n73509 );
buf ( n73511 , n68634 );
or ( n73512 , n70109 , n71986 );
not ( n73513 , n70557 );
not ( n73514 , n73513 );
not ( n73515 , n71991 );
and ( n73516 , n73514 , n73515 );
nand ( n73517 , n70812 , n72014 );
nand ( n73518 , n72057 , n70898 );
nand ( n73519 , n70837 , n72017 );
nand ( n73520 , n71999 , n70225 );
nor ( n73521 , n70894 , n72071 );
not ( n73522 , n73521 );
and ( n73523 , n73519 , n73520 , n73522 );
nand ( n73524 , n73517 , n73518 , n73523 );
nor ( n73525 , n73516 , n73524 );
nand ( n73526 , n73512 , n73525 );
buf ( n7388 , n73526 );
buf ( n7389 , 1'b0 );
not ( n73529 , n68838 );
buf ( n7391 , n73529 );
buf ( n7392 , n68634 );
not ( n73532 , n71364 );
or ( n73533 , n73532 , n71986 );
not ( n73534 , n72003 );
not ( n73535 , n69603 );
and ( n73536 , n70892 , n73535 );
not ( n73537 , n70892 );
and ( n73538 , n73537 , n69603 );
nor ( n73539 , n73536 , n73538 );
not ( n73540 , n73539 );
and ( n73541 , n73534 , n73540 );
and ( n73542 , n71390 , n72011 );
nor ( n73543 , n73541 , n73542 );
and ( n73544 , n72014 , n71416 );
nand ( n73545 , n71428 , n72017 );
nand ( n73546 , n71999 , n70238 );
nand ( n73547 , n69603 , n70859 );
nand ( n73548 , n73545 , n73546 , n73547 );
nor ( n73549 , n73544 , n73548 );
and ( n73550 , n73543 , n73549 );
nand ( n73551 , n73533 , n73550 );
buf ( n73552 , n73551 );
buf ( n73553 , 1'b0 );
not ( n73554 , n68838 );
buf ( n73555 , n73554 );
buf ( n73556 , n68634 );
not ( n73557 , n71457 );
or ( n73558 , n73557 , n71986 );
not ( n73559 , n72003 );
and ( n73560 , n70890 , n3454 );
not ( n73561 , n70890 );
and ( n73562 , n73561 , n70891 );
nor ( n73563 , n73560 , n73562 );
not ( n73564 , n73563 );
and ( n73565 , n73559 , n73564 );
and ( n73566 , n71475 , n72011 );
nor ( n73567 , n73565 , n73566 );
and ( n73568 , n72014 , n71491 );
nand ( n73569 , n71501 , n72017 );
nand ( n73570 , n71999 , n70327 );
nand ( n73571 , n3454 , n70859 );
nand ( n73572 , n73569 , n73570 , n73571 );
nor ( n73573 , n73568 , n73572 );
and ( n73574 , n73567 , n73573 );
nand ( n73575 , n73558 , n73574 );
buf ( n73576 , n73575 );
buf ( n73577 , 1'b0 );
not ( n73578 , n68838 );
buf ( n73579 , n73578 );
buf ( n73580 , n68634 );
not ( n73581 , n69358 );
not ( n73582 , n69981 );
not ( n73583 , n71447 );
or ( n73584 , n73582 , n73583 );
or ( n73585 , n71447 , n69981 );
nand ( n73586 , n73584 , n73585 );
not ( n73587 , n73586 );
or ( n73588 , n73581 , n73587 );
nand ( n73589 , n69990 , n69359 );
nand ( n73590 , n73588 , n73589 );
not ( n73591 , n73590 );
or ( n73592 , n73591 , n71986 );
not ( n73593 , n72003 );
not ( n73594 , n69567 );
and ( n73595 , n70889 , n73594 );
not ( n73596 , n70889 );
and ( n73597 , n73596 , n69567 );
nor ( n73598 , n73595 , n73597 );
not ( n73599 , n73598 );
and ( n73600 , n73593 , n73599 );
nand ( n73601 , n70354 , n70357 );
not ( n73602 , n73601 );
nor ( n73603 , n71372 , n70320 );
not ( n73604 , n73603 );
not ( n73605 , n70957 );
or ( n73606 , n73604 , n73605 );
or ( n73607 , n71377 , n70320 );
nand ( n73608 , n73607 , n70351 );
not ( n73609 , n73608 );
nand ( n73610 , n73606 , n73609 );
not ( n73611 , n73610 );
or ( n73612 , n73602 , n73611 );
or ( n73613 , n73610 , n73601 );
nand ( n73614 , n73612 , n73613 );
and ( n73615 , n73614 , n72011 );
nor ( n73616 , n73600 , n73615 );
not ( n73617 , n70670 );
nand ( n73618 , n73617 , n70786 );
not ( n73619 , n73618 );
nor ( n73620 , n71397 , n70679 );
not ( n73621 , n73620 );
not ( n73622 , n70984 );
or ( n73623 , n73621 , n73622 );
not ( n73624 , n71402 );
not ( n73625 , n70679 );
and ( n73626 , n73624 , n73625 );
not ( n73627 , n70784 );
nor ( n73628 , n73626 , n73627 );
nand ( n73629 , n73623 , n73628 );
not ( n73630 , n73629 );
or ( n73631 , n73619 , n73630 );
or ( n73632 , n73629 , n73618 );
nand ( n73633 , n73631 , n73632 );
and ( n73634 , n72014 , n73633 );
not ( n73635 , n70296 );
not ( n73636 , n73635 );
and ( n73637 , n70827 , n71561 );
nand ( n73638 , n71003 , n73637 );
not ( n73639 , n73638 );
or ( n73640 , n73636 , n73639 );
or ( n73641 , n73638 , n73635 );
nand ( n73642 , n73640 , n73641 );
nand ( n73643 , n73642 , n72017 );
nand ( n73644 , n71999 , n70296 );
nand ( n73645 , n69567 , n70859 );
nand ( n73646 , n73643 , n73644 , n73645 );
nor ( n73647 , n73634 , n73646 );
and ( n73648 , n73616 , n73647 );
nand ( n73649 , n73592 , n73648 );
buf ( n73650 , n73649 );
buf ( n73651 , 1'b0 );
not ( n73652 , n68838 );
buf ( n73653 , n73652 );
buf ( n73654 , n68634 );
not ( n73655 , n71532 );
or ( n73656 , n73655 , n71986 );
not ( n73657 , n72003 );
not ( n73658 , n3442 );
and ( n73659 , n70888 , n73658 );
not ( n73660 , n70888 );
and ( n73661 , n73660 , n3442 );
nor ( n73662 , n73659 , n73661 );
not ( n73663 , n73662 );
and ( n73664 , n73657 , n73663 );
and ( n73665 , n71545 , n72011 );
nor ( n73666 , n73664 , n73665 );
and ( n73667 , n71558 , n72014 );
nand ( n73668 , n71567 , n72017 );
nand ( n73669 , n71999 , n70308 );
nand ( n73670 , n3442 , n70859 );
nand ( n73671 , n73668 , n73669 , n73670 );
nor ( n73672 , n73667 , n73671 );
and ( n73673 , n73666 , n73672 );
nand ( n73674 , n73656 , n73673 );
buf ( n7536 , n73674 );
buf ( n7537 , 1'b0 );
not ( n73677 , n68838 );
buf ( n7539 , n73677 );
buf ( n7540 , n68634 );
not ( n73680 , n71598 );
or ( n73681 , n73680 , n71986 );
not ( n73682 , n72003 );
and ( n73683 , n70886 , n69512 );
not ( n73684 , n70886 );
and ( n73685 , n73684 , n70887 );
nor ( n73686 , n73683 , n73685 );
not ( n73687 , n73686 );
and ( n73688 , n73682 , n73687 );
and ( n73689 , n71618 , n72011 );
nor ( n73690 , n73688 , n73689 );
and ( n73691 , n72014 , n71638 );
nand ( n73692 , n71647 , n72017 );
nand ( n73693 , n71999 , n70273 );
nand ( n73694 , n69512 , n70859 );
nand ( n73695 , n73692 , n73693 , n73694 );
nor ( n73696 , n73691 , n73695 );
and ( n73697 , n73690 , n73696 );
nand ( n73698 , n73681 , n73697 );
buf ( n73699 , n73698 );
buf ( n73700 , 1'b0 );
not ( n73701 , n68838 );
buf ( n73702 , n73701 );
buf ( n73703 , n68634 );
not ( n73704 , n71672 );
or ( n73705 , n73704 , n71986 );
not ( n73706 , n72003 );
not ( n73707 , n69520 );
and ( n73708 , n70885 , n73707 );
not ( n73709 , n70885 );
and ( n73710 , n73709 , n69520 );
nor ( n73711 , n73708 , n73710 );
not ( n73712 , n73711 );
and ( n73713 , n73706 , n73712 );
and ( n73714 , n71685 , n72011 );
nor ( n73715 , n73713 , n73714 );
and ( n73716 , n72014 , n71699 );
nand ( n73717 , n71707 , n72017 );
nand ( n73718 , n71999 , n70253 );
nand ( n73719 , n69520 , n70859 );
nand ( n73720 , n73717 , n73718 , n73719 );
nor ( n73721 , n73716 , n73720 );
and ( n73722 , n73715 , n73721 );
nand ( n73723 , n73705 , n73722 );
buf ( n73724 , n73723 );
buf ( n73725 , 1'b0 );
not ( n73726 , n68838 );
buf ( n73727 , n73726 );
buf ( n73728 , n68634 );
not ( n73729 , n70053 );
not ( n73730 , n69970 );
or ( n73731 , n73729 , n73730 );
not ( n73732 , n70053 );
nand ( n73733 , n73732 , n69971 );
nand ( n73734 , n73731 , n73733 );
nand ( n73735 , n73734 , n69358 );
or ( n73736 , n73735 , n71986 );
nand ( n73737 , n72386 , n69950 );
not ( n73738 , n70522 );
nor ( n73739 , n73738 , n72002 );
not ( n73740 , n70523 );
not ( n73741 , n69967 );
or ( n73742 , n73740 , n73741 );
not ( n73743 , n70523 );
nand ( n73744 , n73743 , n70519 );
nand ( n73745 , n73742 , n73744 );
not ( n73746 , n73745 );
not ( n73747 , n72011 );
or ( n73748 , n73746 , n73747 );
not ( n73749 , n70724 );
not ( n73750 , n69967 );
or ( n73751 , n73749 , n73750 );
or ( n73752 , n69967 , n70724 );
nand ( n73753 , n73751 , n73752 );
nand ( n73754 , n72014 , n73753 );
nand ( n73755 , n73748 , n73754 );
nor ( n73756 , n73739 , n73755 );
nand ( n73757 , n73736 , n73737 , n73756 );
buf ( n7619 , n73757 );
buf ( n73759 , 1'b0 );
not ( n73760 , n68838 );
buf ( n7622 , n73760 );
buf ( n7623 , n68634 );
or ( n73763 , n71981 , n70210 );
and ( n73764 , n70573 , n70992 );
not ( n73765 , n70840 );
not ( n73766 , n73765 );
nand ( n73767 , n71008 , n73766 );
not ( n73768 , n70875 );
not ( n73769 , n72008 );
and ( n73770 , n73768 , n73769 );
and ( n73771 , n70849 , n70263 );
nor ( n73772 , n73770 , n73771 );
nand ( n73773 , n70870 , n69533 );
nand ( n73774 , n73767 , n73772 , n73773 );
nor ( n73775 , n73764 , n73774 );
nand ( n73776 , n70965 , n70568 );
and ( n73777 , n73775 , n73776 );
nand ( n73778 , n73763 , n73777 );
buf ( n7640 , n73778 );
buf ( n7641 , 1'b0 );
not ( n73781 , n68838 );
buf ( n73782 , n73781 );
buf ( n73783 , n68634 );
or ( n73784 , n72041 , n70210 );
nand ( n73785 , n72048 , n70573 );
nand ( n73786 , n72055 , n70568 );
not ( n73787 , n72069 );
not ( n73788 , n70840 );
or ( n73789 , n73787 , n73788 );
and ( n73790 , n70870 , n3405 );
and ( n73791 , n70876 , n72062 );
nor ( n73792 , n73790 , n73791 );
nand ( n73793 , n73789 , n73792 );
not ( n73794 , n70378 );
nor ( n73795 , n70848 , n73794 );
nor ( n73796 , n73793 , n73795 );
and ( n73797 , n73785 , n73786 , n73796 );
nand ( n73798 , n73784 , n73797 );
buf ( n73799 , n73798 );
buf ( n73800 , 1'b0 );
not ( n73801 , n68838 );
buf ( n73802 , n73801 );
buf ( n73803 , n68634 );
or ( n73804 , n72094 , n70210 );
nand ( n73805 , n72112 , n70568 );
nand ( n73806 , n72130 , n70573 );
and ( n73807 , n70849 , n70388 );
and ( n73808 , n70876 , n72135 );
nor ( n73809 , n73807 , n73808 );
nand ( n73810 , n70840 , n72150 );
nand ( n73811 , n70870 , n3320 );
and ( n73812 , n73809 , n73810 , n73811 );
and ( n73813 , n73805 , n73806 , n73812 );
nand ( n73814 , n73804 , n73813 );
buf ( n7676 , n73814 );
buf ( n7677 , 1'b0 );
not ( n73817 , n68838 );
buf ( n73818 , n73817 );
buf ( n73819 , n68634 );
or ( n73820 , n72169 , n70210 );
nand ( n73821 , n72178 , n70573 );
nand ( n73822 , n72191 , n70568 );
and ( n73823 , n70849 , n70477 );
and ( n73824 , n70876 , n72197 );
nor ( n73825 , n73823 , n73824 );
nand ( n73826 , n70840 , n72207 );
nand ( n73827 , n70870 , n3276 );
and ( n73828 , n73825 , n73826 , n73827 );
and ( n73829 , n73821 , n73822 , n73828 );
nand ( n73830 , n73820 , n73829 );
buf ( n7692 , n73830 );
buf ( n7693 , 1'b0 );
not ( n73833 , n68838 );
buf ( n73834 , n73833 );
buf ( n7696 , n68634 );
or ( n73836 , n72230 , n70210 );
nand ( n73837 , n72242 , n70568 );
nand ( n73838 , n72254 , n70573 );
and ( n73839 , n70849 , n70432 );
and ( n73840 , n70876 , n72259 );
nor ( n73841 , n73839 , n73840 );
nand ( n73842 , n70840 , n72269 );
not ( n73843 , n70870 );
not ( n73844 , n73843 );
nand ( n73845 , n73844 , n3350 );
and ( n73846 , n73841 , n73842 , n73845 );
and ( n73847 , n73837 , n73838 , n73846 );
nand ( n73848 , n73836 , n73847 );
buf ( n73849 , n73848 );
buf ( n73850 , 1'b0 );
not ( n73851 , n68838 );
buf ( n73852 , n73851 );
buf ( n7714 , n68634 );
or ( n73854 , n72290 , n70210 );
and ( n73855 , n72300 , n70573 );
not ( n73856 , n3346 );
nor ( n73857 , n73843 , n73856 );
nor ( n73858 , n73855 , n73857 );
nand ( n73859 , n72293 , n70568 );
not ( n73860 , n72302 );
not ( n73861 , n70849 );
or ( n73862 , n73860 , n73861 );
not ( n73863 , n70876 );
or ( n73864 , n73863 , n72319 );
nand ( n73865 , n73862 , n73864 );
not ( n73866 , n70840 );
not ( n73867 , n72307 );
nor ( n73868 , n73866 , n73867 );
nor ( n73869 , n73865 , n73868 );
and ( n73870 , n73858 , n73859 , n73869 );
nand ( n73871 , n73854 , n73870 );
buf ( n73872 , n73871 );
buf ( n73873 , 1'b0 );
not ( n73874 , n68838 );
buf ( n73875 , n73874 );
buf ( n73876 , n68634 );
or ( n73877 , n72340 , n70210 );
nand ( n73878 , n72345 , n70568 );
nand ( n73879 , n72356 , n70573 );
nand ( n73880 , n73766 , n72365 );
and ( n73881 , n70849 , n70420 );
and ( n73882 , n70876 , n72317 );
nor ( n73883 , n73881 , n73882 );
nand ( n73884 , n70870 , n69437 );
and ( n73885 , n73880 , n73883 , n73884 );
and ( n73886 , n73878 , n73879 , n73885 );
nand ( n73887 , n73877 , n73886 );
buf ( n7749 , n73887 );
buf ( n7750 , 1'b0 );
not ( n73890 , n68838 );
buf ( n73891 , n73890 );
buf ( n73892 , n68634 );
and ( n73893 , n70870 , n69940 );
not ( n73894 , n70870 );
not ( n73895 , n69947 );
nand ( n73896 , n72454 , n72463 );
not ( n73897 , n73896 );
not ( n73898 , n71750 );
nor ( n73899 , n72449 , n69744 );
nand ( n73900 , n73898 , n72447 , n73899 );
not ( n73901 , n69908 );
xor ( n73902 , n73900 , n73901 );
nand ( n73903 , n73897 , n73902 );
not ( n73904 , n73903 );
or ( n73905 , n73895 , n73904 );
or ( n73906 , n69947 , n73903 );
nand ( n73907 , n73905 , n73906 );
or ( n73908 , n71272 , n70151 );
nand ( n73909 , n73908 , n70222 );
and ( n73910 , n70196 , n73909 );
nand ( n73911 , n73907 , n73910 );
and ( n73912 , n70222 , n68636 );
not ( n73913 , n73912 );
and ( n73914 , n70222 , n2498 );
not ( n73915 , n73914 );
and ( n73916 , n70222 , n2499 );
nor ( n73917 , n72626 , n73916 );
nand ( n73918 , n73915 , n72812 , n73917 , n72817 );
nor ( n73919 , n70832 , n73918 );
not ( n73920 , n73919 );
or ( n73921 , n73913 , n73920 );
or ( n73922 , n73919 , n73912 );
nand ( n73923 , n73921 , n73922 );
and ( n73924 , n73923 , n70995 );
not ( n73925 , n73912 );
nor ( n73926 , n73925 , n70846 );
nor ( n73927 , n73924 , n73926 );
nand ( n73928 , n73911 , n73927 );
and ( n73929 , n73894 , n73928 );
or ( n73930 , n73893 , n73929 );
buf ( n73931 , n73930 );
buf ( n7793 , 1'b0 );
not ( n73933 , n68838 );
buf ( n73934 , n73933 );
buf ( n73935 , n68634 );
and ( n73936 , n70870 , n69902 );
not ( n73937 , n70870 );
and ( n73938 , n70847 , n73914 );
not ( n73939 , n73914 );
nand ( n73940 , n72812 , n72817 , n73917 );
nor ( n73941 , n70832 , n73940 );
not ( n73942 , n73941 );
or ( n73943 , n73939 , n73942 );
or ( n73944 , n73941 , n73914 );
nand ( n73945 , n73943 , n73944 );
and ( n73946 , n73945 , n70995 );
nor ( n73947 , n73938 , n73946 );
nand ( n73948 , n73911 , n73947 );
and ( n73949 , n73937 , n73948 );
or ( n73950 , n73936 , n73949 );
buf ( n73951 , n73950 );
buf ( n73952 , 1'b0 );
not ( n73953 , n68838 );
buf ( n73954 , n73953 );
buf ( n73955 , n68634 );
or ( n73956 , n72384 , n70210 );
nand ( n73957 , n72405 , n70568 );
nand ( n73958 , n70573 , n72418 );
nand ( n73959 , n70876 , n3915 );
nand ( n73960 , n73957 , n73958 , n73959 );
or ( n73961 , n73765 , n72394 );
not ( n73962 , n70058 );
or ( n73963 , n73843 , n73962 );
or ( n73964 , n70848 , n72410 );
nand ( n73965 , n73961 , n73963 , n73964 );
nor ( n73966 , n73960 , n73965 );
nand ( n73967 , n73956 , n73966 );
buf ( n7829 , n73967 );
buf ( n7830 , 1'b0 );
not ( n73970 , n68838 );
buf ( n7832 , n73970 );
buf ( n7833 , n68634 );
not ( n73973 , n73902 );
not ( n73974 , n73973 );
not ( n73975 , n73897 );
or ( n73976 , n73974 , n73975 );
or ( n73977 , n73973 , n73897 );
nand ( n73978 , n73976 , n73977 );
and ( n73979 , n73978 , n73909 );
and ( n73980 , n72452 , n69359 );
nor ( n73981 , n73979 , n73980 );
or ( n73982 , n73981 , n70210 );
nor ( n73983 , n72633 , n72626 );
not ( n73984 , n73983 );
not ( n73985 , n73916 );
not ( n73986 , n69743 );
or ( n73987 , n73985 , n73986 );
or ( n73988 , n69743 , n73916 );
nand ( n73989 , n73987 , n73988 );
not ( n73990 , n73989 );
or ( n73991 , n73984 , n73990 );
or ( n73992 , n73983 , n73989 );
nand ( n73993 , n73991 , n73992 );
not ( n73994 , n73993 );
nor ( n73995 , n72570 , n72638 );
not ( n73996 , n73995 );
nor ( n73997 , n73996 , n72522 );
not ( n73998 , n73997 );
not ( n73999 , n70553 );
or ( n74000 , n73998 , n73999 );
not ( n74001 , n73995 );
not ( n74002 , n72604 );
or ( n74003 , n74001 , n74002 );
not ( n74004 , n72639 );
not ( n74005 , n72620 );
or ( n74006 , n74004 , n74005 );
nand ( n74007 , n74006 , n72640 );
not ( n74008 , n74007 );
nand ( n74009 , n74003 , n74008 );
not ( n74010 , n74009 );
nand ( n74011 , n74000 , n74010 );
not ( n74012 , n74011 );
or ( n74013 , n73994 , n74012 );
or ( n74014 , n74011 , n73993 );
nand ( n74015 , n74013 , n74014 );
nand ( n74016 , n74015 , n70568 );
xor ( n74017 , n73916 , n69743 );
not ( n74018 , n74017 );
and ( n74019 , n72626 , n69729 );
not ( n74020 , n74019 );
or ( n74021 , n74018 , n74020 );
or ( n74022 , n74019 , n74017 );
nand ( n74023 , n74021 , n74022 );
not ( n74024 , n74023 );
nand ( n74025 , n72674 , n72771 );
nor ( n74026 , n74025 , n72724 );
not ( n74027 , n74026 );
not ( n74028 , n70809 );
or ( n74029 , n74027 , n74028 );
not ( n74030 , n72749 );
not ( n74031 , n74025 );
and ( n74032 , n74030 , n74031 );
not ( n74033 , n72771 );
not ( n74034 , n72766 );
or ( n74035 , n74033 , n74034 );
nand ( n74036 , n74035 , n72772 );
nor ( n74037 , n74032 , n74036 );
nand ( n74038 , n74029 , n74037 );
not ( n74039 , n74038 );
or ( n74040 , n74024 , n74039 );
or ( n74041 , n74038 , n74023 );
nand ( n74042 , n74040 , n74041 );
and ( n74043 , n74042 , n70573 );
nand ( n74044 , n72797 , n70876 , n69721 );
not ( n74045 , n73916 );
not ( n74046 , n72626 );
nand ( n74047 , n74046 , n72812 , n72817 );
nor ( n74048 , n70832 , n74047 );
not ( n74049 , n74048 );
or ( n74050 , n74045 , n74049 );
or ( n74051 , n74048 , n73916 );
nand ( n74052 , n74050 , n74051 );
nand ( n74053 , n74052 , n73766 );
nand ( n74054 , n70849 , n73916 );
nand ( n74055 , n70870 , n69741 );
nand ( n74056 , n74044 , n74053 , n74054 , n74055 );
nor ( n74057 , n74043 , n74056 );
nand ( n74058 , n73982 , n74016 , n74057 );
buf ( n7920 , n74058 );
buf ( n7921 , 1'b0 );
not ( n74061 , n68838 );
buf ( n74062 , n74061 );
buf ( n74063 , n68634 );
or ( n74064 , n72470 , n70210 );
nand ( n74065 , n72646 , n70568 );
and ( n74066 , n72778 , n70573 );
nand ( n74067 , n72801 , n70876 );
nand ( n74068 , n72823 , n70840 );
nand ( n74069 , n70849 , n72626 );
nand ( n74070 , n70870 , n69710 );
nand ( n74071 , n74067 , n74068 , n74069 , n74070 );
nor ( n74072 , n74066 , n74071 );
and ( n74073 , n74065 , n74072 );
nand ( n74074 , n74064 , n74073 );
buf ( n7936 , n74074 );
buf ( n7937 , 1'b0 );
not ( n74077 , n68838 );
buf ( n74078 , n74077 );
buf ( n74079 , n68634 );
or ( n74080 , n72845 , n70210 );
nand ( n74081 , n72866 , n70568 );
and ( n74082 , n72889 , n70573 );
not ( n74083 , n72894 );
nand ( n74084 , n74083 , n70876 );
nand ( n74085 , n72906 , n73766 );
nand ( n74086 , n70849 , n72815 );
nand ( n74087 , n70870 , n69688 );
nand ( n74088 , n74084 , n74085 , n74086 , n74087 );
nor ( n74089 , n74082 , n74088 );
and ( n74090 , n74081 , n74089 );
nand ( n74091 , n74080 , n74090 );
buf ( n7953 , n74091 );
buf ( n74093 , 1'b0 );
not ( n74094 , n68838 );
buf ( n74095 , n74094 );
buf ( n74096 , n68634 );
or ( n74097 , n72933 , n70210 );
nand ( n74098 , n72952 , n70568 );
and ( n74099 , n72967 , n70573 );
nor ( n74100 , n72972 , n73863 );
not ( n74101 , n72534 );
nor ( n74102 , n74101 , n70848 );
nor ( n74103 , n74100 , n74102 );
nand ( n74104 , n72982 , n70840 );
nand ( n74105 , n70870 , n69670 );
nand ( n74106 , n74103 , n74104 , n74105 );
nor ( n74107 , n74099 , n74106 );
and ( n74108 , n74098 , n74107 );
nand ( n74109 , n74097 , n74108 );
buf ( n7971 , n74109 );
buf ( n7972 , 1'b0 );
not ( n74112 , n68838 );
buf ( n74113 , n74112 );
buf ( n74114 , n68634 );
or ( n74115 , n73007 , n70210 );
nand ( n74116 , n73022 , n70568 );
and ( n74117 , n73040 , n70573 );
nand ( n74118 , n73056 , n73766 );
and ( n74119 , n70849 , n72544 );
nor ( n74120 , n73045 , n73863 );
nor ( n74121 , n74119 , n74120 );
nand ( n74122 , n70870 , n69831 );
nand ( n74123 , n74118 , n74121 , n74122 );
nor ( n74124 , n74117 , n74123 );
and ( n74125 , n74116 , n74124 );
nand ( n74126 , n74115 , n74125 );
buf ( n7988 , n74126 );
buf ( n7989 , 1'b0 );
not ( n74129 , n68838 );
buf ( n74130 , n74129 );
buf ( n7992 , n68634 );
or ( n74132 , n73079 , n70210 );
nand ( n74133 , n73092 , n70568 );
and ( n74134 , n73104 , n70573 );
nand ( n74135 , n73117 , n73766 );
not ( n74136 , n73109 );
not ( n74137 , n70875 );
and ( n74138 , n74136 , n74137 );
and ( n74139 , n70849 , n72557 );
nor ( n74140 , n74138 , n74139 );
nand ( n74141 , n70870 , n69916 );
nand ( n74142 , n74135 , n74140 , n74141 );
nor ( n74143 , n74134 , n74142 );
and ( n74144 , n74133 , n74143 );
nand ( n74145 , n74132 , n74144 );
buf ( n74146 , n74145 );
buf ( n74147 , 1'b0 );
not ( n74148 , n68838 );
buf ( n8010 , n74148 );
buf ( n8011 , n68634 );
or ( n74151 , n73143 , n70210 );
nand ( n74152 , n73161 , n70568 );
and ( n74153 , n73189 , n70573 );
nand ( n74154 , n73202 , n73766 );
not ( n74155 , n73194 );
not ( n74156 , n70875 );
and ( n74157 , n74155 , n74156 );
and ( n74158 , n70849 , n72510 );
nor ( n74159 , n74157 , n74158 );
nand ( n74160 , n70870 , n69749 );
nand ( n74161 , n74154 , n74159 , n74160 );
nor ( n74162 , n74153 , n74161 );
and ( n74163 , n74152 , n74162 );
nand ( n74164 , n74151 , n74163 );
buf ( n8026 , n74164 );
buf ( n8027 , 1'b0 );
not ( n74167 , n68838 );
buf ( n74168 , n74167 );
buf ( n74169 , n68634 );
or ( n74170 , n73224 , n70210 );
nand ( n74171 , n73239 , n70568 );
and ( n74172 , n73253 , n70573 );
nand ( n74173 , n73266 , n73766 );
not ( n74174 , n73258 );
not ( n74175 , n70875 );
and ( n74176 , n74174 , n74175 );
and ( n74177 , n70849 , n72499 );
nor ( n74178 , n74176 , n74177 );
nand ( n74179 , n70870 , n69783 );
nand ( n74180 , n74173 , n74178 , n74179 );
nor ( n74181 , n74172 , n74180 );
and ( n74182 , n74171 , n74181 );
nand ( n74183 , n74170 , n74182 );
buf ( n8045 , n74183 );
buf ( n8046 , 1'b0 );
not ( n74186 , n68838 );
buf ( n74187 , n74186 );
buf ( n74188 , n68634 );
or ( n74189 , n73289 , n70210 );
nand ( n74190 , n73304 , n70568 );
and ( n74191 , n73323 , n70573 );
nand ( n74192 , n73337 , n73766 );
not ( n74193 , n70875 );
not ( n74194 , n73328 );
and ( n74195 , n74193 , n74194 );
and ( n74196 , n70849 , n72475 );
nor ( n74197 , n74195 , n74196 );
nand ( n74198 , n70870 , n69876 );
nand ( n74199 , n74192 , n74197 , n74198 );
nor ( n74200 , n74191 , n74199 );
and ( n74201 , n74190 , n74200 );
nand ( n74202 , n74189 , n74201 );
buf ( n74203 , n74202 );
buf ( n74204 , 1'b0 );
not ( n74205 , n68838 );
buf ( n8067 , n74205 );
buf ( n8068 , n68634 );
or ( n74208 , n73361 , n70210 );
nand ( n74209 , n73369 , n70568 );
and ( n74210 , n70573 , n73381 );
nand ( n74211 , n73394 , n73766 );
not ( n74212 , n70875 );
not ( n74213 , n73386 );
and ( n74214 , n74212 , n74213 );
and ( n74215 , n70849 , n72485 );
nor ( n74216 , n74214 , n74215 );
nand ( n74217 , n70870 , n69862 );
nand ( n74218 , n74211 , n74216 , n74217 );
nor ( n74219 , n74210 , n74218 );
and ( n74220 , n74209 , n74219 );
nand ( n74221 , n74208 , n74220 );
buf ( n74222 , n74221 );
buf ( n8084 , 1'b0 );
not ( n74224 , n68838 );
buf ( n74225 , n74224 );
buf ( n74226 , n68634 );
or ( n74227 , n73416 , n70210 );
not ( n74228 , n73435 );
or ( n74229 , n73765 , n74228 );
not ( n74230 , n70051 );
or ( n74231 , n73843 , n74230 );
not ( n74232 , n70503 );
or ( n74233 , n70848 , n74232 );
nand ( n74234 , n74229 , n74231 , n74233 );
not ( n74235 , n73426 );
not ( n74236 , n70568 );
or ( n74237 , n74235 , n74236 );
nand ( n74238 , n70573 , n73428 );
nand ( n74239 , n70876 , n70041 );
nand ( n74240 , n74237 , n74238 , n74239 );
nor ( n74241 , n74234 , n74240 );
nand ( n74242 , n74227 , n74241 );
buf ( n74243 , n74242 );
buf ( n74244 , 1'b0 );
not ( n74245 , n68838 );
buf ( n74246 , n74245 );
buf ( n74247 , n68634 );
or ( n74248 , n73445 , n70210 );
nand ( n74249 , n71134 , n70568 );
and ( n74250 , n71188 , n70573 );
nand ( n74251 , n71200 , n73766 );
not ( n74252 , n70875 );
not ( n74253 , n73453 );
and ( n74254 , n74252 , n74253 );
and ( n74255 , n70849 , n71122 );
nor ( n74256 , n74254 , n74255 );
nand ( n74257 , n70870 , n69798 );
nand ( n74258 , n74251 , n74256 , n74257 );
nor ( n74259 , n74250 , n74258 );
and ( n74260 , n74249 , n74259 );
nand ( n74261 , n74248 , n74260 );
buf ( n74262 , n74261 );
buf ( n74263 , 1'b0 );
not ( n74264 , n68838 );
buf ( n8126 , n74264 );
buf ( n8127 , n68634 );
or ( n74267 , n73468 , n70210 );
nand ( n74268 , n71233 , n70568 );
and ( n74269 , n71248 , n70573 );
nand ( n74270 , n71256 , n70840 );
not ( n74271 , n70875 );
not ( n74272 , n73475 );
and ( n74273 , n74271 , n74272 );
and ( n74274 , n70849 , n71092 );
nor ( n74275 , n74273 , n74274 );
nand ( n74276 , n70870 , n69806 );
nand ( n74277 , n74270 , n74275 , n74276 );
nor ( n74278 , n74269 , n74277 );
and ( n74279 , n74268 , n74278 );
nand ( n74280 , n74267 , n74279 );
buf ( n8142 , n74280 );
buf ( n8143 , 1'b0 );
not ( n74283 , n68838 );
buf ( n74284 , n74283 );
buf ( n74285 , n68634 );
or ( n74286 , n71281 , n70210 );
nand ( n74287 , n71291 , n70568 );
and ( n74288 , n71304 , n70573 );
nand ( n74289 , n71312 , n70840 );
not ( n74290 , n70875 );
not ( n74291 , n73497 );
and ( n74292 , n74290 , n74291 );
and ( n74293 , n70849 , n71074 );
nor ( n74294 , n74292 , n74293 );
nand ( n74295 , n73844 , n69651 );
nand ( n74296 , n74289 , n74294 , n74295 );
nor ( n74297 , n74288 , n74296 );
nand ( n74298 , n74286 , n74287 , n74297 );
buf ( n74299 , n74298 );
buf ( n74300 , 1'b0 );
not ( n74301 , n68838 );
buf ( n8163 , n74301 );
buf ( n8164 , n68634 );
or ( n74304 , n73532 , n70210 );
and ( n74305 , n70573 , n71416 );
nand ( n74306 , n71428 , n70840 );
not ( n74307 , n73863 );
not ( n74308 , n73539 );
and ( n74309 , n74307 , n74308 );
and ( n74310 , n70849 , n70238 );
nor ( n74311 , n74309 , n74310 );
nand ( n74312 , n73844 , n3466 );
nand ( n74313 , n74306 , n74311 , n74312 );
nor ( n74314 , n74305 , n74313 );
nand ( n74315 , n71390 , n70568 );
and ( n74316 , n74314 , n74315 );
nand ( n74317 , n74304 , n74316 );
buf ( n74318 , n74317 );
buf ( n74319 , 1'b0 );
not ( n74320 , n68838 );
buf ( n74321 , n74320 );
buf ( n74322 , n68634 );
or ( n74323 , n73557 , n70210 );
and ( n74324 , n70573 , n71491 );
nand ( n74325 , n71501 , n73766 );
not ( n74326 , n70875 );
not ( n74327 , n73563 );
and ( n74328 , n74326 , n74327 );
and ( n74329 , n70849 , n70327 );
nor ( n74330 , n74328 , n74329 );
nand ( n74331 , n73844 , n3450 );
nand ( n74332 , n74325 , n74330 , n74331 );
nor ( n74333 , n74324 , n74332 );
nand ( n74334 , n71475 , n70568 );
and ( n74335 , n74333 , n74334 );
nand ( n74336 , n74323 , n74335 );
buf ( n74337 , n74336 );
buf ( n8199 , 1'b0 );
not ( n74339 , n68838 );
buf ( n8201 , n74339 );
buf ( n8202 , n68634 );
or ( n74342 , n73591 , n70210 );
and ( n74343 , n70573 , n73633 );
nand ( n74344 , n73642 , n70840 );
not ( n74345 , n70875 );
not ( n74346 , n73598 );
and ( n74347 , n74345 , n74346 );
and ( n74348 , n70849 , n70296 );
nor ( n74349 , n74347 , n74348 );
nand ( n74350 , n73844 , n69558 );
nand ( n74351 , n74344 , n74349 , n74350 );
nor ( n74352 , n74343 , n74351 );
nand ( n74353 , n73614 , n70568 );
and ( n74354 , n74352 , n74353 );
nand ( n74355 , n74342 , n74354 );
buf ( n8217 , n74355 );
buf ( n74357 , 1'b0 );
not ( n74358 , n68838 );
buf ( n74359 , n74358 );
buf ( n8221 , n68634 );
or ( n74361 , n73655 , n70210 );
and ( n74362 , n70573 , n71558 );
nand ( n74363 , n71567 , n73766 );
not ( n74364 , n70875 );
not ( n74365 , n73662 );
and ( n74366 , n74364 , n74365 );
and ( n74367 , n70849 , n70308 );
nor ( n74368 , n74366 , n74367 );
nand ( n74369 , n73844 , n69577 );
nand ( n74370 , n74363 , n74368 , n74369 );
nor ( n74371 , n74362 , n74370 );
nand ( n74372 , n71545 , n70568 );
and ( n74373 , n74371 , n74372 );
nand ( n74374 , n74361 , n74373 );
buf ( n74375 , n74374 );
buf ( n8237 , 1'b0 );
not ( n74377 , n68838 );
buf ( n74378 , n74377 );
buf ( n74379 , n68634 );
or ( n74380 , n73680 , n70210 );
and ( n74381 , n70573 , n71638 );
nand ( n74382 , n71647 , n70840 );
not ( n74383 , n70875 );
not ( n74384 , n73686 );
and ( n74385 , n74383 , n74384 );
and ( n74386 , n70849 , n70273 );
nor ( n74387 , n74385 , n74386 );
nand ( n74388 , n73844 , n69507 );
nand ( n74389 , n74382 , n74387 , n74388 );
nor ( n74390 , n74381 , n74389 );
nand ( n74391 , n71618 , n70568 );
and ( n74392 , n74390 , n74391 );
nand ( n74393 , n74380 , n74392 );
buf ( n74394 , n74393 );
buf ( n74395 , 1'b0 );
not ( n74396 , n68838 );
buf ( n74397 , n74396 );
buf ( n74398 , n68634 );
or ( n74399 , n73704 , n70210 );
and ( n74400 , n70573 , n71699 );
nand ( n74401 , n71707 , n70840 );
not ( n74402 , n73863 );
not ( n74403 , n73711 );
and ( n74404 , n74402 , n74403 );
and ( n74405 , n70849 , n70253 );
nor ( n74406 , n74404 , n74405 );
nand ( n74407 , n73844 , n69522 );
nand ( n74408 , n74401 , n74406 , n74407 );
nor ( n74409 , n74400 , n74408 );
nand ( n74410 , n71685 , n70568 );
and ( n74411 , n74409 , n74410 );
nand ( n74412 , n74399 , n74411 );
buf ( n8274 , n74412 );
buf ( n8275 , 1'b0 );
not ( n74415 , n68838 );
buf ( n8277 , n74415 );
buf ( n74417 , n68634 );
or ( n74418 , n73735 , n70210 );
not ( n74419 , n3815 );
not ( n74420 , n70870 );
or ( n74421 , n74419 , n74420 );
or ( n74422 , n70840 , n70849 );
nand ( n74423 , n74422 , n70522 );
nand ( n74424 , n74421 , n74423 );
nand ( n74425 , n70568 , n73745 );
nand ( n74426 , n70573 , n73753 );
nand ( n74427 , n70876 , n69950 );
nand ( n74428 , n74425 , n74426 , n74427 );
nor ( n74429 , n74424 , n74428 );
nand ( n74430 , n74418 , n74429 );
buf ( n74431 , n74430 );
buf ( n74432 , 1'b0 );
not ( n74433 , n68838 );
buf ( n8295 , n74433 );
buf ( n8296 , n68634 );
and ( n74436 , n72040 , n70196 );
nand ( n74437 , n72055 , n70929 );
nand ( n74438 , n72048 , n70571 );
not ( n74439 , n73794 );
not ( n74440 , n70846 );
and ( n74441 , n74439 , n74440 );
and ( n74442 , n72069 , n70995 );
nor ( n74443 , n74441 , n74442 );
nand ( n74444 , n74437 , n74438 , n74443 );
nor ( n74445 , n74436 , n74444 );
or ( n74446 , n74445 , n71016 );
nand ( n74447 , n71016 , n69546 );
nand ( n74448 , n74446 , n74447 );
buf ( n74449 , n74448 );
buf ( n8311 , 1'b0 );
not ( n74451 , n68838 );
buf ( n74452 , n74451 );
buf ( n74453 , n68634 );
not ( n74454 , n72094 );
and ( n74455 , n74454 , n70923 );
not ( n74456 , n70929 );
not ( n74457 , n72112 );
or ( n74458 , n74456 , n74457 );
and ( n74459 , n72130 , n70571 );
not ( n74460 , n70847 );
not ( n74461 , n70388 );
or ( n74462 , n74460 , n74461 );
nand ( n74463 , n72150 , n70995 );
nand ( n74464 , n74462 , n74463 );
nor ( n74465 , n74459 , n74464 );
nand ( n74466 , n74458 , n74465 );
nor ( n74467 , n74455 , n74466 );
or ( n74468 , n74467 , n71016 );
not ( n74469 , n71016 );
not ( n74470 , n74469 );
nand ( n74471 , n74470 , n3316 );
nand ( n74472 , n74468 , n74471 );
buf ( n74473 , n74472 );
buf ( n74474 , 1'b0 );
not ( n74475 , n68838 );
buf ( n74476 , n74475 );
buf ( n74477 , n68634 );
not ( n74478 , n72169 );
and ( n74479 , n74478 , n70923 );
nand ( n74480 , n72191 , n70931 );
nand ( n74481 , n72178 , n70571 );
and ( n74482 , n70477 , n70847 );
and ( n74483 , n72207 , n70995 );
nor ( n74484 , n74482 , n74483 );
nand ( n74485 , n74480 , n74481 , n74484 );
nor ( n74486 , n74479 , n74485 );
or ( n74487 , n74486 , n71016 );
not ( n74488 , n71343 );
nand ( n74489 , n74488 , n3282 );
nand ( n74490 , n74487 , n74489 );
buf ( n74491 , n74490 );
buf ( n8353 , 1'b0 );
not ( n74493 , n68838 );
buf ( n74494 , n74493 );
buf ( n74495 , n68634 );
not ( n74496 , n72230 );
and ( n74497 , n74496 , n70923 );
not ( n74498 , n70929 );
not ( n74499 , n72242 );
or ( n74500 , n74498 , n74499 );
and ( n74501 , n72254 , n70571 );
not ( n74502 , n70847 );
not ( n74503 , n70432 );
or ( n74504 , n74502 , n74503 );
nand ( n74505 , n72269 , n70995 );
nand ( n74506 , n74504 , n74505 );
nor ( n74507 , n74501 , n74506 );
nand ( n74508 , n74500 , n74507 );
nor ( n74509 , n74497 , n74508 );
or ( n74510 , n74509 , n71016 );
nand ( n74511 , n74470 , n69492 );
nand ( n74512 , n74510 , n74511 );
buf ( n74513 , n74512 );
buf ( n74514 , 1'b0 );
not ( n74515 , n68838 );
buf ( n74516 , n74515 );
buf ( n74517 , n68634 );
and ( n74518 , n72289 , n70923 );
not ( n74519 , n70929 );
not ( n74520 , n72293 );
or ( n74521 , n74519 , n74520 );
and ( n74522 , n72300 , n70571 );
not ( n74523 , n72302 );
not ( n74524 , n70847 );
or ( n74525 , n74523 , n74524 );
not ( n74526 , n70995 );
or ( n74527 , n73867 , n74526 );
nand ( n74528 , n74525 , n74527 );
nor ( n74529 , n74522 , n74528 );
nand ( n74530 , n74521 , n74529 );
nor ( n74531 , n74518 , n74530 );
or ( n74532 , n74531 , n71344 );
nand ( n74533 , n74488 , n3342 );
nand ( n74534 , n74532 , n74533 );
buf ( n8396 , n74534 );
buf ( n8397 , 1'b0 );
not ( n74537 , n68838 );
buf ( n74538 , n74537 );
buf ( n74539 , n68634 );
not ( n74540 , n74469 );
or ( n74541 , n72340 , n70195 );
and ( n74542 , n72356 , n70571 );
not ( n74543 , n70420 );
not ( n74544 , n70847 );
or ( n74545 , n74543 , n74544 );
nand ( n74546 , n72365 , n70995 );
nand ( n74547 , n74545 , n74546 );
nor ( n74548 , n74542 , n74547 );
nand ( n74549 , n72345 , n70929 );
and ( n74550 , n74548 , n74549 );
nand ( n74551 , n74541 , n74550 );
not ( n74552 , n74551 );
or ( n74553 , n74540 , n74552 );
nand ( n74554 , n71344 , n3301 );
nand ( n74555 , n74553 , n74554 );
buf ( n8417 , n74555 );
buf ( n74557 , 1'b0 );
not ( n74558 , n68838 );
buf ( n74559 , n74558 );
buf ( n8421 , n68634 );
and ( n74561 , n71016 , n69936 );
not ( n74562 , n71016 );
and ( n74563 , n74562 , n73928 );
or ( n74564 , n74561 , n74563 );
buf ( n74565 , n74564 );
buf ( n8427 , 1'b0 );
not ( n74567 , n68838 );
buf ( n74568 , n74567 );
buf ( n74569 , n68634 );
not ( n74570 , n73948 );
or ( n74571 , n74570 , n74470 );
or ( n74572 , n71343 , n69898 );
nand ( n74573 , n74571 , n74572 );
buf ( n74574 , n74573 );
buf ( n8436 , 1'b0 );
not ( n74576 , n68838 );
buf ( n8438 , n74576 );
buf ( n8439 , n68634 );
not ( n74579 , n72384 );
and ( n74580 , n74579 , n70196 );
not ( n74581 , n70929 );
not ( n74582 , n72405 );
or ( n74583 , n74581 , n74582 );
and ( n74584 , n72418 , n70571 );
or ( n74585 , n72410 , n70846 );
or ( n74586 , n72394 , n74526 );
nand ( n74587 , n74585 , n74586 );
nor ( n74588 , n74584 , n74587 );
nand ( n74589 , n74583 , n74588 );
nor ( n74590 , n74580 , n74589 );
or ( n74591 , n74590 , n71016 );
nand ( n74592 , n71344 , n70069 );
nand ( n74593 , n74591 , n74592 );
buf ( n8455 , n74593 );
buf ( n74595 , 1'b0 );
not ( n74596 , n68838 );
buf ( n74597 , n74596 );
buf ( n8459 , n68634 );
not ( n74599 , n73981 );
and ( n74600 , n74599 , n70196 );
not ( n74601 , n70929 );
not ( n74602 , n74015 );
or ( n74603 , n74601 , n74602 );
and ( n74604 , n74042 , n70571 );
not ( n74605 , n70995 );
not ( n74606 , n74052 );
or ( n74607 , n74605 , n74606 );
nand ( n74608 , n70847 , n73916 );
nand ( n74609 , n74607 , n74608 );
nor ( n74610 , n74604 , n74609 );
nand ( n74611 , n74603 , n74610 );
nor ( n74612 , n74600 , n74611 );
or ( n74613 , n74612 , n74488 );
nand ( n74614 , n71344 , n69737 );
nand ( n74615 , n74613 , n74614 );
buf ( n74616 , n74615 );
buf ( n74617 , 1'b0 );
not ( n74618 , n68838 );
buf ( n74619 , n74618 );
buf ( n74620 , n68634 );
not ( n74621 , n72470 );
not ( n74622 , n70923 );
not ( n74623 , n74622 );
and ( n74624 , n74621 , n74623 );
nand ( n74625 , n72646 , n70929 );
and ( n74626 , n72778 , n70571 );
not ( n74627 , n70995 );
not ( n74628 , n72823 );
or ( n74629 , n74627 , n74628 );
nand ( n74630 , n70847 , n72626 );
nand ( n74631 , n74629 , n74630 );
nor ( n74632 , n74626 , n74631 );
nand ( n74633 , n74625 , n74632 );
nor ( n74634 , n74624 , n74633 );
or ( n74635 , n74634 , n74488 );
nand ( n74636 , n74470 , n69715 );
nand ( n74637 , n74635 , n74636 );
buf ( n8499 , n74637 );
buf ( n74639 , 1'b0 );
not ( n74640 , n68838 );
buf ( n8502 , n74640 );
buf ( n74642 , n68634 );
not ( n74643 , n72845 );
and ( n74644 , n74643 , n74623 );
and ( n74645 , n72889 , n70571 );
not ( n74646 , n70995 );
not ( n74647 , n72906 );
or ( n74648 , n74646 , n74647 );
nand ( n74649 , n70847 , n72815 );
nand ( n74650 , n74648 , n74649 );
nor ( n74651 , n74645 , n74650 );
nand ( n74652 , n72866 , n70929 );
nand ( n74653 , n74651 , n74652 );
nor ( n74654 , n74644 , n74653 );
or ( n74655 , n74654 , n74488 );
nand ( n74656 , n74470 , n69693 );
nand ( n74657 , n74655 , n74656 );
buf ( n8519 , n74657 );
buf ( n8520 , 1'b0 );
not ( n74660 , n68838 );
buf ( n74661 , n74660 );
buf ( n74662 , n68634 );
not ( n74663 , n72933 );
and ( n74664 , n74663 , n70196 );
nand ( n74665 , n72952 , n70929 );
and ( n74666 , n72967 , n70571 );
not ( n74667 , n70995 );
not ( n74668 , n72982 );
or ( n74669 , n74667 , n74668 );
nand ( n74670 , n70847 , n72534 );
nand ( n74671 , n74669 , n74670 );
nor ( n74672 , n74666 , n74671 );
nand ( n74673 , n74665 , n74672 );
nor ( n74674 , n74664 , n74673 );
or ( n74675 , n74674 , n71016 );
nand ( n74676 , n71344 , n69665 );
nand ( n74677 , n74675 , n74676 );
buf ( n8539 , n74677 );
buf ( n8540 , 1'b0 );
not ( n74680 , n68838 );
buf ( n74681 , n74680 );
buf ( n74682 , n68634 );
not ( n74683 , n73007 );
and ( n74684 , n74683 , n74623 );
nand ( n74685 , n73022 , n70929 );
and ( n74686 , n70571 , n73040 );
not ( n74687 , n70995 );
not ( n74688 , n73056 );
or ( n74689 , n74687 , n74688 );
nand ( n74690 , n70847 , n72544 );
nand ( n74691 , n74689 , n74690 );
nor ( n74692 , n74686 , n74691 );
nand ( n74693 , n74685 , n74692 );
nor ( n74694 , n74684 , n74693 );
or ( n74695 , n74694 , n71344 );
nand ( n74696 , n74470 , n69837 );
nand ( n74697 , n74695 , n74696 );
buf ( n74698 , n74697 );
buf ( n74699 , 1'b0 );
not ( n74700 , n68838 );
buf ( n74701 , n74700 );
buf ( n8563 , n68634 );
not ( n74703 , n73079 );
and ( n74704 , n74703 , n70923 );
nand ( n74705 , n73092 , n70929 );
and ( n74706 , n73104 , n70571 );
not ( n74707 , n70995 );
not ( n74708 , n73117 );
or ( n74709 , n74707 , n74708 );
nand ( n74710 , n70847 , n72557 );
nand ( n74711 , n74709 , n74710 );
nor ( n74712 , n74706 , n74711 );
nand ( n74713 , n74705 , n74712 );
nor ( n74714 , n74704 , n74713 );
or ( n74715 , n74714 , n74470 );
nand ( n74716 , n74470 , n69912 );
nand ( n74717 , n74715 , n74716 );
buf ( n74718 , n74717 );
buf ( n8580 , 1'b0 );
not ( n74720 , n68838 );
buf ( n74721 , n74720 );
buf ( n74722 , n68634 );
not ( n74723 , n73143 );
and ( n74724 , n74723 , n70923 );
nand ( n74725 , n73161 , n70929 );
and ( n74726 , n73189 , n70571 );
not ( n74727 , n70995 );
not ( n74728 , n73202 );
or ( n74729 , n74727 , n74728 );
nand ( n74730 , n70847 , n72510 );
nand ( n74731 , n74729 , n74730 );
nor ( n74732 , n74726 , n74731 );
nand ( n74733 , n74725 , n74732 );
nor ( n74734 , n74724 , n74733 );
or ( n74735 , n74734 , n71344 );
nand ( n74736 , n74488 , n69755 );
nand ( n74737 , n74735 , n74736 );
buf ( n74738 , n74737 );
buf ( n74739 , 1'b0 );
not ( n74740 , n68838 );
buf ( n8602 , n74740 );
buf ( n8603 , n68634 );
not ( n74743 , n73224 );
and ( n74744 , n74743 , n70923 );
nand ( n74745 , n73239 , n70929 );
and ( n74746 , n73253 , n70571 );
not ( n74747 , n70995 );
not ( n74748 , n73266 );
or ( n74749 , n74747 , n74748 );
nand ( n74750 , n70847 , n72499 );
nand ( n74751 , n74749 , n74750 );
nor ( n74752 , n74746 , n74751 );
nand ( n74753 , n74745 , n74752 );
nor ( n74754 , n74744 , n74753 );
or ( n74755 , n74754 , n71344 );
nand ( n74756 , n74488 , n69777 );
nand ( n74757 , n74755 , n74756 );
buf ( n8619 , n74757 );
buf ( n74759 , 1'b0 );
not ( n74760 , n68838 );
buf ( n74761 , n74760 );
buf ( n74762 , n68634 );
not ( n74763 , n73289 );
and ( n74764 , n74763 , n70923 );
nand ( n74765 , n73304 , n70929 );
and ( n74766 , n73323 , n70571 );
not ( n74767 , n70995 );
not ( n74768 , n73337 );
or ( n74769 , n74767 , n74768 );
nand ( n74770 , n70847 , n72475 );
nand ( n74771 , n74769 , n74770 );
nor ( n74772 , n74766 , n74771 );
nand ( n74773 , n74765 , n74772 );
nor ( n74774 , n74764 , n74773 );
or ( n74775 , n74774 , n74470 );
nand ( n74776 , n74488 , n69882 );
nand ( n74777 , n74775 , n74776 );
buf ( n8639 , n74777 );
buf ( n74779 , 1'b0 );
not ( n74780 , n68838 );
buf ( n74781 , n74780 );
buf ( n8643 , n68634 );
not ( n74783 , n73361 );
and ( n74784 , n74783 , n74623 );
not ( n74785 , n70929 );
not ( n74786 , n73369 );
or ( n74787 , n74785 , n74786 );
and ( n74788 , n73381 , n70571 );
not ( n74789 , n70995 );
not ( n74790 , n73394 );
or ( n74791 , n74789 , n74790 );
nand ( n74792 , n70847 , n72485 );
nand ( n74793 , n74791 , n74792 );
nor ( n74794 , n74788 , n74793 );
nand ( n74795 , n74787 , n74794 );
nor ( n74796 , n74784 , n74795 );
or ( n74797 , n74796 , n71344 );
nand ( n74798 , n74470 , n69856 );
nand ( n74799 , n74797 , n74798 );
buf ( n8661 , n74799 );
buf ( n74801 , 1'b0 );
not ( n74802 , n68838 );
buf ( n74803 , n74802 );
buf ( n8665 , n68634 );
not ( n74805 , n73416 );
and ( n74806 , n74805 , n70196 );
not ( n74807 , n70929 );
not ( n74808 , n73426 );
or ( n74809 , n74807 , n74808 );
and ( n74810 , n73428 , n70571 );
and ( n74811 , n70847 , n70503 );
and ( n74812 , n73435 , n70995 );
nor ( n74813 , n74810 , n74811 , n74812 );
nand ( n74814 , n74809 , n74813 );
nor ( n74815 , n74806 , n74814 );
or ( n74816 , n74815 , n71016 );
nand ( n74817 , n71344 , n70049 );
nand ( n74818 , n74816 , n74817 );
buf ( n74819 , n74818 );
buf ( n8681 , 1'b0 );
not ( n74821 , n68838 );
buf ( n74822 , n74821 );
buf ( n74823 , n68634 );
and ( n74824 , n73590 , n70923 );
not ( n74825 , n70931 );
not ( n74826 , n73614 );
or ( n74827 , n74825 , n74826 );
and ( n74828 , n73633 , n70571 );
not ( n74829 , n70995 );
not ( n74830 , n73642 );
or ( n74831 , n74829 , n74830 );
nand ( n74832 , n70296 , n70847 );
nand ( n74833 , n74831 , n74832 );
nor ( n74834 , n74828 , n74833 );
nand ( n74835 , n74827 , n74834 );
nor ( n74836 , n74824 , n74835 );
or ( n74837 , n74836 , n71016 );
nand ( n74838 , n71016 , n69562 );
nand ( n74839 , n74837 , n74838 );
buf ( n74840 , n74839 );
buf ( n74841 , 1'b0 );
not ( n74842 , n68838 );
buf ( n74843 , n74842 );
buf ( n74844 , n68634 );
not ( n74845 , n73735 );
not ( n74846 , n70195 );
and ( n74847 , n74845 , n74846 );
not ( n74848 , n70571 );
not ( n74849 , n73753 );
or ( n74850 , n74848 , n74849 );
and ( n74851 , n73745 , n70929 );
nand ( n74852 , n70846 , n74526 );
and ( n74853 , n74852 , n70522 );
nor ( n74854 , n74851 , n74853 );
nand ( n74855 , n74850 , n74854 );
nor ( n74856 , n74847 , n74855 );
or ( n74857 , n74856 , n71016 );
nand ( n74858 , n71016 , n69957 );
nand ( n74859 , n74857 , n74858 );
buf ( n8721 , n74859 );
buf ( n74861 , 1'b0 );
not ( n74862 , n68838 );
buf ( n8724 , n74862 );
buf ( n74864 , n68634 );
not ( n74865 , n70164 );
and ( n74866 , n70148 , n74865 , n70181 , n70854 );
not ( n74867 , n74866 );
or ( n74868 , n71015 , n74867 );
nand ( n74869 , n74867 , n69541 );
nand ( n74870 , n74868 , n74869 );
buf ( n8732 , n74870 );
buf ( n8733 , 1'b0 );
not ( n74873 , n68838 );
buf ( n8735 , n74873 );
buf ( n74875 , n68634 );
or ( n74876 , n74445 , n74867 );
nand ( n74877 , n74867 , n3412 );
nand ( n74878 , n74876 , n74877 );
buf ( n8740 , n74878 );
buf ( n8741 , 1'b0 );
not ( n74881 , n68838 );
buf ( n74882 , n74881 );
buf ( n74883 , n68634 );
or ( n74884 , n74467 , n74867 );
nand ( n74885 , n74867 , n69468 );
nand ( n74886 , n74884 , n74885 );
buf ( n74887 , n74886 );
buf ( n74888 , 1'b0 );
not ( n74889 , n68838 );
buf ( n8751 , n74889 );
buf ( n74891 , n68634 );
or ( n74892 , n74486 , n74867 );
nand ( n74893 , n74867 , n69433 );
nand ( n74894 , n74892 , n74893 );
buf ( n8756 , n74894 );
buf ( n74896 , 1'b0 );
not ( n74897 , n68838 );
buf ( n74898 , n74897 );
buf ( n74899 , n68634 );
or ( n74900 , n74509 , n74867 );
nand ( n74901 , n74867 , n69500 );
nand ( n74902 , n74900 , n74901 );
buf ( n74903 , n74902 );
buf ( n74904 , 1'b0 );
not ( n74905 , n68838 );
buf ( n8767 , n74905 );
buf ( n74907 , n68634 );
or ( n74908 , n74531 , n74867 );
nand ( n74909 , n74867 , n69477 );
nand ( n74910 , n74908 , n74909 );
buf ( n74911 , n74910 );
buf ( n74912 , 1'b0 );
not ( n74913 , n68838 );
buf ( n74914 , n74913 );
buf ( n74915 , n68634 );
not ( n74916 , n74551 );
or ( n74917 , n74916 , n74867 );
or ( n74918 , n74866 , n69448 );
nand ( n74919 , n74917 , n74918 );
buf ( n74920 , n74919 );
buf ( n74921 , 1'b0 );
not ( n74922 , n68838 );
buf ( n74923 , n74922 );
buf ( n8785 , n68634 );
and ( n74925 , n74867 , n3799 );
not ( n74926 , n74867 );
and ( n74927 , n74926 , n73928 );
or ( n74928 , n74925 , n74927 );
buf ( n74929 , n74928 );
buf ( n8791 , 1'b0 );
not ( n74931 , n68838 );
buf ( n8793 , n74931 );
buf ( n8794 , n68634 );
or ( n74934 , n74570 , n74867 );
or ( n74935 , n74866 , n69905 );
nand ( n74936 , n74934 , n74935 );
buf ( n8798 , n74936 );
buf ( n74938 , 1'b0 );
not ( n74939 , n68838 );
buf ( n74940 , n74939 );
buf ( n8802 , n68634 );
or ( n74942 , n74590 , n74867 );
nand ( n74943 , n74867 , n70063 );
nand ( n74944 , n74942 , n74943 );
buf ( n8806 , n74944 );
buf ( n8807 , 1'b0 );
not ( n74947 , n68838 );
buf ( n8809 , n74947 );
buf ( n74949 , n68634 );
or ( n74950 , n74612 , n74867 );
nand ( n74951 , n74867 , n69732 );
nand ( n74952 , n74950 , n74951 );
buf ( n8814 , n74952 );
buf ( n8815 , 1'b0 );
not ( n74955 , n68838 );
buf ( n74956 , n74955 );
buf ( n74957 , n68634 );
or ( n74958 , n74634 , n74867 );
nand ( n74959 , n74867 , n69725 );
nand ( n74960 , n74958 , n74959 );
buf ( n74961 , n74960 );
buf ( n74962 , 1'b0 );
not ( n74963 , n68838 );
buf ( n8825 , n74963 );
buf ( n74965 , n68634 );
not ( n74966 , n69697 );
and ( n74967 , n74867 , n74966 );
not ( n74968 , n74867 );
and ( n74969 , n74968 , n74654 );
nor ( n74970 , n74967 , n74969 );
buf ( n74971 , n74970 );
buf ( n74972 , 1'b0 );
not ( n74973 , n68838 );
buf ( n8835 , n74973 );
buf ( n8836 , n68634 );
or ( n74976 , n74674 , n74867 );
nand ( n74977 , n74867 , n69681 );
nand ( n74978 , n74976 , n74977 );
buf ( n8840 , n74978 );
buf ( n8841 , 1'b0 );
not ( n74981 , n68838 );
buf ( n74982 , n74981 );
buf ( n74983 , n68634 );
or ( n74984 , n74694 , n74867 );
nand ( n74985 , n74867 , n69842 );
nand ( n74986 , n74984 , n74985 );
buf ( n74987 , n74986 );
buf ( n74988 , 1'b0 );
not ( n74989 , n68838 );
buf ( n74990 , n74989 );
buf ( n74991 , n68634 );
or ( n74992 , n74714 , n74867 );
nand ( n74993 , n74867 , n69923 );
nand ( n74994 , n74992 , n74993 );
buf ( n74995 , n74994 );
buf ( n74996 , 1'b0 );
not ( n74997 , n68838 );
buf ( n8859 , n74997 );
buf ( n8860 , n68634 );
or ( n75000 , n74734 , n74867 );
nand ( n75001 , n74867 , n69761 );
nand ( n75002 , n75000 , n75001 );
buf ( n75003 , n75002 );
buf ( n8865 , 1'b0 );
not ( n75005 , n68838 );
buf ( n8867 , n75005 );
buf ( n8868 , n68634 );
or ( n75008 , n74754 , n74867 );
nand ( n75009 , n74867 , n69788 );
nand ( n75010 , n75008 , n75009 );
buf ( n8872 , n75010 );
buf ( n75012 , 1'b0 );
not ( n75013 , n68838 );
buf ( n75014 , n75013 );
buf ( n8876 , n68634 );
or ( n75016 , n74774 , n74867 );
nand ( n75017 , n74867 , n69892 );
nand ( n75018 , n75016 , n75017 );
buf ( n8880 , n75018 );
buf ( n8881 , 1'b0 );
not ( n75021 , n68838 );
buf ( n8883 , n75021 );
buf ( n75023 , n68634 );
or ( n75024 , n74796 , n74867 );
nand ( n75025 , n74867 , n69867 );
nand ( n75026 , n75024 , n75025 );
buf ( n8888 , n75026 );
buf ( n8889 , 1'b0 );
not ( n75029 , n68838 );
buf ( n75030 , n75029 );
buf ( n75031 , n68634 );
or ( n75032 , n74815 , n74867 );
nand ( n75033 , n74867 , n70045 );
nand ( n75034 , n75032 , n75033 );
buf ( n75035 , n75034 );
buf ( n75036 , 1'b0 );
not ( n75037 , n68838 );
buf ( n8899 , n75037 );
buf ( n75039 , n68634 );
or ( n75040 , n71207 , n74867 );
nand ( n75041 , n74867 , n69796 );
nand ( n75042 , n75040 , n75041 );
buf ( n8904 , n75042 );
buf ( n75044 , 1'b0 );
not ( n75045 , n68838 );
buf ( n75046 , n75045 );
buf ( n75047 , n68634 );
or ( n75048 , n71263 , n74867 );
nand ( n75049 , n74867 , n69815 );
nand ( n75050 , n75048 , n75049 );
buf ( n75051 , n75050 );
buf ( n75052 , 1'b0 );
not ( n75053 , n68838 );
buf ( n8915 , n75053 );
buf ( n75055 , n68634 );
or ( n75056 , n71319 , n74867 );
nand ( n75057 , n74867 , n69645 );
nand ( n75058 , n75056 , n75057 );
buf ( n75059 , n75058 );
buf ( n75060 , 1'b0 );
not ( n75061 , n68838 );
buf ( n75062 , n75061 );
buf ( n75063 , n68634 );
or ( n75064 , n71341 , n74867 );
nand ( n75065 , n74867 , n69630 );
nand ( n75066 , n75064 , n75065 );
buf ( n75067 , n75066 );
buf ( n75068 , 1'b0 );
not ( n75069 , n68838 );
buf ( n75070 , n75069 );
buf ( n75071 , n68634 );
or ( n75072 , n71435 , n74867 );
nand ( n75073 , n74867 , n69611 );
nand ( n75074 , n75072 , n75073 );
buf ( n75075 , n75074 );
buf ( n75076 , 1'b0 );
not ( n75077 , n68838 );
buf ( n8939 , n75077 );
buf ( n8940 , n68634 );
or ( n75080 , n71508 , n74867 );
nand ( n75081 , n74867 , n69597 );
nand ( n75082 , n75080 , n75081 );
buf ( n75083 , n75082 );
buf ( n8945 , 1'b0 );
not ( n75085 , n68838 );
buf ( n75086 , n75085 );
buf ( n75087 , n68634 );
or ( n75088 , n74836 , n74867 );
nand ( n75089 , n74867 , n69572 );
nand ( n75090 , n75088 , n75089 );
buf ( n75091 , n75090 );
buf ( n75092 , 1'b0 );
not ( n75093 , n68838 );
buf ( n8955 , n75093 );
buf ( n8956 , n68634 );
or ( n75096 , n71574 , n74867 );
nand ( n75097 , n74867 , n69585 );
nand ( n75098 , n75096 , n75097 );
buf ( n75099 , n75098 );
buf ( n8961 , 1'b0 );
not ( n75101 , n68838 );
buf ( n8963 , n75101 );
buf ( n8964 , n68634 );
or ( n75104 , n71654 , n74867 );
nand ( n75105 , n74867 , n69517 );
nand ( n75106 , n75104 , n75105 );
buf ( n75107 , n75106 );
buf ( n75108 , 1'b0 );
not ( n75109 , n68838 );
buf ( n75110 , n75109 );
buf ( n8972 , n68634 );
or ( n75112 , n71714 , n74867 );
nand ( n75113 , n74867 , n69529 );
nand ( n75114 , n75112 , n75113 );
buf ( n75115 , n75114 );
buf ( n8977 , 1'b0 );
not ( n75117 , n68838 );
buf ( n75118 , n75117 );
buf ( n75119 , n68634 );
or ( n75120 , n74856 , n74867 );
or ( n75121 , n74866 , n69962 );
nand ( n75122 , n75120 , n75121 );
buf ( n8984 , n75122 );
buf ( n75124 , 1'b0 );
not ( n75125 , n68838 );
buf ( n75126 , n75125 );
buf ( n8988 , n68634 );
and ( n75128 , n71843 , n2669 );
not ( n75129 , n71843 );
and ( n75130 , n75129 , n70082 );
or ( n75131 , n75128 , n75130 );
buf ( n75132 , n75131 );
buf ( n75133 , 1'b0 );
not ( n75134 , n68838 );
buf ( n75135 , n75134 );
buf ( n75136 , n68634 );
and ( n75137 , n71843 , n68810 );
not ( n75138 , n71843 );
and ( n75139 , n75138 , n70090 );
or ( n75140 , n75137 , n75139 );
buf ( n75141 , n75140 );
buf ( n75142 , 1'b0 );
not ( n75143 , n68838 );
buf ( n75144 , n75143 );
buf ( n75145 , n68634 );
and ( n75146 , n71843 , n2673 );
not ( n75147 , n71843 );
and ( n75148 , n75147 , n70031 );
or ( n75149 , n75146 , n75148 );
buf ( n75150 , n75149 );
buf ( n75151 , 1'b0 );
not ( n75152 , n68838 );
buf ( n9014 , n75152 );
buf ( n9015 , n68634 );
and ( n75155 , n71843 , n68814 );
not ( n75156 , n71843 );
and ( n75157 , n75156 , n70024 );
or ( n75158 , n75155 , n75157 );
buf ( n9020 , n75158 );
buf ( n75160 , 1'b0 );
not ( n75161 , n68838 );
buf ( n75162 , n75161 );
buf ( n9024 , n68634 );
and ( n75164 , n71725 , n68818 );
not ( n75165 , n71725 );
and ( n75166 , n75165 , n70038 );
or ( n75167 , n75164 , n75166 );
buf ( n9029 , n75167 );
buf ( n9030 , 1'b0 );
not ( n75170 , n68838 );
buf ( n75171 , n75170 );
buf ( n75172 , n68634 );
not ( n75173 , n71725 );
not ( n75174 , n75173 );
not ( n75175 , n70040 );
or ( n75176 , n75174 , n75175 );
nand ( n75177 , n71843 , n68823 );
nand ( n75178 , n75176 , n75177 );
buf ( n75179 , n75178 );
buf ( n75180 , 1'b0 );
not ( n75181 , n68838 );
buf ( n75182 , n75181 );
buf ( n75183 , n68634 );
and ( n75184 , n71725 , n68764 );
not ( n75185 , n71725 );
and ( n75186 , n75185 , n73902 );
or ( n75187 , n75184 , n75186 );
buf ( n75188 , n75187 );
buf ( n75189 , 1'b0 );
not ( n75190 , n68838 );
buf ( n9052 , n75190 );
buf ( n75192 , n68634 );
not ( n75193 , n70073 );
not ( n75194 , n71725 );
not ( n75195 , n75194 );
or ( n75196 , n75193 , n75195 );
not ( n75197 , n68826 );
or ( n75198 , n71842 , n75197 );
nand ( n75199 , n75196 , n75198 );
buf ( n75200 , n75199 );
buf ( n9062 , 1'b0 );
not ( n75202 , n68838 );
buf ( n75203 , n75202 );
buf ( n75204 , n68634 );
and ( n75205 , n71725 , n68766 );
not ( n75206 , n71725 );
and ( n75207 , n75206 , n72463 );
or ( n75208 , n75205 , n75207 );
buf ( n75209 , n75208 );
buf ( n75210 , 1'b0 );
not ( n75211 , n68838 );
buf ( n75212 , n75211 );
buf ( n75213 , n68634 );
and ( n75214 , n71725 , n2629 );
not ( n75215 , n71725 );
and ( n75216 , n75215 , n72452 );
or ( n75217 , n75214 , n75216 );
buf ( n75218 , n75217 );
buf ( n75219 , 1'b0 );
not ( n75220 , n68838 );
buf ( n9082 , n75220 );
buf ( n9083 , n68634 );
not ( n75223 , n70053 );
not ( n75224 , n75194 );
or ( n75225 , n75223 , n75224 );
not ( n75226 , n71725 );
not ( n75227 , n2689 );
or ( n75228 , n75226 , n75227 );
nand ( n75229 , n75225 , n75228 );
buf ( n9091 , n75229 );
buf ( n75231 , 1'b0 );
not ( n75232 , n68838 );
buf ( n75233 , n75232 );
buf ( n75234 , n68634 );
not ( n75235 , n69967 );
not ( n75236 , n71725 );
not ( n75237 , n75236 );
or ( n75238 , n75235 , n75237 );
not ( n75239 , n68830 );
or ( n75240 , n75226 , n75239 );
nand ( n75241 , n75238 , n75240 );
buf ( n75242 , n75241 );
buf ( n75243 , 1'b0 );
not ( n75244 , n68838 );
buf ( n75245 , n75244 );
buf ( n75246 , n68634 );
nor ( n75247 , n70861 , n70147 );
not ( n75248 , n75247 );
or ( n75249 , n75248 , n70181 );
or ( n75250 , n75247 , n70170 );
nand ( n75251 , n75249 , n75250 );
buf ( n75252 , n75251 );
buf ( n75253 , 1'b0 );
not ( n75254 , n68838 );
buf ( n75255 , n75254 );
buf ( n75256 , n68634 );
or ( n75257 , n75248 , n74865 );
not ( n75258 , n70161 );
or ( n75259 , n75247 , n75258 );
nand ( n75260 , n75257 , n75259 );
buf ( n75261 , n75260 );
buf ( n75262 , 1'b0 );
not ( n75263 , n68838 );
buf ( n9125 , n75263 );
buf ( n9126 , n68634 );
not ( n75266 , n70195 );
not ( n75267 , n70140 );
or ( n75268 , n75266 , n75267 );
nand ( n75269 , n70147 , n70139 );
nand ( n75270 , n75268 , n75269 );
not ( n75271 , n70217 );
and ( n75272 , n69358 , n75271 );
and ( n75273 , n75270 , n75272 );
nand ( n75274 , n75273 , n69123 );
and ( n75275 , n69357 , n75271 );
nand ( n75276 , n75270 , n75275 );
not ( n75277 , n75276 );
nor ( n75278 , n69123 , n69533 );
not ( n75279 , n75278 );
nand ( n75280 , n69123 , n69533 );
nand ( n75281 , n75279 , n75280 );
not ( n75282 , n75281 );
or ( n75283 , n3276 , n69059 );
not ( n75284 , n75283 );
not ( n75285 , n69010 );
not ( n75286 , n75285 );
nor ( n75287 , n75286 , n3320 );
nor ( n75288 , n75284 , n75287 );
not ( n75289 , n69025 );
not ( n75290 , n75289 );
nor ( n75291 , n75290 , n3350 );
nand ( n75292 , n69083 , n3346 );
or ( n75293 , n75291 , n75292 );
nand ( n75294 , n75290 , n3350 );
nand ( n75295 , n75293 , n75294 );
and ( n75296 , n75288 , n75295 );
nand ( n75297 , n69059 , n3276 );
or ( n75298 , n75287 , n75297 );
nand ( n75299 , n75286 , n3320 );
nand ( n75300 , n75298 , n75299 );
nor ( n75301 , n75296 , n75300 );
nor ( n75302 , n69083 , n3346 );
nor ( n75303 , n75291 , n75302 );
nor ( n75304 , n69072 , n69437 );
nand ( n75305 , n69095 , n70058 );
or ( n75306 , n75304 , n75305 );
nand ( n75307 , n69072 , n69437 );
nand ( n75308 , n75306 , n75307 );
or ( n75309 , n70058 , n69095 );
and ( n75310 , n3815 , n2728 );
xor ( n75311 , n70051 , n75310 );
and ( n75312 , n75311 , n69106 );
and ( n75313 , n70051 , n75310 );
or ( n75314 , n75312 , n75313 );
nand ( n75315 , n75309 , n75314 );
nor ( n75316 , n75304 , n75315 );
or ( n75317 , n75308 , n75316 );
nand ( n75318 , n75288 , n75303 , n75317 );
nand ( n75319 , n75301 , n75318 );
not ( n75320 , n75319 );
nor ( n75321 , n68988 , n3405 );
or ( n75322 , n75320 , n75321 );
nand ( n75323 , n68988 , n3405 );
nand ( n75324 , n75322 , n75323 );
not ( n75325 , n75324 );
or ( n75326 , n75282 , n75325 );
or ( n75327 , n75324 , n75281 );
nand ( n75328 , n75326 , n75327 );
nand ( n75329 , n75277 , n75328 );
not ( n75330 , n69357 );
nor ( n75331 , n75330 , n75271 );
and ( n75332 , n75270 , n75331 );
nor ( n75333 , n69123 , n69535 );
not ( n75334 , n75333 );
nand ( n75335 , n69123 , n69535 );
nand ( n75336 , n75334 , n75335 );
not ( n75337 , n75336 );
or ( n75338 , n3282 , n69059 );
not ( n75339 , n75338 );
not ( n75340 , n75285 );
nor ( n75341 , n75340 , n3316 );
nor ( n75342 , n75339 , n75341 );
not ( n75343 , n75289 );
nor ( n75344 , n75343 , n69492 );
nand ( n75345 , n69083 , n3342 );
or ( n75346 , n75344 , n75345 );
nand ( n75347 , n75343 , n69492 );
nand ( n75348 , n75346 , n75347 );
and ( n75349 , n75342 , n75348 );
nand ( n75350 , n69059 , n3282 );
or ( n75351 , n75341 , n75350 );
nand ( n75352 , n75340 , n3316 );
nand ( n75353 , n75351 , n75352 );
nor ( n75354 , n75349 , n75353 );
nor ( n75355 , n69083 , n3342 );
nor ( n75356 , n75344 , n75355 );
nor ( n75357 , n69072 , n3301 );
nand ( n75358 , n69095 , n70069 );
or ( n75359 , n75357 , n75358 );
nand ( n75360 , n69072 , n3301 );
nand ( n75361 , n75359 , n75360 );
or ( n75362 , n70069 , n69095 );
and ( n75363 , n69957 , n2728 );
xor ( n75364 , n70049 , n75363 );
and ( n75365 , n75364 , n69106 );
and ( n75366 , n70049 , n75363 );
or ( n75367 , n75365 , n75366 );
nand ( n75368 , n75362 , n75367 );
nor ( n75369 , n75357 , n75368 );
or ( n75370 , n75361 , n75369 );
nand ( n75371 , n75342 , n75356 , n75370 );
nand ( n75372 , n75354 , n75371 );
not ( n75373 , n75372 );
nor ( n75374 , n68988 , n69546 );
or ( n75375 , n75373 , n75374 );
nand ( n75376 , n68988 , n69546 );
nand ( n75377 , n75375 , n75376 );
not ( n75378 , n75377 );
or ( n75379 , n75337 , n75378 );
or ( n75380 , n75377 , n75336 );
nand ( n75381 , n75379 , n75380 );
nand ( n75382 , n75332 , n75381 );
nor ( n75383 , n70136 , n70147 );
not ( n75384 , n70195 );
and ( n75385 , n75384 , n70863 );
nor ( n75386 , n69357 , n75271 );
nor ( n75387 , n75385 , n75386 );
or ( n75388 , n75383 , n75387 , n71992 );
not ( n75389 , n75388 );
and ( n75390 , n75389 , n68720 );
not ( n75391 , n72020 );
nor ( n75392 , n75390 , n75391 );
nand ( n75393 , n75274 , n75329 , n75382 , n75392 );
buf ( n75394 , n75393 );
buf ( n9256 , 1'b0 );
not ( n75396 , n68838 );
buf ( n9258 , n75396 );
buf ( n9259 , n68634 );
nand ( n75399 , n75273 , n68988 );
not ( n75400 , n75321 );
nand ( n75401 , n75400 , n75323 );
not ( n75402 , n75401 );
not ( n75403 , n75319 );
or ( n75404 , n75402 , n75403 );
or ( n75405 , n75319 , n75401 );
nand ( n75406 , n75404 , n75405 );
nand ( n75407 , n75277 , n75406 );
not ( n75408 , n75374 );
nand ( n75409 , n75408 , n75376 );
not ( n75410 , n75409 );
not ( n75411 , n75372 );
or ( n75412 , n75410 , n75411 );
or ( n75413 , n75372 , n75409 );
nand ( n75414 , n75412 , n75413 );
nand ( n75415 , n75332 , n75414 );
and ( n75416 , n75389 , n68725 );
nor ( n75417 , n75416 , n72072 );
nand ( n75418 , n75399 , n75407 , n75415 , n75417 );
buf ( n75419 , n75418 );
buf ( n75420 , 1'b0 );
not ( n75421 , n68838 );
buf ( n9283 , n75421 );
buf ( n9284 , n68634 );
nand ( n75424 , n75273 , n69010 );
not ( n75425 , n75299 );
nor ( n75426 , n75425 , n75287 );
not ( n75427 , n75426 );
and ( n75428 , n75303 , n75317 , n75283 );
not ( n75429 , n75283 );
not ( n75430 , n75295 );
or ( n75431 , n75429 , n75430 );
nand ( n75432 , n75431 , n75297 );
nor ( n75433 , n75428 , n75432 );
not ( n75434 , n75433 );
or ( n75435 , n75427 , n75434 );
or ( n75436 , n75433 , n75426 );
nand ( n75437 , n75435 , n75436 );
nand ( n75438 , n75277 , n75437 );
not ( n75439 , n75352 );
nor ( n75440 , n75439 , n75341 );
not ( n75441 , n75440 );
and ( n75442 , n75356 , n75370 , n75338 );
not ( n75443 , n75338 );
not ( n75444 , n75348 );
or ( n75445 , n75443 , n75444 );
nand ( n75446 , n75445 , n75350 );
nor ( n75447 , n75442 , n75446 );
not ( n75448 , n75447 );
or ( n75449 , n75441 , n75448 );
or ( n75450 , n75447 , n75440 );
nand ( n75451 , n75449 , n75450 );
nand ( n75452 , n75332 , n75451 );
and ( n75453 , n75389 , n68730 );
nor ( n75454 , n75453 , n72138 );
nand ( n75455 , n75424 , n75438 , n75452 , n75454 );
buf ( n9317 , n75455 );
buf ( n9318 , 1'b0 );
not ( n75458 , n68838 );
buf ( n75459 , n75458 );
buf ( n75460 , n68634 );
nand ( n75461 , n75273 , n69059 );
and ( n75462 , n75283 , n75297 );
not ( n75463 , n75462 );
and ( n75464 , n75303 , n75317 );
nor ( n75465 , n75464 , n75295 );
not ( n75466 , n75465 );
or ( n75467 , n75463 , n75466 );
or ( n75468 , n75465 , n75462 );
nand ( n75469 , n75467 , n75468 );
nand ( n75470 , n75277 , n75469 );
and ( n75471 , n75338 , n75350 );
not ( n75472 , n75471 );
and ( n75473 , n75356 , n75370 );
nor ( n75474 , n75473 , n75348 );
not ( n75475 , n75474 );
or ( n75476 , n75472 , n75475 );
or ( n75477 , n75474 , n75471 );
nand ( n75478 , n75476 , n75477 );
nand ( n75479 , n75332 , n75478 );
and ( n75480 , n75389 , n68735 );
nor ( n75481 , n75480 , n72200 );
nand ( n75482 , n75461 , n75470 , n75479 , n75481 );
buf ( n75483 , n75482 );
buf ( n75484 , 1'b0 );
not ( n75485 , n68838 );
buf ( n75486 , n75485 );
buf ( n75487 , n68634 );
nand ( n75488 , n75273 , n69025 );
not ( n75489 , n75291 );
nand ( n75490 , n75489 , n75294 );
not ( n75491 , n75490 );
not ( n75492 , n75317 );
or ( n75493 , n75492 , n75302 );
nand ( n75494 , n75493 , n75292 );
not ( n75495 , n75494 );
or ( n75496 , n75491 , n75495 );
or ( n75497 , n75494 , n75490 );
nand ( n75498 , n75496 , n75497 );
nand ( n75499 , n75277 , n75498 );
not ( n75500 , n75344 );
nand ( n75501 , n75500 , n75347 );
not ( n75502 , n75501 );
not ( n75503 , n75370 );
or ( n75504 , n75503 , n75355 );
nand ( n75505 , n75504 , n75345 );
not ( n75506 , n75505 );
or ( n75507 , n75502 , n75506 );
or ( n75508 , n75505 , n75501 );
nand ( n75509 , n75507 , n75508 );
nand ( n75510 , n75332 , n75509 );
and ( n75511 , n75389 , n68740 );
nor ( n75512 , n75511 , n72262 );
nand ( n75513 , n75488 , n75499 , n75510 , n75512 );
buf ( n75514 , n75513 );
buf ( n75515 , 1'b0 );
not ( n75516 , n68838 );
buf ( n75517 , n75516 );
buf ( n75518 , n68634 );
nand ( n75519 , n75273 , n69083 );
not ( n75520 , n75292 );
nor ( n75521 , n75520 , n75302 );
not ( n75522 , n75521 );
not ( n75523 , n75492 );
or ( n75524 , n75522 , n75523 );
or ( n75525 , n75492 , n75521 );
nand ( n75526 , n75524 , n75525 );
nand ( n75527 , n75277 , n75526 );
not ( n75528 , n75345 );
nor ( n75529 , n75528 , n75355 );
not ( n75530 , n75529 );
not ( n75531 , n75503 );
or ( n75532 , n75530 , n75531 );
or ( n75533 , n75503 , n75529 );
nand ( n75534 , n75532 , n75533 );
nand ( n75535 , n75332 , n75534 );
not ( n75536 , n75388 );
not ( n75537 , n2604 );
not ( n75538 , n75537 );
and ( n75539 , n75536 , n75538 );
not ( n75540 , n3815 );
not ( n75541 , n75275 );
or ( n75542 , n75540 , n75541 );
nand ( n75543 , n75331 , n69957 );
nand ( n75544 , n75542 , n75543 );
xnor ( n75545 , n75544 , n2728 );
or ( n75546 , n71725 , n75545 );
nand ( n75547 , n75546 , n72311 );
nor ( n75548 , n75539 , n75547 );
nand ( n75549 , n75519 , n75527 , n75535 , n75548 );
buf ( n75550 , n75549 );
buf ( n75551 , 1'b0 );
not ( n75552 , n68838 );
buf ( n75553 , n75552 );
buf ( n9415 , n68634 );
nand ( n75555 , n75273 , n69072 );
nand ( n75556 , n75315 , n75305 );
not ( n75557 , n75556 );
not ( n75558 , n75304 );
nand ( n75559 , n75558 , n75307 );
not ( n75560 , n75559 );
or ( n75561 , n75557 , n75560 );
or ( n75562 , n75559 , n75556 );
nand ( n75563 , n75561 , n75562 );
nand ( n75564 , n75277 , n75563 );
nand ( n75565 , n75368 , n75358 );
not ( n75566 , n75565 );
not ( n75567 , n75357 );
nand ( n75568 , n75567 , n75360 );
not ( n75569 , n75568 );
or ( n75570 , n75566 , n75569 );
or ( n75571 , n75568 , n75565 );
nand ( n75572 , n75570 , n75571 );
nand ( n75573 , n75332 , n75572 );
and ( n75574 , n75389 , n68747 );
nor ( n75575 , n75574 , n72368 );
nand ( n75576 , n75555 , n75564 , n75573 , n75575 );
buf ( n75577 , n75576 );
buf ( n75578 , 1'b0 );
not ( n75579 , n68838 );
buf ( n75580 , n75579 );
buf ( n75581 , n68634 );
not ( n75582 , n75314 );
nand ( n75583 , n75305 , n75309 );
not ( n75584 , n75583 );
or ( n75585 , n75582 , n75584 );
or ( n75586 , n75583 , n75314 );
nand ( n75587 , n75585 , n75586 );
nand ( n75588 , n75277 , n75587 );
nand ( n75589 , n75273 , n69095 );
not ( n75590 , n75367 );
nand ( n75591 , n75358 , n75362 );
not ( n75592 , n75591 );
or ( n75593 , n75590 , n75592 );
or ( n75594 , n75591 , n75367 );
nand ( n75595 , n75593 , n75594 );
nand ( n75596 , n75332 , n75595 );
not ( n75597 , n75388 );
not ( n75598 , n68750 );
not ( n75599 , n75598 );
and ( n75600 , n75597 , n75599 );
not ( n75601 , n70859 );
not ( n75602 , n3915 );
or ( n75603 , n75601 , n75602 );
nand ( n75604 , n75603 , n75546 );
nor ( n75605 , n75600 , n75604 );
nand ( n75606 , n75588 , n75589 , n75596 , n75605 );
buf ( n75607 , n75606 );
buf ( n75608 , 1'b0 );
not ( n75609 , n68838 );
buf ( n75610 , n75609 );
buf ( n75611 , n68634 );
nand ( n75612 , n75273 , n69106 );
xor ( n75613 , n70051 , n75310 );
xor ( n75614 , n75613 , n69106 );
nand ( n75615 , n75277 , n75614 );
xor ( n75616 , n70049 , n75363 );
xor ( n75617 , n75616 , n69106 );
nand ( n75618 , n75332 , n75617 );
and ( n75619 , n75389 , n68754 );
and ( n75620 , n70041 , n70859 );
nor ( n75621 , n75619 , n75620 );
nand ( n75622 , n75612 , n75615 , n75618 , n75621 );
buf ( n75623 , n75622 );
buf ( n75624 , 1'b0 );
not ( n75625 , n68838 );
buf ( n9487 , n75625 );
buf ( n9488 , n68634 );
nand ( n75628 , n75273 , n69240 );
not ( n75629 , n69240 );
not ( n75630 , n69798 );
and ( n75631 , n75629 , n75630 );
and ( n75632 , n69240 , n69798 );
nor ( n75633 , n75631 , n75632 );
not ( n75634 , n75633 );
or ( n75635 , n69045 , n69522 );
not ( n75636 , n75635 );
nor ( n75637 , n68977 , n69507 );
nor ( n75638 , n75636 , n75637 );
or ( n75639 , n75278 , n75323 );
nand ( n75640 , n75639 , n75280 );
and ( n75641 , n75638 , n75640 );
nand ( n75642 , n69045 , n69522 );
or ( n75643 , n75637 , n75642 );
nand ( n75644 , n68977 , n69507 );
nand ( n75645 , n75643 , n75644 );
nor ( n75646 , n75641 , n75645 );
nor ( n75647 , n75278 , n75321 );
and ( n75648 , n75638 , n75647 );
nand ( n75649 , n75648 , n75319 );
nand ( n75650 , n75646 , n75649 );
nor ( n75651 , n68934 , n3466 );
nor ( n75652 , n68961 , n3450 );
nor ( n75653 , n75651 , n75652 );
nor ( n75654 , n68947 , n69558 );
nor ( n75655 , n68908 , n69577 );
nor ( n75656 , n75654 , n75655 );
nand ( n75657 , n75653 , n75656 );
not ( n75658 , n75657 );
nor ( n75659 , n69157 , n69806 );
not ( n75660 , n75659 );
nor ( n75661 , n69176 , n69651 );
nor ( n75662 , n69187 , n2697 );
nor ( n75663 , n75661 , n75662 );
nand ( n75664 , n75660 , n75663 );
not ( n75665 , n75664 );
and ( n75666 , n75650 , n75658 , n75665 );
nand ( n75667 , n68908 , n69577 );
or ( n75668 , n75654 , n75667 );
nand ( n75669 , n68947 , n69558 );
nand ( n75670 , n75668 , n75669 );
and ( n75671 , n75653 , n75670 );
nand ( n75672 , n68961 , n3450 );
or ( n75673 , n75651 , n75672 );
nand ( n75674 , n68934 , n3466 );
nand ( n75675 , n75673 , n75674 );
nor ( n75676 , n75671 , n75675 );
or ( n75677 , n75676 , n75664 );
nand ( n75678 , n69187 , n2697 );
or ( n75679 , n75661 , n75678 );
nand ( n75680 , n69176 , n69651 );
nand ( n75681 , n75679 , n75680 );
not ( n75682 , n75681 );
or ( n75683 , n75659 , n75682 );
nand ( n75684 , n69157 , n69806 );
nand ( n75685 , n75677 , n75683 , n75684 );
nor ( n75686 , n75666 , n75685 );
not ( n75687 , n75686 );
or ( n75688 , n75634 , n75687 );
or ( n75689 , n75686 , n75633 );
nand ( n75690 , n75688 , n75689 );
nand ( n75691 , n75277 , n75690 );
not ( n75692 , n69240 );
not ( n75693 , n69800 );
and ( n75694 , n75692 , n75693 );
and ( n75695 , n69240 , n69800 );
nor ( n75696 , n75694 , n75695 );
not ( n75697 , n75696 );
or ( n75698 , n69045 , n69524 );
not ( n75699 , n75698 );
nor ( n75700 , n68977 , n69509 );
nor ( n75701 , n75699 , n75700 );
or ( n75702 , n75333 , n75376 );
nand ( n75703 , n75702 , n75335 );
and ( n75704 , n75701 , n75703 );
nand ( n75705 , n69045 , n69524 );
or ( n75706 , n75700 , n75705 );
nand ( n75707 , n68977 , n69509 );
nand ( n75708 , n75706 , n75707 );
nor ( n75709 , n75704 , n75708 );
nor ( n75710 , n75333 , n75374 );
and ( n75711 , n75701 , n75710 );
nand ( n75712 , n75711 , n75372 );
nand ( n75713 , n75709 , n75712 );
nor ( n75714 , n68934 , n69607 );
nor ( n75715 , n68961 , n69591 );
nor ( n75716 , n75714 , n75715 );
nor ( n75717 , n68947 , n69562 );
nor ( n75718 , n68908 , n69579 );
nor ( n75719 , n75717 , n75718 );
nand ( n75720 , n75716 , n75719 );
not ( n75721 , n75720 );
nor ( n75722 , n69157 , n69810 );
not ( n75723 , n75722 );
nor ( n75724 , n69176 , n3510 );
nor ( n75725 , n69187 , n3498 );
nor ( n75726 , n75724 , n75725 );
nand ( n75727 , n75723 , n75726 );
not ( n75728 , n75727 );
and ( n75729 , n75713 , n75721 , n75728 );
nand ( n75730 , n68908 , n69579 );
or ( n75731 , n75717 , n75730 );
nand ( n75732 , n68947 , n69562 );
nand ( n75733 , n75731 , n75732 );
and ( n75734 , n75716 , n75733 );
nand ( n75735 , n68961 , n69591 );
or ( n75736 , n75714 , n75735 );
nand ( n75737 , n68934 , n69607 );
nand ( n75738 , n75736 , n75737 );
nor ( n75739 , n75734 , n75738 );
or ( n75740 , n75739 , n75727 );
nand ( n75741 , n69187 , n3498 );
or ( n75742 , n75724 , n75741 );
nand ( n75743 , n69176 , n3510 );
nand ( n75744 , n75742 , n75743 );
not ( n75745 , n75744 );
or ( n75746 , n75722 , n75745 );
nand ( n75747 , n69157 , n69810 );
nand ( n75748 , n75740 , n75746 , n75747 );
nor ( n75749 , n75729 , n75748 );
not ( n75750 , n75749 );
or ( n75751 , n75697 , n75750 );
or ( n75752 , n75749 , n75696 );
nand ( n75753 , n75751 , n75752 );
nand ( n75754 , n75332 , n75753 );
and ( n75755 , n75389 , n68670 );
nor ( n75756 , n75755 , n73456 );
nand ( n75757 , n75628 , n75691 , n75754 , n75756 );
buf ( n9619 , n75757 );
buf ( n9620 , 1'b0 );
not ( n75760 , n68838 );
buf ( n9622 , n75760 );
buf ( n9623 , n68634 );
nand ( n75763 , n75273 , n69157 );
not ( n75764 , n75684 );
nor ( n75765 , n75764 , n75659 );
not ( n75766 , n75765 );
and ( n75767 , n75650 , n75658 , n75663 );
not ( n75768 , n75681 );
not ( n75769 , n75676 );
nand ( n75770 , n75769 , n75663 );
nand ( n75771 , n75768 , n75770 );
nor ( n75772 , n75767 , n75771 );
not ( n75773 , n75772 );
or ( n75774 , n75766 , n75773 );
or ( n75775 , n75772 , n75765 );
nand ( n75776 , n75774 , n75775 );
nand ( n75777 , n75277 , n75776 );
not ( n75778 , n75747 );
nor ( n75779 , n75778 , n75722 );
not ( n75780 , n75779 );
and ( n75781 , n75713 , n75721 , n75726 );
not ( n75782 , n75744 );
not ( n75783 , n75739 );
nand ( n75784 , n75783 , n75726 );
nand ( n75785 , n75782 , n75784 );
nor ( n75786 , n75781 , n75785 );
not ( n75787 , n75786 );
or ( n75788 , n75780 , n75787 );
or ( n75789 , n75786 , n75779 );
nand ( n75790 , n75788 , n75789 );
nand ( n75791 , n75332 , n75790 );
and ( n75792 , n75389 , n68675 );
nor ( n75793 , n75792 , n73478 );
nand ( n75794 , n75763 , n75777 , n75791 , n75793 );
buf ( n9656 , n75794 );
buf ( n75796 , 1'b0 );
not ( n75797 , n68838 );
buf ( n75798 , n75797 );
buf ( n75799 , n68634 );
nand ( n75800 , n75273 , n69176 );
not ( n75801 , n75661 );
nand ( n75802 , n75801 , n75680 );
not ( n75803 , n75802 );
or ( n75804 , n75676 , n75662 );
not ( n75805 , n75662 );
nand ( n75806 , n75805 , n75650 , n75658 );
nand ( n75807 , n75804 , n75806 , n75678 );
not ( n75808 , n75807 );
or ( n75809 , n75803 , n75808 );
or ( n75810 , n75807 , n75802 );
nand ( n75811 , n75809 , n75810 );
nand ( n75812 , n75277 , n75811 );
not ( n75813 , n75724 );
nand ( n75814 , n75813 , n75743 );
not ( n75815 , n75814 );
or ( n75816 , n75739 , n75725 );
not ( n75817 , n75725 );
nand ( n75818 , n75817 , n75713 , n75721 );
nand ( n75819 , n75816 , n75818 , n75741 );
not ( n75820 , n75819 );
or ( n75821 , n75815 , n75820 );
or ( n75822 , n75819 , n75814 );
nand ( n75823 , n75821 , n75822 );
nand ( n75824 , n75332 , n75823 );
and ( n75825 , n75389 , n68680 );
nor ( n75826 , n75825 , n73500 );
nand ( n75827 , n75800 , n75812 , n75824 , n75826 );
buf ( n9689 , n75827 );
buf ( n75829 , 1'b0 );
not ( n75830 , n68838 );
buf ( n75831 , n75830 );
buf ( n75832 , n68634 );
nand ( n75833 , n75273 , n69187 );
not ( n75834 , n75662 );
nand ( n75835 , n75834 , n75678 );
not ( n75836 , n75835 );
or ( n75837 , n75649 , n75657 );
or ( n75838 , n75657 , n75646 );
nand ( n75839 , n75837 , n75838 , n75676 );
not ( n75840 , n75839 );
or ( n75841 , n75836 , n75840 );
or ( n75842 , n75839 , n75835 );
nand ( n75843 , n75841 , n75842 );
nand ( n75844 , n75277 , n75843 );
not ( n75845 , n75725 );
nand ( n75846 , n75845 , n75741 );
not ( n75847 , n75846 );
or ( n75848 , n75712 , n75720 );
or ( n75849 , n75720 , n75709 );
nand ( n75850 , n75848 , n75849 , n75739 );
not ( n75851 , n75850 );
or ( n75852 , n75847 , n75851 );
or ( n75853 , n75850 , n75846 );
nand ( n75854 , n75852 , n75853 );
nand ( n75855 , n75332 , n75854 );
and ( n75856 , n75389 , n68685 );
nor ( n75857 , n75856 , n73521 );
nand ( n75858 , n75833 , n75844 , n75855 , n75857 );
buf ( n9720 , n75858 );
buf ( n9721 , 1'b0 );
not ( n75861 , n68838 );
buf ( n75862 , n75861 );
buf ( n75863 , n68634 );
nand ( n75864 , n75273 , n68934 );
not ( n75865 , n75674 );
nor ( n75866 , n75865 , n75651 );
not ( n75867 , n75866 );
not ( n75868 , n75652 );
and ( n75869 , n75656 , n75868 );
and ( n75870 , n75648 , n75869 , n75319 );
not ( n75871 , n75869 );
not ( n75872 , n75646 );
not ( n75873 , n75872 );
or ( n75874 , n75871 , n75873 );
and ( n75875 , n75670 , n75868 );
not ( n75876 , n75672 );
nor ( n75877 , n75875 , n75876 );
nand ( n75878 , n75874 , n75877 );
nor ( n75879 , n75870 , n75878 );
not ( n75880 , n75879 );
or ( n75881 , n75867 , n75880 );
or ( n75882 , n75879 , n75866 );
nand ( n75883 , n75881 , n75882 );
nand ( n75884 , n75277 , n75883 );
not ( n75885 , n75737 );
nor ( n75886 , n75885 , n75714 );
not ( n75887 , n75886 );
not ( n75888 , n75715 );
and ( n75889 , n75719 , n75888 );
and ( n75890 , n75711 , n75889 , n75372 );
not ( n75891 , n75889 );
not ( n75892 , n75709 );
not ( n75893 , n75892 );
or ( n75894 , n75891 , n75893 );
and ( n75895 , n75733 , n75888 );
not ( n75896 , n75735 );
nor ( n75897 , n75895 , n75896 );
nand ( n75898 , n75894 , n75897 );
nor ( n75899 , n75890 , n75898 );
not ( n75900 , n75899 );
or ( n75901 , n75887 , n75900 );
or ( n75902 , n75899 , n75886 );
nand ( n75903 , n75901 , n75902 );
nand ( n75904 , n75332 , n75903 );
and ( n75905 , n75389 , n68690 );
not ( n75906 , n73547 );
nor ( n75907 , n75905 , n75906 );
nand ( n75908 , n75864 , n75884 , n75904 , n75907 );
buf ( n75909 , n75908 );
buf ( n75910 , 1'b0 );
not ( n75911 , n68838 );
buf ( n75912 , n75911 );
buf ( n75913 , n68634 );
nand ( n75914 , n75273 , n68961 );
and ( n75915 , n75868 , n75672 );
not ( n75916 , n75915 );
and ( n75917 , n75872 , n75656 );
and ( n75918 , n75648 , n75319 , n75656 );
nor ( n75919 , n75917 , n75918 , n75670 );
not ( n75920 , n75919 );
or ( n75921 , n75916 , n75920 );
or ( n75922 , n75919 , n75915 );
nand ( n75923 , n75921 , n75922 );
nand ( n75924 , n75277 , n75923 );
and ( n75925 , n75888 , n75735 );
not ( n75926 , n75925 );
and ( n75927 , n75892 , n75719 );
and ( n75928 , n75711 , n75372 , n75719 );
nor ( n75929 , n75927 , n75928 , n75733 );
not ( n75930 , n75929 );
or ( n75931 , n75926 , n75930 );
or ( n75932 , n75929 , n75925 );
nand ( n75933 , n75931 , n75932 );
nand ( n75934 , n75332 , n75933 );
and ( n75935 , n75389 , n68695 );
not ( n75936 , n73571 );
nor ( n75937 , n75935 , n75936 );
nand ( n75938 , n75914 , n75924 , n75934 , n75937 );
buf ( n75939 , n75938 );
buf ( n75940 , 1'b0 );
not ( n75941 , n68838 );
buf ( n75942 , n75941 );
buf ( n75943 , n68634 );
nand ( n75944 , n75273 , n68947 );
not ( n75945 , n75654 );
nand ( n75946 , n75945 , n75669 );
not ( n75947 , n75946 );
or ( n75948 , n75646 , n75655 );
not ( n75949 , n75655 );
nand ( n75950 , n75949 , n75648 , n75319 );
nand ( n75951 , n75948 , n75950 , n75667 );
not ( n75952 , n75951 );
or ( n75953 , n75947 , n75952 );
or ( n75954 , n75951 , n75946 );
nand ( n75955 , n75953 , n75954 );
nand ( n75956 , n75277 , n75955 );
not ( n75957 , n75717 );
nand ( n75958 , n75957 , n75732 );
not ( n75959 , n75958 );
or ( n75960 , n75709 , n75718 );
not ( n75961 , n75718 );
nand ( n75962 , n75961 , n75711 , n75372 );
nand ( n75963 , n75960 , n75962 , n75730 );
not ( n75964 , n75963 );
or ( n75965 , n75959 , n75964 );
or ( n75966 , n75963 , n75958 );
nand ( n75967 , n75965 , n75966 );
nand ( n75968 , n75332 , n75967 );
and ( n75969 , n75389 , n68700 );
not ( n75970 , n73645 );
nor ( n75971 , n75969 , n75970 );
nand ( n75972 , n75944 , n75956 , n75968 , n75971 );
buf ( n75973 , n75972 );
buf ( n75974 , 1'b0 );
not ( n75975 , n68838 );
buf ( n75976 , n75975 );
buf ( n75977 , n68634 );
nand ( n75978 , n75273 , n68908 );
not ( n75979 , n75655 );
nand ( n75980 , n75979 , n75667 );
not ( n75981 , n75980 );
not ( n75982 , n75650 );
or ( n75983 , n75981 , n75982 );
or ( n75984 , n75650 , n75980 );
nand ( n75985 , n75983 , n75984 );
nand ( n75986 , n75277 , n75985 );
not ( n75987 , n75718 );
nand ( n75988 , n75987 , n75730 );
not ( n75989 , n75988 );
not ( n75990 , n75713 );
or ( n75991 , n75989 , n75990 );
or ( n75992 , n75713 , n75988 );
nand ( n75993 , n75991 , n75992 );
nand ( n75994 , n75332 , n75993 );
and ( n75995 , n75389 , n68705 );
not ( n75996 , n73670 );
nor ( n75997 , n75995 , n75996 );
nand ( n75998 , n75978 , n75986 , n75994 , n75997 );
buf ( n75999 , n75998 );
buf ( n76000 , 1'b0 );
not ( n76001 , n68838 );
buf ( n76002 , n76001 );
buf ( n76003 , n68634 );
nand ( n76004 , n75273 , n68977 );
not ( n76005 , n75644 );
nor ( n76006 , n76005 , n75637 );
not ( n76007 , n76006 );
and ( n76008 , n75319 , n75647 , n75635 );
not ( n76009 , n75635 );
not ( n76010 , n75640 );
or ( n76011 , n76009 , n76010 );
nand ( n76012 , n76011 , n75642 );
nor ( n76013 , n76008 , n76012 );
not ( n76014 , n76013 );
or ( n76015 , n76007 , n76014 );
or ( n76016 , n76013 , n76006 );
nand ( n76017 , n76015 , n76016 );
nand ( n76018 , n75277 , n76017 );
not ( n76019 , n75707 );
nor ( n76020 , n76019 , n75700 );
not ( n76021 , n76020 );
and ( n76022 , n75372 , n75710 , n75698 );
not ( n76023 , n75698 );
not ( n76024 , n75703 );
or ( n76025 , n76023 , n76024 );
nand ( n76026 , n76025 , n75705 );
nor ( n76027 , n76022 , n76026 );
not ( n76028 , n76027 );
or ( n76029 , n76021 , n76028 );
or ( n76030 , n76027 , n76020 );
nand ( n76031 , n76029 , n76030 );
nand ( n76032 , n75332 , n76031 );
and ( n76033 , n75389 , n68710 );
not ( n76034 , n73694 );
nor ( n76035 , n76033 , n76034 );
nand ( n76036 , n76004 , n76018 , n76032 , n76035 );
buf ( n76037 , n76036 );
buf ( n76038 , 1'b0 );
not ( n76039 , n68838 );
buf ( n76040 , n76039 );
buf ( n76041 , n68634 );
nand ( n76042 , n75273 , n69045 );
and ( n76043 , n75635 , n75642 );
not ( n76044 , n76043 );
and ( n76045 , n75319 , n75647 );
nor ( n76046 , n76045 , n75640 );
not ( n76047 , n76046 );
or ( n76048 , n76044 , n76047 );
or ( n76049 , n76046 , n76043 );
nand ( n76050 , n76048 , n76049 );
nand ( n76051 , n75277 , n76050 );
and ( n76052 , n75698 , n75705 );
not ( n76053 , n76052 );
and ( n76054 , n75372 , n75710 );
nor ( n76055 , n76054 , n75703 );
not ( n76056 , n76055 );
or ( n76057 , n76053 , n76056 );
or ( n76058 , n76055 , n76052 );
nand ( n76059 , n76057 , n76058 );
nand ( n76060 , n75332 , n76059 );
and ( n76061 , n75389 , n68715 );
not ( n76062 , n73719 );
nor ( n76063 , n76061 , n76062 );
nand ( n76064 , n76042 , n76051 , n76060 , n76063 );
buf ( n76065 , n76064 );
buf ( n76066 , 1'b0 );
not ( n76067 , n68838 );
buf ( n76068 , n76067 );
buf ( n76069 , n68634 );
nand ( n76070 , n75273 , n2728 );
xor ( n76071 , n3815 , n2728 );
nand ( n76072 , n75277 , n76071 );
xor ( n76073 , n69957 , n2728 );
nand ( n76074 , n75332 , n76073 );
and ( n76075 , n75389 , n68759 );
and ( n76076 , n69950 , n70859 );
nor ( n76077 , n76075 , n76076 );
nand ( n76078 , n76070 , n76072 , n76074 , n76077 );
buf ( n76079 , n76078 );
buf ( n76080 , 1'b0 );
not ( n76081 , n68838 );
buf ( n9943 , n76081 );
buf ( n9944 , n68634 );
not ( n76084 , n69123 );
or ( n76085 , n71992 , n76084 );
nand ( n76086 , n70859 , n2519 );
nand ( n76087 , n76085 , n76086 );
buf ( n9949 , n76087 );
buf ( n9950 , 1'b0 );
not ( n76090 , n68838 );
buf ( n9952 , n76090 );
buf ( n9953 , n68634 );
not ( n76093 , n68988 );
or ( n76094 , n71992 , n76093 );
not ( n76095 , n68659 );
or ( n76096 , n72071 , n76095 );
nand ( n76097 , n76094 , n76096 );
buf ( n76098 , n76097 );
buf ( n76099 , 1'b0 );
not ( n76100 , n68838 );
buf ( n76101 , n76100 );
buf ( n76102 , n68634 );
not ( n76103 , n69010 );
not ( n76104 , n70139 );
or ( n76105 , n76103 , n76104 );
nand ( n76106 , n70859 , n68660 );
nand ( n76107 , n76105 , n76106 );
buf ( n76108 , n76107 );
buf ( n76109 , 1'b0 );
not ( n76110 , n68838 );
buf ( n76111 , n76110 );
buf ( n76112 , n68634 );
not ( n76113 , n69059 );
not ( n76114 , n70139 );
or ( n76115 , n76113 , n76114 );
nand ( n76116 , n70859 , n68661 );
nand ( n76117 , n76115 , n76116 );
buf ( n76118 , n76117 );
buf ( n76119 , 1'b0 );
not ( n76120 , n68838 );
buf ( n9982 , n76120 );
buf ( n9983 , n68634 );
not ( n76123 , n69025 );
not ( n76124 , n70139 );
or ( n76125 , n76123 , n76124 );
nand ( n76126 , n70859 , n2523 );
nand ( n76127 , n76125 , n76126 );
buf ( n76128 , n76127 );
buf ( n76129 , 1'b0 );
not ( n76130 , n68838 );
buf ( n76131 , n76130 );
buf ( n76132 , n68634 );
not ( n76133 , n69083 );
not ( n76134 , n70139 );
or ( n76135 , n76133 , n76134 );
nand ( n76136 , n70859 , n2524 );
nand ( n76137 , n76135 , n76136 );
buf ( n76138 , n76137 );
buf ( n76139 , 1'b0 );
not ( n76140 , n68838 );
buf ( n76141 , n76140 );
buf ( n76142 , n68634 );
not ( n76143 , n69072 );
not ( n76144 , n70139 );
or ( n76145 , n76143 , n76144 );
nand ( n76146 , n70859 , n68664 );
nand ( n76147 , n76145 , n76146 );
buf ( n10009 , n76147 );
buf ( n10010 , 1'b0 );
not ( n76150 , n68838 );
buf ( n76151 , n76150 );
buf ( n76152 , n68634 );
not ( n76153 , n69230 );
or ( n76154 , n71992 , n76153 );
nand ( n76155 , n70859 , n68636 );
nand ( n76156 , n76154 , n76155 );
buf ( n10018 , n76156 );
buf ( n10019 , 1'b0 );
not ( n76159 , n68838 );
buf ( n76160 , n76159 );
buf ( n76161 , n68634 );
not ( n76162 , n69400 );
or ( n76163 , n76162 , n71992 );
nand ( n76164 , n70859 , n2498 );
nand ( n76165 , n76163 , n76164 );
buf ( n76166 , n76165 );
buf ( n76167 , 1'b0 );
not ( n76168 , n68838 );
buf ( n76169 , n76168 );
buf ( n76170 , n68634 );
not ( n76171 , n69095 );
not ( n76172 , n70139 );
or ( n76173 , n76171 , n76172 );
nand ( n76174 , n70859 , n68665 );
nand ( n76175 , n76173 , n76174 );
buf ( n76176 , n76175 );
buf ( n76177 , 1'b0 );
not ( n76178 , n68838 );
buf ( n76179 , n76178 );
buf ( n76180 , n68634 );
not ( n76181 , n69409 );
or ( n76182 , n71992 , n76181 );
nand ( n76183 , n70859 , n2499 );
nand ( n76184 , n76182 , n76183 );
buf ( n76185 , n76184 );
buf ( n76186 , 1'b0 );
not ( n76187 , n68838 );
buf ( n10049 , n76187 );
buf ( n10050 , n68634 );
not ( n76190 , n69352 );
or ( n76191 , n71992 , n76190 );
not ( n76192 , n2500 );
or ( n76193 , n72071 , n76192 );
nand ( n76194 , n76191 , n76193 );
buf ( n76195 , n76194 );
buf ( n76196 , 1'b0 );
not ( n76197 , n68838 );
buf ( n10059 , n76197 );
buf ( n76199 , n68634 );
not ( n76200 , n69338 );
or ( n76201 , n71992 , n76200 );
not ( n76202 , n2501 );
or ( n76203 , n72071 , n76202 );
nand ( n76204 , n76201 , n76203 );
buf ( n10066 , n76204 );
buf ( n10067 , 1'b0 );
not ( n76207 , n68838 );
buf ( n10069 , n76207 );
buf ( n10070 , n68634 );
not ( n76210 , n69324 );
or ( n76211 , n71992 , n76210 );
not ( n76212 , n2502 );
or ( n76213 , n72071 , n76212 );
nand ( n76214 , n76211 , n76213 );
buf ( n76215 , n76214 );
buf ( n76216 , 1'b0 );
not ( n76217 , n68838 );
buf ( n76218 , n76217 );
buf ( n76219 , n68634 );
not ( n76220 , n69298 );
not ( n76221 , n70139 );
or ( n76222 , n76220 , n76221 );
nand ( n76223 , n70859 , n2503 );
nand ( n76224 , n76222 , n76223 );
buf ( n76225 , n76224 );
buf ( n76226 , 1'b0 );
not ( n76227 , n68838 );
buf ( n10089 , n76227 );
buf ( n76229 , n68634 );
not ( n76230 , n69311 );
or ( n76231 , n71992 , n76230 );
not ( n76232 , n2504 );
or ( n76233 , n72071 , n76232 );
nand ( n76234 , n76231 , n76233 );
buf ( n76235 , n76234 );
buf ( n76236 , 1'b0 );
not ( n76237 , n68838 );
buf ( n10099 , n76237 );
buf ( n10100 , n68634 );
not ( n76240 , n69289 );
not ( n76241 , n70139 );
or ( n76242 , n76240 , n76241 );
nand ( n76243 , n70859 , n68644 );
nand ( n76244 , n76242 , n76243 );
buf ( n76245 , n76244 );
buf ( n76246 , 1'b0 );
not ( n76247 , n68838 );
buf ( n76248 , n76247 );
buf ( n76249 , n68634 );
not ( n76250 , n69277 );
or ( n76251 , n71992 , n76250 );
not ( n76252 , n68645 );
or ( n76253 , n72071 , n76252 );
nand ( n76254 , n76251 , n76253 );
buf ( n76255 , n76254 );
buf ( n76256 , 1'b0 );
not ( n76257 , n68838 );
buf ( n10119 , n76257 );
buf ( n10120 , n68634 );
not ( n76260 , n69265 );
or ( n76261 , n71992 , n76260 );
not ( n76262 , n68646 );
or ( n76263 , n72071 , n76262 );
nand ( n76264 , n76261 , n76263 );
buf ( n10126 , n76264 );
buf ( n10127 , 1'b0 );
not ( n76267 , n68838 );
buf ( n10129 , n76267 );
buf ( n10130 , n68634 );
not ( n76270 , n69256 );
or ( n76271 , n71992 , n76270 );
not ( n76272 , n2508 );
or ( n76273 , n72071 , n76272 );
nand ( n76274 , n76271 , n76273 );
buf ( n10136 , n76274 );
buf ( n10137 , 1'b0 );
not ( n76277 , n68838 );
buf ( n76278 , n76277 );
buf ( n10140 , n68634 );
not ( n76280 , n69106 );
not ( n76281 , n70139 );
or ( n76282 , n76280 , n76281 );
nand ( n76283 , n70859 , n68666 );
nand ( n76284 , n76282 , n76283 );
buf ( n76285 , n76284 );
buf ( n76286 , 1'b0 );
not ( n76287 , n68838 );
buf ( n76288 , n76287 );
buf ( n76289 , n68634 );
not ( n76290 , n69240 );
or ( n76291 , n71992 , n76290 );
not ( n76292 , n2509 );
or ( n76293 , n72071 , n76292 );
nand ( n76294 , n76291 , n76293 );
buf ( n10156 , n76294 );
buf ( n76296 , 1'b0 );
not ( n76297 , n68838 );
buf ( n76298 , n76297 );
buf ( n76299 , n68634 );
not ( n76300 , n68649 );
not ( n76301 , n70859 );
or ( n76302 , n76300 , n76301 );
not ( n76303 , n69157 );
or ( n76304 , n71992 , n76303 );
nand ( n76305 , n76302 , n76304 );
buf ( n76306 , n76305 );
buf ( n76307 , 1'b0 );
not ( n76308 , n68838 );
buf ( n76309 , n76308 );
buf ( n76310 , n68634 );
not ( n76311 , n69176 );
or ( n76312 , n71992 , n76311 );
not ( n76313 , n68650 );
or ( n76314 , n72071 , n76313 );
nand ( n76315 , n76312 , n76314 );
buf ( n76316 , n76315 );
buf ( n76317 , 1'b0 );
not ( n76318 , n68838 );
buf ( n76319 , n76318 );
buf ( n76320 , n68634 );
not ( n76321 , n69187 );
not ( n76322 , n70139 );
or ( n76323 , n76321 , n76322 );
nand ( n76324 , n70859 , n68651 );
nand ( n76325 , n76323 , n76324 );
buf ( n76326 , n76325 );
buf ( n76327 , 1'b0 );
not ( n76328 , n68838 );
buf ( n10190 , n76328 );
buf ( n10191 , n68634 );
not ( n76331 , n68934 );
or ( n76332 , n76331 , n71992 );
nand ( n76333 , n70859 , n2513 );
nand ( n76334 , n76332 , n76333 );
buf ( n10196 , n76334 );
buf ( n10197 , 1'b0 );
not ( n76337 , n68838 );
buf ( n76338 , n76337 );
buf ( n76339 , n68634 );
not ( n76340 , n68961 );
or ( n76341 , n71992 , n76340 );
nand ( n76342 , n70859 , n2514 );
nand ( n76343 , n76341 , n76342 );
buf ( n76344 , n76343 );
buf ( n76345 , 1'b0 );
not ( n76346 , n68838 );
buf ( n76347 , n76346 );
buf ( n76348 , n68634 );
not ( n76349 , n68947 );
or ( n76350 , n71992 , n76349 );
nand ( n76351 , n70859 , n2515 );
nand ( n76352 , n76350 , n76351 );
buf ( n76353 , n76352 );
buf ( n76354 , 1'b0 );
not ( n76355 , n68838 );
buf ( n76356 , n76355 );
buf ( n76357 , n68634 );
not ( n76358 , n68908 );
or ( n76359 , n71992 , n76358 );
nand ( n76360 , n70859 , n2516 );
nand ( n76361 , n76359 , n76360 );
buf ( n10223 , n76361 );
buf ( n10224 , 1'b0 );
not ( n76364 , n68838 );
buf ( n76365 , n76364 );
buf ( n76366 , n68634 );
not ( n76367 , n68977 );
or ( n76368 , n71992 , n76367 );
nand ( n76369 , n70859 , n2517 );
nand ( n76370 , n76368 , n76369 );
buf ( n10232 , n76370 );
buf ( n10233 , 1'b0 );
not ( n76373 , n68838 );
buf ( n76374 , n76373 );
buf ( n76375 , n68634 );
not ( n76376 , n69045 );
or ( n76377 , n71992 , n76376 );
nand ( n76378 , n70859 , n2518 );
nand ( n76379 , n76377 , n76378 );
buf ( n76380 , n76379 );
buf ( n76381 , 1'b0 );
not ( n76382 , n68838 );
buf ( n76383 , n76382 );
buf ( n76384 , n68634 );
not ( n76385 , n2728 );
not ( n76386 , n70139 );
or ( n76387 , n76385 , n76386 );
nand ( n76388 , n70859 , n2528 );
nand ( n76389 , n76387 , n76388 );
buf ( n76390 , n76389 );
buf ( n76391 , 1'b0 );
not ( n76392 , n68838 );
buf ( n76393 , n76392 );
buf ( n76394 , n68634 );
not ( n76395 , n69619 );
not ( n76396 , n76395 );
not ( n76397 , n69947 );
nand ( n76398 , n76397 , n73902 );
not ( n76399 , n76398 );
or ( n76400 , n76396 , n76399 );
not ( n76401 , n76398 );
not ( n76402 , n76401 );
and ( n76403 , n69553 , n69543 );
and ( n76404 , n76403 , n69531 , n69519 );
nand ( n76405 , n69470 , n69451 , n69435 , n69471 );
nand ( n76406 , n69487 , n69502 );
nor ( n76407 , n76405 , n76406 );
nand ( n76408 , n76404 , n76407 );
not ( n76409 , n76408 );
and ( n76410 , n69587 , n69576 );
and ( n76411 , n76410 , n69599 );
nand ( n76412 , n76409 , n76411 );
not ( n76413 , n69613 );
xor ( n76414 , n76412 , n76413 );
not ( n76415 , n76414 );
or ( n76416 , n76402 , n76415 );
nand ( n76417 , n76400 , n76416 );
not ( n76418 , n70238 );
nor ( n76419 , n76417 , n76418 );
not ( n76420 , n69599 );
nand ( n76421 , n76404 , n76407 , n76410 );
not ( n76422 , n76421 );
or ( n76423 , n76420 , n76422 );
or ( n76424 , n76421 , n69599 );
nand ( n76425 , n76423 , n76424 );
not ( n76426 , n76425 );
or ( n76427 , n76398 , n76426 );
nand ( n76428 , n76398 , n69981 );
nand ( n76429 , n76427 , n76428 );
not ( n76430 , n70327 );
nor ( n76431 , n76429 , n76430 );
nor ( n76432 , n76419 , n76431 );
not ( n76433 , n70296 );
and ( n76434 , n76403 , n69531 , n69519 );
nand ( n76435 , n76434 , n76407 , n69587 );
xnor ( n76436 , n76435 , n69576 );
not ( n76437 , n76436 );
or ( n76438 , n76398 , n76437 );
nand ( n76439 , n76398 , n70098 );
nand ( n76440 , n76438 , n76439 );
nor ( n76441 , n76433 , n76440 );
not ( n76442 , n70308 );
not ( n76443 , n69990 );
not ( n76444 , n76398 );
not ( n76445 , n76444 );
not ( n76446 , n76445 );
or ( n76447 , n76443 , n76446 );
not ( n76448 , n69587 );
not ( n76449 , n76408 );
or ( n76450 , n76448 , n76449 );
or ( n76451 , n76408 , n69587 );
nand ( n76452 , n76450 , n76451 );
not ( n76453 , n76452 );
or ( n76454 , n76398 , n76453 );
nand ( n76455 , n76447 , n76454 );
nor ( n76456 , n76442 , n76455 );
nor ( n76457 , n76441 , n76456 );
and ( n76458 , n76432 , n76457 );
not ( n76459 , n70378 );
not ( n76460 , n76459 );
not ( n76461 , n70082 );
not ( n76462 , n76398 );
or ( n76463 , n76461 , n76462 );
not ( n76464 , n76401 );
xor ( n76465 , n69553 , n76407 );
not ( n76466 , n76465 );
or ( n76467 , n76464 , n76466 );
nand ( n76468 , n76463 , n76467 );
not ( n76469 , n76468 );
or ( n76470 , n76460 , n76469 );
not ( n76471 , n70263 );
not ( n76472 , n69543 );
nand ( n76473 , n76407 , n69553 );
not ( n76474 , n76473 );
or ( n76475 , n76472 , n76474 );
or ( n76476 , n76473 , n69543 );
nand ( n76477 , n76475 , n76476 );
not ( n76478 , n76477 );
or ( n76479 , n76398 , n76478 );
nand ( n76480 , n76398 , n70007 );
nand ( n76481 , n76479 , n76480 );
nand ( n76482 , n76471 , n76481 );
nand ( n76483 , n76470 , n76482 );
not ( n76484 , n76481 );
nand ( n76485 , n76484 , n70263 );
nand ( n76486 , n76483 , n76485 );
not ( n76487 , n70253 );
not ( n76488 , n70013 );
not ( n76489 , n76398 );
or ( n76490 , n76488 , n76489 );
not ( n76491 , n69531 );
nand ( n76492 , n76407 , n76403 );
not ( n76493 , n76492 );
or ( n76494 , n76491 , n76493 );
or ( n76495 , n76492 , n69531 );
nand ( n76496 , n76494 , n76495 );
not ( n76497 , n76496 );
or ( n76498 , n76402 , n76497 );
nand ( n76499 , n76490 , n76498 );
not ( n76500 , n76499 );
not ( n76501 , n76500 );
or ( n76502 , n76487 , n76501 );
not ( n76503 , n69519 );
nand ( n76504 , n76407 , n76403 , n69531 );
not ( n76505 , n76504 );
or ( n76506 , n76503 , n76505 );
or ( n76507 , n76504 , n69519 );
nand ( n76508 , n76506 , n76507 );
not ( n76509 , n76508 );
or ( n76510 , n76398 , n76509 );
not ( n76511 , n76398 );
not ( n76512 , n76511 );
not ( n76513 , n71529 );
nand ( n76514 , n76512 , n76513 );
nand ( n76515 , n76510 , n76514 );
not ( n76516 , n70273 );
nor ( n76517 , n76515 , n76516 );
not ( n76518 , n76517 );
nand ( n76519 , n76502 , n76518 );
or ( n76520 , n76486 , n76519 );
not ( n76521 , n70253 );
nand ( n76522 , n76521 , n76499 );
or ( n76523 , n76517 , n76522 );
not ( n76524 , n76515 );
or ( n76525 , n76524 , n70273 );
nand ( n76526 , n76523 , n76525 );
not ( n76527 , n76526 );
nand ( n76528 , n76520 , n76527 );
and ( n76529 , n76458 , n76528 );
not ( n76530 , n76432 );
not ( n76531 , n70308 );
nand ( n76532 , n76531 , n76455 );
or ( n76533 , n76441 , n76532 );
not ( n76534 , n76440 );
or ( n76535 , n76534 , n70296 );
nand ( n76536 , n76533 , n76535 );
not ( n76537 , n76536 );
or ( n76538 , n76530 , n76537 );
not ( n76539 , n76419 );
nand ( n76540 , n76429 , n76430 );
not ( n76541 , n76540 );
and ( n76542 , n76539 , n76541 );
and ( n76543 , n76417 , n76418 );
nor ( n76544 , n76542 , n76543 );
nand ( n76545 , n76538 , n76544 );
nor ( n76546 , n76529 , n76545 );
not ( n76547 , n70378 );
not ( n76548 , n76468 );
not ( n76549 , n76548 );
or ( n76550 , n76547 , n76549 );
nand ( n76551 , n76550 , n76485 );
nor ( n76552 , n76551 , n76519 );
not ( n76553 , n70024 );
not ( n76554 , n76398 );
or ( n76555 , n76553 , n76554 );
not ( n76556 , n76398 );
not ( n76557 , n69502 );
nand ( n76558 , n69451 , n69471 );
not ( n76559 , n76558 );
nand ( n76560 , n76559 , n69487 );
not ( n76561 , n76560 );
or ( n76562 , n76557 , n76561 );
or ( n76563 , n76560 , n69502 );
nand ( n76564 , n76562 , n76563 );
nand ( n76565 , n76556 , n76564 );
nand ( n76566 , n76555 , n76565 );
not ( n76567 , n70432 );
nor ( n76568 , n76566 , n76567 );
not ( n76569 , n72302 );
not ( n76570 , n69487 );
not ( n76571 , n76558 );
or ( n76572 , n76570 , n76571 );
or ( n76573 , n76558 , n69487 );
nand ( n76574 , n76572 , n76573 );
not ( n76575 , n76574 );
or ( n76576 , n76398 , n76575 );
nand ( n76577 , n76512 , n70038 );
nand ( n76578 , n76576 , n76577 );
nor ( n76579 , n76569 , n76578 );
nor ( n76580 , n76568 , n76579 );
not ( n76581 , n69470 );
not ( n76582 , n76406 );
nand ( n76583 , n76582 , n76559 , n69435 );
not ( n76584 , n76583 );
or ( n76585 , n76581 , n76584 );
or ( n76586 , n76583 , n69470 );
nand ( n76587 , n76585 , n76586 );
not ( n76588 , n76587 );
or ( n76589 , n76398 , n76588 );
nand ( n76590 , n76512 , n70090 );
nand ( n76591 , n76589 , n76590 );
not ( n76592 , n70388 );
nor ( n76593 , n76591 , n76592 );
not ( n76594 , n70031 );
not ( n76595 , n76398 );
or ( n76596 , n76594 , n76595 );
not ( n76597 , n76444 );
not ( n76598 , n69435 );
or ( n76599 , n76558 , n76406 );
not ( n76600 , n76599 );
or ( n76601 , n76598 , n76600 );
or ( n76602 , n76599 , n69435 );
nand ( n76603 , n76601 , n76602 );
not ( n76604 , n76603 );
or ( n76605 , n76597 , n76604 );
nand ( n76606 , n76596 , n76605 );
not ( n76607 , n70477 );
nor ( n76608 , n76606 , n76607 );
nor ( n76609 , n76593 , n76608 );
not ( n76610 , n70420 );
not ( n76611 , n76610 );
not ( n76612 , n69451 );
not ( n76613 , n69471 );
and ( n76614 , n76612 , n76613 );
nor ( n76615 , n76614 , n76559 );
not ( n76616 , n76615 );
or ( n76617 , n76398 , n76616 );
nand ( n76618 , n76512 , n70040 );
nand ( n76619 , n76617 , n76618 );
not ( n76620 , n76619 );
or ( n76621 , n76611 , n76620 );
or ( n76622 , n76619 , n76610 );
not ( n76623 , n70053 );
nand ( n76624 , n76623 , n70503 );
not ( n76625 , n69967 );
nand ( n76626 , n76625 , n70522 );
and ( n76627 , n76624 , n76626 );
not ( n76628 , n70503 );
and ( n76629 , n70053 , n76628 );
nor ( n76630 , n76627 , n76629 );
not ( n76631 , n70073 );
and ( n76632 , n76631 , n70459 );
or ( n76633 , n76630 , n76632 );
or ( n76634 , n76631 , n70459 );
nand ( n76635 , n76633 , n76634 );
nand ( n76636 , n76622 , n76635 );
nand ( n76637 , n76621 , n76636 );
nand ( n76638 , n76580 , n76609 , n76637 );
not ( n76639 , n72302 );
nand ( n76640 , n76639 , n76578 );
not ( n76641 , n70432 );
nand ( n76642 , n76641 , n76566 );
and ( n76643 , n76640 , n76642 );
nor ( n76644 , n76643 , n76568 );
nand ( n76645 , n76644 , n76609 );
nand ( n76646 , n76606 , n76607 );
nor ( n76647 , n76593 , n76646 );
and ( n76648 , n76591 , n76592 );
nor ( n76649 , n76647 , n76648 );
nand ( n76650 , n76638 , n76645 , n76649 );
nand ( n76651 , n76552 , n76458 , n76650 );
nand ( n76652 , n76546 , n76651 );
and ( n76653 , n69599 , n69613 );
nand ( n76654 , n76410 , n76653 );
nor ( n76655 , n76408 , n76654 );
nand ( n76656 , n69655 , n69641 );
nand ( n76657 , n69896 , n69769 );
nor ( n76658 , n76656 , n76657 );
and ( n76659 , n69822 , n69871 , n69804 , n69792 );
nand ( n76660 , n76658 , n76659 );
nand ( n76661 , n69932 , n69850 );
nand ( n76662 , n69685 , n69706 );
nor ( n76663 , n76661 , n76662 );
not ( n76664 , n72628 );
nand ( n76665 , n76663 , n76664 );
nor ( n76666 , n76660 , n76665 );
nand ( n76667 , n76655 , n76666 );
not ( n76668 , n69743 );
and ( n76669 , n76667 , n76668 );
not ( n76670 , n76667 );
and ( n76671 , n76670 , n69743 );
nor ( n76672 , n76669 , n76671 );
not ( n76673 , n76672 );
or ( n76674 , n76445 , n76673 );
nand ( n76675 , n76398 , n72463 );
nand ( n76676 , n76674 , n76675 );
not ( n76677 , n76676 );
nand ( n76678 , n76677 , n73916 );
not ( n76679 , n76663 );
nand ( n76680 , n76658 , n76659 );
nor ( n76681 , n76679 , n76680 );
nand ( n76682 , n76655 , n76681 );
not ( n76683 , n76664 );
and ( n76684 , n76682 , n76683 );
not ( n76685 , n76682 );
and ( n76686 , n76685 , n76664 );
nor ( n76687 , n76684 , n76686 );
not ( n76688 , n76687 );
or ( n76689 , n76398 , n76688 );
nand ( n76690 , n76512 , n72452 );
nand ( n76691 , n76689 , n76690 );
not ( n76692 , n76691 );
nand ( n76693 , n76692 , n72626 );
nand ( n76694 , n76678 , n76693 );
not ( n76695 , n73914 );
nand ( n76696 , n76664 , n69743 );
not ( n76697 , n76696 );
nand ( n76698 , n76697 , n76663 );
nor ( n76699 , n76680 , n76698 );
nand ( n76700 , n76655 , n76699 );
and ( n76701 , n76700 , n69908 );
not ( n76702 , n76700 );
not ( n76703 , n69908 );
and ( n76704 , n76702 , n76703 );
nor ( n76705 , n76701 , n76704 );
not ( n76706 , n76705 );
or ( n76707 , n76398 , n76706 );
nand ( n76708 , n76398 , n73902 );
nand ( n76709 , n76707 , n76708 );
not ( n76710 , n76709 );
not ( n76711 , n76710 );
or ( n76712 , n76695 , n76711 );
nor ( n76713 , n76696 , n69908 );
nand ( n76714 , n76663 , n76713 );
nor ( n76715 , n76680 , n76714 );
nand ( n76716 , n76655 , n76715 );
not ( n76717 , n69942 );
and ( n76718 , n76717 , n76703 );
not ( n76719 , n76717 );
and ( n76720 , n76719 , n69908 );
nor ( n76721 , n76718 , n76720 );
xor ( n76722 , n76716 , n76721 );
not ( n76723 , n76722 );
not ( n76724 , n76398 );
not ( n76725 , n76724 );
or ( n76726 , n76723 , n76725 );
not ( n76727 , n69947 );
nand ( n76728 , n76726 , n76727 );
not ( n76729 , n73912 );
nand ( n76730 , n76728 , n76729 );
nand ( n76731 , n76712 , n76730 );
nor ( n76732 , n76694 , n76731 );
not ( n76733 , n76661 );
nand ( n76734 , n76733 , n69685 );
nor ( n76735 , n76660 , n76734 );
nand ( n76736 , n76655 , n76735 );
not ( n76737 , n69706 );
and ( n76738 , n76736 , n76737 );
not ( n76739 , n76736 );
and ( n76740 , n76739 , n69706 );
nor ( n76741 , n76738 , n76740 );
not ( n76742 , n76741 );
or ( n76743 , n76597 , n76742 );
nand ( n76744 , n76398 , n71763 );
nand ( n76745 , n76743 , n76744 );
not ( n76746 , n72815 );
nor ( n76747 , n76745 , n76746 );
not ( n76748 , n71779 );
not ( n76749 , n76748 );
not ( n76750 , n76512 );
or ( n76751 , n76749 , n76750 );
nor ( n76752 , n76660 , n76661 );
nand ( n76753 , n76655 , n76752 );
not ( n76754 , n69685 );
and ( n76755 , n76753 , n76754 );
not ( n76756 , n76753 );
and ( n76757 , n76756 , n69685 );
nor ( n76758 , n76755 , n76757 );
not ( n76759 , n76758 );
or ( n76760 , n76597 , n76759 );
nand ( n76761 , n76751 , n76760 );
not ( n76762 , n72534 );
nor ( n76763 , n76761 , n76762 );
nor ( n76764 , n76747 , n76763 );
not ( n76765 , n76764 );
not ( n76766 , n72557 );
not ( n76767 , n76680 );
nand ( n76768 , n76767 , n76655 );
not ( n76769 , n69932 );
and ( n76770 , n76768 , n76769 );
not ( n76771 , n76768 );
and ( n76772 , n76771 , n69932 );
nor ( n76773 , n76770 , n76772 );
not ( n76774 , n76773 );
or ( n76775 , n76398 , n76774 );
nand ( n76776 , n76398 , n71814 );
nand ( n76777 , n76775 , n76776 );
not ( n76778 , n76777 );
not ( n76779 , n76778 );
or ( n76780 , n76766 , n76779 );
not ( n76781 , n71798 );
not ( n76782 , n76781 );
not ( n76783 , n76398 );
or ( n76784 , n76782 , n76783 );
nor ( n76785 , n76660 , n76769 );
nand ( n76786 , n76655 , n76785 );
not ( n76787 , n69850 );
and ( n76788 , n76786 , n76787 );
not ( n76789 , n76786 );
and ( n76790 , n76789 , n69850 );
nor ( n76791 , n76788 , n76790 );
not ( n76792 , n76791 );
or ( n76793 , n76398 , n76792 );
nand ( n76794 , n76784 , n76793 );
not ( n76795 , n72544 );
nor ( n76796 , n76794 , n76795 );
not ( n76797 , n76796 );
nand ( n76798 , n76780 , n76797 );
nor ( n76799 , n76765 , n76798 );
nand ( n76800 , n76732 , n76799 );
nand ( n76801 , n69804 , n69822 );
nor ( n76802 , n76656 , n76801 );
nand ( n76803 , n69896 , n69871 );
not ( n76804 , n69792 );
nor ( n76805 , n76803 , n76804 );
and ( n76806 , n76802 , n76805 );
nand ( n76807 , n76655 , n76806 );
not ( n76808 , n69769 );
and ( n76809 , n76807 , n76808 );
not ( n76810 , n76807 );
and ( n76811 , n76810 , n69769 );
nor ( n76812 , n76809 , n76811 );
not ( n76813 , n76812 );
or ( n76814 , n76597 , n76813 );
not ( n76815 , n71833 );
nand ( n76816 , n76398 , n76815 );
nand ( n76817 , n76814 , n76816 );
not ( n76818 , n72510 );
nor ( n76819 , n76817 , n76818 );
not ( n76820 , n72499 );
not ( n76821 , n71852 );
not ( n76822 , n76445 );
or ( n76823 , n76821 , n76822 );
not ( n76824 , n76803 );
and ( n76825 , n76802 , n76824 );
nand ( n76826 , n76655 , n76825 );
and ( n76827 , n76826 , n76804 );
not ( n76828 , n76826 );
and ( n76829 , n76828 , n69792 );
nor ( n76830 , n76827 , n76829 );
not ( n76831 , n76830 );
or ( n76832 , n76398 , n76831 );
nand ( n76833 , n76823 , n76832 );
nor ( n76834 , n76820 , n76833 );
nor ( n76835 , n76819 , n76834 );
not ( n76836 , n71869 );
not ( n76837 , n76398 );
or ( n76838 , n76836 , n76837 );
and ( n76839 , n76802 , n69871 );
nand ( n76840 , n76655 , n76839 );
not ( n76841 , n69896 );
and ( n76842 , n76840 , n76841 );
not ( n76843 , n76840 );
and ( n76844 , n76843 , n69896 );
nor ( n76845 , n76842 , n76844 );
not ( n76846 , n76845 );
or ( n76847 , n76464 , n76846 );
nand ( n76848 , n76838 , n76847 );
not ( n76849 , n72475 );
nor ( n76850 , n76848 , n76849 );
not ( n76851 , n71037 );
not ( n76852 , n76398 );
or ( n76853 , n76851 , n76852 );
nand ( n76854 , n76655 , n76802 );
not ( n76855 , n69871 );
and ( n76856 , n76854 , n76855 );
not ( n76857 , n76854 );
and ( n76858 , n76857 , n69871 );
nor ( n76859 , n76856 , n76858 );
not ( n76860 , n76859 );
or ( n76861 , n76402 , n76860 );
nand ( n76862 , n76853 , n76861 );
not ( n76863 , n72485 );
nor ( n76864 , n76862 , n76863 );
nor ( n76865 , n76850 , n76864 );
and ( n76866 , n76835 , n76865 );
not ( n76867 , n70225 );
not ( n76868 , n69977 );
not ( n76869 , n76398 );
or ( n76870 , n76868 , n76869 );
xor ( n76871 , n69641 , n76655 );
not ( n76872 , n76871 );
or ( n76873 , n76398 , n76872 );
nand ( n76874 , n76870 , n76873 );
not ( n76875 , n76874 );
not ( n76876 , n76875 );
or ( n76877 , n76867 , n76876 );
nand ( n76878 , n76655 , n69641 );
not ( n76879 , n69655 );
and ( n76880 , n76878 , n76879 );
not ( n76881 , n76878 );
and ( n76882 , n76881 , n69655 );
nor ( n76883 , n76880 , n76882 );
not ( n76884 , n76883 );
or ( n76885 , n76398 , n76884 );
nand ( n76886 , n76445 , n69660 );
nand ( n76887 , n76885 , n76886 );
not ( n76888 , n76887 );
nand ( n76889 , n76888 , n71074 );
nand ( n76890 , n76877 , n76889 );
not ( n76891 , n71092 );
not ( n76892 , n71047 );
not ( n76893 , n76398 );
or ( n76894 , n76892 , n76893 );
not ( n76895 , n76656 );
nand ( n76896 , n76895 , n76655 );
not ( n76897 , n69822 );
and ( n76898 , n76896 , n76897 );
not ( n76899 , n76896 );
and ( n76900 , n76899 , n69822 );
nor ( n76901 , n76898 , n76900 );
not ( n76902 , n76901 );
or ( n76903 , n76402 , n76902 );
nand ( n76904 , n76894 , n76903 );
not ( n76905 , n76904 );
not ( n76906 , n76905 );
or ( n76907 , n76891 , n76906 );
nor ( n76908 , n76656 , n76897 );
nand ( n76909 , n76655 , n76908 );
xnor ( n76910 , n76909 , n69804 );
not ( n76911 , n76910 );
not ( n76912 , n76401 );
or ( n76913 , n76911 , n76912 );
not ( n76914 , n76398 );
not ( n76915 , n71058 );
or ( n76916 , n76914 , n76915 );
nand ( n76917 , n76913 , n76916 );
not ( n76918 , n71122 );
nor ( n76919 , n76917 , n76918 );
not ( n76920 , n76919 );
nand ( n76921 , n76907 , n76920 );
nor ( n76922 , n76890 , n76921 );
nand ( n76923 , n76866 , n76922 );
nor ( n76924 , n76800 , n76923 );
and ( n76925 , n76652 , n76924 );
not ( n76926 , n71074 );
nand ( n76927 , n76926 , n76887 );
not ( n76928 , n76927 );
not ( n76929 , n70225 );
nand ( n76930 , n76929 , n76874 );
not ( n76931 , n76930 );
or ( n76932 , n76928 , n76931 );
nand ( n76933 , n76932 , n76889 );
or ( n76934 , n76921 , n76933 );
not ( n76935 , n71092 );
nand ( n76936 , n76935 , n76904 );
or ( n76937 , n76919 , n76936 );
nand ( n76938 , n76917 , n76918 );
nand ( n76939 , n76937 , n76938 );
not ( n76940 , n76939 );
nand ( n76941 , n76934 , n76940 );
and ( n76942 , n76866 , n76941 );
not ( n76943 , n76835 );
nand ( n76944 , n76862 , n76863 );
or ( n76945 , n76850 , n76944 );
nand ( n76946 , n76848 , n76849 );
nand ( n76947 , n76945 , n76946 );
not ( n76948 , n76947 );
or ( n76949 , n76943 , n76948 );
not ( n76950 , n76819 );
not ( n76951 , n72499 );
nand ( n76952 , n76951 , n76833 );
not ( n76953 , n76952 );
and ( n76954 , n76950 , n76953 );
and ( n76955 , n76817 , n76818 );
nor ( n76956 , n76954 , n76955 );
nand ( n76957 , n76949 , n76956 );
nor ( n76958 , n76942 , n76957 );
or ( n76959 , n76958 , n76800 );
not ( n76960 , n76764 );
not ( n76961 , n72557 );
nand ( n76962 , n76961 , n76777 );
or ( n76963 , n76796 , n76962 );
nand ( n76964 , n76794 , n76795 );
nand ( n76965 , n76963 , n76964 );
not ( n76966 , n76965 );
or ( n76967 , n76960 , n76966 );
not ( n76968 , n76747 );
nand ( n76969 , n76761 , n76762 );
not ( n76970 , n76969 );
and ( n76971 , n76968 , n76970 );
and ( n76972 , n76745 , n76746 );
nor ( n76973 , n76971 , n76972 );
nand ( n76974 , n76967 , n76973 );
and ( n76975 , n76974 , n76732 );
not ( n76976 , n76691 );
nor ( n76977 , n76976 , n72626 );
and ( n76978 , n76678 , n76977 );
not ( n76979 , n76676 );
nor ( n76980 , n76979 , n73916 );
nor ( n76981 , n76978 , n76980 );
or ( n76982 , n76981 , n76731 );
nor ( n76983 , n76710 , n73914 );
and ( n76984 , n76983 , n76730 );
nor ( n76985 , n76728 , n76729 );
nor ( n76986 , n76984 , n76985 );
nand ( n76987 , n76982 , n76986 );
nor ( n76988 , n76975 , n76987 );
nand ( n76989 , n76959 , n76988 );
nor ( n76990 , n76925 , n76989 );
not ( n76991 , n76990 );
not ( n76992 , n72499 );
not ( n76993 , n76992 );
not ( n76994 , n71852 );
or ( n76995 , n76993 , n76994 );
not ( n76996 , n72510 );
nand ( n76997 , n76815 , n76996 );
nand ( n76998 , n76995 , n76997 );
not ( n76999 , n72485 );
not ( n77000 , n76999 );
not ( n77001 , n71037 );
or ( n77002 , n77000 , n77001 );
not ( n77003 , n72475 );
nand ( n77004 , n71869 , n77003 );
nand ( n77005 , n77002 , n77004 );
nor ( n77006 , n76998 , n77005 );
not ( n77007 , n71092 );
not ( n77008 , n77007 );
not ( n77009 , n71047 );
or ( n77010 , n77008 , n77009 );
not ( n77011 , n71122 );
nand ( n77012 , n71058 , n77011 );
nand ( n77013 , n77010 , n77012 );
not ( n77014 , n71074 );
not ( n77015 , n69660 );
not ( n77016 , n77015 );
or ( n77017 , n77014 , n77016 );
not ( n77018 , n69977 );
nand ( n77019 , n77018 , n70225 );
nand ( n77020 , n77017 , n77019 );
not ( n77021 , n71074 );
nand ( n77022 , n77021 , n69660 );
nand ( n77023 , n77020 , n77022 );
or ( n77024 , n77013 , n77023 );
nor ( n77025 , n71047 , n77007 );
and ( n77026 , n77012 , n77025 );
nor ( n77027 , n71058 , n77011 );
nor ( n77028 , n77026 , n77027 );
nand ( n77029 , n77024 , n77028 );
and ( n77030 , n77006 , n77029 );
nor ( n77031 , n71037 , n76999 );
and ( n77032 , n77004 , n77031 );
nor ( n77033 , n71869 , n77003 );
nor ( n77034 , n77032 , n77033 );
or ( n77035 , n77034 , n76998 );
nor ( n77036 , n71852 , n76992 );
and ( n77037 , n76997 , n77036 );
nor ( n77038 , n76815 , n76996 );
nor ( n77039 , n77037 , n77038 );
nand ( n77040 , n77035 , n77039 );
nor ( n77041 , n77030 , n77040 );
not ( n77042 , n72626 );
not ( n77043 , n77042 );
not ( n77044 , n72452 );
or ( n77045 , n77043 , n77044 );
not ( n77046 , n73916 );
nand ( n77047 , n77046 , n72463 );
nand ( n77048 , n77045 , n77047 );
not ( n77049 , n73914 );
not ( n77050 , n77049 );
not ( n77051 , n73902 );
or ( n77052 , n77050 , n77051 );
not ( n77053 , n69947 );
nand ( n77054 , n77053 , n73912 );
nand ( n77055 , n77052 , n77054 );
nor ( n77056 , n77048 , n77055 );
not ( n77057 , n72534 );
not ( n77058 , n77057 );
not ( n77059 , n76748 );
or ( n77060 , n77058 , n77059 );
not ( n77061 , n72815 );
nand ( n77062 , n71763 , n77061 );
nand ( n77063 , n77060 , n77062 );
not ( n77064 , n72557 );
not ( n77065 , n77064 );
not ( n77066 , n71814 );
or ( n77067 , n77065 , n77066 );
not ( n77068 , n72544 );
nand ( n77069 , n76781 , n77068 );
nand ( n77070 , n77067 , n77069 );
nor ( n77071 , n77063 , n77070 );
nand ( n77072 , n77056 , n77071 );
or ( n77073 , n77041 , n77072 );
nor ( n77074 , n76781 , n77068 );
nor ( n77075 , n71814 , n77064 );
or ( n77076 , n77074 , n77075 );
nand ( n77077 , n77076 , n77069 );
or ( n77078 , n77063 , n77077 );
nor ( n77079 , n76748 , n77057 );
and ( n77080 , n77062 , n77079 );
nor ( n77081 , n71763 , n77061 );
nor ( n77082 , n77080 , n77081 );
nand ( n77083 , n77078 , n77082 );
and ( n77084 , n77056 , n77083 );
not ( n77085 , n72463 );
not ( n77086 , n73916 );
not ( n77087 , n77086 );
and ( n77088 , n77085 , n77087 );
nor ( n77089 , n72452 , n77042 );
and ( n77090 , n77047 , n77089 );
nor ( n77091 , n77088 , n77090 );
or ( n77092 , n77091 , n77055 );
nor ( n77093 , n73902 , n77049 );
and ( n77094 , n77054 , n77093 );
not ( n77095 , n69947 );
nor ( n77096 , n77095 , n73912 );
nor ( n77097 , n77094 , n77096 );
nand ( n77098 , n77092 , n77097 );
nor ( n77099 , n77084 , n77098 );
nand ( n77100 , n77073 , n77099 );
not ( n77101 , n70225 );
not ( n77102 , n77101 );
not ( n77103 , n69977 );
or ( n77104 , n77102 , n77103 );
nand ( n77105 , n77104 , n77022 );
nor ( n77106 , n77013 , n77105 );
nand ( n77107 , n77006 , n77106 );
not ( n77108 , n70327 );
not ( n77109 , n77108 );
not ( n77110 , n69981 );
or ( n77111 , n77109 , n77110 );
not ( n77112 , n70238 );
nand ( n77113 , n77112 , n76395 );
nand ( n77114 , n77111 , n77113 );
not ( n77115 , n70308 );
not ( n77116 , n77115 );
not ( n77117 , n69990 );
or ( n77118 , n77116 , n77117 );
not ( n77119 , n70296 );
nand ( n77120 , n77119 , n70098 );
nand ( n77121 , n77118 , n77120 );
nor ( n77122 , n77114 , n77121 );
not ( n77123 , n70253 );
not ( n77124 , n77123 );
not ( n77125 , n70013 );
or ( n77126 , n77124 , n77125 );
not ( n77127 , n71529 );
not ( n77128 , n70273 );
nand ( n77129 , n77127 , n77128 );
nand ( n77130 , n77126 , n77129 );
not ( n77131 , n70378 );
not ( n77132 , n77131 );
not ( n77133 , n70082 );
or ( n77134 , n77132 , n77133 );
not ( n77135 , n70263 );
nand ( n77136 , n77135 , n70007 );
nand ( n77137 , n77134 , n77136 );
nor ( n77138 , n77130 , n77137 );
not ( n77139 , n70388 );
nand ( n77140 , n70090 , n77139 );
not ( n77141 , n70477 );
nand ( n77142 , n77141 , n70031 );
and ( n77143 , n77140 , n77142 );
not ( n77144 , n70432 );
nand ( n77145 , n77144 , n70024 );
not ( n77146 , n70817 );
not ( n77147 , n77146 );
nand ( n77148 , n77147 , n70038 );
and ( n77149 , n77145 , n77148 );
not ( n77150 , n70420 );
nand ( n77151 , n77150 , n70040 );
not ( n77152 , n69967 );
nor ( n77153 , n77152 , n70522 );
not ( n77154 , n70053 );
nor ( n77155 , n77154 , n70503 );
or ( n77156 , n77153 , n77155 );
not ( n77157 , n70503 );
or ( n77158 , n70053 , n77157 );
nand ( n77159 , n77156 , n77158 );
not ( n77160 , n70459 );
nand ( n77161 , n77160 , n70073 );
nand ( n77162 , n77151 , n77159 , n77161 );
not ( n77163 , n70459 );
nor ( n77164 , n77163 , n70073 );
nand ( n77165 , n77151 , n77164 );
not ( n77166 , n70040 );
nand ( n77167 , n77166 , n70420 );
nand ( n77168 , n77162 , n77165 , n77167 );
nand ( n77169 , n77143 , n77149 , n77168 );
not ( n77170 , n77146 );
nor ( n77171 , n77170 , n70038 );
not ( n77172 , n77171 );
not ( n77173 , n77145 );
or ( n77174 , n77172 , n77173 );
not ( n77175 , n70024 );
nand ( n77176 , n77175 , n70432 );
nand ( n77177 , n77174 , n77176 );
nand ( n77178 , n77143 , n77177 );
not ( n77179 , n70477 );
nor ( n77180 , n77179 , n70031 );
and ( n77181 , n77140 , n77180 );
nor ( n77182 , n70090 , n77139 );
nor ( n77183 , n77181 , n77182 );
nand ( n77184 , n77169 , n77178 , n77183 );
and ( n77185 , n77122 , n77138 , n77184 );
not ( n77186 , n77122 );
nor ( n77187 , n70082 , n77131 );
and ( n77188 , n77136 , n77187 );
not ( n77189 , n70007 );
and ( n77190 , n77189 , n70263 );
nor ( n77191 , n77188 , n77190 );
or ( n77192 , n77191 , n77130 );
nor ( n77193 , n70013 , n77123 );
and ( n77194 , n77129 , n77193 );
nor ( n77195 , n77127 , n77128 );
nor ( n77196 , n77194 , n77195 );
nand ( n77197 , n77192 , n77196 );
not ( n77198 , n77197 );
or ( n77199 , n77186 , n77198 );
not ( n77200 , n77114 );
nor ( n77201 , n69990 , n77115 );
not ( n77202 , n77201 );
not ( n77203 , n77120 );
or ( n77204 , n77202 , n77203 );
not ( n77205 , n70098 );
nand ( n77206 , n77205 , n70296 );
nand ( n77207 , n77204 , n77206 );
and ( n77208 , n77200 , n77207 );
nor ( n77209 , n69981 , n77108 );
not ( n77210 , n77209 );
not ( n77211 , n77113 );
or ( n77212 , n77210 , n77211 );
not ( n77213 , n76395 );
nand ( n77214 , n77213 , n70238 );
nand ( n77215 , n77212 , n77214 );
nor ( n77216 , n77208 , n77215 );
nand ( n77217 , n77199 , n77216 );
nor ( n77218 , n77185 , n77217 );
nor ( n77219 , n77107 , n77218 , n77072 );
nor ( n77220 , n77100 , n77219 );
nand ( n77221 , n70196 , n70147 );
or ( n77222 , n77220 , n77221 );
or ( n77223 , n77221 , n70152 );
nand ( n77224 , n77222 , n77223 );
nand ( n77225 , n77224 , n71983 );
not ( n77226 , n70194 );
nor ( n77227 , n77226 , n70188 );
nand ( n77228 , n77227 , n70147 );
nand ( n77229 , n77221 , n77228 );
not ( n77230 , n77229 );
not ( n77231 , n77220 );
or ( n77232 , n77230 , n77231 );
nand ( n77233 , n77232 , n77223 );
nand ( n77234 , n77233 , n70874 );
not ( n77235 , n77220 );
not ( n77236 , n77228 );
nand ( n77237 , n77236 , n71983 );
not ( n77238 , n77237 );
and ( n77239 , n77235 , n77238 );
and ( n77240 , n70202 , n70206 , n70139 );
not ( n77241 , n77240 );
not ( n77242 , n70225 );
nand ( n77243 , n77242 , n69641 );
not ( n77244 , n69641 );
nand ( n77245 , n77244 , n70225 );
nand ( n77246 , n77243 , n77245 );
not ( n77247 , n70238 );
nand ( n77248 , n77247 , n69613 );
and ( n77249 , n77246 , n77248 );
not ( n77250 , n77246 );
not ( n77251 , n77248 );
and ( n77252 , n77250 , n77251 );
nor ( n77253 , n77249 , n77252 );
not ( n77254 , n72557 );
nand ( n77255 , n77254 , n69932 );
not ( n77256 , n69932 );
nand ( n77257 , n77256 , n72557 );
nand ( n77258 , n77255 , n77257 );
not ( n77259 , n72510 );
nand ( n77260 , n77259 , n69769 );
xor ( n77261 , n77258 , n77260 );
nand ( n77262 , n77253 , n77261 );
not ( n77263 , n72626 );
nand ( n77264 , n77263 , n69729 );
not ( n77265 , n69729 );
nand ( n77266 , n77265 , n72626 );
nand ( n77267 , n77264 , n77266 );
not ( n77268 , n72814 );
not ( n77269 , n77268 );
nand ( n77270 , n77269 , n69706 );
xor ( n77271 , n77267 , n77270 );
not ( n77272 , n73916 );
nand ( n77273 , n77272 , n69743 );
not ( n77274 , n77273 );
not ( n77275 , n77274 );
not ( n77276 , n73914 );
nand ( n77277 , n77276 , n69908 );
not ( n77278 , n69908 );
nand ( n77279 , n77278 , n73914 );
nand ( n77280 , n77277 , n77279 );
not ( n77281 , n77280 );
or ( n77282 , n77275 , n77281 );
or ( n77283 , n77280 , n77274 );
nand ( n77284 , n77282 , n77283 );
not ( n77285 , n77277 );
not ( n77286 , n77285 );
xor ( n77287 , n69942 , n73912 );
not ( n77288 , n77287 );
or ( n77289 , n77286 , n77288 );
or ( n77290 , n77287 , n77285 );
nand ( n77291 , n77289 , n77290 );
nand ( n77292 , n77271 , n77284 , n77291 );
nor ( n77293 , n77262 , n77292 );
not ( n77294 , n71122 );
not ( n77295 , n69804 );
not ( n77296 , n77295 );
or ( n77297 , n77294 , n77296 );
not ( n77298 , n71122 );
nand ( n77299 , n77298 , n69804 );
nand ( n77300 , n77297 , n77299 );
not ( n77301 , n77300 );
not ( n77302 , n71092 );
nand ( n77303 , n77302 , n69822 );
not ( n77304 , n77303 );
and ( n77305 , n77301 , n77304 );
and ( n77306 , n77300 , n77303 );
nor ( n77307 , n77305 , n77306 );
not ( n77308 , n71092 );
not ( n77309 , n69822 );
not ( n77310 , n77309 );
or ( n77311 , n77308 , n77310 );
nand ( n77312 , n77311 , n77303 );
not ( n77313 , n71074 );
nand ( n77314 , n77313 , n69655 );
and ( n77315 , n77312 , n77314 );
not ( n77316 , n77312 );
not ( n77317 , n77314 );
and ( n77318 , n77316 , n77317 );
nor ( n77319 , n77315 , n77318 );
not ( n77320 , n69576 );
not ( n77321 , n77320 );
not ( n77322 , n70296 );
or ( n77323 , n77321 , n77322 );
not ( n77324 , n70296 );
nand ( n77325 , n77324 , n69576 );
nand ( n77326 , n77323 , n77325 );
not ( n77327 , n70308 );
nand ( n77328 , n77327 , n69587 );
xor ( n77329 , n77326 , n77328 );
not ( n77330 , n72499 );
nand ( n77331 , n77330 , n69792 );
not ( n77332 , n69792 );
nand ( n77333 , n77332 , n72499 );
nand ( n77334 , n77331 , n77333 );
not ( n77335 , n72475 );
nand ( n77336 , n77335 , n69896 );
xor ( n77337 , n77334 , n77336 );
nand ( n77338 , n77307 , n77319 , n77329 , n77337 );
not ( n77339 , n72544 );
nand ( n77340 , n77339 , n69850 );
not ( n77341 , n69850 );
nand ( n77342 , n77341 , n72544 );
nand ( n77343 , n77340 , n77342 );
xor ( n77344 , n77343 , n77255 );
not ( n77345 , n69587 );
not ( n77346 , n77345 );
not ( n77347 , n70308 );
or ( n77348 , n77346 , n77347 );
nand ( n77349 , n77348 , n77328 );
not ( n77350 , n70273 );
nand ( n77351 , n77350 , n69519 );
xor ( n77352 , n77349 , n77351 );
not ( n77353 , n69706 );
nand ( n77354 , n77353 , n77268 );
nand ( n77355 , n77270 , n77354 );
not ( n77356 , n72534 );
nand ( n77357 , n77356 , n69685 );
xor ( n77358 , n77355 , n77357 );
not ( n77359 , n69685 );
nand ( n77360 , n77359 , n72534 );
nand ( n77361 , n77357 , n77360 );
xor ( n77362 , n77361 , n77340 );
nand ( n77363 , n77344 , n77352 , n77358 , n77362 );
nor ( n77364 , n77338 , n77363 );
not ( n77365 , n69655 );
nand ( n77366 , n77365 , n71074 );
nand ( n77367 , n77314 , n77366 );
and ( n77368 , n77367 , n77243 );
not ( n77369 , n77367 );
not ( n77370 , n77243 );
and ( n77371 , n77369 , n77370 );
nor ( n77372 , n77368 , n77371 );
not ( n77373 , n69896 );
nand ( n77374 , n77373 , n72475 );
nand ( n77375 , n77336 , n77374 );
not ( n77376 , n72485 );
nand ( n77377 , n77376 , n69871 );
xor ( n77378 , n77375 , n77377 );
not ( n77379 , n70273 );
not ( n77380 , n69519 );
not ( n77381 , n77380 );
or ( n77382 , n77379 , n77381 );
nand ( n77383 , n77382 , n77351 );
not ( n77384 , n70253 );
nand ( n77385 , n77384 , n69531 );
xor ( n77386 , n77383 , n77385 );
not ( n77387 , n69435 );
not ( n77388 , n77387 );
not ( n77389 , n70477 );
or ( n77390 , n77388 , n77389 );
not ( n77391 , n70477 );
nand ( n77392 , n77391 , n69435 );
nand ( n77393 , n77390 , n77392 );
not ( n77394 , n70432 );
nand ( n77395 , n77394 , n69502 );
xor ( n77396 , n77393 , n77395 );
nand ( n77397 , n77372 , n77378 , n77386 , n77396 );
not ( n77398 , n70327 );
not ( n77399 , n69599 );
not ( n77400 , n77399 );
or ( n77401 , n77398 , n77400 );
not ( n77402 , n70327 );
nand ( n77403 , n77402 , n69599 );
nand ( n77404 , n77401 , n77403 );
xor ( n77405 , n77404 , n77325 );
not ( n77406 , n70238 );
not ( n77407 , n69613 );
not ( n77408 , n77407 );
or ( n77409 , n77406 , n77408 );
nand ( n77410 , n77409 , n77248 );
xor ( n77411 , n77410 , n77403 );
not ( n77412 , n69871 );
nand ( n77413 , n77412 , n72485 );
nand ( n77414 , n77377 , n77413 );
xor ( n77415 , n77414 , n77299 );
not ( n77416 , n69769 );
nand ( n77417 , n77416 , n72510 );
nand ( n77418 , n77260 , n77417 );
xor ( n77419 , n77418 , n77331 );
nand ( n77420 , n77405 , n77411 , n77415 , n77419 );
nor ( n77421 , n77397 , n77420 );
not ( n77422 , n69743 );
nand ( n77423 , n77422 , n73916 );
nand ( n77424 , n77273 , n77423 );
xor ( n77425 , n77424 , n77264 );
not ( n77426 , n69487 );
not ( n77427 , n77426 );
not ( n77428 , n70817 );
not ( n77429 , n77428 );
or ( n77430 , n77427 , n77429 );
not ( n77431 , n77428 );
nand ( n77432 , n77431 , n69487 );
nand ( n77433 , n77430 , n77432 );
not ( n77434 , n70420 );
nand ( n77435 , n77434 , n69471 );
xor ( n77436 , n77433 , n77435 );
not ( n77437 , n69470 );
not ( n77438 , n77437 );
not ( n77439 , n70388 );
or ( n77440 , n77438 , n77439 );
not ( n77441 , n70388 );
nand ( n77442 , n77441 , n69470 );
nand ( n77443 , n77440 , n77442 );
xor ( n77444 , n77443 , n77392 );
not ( n77445 , n69543 );
not ( n77446 , n77445 );
not ( n77447 , n70263 );
or ( n77448 , n77446 , n77447 );
not ( n77449 , n70263 );
nand ( n77450 , n77449 , n69543 );
nand ( n77451 , n77448 , n77450 );
not ( n77452 , n70378 );
nand ( n77453 , n77452 , n69553 );
xor ( n77454 , n77451 , n77453 );
nand ( n77455 , n77425 , n77436 , n77444 , n77454 );
not ( n77456 , n70253 );
not ( n77457 , n69531 );
not ( n77458 , n77457 );
or ( n77459 , n77456 , n77458 );
nand ( n77460 , n77459 , n77385 );
xor ( n77461 , n77460 , n77450 );
not ( n77462 , n69502 );
not ( n77463 , n77462 );
not ( n77464 , n70432 );
or ( n77465 , n77463 , n77464 );
nand ( n77466 , n77465 , n77395 );
and ( n77467 , n77466 , n77432 );
not ( n77468 , n77466 );
not ( n77469 , n77432 );
and ( n77470 , n77468 , n77469 );
nor ( n77471 , n77467 , n77470 );
not ( n77472 , n69553 );
not ( n77473 , n77472 );
not ( n77474 , n70378 );
or ( n77475 , n77473 , n77474 );
nand ( n77476 , n77475 , n77453 );
xor ( n77477 , n77476 , n77442 );
xnor ( n77478 , n70073 , n70459 );
not ( n77479 , n69967 );
and ( n77480 , n70522 , n77479 );
not ( n77481 , n70522 );
and ( n77482 , n77481 , n69967 );
nor ( n77483 , n77480 , n77482 );
xnor ( n77484 , n70503 , n70053 );
nand ( n77485 , n77478 , n77483 , n77484 );
xor ( n77486 , n69471 , n69451 );
xor ( n77487 , n77486 , n70420 );
nor ( n77488 , n77485 , n77487 );
nand ( n77489 , n77461 , n77471 , n77477 , n77488 );
nor ( n77490 , n77455 , n77489 );
and ( n77491 , n77293 , n77364 , n77421 , n77490 );
not ( n77492 , n70188 );
nor ( n77493 , n77492 , n70863 , n70194 );
not ( n77494 , n77493 );
or ( n77495 , n77491 , n77494 );
nand ( n77496 , n77493 , n70151 );
nand ( n77497 , n77495 , n77496 );
not ( n77498 , n77497 );
or ( n77499 , n77241 , n77498 );
nor ( n77500 , n70560 , n70863 );
nand ( n77501 , n77500 , n77240 );
nor ( n77502 , n77491 , n77501 );
not ( n77503 , n71983 );
nand ( n77504 , n70202 , n70865 , n70139 );
and ( n77505 , n70873 , n77503 , n77504 );
nor ( n77506 , n77505 , n77496 );
nor ( n77507 , n77502 , n77506 );
nand ( n77508 , n77499 , n77507 );
nor ( n77509 , n77239 , n77508 );
and ( n77510 , n77225 , n77234 , n77509 );
not ( n77511 , n71122 );
nor ( n77512 , n71058 , n77511 );
not ( n77513 , n71092 );
nor ( n77514 , n71047 , n77513 );
nor ( n77515 , n77512 , n77514 );
not ( n77516 , n71074 );
nand ( n77517 , n77516 , n69660 );
not ( n77518 , n70225 );
nand ( n77519 , n77518 , n69977 );
and ( n77520 , n77517 , n77519 );
not ( n77521 , n71074 );
nor ( n77522 , n77521 , n69660 );
nor ( n77523 , n77520 , n77522 );
and ( n77524 , n77515 , n77523 );
not ( n77525 , n71092 );
nand ( n77526 , n77525 , n71047 );
or ( n77527 , n77512 , n77526 );
nand ( n77528 , n71058 , n77511 );
nand ( n77529 , n77527 , n77528 );
nor ( n77530 , n77524 , n77529 );
not ( n77531 , n71833 );
not ( n77532 , n72510 );
nor ( n77533 , n77531 , n77532 );
not ( n77534 , n72499 );
nor ( n77535 , n71852 , n77534 );
nor ( n77536 , n77533 , n77535 );
not ( n77537 , n72475 );
nor ( n77538 , n71869 , n77537 );
not ( n77539 , n72485 );
nor ( n77540 , n77539 , n71037 );
nor ( n77541 , n77538 , n77540 );
nand ( n77542 , n77536 , n77541 );
or ( n77543 , n77530 , n77542 );
not ( n77544 , n71869 );
not ( n77545 , n77537 );
or ( n77546 , n77544 , n77545 );
not ( n77547 , n72485 );
nand ( n77548 , n77547 , n71037 );
or ( n77549 , n77538 , n77548 );
nand ( n77550 , n77546 , n77549 );
and ( n77551 , n77550 , n77536 );
nand ( n77552 , n71852 , n77534 );
or ( n77553 , n77533 , n77552 );
nand ( n77554 , n77531 , n77532 );
nand ( n77555 , n77553 , n77554 );
nor ( n77556 , n77551 , n77555 );
nand ( n77557 , n77543 , n77556 );
not ( n77558 , n77557 );
not ( n77559 , n73914 );
not ( n77560 , n73902 );
not ( n77561 , n77560 );
or ( n77562 , n77559 , n77561 );
not ( n77563 , n73912 );
nand ( n77564 , n69947 , n77563 );
nand ( n77565 , n77562 , n77564 );
not ( n77566 , n77565 );
not ( n77567 , n73916 );
nor ( n77568 , n72463 , n77567 );
not ( n77569 , n72626 );
nor ( n77570 , n77569 , n72452 );
nor ( n77571 , n77568 , n77570 );
nand ( n77572 , n77566 , n77571 );
not ( n77573 , n72815 );
nor ( n77574 , n77573 , n71763 );
not ( n77575 , n72534 );
nor ( n77576 , n77575 , n76748 );
nor ( n77577 , n77574 , n77576 );
not ( n77578 , n72544 );
nor ( n77579 , n76781 , n77578 );
not ( n77580 , n72557 );
nor ( n77581 , n71814 , n77580 );
nor ( n77582 , n77579 , n77581 );
nand ( n77583 , n77577 , n77582 );
nor ( n77584 , n77572 , n77583 );
not ( n77585 , n77584 );
or ( n77586 , n77558 , n77585 );
not ( n77587 , n77572 );
nand ( n77588 , n76781 , n77578 );
nand ( n77589 , n71814 , n77580 );
and ( n77590 , n77588 , n77589 );
nor ( n77591 , n77590 , n77579 );
not ( n77592 , n77591 );
not ( n77593 , n77577 );
or ( n77594 , n77592 , n77593 );
not ( n77595 , n77574 );
not ( n77596 , n76748 );
nor ( n77597 , n77596 , n72534 );
and ( n77598 , n77595 , n77597 );
not ( n77599 , n71763 );
nor ( n77600 , n77599 , n72815 );
nor ( n77601 , n77598 , n77600 );
nand ( n77602 , n77594 , n77601 );
and ( n77603 , n77587 , n77602 );
not ( n77604 , n72463 );
not ( n77605 , n77604 );
not ( n77606 , n73916 );
and ( n77607 , n77605 , n77606 );
not ( n77608 , n77568 );
not ( n77609 , n72452 );
nor ( n77610 , n77609 , n72626 );
and ( n77611 , n77608 , n77610 );
nor ( n77612 , n77607 , n77611 );
or ( n77613 , n77612 , n77565 );
not ( n77614 , n73902 );
nor ( n77615 , n77614 , n73914 );
and ( n77616 , n77564 , n77615 );
nor ( n77617 , n69947 , n77563 );
nor ( n77618 , n77616 , n77617 );
nand ( n77619 , n77613 , n77618 );
nor ( n77620 , n77603 , n77619 );
nand ( n77621 , n77586 , n77620 );
not ( n77622 , n76395 );
nand ( n77623 , n77622 , n70238 );
not ( n77624 , n69981 );
nand ( n77625 , n77624 , n70327 );
nand ( n77626 , n77623 , n77625 );
not ( n77627 , n70098 );
nand ( n77628 , n77627 , n70296 );
not ( n77629 , n69990 );
nand ( n77630 , n77629 , n70308 );
nand ( n77631 , n77628 , n77630 );
nor ( n77632 , n77626 , n77631 );
not ( n77633 , n70273 );
nor ( n77634 , n77633 , n76513 );
not ( n77635 , n70253 );
nor ( n77636 , n77635 , n70013 );
nor ( n77637 , n77634 , n77636 );
not ( n77638 , n77637 );
not ( n77639 , n70378 );
not ( n77640 , n70082 );
not ( n77641 , n77640 );
or ( n77642 , n77639 , n77641 );
not ( n77643 , n70263 );
nor ( n77644 , n77643 , n70007 );
not ( n77645 , n77644 );
nand ( n77646 , n77642 , n77645 );
nor ( n77647 , n77638 , n77646 );
not ( n77648 , n70388 );
nor ( n77649 , n77648 , n70090 );
not ( n77650 , n70477 );
nor ( n77651 , n77650 , n70031 );
nor ( n77652 , n77649 , n77651 );
not ( n77653 , n70432 );
nor ( n77654 , n70024 , n77653 );
not ( n77655 , n72302 );
nor ( n77656 , n77655 , n70038 );
nor ( n77657 , n77654 , n77656 );
not ( n77658 , n70040 );
nand ( n77659 , n77658 , n70420 );
not ( n77660 , n70522 );
nor ( n77661 , n77660 , n69967 );
not ( n77662 , n70053 );
and ( n77663 , n77662 , n70503 );
or ( n77664 , n77661 , n77663 );
or ( n77665 , n77662 , n70503 );
nand ( n77666 , n77664 , n77665 );
not ( n77667 , n70073 );
nand ( n77668 , n77667 , n70459 );
nand ( n77669 , n77659 , n77666 , n77668 );
not ( n77670 , n70073 );
nor ( n77671 , n77670 , n70459 );
nand ( n77672 , n77659 , n77671 );
not ( n77673 , n70420 );
nand ( n77674 , n77673 , n70040 );
nand ( n77675 , n77669 , n77672 , n77674 );
nand ( n77676 , n77652 , n77657 , n77675 );
not ( n77677 , n72302 );
nand ( n77678 , n77677 , n70038 );
or ( n77679 , n77654 , n77678 );
nand ( n77680 , n70024 , n77653 );
nand ( n77681 , n77679 , n77680 );
nand ( n77682 , n77652 , n77681 );
not ( n77683 , n77649 );
not ( n77684 , n70031 );
nor ( n77685 , n77684 , n70477 );
and ( n77686 , n77683 , n77685 );
not ( n77687 , n70090 );
nor ( n77688 , n77687 , n70388 );
nor ( n77689 , n77686 , n77688 );
nand ( n77690 , n77676 , n77682 , n77689 );
nand ( n77691 , n77632 , n77647 , n77690 );
not ( n77692 , n77637 );
not ( n77693 , n70378 );
nand ( n77694 , n77693 , n70082 );
or ( n77695 , n77644 , n77694 );
not ( n77696 , n70007 );
or ( n77697 , n77696 , n70263 );
nand ( n77698 , n77695 , n77697 );
not ( n77699 , n77698 );
or ( n77700 , n77692 , n77699 );
not ( n77701 , n77634 );
not ( n77702 , n70013 );
nor ( n77703 , n77702 , n70253 );
and ( n77704 , n77701 , n77703 );
not ( n77705 , n76513 );
nor ( n77706 , n77705 , n70273 );
nor ( n77707 , n77704 , n77706 );
nand ( n77708 , n77700 , n77707 );
nand ( n77709 , n77708 , n77632 );
not ( n77710 , n77628 );
not ( n77711 , n70308 );
nand ( n77712 , n77711 , n69990 );
or ( n77713 , n77710 , n77712 );
not ( n77714 , n70296 );
nand ( n77715 , n77714 , n70098 );
nand ( n77716 , n77713 , n77715 );
not ( n77717 , n77626 );
and ( n77718 , n77716 , n77717 );
not ( n77719 , n77623 );
not ( n77720 , n70327 );
nand ( n77721 , n77720 , n69981 );
or ( n77722 , n77719 , n77721 );
not ( n77723 , n70238 );
nand ( n77724 , n77723 , n76395 );
nand ( n77725 , n77722 , n77724 );
nor ( n77726 , n77718 , n77725 );
nand ( n77727 , n77691 , n77709 , n77726 );
not ( n77728 , n70225 );
nor ( n77729 , n77728 , n69977 );
nor ( n77730 , n77522 , n77729 );
nand ( n77731 , n77515 , n77730 );
nor ( n77732 , n77542 , n77731 );
not ( n77733 , n77583 );
and ( n77734 , n77587 , n77727 , n77732 , n77733 );
nor ( n77735 , n77621 , n77734 );
or ( n77736 , n77735 , n70873 );
not ( n77737 , n77504 );
nand ( n77738 , n77491 , n77737 );
nand ( n77739 , n77736 , n77738 );
not ( n77740 , n77739 );
nand ( n77741 , n77735 , n71983 );
nand ( n77742 , n77740 , n77741 );
nand ( n77743 , n77742 , n77493 );
nand ( n77744 , n77742 , n77500 );
and ( n77745 , n77229 , n77737 );
not ( n77746 , n77223 );
and ( n77747 , n77746 , n77240 );
nor ( n77748 , n77745 , n77747 );
and ( n77749 , n77510 , n77743 , n77744 , n77748 );
or ( n77750 , n76991 , n77749 );
nand ( n77751 , n77510 , n77743 , n77744 );
not ( n77752 , n77240 );
not ( n77753 , n77229 );
or ( n77754 , n77752 , n77753 );
or ( n77755 , n77223 , n77504 );
nand ( n77756 , n77754 , n77755 );
nor ( n77757 , n77751 , n77756 );
or ( n77758 , n77757 , n76990 );
not ( n77759 , n75275 );
nor ( n77760 , n70141 , n70208 , n77759 );
not ( n77761 , n77760 );
nand ( n77762 , n70147 , n70860 );
nand ( n77763 , n77761 , n77762 , n70151 );
nand ( n77764 , n77750 , n77758 , n77763 );
buf ( n77765 , n77764 );
buf ( n77766 , 1'b0 );
not ( n77767 , n68635 );
not ( n77768 , n77767 );
buf ( n77769 , n77768 );
buf ( n77770 , n68634 );
buf ( n77771 , n71724 );
buf ( n77772 , 1'b0 );
not ( n77773 , n77767 );
buf ( n77774 , n77773 );
buf ( n77775 , n68634 );
nand ( n77776 , n70188 , n70194 );
and ( n77777 , n70136 , n77776 );
nor ( n77778 , n77777 , n70147 );
not ( n77779 , n70222 );
or ( n77780 , n77778 , n77779 );
nand ( n77781 , n77780 , n70860 );
buf ( n77782 , n77781 );
endmodule
|
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_dag3_lpm_mod(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
c top_c(clock, c_in, d_in, temp_c);
d top_d(clock, c_in, d_in, temp_d);
assign out0 = temp_a + temp_b;
assign out1 = temp_c - temp_d;
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire [`BITS-1:0] temp;
d mya_d(clock, a_in[0], b_in[0], temp[0]);
d mya_d2(clock, a_in[1], b_in[0], temp[1]);
always @(posedge clock)
begin
out <= a_in + b_in + temp;
end
endmodule
/*---------------------------------------------------------*/
module b(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire [`BITS-1:0] temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c(clock, a_in[0], b_in[0], temp2[0]);
c myb_c2(clock, a_in[0], b_in[1], temp2[1]);
always @(posedge clock)
begin
temp <= a_in + b_in - temp2;
out <= a_in + temp;
end
endmodule
/*---------------------------------------------------------*/
module c(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
wire out1;
wire temp;
wire temp2;
d myc_d(clock, c_in, d_in, temp2);
assign out1 = temp + d_in;
assign temp = c_in + temp2;
endmodule
/*---------------------------------------------------------*/
module d(clock,
c_in,
d_in,
out1);
// SIGNAL DECLARATIONS
input clock;
input c_in;
input d_in;
output out1;
reg out1;
reg temp;
always @(posedge clock)
begin
out1 <= temp - d_in;
temp <= c_in - d_in;
end
endmodule
|
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs ZGcd ZDivTrunc ZDivFloor.
(** * Least Common Multiple *)
(** Unlike other functions around, we will define lcm below instead of
axiomatizing it. Indeed, there is no "prior art" about lcm in the
standard library to be compliant with, and the generic definition
of lcm via gcd is quite reasonable.
By the way, we also state here some combined properties of div/mod
and quot/rem and gcd.
*)
Module Type ZLcmProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B)
(Import D : ZDivProp A B C)
(Import E : ZQuotProp A B C)
(Import F : ZGcdProp A B C).
(** The two notions of division are equal on non-negative numbers *)
Lemma quot_div_nonneg : forall a b, 0<=a -> 0<b -> a÷b == a/b.
Proof.
intros a b **. apply div_unique_pos with (a rem b).
now apply rem_bound_pos.
apply quot_rem. order.
Qed.
Lemma rem_mod_nonneg : forall a b, 0<=a -> 0<b -> a rem b == a mod b.
Proof.
intros a b **. apply mod_unique_pos with (a÷b).
now apply rem_bound_pos.
apply quot_rem. order.
Qed.
(** We can use the sign rule to have an relation between divisions. *)
Lemma quot_div : forall a b, b~=0 ->
a÷b == (sgn a)*(sgn b)*(abs a / abs b).
Proof.
assert (AUX : forall a b, 0<b -> a÷b == (sgn a)*(sgn b)*(abs a / abs b)).
intros a b Hb. rewrite (sgn_pos b), (abs_eq b), mul_1_r by order.
destruct (lt_trichotomy 0 a) as [Ha|[Ha|Ha]].
rewrite sgn_pos, abs_eq, mul_1_l, quot_div_nonneg; order.
rewrite <- Ha, abs_0, sgn_0, quot_0_l, div_0_l, mul_0_l; order.
rewrite sgn_neg, abs_neq, mul_opp_l, mul_1_l, eq_opp_r, <-quot_opp_l
by order.
apply quot_div_nonneg; trivial. apply opp_nonneg_nonpos; order.
(* main *)
intros a b Hb.
apply neg_pos_cases in Hb. destruct Hb as [Hb|Hb]; [|now apply AUX].
rewrite <- (opp_involutive b) at 1. rewrite quot_opp_r.
rewrite AUX, abs_opp, sgn_opp, mul_opp_r, mul_opp_l, opp_involutive.
reflexivity.
now apply opp_pos_neg.
rewrite eq_opp_l, opp_0; order.
Qed.
Lemma rem_mod : forall a b, b~=0 ->
a rem b == (sgn a) * ((abs a) mod (abs b)).
Proof.
intros a b Hb.
rewrite <- rem_abs_r by trivial.
assert (Hb' := proj2 (abs_pos b) Hb).
destruct (lt_trichotomy 0 a) as [Ha|[Ha|Ha]].
rewrite (abs_eq a), sgn_pos, mul_1_l, rem_mod_nonneg; order.
rewrite <- Ha, abs_0, sgn_0, mod_0_l, rem_0_l, mul_0_l; order.
rewrite sgn_neg, (abs_neq a), mul_opp_l, mul_1_l, eq_opp_r, <-rem_opp_l
by order.
apply rem_mod_nonneg; trivial. apply opp_nonneg_nonpos; order.
Qed.
(** Modulo and remainder are null at the same place,
and this correspond to the divisibility relation. *)
Lemma mod_divide : forall a b, b~=0 -> (a mod b == 0 <-> (b|a)).
Proof.
intros a b Hb. split.
intros Hab. exists (a/b). rewrite mul_comm.
rewrite (div_mod a b Hb) at 1. rewrite Hab; now nzsimpl.
intros (c,Hc). rewrite Hc. now apply mod_mul.
Qed.
Lemma rem_divide : forall a b, b~=0 -> (a rem b == 0 <-> (b|a)).
Proof.
intros a b Hb. split.
intros Hab. exists (a÷b). rewrite mul_comm.
rewrite (quot_rem a b Hb) at 1. rewrite Hab; now nzsimpl.
intros (c,Hc). rewrite Hc. now apply rem_mul.
Qed.
Lemma rem_mod_eq_0 : forall a b, b~=0 -> (a rem b == 0 <-> a mod b == 0).
Proof.
intros a b Hb. now rewrite mod_divide, rem_divide.
Qed.
(** When division is exact, div and quot agree *)
Lemma quot_div_exact : forall a b, b~=0 -> (b|a) -> a÷b == a/b.
Proof.
intros a b Hb H.
apply mul_cancel_l with b; trivial.
assert (H':=H).
apply rem_divide, quot_exact in H; trivial.
apply mod_divide, div_exact in H'; trivial.
now rewrite <-H,<-H'.
Qed.
Lemma divide_div_mul_exact : forall a b c, b~=0 -> (b|a) ->
(c*a)/b == c*(a/b).
Proof.
intros a b c Hb H.
apply mul_cancel_l with b; trivial.
rewrite mul_assoc, mul_shuffle0.
assert (H':=H). apply mod_divide, div_exact in H'; trivial.
rewrite <- H', (mul_comm a c).
symmetry. apply div_exact; trivial.
apply mod_divide; trivial.
now apply divide_mul_r.
Qed.
Lemma divide_quot_mul_exact : forall a b c, b~=0 -> (b|a) ->
(c*a)÷b == c*(a÷b).
Proof.
intros a b c Hb H.
rewrite 2 quot_div_exact; trivial.
apply divide_div_mul_exact; trivial.
now apply divide_mul_r.
Qed.
(** Gcd of divided elements, for exact divisions *)
Lemma gcd_div_factor : forall a b c, 0<c -> (c|a) -> (c|b) ->
gcd (a/c) (b/c) == (gcd a b)/c.
Proof.
intros a b c Hc Ha Hb.
apply mul_cancel_l with c; try order.
assert (H:=gcd_greatest _ _ _ Ha Hb).
apply mod_divide, div_exact in H; try order.
rewrite <- H.
rewrite <- gcd_mul_mono_l_nonneg; try order.
f_equiv; symmetry; apply div_exact; try order;
apply mod_divide; trivial; try order.
Qed.
Lemma gcd_quot_factor : forall a b c, 0<c -> (c|a) -> (c|b) ->
gcd (a÷c) (b÷c) == (gcd a b)÷c.
Proof.
intros a b c Hc Ha Hb. rewrite !quot_div_exact; trivial; try order.
now apply gcd_div_factor. now apply gcd_greatest.
Qed.
Lemma gcd_div_gcd : forall a b g, g~=0 -> g == gcd a b ->
gcd (a/g) (b/g) == 1.
Proof.
intros a b g NZ EQ. rewrite gcd_div_factor.
now rewrite <- EQ, div_same.
generalize (gcd_nonneg a b); order.
rewrite EQ; apply gcd_divide_l.
rewrite EQ; apply gcd_divide_r.
Qed.
Lemma gcd_quot_gcd : forall a b g, g~=0 -> g == gcd a b ->
gcd (a÷g) (b÷g) == 1.
Proof.
intros a b g NZ EQ. rewrite !quot_div_exact; trivial.
now apply gcd_div_gcd.
rewrite EQ; apply gcd_divide_r.
rewrite EQ; apply gcd_divide_l.
Qed.
(** The following equality is crucial for Euclid algorithm *)
Lemma gcd_mod : forall a b, b~=0 -> gcd (a mod b) b == gcd b a.
Proof.
intros a b Hb. rewrite mod_eq; trivial.
rewrite <- add_opp_r, mul_comm, <- mul_opp_l.
rewrite (gcd_comm _ b).
apply gcd_add_mult_diag_r.
Qed.
Lemma gcd_rem : forall a b, b~=0 -> gcd (a rem b) b == gcd b a.
Proof.
intros a b Hb. rewrite rem_eq; trivial.
rewrite <- add_opp_r, mul_comm, <- mul_opp_l.
rewrite (gcd_comm _ b).
apply gcd_add_mult_diag_r.
Qed.
(** We now define lcm thanks to gcd:
lcm a b = a * (b / gcd a b)
= (a / gcd a b) * b
= (a*b) / gcd a b
We had an abs in order to have an always-nonnegative lcm,
in the spirit of gcd. Nota: [lcm 0 0] should be 0, which
isn't guarantee with the third equation above.
*)
Definition lcm a b := abs (a*(b/gcd a b)).
#[global]
Instance lcm_wd : Proper (eq==>eq==>eq) lcm.
Proof. unfold lcm. solve_proper. Qed.
Lemma lcm_equiv1 : forall a b, gcd a b ~= 0 ->
a * (b / gcd a b) == (a*b)/gcd a b.
Proof.
intros a b H. rewrite divide_div_mul_exact; try easy. apply gcd_divide_r.
Qed.
Lemma lcm_equiv2 : forall a b, gcd a b ~= 0 ->
(a / gcd a b) * b == (a*b)/gcd a b.
Proof.
intros a b H. rewrite 2 (mul_comm _ b).
rewrite divide_div_mul_exact; try easy. apply gcd_divide_l.
Qed.
Lemma gcd_div_swap : forall a b,
(a / gcd a b) * b == a * (b / gcd a b).
Proof.
intros a b. destruct (eq_decidable (gcd a b) 0) as [EQ|NEQ].
apply gcd_eq_0 in EQ. destruct EQ as (EQ,EQ'). rewrite EQ, EQ'. now nzsimpl.
now rewrite lcm_equiv1, <-lcm_equiv2.
Qed.
Lemma divide_lcm_l : forall a b, (a | lcm a b).
Proof.
unfold lcm. intros a b. apply divide_abs_r, divide_factor_l.
Qed.
Lemma divide_lcm_r : forall a b, (b | lcm a b).
Proof.
unfold lcm. intros a b. apply divide_abs_r. rewrite <- gcd_div_swap.
apply divide_factor_r.
Qed.
Lemma divide_div : forall a b c, a~=0 -> (a|b) -> (b|c) -> (b/a|c/a).
Proof.
intros a b c Ha Hb (c',Hc). exists c'.
now rewrite <- divide_div_mul_exact, <- Hc.
Qed.
Lemma lcm_least : forall a b c,
(a | c) -> (b | c) -> (lcm a b | c).
Proof.
intros a b c Ha Hb. unfold lcm. apply divide_abs_l.
destruct (eq_decidable (gcd a b) 0) as [EQ|NEQ].
apply gcd_eq_0 in EQ. destruct EQ as (EQ,EQ'). rewrite EQ in *. now nzsimpl.
assert (Ga := gcd_divide_l a b).
assert (Gb := gcd_divide_r a b).
set (g:=gcd a b) in *.
assert (Ha' := divide_div g a c NEQ Ga Ha).
assert (Hb' := divide_div g b c NEQ Gb Hb).
destruct Ha' as (a',Ha'). rewrite Ha', mul_comm in Hb'.
apply gauss in Hb'; [|apply gcd_div_gcd; unfold g; trivial using gcd_comm].
destruct Hb' as (b',Hb').
exists b'.
rewrite mul_shuffle3, <- Hb'.
rewrite (proj2 (div_exact c g NEQ)).
rewrite Ha', mul_shuffle3, (mul_comm a a'). f_equiv.
symmetry. apply div_exact; trivial.
apply mod_divide; trivial.
apply mod_divide; trivial. transitivity a; trivial.
Qed.
Lemma lcm_nonneg : forall a b, 0 <= lcm a b.
Proof.
intros a b. unfold lcm. apply abs_nonneg.
Qed.
Lemma lcm_comm : forall a b, lcm a b == lcm b a.
Proof.
intros a b. unfold lcm. rewrite (gcd_comm b), (mul_comm b).
now rewrite <- gcd_div_swap.
Qed.
Lemma lcm_divide_iff : forall n m p,
(lcm n m | p) <-> (n | p) /\ (m | p).
Proof.
intros n m p. split. split.
transitivity (lcm n m); trivial using divide_lcm_l.
transitivity (lcm n m); trivial using divide_lcm_r.
intros (H,H'). now apply lcm_least.
Qed.
Lemma lcm_unique : forall n m p,
0<=p -> (n|p) -> (m|p) ->
(forall q, (n|q) -> (m|q) -> (p|q)) ->
lcm n m == p.
Proof.
intros n m p Hp Hn Hm H.
apply divide_antisym_nonneg; trivial. apply lcm_nonneg.
now apply lcm_least.
apply H. apply divide_lcm_l. apply divide_lcm_r.
Qed.
Lemma lcm_unique_alt : forall n m p, 0<=p ->
(forall q, (p|q) <-> (n|q) /\ (m|q)) ->
lcm n m == p.
Proof.
intros n m p Hp H.
apply lcm_unique; trivial.
apply H, divide_refl.
apply H, divide_refl.
intros. apply H. now split.
Qed.
Lemma lcm_assoc : forall n m p, lcm n (lcm m p) == lcm (lcm n m) p.
Proof.
intros. apply lcm_unique_alt; try apply lcm_nonneg.
intros. now rewrite !lcm_divide_iff, and_assoc.
Qed.
Lemma lcm_0_l : forall n, lcm 0 n == 0.
Proof.
intros. apply lcm_unique; trivial. order.
apply divide_refl.
apply divide_0_r.
Qed.
Lemma lcm_0_r : forall n, lcm n 0 == 0.
Proof.
intros. now rewrite lcm_comm, lcm_0_l.
Qed.
Lemma lcm_1_l_nonneg : forall n, 0<=n -> lcm 1 n == n.
Proof.
intros. apply lcm_unique; trivial using divide_1_l, le_0_1, divide_refl.
Qed.
Lemma lcm_1_r_nonneg : forall n, 0<=n -> lcm n 1 == n.
Proof.
intros. now rewrite lcm_comm, lcm_1_l_nonneg.
Qed.
Lemma lcm_diag_nonneg : forall n, 0<=n -> lcm n n == n.
Proof.
intros. apply lcm_unique; trivial using divide_refl.
Qed.
Lemma lcm_eq_0 : forall n m, lcm n m == 0 <-> n == 0 \/ m == 0.
Proof.
intros. split.
intros EQ.
apply eq_mul_0.
apply divide_0_l. rewrite <- EQ. apply lcm_least.
apply divide_factor_l. apply divide_factor_r.
destruct 1 as [EQ|EQ]; rewrite EQ. apply lcm_0_l. apply lcm_0_r.
Qed.
Lemma divide_lcm_eq_r : forall n m, 0<=m -> (n|m) -> lcm n m == m.
Proof.
intros n m Hm H. apply lcm_unique_alt; trivial.
intros q. split. split; trivial. now transitivity m.
now destruct 1.
Qed.
Lemma divide_lcm_iff : forall n m, 0<=m -> ((n|m) <-> lcm n m == m).
Proof.
intros n m Hn. split. now apply divide_lcm_eq_r.
intros EQ. rewrite <- EQ. apply divide_lcm_l.
Qed.
Lemma lcm_opp_l : forall n m, lcm (-n) m == lcm n m.
Proof.
intros. apply lcm_unique_alt; try apply lcm_nonneg.
intros. rewrite divide_opp_l. apply lcm_divide_iff.
Qed.
Lemma lcm_opp_r : forall n m, lcm n (-m) == lcm n m.
Proof.
intros. now rewrite lcm_comm, lcm_opp_l, lcm_comm.
Qed.
Lemma lcm_abs_l : forall n m, lcm (abs n) m == lcm n m.
Proof.
intros n m. destruct (abs_eq_or_opp n) as [H|H]; rewrite H.
easy. apply lcm_opp_l.
Qed.
Lemma lcm_abs_r : forall n m, lcm n (abs m) == lcm n m.
Proof.
intros. now rewrite lcm_comm, lcm_abs_l, lcm_comm.
Qed.
Lemma lcm_1_l : forall n, lcm 1 n == abs n.
Proof.
intros. rewrite <- lcm_abs_r. apply lcm_1_l_nonneg, abs_nonneg.
Qed.
Lemma lcm_1_r : forall n, lcm n 1 == abs n.
Proof.
intros. now rewrite lcm_comm, lcm_1_l.
Qed.
Lemma lcm_diag : forall n, lcm n n == abs n.
Proof.
intros. rewrite <- lcm_abs_l, <- lcm_abs_r.
apply lcm_diag_nonneg, abs_nonneg.
Qed.
Lemma lcm_mul_mono_l :
forall n m p, lcm (p * n) (p * m) == abs p * lcm n m.
Proof.
intros n m p.
destruct (eq_decidable p 0) as [Hp|Hp].
rewrite Hp. nzsimpl. rewrite lcm_0_l, abs_0. now nzsimpl.
destruct (eq_decidable (gcd n m) 0) as [Hg|Hg].
apply gcd_eq_0 in Hg. destruct Hg as (Hn,Hm); rewrite Hn, Hm.
nzsimpl. rewrite lcm_0_l. now nzsimpl.
unfold lcm.
rewrite gcd_mul_mono_l.
rewrite !abs_mul, mul_assoc. f_equiv.
rewrite <- (abs_sgn p) at 1. rewrite <- mul_assoc.
rewrite div_mul_cancel_l; trivial.
rewrite divide_div_mul_exact; trivial. rewrite abs_mul.
rewrite <- (sgn_abs (sgn p)), sgn_sgn.
destruct (sgn_spec p) as [(_,EQ)|[(EQ,_)|(_,EQ)]].
rewrite EQ. now nzsimpl. order.
rewrite EQ. rewrite mul_opp_l, mul_opp_r, opp_involutive. now nzsimpl.
apply gcd_divide_r.
contradict Hp. now apply abs_0_iff.
Qed.
Lemma lcm_mul_mono_l_nonneg :
forall n m p, 0<=p -> lcm (p*n) (p*m) == p * lcm n m.
Proof.
intros n m p ?. rewrite <- (abs_eq p) at 3; trivial. apply lcm_mul_mono_l.
Qed.
Lemma lcm_mul_mono_r :
forall n m p, lcm (n * p) (m * p) == lcm n m * abs p.
Proof.
intros n m p. now rewrite !(mul_comm _ p), lcm_mul_mono_l, mul_comm.
Qed.
Lemma lcm_mul_mono_r_nonneg :
forall n m p, 0<=p -> lcm (n*p) (m*p) == lcm n m * p.
Proof.
intros n m p ?. rewrite <- (abs_eq p) at 3; trivial. apply lcm_mul_mono_r.
Qed.
Lemma gcd_1_lcm_mul : forall n m, n~=0 -> m~=0 ->
(gcd n m == 1 <-> lcm n m == abs (n*m)).
Proof.
intros n m Hn Hm. split; intros H.
unfold lcm. rewrite H. now rewrite div_1_r.
unfold lcm in *.
rewrite !abs_mul in H. apply mul_cancel_l in H; [|now rewrite abs_0_iff].
assert (H' := gcd_divide_r n m).
assert (Hg : gcd n m ~= 0) by (red; rewrite gcd_eq_0; destruct 1; order).
apply mod_divide in H'; trivial. apply div_exact in H'; trivial.
assert (m / gcd n m ~=0) by (contradict Hm; rewrite H', Hm; now nzsimpl).
rewrite <- (mul_1_l (abs (_/_))) in H.
rewrite H' in H at 3. rewrite abs_mul in H.
apply mul_cancel_r in H; [|now rewrite abs_0_iff].
rewrite abs_eq in H. order. apply gcd_nonneg.
Qed.
End ZLcmProp.
|
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Register Slice
// Register selected channels on the forward and/or reverse signal paths.
// 5-channel memory-mapped AXI4 interfaces.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_register_slice
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
parameter integer C_REG_CONFIG_AW = 0,
parameter integer C_REG_CONFIG_W = 0,
parameter integer C_REG_CONFIG_B = 0,
parameter integer C_REG_CONFIG_AR = 0,
parameter integer C_REG_CONFIG_R = 0
)
(
// System Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire reset;
localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
`include "axi_infrastructure_v1_1_header.vh"
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
assign reset = ~aresetn;
axi_infrastructure_v1_1_axi2vector #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_axi2vector_0 (
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awuser ( s_axi_awuser ) ,
.s_axi_awregion ( s_axi_awregion ) ,
.s_axi_wid ( s_axi_wid ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( s_axi_wuser ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( s_axi_buser ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_aruser ( s_axi_aruser ) ,
.s_axi_arregion ( s_axi_arregion ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( s_axi_ruser ) ,
.s_awpayload ( s_awpayload ) ,
.s_wpayload ( s_wpayload ) ,
.s_bpayload ( s_bpayload ) ,
.s_arpayload ( s_arpayload ) ,
.s_rpayload ( s_rpayload )
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AW )
)
aw_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_awpayload),
.S_VALID(s_axi_awvalid),
.S_READY(s_axi_awready),
// Master side
.M_PAYLOAD_DATA(m_awpayload),
.M_VALID(m_axi_awvalid),
.M_READY(m_axi_awready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_W )
)
w_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_wpayload),
.S_VALID(s_axi_wvalid),
.S_READY(s_axi_wready),
// Master side
.M_PAYLOAD_DATA(m_wpayload),
.M_VALID(m_axi_wvalid),
.M_READY(m_axi_wready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_B )
)
b_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_bpayload),
.S_VALID(m_axi_bvalid),
.S_READY(m_axi_bready),
// Master side
.M_PAYLOAD_DATA(s_bpayload),
.M_VALID(s_axi_bvalid),
.M_READY(s_axi_bready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AR )
)
ar_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_arpayload),
.S_VALID(s_axi_arvalid),
.S_READY(s_axi_arready),
// Master side
.M_PAYLOAD_DATA(m_arpayload),
.M_VALID(m_axi_arvalid),
.M_READY(m_axi_arready)
);
axi_register_slice_v2_1_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_R )
)
r_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_rpayload),
.S_VALID(m_axi_rvalid),
.S_READY(m_axi_rready),
// Master side
.M_PAYLOAD_DATA(s_rpayload),
.M_VALID(s_axi_rvalid),
.M_READY(s_axi_rready)
);
axi_infrastructure_v1_1_vector2axi #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_vector2axi_0 (
.m_awpayload ( m_awpayload ) ,
.m_wpayload ( m_wpayload ) ,
.m_bpayload ( m_bpayload ) ,
.m_arpayload ( m_arpayload ) ,
.m_rpayload ( m_rpayload ) ,
.m_axi_awid ( m_axi_awid ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awuser ( m_axi_awuser ) ,
.m_axi_awregion ( m_axi_awregion ) ,
.m_axi_wid ( m_axi_wid ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wuser ( m_axi_wuser ) ,
.m_axi_bid ( m_axi_bid ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( m_axi_buser ) ,
.m_axi_arid ( m_axi_arid ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_aruser ( m_axi_aruser ) ,
.m_axi_arregion ( m_axi_arregion ) ,
.m_axi_rid ( m_axi_rid ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_ruser ( m_axi_ruser )
);
endmodule // axi_register_slice
|
module de10_lite(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
output [ 7:0 ] HEX0,
output [ 7:0 ] HEX1,
output [ 7:0 ] HEX2,
output [ 7:0 ] HEX3,
output [ 7:0 ] HEX4,
output [ 7:0 ] HEX5,
input [ 1:0 ] KEY,
output [ 9:0 ] LEDR,
input [ 9:0 ] SW,
inout [ 35:0 ] GPIO
);
// wires & inputs
wire clk;
wire clkIn = MAX10_CLK1_50;
wire rst_n = KEY[0];
wire clkEnable = SW [9] | ~KEY[1];
wire [ 3:0 ] clkDevide = SW [8:5];
wire [ 4:0 ] regAddr = SW [4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clk ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign LEDR[0] = clk;
assign LEDR[9:1] = regData[8:0];
wire [ 31:0 ] h7segment = regData;
assign HEX0 [7] = 1'b1;
assign HEX1 [7] = 1'b1;
assign HEX2 [7] = 1'b1;
assign HEX3 [7] = 1'b1;
assign HEX4 [7] = 1'b1;
assign HEX5 [7] = 1'b1;
sm_hex_display digit_5 ( h7segment [23:20] , HEX5 [6:0] );
sm_hex_display digit_4 ( h7segment [19:16] , HEX4 [6:0] );
sm_hex_display digit_3 ( h7segment [15:12] , HEX3 [6:0] );
sm_hex_display digit_2 ( h7segment [11: 8] , HEX2 [6:0] );
sm_hex_display digit_1 ( h7segment [ 7: 4] , HEX1 [6:0] );
sm_hex_display digit_0 ( h7segment [ 3: 0] , HEX0 [6:0] );
endmodule
|
module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
wire [5:0] offset = idx << 2;
assign slice_up = data[offset +: 4];
assign slice_down = data[offset + 3 -: 4];
endmodule
module partsel_test002 (
input clk, rst,
input [7:0] a,
input [0:7] b,
input [1:0] s,
output [7:0] x1, x2, x3,
output [0:7] x4, x5, x6,
output [7:0] y1, y2, y3,
output [0:7] y4, y5, y6,
output [7:0] z1, z2, z3,
output [0:7] z4, z5, z6,
output [7:0] w1, w2, w3,
output [0:7] w4, w5, w6,
output [7:0] p1, p2, p3, p4, p5, p6,
output [0:7] q1, q2, q3, q4, q5, q6,
output reg [7:0] r1,
output reg [0:7] r2
);
assign x1 = a, x2 = a + b, x3 = b;
assign x4 = a, x5 = a + b, x6 = b;
assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];
assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];
assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];
assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];
assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];
assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];
assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];
assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];
always @(posedge clk) begin
if (rst) begin
{ r1, r2 } = 16'h1337 ^ {a, b};
end else begin
case (s)
0: begin
r1[3:0] <= r2[0:3] ^ x1;
r2[4:7] <= r1[7:4] ^ x4;
end
1: begin
r1[2 +: 3] <= r2[5 -: 3] + x1;
r2[3 +: 3] <= r1[6 -: 3] + x4;
end
2: begin
r1[6 -: 3] <= r2[3 +: 3] - x1;
r2[7 -: 3] <= r1[4 +: 3] - x4;
end
3: begin
r1 <= r2;
r2 <= r1;
end
endcase
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Register Interface Unit Selection Block
// /___/ /\ Filename : RIU_OR.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RIU_OR #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter real SIM_VERSION = 2.0
)(
output [15:0] RIU_RD_DATA,
output RIU_RD_VALID,
input [15:0] RIU_RD_DATA_LOW,
input [15:0] RIU_RD_DATA_UPP,
input RIU_RD_VALID_LOW,
input RIU_RD_VALID_UPP
);
// define constants
localparam MODULE_NAME = "RIU_OR";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam real SIM_VERSION_REG = SIM_VERSION;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
wire RIU_RD_VALID_out;
wire [15:0] RIU_RD_DATA_out;
wire RIU_RD_VALID_delay;
wire [15:0] RIU_RD_DATA_delay;
wire RIU_RD_VALID_LOW_in;
wire RIU_RD_VALID_UPP_in;
wire [15:0] RIU_RD_DATA_LOW_in;
wire [15:0] RIU_RD_DATA_UPP_in;
wire RIU_RD_VALID_LOW_delay;
wire RIU_RD_VALID_UPP_delay;
wire [15:0] RIU_RD_DATA_LOW_delay;
wire [15:0] RIU_RD_DATA_UPP_delay;
assign #(out_delay) RIU_RD_DATA = RIU_RD_DATA_delay;
assign #(out_delay) RIU_RD_VALID = RIU_RD_VALID_delay;
// inputs with no timing checks
assign #(in_delay) RIU_RD_DATA_LOW_delay = RIU_RD_DATA_LOW;
assign #(in_delay) RIU_RD_DATA_UPP_delay = RIU_RD_DATA_UPP;
assign #(in_delay) RIU_RD_VALID_LOW_delay = RIU_RD_VALID_LOW;
assign #(in_delay) RIU_RD_VALID_UPP_delay = RIU_RD_VALID_UPP;
assign RIU_RD_DATA_delay = RIU_RD_DATA_out;
assign RIU_RD_VALID_delay = RIU_RD_VALID_out;
assign RIU_RD_DATA_LOW_in = RIU_RD_DATA_LOW_delay;
assign RIU_RD_DATA_UPP_in = RIU_RD_DATA_UPP_delay;
assign RIU_RD_VALID_LOW_in = RIU_RD_VALID_LOW_delay;
assign RIU_RD_VALID_UPP_in = RIU_RD_VALID_UPP_delay;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
assign RIU_RD_DATA_out = RIU_RD_DATA_UPP_in | RIU_RD_DATA_LOW_in;
assign RIU_RD_VALID_out = RIU_RD_VALID_UPP_in & RIU_RD_VALID_LOW_in;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-101] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
specify
(RIU_RD_DATA_LOW *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_DATA_UPP *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_VALID_LOW => RIU_RD_VALID) = (0:0:0, 0:0:0);
(RIU_RD_VALID_UPP => RIU_RD_VALID) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//------------------------------------------------------------------------
// ok_wbm.v
//
// $Rev$ $Date$
//------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module ok_wbm (
input wire [7:0] hi_in,
output wire [1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire hi_muxsel,
input wire clk1,
output wire [7:0] led,
output wire [15:0] jp1,
input wire [3:0] button
);
wire ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;
// Endpoint connections:
wire [15:0] ep00wire;
wire [15:0] ep01wire;
wire [15:0] ep20wire;
wire [15:0] ep21wire;
wire [15:0] ep40trig;
wire [15:0] ep60trig;
// Data
wire ep80_write;
wire ep80_ready;
wire ep80_stb;
wire [15:0] ep80_data;
wire epA0_read;
wire epA0_ready;
wire epA0_stb;
wire [15:0] epA0_data;
// Opal Kelly stuff
assign hi_muxsel = 1'b0;
// Main clock DCM - copied from okLibrary.v
wire dcm_clk1, rstin;
DCM_SP hi_dcm ( .CLKIN (clk1),
.CLKFB (clk),
.CLK0 (dcm_clk1),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (rstin),
.DSSEN (1'b0));
BUFG clk1_buf (.I(dcm_clk1), .O(clk));
// Shift register to implement 4xclk1 reset pulse
SRL16 #(.INIT(16'hF000))
SRL16_inst (.CLK(clk1),.Q(rstin),.D(1'b0),
.A0(1'b1),.A1(1'b1),.A2(1'b1),.A3(1'b1));
// Physical debug IO
wire [15:0] debug_out;
assign jp1 = {debug_out};
assign led = ~{debug_out[7:0]};
// System wires
wire clk;
// Opal Kelly host interface wires
wire rst;
wire irq;
wire done;
wire busy;
// Opal Kelly host interface
assign rst = ep40trig[0];
assign ep21wire = debug_out;
assign ep60trig = {14'd0, irq, done};
// Wishbone Master
wire wb_clk_i;
wire wb_rst_i;
wire wb_ack_i;
wire wb_int_i;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_we_o;
wire [1:0] wb_sel_o;
wire [2:0] wb_cti_o;
wire [15:0] wb_data_i;
wire [15:0] wb_data_o;
wire [4:0] wb_addr_o;
assign wb_clk_i = ti_clk;
assign wb_rst_i = rst;
ok2wbm inst_ok2wbm(
.debug_out(),
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i),
.wb_ack_i(wb_ack_i), .wb_int_i(wb_int_i),
.wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
.wb_addr_o(wb_addr_o), .wb_data_o(wb_data_o), .wb_data_i(wb_data_i),
.wb_sel_o(wb_sel_o), .wb_cti_o(wb_cti_o),
.trg_irq(irq), .trg_done(done), .busy(busy),
.trg_sngl_rd(ep40trig[1]), .trg_sngl_wr(ep40trig[2]),
.trg_brst_rd(epA0_stb), .trg_brst_wr(ep80_stb), .brst_rd(epA0_read), .brst_wr(ep80_write),
.addr_in(ep00wire),
.sngl_data_in(ep01wire), .sngl_data_out(ep20wire),
.brst_data_in(ep80_data), .brst_data_out(epA0_data)
);
// Wishbone Slave Register Map
wb_regmap inst_regmap(
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i),
.wb_adr_i(wb_addr_o), .wb_dat_i(wb_data_o), .wb_dat_o(wb_data_i),
.wb_sel_i(wb_sel_o), .wb_cti_i(wb_cti_o),
.wb_we_i(wb_we_o), .wb_stb_i(wb_stb_o), .wb_cyc_i(wb_cyc_o), .wb_ack_o(wb_ack_i),
.wb_err_o(), .wb_int_o(wb_int_i),
.debug_out(debug_out)
);
// Instantiate the okHost and connect endpoints.
wire [17*5-1:0] ok2x;
okHost okHI(
.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .hi_aa(hi_aa), .ti_clk(ti_clk),
.ok1(ok1), .ok2(ok2));
okWireOR # (.N(5)) wireOR (ok2, ok2x);
okWireIn ep00(.ok1(ok1), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireIn ep01(.ok1(ok1), .ep_addr(8'h01), .ep_dataout(ep01wire));
okWireOut wo20(.ok1(ok1), .ok2(ok2x[ 0*17 +: 17 ]), .ep_addr(8'h20), .ep_datain(ep20wire));
okWireOut wo21(.ok1(ok1), .ok2(ok2x[ 1*17 +: 17 ]), .ep_addr(8'h21), .ep_datain(ep21wire));
okTriggerIn ti40(.ok1(ok1), .ep_addr(8'h40), .ep_clk(wb_clk_i), .ep_trigger(ep40trig));
okTriggerOut to60(.ok1(ok1), .ok2(ok2x[ 2*17 +: 17 ]), .ep_addr(8'h60), .ep_clk(wb_clk_i), .ep_trigger(ep60trig));
okBTPipeIn ep80(.ok1(ok1), .ok2(ok2x[ 3*17 +: 17 ]), .ep_addr(8'h80), .ep_write(ep80_write), .ep_dataout(ep80_data), .ep_blockstrobe(ep80_stb), .ep_ready(~busy));
okBTPipeOut epA0(.ok1(ok1), .ok2(ok2x[ 4*17 +: 17 ]), .ep_addr(8'hA0), .ep_read(epA0_read), .ep_datain(epA0_data), .ep_blockstrobe(epA0_stb), .ep_ready(~busy));
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_static_top.v
// Version : v1.0
// Description: static configuration top level module
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_static_top #
(
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 1 ,
parameter C_M_AXI_ARUSER_WIDTH = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_M_AXI_ADDR_WIDTH = 32 ,
parameter C_ATG_STATIC_WR_ADDRESS = 32'h12A0_0000 ,
parameter C_ATG_STATIC_RD_ADDRESS = 32'h13A0_0000 ,
parameter C_ATG_STATIC_WR_HIGH_ADDRESS = 32'h12A0_0FFF,
parameter C_ATG_STATIC_RD_HIGH_ADDRESS = 32'h13A0_0FFF,
parameter C_ATG_STATIC_INCR = 0 ,
parameter C_ATG_STATIC_EN_READ = 1 ,
parameter C_ATG_STATIC_EN_WRITE = 1 ,
parameter C_ATG_STATIC_FREE_RUN = 1 ,
parameter C_ATG_STATIC_TRANGAP = 32'd255 ,
parameter C_ATG_STATIC_RD_PIPELINE = 1 ,
parameter C_ATG_STATIC_WR_PIPELINE = 1 ,
parameter C_ATG_HLTP_MODE = 0 , //0-Custom,1-High Level Traffic.
parameter C_ATG_STATIC_LENGTH = 8'h3
) (
// system
input Clk ,
input rst_l ,
input core_global_start,
input core_global_stop ,
//Slave
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input awvalid_s ,
output awready_s ,
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input arvalid_s ,
output arready_s ,
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
//Master-write
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
input awready_m ,
output wlast_m ,
output [C_M_AXI_DATA_WIDTH-1:0] wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_m ,
output wvalid_m ,
input wready_m ,
input [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m ,
input [1:0] bresp_m ,
input bvalid_m ,
output bready_m ,
//Master-read
output [C_M_AXI_THREAD_ID_WIDTH-1:0] arid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] araddr_m ,
output [7:0] arlen_m ,
output [2:0] arsize_m ,
output [1:0] arburst_m ,
output [0:0] arlock_m ,
output [3:0] arcache_m ,
output [2:0] arprot_m ,
output [3:0] arqos_m ,
output [C_M_AXI_ARUSER_WIDTH-1:0] aruser_m ,
output arvalid_m ,
input arready_m ,
//r
input [C_M_AXI_THREAD_ID_WIDTH-1:0] rid_m ,
input rlast_m ,
input [C_M_AXI_DATA_WIDTH-1:0] rdata_m ,
input [1:0] rresp_m ,
input rvalid_m ,
output rready_m
);
wire reg0_m_enable_ff ;
wire static_ctl_en ;
wire reg1_done ;
wire reset_reg1_done ;
wire reset_reg1_en ;
wire static_ctl_en_pulse ;
wire [31:0] static_mr_tran_cnt ;
wire [31:0] static_mw_tran_cnt ;
wire [31:0] reg5_glcnt ;
wire [7:0] static_len ;
wire reg2_length_req ;
wire reg0_m_enable_3ff ;
wire [127:0] cmd_out_mw ;
wire [127:0] cmd_out_mr ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_out ;
axi_traffic_gen_v2_0_7_static_regblk #(
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ) ,
.C_ATG_STATIC_LENGTH(C_ATG_STATIC_LENGTH) ,
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH )
) static_regblk (
.Clk (Clk ),
.rst_l (rst_l ),
.core_global_start (core_global_start ),
.core_global_stop (core_global_stop ),
.awid_s (awid_s ),
.awaddr_s (awaddr_s ),
.awvalid_s (awvalid_s ),
.awready_s (awready_s ),
.wlast_s (wlast_s ),
.wdata_s (wdata_s ),
.wstrb_s (wstrb_s ),
.wvalid_s (wvalid_s ),
.wready_s (wready_s ),
.bid_s (bid_s ),
.bresp_s (bresp_s ),
.bvalid_s (bvalid_s ),
.bready_s (bready_s ),
.arid_s (arid_s ),
.araddr_s (araddr_s ),
.arvalid_s (arvalid_s ),
.arready_s (arready_s ),
.rid_s (rid_s ),
.rlast_s (rlast_s ),
.rdata_s (rdata_s ),
.rresp_s (rresp_s ),
.rvalid_s (rvalid_s ),
.rready_s (rready_s ),
.reg0_m_enable_ff (reg0_m_enable_ff ),
.static_ctl_en (static_ctl_en ),
.reg1_done (reg1_done ),
.reset_reg1_done (reset_reg1_done ),
.reset_reg1_en (reset_reg1_en ),
.static_ctl_en_pulse(static_ctl_en_pulse),
.static_mw_tran_cnt (static_mw_tran_cnt ),
.static_mr_tran_cnt (static_mr_tran_cnt ),
.static_len (static_len ),
.reg5_glbcnt (reg5_glcnt ),
.reg2_length_req (reg2_length_req ),
.reg0_m_enable_3ff (reg0_m_enable_3ff )
);
//New ST_CODE
axi_traffic_gen_v2_0_7_static_mrdwr #
(
.C_M_AXI_THREAD_ID_WIDTH ( C_M_AXI_THREAD_ID_WIDTH ),
.C_M_AXI_AWUSER_WIDTH ( C_M_AXI_AWUSER_WIDTH ),
.C_M_AXI_ARUSER_WIDTH ( C_M_AXI_ARUSER_WIDTH ),
.C_M_AXI_ADDR_WIDTH ( C_M_AXI_ADDR_WIDTH ),
.C_ATG_STATIC_RD_ADDRESS ( C_ATG_STATIC_RD_ADDRESS ),
.C_ATG_STATIC_WR_ADDRESS ( C_ATG_STATIC_WR_ADDRESS ),
.C_ATG_STATIC_WR_HIGH_ADDRESS(C_ATG_STATIC_WR_HIGH_ADDRESS),
.C_ATG_STATIC_RD_HIGH_ADDRESS(C_ATG_STATIC_RD_HIGH_ADDRESS),
.C_ATG_STATIC_INCR (C_ATG_STATIC_INCR ),
.C_ATG_STATIC_EN_READ ( C_ATG_STATIC_EN_READ ),
.C_ATG_STATIC_EN_WRITE ( C_ATG_STATIC_EN_WRITE ),
.C_ATG_STATIC_LENGTH ( C_ATG_STATIC_LENGTH ),
.C_ATG_STATIC_RD_PIPELINE( C_ATG_STATIC_RD_PIPELINE),
.C_ATG_STATIC_WR_PIPELINE( C_ATG_STATIC_WR_PIPELINE),
.C_ATG_STATIC_FREE_RUN ( C_ATG_STATIC_FREE_RUN ),
.C_ATG_STATIC_TRANGAP ( C_ATG_STATIC_TRANGAP ),
.C_ATG_HLTP_MODE (C_ATG_HLTP_MODE ),
.C_M_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH )
) static_mrdwr (
.Clk (Clk ),
.rst_l (rst_l ),
.awid_m (awid_m ),
.awaddr_m (awaddr_m ),
.awlen_m (awlen_m ),
.awsize_m (awsize_m ),
.awburst_m (awburst_m ),
.awlock_m (awlock_m ),
.awcache_m (awcache_m ),
.awprot_m (awprot_m ),
.awqos_m (awqos_m ),
.awuser_m (awuser_m ),
.awvalid_m (awvalid_m ),
.awready_m (awready_m ),
.wlast_m (wlast_m ),
.wdata_m (wdata_m ),
.wstrb_m (wstrb_m ),
.wvalid_m (wvalid_m ),
.wready_m (wready_m ),
.bid_m (bid_m ),
.bresp_m (bresp_m ),
.bvalid_m (bvalid_m ),
.bready_m (bready_m ),
.arid_m (arid_m ),
.araddr_m (araddr_m ),
.arlen_m (arlen_m ),
.arsize_m (arsize_m ),
.arburst_m (arburst_m ),
.arlock_m (arlock_m ),
.arcache_m (arcache_m ),
.arprot_m (arprot_m ),
.arqos_m (arqos_m ),
.aruser_m (aruser_m ),
.arvalid_m (arvalid_m ),
.arready_m (arready_m ),
.rid_m (rid_m ),
.rlast_m (rlast_m ),
.rdata_m (rdata_m ),
.rresp_m (rresp_m ),
.rvalid_m (rvalid_m ),
.rready_m (rready_m ),
.reg1_st_enable (static_ctl_en ),
.reg1_done (reg1_done ),
.reset_reg1_done (reset_reg1_done ),
.reset_reg1_en (reset_reg1_en ),
.reg2_length (static_len ),
.reg2_length_req(reg2_length_req),
.reg3_rdcnt (static_mr_tran_cnt),
.reg4_wrcnt (static_mw_tran_cnt ),
.reg5_glcnt (reg5_glcnt )
);
//New ST_CODE
//axi_traffic_gen_v2_0_7_static_cmdgen # (
// .C_ATG_STATIC_ADDRESS(C_ATG_STATIC_ADDRESS),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
// .C_ATG_STATIC_LENGTH (C_ATG_STATIC_LENGTH )
//) static_cmdgen (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .static_ctl_en(static_ctl_en),
// .static_len (static_len ),
// .cmd_out_mw (cmd_out_mw ),
// .cmd_data (mram_out ),
// .cmd_out_mr (cmd_out_mr )
//);
//
//
//axi_traffic_gen_v2_0_7_static_mw # (
// .C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
// .C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH ),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH )
//) static_mw (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .awid_m (awid_m ),
// .awaddr_m (awaddr_m ),
// .awlen_m (awlen_m ),
// .awsize_m (awsize_m ),
// .awburst_m (awburst_m ),
// .awlock_m (awlock_m ),
// .awcache_m (awcache_m ),
// .awprot_m (awprot_m ),
// .awqos_m (awqos_m ),
// .awuser_m (awuser_m ),
// .awvalid_m (awvalid_m ),
// .awready_m (awready_m ),
// .wlast_m (wlast_m ),
// .wdata_m (wdata_m ),
// .wstrb_m (wstrb_m ),
// .wvalid_m (wvalid_m ),
// .wready_m (wready_m ),
// .bid_m (bid_m ),
// .bresp_m (bresp_m ),
// .bvalid_m (bvalid_m ),
// .bready_m (bready_m ),
// .mram_out (mram_out ),
// .reg0_m_enable_ff (reg0_m_enable_ff ),
// .reg0_m_enable_3ff (reg0_m_enable_3ff ),
// .static_ctl_en_pulse(static_ctl_en_pulse),
// .static_mw_tran_cnt (static_mw_tran_cnt ),
// .cmd_out_mw (cmd_out_mw )
//);
//
//axi_traffic_gen_v2_0_7_static_mr #
//(
// .C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
// .C_M_AXI_ARUSER_WIDTH (C_M_AXI_ARUSER_WIDTH ),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH )
//) static_mr (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .arid_m (arid_m ),
// .araddr_m (araddr_m ),
// .arlen_m (arlen_m ),
// .arsize_m (arsize_m ),
// .arburst_m (arburst_m ),
// .arlock_m (arlock_m ),
// .arcache_m (arcache_m ),
// .arprot_m (arprot_m ),
// .arqos_m (arqos_m ),
// .aruser_m (aruser_m ),
// .arvalid_m (arvalid_m ),
// .arready_m (arready_m ),
// .rid_m (rid_m ),
// .rlast_m (rlast_m ),
// .rdata_m (rdata_m ),
// .rresp_m (rresp_m ),
// .rvalid_m (rvalid_m ),
// .rready_m (rready_m ),
// .reg0_m_enable_ff (reg0_m_enable_ff ),
// .reg0_m_enable_3ff (reg0_m_enable_3ff ),
// .static_ctl_en_pulse(static_ctl_en_pulse),
// .static_mr_tran_cnt (static_mr_tran_cnt ),
// .cmd_out_mr (cmd_out_mr )
//);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Bool NAxioms NSub NPow NDiv NParity NLog.
(** Derived properties of bitwise operations *)
Module Type NBitsProp
(Import A : NAxiomsSig')
(Import B : NSubProp A)
(Import C : NParityProp A B)
(Import D : NPowProp A B C)
(Import E : NDivProp A B)
(Import F : NLog2Prop A B C D).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha H.
apply div_unique with 0.
generalize (pow_nonzero a c Ha) (le_0_l (a^c)); order'.
nzsimpl. now rewrite <- pow_add_r, add_comm, sub_add.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb H.
apply div_unique with 0.
generalize (pow_nonzero b c Hb) (le_0_l (b^c)); order'.
nzsimpl. rewrite <- pow_mul_l. f_equiv. now apply div_exact.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2n (b:bool) := if b then 1 else 0.
Local Coercion b2n : bool >-> t.
Instance b2n_proper : Proper (Logic.eq ==> eq) b2n.
Proof. solve_proper. Qed.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n :
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_succ, le_0_l.
apply testbit_even_succ, le_0_l.
Qed.
(** Alternative characterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : a.[n] == (a / 2^n) mod 2.
Proof.
revert a. induct n.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
destruct b; order'.
intros n IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH. f_equiv.
rewrite pow_succ_r', <- div_div by order_nz. f_equiv.
apply div_unique with b; trivial.
destruct b; order'.
Qed.
(** This characterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This characterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n :
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
exists (a mod 2^n). exists (a / 2^n / 2). split.
split; [apply le_0_l | apply mod_upper_bound; order_nz].
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec'. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n,
a.[n] = true <-> (a / 2^n) mod 2 == 1.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n,
a.[n] = false <-> (a / 2^n) mod 2 == 0.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n,
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2n] *)
Lemma b2n_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2n_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; order').
Qed.
Lemma add_b2n_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2n_inj.
rewrite testbit_spec'. nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; order').
Qed.
Lemma b2n_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2n_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2n_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2n_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
apply b2n_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h. destruct a0; simpl; order'.
symmetry. apply div_unique with l; trivial.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n. apply testbit_false. nzsimpl; order_nz.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec'. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit *)
Lemma bit_log2 : forall a, a~=0 -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by (generalize (le_0_l a); order).
destruct (log2_spec_alt a Ha') as (r & EQ & (_,Hr)).
rewrite EQ at 1.
rewrite testbit_true, add_comm.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small by trivial.
rewrite add_0_l. apply mod_small. order'.
Qed.
Lemma bits_above_log2 : forall a n, log2 a < n ->
a.[n] = false.
Proof.
intros a n H.
rewrite testbit_false.
rewrite div_small. nzsimpl; order'.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, (a/2).[n] = a.[S n].
Proof.
intros. apply eq_true_iff_eq.
rewrite 2 testbit_true.
rewrite pow_succ_r by apply le_0_l.
now rewrite div_div by order_nz.
Qed.
Lemma div_pow2_bits : forall a n m, (a/2^n).[m] = a.[m+n].
Proof.
intros a n. revert a. induct n.
intros a m. now nzsimpl.
intros n IH a m. nzsimpl; try apply le_0_l.
rewrite <- div_div by order_nz.
now rewrite IH, div2_bits.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros. rewrite <- div2_bits. now rewrite mul_comm, div_mul by order'.
Qed.
Lemma mul_pow2_bits_add : forall a n m, (a*2^n).[m+n] = a.[m].
Proof.
intros. rewrite <- div_pow2_bits. now rewrite div_mul by order_nz.
Qed.
Lemma mul_pow2_bits_high : forall a n m, n<=m -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (sub_add n m) at 1 by order'.
now rewrite mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros. apply testbit_false.
rewrite <- (sub_add m n) by order'. rewrite pow_add_r, mul_assoc.
rewrite div_mul by order_nz.
rewrite <- (succ_pred (n-m)). rewrite pow_succ_r.
now rewrite (mul_comm 2), mul_assoc, mod_mul by order'.
apply lt_le_pred.
apply sub_gt in H. generalize (le_0_l (n-m)); order.
now apply sub_gt.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m H.
destruct (eq_0_gt_0_cases (a mod 2^n)) as [EQ|LT].
now rewrite EQ, bits_0.
apply bits_above_log2.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
apply mod_upper_bound; order_nz.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
rewrite testbit_eqb.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r', succ_pred
by now apply sub_gt.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add
by order.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (eq_decidable a 0) as [EQ|NEQ]; trivial.
apply bit_log2 in NEQ. now rewrite H in NEQ.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
intros a. pattern a.
apply strong_right_induction with 0;[solve_proper|clear a|apply le_0_l].
intros a _ IH b H.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ in H |- *. symmetry. apply bits_inj_0.
intros n. now rewrite <- H, bits_0.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH; trivial using le_0_l.
apply div_lt; order'.
intro n. rewrite 2 div2_bits. apply H.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
Ltac bitwise := apply bits_inj; intros ?m; autorewrite with bitwise.
(** The streams of bits that correspond to a natural numbers are
exactly the ones that are always 0 after some point *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, f === testbit n) <->
(exists k, forall m, k<=m -> f m = false)).
Proof.
intros f Hf. split.
intros (a,H).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite H, bits_above_log2; trivial using lt_succ_diag_r.
intros (k,Hk).
revert f Hf Hk. induct k.
intros f Hf H0.
exists 0. intros m. rewrite bits_0, H0; trivial. apply le_0_l.
intros k IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m.
destruct (zero_or_succ m) as [Hm|(m', Hm)]; rewrite Hm.
symmetry. apply add_b2n_double_bit0.
rewrite Hn, <- div2_bits.
rewrite mul_comm, div_add, b2n_div2, add_0_l; trivial. order'.
Qed.
(** Properties of shifts *)
Lemma shiftr_spec' : forall a n m, (a >> n).[m] = a.[m+n].
Proof.
intros. apply shiftr_spec. apply le_0_l.
Qed.
Lemma shiftl_spec_high' : forall a n m, n<=m -> (a << n).[m] = a.[m-n].
Proof.
intros. apply shiftl_spec_high; trivial. apply le_0_l.
Qed.
Lemma shiftr_div_pow2 : forall a n, a >> n == a / 2^n.
Proof.
intros. bitwise. rewrite shiftr_spec'.
symmetry. apply div_pow2_bits.
Qed.
Lemma shiftl_mul_pow2 : forall a n, a << n == a * 2^n.
Proof.
intros. bitwise.
destruct (le_gt_cases n m) as [H|H].
now rewrite shiftl_spec_high', mul_pow2_bits_high.
now rewrite shiftl_spec_low, mul_pow2_bits_low.
Qed.
Lemma shiftl_spec_alt : forall a n m, (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits_add.
Qed.
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftr_div_pow2, Ha, Hb.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftl_mul_pow2, Ha, Hb.
Qed.
Lemma shiftl_shiftl : forall a n m,
(a << n) << m == a << (n+m).
Proof.
intros. now rewrite !shiftl_mul_pow2, pow_add_r, mul_assoc.
Qed.
Lemma shiftr_shiftr : forall a n m,
(a >> n) >> m == a >> (n+m).
Proof.
intros.
now rewrite !shiftr_div_pow2, pow_add_r, div_div by order_nz.
Qed.
Lemma shiftr_shiftl_l : forall a n m, m<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros.
rewrite shiftr_div_pow2, !shiftl_mul_pow2.
rewrite <- (sub_add m n) at 1 by trivial.
now rewrite pow_add_r, mul_assoc, div_mul by order_nz.
Qed.
Lemma shiftr_shiftl_r : forall a n m, n<=m ->
(a << n) >> m == a >> (m-n).
Proof.
intros.
rewrite !shiftr_div_pow2, shiftl_mul_pow2.
rewrite <- (sub_add n m) at 1 by trivial.
rewrite pow_add_r, (mul_comm (2^(m-n))).
now rewrite <- div_div, div_mul by order_nz.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros. now rewrite shiftl_mul_pow2, mul_1_l.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. rewrite shiftr_div_pow2. now nzsimpl.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. rewrite shiftr_div_pow2. nzsimpl; order_nz.
Qed.
Lemma shiftl_eq_0_iff : forall a n, a << n == 0 <-> a == 0.
Proof.
intros a n. rewrite shiftl_mul_pow2. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ. split. now left. intros _.
assert (H : 2~=0) by order'.
generalize (pow_nonzero 2 n H) (le_0_l (2^n)); order.
rewrite log2_lt_pow2; trivial.
split. right; split; trivial. intros [H|[_ H]]; now order.
Qed.
Lemma shiftr_eq_0 : forall a n, log2 a < n -> a >> n == 0.
Proof.
intros a n H. rewrite shiftr_eq_0_iff.
destruct (eq_0_gt_0_cases a) as [EQ|LT]. now left. right; now split.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1<<n).
Definition clearbit a n := ldiff a (1<<n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)). rewrite <- (add_0_l n) at 2.
now rewrite mul_pow2_bits_add, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
rewrite <- (mul_1_l (2^n)).
destruct (le_gt_cases n m).
rewrite mul_pow2_bits_high; trivial.
rewrite <- (succ_pred (m-n)) by (apply sub_gt; order).
now rewrite <- div2_bits, div_small, bits_0 by order'.
rewrite mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, (2^n).[m] = eqb n m.
Proof.
intros. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true.
Qed.
Lemma setbit_eqb : forall a n m,
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m,
(setbit a n).[m] = true <-> n==m \/ a.[m] = true.
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff. now left.
Qed.
Lemma setbit_neq : forall a n m, n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite setbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros. now rewrite clearbit_spec', ldiff_spec, pow2_bits_eqb.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lxor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', land_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', ldiff_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', ldiff_spec.
Qed.
(** We cannot have a function complementing all bits of a number,
otherwise it would have an infinity of bit 1. Nonetheless,
we can design a bounded complement *)
Definition ones n := P (1 << n).
Definition lnot a n := lxor a (ones n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Instance lnot_wd : Proper (eq==>eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros; unfold ones; now rewrite shiftl_1_l.
Qed.
Lemma ones_add : forall n m, ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r.
rewrite add_sub_assoc, sub_add. reflexivity.
apply pow_le_mono_r. order'.
rewrite <- (add_0_r m) at 1. apply add_le_mono_l, le_0_l.
rewrite <- (pow_0_r 2). apply pow_le_mono_r. order'. apply le_0_l.
Qed.
Lemma ones_div_pow2 : forall n m, m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m H. symmetry. apply div_unique with (ones m).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_mod_pow2 : forall n m, m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m H. symmetry. apply mod_unique with (ones (n-m)).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_spec_low : forall n m, m<n -> (ones n).[m] = true.
Proof.
intros. apply testbit_true. rewrite ones_div_pow2 by order.
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, n<=m -> (ones n).[m] = false.
Proof.
intros.
destruct (eq_0_gt_0_cases n) as [EQ|LT]; rewrite ones_equiv.
now rewrite EQ, pow_0_r, one_succ, pred_succ, bits_0.
apply bits_above_log2.
rewrite log2_pred_pow2; trivial. rewrite <-le_succ_l, succ_pred; order.
Qed.
Lemma ones_spec_iff : forall n m, (ones n).[m] = true <-> m<n.
Proof.
intros. split. intros H.
apply lt_nge. intro H'. apply ones_spec_high in H'.
rewrite H in H'; discriminate.
apply ones_spec_low.
Qed.
Lemma lnot_spec_low : forall a n m, m<n ->
(lnot a n).[m] = negb a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_low.
Qed.
Lemma lnot_spec_high : forall a n m, n<=m ->
(lnot a n).[m] = a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_high, xorb_false_r.
Qed.
Lemma lnot_involutive : forall a n, lnot (lnot a n) n == a.
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
now rewrite 2 lnot_spec_high.
now rewrite 2 lnot_spec_low, negb_involutive.
Qed.
Lemma lnot_0_l : forall n, lnot 0 n == ones n.
Proof.
intros. unfold lnot. apply lxor_0_l.
Qed.
Lemma lnot_ones : forall n, lnot (ones n) n == 0.
Proof.
intros. unfold lnot. apply lxor_nilpotent.
Qed.
(** Bounded complement and other operations *)
Lemma lor_ones_low : forall a n, log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, orb_true_r.
Qed.
Lemma land_ones : forall a n, land a (ones n) == a mod 2^n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
now rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r.
now rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r.
Qed.
Lemma land_ones_low : forall a n, log2 a < n ->
land a (ones n) == a.
Proof.
intros; rewrite land_ones. apply mod_small.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
Lemma ldiff_ones_r : forall a n,
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high', shiftr_spec'; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now rewrite ones_spec_low, shiftl_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_r_low : forall a n, log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_l_low : forall a n, log2 a < n ->
ldiff (ones n) a == lnot a n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, lnot_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, lnot_spec_low.
Qed.
Lemma lor_lnot_diag : forall a n,
lor a (lnot a n) == lor a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma lor_lnot_diag_low : forall a n, log2 a < n ->
lor a (lnot a n) == ones n.
Proof.
intros a n H. now rewrite lor_lnot_diag, lor_ones_low.
Qed.
Lemma land_lnot_diag : forall a n,
land a (lnot a n) == ldiff a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma land_lnot_diag_low : forall a n, log2 a < n ->
land a (lnot a n) == 0.
Proof.
intros. now rewrite land_lnot_diag, ldiff_ones_r_low.
Qed.
Lemma lnot_lor_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (lor a b) n == land (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lor_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, lor_spec, negb_orb.
Qed.
Lemma lnot_land_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (land a b) n == lor (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, land_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, land_spec, negb_andb.
Qed.
Lemma ldiff_land_low : forall a b n, log2 a < n ->
ldiff a b == land a (lnot b n).
Proof.
intros a b n Ha. bitwise. destruct (le_gt_cases n m).
rewrite (bits_above_log2 a m). trivial.
now apply lt_le_trans with n.
rewrite !lnot_spec_low; trivial.
Qed.
Lemma lnot_ldiff_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (ldiff a b) n == lor (lnot a n) b.
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, ldiff_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b n,
lxor (lnot a n) (lnot b n) == lxor a b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high; trivial.
rewrite !lnot_spec_low, xorb_negb_negb; trivial.
Qed.
Lemma lnot_lxor_l : forall a b n,
lnot (lxor a b) n == lxor (lnot a n) b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_l; trivial.
Qed.
Lemma lnot_lxor_r : forall a b n,
lnot (lxor a b) n == lxor a (lnot b n).
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_r; trivial.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, bits_0 in H.
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H' by order.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, log2 (a >> n) == log2 a - n.
Proof.
intros a n.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, shiftr_0_l, log2_nonpos, sub_0_l by order.
destruct (lt_ge_cases (log2 a) n).
rewrite shiftr_eq_0, log2_nonpos by order.
symmetry. rewrite sub_0_le; order.
apply log2_bits_unique.
now rewrite shiftr_spec', sub_add, bit_log2 by order.
intros m Hm.
rewrite shiftr_spec'; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
Qed.
Lemma log2_shiftl : forall a n, a~=0 -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha.
rewrite shiftl_mul_pow2, add_comm by trivial.
apply log2_mul_pow2. generalize (le_0_l a); order. apply le_0_l.
Qed.
Lemma log2_lor : forall a b,
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lor a b) == log2 b).
intros a b H.
destruct (eq_0_gt_0_cases a) as [Ha|Ha]. now rewrite Ha, lor_0_l.
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b,
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (land a b) <= log2 a).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (land a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (land a b) NEQ).
now rewrite land_spec, bits_above_log2.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b,
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lxor a b) <= log2 b).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (lxor a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (lxor a b) NEQ).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; order') || idtac.
symmetry. apply div_unique with 1. order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1. fold (b2n a.[0]).
rewrite (div2_odd b), <- bit0_odd at 1. fold (b2n b.[0]).
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
(* induction over some n such that [a<2^n] and [b<2^n] *)
set (n:=max a b).
assert (Ha : a<2^n).
apply lt_le_trans with (2^a). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
assert (Hb : b<2^n).
apply lt_le_trans with (2^b). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
clearbody n.
revert a b c0 Ha Hb. induct n.
(*base*)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r. intros Ha Hb.
exists c0.
setoid_replace a with 0 by (generalize (le_0_l a); order').
setoid_replace b with 0 by (generalize (le_0_l b); order').
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2n_div2, b2n_bit0; now repeat split.
(*step*)
intros n IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
exists (c0 + 2*c). repeat split.
(* - add *)
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0, add3_bit0, b2n_bit0.
rewrite <- !div2_bits, <- 2 lxor_spec.
f_equiv.
rewrite add_b2n_double_div2, <- IH1. apply add_carry_div2.
(* - carry *)
rewrite add_b2n_double_div2.
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0.
rewrite <- !div2_bits, IH2. autorewrite with bitwise.
now rewrite add_b2n_double_div2.
(* - carry0 *)
apply add_b2n_double_bit0.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj_0.
induct n. trivial.
intros n IH.
rewrite <- div2_bits, H.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, ldiff a b == 0 -> a <= b.
Proof.
cut (forall n a b, a < 2^n -> ldiff a b == 0 -> a <= b).
intros H a b. apply (H a), pow_gt_lin_r; order'.
induct n.
intros a b Ha _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (generalize (le_0_l a); order').
rewrite Ha'. apply le_0_l.
intros n IH a b Ha H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_l.
apply IH.
apply div_lt_upper_bound; trivial. now rewrite <- pow_succ_r'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2.
now rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
now apply ldiff_le.
Qed.
(** We can express lnot in term of subtraction *)
Lemma add_lnot_diag_low : forall a n, log2 a < n ->
a + lnot a n == ones n.
Proof.
intros a n H.
assert (H' := land_lnot_diag_low a n H).
rewrite add_nocarry_lxor, lxor_lor by trivial.
now apply lor_lnot_diag_low.
Qed.
Lemma lnot_sub_low : forall a n, log2 a < n ->
lnot a n == ones n - a.
Proof.
intros a n H.
now rewrite <- (add_lnot_diag_low a n H), add_comm, add_sub.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
rewrite add_nocarry_lxor by trivial.
apply div_small_iff. order_nz.
rewrite <- shiftr_div_pow2, shiftr_lxor, !shiftr_div_pow2.
rewrite 2 div_small by trivial.
apply lxor_0_l.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
now rewrite mod_pow2_bits_high.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_upper_bound; order_nz.
apply mod_upper_bound; order_nz.
Qed.
End NBitsProp.
|
`include "lo_read.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
lo_is_125khz - input freq selector (1=125Khz, 0=136Khz)
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal 1Mhz/1.09Mhz (pck0 / 2*(11+lo_is_125khz) )
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_lo_read;
reg pck0;
reg [7:0] adc_d;
reg lo_is_125khz;
reg [15:0] divisor;
wire pwr_lo;
wire adc_clk;
wire ck_1356meg;
wire ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
lo_read #(5,10) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.lo_is_125khz(lo_is_125khz),
.divisor(divisor)
);
integer idx, i, adc_val=8;
// main clock
always #5 pck0 = !pck0;
task crank_dut;
begin
@(posedge adc_clk) ;
adc_d = adc_val;
adc_val = (adc_val *2) + 53;
end
endtask
initial begin
// init inputs
pck0 = 0;
adc_d = 0;
ssp_dout = 0;
lo_is_125khz = 1;
divisor = 255; //min 16, 95=125Khz, max 255
// simulate 4 A/D cycles at 125Khz
for (i = 0 ; i < 8 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
// Virtex 6 and Series 7 block RAM mapping.
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [71:0] A1DATA;
input A1EN;
input [8:0] B1ADDR;
input [71:0] B1DATA;
input [7:0] B1EN;
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
wire [7:0] DIP, DOP;
wire [63:0] DI, DO;
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB36E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(72),
.WRITE_WIDTH_B(72),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_36.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[63:32]),
.DOADO(DO[31:0]),
.DOPBDOP(DOP[7:4]),
.DOPADOP(DOP[3:0]),
.DIBDI(DI[63:32]),
.DIADI(DI[31:0]),
.DIPBDIP(DIP[7:4]),
.DIPADIP(DIP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [35:0] A1DATA;
input A1EN;
input [8:0] B1ADDR;
input [35:0] B1DATA;
input [3:0] B1EN;
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.WRITE_WIDTH_B(36),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_18.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[31:16]),
.DOADO(DO[15:0]),
.DOPBDOP(DOP[3:2]),
.DOPADOP(DOP[1:0]),
.DIBDI(DI[31:16]),
.DIADI(DI[15:0]),
.DIPBDIP(DIP[3:2]),
.DIPADIP(DIP[1:0]),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
wire [7:0] B1EN_8 = B1EN;
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOBDO;
wire [3:0] DOPBDOP;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB36E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_36.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(32'd0),
.DIPADIP(4'd0),
.DOADO(DO[31:0]),
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_8)
);
end else begin
RAMB36E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_32.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(32'd0),
.DIPADIP(4'd0),
.DOADO(DO[31:0]),
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_8)
);
end endgenerate
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
wire [3:0] B1EN_4 = B1EN;
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB18E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_18.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_4)
);
end else begin
RAMB18E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_16.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_4)
);
end endgenerate
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Detect that b is declared as a scaler and a vector.
*/
module simple (a, b);
input [7:0] a;
output [7:0] b;
reg b; // Error here!
always @(a)
begin
b = a;
end
endmodule
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
`ifndef _arbiter
`define _arbiter
module arbiter
#( parameter integer WIDTH = 2)
(
input [WIDTH-1:0] req,
input enable,
input clk,
input rst,
output reg [WIDTH-1:0] grant,
output anyreq
);
parameter P_WIDTH = $clog2(WIDTH);
logic [P_WIDTH-1:0] pointer;
logic [2*WIDTH-1:0] req_shifted_double;
logic [WIDTH-1:0] req_shifted;
logic [2*WIDTH-1:0] grant_shifted_double;
logic [WIDTH-1:0] grant_shifted;
assign req_shifted_double = {req,req} >> pointer;
assign req_shifted = req_shifted_double[WIDTH-1:0];
always @(posedge clk, negedge rst) begin
if (!rst) begin
pointer <= 0;
end
else begin
if (pointer < WIDTH -1) begin
pointer <= pointer + 1;
end
else begin
pointer <= 0;
end
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
assign anyreq = |req;
genvar i;
always @(*) begin
grant_shifted = {WIDTH{1'b0}};
if (enable) begin
for (int i = 0; i < WIDTH; i = i + 1) begin
if (req_shifted[i]) begin
grant_shifted[i] = 1'b1;
break;
end
end
end
end
assign grant_shifted_double = {grant_shifted, grant_shifted} << pointer;
assign grant = grant_shifted_double[2*WIDTH-1:WIDTH];
endmodule // arbiter
`endif // `ifndef _arbiter
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_lp__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , D, CLK, SET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:00:14 05/19/2015
// Design Name:
// Module Name: display2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display2(
input wire clk,
input wire rst,
input wire [31:0] instr,
input wire [31:0] reg_data,
input wire [31:0] stage,
input wire [7:0] clk_cnt,
input wire [7:0] reg_addr,
output wire lcd_e,
output wire lcd_rs,
output wire lcd_rw,
output wire [3:0] lcd_dat
);
reg [255:0] strdata = "";
wire [95:0] datain = {instr,reg_data,stage};
function [7:0] num2str;
input [3:0] number;
begin
if(number < 10)
num2str = "0" + number;
else
num2str = "A" - 10 + number;
end
endfunction
//instr
genvar i;
generate for (i=0; i<24; i=i+1) begin: NUM2STR
always @(posedge clk) begin
strdata[8*i+71-:8] <= num2str(datain[4*i+3-:4]);
end
end
endgenerate
generate for (i=0; i<2; i=i+1) begin: NUM2STR2
always @(posedge clk) begin
strdata[8*i+39-:8] <= num2str(clk_cnt[4*i+3-:4]);
end
end
endgenerate
generate for (i=0; i<2; i=i+1) begin: NUM2STR3
always @(posedge clk) begin
strdata[8*i+7-:8] <= num2str(reg_addr[4*i+3-:4]);
end
end
endgenerate
reg refresh = 0;
// reg [7:0] addr_buf;
// reg [31:0] data_buf;
reg [127:0] datain_buf;
reg [7:0] clk_cnt_buf;
reg [7:0] reg_addr_buf;
always @(posedge clk) begin
datain_buf <= datain;
clk_cnt_buf <= clk_cnt;
reg_addr_buf <= reg_addr;
refresh <= (datain_buf != datain) | (clk_cnt_buf != clk_cnt) | (reg_addr_buf != reg_addr);
end
displcd DISPLCD (
.CCLK(clk),
.reset(rst | refresh),
.strdata(strdata),
.rslcd(lcd_rs),
.rwlcd(lcd_rw),
.elcd(lcd_e),
.lcdd(lcd_dat)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg rnd;
reg [2:0] a;
reg [2:0] b;
reg [31:0] wide;
// surefire lint_off STMINI
initial _ranit = 0;
wire sigone1 = 1'b1;
wire sigone2 = 1'b1;
reg ok;
parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b??
// Large case statements should be well optimizable.
reg [2:0] anot;
always @ (/*AS*/a) begin
casez (a)
default: anot = 3'b001;
3'd0: anot = 3'b111;
3'd1: anot = 3'b110;
3'd2: anot = 3'b101;
3'd3: anot = 3'b101;
3'd4: anot = 3'b011;
3'd5: anot = 3'b010;
3'd6: anot = 3'b001; // Same so folds with 7
endcase
end
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
rnd <= 1;
$write("[%0t] t_case: Running\n", $time);
//
a = 3'b101;
b = 3'b111;
// verilator lint_off CASEX
casex (a)
default: $stop;
3'bx1x: $stop;
3'b100: $stop;
3'bx01: ;
endcase
casez (a)
default: $stop;
3'b?1?: $stop;
3'b100: $stop;
3'b?01: ;
endcase
casez (a)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
endcase
casez (b)
default: $stop;
{1'b0, twounkn}: $stop;
{1'b1, twounkn}: ;
// {1'b0, 2'b??}: $stop;
// {1'b1, 2'b??}: ;
endcase
case(a[0])
default: ;
endcase
casex(a)
default: ;
3'b?0?: ;
endcase
// verilator lint_off CASEX
//This is illegal, the default occurs before the statements.
//case(a[0])
// default: $stop;
// 1'b1: ;
//endcase
//
wide = 32'h12345678;
casez (wide)
default: $stop;
32'h12345677,
32'h12345678,
32'h12345679: ;
endcase
//
ok = 0;
casez ({sigone1,sigone2})
//2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true...
2'b10, 2'b01: ;
2'b00: ;
default: ok=1'b1;
endcase
if (ok !== 1'b1) $stop;
//
if (rnd) begin
$write("");
end
//
$write("*-* All Finished *-*\n");
$finish;
end
end
// Check parameters in case statements
parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr.
parameter DSP_REGISTER_V = 6'h03;
reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl
reg [5:0] reg_addr_2s; // Delayed version of reg_addr
reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases
reg [15:10] f_tmp_2s; // Delayed copy of F
reg p00_2s;
initial begin
alu_ctl_2s = 3'h1;
reg_addr_2s = 6'h3;
ir_slave_2s= 0;
f_tmp_2s= 0;
casex ({alu_ctl_2s,reg_addr_2s,
ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0],
f_tmp_2s[11:10]})
default: p00_2s = 1'b0;
{ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1;
endcase
if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused
//
case ({1'b1, 1'b1})
default: $stop;
{1'b1, p00_2s}: ;
endcase
end
// Check wide overlapping cases
// surefire lint_off CSEOVR
parameter ANY_STATE = 7'h??;
reg [19:0] foo;
initial begin
foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0};
casez (foo)
default: $stop;
{1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop;
{1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop;
{1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop;
endcase
end
initial begin
foo = 20'b1010;
casex (foo[3:0])
default: $stop;
4'b0xxx,
4'b100x,
4'b11xx: $stop;
4'b1010: ;
endcase
end
initial begin
foo = 20'b1010;
ok = 1'b0;
// Test of RANGE(CONCAT reductions...
casex ({foo[3:2],foo[1:0],foo[3]})
5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions
5'bxx00x: $stop;
5'bxx01x: $stop;
5'bxx11x: $stop;
endcase
if (!ok) $stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
`define SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$NSR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
input SET ,
//# {{clocks|Clocking}}
input CLK_N
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_NSR_SYMBOL_V
|
`timescale 1 ns / 1 ps
module s2mm_adv #
(
// Users to add parameters here
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12,
parameter integer C_DATACOUNT_BITS = 12,
parameter integer C_PIXEL_STORE_WIDTH = 8,
parameter integer C_IMG_STRIDE_SIZE = 1024,
// User parameters ends
// Parameters of Axi Master Bus Interface M_AXI
parameter integer C_M_AXI_BURST_LEN = 16,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
input wire [C_IMG_WBITS-1:0] img_width,
input wire [C_IMG_HBITS-1:0] img_height,
input wire [C_M_AXI_ADDR_WIDTH-1:0] img_stride,
input wire clk,
input wire resetn,
/// @NOTE: resetting will keep until current transaction done.
/// if under idle state when negedge of soft_resetn,
/// don't need resetting, i.e. resetting will keep zero.
input wire soft_resetn,
output wire resetting,
/// sream to fifo
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
input wire s2mm_full,
input wire s2mm_almost_full,
output wire [C_PIXEL_WIDTH+1 : 0] s2mm_wr_data,
output wire s2mm_wr_en,
/// fifo to memory
output wire s2mm_sof,
input wire [C_M_AXI_ADDR_WIDTH-1:0] s2mm_addr,
input wire [C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH*(C_PIXEL_WIDTH+2)-1 : 0] s2mm_rd_data,
input wire s2mm_empty,
output wire s2mm_rd_en,
input wire [C_DATACOUNT_BITS-1:0] s2mm_rd_data_count,
// Ports of Axi Master Bus Interface M_AXI
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output wire [7 : 0] m_axi_awlen,
output wire [2 : 0] m_axi_awsize,
output wire [1 : 0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3 : 0] m_axi_awcache,
output wire [2 : 0] m_axi_awprot,
output wire [3 : 0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [1 : 0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready
);
localparam C_PM1 = C_PIXEL_WIDTH - 1;
localparam C_PP1 = C_PIXEL_WIDTH + 1;
localparam C_PP2 = C_PIXEL_WIDTH + 2;
localparam C_ADATA_PIXELS = C_M_AXI_DATA_WIDTH/C_PIXEL_STORE_WIDTH;
function integer reverseI(input integer i);
begin
reverseI = C_ADATA_PIXELS-1-i;
end
endfunction
function integer sofIdx(input integer i);
begin
sofIdx = i * C_PP2 + C_PIXEL_WIDTH;
end
endfunction
function integer eolIdx(input integer i);
begin
eolIdx = i * C_PP2 + C_PP1;
end
endfunction
// stream to fifo
wire working;
assign working = (resetn && soft_resetn);
assign resetting = ~working;
/// use s2f_aclk
assign s2mm_wr_data = {s_axis_tlast, s_axis_tuser, s_axis_tdata};
assign s2mm_wr_en = s_axis_tvalid && s_axis_tready;
reg sready;
assign s_axis_tready = sready;
always @ (posedge clk) begin
if (resetting)
sready <= 0;
else if (s2mm_wr_en && s2mm_almost_full)
sready <= 0;
else
sready <= 1;
end
// fifo to mm
/// use f2m_aclk
wire [C_M_AXI_DATA_WIDTH-1 : 0] s2mm_pixel_data;
generate
genvar i;
for (i = 0; i < C_M_AXI_DATA_WIDTH/C_PIXEL_WIDTH; i = i+1) begin: single_pixel
assign s2mm_pixel_data[i*C_PIXEL_STORE_WIDTH + C_PM1 : i*C_PIXEL_STORE_WIDTH]
= s2mm_rd_data[reverseI(i)*C_PP2 + C_PM1 : reverseI(i)*C_PP2];
end
endgenerate
wire f2mm_resetting;
wire f2mm_write_resp_error;
FIFO2MM_adv # (
.C_DATACOUNT_BITS(C_DATACOUNT_BITS),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M_AXI_DATA_WIDTH),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS),
.C_ADATA_PIXELS(C_ADATA_PIXELS)
) FIFO2MM_inst (
.img_width(img_width),
.img_height(img_height),
.img_stride(C_IMG_STRIDE_SIZE),
.soft_resetn(soft_resetn),
.resetting(f2mm_resetting),
//.sof(s2mm_rd_data[sofIdx(reverseI(0))]),
.din(s2mm_pixel_data),
//.empty(s2mm_empty),
.rd_en(s2mm_rd_en),
.rd_data_count(s2mm_rd_data_count),
.frame_pulse(s2mm_sof),
.base_addr(s2mm_addr),
.M_AXI_ACLK(clk),
.M_AXI_ARESETN(resetn),
.M_AXI_AWADDR(m_axi_awaddr),
.M_AXI_AWLEN(m_axi_awlen),
.M_AXI_AWSIZE(m_axi_awsize),
.M_AXI_AWBURST(m_axi_awburst),
.M_AXI_AWLOCK(m_axi_awlock),
.M_AXI_AWCACHE(m_axi_awcache),
.M_AXI_AWPROT(m_axi_awprot),
.M_AXI_AWQOS(m_axi_awqos),
.M_AXI_AWVALID(m_axi_awvalid),
.M_AXI_AWREADY(m_axi_awready),
.M_AXI_WDATA(m_axi_wdata),
.M_AXI_WSTRB(m_axi_wstrb),
.M_AXI_WLAST(m_axi_wlast),
.M_AXI_WVALID(m_axi_wvalid),
.M_AXI_WREADY(m_axi_wready),
.M_AXI_BRESP(m_axi_bresp),
.M_AXI_BVALID(m_axi_bvalid),
.M_AXI_BREADY(m_axi_bready),
.write_resp_error(f2mm_write_resp_error)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Oct 17 02:50:46 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top RAT_slice_7_0_0 -prefix
// RAT_slice_7_0_0_ RAT_slice_7_3_0_sim_netlist.v
// Design : RAT_slice_7_3_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_slice_7_3_0,xlslice,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlslice,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_slice_7_0_0
(Din,
Dout);
input [17:0]Din;
output [4:0]Dout;
wire [17:0]Din;
assign Dout[4:0] = Din[12:8];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module mux_sram
#(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 20
)
(/*autoport*/
// boot ports interface
input boot_mode,
input boot_mem_wr_en,
input [ADDR_WIDTH-1:0] boot_mem_addr,
input [DATA_WIDTH-1:0] boot_mem_rd_data,
// dlx ports interface
input inst_mem_wr_en,
input inst_mem_rd_en,
input [DATA_WIDTH-1:0] inst_mem_wr_data,
output reg [DATA_WIDTH-1:0] inst_mem_rd_data,
input [ADDR_WIDTH-1:0] inst_mem_addr,
//sram insterface
output reg sram_mem_wr_en,
output reg sram_mem_rd_en,
output reg [DATA_WIDTH-1:0] sram_mem_wr_data,
input [DATA_WIDTH-1:0] sram_mem_rd_data,
output reg [ADDR_WIDTH-1:0] sram_mem_addr
);
//*******************************************************
//Outputs
//*******************************************************
always @(*) begin
if (boot_mode) begin
sram_mem_wr_en = boot_mem_wr_en;
sram_mem_rd_en = 1'b0;
sram_mem_wr_data = boot_mem_rd_data;
sram_mem_addr = boot_mem_addr;
inst_mem_rd_data = {DATA_WIDTH{1'b0}};
end
else begin
sram_mem_wr_en = inst_mem_wr_en;
sram_mem_rd_en = inst_mem_rd_en;
sram_mem_wr_data = inst_mem_wr_data;
inst_mem_rd_data = sram_mem_rd_data;
sram_mem_addr = inst_mem_addr;
end
end
endmodule |
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions:i2c controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
// --------------------------------------------------------------------
module I2C_Controller (
CLOCK,
I2C_SCLK,//I2C CLOCK
I2C_SDAT,//I2C DATA
I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
END, //END transfor
W_R, //W_R
ACK, //ACK
RESET,
//TEST
SD_COUNTER,
SDO
);
input CLOCK;
input [23:0]I2C_DATA;
input GO;
input RESET;
input W_R;
inout I2C_SDAT;
output I2C_SCLK;
output END;
output ACK;
//TEST
output [5:0] SD_COUNTER;
output SDO;
reg SDO;
reg SCLK;
reg END;
reg [23:0]SD;
reg [5:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK :0 );
wire I2C_SDAT=SDO?1'bz:0 ;
reg ACK1,ACK2,ACK3;
wire ACK=ACK1 | ACK2 |ACK3;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 6'b111111) SD_COUNTER=SD_COUNTER+1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[23];
6'd4 : SDO=SD[22];
6'd5 : SDO=SD[21];
6'd6 : SDO=SD[20];
6'd7 : SDO=SD[19];
6'd8 : SDO=SD[18];
6'd9 : SDO=SD[17];
6'd10 : SDO=SD[16];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[14];
6'd14 : SDO=SD[13];
6'd15 : SDO=SD[12];
6'd16 : SDO=SD[11];
6'd17 : SDO=SD[10];
6'd18 : SDO=SD[9];
6'd19 : SDO=SD[8];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[6];
6'd23 : SDO=SD[5];
6'd24 : SDO=SD[4];
6'd25 : SDO=SD[3];
6'd26 : SDO=SD[2];
6'd27 : SDO=SD[1];
6'd28 : SDO=SD[0];
6'd29 : SDO=1'b1;//ACK
//stop
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
6'd31 : SCLK=1'b1;
6'd32 : begin SDO=1'b1; END=1; end
endcase
end
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue = @ event_identifier constant
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
#10 ;
if(value1 != 4'h5)
$display("FAILED - always reg_lvalue = @ event_identifier constant\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 = repeat ( 5 ) @ event_ident 4'h5 ;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_s01_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(1),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="array_arith,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=21,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=108,HLS_SYN_LUT=122,HLS_VERSION=2018_2}" *)
module array_arith (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
d_address0,
d_ce0,
d_we0,
d_d0,
d_q0
);
parameter ap_ST_fsm_state1 = 6'd1;
parameter ap_ST_fsm_state2 = 6'd2;
parameter ap_ST_fsm_state3 = 6'd4;
parameter ap_ST_fsm_state4 = 6'd8;
parameter ap_ST_fsm_state5 = 6'd16;
parameter ap_ST_fsm_state6 = 6'd32;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [2:0] d_address0;
output d_ce0;
output d_we0;
output [31:0] d_d0;
input [31:0] d_q0;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[2:0] d_address0;
reg d_ce0;
reg d_we0;
(* fsm_encoding = "none" *) reg [5:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] acc;
wire [2:0] i_1_fu_61_p2;
reg [2:0] i_1_reg_94;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_state3;
reg [31:0] d_load_reg_105;
wire ap_CS_fsm_state4;
wire [31:0] tmp_2_fu_75_p2;
reg [31:0] tmp_2_reg_110;
wire ap_CS_fsm_state5;
reg [2:0] i_reg_43;
wire ap_CS_fsm_state6;
wire [63:0] tmp_1_fu_67_p1;
wire [63:0] tmp_3_fu_86_p1;
wire [0:0] exitcond_fu_55_p2;
reg [5:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 6'd1;
#0 acc = 32'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state6)) begin
i_reg_43 <= i_1_reg_94;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
i_reg_43 <= 3'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state5)) begin
acc <= tmp_2_fu_75_p2;
tmp_2_reg_110 <= tmp_2_fu_75_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state4)) begin
d_load_reg_105 <= d_q0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
i_1_reg_94 <= i_1_fu_61_p2;
end
end
always @ (*) begin
if (((exitcond_fu_55_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((exitcond_fu_55_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state6)) begin
d_address0 = tmp_3_fu_86_p1;
end else if ((1'b1 == ap_CS_fsm_state3)) begin
d_address0 = tmp_1_fu_67_p1;
end else begin
d_address0 = 'bx;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state6) | (1'b1 == ap_CS_fsm_state3))) begin
d_ce0 = 1'b1;
end else begin
d_ce0 = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state6)) begin
d_we0 = 1'b1;
end else begin
d_we0 = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((exitcond_fu_55_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state2))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state3;
end
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state4;
end
ap_ST_fsm_state4 : begin
ap_NS_fsm = ap_ST_fsm_state5;
end
ap_ST_fsm_state5 : begin
ap_NS_fsm = ap_ST_fsm_state6;
end
ap_ST_fsm_state6 : begin
ap_NS_fsm = ap_ST_fsm_state2;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state4 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state5 = ap_CS_fsm[32'd4];
assign ap_CS_fsm_state6 = ap_CS_fsm[32'd5];
assign d_d0 = tmp_2_reg_110;
assign exitcond_fu_55_p2 = ((i_reg_43 == 3'd4) ? 1'b1 : 1'b0);
assign i_1_fu_61_p2 = (i_reg_43 + 3'd1);
assign tmp_1_fu_67_p1 = i_1_reg_94;
assign tmp_2_fu_75_p2 = (d_load_reg_105 + acc);
assign tmp_3_fu_86_p1 = i_reg_43;
endmodule //array_arith
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_dram_sc_bank3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//////////////////////////////////////////////////////////////////////
// Flop repeater for L2<-> dram controller signals.
// This repeter block has
// 8 row of data flops and 4 rows of ctl/addr flops.
// The 8 data rows are placed in one column ( 39 bits wide )
// the 4 addr/ctl rows are placed in one column ( 13 bits wide )
//////////////////////////////////////////////////////////////////////
module ff_dram_sc_bank3(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_d1, dram_scbuf_ecc_r2_d1,
scbuf_dram_wr_data_r5_d1, scbuf_dram_data_vld_r5_d1,
scbuf_dram_data_mecc_r5_d1, sctag_dram_rd_req_d1,
sctag_dram_rd_dummy_req_d1, sctag_dram_rd_req_id_d1,
sctag_dram_addr_d1, sctag_dram_wr_req_d1, dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1, dram_sctag_chunk_id_r0_d1,
dram_sctag_data_vld_r0_d1, dram_sctag_rd_req_id_r0_d1,
dram_sctag_secc_err_r2_d1, dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1, dram_sctag_scb_secc_err_d1, so,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, rclk, si, se
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_d1;
output [27:0] dram_scbuf_ecc_r2_d1;
// scbuf to dram BOTTOM
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// TOP
output [63:0] scbuf_dram_wr_data_r5_d1;
output scbuf_dram_data_vld_r5_d1;
output scbuf_dram_data_mecc_r5_d1;
// sctag_dram-sctag signals INputs
// @ the bottom.
// Outputs @ the top.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
//
output sctag_dram_rd_req_d1;
output sctag_dram_rd_dummy_req_d1;
output [2:0] sctag_dram_rd_req_id_d1;
output [39:5] sctag_dram_addr_d1;
output sctag_dram_wr_req_d1;
// dram-sctag signals. Outputs @ bottom
// and Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
//
output dram_sctag_rd_ack_d1;
output dram_sctag_wr_ack_d1;
output [1:0] dram_sctag_chunk_id_r0_d1;
output dram_sctag_data_vld_r0_d1;
output [2:0] dram_sctag_rd_req_id_r0_d1;
output dram_sctag_secc_err_r2_d1 ;
output dram_sctag_mecc_err_r2_d1 ;
output dram_sctag_scb_mecc_err_d1;
output dram_sctag_scb_secc_err_d1;
input rclk;
input si, se;
output so;
// dram-scbuf signals. 8 rows of flops.
// Input at the top and output at the bottom.
dff_s #(39) ff_flop_bank0_row_0 (.q({dram_scbuf_data_r2_d1[127],
dram_scbuf_data_r2_d1[123],
dram_scbuf_data_r2_d1[119],
dram_scbuf_data_r2_d1[115],
dram_scbuf_data_r2_d1[111],
dram_scbuf_data_r2_d1[107],
dram_scbuf_data_r2_d1[103],
dram_scbuf_data_r2_d1[99],
dram_scbuf_data_r2_d1[95],
dram_scbuf_data_r2_d1[91],
dram_scbuf_data_r2_d1[87],
dram_scbuf_data_r2_d1[83],
dram_scbuf_data_r2_d1[79],
dram_scbuf_data_r2_d1[75],
dram_scbuf_data_r2_d1[71],
dram_scbuf_data_r2_d1[67],
dram_scbuf_data_r2_d1[63],
dram_scbuf_data_r2_d1[59],
dram_scbuf_data_r2_d1[55],
dram_scbuf_data_r2_d1[51],
dram_scbuf_data_r2_d1[47],
dram_scbuf_data_r2_d1[43],
dram_scbuf_data_r2_d1[39],
dram_scbuf_data_r2_d1[35],
dram_scbuf_data_r2_d1[31],
dram_scbuf_data_r2_d1[27],
dram_scbuf_data_r2_d1[23],
dram_scbuf_data_r2_d1[19],
dram_scbuf_data_r2_d1[15],
dram_scbuf_data_r2_d1[11],
dram_scbuf_data_r2_d1[7],
dram_scbuf_data_r2_d1[3],
dram_scbuf_ecc_r2_d1[27],
dram_scbuf_ecc_r2_d1[23],
dram_scbuf_ecc_r2_d1[19],
dram_scbuf_ecc_r2_d1[15],
dram_scbuf_ecc_r2_d1[11],
dram_scbuf_ecc_r2_d1[7],
dram_scbuf_ecc_r2_d1[3] }),
.din({dram_scbuf_data_r2[127],
dram_scbuf_data_r2[123],
dram_scbuf_data_r2[119],
dram_scbuf_data_r2[115],
dram_scbuf_data_r2[111],
dram_scbuf_data_r2[107],
dram_scbuf_data_r2[103],
dram_scbuf_data_r2[99],
dram_scbuf_data_r2[95],
dram_scbuf_data_r2[91],
dram_scbuf_data_r2[87],
dram_scbuf_data_r2[83],
dram_scbuf_data_r2[79],
dram_scbuf_data_r2[75],
dram_scbuf_data_r2[71],
dram_scbuf_data_r2[67],
dram_scbuf_data_r2[63],
dram_scbuf_data_r2[59],
dram_scbuf_data_r2[55],
dram_scbuf_data_r2[51],
dram_scbuf_data_r2[47],
dram_scbuf_data_r2[43],
dram_scbuf_data_r2[39],
dram_scbuf_data_r2[35],
dram_scbuf_data_r2[31],
dram_scbuf_data_r2[27],
dram_scbuf_data_r2[23],
dram_scbuf_data_r2[19],
dram_scbuf_data_r2[15],
dram_scbuf_data_r2[11],
dram_scbuf_data_r2[7],
dram_scbuf_data_r2[3],
dram_scbuf_ecc_r2[27],
dram_scbuf_ecc_r2[23],
dram_scbuf_ecc_r2[19],
dram_scbuf_ecc_r2[15],
dram_scbuf_ecc_r2[11],
dram_scbuf_ecc_r2[7],
dram_scbuf_ecc_r2[3]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_1 (.q({dram_scbuf_data_r2_d1[126],
dram_scbuf_data_r2_d1[122],
dram_scbuf_data_r2_d1[118],
dram_scbuf_data_r2_d1[114],
dram_scbuf_data_r2_d1[110],
dram_scbuf_data_r2_d1[106],
dram_scbuf_data_r2_d1[102],
dram_scbuf_data_r2_d1[98],
dram_scbuf_data_r2_d1[94],
dram_scbuf_data_r2_d1[90],
dram_scbuf_data_r2_d1[86],
dram_scbuf_data_r2_d1[82],
dram_scbuf_data_r2_d1[78],
dram_scbuf_data_r2_d1[74],
dram_scbuf_data_r2_d1[70],
dram_scbuf_data_r2_d1[66],
dram_scbuf_data_r2_d1[62],
dram_scbuf_data_r2_d1[58],
dram_scbuf_data_r2_d1[54],
dram_scbuf_data_r2_d1[50],
dram_scbuf_data_r2_d1[46],
dram_scbuf_data_r2_d1[42],
dram_scbuf_data_r2_d1[38],
dram_scbuf_data_r2_d1[34],
dram_scbuf_data_r2_d1[30],
dram_scbuf_data_r2_d1[26],
dram_scbuf_data_r2_d1[22],
dram_scbuf_data_r2_d1[18],
dram_scbuf_data_r2_d1[14],
dram_scbuf_data_r2_d1[10],
dram_scbuf_data_r2_d1[6],
dram_scbuf_data_r2_d1[2],
dram_scbuf_ecc_r2_d1[26],
dram_scbuf_ecc_r2_d1[22],
dram_scbuf_ecc_r2_d1[18],
dram_scbuf_ecc_r2_d1[14],
dram_scbuf_ecc_r2_d1[10],
dram_scbuf_ecc_r2_d1[6],
dram_scbuf_ecc_r2_d1[2] }),
.din({dram_scbuf_data_r2[126],
dram_scbuf_data_r2[122],
dram_scbuf_data_r2[118],
dram_scbuf_data_r2[114],
dram_scbuf_data_r2[110],
dram_scbuf_data_r2[106],
dram_scbuf_data_r2[102],
dram_scbuf_data_r2[98],
dram_scbuf_data_r2[94],
dram_scbuf_data_r2[90],
dram_scbuf_data_r2[86],
dram_scbuf_data_r2[82],
dram_scbuf_data_r2[78],
dram_scbuf_data_r2[74],
dram_scbuf_data_r2[70],
dram_scbuf_data_r2[66],
dram_scbuf_data_r2[62],
dram_scbuf_data_r2[58],
dram_scbuf_data_r2[54],
dram_scbuf_data_r2[50],
dram_scbuf_data_r2[46],
dram_scbuf_data_r2[42],
dram_scbuf_data_r2[38],
dram_scbuf_data_r2[34],
dram_scbuf_data_r2[30],
dram_scbuf_data_r2[26],
dram_scbuf_data_r2[22],
dram_scbuf_data_r2[18],
dram_scbuf_data_r2[14],
dram_scbuf_data_r2[10],
dram_scbuf_data_r2[6],
dram_scbuf_data_r2[2],
dram_scbuf_ecc_r2[26],
dram_scbuf_ecc_r2[22],
dram_scbuf_ecc_r2[18],
dram_scbuf_ecc_r2[14],
dram_scbuf_ecc_r2[10],
dram_scbuf_ecc_r2[6],
dram_scbuf_ecc_r2[2]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_2 (.q({dram_scbuf_data_r2_d1[125],
dram_scbuf_data_r2_d1[121],
dram_scbuf_data_r2_d1[117],
dram_scbuf_data_r2_d1[113],
dram_scbuf_data_r2_d1[109],
dram_scbuf_data_r2_d1[105],
dram_scbuf_data_r2_d1[101],
dram_scbuf_data_r2_d1[97],
dram_scbuf_data_r2_d1[93],
dram_scbuf_data_r2_d1[89],
dram_scbuf_data_r2_d1[85],
dram_scbuf_data_r2_d1[81],
dram_scbuf_data_r2_d1[77],
dram_scbuf_data_r2_d1[73],
dram_scbuf_data_r2_d1[69],
dram_scbuf_data_r2_d1[65],
dram_scbuf_data_r2_d1[61],
dram_scbuf_data_r2_d1[57],
dram_scbuf_data_r2_d1[53],
dram_scbuf_data_r2_d1[49],
dram_scbuf_data_r2_d1[45],
dram_scbuf_data_r2_d1[41],
dram_scbuf_data_r2_d1[37],
dram_scbuf_data_r2_d1[33],
dram_scbuf_data_r2_d1[29],
dram_scbuf_data_r2_d1[25],
dram_scbuf_data_r2_d1[21],
dram_scbuf_data_r2_d1[17],
dram_scbuf_data_r2_d1[13],
dram_scbuf_data_r2_d1[9],
dram_scbuf_data_r2_d1[5],
dram_scbuf_data_r2_d1[1],
dram_scbuf_ecc_r2_d1[25],
dram_scbuf_ecc_r2_d1[21],
dram_scbuf_ecc_r2_d1[17],
dram_scbuf_ecc_r2_d1[13],
dram_scbuf_ecc_r2_d1[9],
dram_scbuf_ecc_r2_d1[5],
dram_scbuf_ecc_r2_d1[1] }),
.din({dram_scbuf_data_r2[125],
dram_scbuf_data_r2[121],
dram_scbuf_data_r2[117],
dram_scbuf_data_r2[113],
dram_scbuf_data_r2[109],
dram_scbuf_data_r2[105],
dram_scbuf_data_r2[101],
dram_scbuf_data_r2[97],
dram_scbuf_data_r2[93],
dram_scbuf_data_r2[89],
dram_scbuf_data_r2[85],
dram_scbuf_data_r2[81],
dram_scbuf_data_r2[77],
dram_scbuf_data_r2[73],
dram_scbuf_data_r2[69],
dram_scbuf_data_r2[65],
dram_scbuf_data_r2[61],
dram_scbuf_data_r2[57],
dram_scbuf_data_r2[53],
dram_scbuf_data_r2[49],
dram_scbuf_data_r2[45],
dram_scbuf_data_r2[41],
dram_scbuf_data_r2[37],
dram_scbuf_data_r2[33],
dram_scbuf_data_r2[29],
dram_scbuf_data_r2[25],
dram_scbuf_data_r2[21],
dram_scbuf_data_r2[17],
dram_scbuf_data_r2[13],
dram_scbuf_data_r2[9],
dram_scbuf_data_r2[5],
dram_scbuf_data_r2[1],
dram_scbuf_ecc_r2[25],
dram_scbuf_ecc_r2[21],
dram_scbuf_ecc_r2[17],
dram_scbuf_ecc_r2[13],
dram_scbuf_ecc_r2[9],
dram_scbuf_ecc_r2[5],
dram_scbuf_ecc_r2[1]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_3 (.q({dram_scbuf_data_r2_d1[124],
dram_scbuf_data_r2_d1[120],
dram_scbuf_data_r2_d1[116],
dram_scbuf_data_r2_d1[112],
dram_scbuf_data_r2_d1[108],
dram_scbuf_data_r2_d1[104],
dram_scbuf_data_r2_d1[100],
dram_scbuf_data_r2_d1[96],
dram_scbuf_data_r2_d1[92],
dram_scbuf_data_r2_d1[88],
dram_scbuf_data_r2_d1[84],
dram_scbuf_data_r2_d1[80],
dram_scbuf_data_r2_d1[76],
dram_scbuf_data_r2_d1[72],
dram_scbuf_data_r2_d1[68],
dram_scbuf_data_r2_d1[64],
dram_scbuf_data_r2_d1[60],
dram_scbuf_data_r2_d1[56],
dram_scbuf_data_r2_d1[52],
dram_scbuf_data_r2_d1[48],
dram_scbuf_data_r2_d1[44],
dram_scbuf_data_r2_d1[40],
dram_scbuf_data_r2_d1[36],
dram_scbuf_data_r2_d1[32],
dram_scbuf_data_r2_d1[28],
dram_scbuf_data_r2_d1[24],
dram_scbuf_data_r2_d1[20],
dram_scbuf_data_r2_d1[16],
dram_scbuf_data_r2_d1[12],
dram_scbuf_data_r2_d1[8],
dram_scbuf_data_r2_d1[4],
dram_scbuf_data_r2_d1[0],
dram_scbuf_ecc_r2_d1[24],
dram_scbuf_ecc_r2_d1[20],
dram_scbuf_ecc_r2_d1[16],
dram_scbuf_ecc_r2_d1[12],
dram_scbuf_ecc_r2_d1[8],
dram_scbuf_ecc_r2_d1[4],
dram_scbuf_ecc_r2_d1[0] }),
.din({dram_scbuf_data_r2[124],
dram_scbuf_data_r2[120],
dram_scbuf_data_r2[116],
dram_scbuf_data_r2[112],
dram_scbuf_data_r2[108],
dram_scbuf_data_r2[104],
dram_scbuf_data_r2[100],
dram_scbuf_data_r2[96],
dram_scbuf_data_r2[92],
dram_scbuf_data_r2[88],
dram_scbuf_data_r2[84],
dram_scbuf_data_r2[80],
dram_scbuf_data_r2[76],
dram_scbuf_data_r2[72],
dram_scbuf_data_r2[68],
dram_scbuf_data_r2[64],
dram_scbuf_data_r2[60],
dram_scbuf_data_r2[56],
dram_scbuf_data_r2[52],
dram_scbuf_data_r2[48],
dram_scbuf_data_r2[44],
dram_scbuf_data_r2[40],
dram_scbuf_data_r2[36],
dram_scbuf_data_r2[32],
dram_scbuf_data_r2[28],
dram_scbuf_data_r2[24],
dram_scbuf_data_r2[20],
dram_scbuf_data_r2[16],
dram_scbuf_data_r2[12],
dram_scbuf_data_r2[8],
dram_scbuf_data_r2[4],
dram_scbuf_data_r2[0],
dram_scbuf_ecc_r2[24],
dram_scbuf_ecc_r2[20],
dram_scbuf_ecc_r2[16],
dram_scbuf_ecc_r2[12],
dram_scbuf_ecc_r2[8],
dram_scbuf_ecc_r2[4],
dram_scbuf_ecc_r2[0]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_bank0_row_4 (.q({scbuf_dram_wr_data_r5_d1[63],
scbuf_dram_wr_data_r5_d1[61],
scbuf_dram_wr_data_r5_d1[59],
scbuf_dram_wr_data_r5_d1[57],
scbuf_dram_wr_data_r5_d1[55],
scbuf_dram_wr_data_r5_d1[53],
scbuf_dram_wr_data_r5_d1[51],
scbuf_dram_wr_data_r5_d1[49],
scbuf_dram_wr_data_r5_d1[47],
scbuf_dram_wr_data_r5_d1[45],
scbuf_dram_wr_data_r5_d1[43],
scbuf_dram_wr_data_r5_d1[41],
scbuf_dram_wr_data_r5_d1[39],
scbuf_dram_wr_data_r5_d1[37],
scbuf_dram_wr_data_r5_d1[35],
scbuf_dram_wr_data_r5_d1[33],
scbuf_dram_wr_data_r5_d1[31],
scbuf_dram_wr_data_r5_d1[29],
scbuf_dram_wr_data_r5_d1[27],
scbuf_dram_wr_data_r5_d1[25],
scbuf_dram_wr_data_r5_d1[23],
scbuf_dram_wr_data_r5_d1[21],
scbuf_dram_wr_data_r5_d1[19],
scbuf_dram_wr_data_r5_d1[17],
scbuf_dram_wr_data_r5_d1[15],
scbuf_dram_wr_data_r5_d1[13],
scbuf_dram_wr_data_r5_d1[11],
scbuf_dram_wr_data_r5_d1[9],
scbuf_dram_wr_data_r5_d1[7],
scbuf_dram_wr_data_r5_d1[5],
scbuf_dram_wr_data_r5_d1[3],
scbuf_dram_wr_data_r5_d1[1]} ),
.din({scbuf_dram_wr_data_r5[63],
scbuf_dram_wr_data_r5[61],
scbuf_dram_wr_data_r5[59],
scbuf_dram_wr_data_r5[57],
scbuf_dram_wr_data_r5[55],
scbuf_dram_wr_data_r5[53],
scbuf_dram_wr_data_r5[51],
scbuf_dram_wr_data_r5[49],
scbuf_dram_wr_data_r5[47],
scbuf_dram_wr_data_r5[45],
scbuf_dram_wr_data_r5[43],
scbuf_dram_wr_data_r5[41],
scbuf_dram_wr_data_r5[39],
scbuf_dram_wr_data_r5[37],
scbuf_dram_wr_data_r5[35],
scbuf_dram_wr_data_r5[33],
scbuf_dram_wr_data_r5[31],
scbuf_dram_wr_data_r5[29],
scbuf_dram_wr_data_r5[27],
scbuf_dram_wr_data_r5[25],
scbuf_dram_wr_data_r5[23],
scbuf_dram_wr_data_r5[21],
scbuf_dram_wr_data_r5[19],
scbuf_dram_wr_data_r5[17],
scbuf_dram_wr_data_r5[15],
scbuf_dram_wr_data_r5[13],
scbuf_dram_wr_data_r5[11],
scbuf_dram_wr_data_r5[9],
scbuf_dram_wr_data_r5[7],
scbuf_dram_wr_data_r5[5],
scbuf_dram_wr_data_r5[3],
scbuf_dram_wr_data_r5[1]} ),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(34) ff_bank0_row_5 (.q({scbuf_dram_wr_data_r5_d1[62],
scbuf_dram_wr_data_r5_d1[60],
scbuf_dram_wr_data_r5_d1[58],
scbuf_dram_wr_data_r5_d1[56],
scbuf_dram_wr_data_r5_d1[54],
scbuf_dram_wr_data_r5_d1[52],
scbuf_dram_wr_data_r5_d1[50],
scbuf_dram_wr_data_r5_d1[48],
scbuf_dram_wr_data_r5_d1[46],
scbuf_dram_wr_data_r5_d1[44],
scbuf_dram_wr_data_r5_d1[42],
scbuf_dram_wr_data_r5_d1[40],
scbuf_dram_wr_data_r5_d1[38],
scbuf_dram_wr_data_r5_d1[36],
scbuf_dram_wr_data_r5_d1[34],
scbuf_dram_wr_data_r5_d1[32],
scbuf_dram_wr_data_r5_d1[30],
scbuf_dram_wr_data_r5_d1[28],
scbuf_dram_wr_data_r5_d1[26],
scbuf_dram_wr_data_r5_d1[24],
scbuf_dram_wr_data_r5_d1[22],
scbuf_dram_wr_data_r5_d1[20],
scbuf_dram_wr_data_r5_d1[18],
scbuf_dram_wr_data_r5_d1[16],
scbuf_dram_wr_data_r5_d1[14],
scbuf_dram_wr_data_r5_d1[12],
scbuf_dram_wr_data_r5_d1[10],
scbuf_dram_wr_data_r5_d1[8],
scbuf_dram_wr_data_r5_d1[6],
scbuf_dram_wr_data_r5_d1[4],
scbuf_dram_wr_data_r5_d1[2],
scbuf_dram_wr_data_r5_d1[0],
scbuf_dram_data_mecc_r5_d1,
scbuf_dram_data_vld_r5_d1
} ),
.din({scbuf_dram_wr_data_r5[62],
scbuf_dram_wr_data_r5[60],
scbuf_dram_wr_data_r5[58],
scbuf_dram_wr_data_r5[56],
scbuf_dram_wr_data_r5[54],
scbuf_dram_wr_data_r5[52],
scbuf_dram_wr_data_r5[50],
scbuf_dram_wr_data_r5[48],
scbuf_dram_wr_data_r5[46],
scbuf_dram_wr_data_r5[44],
scbuf_dram_wr_data_r5[42],
scbuf_dram_wr_data_r5[40],
scbuf_dram_wr_data_r5[38],
scbuf_dram_wr_data_r5[36],
scbuf_dram_wr_data_r5[34],
scbuf_dram_wr_data_r5[32],
scbuf_dram_wr_data_r5[30],
scbuf_dram_wr_data_r5[28],
scbuf_dram_wr_data_r5[26],
scbuf_dram_wr_data_r5[24],
scbuf_dram_wr_data_r5[22],
scbuf_dram_wr_data_r5[20],
scbuf_dram_wr_data_r5[18],
scbuf_dram_wr_data_r5[16],
scbuf_dram_wr_data_r5[14],
scbuf_dram_wr_data_r5[12],
scbuf_dram_wr_data_r5[10],
scbuf_dram_wr_data_r5[8],
scbuf_dram_wr_data_r5[6],
scbuf_dram_wr_data_r5[4],
scbuf_dram_wr_data_r5[2],
scbuf_dram_wr_data_r5[0],
scbuf_dram_data_mecc_r5,
scbuf_dram_data_vld_r5 }),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(41) ff_flop_bank0_col1_row012 (.q({sctag_dram_addr_d1[39:5],
sctag_dram_rd_req_id_d1[2:0],
sctag_dram_wr_req_d1,
sctag_dram_rd_dummy_req_d1,
sctag_dram_rd_req_d1}),
.din({sctag_dram_addr[39:5],
sctag_dram_rd_req_id[2:0],
sctag_dram_wr_req,
sctag_dram_rd_dummy_req,
sctag_dram_rd_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(12) ff_flop_bank0_col1_row3 (.q({dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1,
dram_sctag_chunk_id_r0_d1[1:0],
dram_sctag_data_vld_r0_d1,
dram_sctag_rd_req_id_r0_d1[2:0],
dram_sctag_secc_err_r2_d1,
dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1,
dram_sctag_scb_secc_err_d1}),
.din({dram_sctag_rd_ack,
dram_sctag_wr_ack,
dram_sctag_chunk_id_r0[1:0],
dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0[2:0],
dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2,
dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
//
// Paul Gao 06/2019
//
//
`timescale 1ps/1ps
`include "bsg_noc_links.vh"
module bsg_wormhole_router_tester
import bsg_noc_pkg::Dirs
, bsg_noc_pkg::P // proc (local node)
, bsg_noc_pkg::W // west
, bsg_noc_pkg::E // east
, bsg_noc_pkg::N // north
, bsg_noc_pkg::S; // south
import bsg_wormhole_router_pkg::StrictXY
, bsg_wormhole_router_pkg::StrictYX
, bsg_wormhole_router_pkg::StrictX
, bsg_wormhole_router_pkg::X_AllowLoopBack
, bsg_wormhole_router_pkg::XY_Allow_S
, bsg_wormhole_router_pkg::XY_Allow_N
, bsg_wormhole_router_pkg::YX_Allow_W
, bsg_wormhole_router_pkg::YX_Allow_E;
#(
// Change this one to test 1d / 2d routing
parameter dims_p = 2
// By default it routes dimension 0 first, set to 1 to route dimension n first
,parameter reverse_order_p = 0
// Determine length of fwd and rev packets
,parameter mc_node_fwd_num_channels_p = 15
,parameter mc_node_rev_num_channels_p = 7
,parameter channel_width_p = 8
,parameter x_marker_p = 4
,parameter y_marker_p = 8
,parameter x_width_p = x_marker_p
,parameter y_width_p = y_marker_p - x_marker_p
,parameter int cord_markers_pos_full_p[2:0] = '{y_marker_p, x_marker_p, 0}
// Wormhole parameters
,parameter flit_width_p = 32
// Payload flit number
,parameter len_width_p = 4
,parameter dirs_p = dims_p*2+1
,parameter int cord_markers_pos_p[dims_p:0] = cord_markers_pos_full_p[dims_p:0]
,parameter bit [1:0][dirs_p-1:0][dirs_p-1:0] routing_matrix_p =
(dims_p == 1)? StrictX
: StrictXY|XY_Allow_S|XY_Allow_N
,parameter cord_width_p = cord_markers_pos_p[dims_p]
)
();
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
// Clocks and control signals
logic mc_clk;
logic mc_reset;
logic clk;
logic reset;
logic [dirs_p-1:0] mc_en;
logic [dirs_p-1:0] mc_error;
logic [dirs_p-1:0][31:0] sent, received;
logic [dirs_p-1:0][cord_width_p-1:0] my_cord, dest_cord;
logic [dirs_p-1:0][y_marker_p-1:0] my_cord_full, dest_cord_full;
bsg_ready_and_link_sif_s [dirs_p-1:0] fwd_link_li;
bsg_ready_and_link_sif_s [dirs_p-1:0] fwd_link_lo;
bsg_ready_and_link_sif_s [dirs_p-1:0] rev_link_li;
bsg_ready_and_link_sif_s [dirs_p-1:0] rev_link_lo;
genvar i;
for (i = 0; i < dirs_p; i++)
begin : test_node_dir
bsg_wormhole_router_test_node
#(.flit_width_p(flit_width_p)
,.dims_p(dims_p)
,.cord_markers_pos_p(cord_markers_pos_p)
,.reverse_order_p(reverse_order_p)
,.len_width_p(len_width_p)
,.node_idx(i)
,.fwd_num_channels_p(mc_node_fwd_num_channels_p)
,.rev_num_channels_p(mc_node_rev_num_channels_p)
,.channel_width_p(channel_width_p)
) node_0
(.mc_clk_i (mc_clk)
,.mc_reset_i(mc_reset)
,.mc_en_i (mc_en[i])
,.error_o (mc_error[i])
,.sent_o (sent[i])
,.received_o(received[i])
,.clk_i (clk)
,.reset_i (reset)
,.my_cord_i(my_cord[i])
,.dest_cord_i(dest_cord[i])
,.link_i({fwd_link_lo[i], rev_link_lo[i]})
,.link_o({fwd_link_li[i], rev_link_li[i]})
);
end
bsg_wormhole_router
#(.flit_width_p(flit_width_p)
,.dims_p(dims_p)
,.cord_markers_pos_p(cord_markers_pos_p)
,.routing_matrix_p(routing_matrix_p)
,.reverse_order_p(reverse_order_p)
,.len_width_p(len_width_p)
) wr_fwd
(.clk_i(clk)
,.reset_i(reset)
,.my_cord_i(my_cord[P])
,.link_i(fwd_link_li)
,.link_o(fwd_link_lo)
);
bsg_wormhole_router
#(.flit_width_p(flit_width_p)
,.dims_p(dims_p)
,.cord_markers_pos_p(cord_markers_pos_p)
,.routing_matrix_p(routing_matrix_p)
,.reverse_order_p(reverse_order_p)
,.len_width_p(len_width_p)
) wr_rev
(.clk_i(clk)
,.reset_i(reset)
,.my_cord_i(my_cord[P])
,.link_i(rev_link_li)
,.link_o(rev_link_lo)
);
integer j, k, m, n, idx;
always_comb
begin
for (m = 0; m < dirs_p; m++)
begin
case(m)
P: begin
my_cord_full[m][x_marker_p-1:0] = 2;
my_cord_full[m][y_marker_p-1:x_marker_p] = 2;
end
W: begin
my_cord_full[m][x_marker_p-1:0] = 1;
my_cord_full[m][y_marker_p-1:x_marker_p] = 2;
end
E: begin
my_cord_full[m][x_marker_p-1:0] = 3;
my_cord_full[m][y_marker_p-1:x_marker_p] = 2;
end
N: begin
my_cord_full[m][x_marker_p-1:0] = 2;
my_cord_full[m][y_marker_p-1:x_marker_p] = 1;
end
S: begin
my_cord_full[m][x_marker_p-1:0] = 2;
my_cord_full[m][y_marker_p-1:x_marker_p] = 3;
end
endcase
end
end
always_comb
begin
for (n = 0; n < dirs_p; n++)
begin
my_cord [n] = my_cord_full [n][cord_width_p-1:0];
dest_cord[n] = dest_cord_full[n][cord_width_p-1:0];
end
end
wire [x_width_p-1:0] x_full_base = my_cord_full[P][x_marker_p-1:0] - 1;
wire [y_width_p-1:0] y_full_base = my_cord_full[P][y_marker_p-1:x_marker_p] - 1;
// Simulation of Clock
always #3 clk = ~clk;
always #4 mc_clk = ~mc_clk;
initial
begin
$display("Start Simulation\n");
// Init
clk = 1;
mc_clk = 1;
reset = 1;
mc_reset = 1;
mc_en = '0;
#500;
// chip reset
@(posedge clk); #1;
reset = 0;
$display("chip reset LOW");
#500;
// mc reset
@(posedge mc_clk); #1;
mc_reset = 0;
$display("mc reset LOW");
#500;
$display("directions test");
/********************* Directions Test **************************/
for (k = 0; k < dirs_p; k++)
begin
for (j = 0; j < dirs_p; j++)
begin
dest_cord_full[j] = my_cord_full[(j+k)%dirs_p];
end
// Only P has loopback path
if (k == P)
for (j = 1; j < dirs_p; j++)
begin
dest_cord_full[j] = my_cord_full[(j+k+1)%dirs_p];
end
#500;
// mc enable
@(posedge mc_clk); #1;
mc_en = '1;
$display("mc en HI");
#10000;
// mc disable
@(posedge mc_clk); #1;
mc_en = '0;
$display("mc en LO");
#2000;
end
$display("advanced directions test");
/********************* Advanced Directions Test **************************/
for (k = 0; k < (3**(dims_p)-dirs_p); k++)
begin
for (j = 0; j < dirs_p; j++)
begin
idx = (k+j)%4;
dest_cord_full[j][x_marker_p-1:0] = x_full_base + (idx/2)*2;
dest_cord_full[j][y_marker_p-1:x_marker_p] = y_full_base + (idx%2)*2;
if ((j==W & (idx/2)==0) | (j==E & (idx/2)==1)
| (j==N & (idx%2)==0) | (j==S & (idx%2)==1))
dest_cord_full[j] = my_cord_full[P];
//$display("k=%d, j=%d, idx=%d, x=%d, y=%d", k, j, idx, dest_cord_full[j][x_marker_p-1:0], dest_cord_full[j][y_marker_p-1:x_marker_p]);
end
#500;
// mc enable
@(posedge mc_clk); #1;
mc_en = '1;
$display("mc en HI");
#10000;
// mc disable
@(posedge mc_clk); #1;
mc_en = '0;
$display("mc en LO");
#2000;
end
$display("congestion test");
/********************* Congestions Test **************************/
for (k = 0; k < dirs_p; k++)
begin
for (j = 0; j < dirs_p; j++)
begin
if (j == k)
begin
dest_cord_full[j] = my_cord_full[P];
end
else
begin
dest_cord_full[j] = my_cord_full[k];
end
end
#500;
// mc enable
@(posedge mc_clk); #1;
mc_en = '1;
$display("mc en HI");
#10000;
// mc disable
@(posedge mc_clk); #1;
mc_en = '0;
$display("mc en LO");
#2000;
end
$display("loopback");
for (j = 0; j < dirs_p; j++)
begin
assert(mc_error[j] == 0)
else
begin
$error("\nFAIL... Error in loopback node %d\n", j);
$finish;
end
assert(sent[j] == received[j])
else
begin
$error("\nFAIL... Loopback node %d sent %d packets but received only %d\n", j, sent[j], received[j]);
$finish;
end
end
$display("\nPASS!\n");
for (j = 0; j < dirs_p; j++)
begin
$display("Loopback node %d sent and received %d packets\n", j, sent[j]);
end
$finish;
end
endmodule
|
// megafunction wizard: %ALTFP_LOG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_LOG
// ============================================================
// File Name: acl_fp_log.v
// Megafunction Name(s):
// ALTFP_LOG
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//`define _USE_DSP_BUILDER_FP_LOG_
`ifdef _USE_DSP_BUILDER_FP_LOG_
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=21 WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 33
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log (
enable, resetn,
clock,
dataa,
result);
input enable, resetn;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_log fpc_log_instance ( .sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(sub_wire0[31]),
.exponentout(sub_wire0[30:23]),
.mantissaout(sub_wire0[22:0]));
endmodule
`else // Use Altera FP Log function
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=21 WIDTH_EXP=8 WIDTH_MAN=23 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 33
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altbarrel_shift_t1e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [31:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
wire [159:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[159:128];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {sbit_piper1d, smux_w[127:0], data},
sel_w = {distance[4:0]},
smux_w = {((({32{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128])), ((({32{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), ((({32{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64])), ((({32{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0]))};
endmodule //acl_fp_log_altbarrel_shift_t1e
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" SHIFTDIR="LEFT" WIDTH=64 WIDTHDIST=6 data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altbarrel_shift_5fb
(
data,
distance,
result) ;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
assign
dir_w = {dir_w[5:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {smux_w[383:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_altbarrel_shift_5fb
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 SHIFTDIR="RIGHT" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 33
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altbarrel_shift_g5e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [31:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
wire [159:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 32'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[159:128];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b1,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {sbit_piper1d, smux_w[127:0], data},
sel_w = {distance[4:0]},
smux_w = {((({32{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128])), ((({32{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), ((({32{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64])), ((({32{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0]))};
endmodule //acl_fp_log_altbarrel_shift_g5e
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="AND" PIPELINE=3 WIDTH=8 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_and_or_h9b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [7:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [7:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [7:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[7], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[6] & connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] & connection_r0_w[5]), (operation_r1_w[3] & connection_r0_w[4]), (operation_r1_w[2] & connection_r0_w[3]), (operation_r1_w[1] & connection_r0_w[2]), (operation_r1_w[0] & connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] & connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_altfp_log_and_or_h9b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=8 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_and_or_v6b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [7:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [7:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [7:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[7], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_altfp_log_and_or_v6b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=23 aclr clken clock data result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_and_or_c8b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [22:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [22:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [3:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [22:0] connection_r0_w;
wire [3:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [22:0] operation_r1_w;
wire [3:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 4'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[22], operation_r1_w[17], operation_r1_w[11], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[3]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[21] | connection_r0_w[22]), (operation_r1_w[20] | connection_r0_w[21]), (operation_r1_w[19] | connection_r0_w[20]), (operation_r1_w[18] | connection_r0_w[19]), connection_r0_w[18], (operation_r1_w[16] | connection_r0_w[17]), (operation_r1_w[15] | connection_r0_w[16]), (operation_r1_w[14] | connection_r0_w[15]), (operation_r1_w[13] | connection_r0_w[14]), (operation_r1_w[12] | connection_r0_w[13]), connection_r0_w[12], (operation_r1_w[10] | connection_r0_w[11]), (operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[2] | connection_r1_w[3]), (operation_r2_w[1] | connection_r1_w[2]), (operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_altfp_log_and_or_c8b
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=39 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_s0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [38:0] dataa;
input [38:0] datab;
output [38:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [38:0] dataa;
tri0 [38:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [19:0] wire_csa_lower_result;
wire [18:0] wire_csa_upper0_result;
wire [18:0] wire_csa_upper1_result;
wire [38:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[19:0]),
.datab(datab[19:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 20,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[38:20]),
.datab(datab[38:20]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 19,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[38:20]),
.datab(datab[38:20]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 19,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({19{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({19{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_s0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=31 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_k0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [30:0] dataa;
input [30:0] datab;
output [30:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [30:0] dataa;
tri0 [30:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [15:0] wire_csa_lower_result;
wire [14:0] wire_csa_upper0_result;
wire [14:0] wire_csa_upper1_result;
wire [30:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[15:0]),
.datab(datab[15:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 16,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 15,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 15,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({15{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({15{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_k0e
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_0nc
(
dataa,
datab,
result) ;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [7:0] dataa;
tri0 [7:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] wire_add_sub1_result;
wire [7:0] result_w;
lpm_add_sub add_sub1
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 8,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_log_altfp_log_csa_0nc
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=12 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_d4b
(
dataa,
datab,
result) ;
input [11:0] dataa;
input [11:0] datab;
output [11:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [11:0] dataa;
tri0 [11:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] wire_add_sub2_result;
wire [11:0] result_w;
lpm_add_sub add_sub2
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 12,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_log_altfp_log_csa_d4b
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=6 dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_umc
(
dataa,
datab,
result) ;
input [5:0] dataa;
input [5:0] datab;
output [5:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [5:0] dataa;
tri0 [5:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] wire_add_sub3_result;
wire [5:0] result_w;
lpm_add_sub add_sub3
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 6,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_log_altfp_log_csa_umc
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_nlf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [25:0] wire_add_sub4_result;
wire [25:0] result_w;
lpm_add_sub add_sub4
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_pipeline = 1,
add_sub4.lpm_representation = "UNSIGNED",
add_sub4.lpm_width = 26,
add_sub4.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub4_result;
endmodule //acl_fp_log_altfp_log_csa_nlf
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_8kf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [7:0] dataa;
tri0 [7:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] wire_add_sub5_result;
wire [7:0] result_w;
lpm_add_sub add_sub5
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "SUB",
add_sub5.lpm_pipeline = 2,
add_sub5.lpm_representation = "UNSIGNED",
add_sub5.lpm_width = 8,
add_sub5.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub5_result;
endmodule //acl_fp_log_altfp_log_csa_8kf
//altfp_log_rr_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" WIDTH_ALMOSTLOG=39 WIDTH_Y0=25 WIDTH_Z=26 a0_in aclr almostlog clk_en clock y0_in z
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=29 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_r0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [28:0] dataa;
input [28:0] datab;
output [28:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [28:0] dataa;
tri0 [28:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [14:0] wire_csa_lower_result;
wire [13:0] wire_csa_upper0_result;
wire [13:0] wire_csa_upper1_result;
wire [28:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[14:0]),
.datab(datab[14:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 15,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 14,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 14,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({14{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({14{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_r0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_o0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_o0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=31 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_l1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [30:0] dataa;
input [30:0] datab;
output [30:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [30:0] dataa;
tri0 [30:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [15:0] wire_csa_lower_result;
wire [14:0] wire_csa_upper0_result;
wire [14:0] wire_csa_upper1_result;
wire [30:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[15:0]),
.datab(datab[15:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 16,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 15,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[30:16]),
.datab(datab[30:16]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 15,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({15{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({15{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_l1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=29 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_s1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [28:0] dataa;
input [28:0] datab;
output [28:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [28:0] dataa;
tri0 [28:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [14:0] wire_csa_lower_result;
wire [13:0] wire_csa_upper0_result;
wire [13:0] wire_csa_upper1_result;
wire [28:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[14:0]),
.datab(datab[14:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 15,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 14,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[28:15]),
.datab(datab[28:15]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 14,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({14{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({14{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_s1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_log 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsquare 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_csa_p1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_altfp_log_csa_p1e
//synthesis_resources = lpm_add_sub 27 lpm_mult 4 lpm_mux 5 reg 531
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_range_reduction_9vd
(
a0_in,
aclr,
almostlog,
clk_en,
clock,
y0_in,
z) ;
input [4:0] a0_in;
input aclr;
output [38:0] almostlog;
input clk_en;
input clock;
input [24:0] y0_in;
output [25:0] z;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [38:0] wire_add0_1_result;
wire [38:0] wire_add0_2_result;
wire [38:0] wire_add0_3_result;
wire [30:0] wire_add1_1_result;
wire [28:0] wire_add1_2_result;
wire [25:0] wire_add1_3_result;
wire [30:0] wire_sub1_1_result;
wire [28:0] wire_sub1_2_result;
wire [25:0] wire_sub1_3_result;
reg [4:0] A_pipe0_reg0;
reg [4:0] A_pipe0_reg1;
reg [4:0] A_pipe0_reg2;
reg [3:0] A_wire1_reg0;
reg [3:0] A_wire2_reg0;
reg [3:0] A_wire3_reg0;
reg [20:0] B_wire1_reg0;
reg [26:0] B_wire2_reg0;
reg [24:0] B_wire3_reg0;
reg [30:0] P_pipe0_reg0;
reg [28:0] P_pipe1_reg0;
reg [28:0] P_pipe2_reg0;
reg [22:0] P_pipe3_reg0;
reg [38:0] S_pipe22_reg0;
reg [38:0] S_pipe23_reg0;
reg [38:0] S_pipe24_reg0;
reg [38:0] S_wire1_reg0;
reg [38:0] S_wire2_reg0;
reg [38:0] S_wire3_reg0;
reg [24:0] Z_wire1_reg0;
reg [30:0] Z_wire2_reg0;
reg [28:0] Z_wire3_reg0;
wire [30:0] wire_mult0_result;
wire [28:0] wire_mult1_result;
wire [28:0] wire_mult2_result;
wire [22:0] wire_mult3_result;
wire [5:0] wire_InvTable0_result;
wire [38:0] wire_LogTable0_result;
wire [34:0] wire_LogTable1_result;
wire [31:0] wire_LogTable2_result;
wire [28:0] wire_LogTable3_result;
wire [3:0] A1_is_all_zero;
wire [3:0] A1_is_not_zero;
wire [3:0] A_all_zero2;
wire [3:0] A_all_zero3;
wire [4:0] A_pipe0;
wire [3:0] A_pipe11;
wire [3:0] A_pipe12;
wire [3:0] A_pipe13;
wire [4:0] A_wire0;
wire [3:0] A_wire1;
wire [3:0] A_wire2;
wire [3:0] A_wire3;
wire [30:0] B_pad_wire1;
wire [28:0] B_pad_wire2;
wire [25:0] B_pad_wire3;
wire [20:0] B_pipe1;
wire [26:0] B_pipe2;
wire [24:0] B_pipe3;
wire [20:0] B_wire1;
wire [26:0] B_wire2;
wire [24:0] B_wire3;
wire [30:0] epsZ_pad_wire1;
wire [28:0] epsZ_pad_wire2;
wire [25:0] epsZ_pad_wire3;
wire [30:0] epsZ_wire1;
wire [39:0] epsZ_wire2;
wire [40:0] epsZ_wire3;
wire [5:0] InvA0;
wire [38:0] L_wire0;
wire [34:0] L_wire1;
wire [31:0] L_wire2;
wire [28:0] L_wire3;
wire [30:0] mux0_data0;
wire [30:0] mux0_data1;
wire [30:0] P_pad_wire1;
wire [28:0] P_pad_wire2;
wire [25:0] P_pad_wire3;
wire [30:0] P_pipe0;
wire [28:0] P_pipe1;
wire [28:0] P_pipe2;
wire [22:0] P_pipe3;
wire [30:0] P_wire0;
wire [28:0] P_wire1;
wire [28:0] P_wire2;
wire [22:0] P_wire3;
wire [38:0] S_pipe11;
wire [38:0] S_pipe12;
wire [38:0] S_pipe13;
wire [38:0] S_pipe22;
wire [38:0] S_pipe23;
wire [38:0] S_pipe24;
wire [38:0] S_wire1;
wire [38:0] S_wire2;
wire [38:0] S_wire3;
wire [38:0] S_wire4;
wire [24:0] Z_pipe1;
wire [30:0] Z_pipe2;
wire [28:0] Z_pipe3;
wire [24:0] Z_wire1;
wire [30:0] Z_wire2;
wire [28:0] Z_wire3;
wire [25:0] Z_wire4;
wire [24:0] ZM_wire1;
wire [24:0] ZM_wire2;
wire [18:0] ZM_wire3;
acl_fp_log_altfp_log_csa_s0e add0_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe11),
.datab({{4{1'b0}}, L_wire1}),
.result(wire_add0_1_result));
acl_fp_log_altfp_log_csa_s0e add0_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe12),
.datab({{7{1'b0}}, L_wire2}),
.result(wire_add0_2_result));
acl_fp_log_altfp_log_csa_s0e add0_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe13),
.datab({{10{1'b0}}, L_wire3}),
.result(wire_add0_3_result));
acl_fp_log_altfp_log_csa_k0e add1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire1),
.datab(epsZ_pad_wire1),
.result(wire_add1_1_result));
acl_fp_log_altfp_log_csa_r0e add1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire2),
.datab(epsZ_pad_wire2),
.result(wire_add1_2_result));
acl_fp_log_altfp_log_csa_o0e add1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire3),
.datab(epsZ_pad_wire3),
.result(wire_add1_3_result));
acl_fp_log_altfp_log_csa_l1e sub1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_1_result),
.datab(P_pad_wire1),
.result(wire_sub1_1_result));
acl_fp_log_altfp_log_csa_s1e sub1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_2_result),
.datab(P_pad_wire2),
.result(wire_sub1_2_result));
acl_fp_log_altfp_log_csa_p1e sub1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_3_result),
.datab(P_pad_wire3),
.result(wire_sub1_3_result));
// synopsys translate_off
initial
A_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg0 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg0 <= A_pipe0;
// synopsys translate_off
initial
A_pipe0_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg1 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg1 <= A_pipe0_reg0;
// synopsys translate_off
initial
A_pipe0_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg2 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg2 <= A_pipe0_reg1;
// synopsys translate_off
initial
A_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire1_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire1_reg0 <= A_wire1;
// synopsys translate_off
initial
A_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire2_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire2_reg0 <= A_wire2;
// synopsys translate_off
initial
A_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire3_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire3_reg0 <= A_wire3;
// synopsys translate_off
initial
B_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire1_reg0 <= 21'b0;
else if (clk_en == 1'b1) B_wire1_reg0 <= B_wire1;
// synopsys translate_off
initial
B_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire2_reg0 <= 27'b0;
else if (clk_en == 1'b1) B_wire2_reg0 <= B_wire2;
// synopsys translate_off
initial
B_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire3_reg0 <= 25'b0;
else if (clk_en == 1'b1) B_wire3_reg0 <= B_wire3;
// synopsys translate_off
initial
P_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe0_reg0 <= 31'b0;
else if (clk_en == 1'b1) P_pipe0_reg0 <= P_pipe0;
// synopsys translate_off
initial
P_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe1_reg0 <= 29'b0;
else if (clk_en == 1'b1) P_pipe1_reg0 <= P_pipe1;
// synopsys translate_off
initial
P_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe2_reg0 <= 29'b0;
else if (clk_en == 1'b1) P_pipe2_reg0 <= P_pipe2;
// synopsys translate_off
initial
P_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) P_pipe3_reg0 <= 23'b0;
else if (clk_en == 1'b1) P_pipe3_reg0 <= P_pipe3;
// synopsys translate_off
initial
S_pipe22_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe22_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe22_reg0 <= S_pipe22;
// synopsys translate_off
initial
S_pipe23_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe23_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe23_reg0 <= S_pipe23;
// synopsys translate_off
initial
S_pipe24_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe24_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_pipe24_reg0 <= S_pipe24;
// synopsys translate_off
initial
S_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire1_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire1_reg0 <= S_wire1;
// synopsys translate_off
initial
S_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire2_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire2_reg0 <= S_wire2;
// synopsys translate_off
initial
S_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire3_reg0 <= 39'b0;
else if (clk_en == 1'b1) S_wire3_reg0 <= S_wire3;
// synopsys translate_off
initial
Z_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire1_reg0 <= 25'b0;
else if (clk_en == 1'b1) Z_wire1_reg0 <= Z_wire1;
// synopsys translate_off
initial
Z_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire2_reg0 <= 31'b0;
else if (clk_en == 1'b1) Z_wire2_reg0 <= Z_wire2;
// synopsys translate_off
initial
Z_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire3_reg0 <= 29'b0;
else if (clk_en == 1'b1) Z_wire3_reg0 <= Z_wire3;
lpm_mult mult0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(InvA0),
.datab(y0_in),
.result(wire_mult0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult0.lpm_pipeline = 2,
mult0.lpm_representation = "UNSIGNED",
mult0.lpm_widtha = 6,
mult0.lpm_widthb = 25,
mult0.lpm_widthp = 31,
mult0.lpm_type = "lpm_mult";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire1),
.datab(ZM_wire1),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 1,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 4,
mult1.lpm_widthb = 25,
mult1.lpm_widthp = 29,
mult1.lpm_type = "lpm_mult";
lpm_mult mult2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire2),
.datab(ZM_wire2),
.result(wire_mult2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult2.lpm_pipeline = 1,
mult2.lpm_representation = "UNSIGNED",
mult2.lpm_widtha = 4,
mult2.lpm_widthb = 25,
mult2.lpm_widthp = 29,
mult2.lpm_type = "lpm_mult";
lpm_mult mult3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire3),
.datab(ZM_wire3),
.result(wire_mult3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult3.lpm_pipeline = 1,
mult3.lpm_representation = "UNSIGNED",
mult3.lpm_widtha = 4,
mult3.lpm_widthb = 19,
mult3.lpm_widthp = 23,
mult3.lpm_type = "lpm_mult";
lpm_mux InvTable0
(
.data({6'b100001, {2{6'b100010}}, {2{6'b100011}}, {2{6'b100100}}, 6'b100101, {2{6'b100110}}, 6'b100111, 6'b101000, {2{6'b101001}}, 6'b101010, 6'b101011, 6'b010110, {2{6'b010111}}, {2{6'b011000}}, {2{6'b011001}}, 6'b011010, {2{6'b011011}}, 6'b011100, 6'b011101, 6'b011110, 6'b011111, {2{6'b100000}}}),
.result(wire_InvTable0_result),
.sel(a0_in)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
InvTable0.lpm_size = 32,
InvTable0.lpm_width = 6,
InvTable0.lpm_widths = 5,
InvTable0.lpm_type = "lpm_mux";
lpm_mux LogTable0
(
.data({39'b111110000001111101011001001111000110001, {2{39'b111100000111101011100111100111111111100}}, {2{39'b111010010000111100101101011101010001110}}, {2{39'b111000011101100011111000100100011101011}}, 39'b110110101101010101011010000011111100001, {2{39'b110101000000000110011111000111101011001}}, 39'b110011010101101101001010110001100001100, 39'b110001101110000000010000011100001100110, {2{39'b110000001000110111001111001001010100010}}, 39'b101110100110001010001101010100010101001, 39'b101101000101110001110101000101000111110, 39'b010111111110101111101000111011110110000, {2{39'b010101001000101010111000000111001110001}}, {2{39'b010010011010010110001000010001001101001}}, {2{39'b001111110011001000111000110110010110011}}, 39'b001101010010011111011010011110010001010, {2{39'b001010110111111010000000110101101010100}}, 39'b001000100010111100011101000001000100111, 39'b000110010011001101011110010111010101100, 39'b000100001000010110011000101101011001111, 39'b000010000010000010101110110001001111001, {2{{39{1'b0}}}}}),
.result(wire_LogTable0_result),
.sel(A_wire0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable0.lpm_size = 32,
LogTable0.lpm_width = 39,
LogTable0.lpm_widths = 5,
LogTable0.lpm_type = "lpm_mux";
lpm_mux LogTable1
(
.data({35'b11100110010110111001111001101110111, 35'b11010101011101111001011010000111110, 35'b11000100101001010101000010100100111, 35'b10110011111001001010011110010110101, 35'b10100011001101010111011010100001011, 35'b10010010100101111001100101111100011, 35'b10000010000010101110110001001111001, 35'b01110001100011110100101110110000010, 35'b01101001010101111101010100100011000, 35'b01011000111101011000010111100001101, 35'b01001000101000111110110001111111101, 35'b00111000011000101110011100001001100, 35'b00101000001100100101001111110010110, 35'b00011000000100100001001000010100010, 35'b00001000000000100000000010101010111, {35{1'b0}}}),
.result(wire_LogTable1_result),
.sel(A_pipe11)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable1.lpm_size = 16,
LogTable1.lpm_width = 35,
LogTable1.lpm_widths = 4,
LogTable1.lpm_type = "lpm_mux";
lpm_mux LogTable2
(
.data({32'b11101000110100110011111101101000, 32'b11011000101101110000111000001100, 32'b11001000100111001110001110000010, 32'b10111000100001001011111101000110, 32'b10101000011011101010000011010111, 32'b10011000010110101000011110110010, 32'b10001000010010000111001101010110, 32'b01111000001110000110001101000000, 32'b01101000001010100101011011110000, 32'b01011000000111100100110111100100, 32'b01001000000101000100011110011011, 32'b00111000000011000100001110010011, 32'b00101000000001100100000101001101, 32'b00011000000000100100000001001000, 32'b00001000000000000100000000000010, {32{1'b0}}}),
.result(wire_LogTable2_result),
.sel(A_pipe12)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable2.lpm_size = 16,
LogTable2.lpm_width = 32,
LogTable2.lpm_widths = 4,
LogTable2.lpm_type = "lpm_mux";
lpm_mux LogTable3
(
.data({29'b11101000000110100100101111111, 29'b11011000000101101100101100110, 29'b11001000000100111000101010001, 29'b10111000000100001000100111111, 29'b10101000000011011100100110000, 29'b10011000000010110100100100011, 29'b10001000000010010000100011001, 29'b01111000000001110000100010001, 29'b01101000000001010100100001011, 29'b01011000000000111100100000110, 29'b01001000000000101000100000011, 29'b00111000000000011000100000001, 29'b00101000000000001100100000000, 29'b00011000000000000100100000000, 29'b00001000000000000000100000000, {29{1'b0}}}),
.result(wire_LogTable3_result),
.sel(A_pipe13)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable3.lpm_size = 16,
LogTable3.lpm_width = 29,
LogTable3.lpm_widths = 4,
LogTable3.lpm_type = "lpm_mux";
assign
A1_is_all_zero = {(A_pipe11[3] | A1_is_all_zero[2]), (A_pipe11[2] | A1_is_all_zero[1]), (A_pipe11[1] | A1_is_all_zero[0]), A_pipe11[0]},
A1_is_not_zero = {((~ A_pipe11[3]) & A1_is_not_zero[2]), (A_pipe11[2] | A1_is_not_zero[1]), (A_pipe11[1] | A1_is_not_zero[0]), A_pipe11[0]},
A_all_zero2 = {((~ A_pipe12[3]) & A_all_zero2[2]), ((~ A_pipe12[2]) & A_all_zero2[1]), ((~ A_pipe12[1]) & A_all_zero2[0]), (~ A_pipe12[0])},
A_all_zero3 = {((~ A_pipe13[3]) & A_all_zero3[2]), ((~ A_pipe13[2]) & A_all_zero3[1]), ((~ A_pipe13[1]) & A_all_zero3[0]), (~ A_pipe13[0])},
A_pipe0 = a0_in,
A_pipe11 = A_wire1_reg0,
A_pipe12 = A_wire2_reg0,
A_pipe13 = A_wire3_reg0,
A_wire0 = A_pipe0_reg2,
A_wire1 = Z_wire1[24:21],
A_wire2 = Z_wire2[30:27],
A_wire3 = Z_wire3[28:25],
almostlog = S_wire4,
B_pad_wire1 = {1'b0, B_pipe1, {9{1'b0}}},
B_pad_wire2 = {1'b0, B_pipe2, 1'b0},
B_pad_wire3 = {1'b0, B_pipe3},
B_pipe1 = B_wire1_reg0,
B_pipe2 = B_wire2_reg0,
B_pipe3 = B_wire3_reg0,
B_wire1 = Z_wire1[20:0],
B_wire2 = Z_wire2[26:0],
B_wire3 = Z_wire3[24:0],
epsZ_pad_wire1 = epsZ_wire1[30:0],
epsZ_pad_wire2 = epsZ_wire2[39:11],
epsZ_pad_wire3 = epsZ_wire3[40:15],
epsZ_wire1 = ({31{A1_is_all_zero[3]}} & (({31{(~ A1_is_not_zero[3])}} & mux0_data0) | ({31{A1_is_not_zero[3]}} & mux0_data1))),
epsZ_wire2 = {1'b0, (~ A_all_zero2[3]), {7{1'b0}}, ({31{(~ A_all_zero2[3])}} & Z_pipe2)},
epsZ_wire3 = {1'b0, (~ A_all_zero3[3]), {10{1'b0}}, ({29{(~ A_all_zero3[3])}} & Z_pipe3)},
InvA0 = wire_InvTable0_result,
L_wire0 = wire_LogTable0_result,
L_wire1 = wire_LogTable1_result,
L_wire2 = wire_LogTable2_result,
L_wire3 = wire_LogTable3_result,
mux0_data0 = {1'b1, {4{1'b0}}, Z_pipe1, 1'b0},
mux0_data1 = {1'b0, 1'b1, {4{1'b0}}, Z_pipe1},
P_pad_wire1 = {1'b0, P_wire1, 1'b0},
P_pad_wire2 = {{4{1'b0}}, P_wire2[28:4]},
P_pad_wire3 = {{7{1'b0}}, P_wire3[22:4]},
P_pipe0 = wire_mult0_result,
P_pipe1 = wire_mult1_result,
P_pipe2 = wire_mult2_result,
P_pipe3 = wire_mult3_result,
P_wire0 = P_pipe0_reg0,
P_wire1 = P_pipe1_reg0,
P_wire2 = P_pipe2_reg0,
P_wire3 = P_pipe3_reg0,
S_pipe11 = S_wire1_reg0,
S_pipe12 = S_wire2_reg0,
S_pipe13 = S_wire3_reg0,
S_pipe22 = wire_add0_1_result,
S_pipe23 = wire_add0_2_result,
S_pipe24 = wire_add0_3_result,
S_wire1 = L_wire0,
S_wire2 = S_pipe22_reg0,
S_wire3 = S_pipe23_reg0,
S_wire4 = S_pipe24_reg0,
z = Z_wire4,
Z_pipe1 = Z_wire1_reg0,
Z_pipe2 = Z_wire2_reg0,
Z_pipe3 = Z_wire3_reg0,
Z_wire1 = P_wire0[24:0],
Z_wire2 = wire_sub1_1_result,
Z_wire3 = wire_sub1_2_result,
Z_wire4 = wire_sub1_3_result,
ZM_wire1 = Z_wire1,
ZM_wire2 = Z_wire2[30:6],
ZM_wire3 = Z_wire3[28:10];
endmodule //acl_fp_log_range_reduction_9vd
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=1 WIDTH=64 WIDTHAD=6 aclr clk_en clock data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_log_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_log_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder14_q;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
acl_fp_log_altpriority_encoder_3v7 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q));
acl_fp_log_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))};
endmodule //acl_fp_log_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [0:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
acl_fp_log_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[1:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
acl_fp_log_altpriority_encoder_3e8 altpriority_encoder17
(
.data(data[3:2]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), ((wire_altpriority_encoder17_zero & wire_altpriority_encoder16_q) | ((~ wire_altpriority_encoder17_zero) & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //acl_fp_log_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder12_q;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
acl_fp_log_altpriority_encoder_6v7 altpriority_encoder12
(
.data(data[3:0]),
.q(wire_altpriority_encoder12_q));
acl_fp_log_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[7:4]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), (({2{wire_altpriority_encoder13_zero}} & wire_altpriority_encoder12_q) | ({2{(~ wire_altpriority_encoder13_zero)}} & wire_altpriority_encoder13_q))};
endmodule //acl_fp_log_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [1:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
acl_fp_log_altpriority_encoder_6e8 altpriority_encoder18
(
.data(data[3:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
acl_fp_log_altpriority_encoder_6e8 altpriority_encoder19
(
.data(data[7:4]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({2{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({2{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //acl_fp_log_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
acl_fp_log_altpriority_encoder_bv7 altpriority_encoder10
(
.data(data[7:0]),
.q(wire_altpriority_encoder10_q));
acl_fp_log_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[15:8]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({3{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({3{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //acl_fp_log_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
wire [2:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
acl_fp_log_altpriority_encoder_be8 altpriority_encoder20
(
.data(data[7:0]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
acl_fp_log_altpriority_encoder_be8 altpriority_encoder21
(
.data(data[15:8]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
assign
q = {(~ wire_altpriority_encoder21_zero), (({3{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder20_q) | ({3{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))},
zero = (wire_altpriority_encoder20_zero & wire_altpriority_encoder21_zero);
endmodule //acl_fp_log_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_tv8
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder8_q;
wire [3:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
acl_fp_log_altpriority_encoder_r08 altpriority_encoder8
(
.data(data[15:0]),
.q(wire_altpriority_encoder8_q));
acl_fp_log_altpriority_encoder_rf8 altpriority_encoder9
(
.data(data[31:16]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({4{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({4{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //acl_fp_log_altpriority_encoder_tv8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_te9
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
acl_fp_log_altpriority_encoder_rf8 altpriority_encoder22
(
.data(data[15:0]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
acl_fp_log_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[31:16]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
assign
q = {(~ wire_altpriority_encoder23_zero), (({4{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))},
zero = (wire_altpriority_encoder22_zero & wire_altpriority_encoder23_zero);
endmodule //acl_fp_log_altpriority_encoder_te9
//synthesis_resources = reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_uja
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_altpriority_encoder6_q;
wire [4:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
reg [5:0] pipeline_q_dffe;
wire [5:0] tmp_q_wire;
acl_fp_log_altpriority_encoder_tv8 altpriority_encoder6
(
.data(data[31:0]),
.q(wire_altpriority_encoder6_q));
acl_fp_log_altpriority_encoder_te9 altpriority_encoder7
(
.data(data[63:32]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 6'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder7_zero), (({5{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({5{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //acl_fp_log_altpriority_encoder_uja
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder24_q;
wire [3:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
acl_fp_log_altpriority_encoder_r08 altpriority_encoder24
(
.data(data[15:0]),
.q(wire_altpriority_encoder24_q));
acl_fp_log_altpriority_encoder_rf8 altpriority_encoder25
(
.data(data[31:16]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
assign
q = {(~ wire_altpriority_encoder25_zero), (({4{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder24_q) | ({4{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))};
endmodule //acl_fp_log_altpriority_encoder_q08
//synthesis_resources = altsquare 1 lpm_add_sub 42 lpm_mult 5 lpm_mux 5 mux21 31 reg 1563
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_altfp_log_h5b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [31:0] data;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_Lshiftsmall_result;
wire [63:0] wire_lzc_norm_L_result;
wire [31:0] wire_Rshiftsmall_result;
wire wire_exp_nan_result;
wire wire_exp_zero_result;
wire wire_man_inf_result;
wire wire_man_nan_result;
wire [38:0] wire_add1_result;
wire [30:0] wire_add2_result;
wire [7:0] wire_exp_biase_sub_result;
wire [11:0] wire_sub1_result;
wire [7:0] wire_sub2_result;
wire [5:0] wire_sub3_result;
wire [25:0] wire_sub4_result;
wire [7:0] wire_sub5_result;
wire [7:0] wire_sub6_result;
wire [38:0] wire_range_reduction_almostlog;
wire [25:0] wire_range_reduction_z;
wire [5:0] wire_lzc_norm_E_q;
wire [4:0] wire_lzoc_q;
wire [13:0] wire_squarer_result;
reg [34:0] absELog2_pipe_reg0;
reg [34:0] absELog2_pipe_reg1;
reg [34:0] absELog2_pipe_reg2;
reg [11:0] absZ0_pipe_reg0;
reg [11:0] absZ0_pipe_reg1;
reg [11:0] absZ0_pipe_reg2;
reg [11:0] absZ0_pipe_reg3;
reg [11:0] absZ0_pipe_reg4;
reg [11:0] absZ0_pipe_reg5;
reg [11:0] absZ0_pipe_reg6;
reg [11:0] absZ0_pipe_reg7;
reg [11:0] absZ0_pipe_reg8;
reg [11:0] absZ0_pipe_reg9;
reg [11:0] absZ0s_pipe1_reg0;
reg [11:0] absZ0s_pipe1_reg1;
reg [11:0] absZ0s_pipe1_reg2;
reg [11:0] absZ0s_pipe1_reg3;
reg [11:0] absZ0s_reg0;
reg [38:0] almostLog_pipe_reg0;
reg [38:0] almostLog_pipe_reg1;
reg [38:0] almostLog_pipe_reg2;
reg [0:0] doRR_reg0;
reg [0:0] doRR_reg1;
reg [7:0] E0_pipe_reg0;
reg [7:0] E0_pipe_reg1;
reg [7:0] E0_pipe_reg2;
reg [7:0] E0_pipe_reg3;
reg [7:0] E0_pipe_reg4;
reg [7:0] E0_pipe_reg5;
reg [7:0] E0_pipe_reg6;
reg [7:0] E0_pipe_reg7;
reg [7:0] E0_pipe_reg8;
reg [7:0] E0_pipe_reg9;
reg [4:0] E_normal_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg1;
reg [0:0] exp_is_ebiase_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg0;
reg [0:0] input_is_infinity_pipe_reg1;
reg [0:0] input_is_infinity_pipe_reg10;
reg [0:0] input_is_infinity_pipe_reg11;
reg [0:0] input_is_infinity_pipe_reg12;
reg [0:0] input_is_infinity_pipe_reg13;
reg [0:0] input_is_infinity_pipe_reg14;
reg [0:0] input_is_infinity_pipe_reg15;
reg [0:0] input_is_infinity_pipe_reg16;
reg [0:0] input_is_infinity_pipe_reg17;
reg [0:0] input_is_infinity_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg3;
reg [0:0] input_is_infinity_pipe_reg4;
reg [0:0] input_is_infinity_pipe_reg5;
reg [0:0] input_is_infinity_pipe_reg6;
reg [0:0] input_is_infinity_pipe_reg7;
reg [0:0] input_is_infinity_pipe_reg8;
reg [0:0] input_is_infinity_pipe_reg9;
reg [0:0] input_is_nan_pipe_reg0;
reg [0:0] input_is_nan_pipe_reg1;
reg [0:0] input_is_nan_pipe_reg10;
reg [0:0] input_is_nan_pipe_reg11;
reg [0:0] input_is_nan_pipe_reg12;
reg [0:0] input_is_nan_pipe_reg13;
reg [0:0] input_is_nan_pipe_reg14;
reg [0:0] input_is_nan_pipe_reg15;
reg [0:0] input_is_nan_pipe_reg16;
reg [0:0] input_is_nan_pipe_reg17;
reg [0:0] input_is_nan_pipe_reg2;
reg [0:0] input_is_nan_pipe_reg3;
reg [0:0] input_is_nan_pipe_reg4;
reg [0:0] input_is_nan_pipe_reg5;
reg [0:0] input_is_nan_pipe_reg6;
reg [0:0] input_is_nan_pipe_reg7;
reg [0:0] input_is_nan_pipe_reg8;
reg [0:0] input_is_nan_pipe_reg9;
reg [0:0] input_is_one_pipe_reg0;
reg [0:0] input_is_one_pipe_reg1;
reg [0:0] input_is_one_pipe_reg10;
reg [0:0] input_is_one_pipe_reg11;
reg [0:0] input_is_one_pipe_reg12;
reg [0:0] input_is_one_pipe_reg13;
reg [0:0] input_is_one_pipe_reg14;
reg [0:0] input_is_one_pipe_reg15;
reg [0:0] input_is_one_pipe_reg16;
reg [0:0] input_is_one_pipe_reg17;
reg [0:0] input_is_one_pipe_reg2;
reg [0:0] input_is_one_pipe_reg3;
reg [0:0] input_is_one_pipe_reg4;
reg [0:0] input_is_one_pipe_reg5;
reg [0:0] input_is_one_pipe_reg6;
reg [0:0] input_is_one_pipe_reg7;
reg [0:0] input_is_one_pipe_reg8;
reg [0:0] input_is_one_pipe_reg9;
reg [0:0] input_is_zero_pipe_reg0;
reg [0:0] input_is_zero_pipe_reg1;
reg [0:0] input_is_zero_pipe_reg10;
reg [0:0] input_is_zero_pipe_reg11;
reg [0:0] input_is_zero_pipe_reg12;
reg [0:0] input_is_zero_pipe_reg13;
reg [0:0] input_is_zero_pipe_reg14;
reg [0:0] input_is_zero_pipe_reg15;
reg [0:0] input_is_zero_pipe_reg16;
reg [0:0] input_is_zero_pipe_reg17;
reg [0:0] input_is_zero_pipe_reg2;
reg [0:0] input_is_zero_pipe_reg3;
reg [0:0] input_is_zero_pipe_reg4;
reg [0:0] input_is_zero_pipe_reg5;
reg [0:0] input_is_zero_pipe_reg6;
reg [0:0] input_is_zero_pipe_reg7;
reg [0:0] input_is_zero_pipe_reg8;
reg [0:0] input_is_zero_pipe_reg9;
reg [46:0] Log_normal_normd_pipe_reg0;
reg [46:0] Log_normal_reg0;
reg [26:0] Log_small_normd_pipe_reg0;
reg [26:0] Log_small_normd_pipe_reg1;
reg [5:0] Lshiftval_reg0;
reg [5:0] Lshiftval_reg1;
reg [5:0] Lshiftval_reg2;
reg [5:0] Lshiftval_reg3;
reg [4:0] lzo_pipe1_reg0;
reg [4:0] lzo_pipe1_reg1;
reg [4:0] lzo_pipe1_reg2;
reg [4:0] lzo_pipe1_reg3;
reg [4:0] lzo_pipe1_reg4;
reg [4:0] lzo_pipe1_reg5;
reg [4:0] lzo_pipe1_reg6;
reg [4:0] lzo_pipe1_reg7;
reg [4:0] lzo_pipe1_reg8;
reg [4:0] lzo_pipe1_reg9;
reg [4:0] lzo_reg0;
reg [4:0] lzo_reg1;
reg [4:0] lzo_reg2;
reg [4:0] lzo_reg3;
reg [4:0] lzo_reg4;
reg [4:0] lzo_reg5;
reg [4:0] lzo_reg6;
reg [4:0] lzo_reg7;
reg [0:0] sign_data_reg0;
reg [0:0] sign_data_reg1;
reg [0:0] sign_data_reg2;
reg [0:0] small_flag_pipe_reg0;
reg [0:0] small_flag_pipe_reg1;
reg [0:0] small_flag_pipe_reg2;
reg [0:0] small_flag_pipe_reg3;
reg [0:0] small_flag_pipe_reg4;
reg [0:0] small_flag_pipe_reg5;
reg [0:0] small_flag_pipe_reg6;
reg [0:0] small_flag_pipe_reg7;
reg [0:0] small_flag_pipe_reg8;
reg [0:0] small_flag_pipe_reg9;
reg [0:0] sR_pipe1_reg0;
reg [0:0] sR_pipe1_reg1;
reg [0:0] sR_pipe1_reg2;
reg [0:0] sR_pipe1_reg3;
reg [0:0] sR_pipe1_reg4;
reg [0:0] sR_pipe1_reg5;
reg [0:0] sR_pipe1_reg6;
reg [0:0] sR_pipe1_reg7;
reg [0:0] sR_pipe1_reg8;
reg [0:0] sR_pipe1_reg9;
reg [0:0] sR_pipe2_reg0;
reg [0:0] sR_pipe2_reg1;
reg [0:0] sR_pipe2_reg2;
reg [0:0] sR_pipe2_reg3;
reg [0:0] sR_pipe2_reg4;
reg [0:0] sR_pipe2_reg5;
reg [0:0] sR_pipe3_reg0;
reg [0:0] sR_pipe3_reg1;
reg [0:0] sR_pipe3_reg2;
reg [0:0] sR_pipe3_reg3;
reg [0:0] sR_pipe3_reg4;
reg [13:0] Z2o2_pipe_reg0;
reg [13:0] Z2o2_small_s_pipe_reg0;
reg [25:0] Zfinal_reg0;
reg [25:0] Zfinal_reg1;
wire [28:0] wire_addsub1_result;
wire [46:0] wire_addsub2_result;
wire [34:0] wire_mult1_result;
wire [30:0]wire_mux_result0a_dataout;
wire [7:0] absE;
wire [34:0] absELog2;
wire [46:0] absELog2_pad;
wire [34:0] absELog2_pipe;
wire [11:0] absZ0;
wire [11:0] absZ0_pipe;
wire [11:0] absZ0s;
wire [11:0] absZ0s_pipe1;
wire [11:0] absZ0s_pipe2;
wire aclr;
wire [38:0] almostLog;
wire [38:0] almostLog_pipe;
wire [7:0] data_exp_is_ebiase;
wire doRR;
wire doRR_pipe;
wire [7:0] E0;
wire [7:0] E0_is_zero;
wire [7:0] E0_pipe;
wire [1:0] E0_sub;
wire [7:0] E0offset;
wire [4:0] E_normal;
wire [4:0] E_normal_pipe;
wire [7:0] E_small;
wire [30:0] EFR;
wire [7:0] ER;
wire exp_all_one;
wire exp_all_zero;
wire [7:0] exp_biase;
wire [7:0] exp_data;
wire exp_is_ebiase;
wire exp_is_ebiase_pipe;
wire First_bit;
wire input_is_infinity;
wire input_is_infinity_pipe;
wire input_is_nan;
wire input_is_nan_pipe;
wire input_is_one;
wire input_is_one_pipe;
wire input_is_zero;
wire input_is_zero_pipe;
wire [25:0] Log1p_normal;
wire [26:0] Log2;
wire [26:0] Log_g;
wire [46:0] Log_normal;
wire [46:0] Log_normal_normd;
wire [46:0] Log_normal_normd_pipe;
wire [46:0] Log_normal_pipe;
wire [28:0] Log_small;
wire [26:0] Log_small1;
wire [26:0] Log_small2;
wire [26:0] Log_small_normd;
wire [26:0] Log_small_normd_pipe;
wire [38:0] LogF_normal;
wire [46:0] LogF_normal_pad;
wire [5:0] Lshiftval;
wire [4:0] lzo;
wire [4:0] lzo_pipe1;
wire [4:0] lzo_pipe2;
wire [24:0] man_above_half;
wire man_all_zero;
wire [24:0] man_below_half;
wire [22:0] man_data;
wire man_not_zero;
wire [4:0] pfinal_s;
wire round;
wire [5:0] Rshiftval;
wire sign_data;
wire sign_data_pipe;
wire small_flag;
wire small_flag_pipe;
wire [12:0] squarerIn;
wire [12:0] squarerIn0;
wire [12:0] squarerIn1;
wire sR;
wire sR_pipe1;
wire sR_pipe2;
wire sR_pipe3;
wire [2:0] sticky;
wire [24:0] Y0;
wire [13:0] Z2o2;
wire [13:0] Z2o2_pipe;
wire [28:0] Z2o2_small;
wire [13:0] Z2o2_small_s;
wire [13:0] Z2o2_small_s_pipe;
wire [28:0] Z_small;
wire [25:0] Zfinal;
wire [25:0] Zfinal_pipe;
acl_fp_log_altbarrel_shift_t1e Lshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({absZ0, {20{1'b0}}}),
.distance(Lshiftval[4:0]),
.result(wire_Lshiftsmall_result));
acl_fp_log_altbarrel_shift_5fb lzc_norm_L
(
.data({Log_normal_pipe, {17{1'b0}}}),
.distance((~ wire_lzc_norm_E_q)),
.result(wire_lzc_norm_L_result));
acl_fp_log_altbarrel_shift_g5e Rshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Z2o2, {18{1'b0}}}),
.distance(Rshiftval[4:0]),
.result(wire_Rshiftsmall_result));
acl_fp_log_altfp_log_and_or_h9b exp_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_nan_result));
acl_fp_log_altfp_log_and_or_v6b exp_zero
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_zero_result));
acl_fp_log_altfp_log_and_or_c8b man_inf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_inf_result));
acl_fp_log_altfp_log_and_or_c8b man_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_nan_result));
acl_fp_log_altfp_log_csa_s0e add1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({{13{1'b0}}, Log1p_normal}),
.datab(almostLog),
.result(wire_add1_result));
acl_fp_log_altfp_log_csa_k0e add2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({ER, Log_g[26:4]}),
.datab({{30{1'b0}}, round}),
.result(wire_add2_result));
acl_fp_log_altfp_log_csa_0nc exp_biase_sub
(
.dataa(exp_data),
.datab(exp_biase),
.result(wire_exp_biase_sub_result));
acl_fp_log_altfp_log_csa_d4b sub1
(
.dataa({12{1'b0}}),
.datab(Y0[11:0]),
.result(wire_sub1_result));
acl_fp_log_altfp_log_csa_0nc sub2
(
.dataa({8{1'b0}}),
.datab(E0),
.result(wire_sub2_result));
acl_fp_log_altfp_log_csa_umc sub3
(
.dataa({1'b0, lzo}),
.datab({1'b0, pfinal_s}),
.result(wire_sub3_result));
acl_fp_log_altfp_log_csa_nlf sub4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(Zfinal_pipe),
.datab({{14{1'b0}}, Z2o2[13:2]}),
.result(wire_sub4_result));
acl_fp_log_altfp_log_csa_8kf sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b0, {5{1'b1}}, E0_sub}),
.datab({{3{1'b0}}, lzo_pipe2}),
.result(wire_sub5_result));
acl_fp_log_altfp_log_csa_0nc sub6
(
.dataa(E0offset),
.datab({{3{1'b0}}, (~ E_normal)}),
.result(wire_sub6_result));
acl_fp_log_range_reduction_9vd range_reduction
(
.a0_in(man_data[22:18]),
.aclr(aclr),
.almostlog(wire_range_reduction_almostlog),
.clk_en(clk_en),
.clock(clock),
.y0_in(Y0),
.z(wire_range_reduction_z));
acl_fp_log_altpriority_encoder_uja lzc_norm_E
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Log_normal, 17'b00000000000000001}),
.q(wire_lzc_norm_E_q));
acl_fp_log_altpriority_encoder_q08 lzoc
(
.data({({23{First_bit}} ^ Y0[23:1]), 9'b000000001}),
.q(wire_lzoc_q));
altsquare squarer
(
.aclr(aclr),
.clock(clock),
.data(squarerIn),
.ena(clk_en),
.result(wire_squarer_result));
defparam
squarer.data_width = 13,
squarer.pipeline = 1,
squarer.representation = "UNSIGNED",
squarer.result_alignment = "MSB",
squarer.result_width = 14,
squarer.lpm_type = "altsquare";
// synopsys translate_off
initial
absELog2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg0 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg0 <= absELog2_pipe;
// synopsys translate_off
initial
absELog2_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg1 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg1 <= absELog2_pipe_reg0;
// synopsys translate_off
initial
absELog2_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg2 <= 35'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg2 <= absELog2_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg0 <= absZ0_pipe;
// synopsys translate_off
initial
absZ0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg1 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg1 <= absZ0_pipe_reg0;
// synopsys translate_off
initial
absZ0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg2 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg2 <= absZ0_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg3 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg3 <= absZ0_pipe_reg2;
// synopsys translate_off
initial
absZ0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg4 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg4 <= absZ0_pipe_reg3;
// synopsys translate_off
initial
absZ0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg5 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg5 <= absZ0_pipe_reg4;
// synopsys translate_off
initial
absZ0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg6 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg6 <= absZ0_pipe_reg5;
// synopsys translate_off
initial
absZ0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg7 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg7 <= absZ0_pipe_reg6;
// synopsys translate_off
initial
absZ0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg8 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg8 <= absZ0_pipe_reg7;
// synopsys translate_off
initial
absZ0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg9 <= 12'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg9 <= absZ0_pipe_reg8;
// synopsys translate_off
initial
absZ0s_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg0 <= absZ0s_pipe1;
// synopsys translate_off
initial
absZ0s_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg1 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg1 <= absZ0s_pipe1_reg0;
// synopsys translate_off
initial
absZ0s_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg2 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg2 <= absZ0s_pipe1_reg1;
// synopsys translate_off
initial
absZ0s_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg3 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg3 <= absZ0s_pipe1_reg2;
// synopsys translate_off
initial
absZ0s_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_reg0 <= 12'b0;
else if (clk_en == 1'b1) absZ0s_reg0 <= absZ0s;
// synopsys translate_off
initial
almostLog_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg0 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg0 <= almostLog_pipe;
// synopsys translate_off
initial
almostLog_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg1 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg1 <= almostLog_pipe_reg0;
// synopsys translate_off
initial
almostLog_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg2 <= 39'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg2 <= almostLog_pipe_reg1;
// synopsys translate_off
initial
doRR_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg0 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg0 <= doRR;
// synopsys translate_off
initial
doRR_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg1 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg1 <= doRR_reg0;
// synopsys translate_off
initial
E0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg0 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg0 <= E0_pipe;
// synopsys translate_off
initial
E0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg1 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg1 <= E0_pipe_reg0;
// synopsys translate_off
initial
E0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg2 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg2 <= E0_pipe_reg1;
// synopsys translate_off
initial
E0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg3 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg3 <= E0_pipe_reg2;
// synopsys translate_off
initial
E0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg4 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg4 <= E0_pipe_reg3;
// synopsys translate_off
initial
E0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg5 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg5 <= E0_pipe_reg4;
// synopsys translate_off
initial
E0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg6 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg6 <= E0_pipe_reg5;
// synopsys translate_off
initial
E0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg7 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg7 <= E0_pipe_reg6;
// synopsys translate_off
initial
E0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg8 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg8 <= E0_pipe_reg7;
// synopsys translate_off
initial
E0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg9 <= 8'b0;
else if (clk_en == 1'b1) E0_pipe_reg9 <= E0_pipe_reg8;
// synopsys translate_off
initial
E_normal_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E_normal_pipe_reg0 <= 5'b0;
else if (clk_en == 1'b1) E_normal_pipe_reg0 <= E_normal_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg0 <= exp_is_ebiase_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg1 <= exp_is_ebiase_pipe_reg0;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg2 <= exp_is_ebiase_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg0 <= input_is_infinity_pipe;
// synopsys translate_off
initial
input_is_infinity_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg1 <= input_is_infinity_pipe_reg0;
// synopsys translate_off
initial
input_is_infinity_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg10 <= input_is_infinity_pipe_reg9;
// synopsys translate_off
initial
input_is_infinity_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg11 <= input_is_infinity_pipe_reg10;
// synopsys translate_off
initial
input_is_infinity_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg12 <= input_is_infinity_pipe_reg11;
// synopsys translate_off
initial
input_is_infinity_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg13 <= input_is_infinity_pipe_reg12;
// synopsys translate_off
initial
input_is_infinity_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg14 <= input_is_infinity_pipe_reg13;
// synopsys translate_off
initial
input_is_infinity_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg15 <= input_is_infinity_pipe_reg14;
// synopsys translate_off
initial
input_is_infinity_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg16 <= input_is_infinity_pipe_reg15;
// synopsys translate_off
initial
input_is_infinity_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg17 <= input_is_infinity_pipe_reg16;
// synopsys translate_off
initial
input_is_infinity_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg2 <= input_is_infinity_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg3 <= input_is_infinity_pipe_reg2;
// synopsys translate_off
initial
input_is_infinity_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg4 <= input_is_infinity_pipe_reg3;
// synopsys translate_off
initial
input_is_infinity_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg5 <= input_is_infinity_pipe_reg4;
// synopsys translate_off
initial
input_is_infinity_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg6 <= input_is_infinity_pipe_reg5;
// synopsys translate_off
initial
input_is_infinity_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg7 <= input_is_infinity_pipe_reg6;
// synopsys translate_off
initial
input_is_infinity_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg8 <= input_is_infinity_pipe_reg7;
// synopsys translate_off
initial
input_is_infinity_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg9 <= input_is_infinity_pipe_reg8;
// synopsys translate_off
initial
input_is_nan_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg0 <= input_is_nan_pipe;
// synopsys translate_off
initial
input_is_nan_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg1 <= input_is_nan_pipe_reg0;
// synopsys translate_off
initial
input_is_nan_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg10 <= input_is_nan_pipe_reg9;
// synopsys translate_off
initial
input_is_nan_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg11 <= input_is_nan_pipe_reg10;
// synopsys translate_off
initial
input_is_nan_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg12 <= input_is_nan_pipe_reg11;
// synopsys translate_off
initial
input_is_nan_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg13 <= input_is_nan_pipe_reg12;
// synopsys translate_off
initial
input_is_nan_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg14 <= input_is_nan_pipe_reg13;
// synopsys translate_off
initial
input_is_nan_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg15 <= input_is_nan_pipe_reg14;
// synopsys translate_off
initial
input_is_nan_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg16 <= input_is_nan_pipe_reg15;
// synopsys translate_off
initial
input_is_nan_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg17 <= input_is_nan_pipe_reg16;
// synopsys translate_off
initial
input_is_nan_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg2 <= input_is_nan_pipe_reg1;
// synopsys translate_off
initial
input_is_nan_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg3 <= input_is_nan_pipe_reg2;
// synopsys translate_off
initial
input_is_nan_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg4 <= input_is_nan_pipe_reg3;
// synopsys translate_off
initial
input_is_nan_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg5 <= input_is_nan_pipe_reg4;
// synopsys translate_off
initial
input_is_nan_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg6 <= input_is_nan_pipe_reg5;
// synopsys translate_off
initial
input_is_nan_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg7 <= input_is_nan_pipe_reg6;
// synopsys translate_off
initial
input_is_nan_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg8 <= input_is_nan_pipe_reg7;
// synopsys translate_off
initial
input_is_nan_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg9 <= input_is_nan_pipe_reg8;
// synopsys translate_off
initial
input_is_one_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg0 <= input_is_one_pipe;
// synopsys translate_off
initial
input_is_one_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg1 <= input_is_one_pipe_reg0;
// synopsys translate_off
initial
input_is_one_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg10 <= input_is_one_pipe_reg9;
// synopsys translate_off
initial
input_is_one_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg11 <= input_is_one_pipe_reg10;
// synopsys translate_off
initial
input_is_one_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg12 <= input_is_one_pipe_reg11;
// synopsys translate_off
initial
input_is_one_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg13 <= input_is_one_pipe_reg12;
// synopsys translate_off
initial
input_is_one_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg14 <= input_is_one_pipe_reg13;
// synopsys translate_off
initial
input_is_one_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg15 <= input_is_one_pipe_reg14;
// synopsys translate_off
initial
input_is_one_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg16 <= input_is_one_pipe_reg15;
// synopsys translate_off
initial
input_is_one_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg17 <= input_is_one_pipe_reg16;
// synopsys translate_off
initial
input_is_one_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg2 <= input_is_one_pipe_reg1;
// synopsys translate_off
initial
input_is_one_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg3 <= input_is_one_pipe_reg2;
// synopsys translate_off
initial
input_is_one_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg4 <= input_is_one_pipe_reg3;
// synopsys translate_off
initial
input_is_one_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg5 <= input_is_one_pipe_reg4;
// synopsys translate_off
initial
input_is_one_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg6 <= input_is_one_pipe_reg5;
// synopsys translate_off
initial
input_is_one_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg7 <= input_is_one_pipe_reg6;
// synopsys translate_off
initial
input_is_one_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg8 <= input_is_one_pipe_reg7;
// synopsys translate_off
initial
input_is_one_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg9 <= input_is_one_pipe_reg8;
// synopsys translate_off
initial
input_is_zero_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg0 <= input_is_zero_pipe;
// synopsys translate_off
initial
input_is_zero_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg1 <= input_is_zero_pipe_reg0;
// synopsys translate_off
initial
input_is_zero_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg10 <= input_is_zero_pipe_reg9;
// synopsys translate_off
initial
input_is_zero_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg11 <= input_is_zero_pipe_reg10;
// synopsys translate_off
initial
input_is_zero_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg12 <= input_is_zero_pipe_reg11;
// synopsys translate_off
initial
input_is_zero_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg13 <= input_is_zero_pipe_reg12;
// synopsys translate_off
initial
input_is_zero_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg14 <= input_is_zero_pipe_reg13;
// synopsys translate_off
initial
input_is_zero_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg15 <= input_is_zero_pipe_reg14;
// synopsys translate_off
initial
input_is_zero_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg16 <= input_is_zero_pipe_reg15;
// synopsys translate_off
initial
input_is_zero_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg17 <= input_is_zero_pipe_reg16;
// synopsys translate_off
initial
input_is_zero_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg2 <= input_is_zero_pipe_reg1;
// synopsys translate_off
initial
input_is_zero_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg3 <= input_is_zero_pipe_reg2;
// synopsys translate_off
initial
input_is_zero_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg4 <= input_is_zero_pipe_reg3;
// synopsys translate_off
initial
input_is_zero_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg5 <= input_is_zero_pipe_reg4;
// synopsys translate_off
initial
input_is_zero_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg6 <= input_is_zero_pipe_reg5;
// synopsys translate_off
initial
input_is_zero_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg7 <= input_is_zero_pipe_reg6;
// synopsys translate_off
initial
input_is_zero_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg8 <= input_is_zero_pipe_reg7;
// synopsys translate_off
initial
input_is_zero_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg9 <= input_is_zero_pipe_reg8;
// synopsys translate_off
initial
Log_normal_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_normd_pipe_reg0 <= 47'b0;
else if (clk_en == 1'b1) Log_normal_normd_pipe_reg0 <= Log_normal_normd_pipe;
// synopsys translate_off
initial
Log_normal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_reg0 <= 47'b0;
else if (clk_en == 1'b1) Log_normal_reg0 <= Log_normal;
// synopsys translate_off
initial
Log_small_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg0 <= 27'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg0 <= Log_small_normd_pipe;
// synopsys translate_off
initial
Log_small_normd_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg1 <= 27'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg1 <= Log_small_normd_pipe_reg0;
// synopsys translate_off
initial
Lshiftval_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg0 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg0 <= Lshiftval;
// synopsys translate_off
initial
Lshiftval_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg1 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg1 <= Lshiftval_reg0;
// synopsys translate_off
initial
Lshiftval_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg2 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg2 <= Lshiftval_reg1;
// synopsys translate_off
initial
Lshiftval_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg3 <= 6'b0;
else if (clk_en == 1'b1) Lshiftval_reg3 <= Lshiftval_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg0 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg0 <= lzo_pipe1;
// synopsys translate_off
initial
lzo_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg1 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg1 <= lzo_pipe1_reg0;
// synopsys translate_off
initial
lzo_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg2 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg2 <= lzo_pipe1_reg1;
// synopsys translate_off
initial
lzo_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg3 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg3 <= lzo_pipe1_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg4 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg4 <= lzo_pipe1_reg3;
// synopsys translate_off
initial
lzo_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg5 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg5 <= lzo_pipe1_reg4;
// synopsys translate_off
initial
lzo_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg6 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg6 <= lzo_pipe1_reg5;
// synopsys translate_off
initial
lzo_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg7 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg7 <= lzo_pipe1_reg6;
// synopsys translate_off
initial
lzo_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg8 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg8 <= lzo_pipe1_reg7;
// synopsys translate_off
initial
lzo_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg9 <= 5'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg9 <= lzo_pipe1_reg8;
// synopsys translate_off
initial
lzo_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg0 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg0 <= lzo;
// synopsys translate_off
initial
lzo_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg1 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg1 <= lzo_reg0;
// synopsys translate_off
initial
lzo_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg2 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg2 <= lzo_reg1;
// synopsys translate_off
initial
lzo_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg3 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg3 <= lzo_reg2;
// synopsys translate_off
initial
lzo_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg4 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg4 <= lzo_reg3;
// synopsys translate_off
initial
lzo_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg5 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg5 <= lzo_reg4;
// synopsys translate_off
initial
lzo_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg6 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg6 <= lzo_reg5;
// synopsys translate_off
initial
lzo_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg7 <= 5'b0;
else if (clk_en == 1'b1) lzo_reg7 <= lzo_reg6;
// synopsys translate_off
initial
sign_data_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg0 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg0 <= sign_data;
// synopsys translate_off
initial
sign_data_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg1 <= sign_data_reg0;
// synopsys translate_off
initial
sign_data_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg2 <= sign_data_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg0 <= small_flag_pipe;
// synopsys translate_off
initial
small_flag_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg1 <= small_flag_pipe_reg0;
// synopsys translate_off
initial
small_flag_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg2 <= small_flag_pipe_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg3 <= small_flag_pipe_reg2;
// synopsys translate_off
initial
small_flag_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg4 <= small_flag_pipe_reg3;
// synopsys translate_off
initial
small_flag_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg5 <= small_flag_pipe_reg4;
// synopsys translate_off
initial
small_flag_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg6 <= small_flag_pipe_reg5;
// synopsys translate_off
initial
small_flag_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg7 <= small_flag_pipe_reg6;
// synopsys translate_off
initial
small_flag_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg8 <= small_flag_pipe_reg7;
// synopsys translate_off
initial
small_flag_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg9 <= small_flag_pipe_reg8;
// synopsys translate_off
initial
sR_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg0 <= sR_pipe1;
// synopsys translate_off
initial
sR_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg1 <= sR_pipe1_reg0;
// synopsys translate_off
initial
sR_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg2 <= sR_pipe1_reg1;
// synopsys translate_off
initial
sR_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg3 <= sR_pipe1_reg2;
// synopsys translate_off
initial
sR_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg4 <= sR_pipe1_reg3;
// synopsys translate_off
initial
sR_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg5 <= sR_pipe1_reg4;
// synopsys translate_off
initial
sR_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg6 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg6 <= sR_pipe1_reg5;
// synopsys translate_off
initial
sR_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg7 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg7 <= sR_pipe1_reg6;
// synopsys translate_off
initial
sR_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg8 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg8 <= sR_pipe1_reg7;
// synopsys translate_off
initial
sR_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg9 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg9 <= sR_pipe1_reg8;
// synopsys translate_off
initial
sR_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg0 <= sR_pipe2;
// synopsys translate_off
initial
sR_pipe2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg1 <= sR_pipe2_reg0;
// synopsys translate_off
initial
sR_pipe2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg2 <= sR_pipe2_reg1;
// synopsys translate_off
initial
sR_pipe2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg3 <= sR_pipe2_reg2;
// synopsys translate_off
initial
sR_pipe2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg4 <= sR_pipe2_reg3;
// synopsys translate_off
initial
sR_pipe2_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg5 <= sR_pipe2_reg4;
// synopsys translate_off
initial
sR_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg0 <= sR_pipe3;
// synopsys translate_off
initial
sR_pipe3_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg1 <= sR_pipe3_reg0;
// synopsys translate_off
initial
sR_pipe3_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg2 <= sR_pipe3_reg1;
// synopsys translate_off
initial
sR_pipe3_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg3 <= sR_pipe3_reg2;
// synopsys translate_off
initial
sR_pipe3_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg4 <= sR_pipe3_reg3;
// synopsys translate_off
initial
Z2o2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_pipe_reg0 <= 14'b0;
else if (clk_en == 1'b1) Z2o2_pipe_reg0 <= Z2o2_pipe;
// synopsys translate_off
initial
Z2o2_small_s_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_small_s_pipe_reg0 <= 14'b0;
else if (clk_en == 1'b1) Z2o2_small_s_pipe_reg0 <= Z2o2_small_s_pipe;
// synopsys translate_off
initial
Zfinal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg0 <= 26'b0;
else if (clk_en == 1'b1) Zfinal_reg0 <= Zfinal;
// synopsys translate_off
initial
Zfinal_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg1 <= 26'b0;
else if (clk_en == 1'b1) Zfinal_reg1 <= Zfinal_reg0;
lpm_add_sub addsub1
(
.add_sub(sR_pipe3),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(Z_small),
.datab(Z2o2_small),
.overflow(),
.result(wire_addsub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub1.lpm_pipeline = 2,
addsub1.lpm_representation = "UNSIGNED",
addsub1.lpm_width = 29,
addsub1.lpm_type = "lpm_add_sub";
lpm_add_sub addsub2
(
.add_sub((~ sR_pipe3)),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(absELog2_pad),
.datab(LogF_normal_pad),
.overflow(),
.result(wire_addsub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub2.lpm_pipeline = 2,
addsub2.lpm_representation = "UNSIGNED",
addsub2.lpm_width = 47,
addsub2.lpm_type = "lpm_add_sub";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(absE),
.datab(Log2),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 3,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 8,
mult1.lpm_widthb = 27,
mult1.lpm_widthp = 35,
mult1.lpm_type = "lpm_mult";
assign wire_mux_result0a_dataout = ((((input_is_zero | input_is_infinity) | input_is_nan) | input_is_one) === 1'b1) ? {{8{((~ input_is_one) | input_is_nan)}}, input_is_nan, {22{1'b0}}} : EFR;
assign
absE = (({8{(~ sR_pipe2)}} & E0) | ({8{sR_pipe2}} & wire_sub2_result)),
absELog2 = absELog2_pipe_reg2,
absELog2_pad = {absELog2, {12{1'b0}}},
absELog2_pipe = wire_mult1_result,
absZ0 = absZ0_pipe_reg9,
absZ0_pipe = (({12{(~ sR_pipe1)}} & Y0[11:0]) | ({12{sR_pipe1}} & wire_sub1_result)),
absZ0s = wire_Lshiftsmall_result[31:20],
absZ0s_pipe1 = absZ0s_reg0,
absZ0s_pipe2 = absZ0s_pipe1_reg3,
aclr = 1'b0,
almostLog = almostLog_pipe_reg2,
almostLog_pipe = wire_range_reduction_almostlog,
data_exp_is_ebiase = {((~ exp_data[7]) & data_exp_is_ebiase[6]), (exp_data[6] & data_exp_is_ebiase[5]), (exp_data[5] & data_exp_is_ebiase[4]), (exp_data[4] & data_exp_is_ebiase[3]), (exp_data[3] & data_exp_is_ebiase[2]), (exp_data[2] & data_exp_is_ebiase[1]), (exp_data[1] & data_exp_is_ebiase[0]), exp_data[0]},
doRR = Lshiftval[5],
doRR_pipe = doRR_reg1,
E0 = E0_pipe_reg9,
E0_is_zero = {((~ E0[7]) & E0_is_zero[6]), ((~ E0[6]) & E0_is_zero[5]), ((~ E0[5]) & E0_is_zero[4]), ((~ E0[4]) & E0_is_zero[3]), ((~ E0[3]) & E0_is_zero[2]), ((~ E0[2]) & E0_is_zero[1]), ((~ E0[1]) & E0_is_zero[0]), (~ E0[0])},
E0_pipe = wire_exp_biase_sub_result,
E0_sub = {(Log_small[28] | Log_small[27]), (Log_small[28] | (~ Log_small[27]))},
E0offset = 8'b10000110,
E_normal = E_normal_pipe_reg0,
E_normal_pipe = wire_lzc_norm_E_q[4:0],
E_small = wire_sub5_result,
EFR = wire_add2_result,
ER = (({8{(~ small_flag)}} & wire_sub6_result) | ({8{small_flag}} & E_small)),
exp_all_one = wire_exp_nan_result,
exp_all_zero = wire_exp_zero_result,
exp_biase = {7'b0111111, (~ First_bit)},
exp_data = data[30:23],
exp_is_ebiase = exp_is_ebiase_pipe_reg2,
exp_is_ebiase_pipe = data_exp_is_ebiase[7],
First_bit = man_data[22],
input_is_infinity = input_is_infinity_pipe_reg17,
input_is_infinity_pipe = (exp_all_one & (~ man_all_zero)),
input_is_nan = input_is_nan_pipe_reg17,
input_is_nan_pipe = ((exp_all_one & man_not_zero) | sign_data_pipe),
input_is_one = input_is_one_pipe_reg17,
input_is_one_pipe = (exp_is_ebiase & (~ man_all_zero)),
input_is_zero = input_is_zero_pipe_reg17,
input_is_zero_pipe = (~ exp_all_zero),
Log1p_normal = wire_sub4_result,
Log2 = 27'b101100010111001000011000000,
Log_g = (({27{(~ small_flag)}} & Log_normal_normd[45:19]) | ({27{small_flag}} & {Log_small_normd[25:0], 1'b0})),
Log_normal = wire_addsub2_result,
Log_normal_normd = Log_normal_normd_pipe_reg0,
Log_normal_normd_pipe = wire_lzc_norm_L_result[63:17],
Log_normal_pipe = Log_normal_reg0,
Log_small = wire_addsub1_result,
Log_small1 = (({27{(~ Log_small[27])}} & Log_small[26:0]) | ({27{Log_small[27]}} & Log_small[27:1])),
Log_small2 = (({27{(~ Log_small[28])}} & Log_small1) | ({27{Log_small[28]}} & Log_small[28:2])),
Log_small_normd = Log_small_normd_pipe_reg1,
Log_small_normd_pipe = Log_small2,
LogF_normal = wire_add1_result,
LogF_normal_pad = {{8{LogF_normal[38]}}, LogF_normal},
Lshiftval = wire_sub3_result,
lzo = lzo_pipe1_reg9,
lzo_pipe1 = (~ wire_lzoc_q),
lzo_pipe2 = lzo_reg7,
man_above_half = {1'b0, 1'b1, man_data},
man_all_zero = wire_man_inf_result,
man_below_half = {1'b1, man_data, 1'b0},
man_data = data[22:0],
man_not_zero = wire_man_nan_result,
pfinal_s = 5'b01101,
result = {(((sR | input_is_zero) | input_is_nan) & (~ input_is_one)), wire_mux_result0a_dataout},
round = (Log_g[3] & (Log_g[4] | sticky[2])),
Rshiftval = Lshiftval_reg3,
sign_data = data[31],
sign_data_pipe = sign_data_reg2,
small_flag = small_flag_pipe_reg9,
small_flag_pipe = ((~ doRR) & E0_is_zero[7]),
squarerIn = (({13{(~ doRR_pipe)}} & squarerIn0) | ({13{doRR_pipe}} & squarerIn1)),
squarerIn0 = {absZ0s_pipe1, 1'b0},
squarerIn1 = Zfinal[25:13],
sR = sR_pipe3_reg4,
sR_pipe1 = (~ (data_exp_is_ebiase[7] | exp_data[7])),
sR_pipe2 = sR_pipe1_reg9,
sR_pipe3 = sR_pipe2_reg5,
sticky = {(Log_g[2] | sticky[1]), (Log_g[1] | sticky[0]), Log_g[0]},
Y0 = (({25{(~ First_bit)}} & man_below_half) | ({25{First_bit}} & man_above_half)),
Z2o2 = Z2o2_pipe_reg0,
Z2o2_pipe = wire_squarer_result,
Z2o2_small = {{13{1'b0}}, Z2o2_small_s, {2{1'b0}}},
Z2o2_small_s = Z2o2_small_s_pipe_reg0,
Z2o2_small_s_pipe = wire_Rshiftsmall_result[31:18],
Z_small = {absZ0s_pipe2, {17{1'b0}}},
Zfinal = wire_range_reduction_z,
Zfinal_pipe = Zfinal_reg1;
endmodule //acl_fp_log_altfp_log_h5b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log (
enable,
clock,
resetn,
dataa,
result);
input enable;
input clock;
input resetn; // Not used
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_log_altfp_log_h5b acl_fp_log_altfp_log_h5b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_log"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "21"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
`endif
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=32 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:04:27:18:06:48:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgpik
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [31:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [31:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [31:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 32,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgpik
//VALID FILE
|
/*
* Copyright (c) 2000 Nadim Shaikli <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This is made up from PR#63 */
module main;
reg one, clk;
reg [1:0] a, b, c, passed;
reg [7:0] count;
always
#1 one = ~one;
// generate a clock
always
#10 clk = ~clk;
initial
begin
$display ("\n<< BEGIN >>");
one = 1'b1;
clk = 1'b0;
passed = 2'b00;
count = 0;
#15 a[1:0] = 2'b01;
#10 a[1:0] = 2'b10;
#20 $display ("\n<< END >>");
if (passed == 2)
$display ("PASSED");
else
$display ("FAILED");
$finish;
end
always @(clk)
begin
// Problematic lines below -- comment them out to see timing skew
b[1:0] <= #2.5 a[1:0];
c[1:0] <= #7.8 a[1:0];
end
always @(one)
count[7:0] <= count + 1;
always @(count)
begin
case ( count )
'd25:
if (b[1:0] == 2'b01)
begin
$display ("@ %0t - Got ONE", $time);
passed = passed + 1;
end
else
$display ("@ %0t - failure", $time);
'd29:
if (b[1:0] == 2'b01)
begin
$display ("@ %0t - Got ONE", $time);
passed = passed + 1;
end
else
$display ("@ %0t - failure", $time);
default:
$display ("@ %0t - no count", $time);
endcase
end
// Waves definition
// initial
// begin
// $recordvars("primitives", "drivers");
// $dumpfile("out.dump");
// $dumpvars(5, main);
// Line below ought to work
// $dumpvars;
// end
endmodule // main
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 1
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "ZynqDesign_xbar_1,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "ZynqDesign_xbar_1,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=3,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x00000000412100000000000043c000000000000041200000,C_M_AXI_ADDR_WIDTH=0x000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x000000010000000100000001,C_M_AXI_READ_ISSUING=0x000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ZynqDesign_xbar_1 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'H00000000412100000000000043c000000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
typedef enum int {
PADTYPE_DEFAULT = 32'd0,
PADTYPE_GPIO,
PADTYPE_VDD,
PADTYPE_GND
} t_padtype;
localparam int STR_PINID [0:15]
= '{
"DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR",
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7"
};
typedef struct packed {
t_padtype padtype;
int aux;
} t_pin_descriptor;
localparam t_pin_descriptor
PINOUT[ 1: 6]
= '{
'{default:0, padtype:PADTYPE_GPIO, aux:1},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_GPIO},
'{default:0, padtype:PADTYPE_VDD},
'{default:0, padtype:PADTYPE_GND}
};
localparam int PINOUT_SIZE = 6;
localparam int PINOUT_WA[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
const int pinout_static_const[1:PINOUT_SIZE][3]
= '{
'{0, PADTYPE_GPIO, 0},
'{1, PADTYPE_GPIO, 0},
'{2, PADTYPE_GPIO, 0},
'{5, PADTYPE_GPIO, 0},
'{6, PADTYPE_VDD, 0},
'{8, PADTYPE_GND , 0}
};
// Make sure consants propagate
checkstr #(.PINID(STR_PINID[1]),
.EXP("ERR"))
substr1 ();
checkstr #(.PINID(STR_PINID[8]),
.EXP("PA0"))
substr8 ();
initial begin
$display("PINID1 %s", STR_PINID[1]);
$display("PINID8 %s", STR_PINID[8]);
if (STR_PINID[1] != "ERR") $stop;
if (STR_PINID[8] != "PA0") $stop;
if (pinout_static_const[1][0] != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module checkstr;
parameter int PINID = " ";
parameter int EXP = " ";
initial begin
$display("PID %s EXP %s", PINID, EXP);
if (EXP != "ERR" && EXP != "PA0") $stop;
if (PINID != EXP) $stop;
end
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
The first row you want to storing, used for eliminating offset.
::range
Depend on your input offset.
*/
parameter row_init = 0;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[addr_width - 1 : 0] reg_ram_addr;
reg[3 : 0] con_ready;
assign ram_addr = reg_ram_addr;
assign out_data = out_ready ? in_data : 0;
generate
if(wr_mode == 0) begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= row_init * im_width;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= row_init * im_width - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
assign out_ready = ~rst_n || ~in_enable ? 0 : 1;
end else begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= 0;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= 0 - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_ready <= 0;
else if (con_ready == ram_read_latency)
con_ready <= con_ready;
else
con_ready <= con_ready + 1;
end
assign out_ready = con_ready == ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
/***********************************************************************************************************************
* Copyright (C) 2016 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
OUTPUTS:
TODO
TEST PROCEDURE:
TODO
*/
module SPIToDCMP(spi_sck, spi_cs_n, spi_mosi, spi_int, dcmp_greater, dcmp_equal);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P8" *)
input wire spi_sck;
(* LOC = "P9" *)
input wire spi_cs_n;
(* LOC = "P10" *)
input wire spi_mosi;
(* LOC = "P7" *)
output wire spi_int;
(* LOC = "P20" *)
output wire dcmp_greater;
(* LOC = "P19" *)
output wire dcmp_equal;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RC oscillator clock and buffers
wire clk_2mhz;
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.HARDIP_DIV(1),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_2mhz),
.CLKOUT_FABRIC()
);
wire clk_2mhz_buf;
GP_CLKBUF clkbuf_rcosc (
.IN(clk_2mhz),
.OUT(clk_2mhz_buf));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI interface
wire spi_sck_buf;
GP_CLKBUF clkbuf_sck(
.IN(spi_sck),
.OUT(spi_sck_buf));
wire[7:0] rxd_low;
wire[7:0] rxd_high;
GP_SPI #(
.DATA_WIDTH(16),
.SPI_CPHA(0),
.SPI_CPOL(0),
.DIRECTION("INPUT")
) spi (
.SCK(spi_sck_buf),
.SDAT(spi_mosi),
.CSN(spi_cs_n),
.TXD_HIGH(8'h00),
.TXD_LOW(8'h00),
.RXD_HIGH(rxd_high),
.RXD_LOW(rxd_low),
.INT(spi_int)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The DCMP
wire[7:0] ref0;
GP_DCMPREF #(
.REF_VAL(8'h40)
) dcref (
.OUT(ref0)
);
GP_DCMP #(
.GREATER_OR_EQUAL(1'b0),
.CLK_EDGE("RISING"),
.PWRDN_SYNC(1'b1)
) dcmp(
.INP(rxd_high),
.INN(ref0),
.CLK(clk_2mhz_buf),
.PWRDN(1'b0),
.GREATER(dcmp_greater),
.EQUAL(dcmp_equal)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_1_V
`define SKY130_FD_SC_HS__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_1_V
|
(** * ProofObjects: The Curry-Howard Correspondence *)
(** "_Algorithms are the computational content of proofs_." --Robert Harper *)
Require Export IndProp.
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types like [nat] or [list] and functions over
these types, and for _proving_ properties of these programs, using
inductive propositions (like [ev]), implication, universal
quantification, and the like. So far, we have mostly treated
these mechanisms as if they were quite separate, and for many
purposes this is a good way to think. But we have also seen hints
that Coq's programming and proving facilities are closely related.
For example, the keyword [Inductive] is used to declare both data
types and propositions, and [->] is used both to describe the type
of functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are
almost the same thing. In this chapter we will study how this
works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of
evidence, which can be thought of as a data structure.
If the proposition is an implication like [A -> B], then its proof
will be an evidence _transformer_: a recipe for converting
evidence for A into evidence for B. So at a fundamental level,
proofs are simply programs that manipulate evidence. *)
(** Question: If evidence is data, what are propositions themselves?
Answer: They are types!
Look again at the formal definition of the [ev] property. *)
Print ev.
(* ==>
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n, ev n -> ev (S (S n)).
*)
(** Suppose we introduce an alternative pronunciation of "[:]".
Instead of "has type," we can say "is a proof of." For example,
the second line in the definition of [ev] declares that [ev_0 : ev
0]. Instead of "[ev_0] has type [ev 0]," we can say that "[ev_0]
is a proof of [ev 0]." *)
(** This pun between types and propositions -- between [:] as "has type"
and [:] as "is a proof of" or "is evidence for" -- is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation:
propositions ~ types
proofs ~ data values
See [Wadler 2015] for a brief history and an up-to-date exposition.
Many useful insights follow from this connection. To begin with,
it gives us a natural interpretation of the type of the [ev_SS]
constructor: *)
Check ev_SS.
(* ===> ev_SS : forall n,
ev n ->
ev (S (S n)) *)
(** This can be read "[ev_SS] is a constructor that takes two
arguments -- a number [n] and evidence for the proposition [ev
n] -- and yields evidence for the proposition [ev (S (S n))]." *)
(** Now let's look again at a previous proof involving [ev]. *)
Theorem ev_4 : ev 4.
Proof.
apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** As with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof
script. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0)
: ev 4 *)
(** As a matter of fact, we can also write down this proof object
_directly_, without the need for a separate proof script: *)
Check (ev_SS 2 (ev_SS 0 ev_0)).
(* ===> ev 4 *)
(** The expression [ev_SS 2 (ev_SS 0 ev_0)] can be thought of as
instantiating the parameterized constructor [ev_SS] with the
specific arguments [2] and [0] plus the corresponding proof
objects for its premises [ev 2] and [ev 0]. Alternatively, we can
think of [ev_SS] as a primitive "evidence constructor" that, when
applied to a particular number, wants to be further applied to
evidence that that number is even; its type,
forall n, ev n -> ev (S (S n)),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] expresses the fact that the constructor
[nil] can be thought of as a function from types to empty lists
with elements of that type. *)
(** We saw in the [Logic] chapter that we can use function
application syntax to instantiate universally quantified variables
in lemmas, as well as to supply evidence for assumptions that
these lemmas impose. For instance: *)
Theorem ev_4': ev 4.
Proof.
apply (ev_SS 2 (ev_SS 0 ev_0)).
Qed.
(** We can now see that this feature is a trivial consequence of the
status the Coq grants to proofs and propositions: Lemmas and
hypotheses can be combined in expressions (i.e., proof objects)
according to the same basic rules used for programs in the
language. *)
(* ################################################################# *)
(** * Proof Scripts *)
(** The _proof objects_ we've been discussing lie at the core of how
Coq operates. When Coq is following a proof script, what is
happening internally is that it is gradually constructing a proof
object -- a term whose type is the proposition being proved. The
tactics between [Proof] and [Qed] tell it how to build up a term
of the required type. To see this process in action, let's use
the [Show Proof] command to display the current state of the proof
tree at various points in the following tactic proof. *)
Theorem ev_4'' : ev 4.
Proof.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_SS.
Show Proof.
apply ev_0.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with a
"hole" (indicated by [?Goal] here, and so on), and it knows what
type of evidence is needed to fill this hole.
Each hole corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
evidence we've built stored in the global context under the name
given in the [Theorem] command. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition ev_4''' : ev 4 :=
ev_SS 2 (ev_SS 0 ev_0).
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print ev_4.
(* ===> ev_4 = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'.
(* ===> ev_4' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4''.
(* ===> ev_4'' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
Print ev_4'''.
(* ===> ev_4''' = ev_SS 2 (ev_SS 0 ev_0) : ev 4 *)
(** **** Exercise: 1 star (eight_is_even) *)
(** Give a tactic proof and a proof object showing that [ev 8]. *)
Theorem ev_8 : ev 8.
Proof. repeat constructor. Qed.
Definition ev_8' : ev 8 := ev_SS 6 (ev_SS 4 ev_4''').
(** [] *)
(* ################################################################# *)
(** * Quantifiers, Implications, Functions *)
(** In Coq's computational universe (where data structures and
programs live), there are two sorts of values with arrows in their
types: _constructors_ introduced by [Inductive]-ly defined data
types, and _functions_.
Similarly, in Coq's logical universe (where we carry out proofs),
there are two ways of giving evidence for an implication:
constructors introduced by [Inductive]-ly defined propositions,
and... functions!
For example, consider this statement: *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n H. simpl.
apply ev_SS.
apply ev_SS.
apply H.
Qed.
(** What is the proof object corresponding to [ev_plus4]?
We're looking for an expression whose _type_ is [forall n, ev n ->
ev (4 + n)] -- that is, a _function_ that takes two arguments (one
number and a piece of evidence) and returns a piece of evidence!
Here it is: *)
Definition ev_plus4' : forall n, ev n -> ev (4 + n) :=
fun (n : nat) => fun (H : ev n) =>
ev_SS (S (S n)) (ev_SS n H).
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]," and that Coq treats [4 + n] and [S (S (S (S n)))]
as synonyms. Another equivalent way to write this definition is: *)
Definition ev_plus4'' (n : nat) (H : ev n) : ev (4 + n) :=
ev_SS (S (S n)) (ev_SS n H).
Check ev_plus4''.
(* ===> ev_plus4'' : forall n : nat, ev n -> ev (4 + n) *)
(** When we view the proposition being proved by [ev_plus4] as a
function type, one aspect of it may seem a little unusual. The
second argument's type, [ev n], mentions the _value_ of the first
argument, [n]. While such _dependent types_ are not found in
conventional programming languages, they can be useful in
programming too, as the recent flurry of activity in the
functional programming community demonstrates.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a
name to the type on the left-hand side of the arrow. *)
(** For example, consider this proposition: *)
Definition ev_plus2 : Prop :=
forall n, forall (E : ev n), ev (n + 2).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
even. But the name [E] for this evidence is not used in the rest
of the statement of [ev_plus2], so it's a bit silly to bother
making up a name for it. We could write it like this instead,
using the dummy identifier [_] in place of a real name: *)
Definition ev_plus2' : Prop :=
forall n, forall (_ : ev n), ev (n + 2).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition ev_plus2'' : Prop :=
forall n, ev n -> ev (n + 2).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(* ################################################################# *)
(** * Programming with Tactics *)
(** If we can build proofs by giving explicit terms rather than
executing tactic scripts, you may be wondering whether we can
build _programs_ using _tactics_ rather than explicit terms.
Naturally, the answer is yes! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Compute add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than
with [:=] followed by a term. This tells Coq to enter _proof
scripting mode_ to build an object of type [nat -> nat]. Also, we
terminate the proof with [Defined] rather than [Qed]; this makes
the definition _transparent_ so that it can be used in computation
like a normally-defined function. ([Qed]-defined objects are
opaque during computation.)
This feature is mainly useful for writing functions with dependent
types, which we won't explore much further in this book. But it
does illustrate the uniformity and orthogonality of the basic
ideas in Coq. *)
(* ################################################################# *)
(** * Logical Connectives as Inductive Types *)
(** Inductive definitions are powerful enough to express most of the
connectives and quantifiers we have seen so far. Indeed, only
universal quantification (and thus implication) is built into Coq;
all the others are defined inductively. We'll see these
definitions in this section. *)
Module Props.
(** ** Conjunction
To prove that [P /\ Q] holds, we must present evidence for both
[P] and [Q]. Thus, it makes sense to define a proof object for [P
/\ Q] as consisting of a pair of two proofs: one for [P] and
another one for [Q]. This leads to the following definition. *)
Module And.
Inductive and (P Q : Prop) : Prop :=
| conj : P -> Q -> and P Q.
End And.
(** Notice the similarity with the definition of the [prod] type,
given in chapter [Poly]; the only difference is that [prod] takes
[Type] arguments, whereas [and] takes [Prop] arguments. *)
Print prod.
(* ===>
Inductive prod (X Y : Type) : Type :=
| pair : X -> Y -> X * Y. *)
(** This should clarify why [destruct] and [intros] patterns can be
used on a conjunctive hypothesis. Case analysis allows us to
consider all possible ways in which [P /\ Q] was proved -- here
just one (the [conj] constructor). Similarly, the [split] tactic
actually works for any inductively defined proposition with only
one constructor. In particular, it works for [and]: *)
Lemma and_comm : forall P Q : Prop, P /\ Q <-> Q /\ P.
Proof.
intros P Q. split.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
- intros [HP HQ]. split.
+ apply HQ.
+ apply HP.
Qed.
(** This shows why the inductive definition of [and] can be
manipulated by tactics as we've been doing. We can also use it to
build proofs directly, using pattern-matching. For instance: *)
Definition and_comm'_aux P Q (H : P /\ Q) :=
match H with
| conj HP HQ => conj HQ HP
end.
Definition and_comm' P Q : P /\ Q <-> Q /\ P :=
conj (and_comm'_aux P Q) (and_comm'_aux Q P).
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun (P Q R : Prop) =>
fun (H1 : P /\ Q) =>
fun (H2 : Q /\ R)
=> match H1, H2 with
| conj Hp Hq, conj _ Hr => conj Hp Hr
end.
(** [] *)
(** ** Disjunction
The inductive definition of disjunction uses two constructors, one
for each side of the disjunct: *)
Module Or.
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
End Or.
(** This declaration explains the behavior of the [destruct] tactic on
a disjunctive hypothesis, since the generated subgoals match the
shape of the [or_introl] and [or_intror] constructors.
Once again, we can also directly write proof objects for theorems
involving [or], without resorting to tactics. *)
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Definition or_comm : forall P Q, P \/ Q -> Q \/ P :=
fun (P Q : Prop) => fun (H : P \/ Q) =>
match H with
| or_introl Hp => or_intror Hp
| or_intror Hq => or_introl Hq
end.
(** [] *)
(** ** Existential Quantification
To give evidence for an existential quantifier, we package a
witness [x] together with a proof that [x] satisfies the property
[P]: *)
Module Ex.
Inductive ex {A : Type} (P : A -> Prop) : Prop :=
| ex_intro : forall x : A, P x -> ex P.
End Ex.
(** This may benefit from a little unpacking. The core definition is
for a type former [ex] that can be used to build propositions of
the form [ex P], where [P] itself is a _function_ from witness
values in the type [A] to propositions. The [ex_intro]
constructor then offers a way of constructing evidence for [ex P],
given a witness [x] and a proof of [P x].
The more familiar form [exists x, P x] desugars to an expression
involving [ex]: *)
Check ex (fun n => ev n).
(* ===> exists n : nat, ev n
: Prop *)
(** Here's how to define an explicit proof object involving [ex]: *)
Definition some_nat_is_even : exists n, ev n :=
ex_intro ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, optional (ex_ev_Sn) *)
(** Complete the definition of the following proof object: *)
Definition ex_ev_Sn : ex (fun n => ev (S n)) :=
ex_intro (fun n => ev (S n)) 1 (ev_SS 0 ev_0).
(** [] *)
(* ================================================================= *)
(** ** [True] and [False] *)
(** The inductive definition of the [True] proposition is simple: *)
Inductive True : Prop :=
| I : True.
(** It has one constructor (so every proof of [True] is the same, so
being given a proof of [True] is not informative.) *)
(** [False] is equally simple -- indeed, so simple it may look
syntactically wrong at first glance! *)
Inductive False : Prop :=.
(** That is, [False] is an inductive type with _no_ constructors --
i.e., no way to build evidence for it. *)
End Props.
(* ################################################################# *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has the
following inductive definition. (Actually, the definition in the
standard library is a small variant of this, which gives an
induction principle that is slightly easier to use.) *)
Module MyEquality.
Inductive eq {X:Type} : X -> X -> Prop :=
| eq_refl : forall x, eq x x.
Notation "x = y" := (eq x y)
(at level 70, no associativity)
: type_scope.
(** The way to think about this definition is that, given a set [X],
it defines a _family_ of propositions "[x] is equal to [y],"
indexed by pairs of values ([x] and [y]) from [X]. There is just
one way of constructing evidence for each member of this family:
applying the constructor [eq_refl] to a type [X] and a value [x :
X] yields evidence that [x] is equal to [x]. *)
(** **** Exercise: 2 stars (leibniz_equality) *)
(** The inductive definition of equality corresponds to _Leibniz
equality_: what we mean when we say "[x] and [y] are equal" is
that every property on [P] that is true of [x] is also true of
[y]. *)
Lemma leibniz_equality : forall (X : Type) (x y: X),
x = y -> forall P:X->Prop, P x -> P y.
Proof.
intros X x y Hxy HP HPx. destruct Hxy. apply HPx.
Qed.
(** [] *)
(** We can use [eq_refl] to construct evidence that, for example, [2 =
2]. Can we also use it to construct evidence that [1 + 1 = 2]?
Yes, we can. Indeed, it is the very same piece of evidence! The
reason is that Coq treats as "the same" any two terms that are
_convertible_ according to a simple set of computation rules.
These rules, which are similar to those used by [Compute], include
evaluation of function application, inlining of definitions, and
simplification of [match]es. *)
Lemma four: 2 + 2 = 1 + 3.
Proof.
apply eq_refl.
Qed.
(** The [reflexivity] tactic that we have used to prove equalities up
to now is essentially just short-hand for [apply refl_equal].
In tactic-based proofs of equality, the conversion rules are
normally hidden in uses of [simpl] (either explicit or implicit in
other tactics such as [reflexivity]). But you can see them
directly at work in the following explicit proof objects: *)
Definition four' : 2 + 2 = 1 + 3 :=
eq_refl 4.
Definition singleton : forall (X:Set) (x:X), []++[x] = x::[] :=
fun (X:Set) (x:X) => eq_refl [x].
End MyEquality.
Definition quiz6 : exists x, x + 3 = 4
:= ex_intro (fun z => (z + 3 = 4)) 1 (refl_equal 4).
(* ================================================================= *)
(** ** Inversion, Again *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves.
In general, the [inversion] tactic...
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context (and, for convenience,
rewrites them in the goal), and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal. *)
(** _Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(** $Date: 2017-01-30 18:47:45 -0500 (Mon, 30 Jan 2017) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire input_signal = crc[0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire output_signal; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.output_signal (output_signal),
// Inputs
.input_signal (input_signal));
// Aggregate outputs into a single result vector
wire [63:0] result = {63'h0, output_signal};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h765b2e12b25ec97b
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input input_signal,
output output_signal
);
// bug872
// verilator lint_off UNOPTFLAT
wire some_signal[1:0][1:0];
assign some_signal[0][0] = input_signal;
assign some_signal[0][1] = some_signal[0][0];
assign some_signal[1][0] = some_signal[0][1];
assign some_signal[1][1] = some_signal[1][0];
assign output_signal = some_signal[1][1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_SYMBOL_V
`define SKY130_FD_SC_LS__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_SYMBOL_V
/**
* udp_dff$PE_pp$PG$N: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PE_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DATA_EN ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_SYMBOL_V
|