module_name
stringlengths 1
2.17k
| module_content
stringlengths 6
11.3k
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|---|---|
System |
public:
/* Instantiated sub-modules. We instantiate the dut_wrapper module,
rather than the dut module directly. This is because the dut
module can exist in multiple versions (such as behavioral and
synthesized RTL), and the wrapper module automatically selects
between the versions based on the simulation configuration. */
dut_wrapper DUT;
tb TB;
sc_clock clk_sig;
sc_signal< bool > rst_sig;
cynw_p2p< input_t > chan1; /* TB to DUT, using struct input_t. */
cynw_p2p< output_t > chan2; /* DUT to TB, using type output_t. */
SC_CTOR( System )
: clk_sig( "clk_sig", CLOCK_PERIOD, SC_NS )
, rst_sig( "rst_sig" )
, TB( "TB" )
, chan1( "chan1" )
, DUT( "DUT" )
, chan2( "chan2" )
{
TB.clk( clk_sig );
TB.rst_out( rst_sig );
DUT.clk( clk_sig );
DUT.rst( rst_sig );
TB.dout( chan1 );
DUT.din( chan1 );
DUT.dout( chan2 );
TB.din( chan2 );
}
|
Sram |
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_addr << i_sram_dq << i_sram_we_n << i_sram_ce_n << i_sram_oe_n << i_sram_ub_n << i_sram_lb_n;
m_sram = new uint16_t[sram_size >> 1];
dont_initialize();
}
void trace_all(sc_trace_file *tf, const std::string& parent_name);
void load_hex(const std::string& filename);
void load_bin(const std::string& filename);
void dump_mem(procyon::utils::dump_format_t group_fmt = procyon::utils::DUMP_FORMAT_4B, procyon::utils::dump_format_t line_fmt = procyon::utils::DUMP_FORMAT_16B);
~Sram();
private:
uint16_t* m_sram;
void process();
|
dut_type_wrapper |
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
#if defined ( ioConfig_TLM )
,clk("clk")
,rst("rst")
#else
,clk("clk")
,rst("rst")
#endif
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
|
vip_uart_receiver |
public:
sc_in<bool> i_nrst;
sc_in<bool> i_clk;
sc_in<bool> i_rx;
sc_out<bool> o_rdy;
sc_in<bool> i_rdy_clr;
sc_out<sc_uint<8>> o_data;
void comb();
void registers();
SC_HAS_PROCESS(vip_uart_receiver);
vip_uart_receiver(sc_module_name name,
bool async_reset,
int scaler);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int scaler_;
int scaler_max;
int scaler_mid;
static const uint8_t startbit = 0;
static const uint8_t data = 1;
static const uint8_t stopbit = 2;
static const uint8_t dummy = 3;
struct vip_uart_receiver_registers {
sc_signal<bool> rx;
sc_signal<sc_uint<2>> state;
sc_signal<bool> rdy;
sc_signal<sc_uint<8>> rdata;
sc_signal<sc_uint<32>> sample;
sc_signal<sc_uint<4>> bitpos;
sc_signal<sc_uint<8>> scratch;
sc_signal<bool> rx_err;
} v, r;
void vip_uart_receiver_r_reset(vip_uart_receiver_registers &iv) {
iv.rx = 0;
iv.state = startbit;
iv.rdy = 0;
iv.rdata = 0;
iv.sample = 0;
iv.bitpos = 0;
iv.scratch = 0;
iv.rx_err = 0;
}
|
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool > main_start;
// sc_signal < bool > main_end;
// Instruction counters
sc_signal < long int > icount;
sc_signal < long int > j_icount;
sc_signal < long int > b_icount;
sc_signal < long int > m_icount;
sc_signal < long int > o_icount;
// Cache modeled as arryas
sc_uint<XLEN> imem[ICACHE_SIZE];
sc_uint<XLEN> dmem[DCACHE_SIZE];
/* The testbench, DUT, IMEM and DMEM modules. */
tb *m_tb;
hl5_wrapper *m_dut;
SC_CTOR(TOP)
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
{
m_tb = new tb("tb", imem, dmem);
m_dut = new hl5_wrapper("dut", imem, dmem);
// Connect the design module
m_dut->clk(clk);
m_dut->rst(cpu_rst);
m_dut->entry_point(entry_point);
m_dut->program_end(program_end);
m_dut->fetch_en(fetch_en);
// m_dut->main_start(main_start);
// m_dut->main_end(main_end);
m_dut->icount(icount);
m_dut->j_icount(j_icount);
m_dut->b_icount(b_icount);
m_dut->m_icount(m_icount);
m_dut->o_icount(o_icount);
// Connect the testbench
m_tb->clk(clk);
m_tb->rst(rst);
m_tb->cpu_rst(cpu_rst);
m_tb->entry_point(entry_point);
m_tb->program_end(program_end);
m_tb->fetch_en(fetch_en);
// m_tb->main_start(main_start);
// m_tb->main_end(main_end);
m_tb->icount(icount);
m_tb->j_icount(j_icount);
m_tb->b_icount(b_icount);
m_tb->m_icount(m_icount);
m_tb->o_icount(o_icount);
}
~TOP()
{
delete m_tb;
delete m_dut;
delete imem;
delete dmem;
}
|
cdc_axi_sync_tech |
public:
sc_in<bool> i_xslv_clk; // system clock
sc_in<bool> i_xslv_nrst; // system reset
sc_in<axi4_slave_in_type> i_xslvi; // system clock
sc_out<axi4_slave_out_type> o_xslvo; // system clock
sc_in<bool> i_xmst_clk; // ddr clock
sc_in<bool> i_xmst_nrst; // ddr reset
sc_out<axi4_slave_in_type> o_xmsto; // ddr clock
sc_in<axi4_slave_out_type> i_xmsti; // ddr clock
void comb();
SC_HAS_PROCESS(cdc_axi_sync_tech);
cdc_axi_sync_tech(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
|
sdctrl_cache |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_req_wdata;
sc_in<sc_uint<8>> i_req_wstrb;
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<64>> o_resp_data;
sc_out<bool> o_resp_err;
sc_in<bool> i_resp_ready;
// Memory interface:
sc_in<bool> i_req_mem_ready;
sc_out<bool> o_req_mem_valid;
sc_out<bool> o_req_mem_write;
sc_out<sc_uint<CFG_SDCACHE_ADDR_BITS>> o_req_mem_addr;
sc_out<sc_biguint<SDCACHE_LINE_BITS>> o_req_mem_data;
sc_in<bool> i_mem_data_valid;
sc_in<sc_biguint<SDCACHE_LINE_BITS>> i_mem_data;
sc_in<bool> i_mem_fault;
// Debug interface
sc_in<bool> i_flush_valid;
sc_out<bool> o_flush_end;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cache);
sdctrl_cache(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cache();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int abus = CFG_SDCACHE_ADDR_BITS;
static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
static const int lnbits = CFG_LOG2_SDCACHE_BYTES_PER_LINE;
static const int flbits = SDCACHE_FL_TOTAL;
// State machine states:
static const uint8_t State_Idle = 0;
static const uint8_t State_CheckHit = 2;
static const uint8_t State_TranslateAddress = 3;
static const uint8_t State_WaitGrant = 4;
static const uint8_t State_WaitResp = 5;
static const uint8_t State_CheckResp = 6;
static const uint8_t State_SetupReadAdr = 1;
static const uint8_t State_WriteBus = 7;
static const uint8_t State_FlushAddr = 8;
static const uint8_t State_FlushCheck = 9;
static const uint8_t State_Reset = 10;
static const uint8_t State_ResetWrite = 11;
static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
static const uint32_t FLUSH_ALL_VALUE = ((1 << ibits) - 1);
struct sdctrl_cache_registers {
sc_signal<bool> req_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> req_addr;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<4>> state;
sc_signal<bool> req_mem_valid;
sc_signal<bool> req_mem_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> mem_addr;
sc_signal<bool> mem_fault;
sc_signal<bool> write_first;
sc_signal<bool> write_flush;
sc_signal<bool> req_flush;
sc_signal<sc_uint<32>> flush_cnt;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_addr_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_o;
} v, r;
void sdctrl_cache_r_reset(sdctrl_cache_registers &iv) {
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.req_mem_write = 0;
iv.mem_addr = 0;
iv.mem_fault = 0;
iv.write_first = 0;
iv.write_flush = 0;
iv.req_flush = 0;
iv.flush_cnt = 0;
iv.line_addr_i = 0;
iv.cache_line_i = 0;
iv.cache_line_o = 0;
}
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_wdata_i;
sc_signal<sc_uint<SDCACHE_BYTES_PER_LINE>> line_wstrb_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_wflags_i;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_raddr_o;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_rdata_o;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_rflags_o;
sc_signal<bool> line_hit_o;
// Snoop signals:
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_snoop_addr_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_snoop_flags_o;
TagMem<abus, ibits, lnbits, flbits, 0> *mem0;
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
testbench)
// {
// public:
// // Clock
// sc_clock clk;
//
// // Interconnect
// sc_in_clk clk;
// sc_signal<bool> rst;
// sc_signal<int> datain;
// sc_signal<int> dataout;
//
// // Design Under Test (DUT)
// CCS_DESIGN(adder) adder_INST;
//
// SC_CTOR(testbench)
// : CCS_CLK_CTOR(clk, "clk", 10, SC_NS, 0.5, 0, SC_NS, false) // effectively clk("clk", 10, SC_NS, 0.5, 0, SC_NS, false)
// , adder_INST("adder_INST")
// , rst("rst"), datain("datain"), dataout("dataout" |
// SC_THREAD(reset_driver);
// }
//
// // Active-high Asynchronous reset driver
// void reset_driver() {
// rst.write(1);
// wait(clk.period() * 1.5); // wait 1.5 clock cycles
// std::ostringstream msg;
// msg << "De-asserting reset signal '" << rst.name() << "' @ " << sc_time_stamp();
// SC_REPORT_INFO(this->name(),msg.str().c_str());
// rst.write(0);
// }
//
// // ... BODY OF TESTBENCH GOES HERE. Create methods
// // to drive inputs and check outputs. Mismatches
// // should report the error using:
// // SC_REPORT_ERROR("testbench", "ERROR: some error message\n");
//
// |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
InstrExecute |
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
sc_in<bool> i_memop_store; // Store to memory operation
sc_in<bool> i_memop_load; // Load from memoru operation
sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
sc_in<bool> i_unsigned_op; // Unsigned operands
sc_in<bool> i_rv32; // 32-bits instruction
sc_in<bool> i_compressed; // C-extension (2-bytes length)
sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
sc_in<bool> i_unsup_exception; // Unsupported instruction exception
sc_in<bool> i_dport_npc_write; // Write npc value from debug port
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
sc_out<sc_uint<5>> o_radr1; // Integer register index 1
sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
sc_out<sc_uint<5>> o_radr2; // Integer register index 2
sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
sc_out<bool> o_csr_wena; // Write new CSR value
sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
sc_in<bool> i_trap_valid; // async trap event
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_trap_pc; // jump to address
// exceptions:
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_ex_npc; // npc on before trap
sc_out<bool> o_ex_illegal_instr;
sc_out<bool> o_ex_unalign_store;
sc_out<bool> o_ex_unalign_load;
sc_out<bool> o_ex_breakpoint;
sc_out<bool> o_ex_ecall;
sc_out<bool> o_memop_sign_ext; // Load data with sign extending
sc_out<bool> o_memop_load; // Load data instruction
sc_out<bool> o_memop_store; // Store data instruction
sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
sc_out<bool> o_pre_valid; // pre-latch of valid
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
sc_out<sc_uint<32>> o_instr; // Valid instruction value
sc_out<bool> o_call; // CALL pseudo instruction detected
sc_out<bool> o_ret; // RET pseudoinstruction detected
sc_out<bool> o_mret; // MRET.
sc_out<bool> o_uret; // MRET.
void comb();
void registers();
SC_HAS_PROCESS(InstrExecute);
InstrExecute(sc_module_name name_);
virtual ~InstrExecute();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
enum EMultiCycleInstruction {
Multi_MUL,
Multi_DIV,
Multi_Total
|
pn532_base |
/* Signals */
sc_out<gn_mixed> irq {"irq" |
decod |
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
sc_in<sc_uint<32>> RDATA2_SR;
// Current value of PC
sc_in<sc_uint<32>> READ_PC_SR;
// Port to write into PC
sc_out<sc_uint<32>> WRITE_PC_SD;
sc_out<bool> WRITE_PC_ENABLE_SD;
/*****************************************************
Interface with EXE
******************************************************/
sc_out<sc_uint<32>> OP1_RD;
sc_out<sc_uint<32>> OP2_RD;
/* Command sent to EXE.
In case of a shift :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
In case of an ALU operation :
- 0 : add
- 1 : and
- 2 : or
- 3 : xor
In case of an SLT operation
- 0 : slt
- 1 : sltu
*/
sc_out<sc_uint<2>> EXE_CMD_RD;
sc_out<bool> NEG_OP2_RD; // negates the second operator, to do substractions
sc_out<bool> WB_RD; // write back the result in reg
sc_out<sc_uint<6>> EXE_DEST_SD; // the destination register
/* operation types :
- 0 : alu
- 1 : shifter
- 2 : slt
*/
sc_out<sc_uint<3>> OPTYPE_RD;
sc_out<sc_uint<32>> MEM_DATA_RD; // data sent to mem for storage
sc_out<bool> MEM_LOAD_RD; // a memory load
sc_out<bool> MEM_STORE_RD; // a memory store
sc_out<bool> MEM_SIGN_EXTEND_RD; // loads and stores can be signed or unsigned
sc_out<sc_uint<2>> MEM_SIZE_RD; // mem accesses can be words, half words or bytes
/*****************************************************
Interface with DEC2IF
******************************************************/
sc_in<bool> DEC2IF_POP_SI; // The POP signal coming from Ifetch
sc_out<bool> DEC2IF_EMPTY_SD;
sc_out<sc_bv<32>> PC_RD; // the output of the fifo, containing the PC of the next instruction
/*****************************************************
Interface with IF2DEC
******************************************************/
sc_in<sc_bv<32>> INSTR_RI; // The instruction coming from Ifetch
sc_in<sc_uint<32>> PC_RI; // The pc of the instruction being executed
sc_in<bool> IF2DEC_EMPTY_SI;
sc_out<bool> IF2DEC_POP_SD; // the POP signal sent to Ifetch
sc_out<bool> IF2DEC_FLUSH_SD; // Signal sent to IFETCH to flush all instructions
/*****************************************************
Interface with DEC2EXE
******************************************************/
sc_in<bool> DEC2EXE_POP_SE; // The POP signal coming from EXE
sc_out<bool> DEC2EXE_EMPTY_SD;
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_out_sd;
/*****************************************************
BYPASSES
******************************************************/
// see the bypasses process in dec.cpp, or the documentation, for an explanation
// pipeline data coming from the end of EXE
sc_in<sc_uint<6>> DEST_RE; // the destination register of the data
sc_in<sc_uint<32>> EXE_RES_RE; // the data
sc_in<bool> MEM_LOAD_RE; // whether it is a memory load
sc_in<bool> EXE2MEM_EMPTY_SE; // whether the data is valid
// pipeline data coming from the end of MEM
sc_in<sc_uint<6>> DEST_RM; // the destination register of the data
sc_in<sc_uint<32>> MEM_RES_RM; // the data
sc_in<bool> MEM2WBK_EMPTY_SM; // Whether the data is valid
// Bypass outputs for EXE
sc_out<sc_uint<6>> BP_RADR1_RD; // the register of the data in OP1
sc_out<sc_uint<6>> BP_RADR2_RD; // the register of the data in OP2
sc_out<bool> BLOCK_BP_RD; // prevent any further bypasses
// General Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Signals :
sc_signal<sc_uint<32>> rdata1_sd;
sc_signal<sc_uint<32>> rdata2_sd;
sc_signal<bool> invalid_operand_sd;
// fifo dec2if :
sc_signal<sc_bv<32>> dec2if_in_sd; // pc sent to fifo
sc_signal<bool> dec2if_push_sd;
sc_signal<bool> dec2if_full_sd;
sc_signal<sc_bv<32>> dec2if_out_sd;
// fifo dec2exe :
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_in_sd;
sc_signal<bool> dec2exe_push_sd;
sc_signal<bool> dec2exe_full_sd;
// Instruction format type :
sc_signal<bool> r_type_inst_sd; // R type format
sc_signal<bool> i_type_inst_sd; // I type format
sc_signal<bool> s_type_inst_sd; // S type format
sc_signal<bool> b_type_inst_sd; // B type format
sc_signal<bool> u_type_inst_sd; // U type format
sc_signal<bool> j_type_inst_sd; // J type format
sc_signal<bool> jalr_type_inst_sd; // JALR has a specific opcode
// R-type Instructions :
sc_signal<bool> add_i_sd;
sc_signal<bool> slt_i_sd;
sc_signal<bool> sltu_i_sd;
sc_signal<bool> and_i_sd;
sc_signal<bool> or_i_sd;
sc_signal<bool> xor_i_sd;
sc_signal<bool> sll_i_sd;
sc_signal<bool> srl_i_sd;
sc_signal<bool> sub_i_sd;
sc_signal<bool> sra_i_sd;
// I-type Instructions :
sc_signal<bool> addi_i_sd;
sc_signal<bool> slti_i_sd;
sc_signal<bool> sltiu_i_sd;
sc_signal<bool> andi_i_sd;
sc_signal<bool> ori_i_sd;
sc_signal<bool> xori_i_sd;
sc_signal<bool> jalr_i_sd;
sc_signal<bool> fence_i_sd;
// I-type shift instructions :
sc_signal<bool> slli_i_sd;
sc_signal<bool> srli_i_sd;
sc_signal<bool> srai_i_sd;
// I-type load instructions :
sc_signal<bool> lw_i_sd;
sc_signal<bool> lh_i_sd;
sc_signal<bool> lhu_i_sd;
sc_signal<bool> lb_i_sd;
sc_signal<bool> lbu_i_sd;
// B-type Instruction :
sc_signal<bool> beq_i_sd;
sc_signal<bool> bne_i_sd;
sc_signal<bool> blt_i_sd;
sc_signal<bool> bge_i_sd;
sc_signal<bool> bltu_i_sd;
sc_signal<bool> bgeu_i_sd;
// U-type Instruction :
sc_signal<bool> lui_i_sd;
sc_signal<bool> auipc_i_sd;
// J-type Instruction :
sc_signal<bool> jal_i_sd;
// S-type Instructions :
sc_signal<bool> sw_i_sd;
sc_signal<bool> sh_i_sd;
sc_signal<bool> sb_i_sd;
// Offset for branch :
sc_signal<sc_uint<32>> offset_branch_sd;
// PC gestion :
sc_signal<bool> inc_pc_sd;
sc_signal<bool> jump_sd;
// Pipeline Gestion
sc_signal<bool> stall_sd;
sc_signal<bool> normal_sd;
sc_signal<bool> block_in_dec_sd;
// Internal signals :
sc_signal<sc_uint<6>> adr_dest_sd;
sc_signal<sc_uint<32>> exe_op1_sd;
sc_signal<sc_uint<32>> exe_op2_sd;
sc_signal<sc_uint<32>> mem_data_sd;
sc_signal<sc_uint<2>> mem_size_sd;
sc_signal<bool> mem_load_sd;
sc_signal<bool> mem_store_sd;
sc_signal<sc_uint<2>> exe_cmd_sd;
sc_signal<sc_uint<2>> optype_sd;
sc_signal<bool> exe_neg_op2_sd;
sc_signal<bool> exe_wb_sd;
sc_signal<bool> mem_sign_extend_sd;
sc_signal<bool> block_bp_sd;
// Instance used :
fifo<32> dec2if;
fifo<DEC2EXE_SIZE> dec2exe;
void concat_dec2exe();
void unconcat_dec2exe();
void decoding_instruction_type();
void decoding_instruction();
void pre_reg_read_decoding();
void post_reg_read_decoding();
void pc_inc();
void bypasses();
void stall_method();
void trace(sc_trace_file * tf);
SC_CTOR(decod) : dec2if("dec2if"), dec2exe("dec2exe") {
dec2if.DATAIN_S(dec2if_in_sd);
dec2if.DATAOUT_R(PC_RD);
dec2if.EMPTY_S(DEC2IF_EMPTY_SD);
dec2if.FULL_S(dec2if_full_sd);
dec2if.PUSH_S(dec2if_push_sd);
dec2if.POP_S(DEC2IF_POP_SI);
dec2if.CLK(CLK);
dec2if.RESET(RESET);
dec2exe.DATAIN_S(dec2exe_in_sd);
dec2exe.DATAOUT_R(dec2exe_out_sd);
dec2exe.EMPTY_S(DEC2EXE_EMPTY_SD);
dec2exe.FULL_S(dec2exe_full_sd);
dec2exe.PUSH_S(dec2exe_push_sd);
dec2exe.POP_S(DEC2EXE_POP_SE);
dec2exe.CLK(CLK);
dec2exe.RESET(RESET);
SC_METHOD(concat_dec2exe)
sensitive << dec2exe_in_sd << exe_op1_sd << exe_op2_sd << exe_cmd_sd << exe_neg_op2_sd
<< exe_wb_sd << mem_data_sd << mem_load_sd << mem_store_sd << mem_sign_extend_sd
<< mem_size_sd << optype_sd << adr_dest_sd << slti_i_sd << slt_i_sd << sltiu_i_sd
<< sltu_i_sd << RADR1_SD << RADR2_SD << block_bp_sd;
SC_METHOD(unconcat_dec2exe)
sensitive << dec2exe_out_sd;
SC_METHOD(stall_method)
sensitive << b_type_inst_sd << jalr_type_inst_sd << j_type_inst_sd << invalid_operand_sd
<< DEC2EXE_EMPTY_SD << EXE2MEM_EMPTY_SE << IF2DEC_EMPTY_SI << dec2exe_full_sd
<< block_in_dec_sd;
SC_METHOD(decoding_instruction_type)
sensitive << INSTR_RI << READ_PC_SR;
SC_METHOD(decoding_instruction)
sensitive << INSTR_RI;
SC_METHOD(pre_reg_read_decoding)
sensitive << INSTR_RI << r_type_inst_sd << i_type_inst_sd << i_type_inst_sd
<< s_type_inst_sd << b_type_inst_sd << u_type_inst_sd << j_type_inst_sd
<< jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd << bltu_i_sd
<< bgeu_i_sd << fence_i_sd << RESET;
SC_METHOD(post_reg_read_decoding)
sensitive << i_type_inst_sd << s_type_inst_sd << b_type_inst_sd << u_type_inst_sd
<< j_type_inst_sd << jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd
<< bge_i_sd << bltu_i_sd << bgeu_i_sd << IF2DEC_EMPTY_SI << dec2if_push_sd
<< READ_PC_SR << stall_sd << dec2if_push_sd << add_i_sd << slt_i_sd << sltu_i_sd
<< and_i_sd << or_i_sd << xor_i_sd << sll_i_sd << srl_i_sd << sub_i_sd << sra_i_sd
<< addi_i_sd << slti_i_sd << sltiu_i_sd << andi_i_sd << ori_i_sd << xori_i_sd
<< jalr_i_sd << slli_i_sd << srli_i_sd << srai_i_sd << lw_i_sd << lh_i_sd
<< lhu_i_sd << lb_i_sd << lbu_i_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd
<< bltu_i_sd << bgeu_i_sd << lui_i_sd << auipc_i_sd << jal_i_sd << sw_i_sd
<< sh_i_sd << sb_i_sd << j_type_inst_sd << jalr_type_inst_sd << dec2exe_push_sd
<< rdata1_sd << rdata2_sd << fence_i_sd << PC_RI;
SC_METHOD(pc_inc)
sensitive << CLK.pos() << READ_PC_SR << offset_branch_sd << inc_pc_sd << jump_sd << PC_RI
<< dec2if_full_sd << IF2DEC_EMPTY_SI << stall_sd;
SC_METHOD(bypasses);
sensitive << RDATA1_SR << RDATA2_SR << DEST_RE << EXE_RES_RE << DEST_RM
<< MEM_RES_RM << RADR1_SD << EXE_DEST_SD << RADR2_SD << EXE2MEM_EMPTY_SE
<< DEC2EXE_EMPTY_SD << MEM_LOAD_RE << MEM2WBK_EMPTY_SM;
reset_signal_is(RESET, false);
}
|
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99} |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
simple_bus_master_direct |
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
SC_HAS_PROCESS(simple_bus_master_direct);
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = true)
: sc_module(name_)
, m_address(address)
, m_timeout(timeout)
, m_verbose(verbose)
{
// process declaration
SC_THREAD(main_action);
}
// process
void main_action();
private:
unsigned int m_address;
int m_timeout;
bool m_verbose;
|
decod |
/*****************************************************
Interface with REG
******************************************************/
// adresses of Rs and Rd
sc_out<sc_uint<6>> RADR1_SD;
sc_out<sc_uint<6>> RADR2_SD;
// Data read in registers
sc_in<sc_uint<32>> RDATA1_SR;
sc_in<sc_uint<32>> RDATA2_SR;
// Current value of PC
sc_in<sc_uint<32>> READ_PC_SR;
// Port to write into PC
sc_out<sc_uint<32>> WRITE_PC_SD;
sc_out<bool> WRITE_PC_ENABLE_SD;
/*****************************************************
Interface with EXE
******************************************************/
sc_out<sc_uint<32>> OP1_RD;
sc_out<sc_uint<32>> OP2_RD;
/* Command sent to EXE.
In case of a shift :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
In case of an ALU operation :
- 0 : add
- 1 : and
- 2 : or
- 3 : xor
In case of an SLT operation
- 0 : slt
- 1 : sltu
*/
sc_out<sc_uint<2>> EXE_CMD_RD;
sc_out<bool> NEG_OP2_RD; // negates the second operator, to do substractions
sc_out<bool> WB_RD; // write back the result in reg
sc_out<sc_uint<6>> EXE_DEST_SD; // the destination register
/* operation types :
- 0 : alu
- 1 : shifter
- 2 : slt
*/
sc_out<sc_uint<3>> OPTYPE_RD;
sc_out<sc_uint<32>> MEM_DATA_RD; // data sent to mem for storage
sc_out<bool> MEM_LOAD_RD; // a memory load
sc_out<bool> MEM_STORE_RD; // a memory store
sc_out<bool> MEM_SIGN_EXTEND_RD; // loads and stores can be signed or unsigned
sc_out<sc_uint<2>> MEM_SIZE_RD; // mem accesses can be words, half words or bytes
/*****************************************************
Interface with DEC2IF
******************************************************/
sc_in<bool> DEC2IF_POP_SI; // The POP signal coming from Ifetch
sc_out<bool> DEC2IF_EMPTY_SD;
sc_out<sc_bv<32>> PC_RD; // the output of the fifo, containing the PC of the next instruction
/*****************************************************
Interface with IF2DEC
******************************************************/
sc_in<sc_bv<32>> INSTR_RI; // The instruction coming from Ifetch
sc_in<sc_uint<32>> PC_RI; // The pc of the instruction being executed
sc_in<bool> IF2DEC_EMPTY_SI;
sc_out<bool> IF2DEC_POP_SD; // the POP signal sent to Ifetch
sc_out<bool> IF2DEC_FLUSH_SD; // Signal sent to IFETCH to flush all instructions
/*****************************************************
Interface with DEC2EXE
******************************************************/
sc_in<bool> DEC2EXE_POP_SE; // The POP signal coming from EXE
sc_out<bool> DEC2EXE_EMPTY_SD;
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_out_sd;
/*****************************************************
BYPASSES
******************************************************/
// see the bypasses process in dec.cpp, or the documentation, for an explanation
// pipeline data coming from the end of EXE
sc_in<sc_uint<6>> DEST_RE; // the destination register of the data
sc_in<sc_uint<32>> EXE_RES_RE; // the data
sc_in<bool> MEM_LOAD_RE; // whether it is a memory load
sc_in<bool> EXE2MEM_EMPTY_SE; // whether the data is valid
// pipeline data coming from the end of MEM
sc_in<sc_uint<6>> DEST_RM; // the destination register of the data
sc_in<sc_uint<32>> MEM_RES_RM; // the data
sc_in<bool> MEM2WBK_EMPTY_SM; // Whether the data is valid
// Bypass outputs for EXE
sc_out<sc_uint<6>> BP_RADR1_RD; // the register of the data in OP1
sc_out<sc_uint<6>> BP_RADR2_RD; // the register of the data in OP2
sc_out<bool> BLOCK_BP_RD; // prevent any further bypasses
// General Interface :
sc_in_clk CLK;
sc_in<bool> RESET;
// Signals :
sc_signal<sc_uint<32>> rdata1_sd;
sc_signal<sc_uint<32>> rdata2_sd;
sc_signal<bool> invalid_operand_sd;
// fifo dec2if :
sc_signal<sc_bv<32>> dec2if_in_sd; // pc sent to fifo
sc_signal<bool> dec2if_push_sd;
sc_signal<bool> dec2if_full_sd;
sc_signal<sc_bv<32>> dec2if_out_sd;
// fifo dec2exe :
sc_signal<sc_bv<DEC2EXE_SIZE>> dec2exe_in_sd;
sc_signal<bool> dec2exe_push_sd;
sc_signal<bool> dec2exe_full_sd;
// Instruction format type :
sc_signal<bool> r_type_inst_sd; // R type format
sc_signal<bool> i_type_inst_sd; // I type format
sc_signal<bool> s_type_inst_sd; // S type format
sc_signal<bool> b_type_inst_sd; // B type format
sc_signal<bool> u_type_inst_sd; // U type format
sc_signal<bool> j_type_inst_sd; // J type format
sc_signal<bool> jalr_type_inst_sd; // JALR has a specific opcode
// R-type Instructions :
sc_signal<bool> add_i_sd;
sc_signal<bool> slt_i_sd;
sc_signal<bool> sltu_i_sd;
sc_signal<bool> and_i_sd;
sc_signal<bool> or_i_sd;
sc_signal<bool> xor_i_sd;
sc_signal<bool> sll_i_sd;
sc_signal<bool> srl_i_sd;
sc_signal<bool> sub_i_sd;
sc_signal<bool> sra_i_sd;
// I-type Instructions :
sc_signal<bool> addi_i_sd;
sc_signal<bool> slti_i_sd;
sc_signal<bool> sltiu_i_sd;
sc_signal<bool> andi_i_sd;
sc_signal<bool> ori_i_sd;
sc_signal<bool> xori_i_sd;
sc_signal<bool> jalr_i_sd;
sc_signal<bool> fence_i_sd;
// I-type shift instructions :
sc_signal<bool> slli_i_sd;
sc_signal<bool> srli_i_sd;
sc_signal<bool> srai_i_sd;
// I-type load instructions :
sc_signal<bool> lw_i_sd;
sc_signal<bool> lh_i_sd;
sc_signal<bool> lhu_i_sd;
sc_signal<bool> lb_i_sd;
sc_signal<bool> lbu_i_sd;
// B-type Instruction :
sc_signal<bool> beq_i_sd;
sc_signal<bool> bne_i_sd;
sc_signal<bool> blt_i_sd;
sc_signal<bool> bge_i_sd;
sc_signal<bool> bltu_i_sd;
sc_signal<bool> bgeu_i_sd;
// U-type Instruction :
sc_signal<bool> lui_i_sd;
sc_signal<bool> auipc_i_sd;
// J-type Instruction :
sc_signal<bool> jal_i_sd;
// S-type Instructions :
sc_signal<bool> sw_i_sd;
sc_signal<bool> sh_i_sd;
sc_signal<bool> sb_i_sd;
// Offset for branch :
sc_signal<sc_uint<32>> offset_branch_sd;
// PC gestion :
sc_signal<bool> inc_pc_sd;
sc_signal<bool> jump_sd;
// Pipeline Gestion
sc_signal<bool> stall_sd;
sc_signal<bool> normal_sd;
sc_signal<bool> block_in_dec_sd;
// Internal signals :
sc_signal<sc_uint<6>> adr_dest_sd;
sc_signal<sc_uint<32>> exe_op1_sd;
sc_signal<sc_uint<32>> exe_op2_sd;
sc_signal<sc_uint<32>> mem_data_sd;
sc_signal<sc_uint<2>> mem_size_sd;
sc_signal<bool> mem_load_sd;
sc_signal<bool> mem_store_sd;
sc_signal<sc_uint<2>> exe_cmd_sd;
sc_signal<sc_uint<2>> optype_sd;
sc_signal<bool> exe_neg_op2_sd;
sc_signal<bool> exe_wb_sd;
sc_signal<bool> mem_sign_extend_sd;
sc_signal<bool> block_bp_sd;
// Instance used :
fifo<32> dec2if;
fifo<DEC2EXE_SIZE> dec2exe;
void concat_dec2exe();
void unconcat_dec2exe();
void decoding_instruction_type();
void decoding_instruction();
void pre_reg_read_decoding();
void post_reg_read_decoding();
void pc_inc();
void bypasses();
void stall_method();
void trace(sc_trace_file * tf);
SC_CTOR(decod) : dec2if("dec2if"), dec2exe("dec2exe") {
dec2if.DATAIN_S(dec2if_in_sd);
dec2if.DATAOUT_R(PC_RD);
dec2if.EMPTY_S(DEC2IF_EMPTY_SD);
dec2if.FULL_S(dec2if_full_sd);
dec2if.PUSH_S(dec2if_push_sd);
dec2if.POP_S(DEC2IF_POP_SI);
dec2if.CLK(CLK);
dec2if.RESET(RESET);
dec2exe.DATAIN_S(dec2exe_in_sd);
dec2exe.DATAOUT_R(dec2exe_out_sd);
dec2exe.EMPTY_S(DEC2EXE_EMPTY_SD);
dec2exe.FULL_S(dec2exe_full_sd);
dec2exe.PUSH_S(dec2exe_push_sd);
dec2exe.POP_S(DEC2EXE_POP_SE);
dec2exe.CLK(CLK);
dec2exe.RESET(RESET);
SC_METHOD(concat_dec2exe)
sensitive << dec2exe_in_sd << exe_op1_sd << exe_op2_sd << exe_cmd_sd << exe_neg_op2_sd
<< exe_wb_sd << mem_data_sd << mem_load_sd << mem_store_sd << mem_sign_extend_sd
<< mem_size_sd << optype_sd << adr_dest_sd << slti_i_sd << slt_i_sd << sltiu_i_sd
<< sltu_i_sd << RADR1_SD << RADR2_SD << block_bp_sd;
SC_METHOD(unconcat_dec2exe)
sensitive << dec2exe_out_sd;
SC_METHOD(stall_method)
sensitive << b_type_inst_sd << jalr_type_inst_sd << j_type_inst_sd << invalid_operand_sd
<< DEC2EXE_EMPTY_SD << EXE2MEM_EMPTY_SE << IF2DEC_EMPTY_SI << dec2exe_full_sd
<< block_in_dec_sd;
SC_METHOD(decoding_instruction_type)
sensitive << INSTR_RI << READ_PC_SR;
SC_METHOD(decoding_instruction)
sensitive << INSTR_RI;
SC_METHOD(pre_reg_read_decoding)
sensitive << INSTR_RI << r_type_inst_sd << i_type_inst_sd << i_type_inst_sd
<< s_type_inst_sd << b_type_inst_sd << u_type_inst_sd << j_type_inst_sd
<< jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd << bltu_i_sd
<< bgeu_i_sd << fence_i_sd << RESET;
SC_METHOD(post_reg_read_decoding)
sensitive << i_type_inst_sd << s_type_inst_sd << b_type_inst_sd << u_type_inst_sd
<< j_type_inst_sd << jalr_type_inst_sd << beq_i_sd << bne_i_sd << blt_i_sd
<< bge_i_sd << bltu_i_sd << bgeu_i_sd << IF2DEC_EMPTY_SI << dec2if_push_sd
<< READ_PC_SR << stall_sd << dec2if_push_sd << add_i_sd << slt_i_sd << sltu_i_sd
<< and_i_sd << or_i_sd << xor_i_sd << sll_i_sd << srl_i_sd << sub_i_sd << sra_i_sd
<< addi_i_sd << slti_i_sd << sltiu_i_sd << andi_i_sd << ori_i_sd << xori_i_sd
<< jalr_i_sd << slli_i_sd << srli_i_sd << srai_i_sd << lw_i_sd << lh_i_sd
<< lhu_i_sd << lb_i_sd << lbu_i_sd << beq_i_sd << bne_i_sd << blt_i_sd << bge_i_sd
<< bltu_i_sd << bgeu_i_sd << lui_i_sd << auipc_i_sd << jal_i_sd << sw_i_sd
<< sh_i_sd << sb_i_sd << j_type_inst_sd << jalr_type_inst_sd << dec2exe_push_sd
<< rdata1_sd << rdata2_sd << fence_i_sd << PC_RI;
SC_METHOD(pc_inc)
sensitive << CLK.pos() << READ_PC_SR << offset_branch_sd << inc_pc_sd << jump_sd << PC_RI
<< dec2if_full_sd << IF2DEC_EMPTY_SI << stall_sd;
SC_METHOD(bypasses);
sensitive << RDATA1_SR << RDATA2_SR << DEST_RE << EXE_RES_RE << DEST_RM
<< MEM_RES_RM << RADR1_SD << EXE_DEST_SD << RADR2_SD << EXE2MEM_EMPTY_SE
<< DEC2EXE_EMPTY_SD << MEM_LOAD_RE << MEM2WBK_EMPTY_SM;
reset_signal_is(RESET, false);
}
|
axi_sram |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<axi4_slave_in_type> i_xslvi; // AXI Slave to Bridge interface
sc_out<axi4_slave_out_type> o_xslvo; // AXI Bridge to Slave interface
void comb();
SC_HAS_PROCESS(axi_sram);
axi_sram(sc_module_name name,
bool async_reset);
virtual ~axi_sram();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> wb_req_addr;
sc_signal<sc_uint<8>> wb_req_size;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_req_wdata;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BYTES>> wb_req_wstrb;
sc_signal<bool> w_req_last;
sc_signal<bool> w_req_ready;
sc_signal<bool> w_resp_valid;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_resp_rdata;
sc_signal<bool> wb_resp_err;
sc_signal<sc_uint<abits>> wb_req_addr_abits;
axi_slv *xslv0;
ram_bytes_tech<abits, CFG_LOG2_SYSBUS_DATA_BYTES> *tech0;
|
Timer |
sc_in<bool> at, reset;
sc_in<bool> clk;
sc_out<bool> IL, IC;
SC_CTOR(Timer){
counter = 0;
SC_METHOD(proc);
sensitive << reset << at << clk.pos();
SC_METHOD(printcounter);
sensitive << clk.pos();
}
private:
void proc();
void printcounter();
int counter;
|
subBytes |
sc_in<sc_logic> in[128];
sc_out<sc_logic> out[128];
sbox* sub_Bytes_0;
sbox* sub_Bytes_1;
sbox* sub_Bytes_2;
sbox* sub_Bytes_3;
sbox* sub_Bytes_4;
sbox* sub_Bytes_5;
sbox* sub_Bytes_6;
sbox* sub_Bytes_7;
sbox* sub_Bytes_8;
sbox* sub_Bytes_9;
sbox* sub_Bytes_10;
sbox* sub_Bytes_11;
sbox* sub_Bytes_12;
sbox* sub_Bytes_13;
sbox* sub_Bytes_14;
sbox* sub_Bytes_15;
SC_CTOR( subBytes ) {
sub_Bytes_0 = new sbox("sub_Bytes_0");
sub_Bytes_0->a[0](in[0]);
sub_Bytes_0->a[1](in[1]);
sub_Bytes_0->a[2](in[2]);
sub_Bytes_0->a[3](in[3]);
sub_Bytes_0->a[4](in[4]);
sub_Bytes_0->a[5](in[5]);
sub_Bytes_0->a[6](in[6]);
sub_Bytes_0->a[7](in[7]);
sub_Bytes_0->c[0](out[0]);
sub_Bytes_0->c[1](out[1]);
sub_Bytes_0->c[2](out[2]);
sub_Bytes_0->c[3](out[3]);
sub_Bytes_0->c[4](out[4]);
sub_Bytes_0->c[5](out[5]);
sub_Bytes_0->c[6](out[6]);
sub_Bytes_0->c[7](out[7]);
sub_Bytes_14 = new sbox("sub_Bytes_14");
sub_Bytes_14->a[0](in[8]);
sub_Bytes_14->a[1](in[9]);
sub_Bytes_14->a[2](in[10]);
sub_Bytes_14->a[3](in[11]);
sub_Bytes_14->a[4](in[12]);
sub_Bytes_14->a[5](in[13]);
sub_Bytes_14->a[6](in[14]);
sub_Bytes_14->a[7](in[15]);
sub_Bytes_14->c[0](out[8]);
sub_Bytes_14->c[1](out[9]);
sub_Bytes_14->c[2](out[10]);
sub_Bytes_14->c[3](out[11]);
sub_Bytes_14->c[4](out[12]);
sub_Bytes_14->c[5](out[13]);
sub_Bytes_14->c[6](out[14]);
sub_Bytes_14->c[7](out[15]);
sub_Bytes_4 = new sbox("sub_Bytes_4");
sub_Bytes_4->a[0](in[16]);
sub_Bytes_4->a[1](in[17]);
sub_Bytes_4->a[2](in[18]);
sub_Bytes_4->a[3](in[19]);
sub_Bytes_4->a[4](in[20]);
sub_Bytes_4->a[5](in[21]);
sub_Bytes_4->a[6](in[22]);
sub_Bytes_4->a[7](in[23]);
sub_Bytes_4->c[0](out[16]);
sub_Bytes_4->c[1](out[17]);
sub_Bytes_4->c[2](out[18]);
sub_Bytes_4->c[3](out[19]);
sub_Bytes_4->c[4](out[20]);
sub_Bytes_4->c[5](out[21]);
sub_Bytes_4->c[6](out[22]);
sub_Bytes_4->c[7](out[23]);
sub_Bytes_5 = new sbox("sub_Bytes_5");
sub_Bytes_5->a[0](in[24]);
sub_Bytes_5->a[1](in[25]);
sub_Bytes_5->a[2](in[26]);
sub_Bytes_5->a[3](in[27]);
sub_Bytes_5->a[4](in[28]);
sub_Bytes_5->a[5](in[29]);
sub_Bytes_5->a[6](in[30]);
sub_Bytes_5->a[7](in[31]);
sub_Bytes_5->c[0](out[24]);
sub_Bytes_5->c[1](out[25]);
sub_Bytes_5->c[2](out[26]);
sub_Bytes_5->c[3](out[27]);
sub_Bytes_5->c[4](out[28]);
sub_Bytes_5->c[5](out[29]);
sub_Bytes_5->c[6](out[30]);
sub_Bytes_5->c[7](out[31]);
sub_Bytes_6 = new sbox("sub_Bytes_6");
sub_Bytes_6->a[0](in[32]);
sub_Bytes_6->a[1](in[33]);
sub_Bytes_6->a[2](in[34]);
sub_Bytes_6->a[3](in[35]);
sub_Bytes_6->a[4](in[36]);
sub_Bytes_6->a[5](in[37]);
sub_Bytes_6->a[6](in[38]);
sub_Bytes_6->a[7](in[39]);
sub_Bytes_6->c[0](out[32]);
sub_Bytes_6->c[1](out[33]);
sub_Bytes_6->c[2](out[34]);
sub_Bytes_6->c[3](out[35]);
sub_Bytes_6->c[4](out[36]);
sub_Bytes_6->c[5](out[37]);
sub_Bytes_6->c[6](out[38]);
sub_Bytes_6->c[7](out[39]);
sub_Bytes_7 = new sbox("sub_Bytes_7");
sub_Bytes_7->a[0](in[40]);
sub_Bytes_7->a[1](in[41]);
sub_Bytes_7->a[2](in[42]);
sub_Bytes_7->a[3](in[43]);
sub_Bytes_7->a[4](in[44]);
sub_Bytes_7->a[5](in[45]);
sub_Bytes_7->a[6](in[46]);
sub_Bytes_7->a[7](in[47]);
sub_Bytes_7->c[0](out[40]);
sub_Bytes_7->c[1](out[41]);
sub_Bytes_7->c[2](out[42]);
sub_Bytes_7->c[3](out[43]);
sub_Bytes_7->c[4](out[44]);
sub_Bytes_7->c[5](out[45]);
sub_Bytes_7->c[6](out[46]);
sub_Bytes_7->c[7](out[47]);
sub_Bytes_8 = new sbox("sub_Bytes_8");
sub_Bytes_8->a[0](in[48]);
sub_Bytes_8->a[1](in[49]);
sub_Bytes_8->a[2](in[50]);
sub_Bytes_8->a[3](in[51]);
sub_Bytes_8->a[4](in[52]);
sub_Bytes_8->a[5](in[53]);
sub_Bytes_8->a[6](in[54]);
sub_Bytes_8->a[7](in[55]);
sub_Bytes_8->c[0](out[48]);
sub_Bytes_8->c[1](out[49]);
sub_Bytes_8->c[2](out[50]);
sub_Bytes_8->c[3](out[51]);
sub_Bytes_8->c[4](out[52]);
sub_Bytes_8->c[5](out[53]);
sub_Bytes_8->c[6](out[54]);
sub_Bytes_8->c[7](out[55]);
sub_Bytes_9 = new sbox("sub_Bytes_9");
sub_Bytes_9->a[0](in[56]);
sub_Bytes_9->a[1](in[57]);
sub_Bytes_9->a[2](in[58]);
sub_Bytes_9->a[3](in[59]);
sub_Bytes_9->a[4](in[60]);
sub_Bytes_9->a[5](in[61]);
sub_Bytes_9->a[6](in[62]);
sub_Bytes_9->a[7](in[63]);
sub_Bytes_9->c[0](out[56]);
sub_Bytes_9->c[1](out[57]);
sub_Bytes_9->c[2](out[58]);
sub_Bytes_9->c[3](out[59]);
sub_Bytes_9->c[4](out[60]);
sub_Bytes_9->c[5](out[61]);
sub_Bytes_9->c[6](out[62]);
sub_Bytes_9->c[7](out[63]);
sub_Bytes_10 = new sbox("sub_Bytes_10");
sub_Bytes_10->a[0](in[64]);
sub_Bytes_10->a[1](in[65]);
sub_Bytes_10->a[2](in[66]);
sub_Bytes_10->a[3](in[67]);
sub_Bytes_10->a[4](in[68]);
sub_Bytes_10->a[5](in[69]);
sub_Bytes_10->a[6](in[70]);
sub_Bytes_10->a[7](in[71]);
sub_Bytes_10->c[0](out[64]);
sub_Bytes_10->c[1](out[65]);
sub_Bytes_10->c[2](out[66]);
sub_Bytes_10->c[3](out[67]);
sub_Bytes_10->c[4](out[68]);
sub_Bytes_10->c[5](out[69]);
sub_Bytes_10->c[6](out[70]);
sub_Bytes_10->c[7](out[71]);
sub_Bytes_11 = new sbox("sub_Bytes_11");
sub_Bytes_11->a[0](in[72]);
sub_Bytes_11->a[1](in[73]);
sub_Bytes_11->a[2](in[74]);
sub_Bytes_11->a[3](in[75]);
sub_Bytes_11->a[4](in[76]);
sub_Bytes_11->a[5](in[77]);
sub_Bytes_11->a[6](in[78]);
sub_Bytes_11->a[7](in[79]);
sub_Bytes_11->c[0](out[72]);
sub_Bytes_11->c[1](out[73]);
sub_Bytes_11->c[2](out[74]);
sub_Bytes_11->c[3](out[75]);
sub_Bytes_11->c[4](out[76]);
sub_Bytes_11->c[5](out[77]);
sub_Bytes_11->c[6](out[78]);
sub_Bytes_11->c[7](out[79]);
sub_Bytes_12 = new sbox("sub_Bytes_12");
sub_Bytes_12->a[0](in[80]);
sub_Bytes_12->a[1](in[81]);
sub_Bytes_12->a[2](in[82]);
sub_Bytes_12->a[3](in[83]);
sub_Bytes_12->a[4](in[84]);
sub_Bytes_12->a[5](in[85]);
sub_Bytes_12->a[6](in[86]);
sub_Bytes_12->a[7](in[87]);
sub_Bytes_12->c[0](out[80]);
sub_Bytes_12->c[1](out[81]);
sub_Bytes_12->c[2](out[82]);
sub_Bytes_12->c[3](out[83]);
sub_Bytes_12->c[4](out[84]);
sub_Bytes_12->c[5](out[85]);
sub_Bytes_12->c[6](out[86]);
sub_Bytes_12->c[7](out[87]);
sub_Bytes_13 = new sbox("sub_Bytes_13");
sub_Bytes_13->a[0](in[88]);
sub_Bytes_13->a[1](in[89]);
sub_Bytes_13->a[2](in[90]);
sub_Bytes_13->a[3](in[91]);
sub_Bytes_13->a[4](in[92]);
sub_Bytes_13->a[5](in[93]);
sub_Bytes_13->a[6](in[94]);
sub_Bytes_13->a[7](in[95]);
sub_Bytes_13->c[0](out[88]);
sub_Bytes_13->c[1](out[89]);
sub_Bytes_13->c[2](out[90]);
sub_Bytes_13->c[3](out[91]);
sub_Bytes_13->c[4](out[92]);
sub_Bytes_13->c[5](out[93]);
sub_Bytes_13->c[6](out[94]);
sub_Bytes_13->c[7](out[95]);
sub_Bytes_15 = new sbox("sub_Bytes_15");
sub_Bytes_15->a[0](in[96]);
sub_Bytes_15->a[1](in[97]);
sub_Bytes_15->a[2](in[98]);
sub_Bytes_15->a[3](in[99]);
sub_Bytes_15->a[4](in[100]);
sub_Bytes_15->a[5](in[101]);
sub_Bytes_15->a[6](in[102]);
sub_Bytes_15->a[7](in[103]);
sub_Bytes_15->c[0](out[96]);
sub_Bytes_15->c[1](out[97]);
sub_Bytes_15->c[2](out[98]);
sub_Bytes_15->c[3](out[99]);
sub_Bytes_15->c[4](out[100]);
sub_Bytes_15->c[5](out[101]);
sub_Bytes_15->c[6](out[102]);
sub_Bytes_15->c[7](out[103]);
sub_Bytes_1 = new sbox("sub_Bytes_1");
sub_Bytes_1->a[0](in[104]);
sub_Bytes_1->a[1](in[105]);
sub_Bytes_1->a[2](in[106]);
sub_Bytes_1->a[3](in[107]);
sub_Bytes_1->a[4](in[108]);
sub_Bytes_1->a[5](in[109]);
sub_Bytes_1->a[6](in[110]);
sub_Bytes_1->a[7](in[111]);
sub_Bytes_1->c[0](out[104]);
sub_Bytes_1->c[1](out[105]);
sub_Bytes_1->c[2](out[106]);
sub_Bytes_1->c[3](out[107]);
sub_Bytes_1->c[4](out[108]);
sub_Bytes_1->c[5](out[109]);
sub_Bytes_1->c[6](out[110]);
sub_Bytes_1->c[7](out[111]);
sub_Bytes_2 = new sbox("sub_Bytes_2");
sub_Bytes_2->a[0](in[112]);
sub_Bytes_2->a[1](in[113]);
sub_Bytes_2->a[2](in[114]);
sub_Bytes_2->a[3](in[115]);
sub_Bytes_2->a[4](in[116]);
sub_Bytes_2->a[5](in[117]);
sub_Bytes_2->a[6](in[118]);
sub_Bytes_2->a[7](in[119]);
sub_Bytes_2->c[0](out[112]);
sub_Bytes_2->c[1](out[113]);
sub_Bytes_2->c[2](out[114]);
sub_Bytes_2->c[3](out[115]);
sub_Bytes_2->c[4](out[116]);
sub_Bytes_2->c[5](out[117]);
sub_Bytes_2->c[6](out[118]);
sub_Bytes_2->c[7](out[119]);
sub_Bytes_3 = new sbox("sub_Bytes_3");
sub_Bytes_3->a[0](in[120]);
sub_Bytes_3->a[1](in[121]);
sub_Bytes_3->a[2](in[122]);
sub_Bytes_3->a[3](in[123]);
sub_Bytes_3->a[4](in[124]);
sub_Bytes_3->a[5](in[125]);
sub_Bytes_3->a[6](in[126]);
sub_Bytes_3->a[7](in[127]);
sub_Bytes_3->c[0](out[120]);
sub_Bytes_3->c[1](out[121]);
sub_Bytes_3->c[2](out[122]);
sub_Bytes_3->c[3](out[123]);
sub_Bytes_3->c[4](out[124]);
sub_Bytes_3->c[5](out[125]);
sub_Bytes_3->c[6](out[126]);
sub_Bytes_3->c[7](out[127]);
}
|
shifter |
sc_in<sc_uint<32>> DIN_SE; // input
sc_in<sc_uint<5>> SHIFT_VAL_SE; // shift value
sc_in<sc_uint<2>> CMD_SE; // command
/*
Command value :
- 0 : Shift Left Logical (sll)
- 1 : Shift Right Logical (srl)
- 2 : Shift Right Arithmetic (sra)
*/
sc_out<sc_uint<32>> DOUT_SE; // output
/*
Vous pouvez ajouter des signaux internes ici.
Si vous les faites, n'oubliez pas de les ajouter à la fonction trace
dans shifter.cpp, pour qu'ils apparaissent dans GTKWAVE
*/
void trace(sc_trace_file * tf);
SC_CTOR(shifter) {}
|
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
ic_axi4_to_l1 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// AXI4 port
sc_in<axi4_master_out_type> i_xmsto;
sc_out<axi4_master_in_type> o_xmsti;
// L1 port
sc_in<axi4_l1_in_type> i_l1i;
sc_out<axi4_l1_out_type> o_l1o;
void comb();
void registers();
SC_HAS_PROCESS(ic_axi4_to_l1);
ic_axi4_to_l1(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const uint8_t Idle = 0;
static const uint8_t ReadLineRequest = 1;
static const uint8_t WaitReadLineResponse = 2;
static const uint8_t WriteDataAccept = 3;
static const uint8_t WriteLineRequest = 4;
static const uint8_t WaitWriteConfirmResponse = 5;
static const uint8_t WaitWriteAccept = 6;
static const uint8_t WaitReadAccept = 7;
static const uint8_t CheckBurst = 8;
struct ic_axi4_to_l1_registers {
sc_signal<sc_uint<4>> state;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> req_addr;
sc_signal<sc_uint<CFG_SYSBUS_ID_BITS>> req_id;
sc_signal<sc_uint<CFG_SYSBUS_USER_BITS>> req_user;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_len;
sc_signal<sc_uint<3>> req_size;
sc_signal<sc_uint<3>> req_prot;
sc_signal<bool> writing;
sc_signal<bool> read_modify_write;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> line_data;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> line_wstrb;
sc_signal<sc_uint<64>> resp_data;
} v, r;
void ic_axi4_to_l1_r_reset(ic_axi4_to_l1_registers &iv) {
iv.state = Idle;
iv.req_addr = 0;
iv.req_id = 0;
iv.req_user = 0;
iv.req_wstrb = 0;
iv.req_wdata = 0;
iv.req_len = 0;
iv.req_size = 0;
iv.req_prot = 0;
iv.writing = 0;
iv.read_modify_write = 0;
iv.line_data = 0;
iv.line_wstrb = 0;
iv.resp_data = 0;
}
|
apb_uart |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<mapinfo_type> i_mapinfo; // interconnect slot information
sc_out<dev_config_type> o_cfg; // Device descriptor
sc_in<apb_in_type> i_apbi; // APB Slave to Bridge interface
sc_out<apb_out_type> o_apbo; // APB Bridge to Slave interface
sc_in<bool> i_rd;
sc_out<bool> o_td;
sc_out<bool> o_irq;
void comb();
void registers();
SC_HAS_PROCESS(apb_uart);
apb_uart(sc_module_name name,
bool async_reset,
int sim_speedup_rate);
virtual ~apb_uart();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
int sim_speedup_rate_;
static const int fifosz = (1 << log2_fifosz);
// Rx/Tx states
static const uint8_t idle = 0;
static const uint8_t startbit = 1;
static const uint8_t data = 2;
static const uint8_t parity = 3;
static const uint8_t stopbit = 4;
struct apb_uart_registers {
sc_signal<sc_uint<32>> scaler;
sc_signal<sc_uint<32>> scaler_cnt;
sc_signal<bool> level;
sc_signal<bool> err_parity;
sc_signal<bool> err_stopbit;
sc_signal<sc_uint<32>> fwcpuid;
sc_signal<sc_uint<8>> rx_fifo[fifosz];
sc_signal<sc_uint<3>> rx_state;
sc_signal<bool> rx_ena;
sc_signal<bool> rx_ie;
sc_signal<bool> rx_ip;
sc_signal<bool> rx_nstop;
sc_signal<bool> rx_par;
sc_signal<sc_uint<log2_fifosz>> rx_wr_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_rd_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_byte_cnt;
sc_signal<sc_uint<log2_fifosz>> rx_irq_thresh;
sc_signal<sc_uint<4>> rx_frame_cnt;
sc_signal<bool> rx_stop_cnt;
sc_signal<sc_uint<11>> rx_shift;
sc_signal<sc_uint<8>> tx_fifo[fifosz];
sc_signal<sc_uint<3>> tx_state;
sc_signal<bool> tx_ena;
sc_signal<bool> tx_ie;
sc_signal<bool> tx_ip;
sc_signal<bool> tx_nstop;
sc_signal<bool> tx_par;
sc_signal<sc_uint<log2_fifosz>> tx_wr_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_rd_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_byte_cnt;
sc_signal<sc_uint<log2_fifosz>> tx_irq_thresh;
sc_signal<sc_uint<4>> tx_frame_cnt;
sc_signal<bool> tx_stop_cnt;
sc_signal<sc_uint<11>> tx_shift;
sc_signal<bool> tx_amo_guard; // AMO operation read-modify-write often hit on full flag border
sc_signal<bool> resp_valid;
sc_signal<sc_uint<32>> resp_rdata;
sc_signal<bool> resp_err;
} v, r;
sc_signal<bool> w_req_valid;
sc_signal<sc_uint<32>> wb_req_addr;
sc_signal<bool> w_req_write;
sc_signal<sc_uint<32>> wb_req_wdata;
apb_slv *pslv0;
|
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_imm_s(sc_bv<12> imm); // Sign extend the S-type immediate field.
sc_bv<XLEN> zero_ext_zimm(sc_bv<ZIMM_SIZE> zimm); // Zero extend the zimm field for CSRRxI instructions.
sc_uint<CSR_IDX_LEN> get_csr_index(sc_bv<CSR_ADDR> csr_addr); // Get csr index given the 12-bit CSR address.
void set_csr_value(sc_uint<CSR_IDX_LEN> csr_index, sc_bv<XLEN> rs1, sc_uint<LOG2_CSR_OP_NUM> operation, sc_bv<2> rw_permission); // Perform requested CSR operation (write/set/clear).
// Divider functions
u_div_res_t udiv_func(sc_uint<XLEN> num, sc_uint<XLEN> den);
div_res_t div_func(sc_int<XLEN> num, sc_int<XLEN> den);
// Constructor
SC_CTOR(execute)
: din("din")
, dout("dout")
, fwd_exe("fwd_exe")
, clk("clk")
, rst("rst")
{
SC_CTHREAD(execute_th, clk.pos());
reset_signal_is(rst, false);
SC_CTHREAD(perf_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
HLS_FLATTEN_ARRAY(csr);
}
// Member variables
de_out_t input;
exe_out_t output;
sc_uint<XLEN> csr[CSR_NUM]; // Control and status registers.
|
execute |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto* > decode_execute;
sc_fifo_out < contexto*> execute_fetch;
void execute_method(){
while(true){
recebimento = decode_execute.read();
escrita = recebimento;
e_rs2 = recebimento->rs2;
e_rs1 = recebimento-> rs1;
e_rd = recebimento->rd;
e_op = recebimento-> opcode;
e_funct7 = recebimento->funct7;
e_funct3 = recebimento->funct3;
e_imm_I = recebimento->Imm_I;
e_imm_U = recebimento->Imm_U;
e_imm_J = recebimento->Imm_J;
e_imm_B = recebimento->Imm_B;
e_shamt = recebimento->shamt;
// switch
//Caso R:
// Caso Funct 3:
// Caso Funct 7:
//Caso I:
// Caso Funct 3:
// Caso Func 7:
//Caso B:
// Caso Funct 3:
//Caso S/ADDI...:
// Caso Funct 3:
switch(e_op){
case TIPO_LUI:
// operacao lui
//20 MSB pro reg, 12 LSB = 0
p_breg->write(e_rd, (e_imm_U<<20) & 0xFFFFF000);
break;
case TIPO_AUIPC:
// operacao AUIPC
//PC = reg(31)
_t1 = ((e_imm_U<<20) & 0xFFFFF000) +
p_breg->read(31);
//Adiciona offset e escreve no PC e no Rd
p_breg->write(31, _t1);
p_breg->write(e_rd, _t1);
break;
case TIPO_JAL:
// operacao JAL
p_breg->write(e_rd, p_breg->read(31));
p_breg->write(31, e_imm_J);
break;
case TIPO_JALR:
// operacao JALR
if(e_funct3 == 0x0){
// operacao JALR
_t1 = e_imm_I + p_breg->read(e_rs1);
//Seta BIT0 como 0
_t1 = _t1 & 0xFFFFFFFE;
p_breg->write(e_rd, p_breg->read(31));
p_breg->write(31, _t1);
}
break;
case TIPO_B:
// branches -> tipo B
switch(e_funct3){
case f3_BEQ:
// funcao beq
if (p_breg->read(e_rs1) == p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BNE:
// funcao bne
if (p_breg->read(e_rs1) != p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BLT:
// funcao bLT
if (p_breg->read(e_rs1) < p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BGE:
// funcao bGe
if (p_breg->read(e_rs1) >= p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BLTU:
// funcao bLTU
if ((unsigned)p_breg->read(e_rs1) < (unsigned)p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
case f3_BGEU:
// funcao bGeU
if ((unsigned)p_breg->read(e_rs1) >= (unsigned)p_breg->read(e_rs2)) {
_t1 = e_imm_B << 1;
_t1 += p_breg->read(31);
p_breg->write(31, _t1);
}
break;
default:
break;
}// fim SWITCHh funct3 - Branch
break;
case TIPO_I_REST0 :
// operacoes loads
switch(e_funct3){
case f3_LB:
// load byte
p_breg->write(e_rd, p_mem->lb(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LH:
// load half
p_breg->write(e_rd, p_mem->lh(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LW:
// load word
p_breg->write(e_rd, p_mem->lw(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LBU:
// load byte unsigned
p_breg->write(e_rd, p_mem->lbu(p_breg->read(e_rs1), e_imm_S));
break;
case f3_LHU:
// load half unsigned
p_breg->write(e_rd, p_mem->lhu(p_breg->read(e_rs1), e_imm_S));
break;
// default?
} // fim switch funct3 - loads
break;
case TIPO_S:
// funcoes do tipo store
switch(e_funct3){
case f3_SB:
// store byte
p_mem->sb((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
case f3_SH:
// store half
p_mem->sh((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
case f3_SW:
// store word
p_mem->sw((p_breg->read(e_rs1)), e_imm_S, p_breg->read(e_rs2));
break;
// default?
} // fim switch funct3 - STORE
break;
case TIPO_I2_SHAMT:
// tipos i e shifts
switch(e_funct3){
case f3_ADDI:
//Se for NOP
if(!e_rs1 && !e_rd && !e_imm_I){
break;
}
// addi
_t1 = e_imm_I + p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_SLTI:
// slti
if(p_breg->read(e_rs1) < e_imm_I){
p_breg->write(e_rd, 1);
}
else{
p_breg->write(e_rd, 0);
}
break;
case f3_SLTIU:
// sltiu
//Primeiro faz extensao de sinal p/ 32 bits,
//dps trata os dois como sem sinal
_t1 = e_imm_I;
if((unsigned)p_breg->read(e_rs1) < (unsigned)_t1){
p_breg->write(e_rd, 1);
}
else{
p_breg->write(e_rd, 0);
}
break;
case f3_XORI:
// XORI
_t1 = e_imm_I ^ p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_ORI:
// ORI
_t1 = e_imm_I | p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_ANDI:
// ANDI
_t1 = e_imm_I & p_breg->read(e_rs1);
p_breg->write(e_rd, _t1);
break;
case f3_SRLI_SRAI:
// srli ou srai
if(e_funct7 == f7_SRAI){
// srai
p_breg->write(e_rd, (p_breg->read(e_rs1)) >> e_shamt);
}
if(e_funct7 == f7_RESTO_I){
// SRLI
_t1 = (unsigned)(p_breg->read(e_rs1)) >> e_shamt;
p_breg->write(e_rd, _t1);
}
break;
case f3_SLLI:
// SLLI
if(e_funct7 == f7_RESTO_I ){
// SLLI
p_breg->write(e_rd, (p_breg->read(e_rs1))<< e_shamt);
}
break;
case TIPO_R:
switch(e_funct7){
case f7_RESTO:
switch(e_funct3){
case f3_ADD_SUB:
// add
p_breg->write(e_rd, (p_breg->read(e_rs1)+ p_breg->read(e_rs2)));
break;
case f3_SLL:
// Sll
//Shamt = 5 LSB do registrador RS2
p_breg->write(e_rd, (p_breg->read(e_rs1))<< (p_breg->read(e_rs2) & 0x1F));
break;
case f3_SLT:
// SlT
p_breg->write(e_rd, (p_breg->read(e_rs1)< p_breg->read(e_rs2)));
break;
case f3_SLTU:
// SLT unsigned
p_breg->write(e_rd, ((unsigned)p_breg->read(e_rs1)<(unsigned)p_breg->read(e_rs2)));
break;
case f3_XOR:
// xor
p_breg->write(e_rd, (p_breg->read(e_rs1) ^ p_breg->read(e_rs2)));
break;
case f3_SRL_SRA:
// SRL
_t1 = (unsigned)(p_breg->read(e_rs1)) >> (p_breg->read(e_rs2) & 0x1F);
p_breg->write(e_rd, _t1);
break;
case f3_OR:
// or
p_breg->write(e_rd, (p_breg->read(e_rs1) | p_breg->read(e_rs2)));
break;
case f3_AND:
// and
p_breg->write(e_rd, (p_breg->read(e_rs1) & p_breg->read(e_rs2)));
break;
} // fim funct 3 -> f7 resto
break;
case f7_SRA_SUB:
switch(e_funct3){
case f3_ADD_SUB:
// sub
p_breg->write(e_rd, (p_breg->read(e_rs1) - p_breg->read(e_rs2)));
break;
case f3_SRL_SRA:
// SRA
p_breg->write(e_rd, (p_breg->read(e_rs1)) >> (p_breg->read(e_rs2) & 0x1F));
break;
}// fim funct 3 -> f7 SRA_SUB
break;
}// fim switch funct 7
break;
}// fim switch funct3 - imediato
}// FIM SWITCH
//p_breg->write(0, 0);
execute_fetch.write(escrita);
} //while
} // execute_method()
SC_CTOR(execute){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(execute_method);
}
private:
contexto *recebimento, *escrita;
unsigned short e_rs1, e_rs2, e_rd, e_op,e_funct3,e_funct7,e_shamt;
int32_t e_imm_I,e_imm_U,e_imm_S,e_imm_B,e_imm_J;
int32_t _t1;
|
simple_bus_master_direct |
// ports
sc_in_clk clock;
sc_port<simple_bus_direct_if> bus_port;
// constructor
simple_bus_master_direct(sc_module_name name_
, unsigned int address
, int timeout
, bool verbose = true)
: sc_module(name_)
, m_address(address)
, m_timeout(timeout)
, m_verbose(verbose)
{
// process declaration
SC_THREAD(main_action);
}
// process
void main_action();
private:
unsigned int m_address;
int m_timeout;
bool m_verbose;
|
ic_csr_m2_s1 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// master[0]:
sc_in<bool> i_m0_req_valid;
sc_out<bool> o_m0_req_ready;
sc_in<sc_uint<CsrReq_TotalBits>> i_m0_req_type;
sc_in<sc_uint<12>> i_m0_req_addr;
sc_in<sc_uint<RISCV_ARCH>> i_m0_req_data;
sc_out<bool> o_m0_resp_valid;
sc_in<bool> i_m0_resp_ready;
sc_out<sc_uint<RISCV_ARCH>> o_m0_resp_data;
sc_out<bool> o_m0_resp_exception;
// master[1]
sc_in<bool> i_m1_req_valid;
sc_out<bool> o_m1_req_ready;
sc_in<sc_uint<CsrReq_TotalBits>> i_m1_req_type;
sc_in<sc_uint<12>> i_m1_req_addr;
sc_in<sc_uint<RISCV_ARCH>> i_m1_req_data;
sc_out<bool> o_m1_resp_valid;
sc_in<bool> i_m1_resp_ready;
sc_out<sc_uint<RISCV_ARCH>> o_m1_resp_data;
sc_out<bool> o_m1_resp_exception;
// slave[0]
sc_out<bool> o_s0_req_valid;
sc_in<bool> i_s0_req_ready;
sc_out<sc_uint<CsrReq_TotalBits>> o_s0_req_type;
sc_out<sc_uint<12>> o_s0_req_addr;
sc_out<sc_uint<RISCV_ARCH>> o_s0_req_data;
sc_in<bool> i_s0_resp_valid;
sc_out<bool> o_s0_resp_ready;
sc_in<sc_uint<RISCV_ARCH>> i_s0_resp_data;
sc_in<bool> i_s0_resp_exception;
void comb();
void registers();
SC_HAS_PROCESS(ic_csr_m2_s1);
ic_csr_m2_s1(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct ic_csr_m2_s1_registers {
sc_signal<bool> midx;
sc_signal<bool> acquired;
} v, r;
void ic_csr_m2_s1_r_reset(ic_csr_m2_s1_registers &iv) {
iv.midx = 0;
iv.acquired = 0;
}
|
sdctrl_cmd_transmitter |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_sclk_posedge;
sc_in<bool> i_sclk_negedge;
sc_in<bool> i_cmd;
sc_out<bool> o_cmd;
sc_out<bool> o_cmd_dir;
sc_out<bool> o_cmd_cs;
sc_in<bool> i_spi_mode; // SPI mode was selected by FW
sc_in<sc_uint<4>> i_err_code;
sc_in<bool> i_wdog_trigger; // Event from wdog timer
sc_in<bool> i_cmd_set_low; // Set forcibly o_cmd output to LOW
sc_in<bool> i_req_valid;
sc_in<sc_uint<6>> i_req_cmd;
sc_in<sc_uint<32>> i_req_arg;
sc_in<sc_uint<3>> i_req_rn; // R1, R3,R6 or R2
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<6>> o_resp_cmd; // Mirrored command
sc_out<sc_uint<32>> o_resp_reg; // Card Status, OCR register (R3) or RCA register (R6)
sc_out<sc_uint<7>> o_resp_crc7_rx; // Received CRC7
sc_out<sc_uint<7>> o_resp_crc7_calc; // Calculated CRC7
sc_out<sc_uint<15>> o_resp_spistatus; // {R1,R2} response valid only in SPI mode
sc_in<bool> i_resp_ready;
sc_out<bool> o_wdog_ena;
sc_out<bool> o_err_valid;
sc_out<sc_uint<4>> o_err_setcode;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cmd_transmitter);
sdctrl_cmd_transmitter(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cmd_transmitter();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
// Command request states:
static const uint8_t CMDSTATE_IDLE = 0;
static const uint8_t CMDSTATE_REQ_CONTENT = 1;
static const uint8_t CMDSTATE_REQ_CRC7 = 2;
static const uint8_t CMDSTATE_REQ_STOPBIT = 3;
static const uint8_t CMDSTATE_RESP_WAIT = 4;
static const uint8_t CMDSTATE_RESP_TRANSBIT = 5;
static const uint8_t CMDSTATE_RESP_CMD_MIRROR = 6;
static const uint8_t CMDSTATE_RESP_REG = 7;
static const uint8_t CMDSTATE_RESP_CID_CSD = 8;
static const uint8_t CMDSTATE_RESP_CRC7 = 9;
static const uint8_t CMDSTATE_RESP_STOPBIT = 10;
static const uint8_t CMDSTATE_RESP_SPI_R1 = 11;
static const uint8_t CMDSTATE_RESP_SPI_R2 = 12;
static const uint8_t CMDSTATE_RESP_SPI_DATA = 13;
static const uint8_t CMDSTATE_PAUSE = 15;
struct sdctrl_cmd_transmitter_registers {
sc_signal<sc_uint<6>> req_cmd;
sc_signal<sc_uint<3>> req_rn;
sc_signal<bool> resp_valid;
sc_signal<sc_uint<6>> resp_cmd;
sc_signal<sc_uint<32>> resp_arg;
sc_signal<sc_uint<15>> resp_spistatus;
sc_signal<sc_uint<40>> cmdshift;
sc_signal<sc_uint<6>> cmdmirror;
sc_signal<sc_uint<32>> regshift;
sc_signal<sc_biguint<120>> cidshift;
sc_signal<sc_uint<7>> crc_calc;
sc_signal<sc_uint<7>> crc_rx;
sc_signal<sc_uint<7>> cmdbitcnt;
sc_signal<bool> crc7_clear;
sc_signal<sc_uint<4>> cmdstate;
sc_signal<bool> err_valid;
sc_signal<sc_uint<4>> err_setcode;
sc_signal<bool> cmd_cs;
sc_signal<bool> cmd_dir;
sc_signal<bool> wdog_ena;
} v, r;
void sdctrl_cmd_transmitter_r_reset(sdctrl_cmd_transmitter_registers &iv) {
iv.req_cmd = 0;
iv.req_rn = 0;
iv.resp_valid = 0;
iv.resp_cmd = 0;
iv.resp_arg = 0;
iv.resp_spistatus = 0;
iv.cmdshift = ~0ull;
iv.cmdmirror = 0;
iv.regshift = 0;
iv.cidshift = 0;
iv.crc_calc = 0;
iv.crc_rx = 0;
iv.cmdbitcnt = 0;
iv.crc7_clear = 1;
iv.cmdstate = CMDSTATE_IDLE;
iv.err_valid = 0;
iv.err_setcode = CMDERR_NONE;
iv.cmd_cs = 1;
iv.cmd_dir = 1;
iv.wdog_ena = 0;
}
sc_signal<sc_uint<7>> wb_crc7;
sc_signal<bool> w_crc7_next;
sc_signal<bool> w_crc7_dat;
sdctrl_crc7 *crc0;
|
Shifter |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<4>> i_mode; // operation type: [0]0=rv64;1=rv32;[1]=sll;[2]=srl;[3]=sra
sc_in<sc_uint<RISCV_ARCH>> i_a1; // Operand 1
sc_in<sc_uint<6>> i_a2; // Operand 2
sc_out<sc_uint<RISCV_ARCH>> o_res; // Result
void comb();
void registers();
SC_HAS_PROCESS(Shifter);
Shifter(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct Shifter_registers {
sc_signal<sc_uint<RISCV_ARCH>> res;
} v, r;
void Shifter_r_reset(Shifter_registers &iv) {
iv.res = 0;
}
|
tb |
public:
sc_out<bool> inp_a[4], inp_b[4], inp_cin;
sc_in<bool> sum[4], co;
SC_HAS_PROCESS( tb );
bool a[6][4];
bool b[6][4];
tb( sc_module_name nm );
private:
void source();
void sink();
|
dut_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > finish;
cynw::cynw_p2p_base_out <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_x_out;
cynw::cynw_p2p_base_in <sc_dt::sc_int <(int)32 >, HLS::hls_enum <(int)1 > > find_max_return_in;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
// create the netlist
void InitInstances( sc_int< 32 > _A[10], sc_int< 32 > _B[10], sc_int< 32 > _D[10]);
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
SC_HAS_PROCESS(dut_wrapper);
dut_wrapper( sc_core::sc_module_name name, sc_int< 32 > _A[10], sc_int< 32 > _B[10], sc_int< 32 > _D[10] )
: sc_module(name)
,clk("clk")
,rst("rst")
,finish("finish")
,find_max_x_out("find_max_x_out")
,find_max_return_in("find_max_return_in")
,dut0(0)
{
InitInstances( _A, _B, _D);
InitThreads();
}
// destructor
~dut_wrapper()
{
DeleteInstances();
}
dut* dut0;
|
axictrl_bus0 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_out<dev_config_type> o_cfg; // Slave config descriptor
sc_vector<sc_in<axi4_master_out_type>> i_xmsto; // AXI4 masters output vector
sc_vector<sc_out<axi4_master_in_type>> o_xmsti; // AXI4 masters input vector
sc_vector<sc_in<axi4_slave_out_type>> i_xslvo; // AXI4 slaves output vectors
sc_vector<sc_out<axi4_slave_in_type>> o_xslvi; // AXI4 slaves input vectors
sc_vector<sc_out<mapinfo_type>> o_mapinfo; // AXI devices memory mapping information
void comb();
void registers();
SC_HAS_PROCESS(axictrl_bus0);
axictrl_bus0(sc_module_name name,
bool async_reset);
virtual ~axictrl_bus0();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct axictrl_bus0_registers {
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> r_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> r_sidx;
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> w_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> w_sidx;
sc_signal<sc_uint<CFG_BUS0_XMST_LOG2_TOTAL>> b_midx;
sc_signal<sc_uint<CFG_BUS0_XSLV_LOG2_TOTAL>> b_sidx;
} v, r;
void axictrl_bus0_r_reset(axictrl_bus0_registers &iv) {
iv.r_midx = CFG_BUS0_XMST_TOTAL;
iv.r_sidx = CFG_BUS0_XSLV_TOTAL;
iv.w_midx = CFG_BUS0_XMST_TOTAL;
iv.w_sidx = CFG_BUS0_XSLV_TOTAL;
iv.b_midx = CFG_BUS0_XMST_TOTAL;
iv.b_sidx = CFG_BUS0_XSLV_TOTAL;
}
sc_signal<mapinfo_type> wb_def_mapinfo;
sc_signal<axi4_slave_in_type> wb_def_xslvi;
sc_signal<axi4_slave_out_type> wb_def_xslvo;
sc_signal<bool> w_def_req_valid;
sc_signal<sc_uint<CFG_SYSBUS_ADDR_BITS>> wb_def_req_addr;
sc_signal<sc_uint<8>> wb_def_req_size;
sc_signal<bool> w_def_req_write;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_def_req_wdata;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BYTES>> wb_def_req_wstrb;
sc_signal<bool> w_def_req_last;
sc_signal<bool> w_def_req_ready;
sc_signal<bool> w_def_resp_valid;
sc_signal<sc_uint<CFG_SYSBUS_DATA_BITS>> wb_def_resp_rdata;
sc_signal<bool> w_def_resp_err;
axi_slv *xdef0;
|
tta_mem_arbiter |
/*MODULE INPUT INTERFACE */
sc_in<bool> clk;
sc_in<bool> rst_n;
sc_in<sc_bv<dataw_g/8> > bit_wr_x[ports_g];
sc_in<bool> en_x[ports_g];
sc_in<bool> wr_x[ports_g];
sc_in<sc_bv<dataw_g> > d[ports_g];
sc_in<sc_bv<addrw_g> > addr[ports_g];
/*MODULE OUTPUT INTERFACE */
sc_out<sc_bv<dataw_g> > q[ports_g];
sc_out<bool> waitrequest[ports_g];
/*RAM MODULE INTERFACE SIGNALS*/
sc_out<bool> ram_en_x;
sc_out<bool> ram_wr_x;
sc_out<sc_bv<dataw_g> > ram_d;
sc_in<sc_bv<dataw_g> > ram_q;
sc_out<sc_bv<dataw_g/8> > ram_bit_wr_x;
sc_out<sc_bv<addrw_g> > ram_addr;
/*MODULE INTERNAL SIGNALS */
sc_signal<bool> input_latch_load;
sc_signal<bool> latch_en_x[ports_g], latch_en_x_r[ports_g];
sc_signal<bool> latch_wr_x[ports_g], latch_wr_x_r[ports_g];
sc_signal<sc_bv<dataw_g/8> > latch_bit_wr_x[ports_g];
sc_signal<sc_bv<dataw_g/8> > latch_bit_wr_x_r[ports_g];
sc_signal<sc_bv<dataw_g> > latch_d[ports_g];
sc_signal<sc_bv<dataw_g> > latch_d_r[ports_g];
sc_signal<sc_bv<addrw_g> > latch_addr[ports_g];
sc_signal<sc_bv<addrw_g> > latch_addr_r[ports_g];
sc_signal<bool> output_latch_load;
sc_signal<sc_bv<dataw_g> > q_v[ports_g];
sc_signal<sc_bv<dataw_g> > q_v_r[ports_g];
sc_signal<int> selected_port;
sc_signal<bool> selected_port_mask_x[ports_g];
sc_signal<bool> selected_port_mask_x_r[ports_g];
sc_signal<bool> wait_rq_r_in [ports_g];
sc_signal<bool> wait_rq_r [ports_g];
int pointer;
void priority_encoder(){
ram_en_x = true;
selected_port = 0;
int i;
for(i=0; i<ports_g; i++){
selected_port_mask_x[i] = true;
}
for(i=0; i<ports_g; i++){
if(latch_en_x[i] == false){
ram_en_x = false;
selected_port = i;
selected_port_mask_x[i] = false;
//cout << "selected_port " << pointer << "\n";
//pointer = (pointer + 1)%ports_g;
break;
}
//pointer = (pointer + 1)%ports_g;
}
}
void regs(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
wait_rq_r[i] = false;
selected_port_mask_x_r[i] = true;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
wait_rq_r[i] = wait_rq_r_in[i];
selected_port_mask_x_r[i] = selected_port_mask_x[i];
}
}
}
void input_latch_seq(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
latch_en_x_r[i] = true;
latch_wr_x_r[i] = true;
latch_d_r[i] = 0;
latch_bit_wr_x_r[i] = -1;
latch_addr_r[i] = 0;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
//cout << " wait_rq_r_in " << wait_rq_r_in[i] << " : wait_rq_r " << wait_rq_r[i] << "\n";
if(wait_rq_r_in[i] == true && wait_rq_r[i] == false){
//cout << "hello\n";
latch_en_x_r[i] = en_x[i].read();
latch_wr_x_r[i] = wr_x[i].read();
latch_d_r[i] = d[i].read();
latch_bit_wr_x_r[i] = bit_wr_x[i].read();
latch_addr_r[i] = addr[i].read();
}
}
}
}
void input_latch_comb(){
int i;
for(i=0; i<ports_g; i++){
if(wait_rq_r[i] == true){
latch_en_x[i] = latch_en_x_r[i];
latch_wr_x[i] = latch_wr_x_r[i];
latch_d[i] = latch_d_r[i];
latch_bit_wr_x[i] = latch_bit_wr_x_r[i];
latch_addr[i] = latch_addr_r[i];
}
else{
latch_en_x[i] = en_x[i];
latch_wr_x[i] = wr_x[i];
latch_d[i] = d[i].read();
latch_bit_wr_x[i] = bit_wr_x[i].read();
latch_addr[i] = addr[i].read();
}
}
}
void output_latch_seq(){
int i;
if(rst_n == false){
for(i=0; i<ports_g; i++){
q_v_r[i] = 0;
}
}
else if(clk.posedge()){
for(i=0; i<ports_g; i++){
if( selected_port_mask_x_r[i] == false){
q_v_r[i] = ram_q;
}
}
}
}
void output_latch_comb(){
int i;
for(i=0; i<ports_g; i++){
if( selected_port_mask_x_r[i] == false){
q_v[i] = ram_q;
}
else{
q_v[i] = q_v_r[i];
}
}
}
void pack(){
int i;
for(i=0; i<ports_g; i++){
q[i].write(q_v[i].read());
}
}
void wires(){
ram_wr_x = latch_wr_x[selected_port];
ram_d = latch_d[selected_port];
ram_bit_wr_x = latch_bit_wr_x[selected_port];
ram_addr = latch_addr[selected_port];
int i;
for(i=0; i<ports_g; i++){
//cout << "latch_en_x_ " <<i << " : " << latch_en_x[i].read()<< "\n" ;
//cout << " selected_port_mask_x_" << i << " : " << selected_port_mask_x[i]<< "\n";
wait_rq_r_in[i].write( (latch_en_x[i] + selected_port_mask_x[i])%2); //XOR
waitrequest[i] = wait_rq_r[i];
//cout << " wait_rq_r_in_" << i << " : " << (latch_en_x[i] + selected_port_mask_x[i])%2 << "\n";
}
}
SC_CTOR(tta_mem_arbiter)
{
int i;
cout << "Constructing Memory arbiter " << name() << endl;
SC_METHOD(wires);
for(i=0; i<ports_g;i++){
sensitive << wait_rq_r[i] << latch_en_x[i] << latch_d[i] << latch_bit_wr_x[i] << latch_addr[i] << latch_wr_x[i] << selected_port_mask_x[i] << selected_port;
}
SC_METHOD(priority_encoder);
for(i=0; i<ports_g;i++){
sensitive << latch_en_x[i] << clk.pos();
}
SC_METHOD(regs);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(input_latch_seq);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(input_latch_comb);
for(i=0; i<ports_g;i++){
sensitive << wait_rq_r[i] << latch_en_x_r[i] << latch_d_r[i] << latch_bit_wr_x_r[i] << latch_addr_r[i] << en_x[i] << bit_wr_x[i] << d[i] << addr[i] << wr_x[i] << latch_wr_x_r[i];
}
SC_METHOD(output_latch_seq);
sensitive << clk.pos() << rst_n.neg();
SC_METHOD(output_latch_comb);
sensitive << ram_q;
for(i=0; i<ports_g;i++){
sensitive << q_v_r[i] << selected_port_mask_x_r[i];
}
SC_METHOD(pack);
for(i=0; i<ports_g;i++){
sensitive << q_v[i];
}
pointer = 0;
//RESET
for(i=0; i<ports_g; i++){
wait_rq_r[i] = false;
selected_port_mask_x_r[i] = true;
latch_en_x_r[i] = true;
latch_wr_x_r[i] = true;
latch_d_r[i] = 0;
latch_bit_wr_x_r[i] = -1;
latch_addr_r[i] = 0;
q_v_r[i] = 0;
}
}
|
TagMem |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i_wflags;
sc_out<sc_uint<abus>> o_raddr;
sc_out<sc_biguint<(8 * (1 << lnbits))>> o_rdata;
sc_out<sc_uint<flbits>> o_rflags;
sc_out<bool> o_hit;
// L2 snoop port, active when snoop = 1
sc_in<sc_uint<abus>> i_snoop_addr;
sc_out<sc_uint<flbits>> o_snoop_flags;
void comb();
void registers();
SC_HAS_PROCESS(TagMem);
TagMem(sc_module_name name,
bool async_reset);
virtual ~TagMem();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int TAG_BITS = ((abus - ibits) - lnbits);
static const int TAG_WITH_FLAGS = (TAG_BITS + flbits);
struct TagMem_registers {
sc_signal<sc_uint<TAG_BITS>> tagaddr;
sc_signal<sc_uint<ibits>> index;
sc_signal<sc_uint<TAG_BITS>> snoop_tagaddr;
} v, r;
void TagMem_r_reset(TagMem_registers &iv) {
iv.tagaddr = 0;
iv.index = 0;
iv.snoop_tagaddr = 0;
}
sc_signal<sc_uint<ibits>> wb_index;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_rdata;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tagi_wdata;
sc_signal<bool> w_tagi_we;
sc_signal<sc_uint<ibits>> wb_snoop_index;
sc_signal<sc_uint<TAG_BITS>> wb_snoop_tagaddr;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_snoop_rdata;
ram_cache_bwe_tech<ibits, (8 * (1 << lnbits))> *data0;
ram_tech<ibits, TAG_WITH_FLAGS> *tag0;
ram_tech<ibits, TAG_WITH_FLAGS> *tagsnoop0;
|
filter_load |
SC_MODULE_CLK_RESET_SIGNAL;
sc_out<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
SC_CTOR_DEFAULT(filter_load)
{
SC_CTHREAD(thread_filter_load, clk.pos());
reset_signal_is(reset,true);
}
void thread_filter_load()
{
sc_fixed<W_WIDTH,P_DATA> coeffs[N_ROWS * N_ROWS] = {1.0f, 0.0f, -1.0f,
2.0f, 0.0f, -2.0f,
1.0f, 0.0f, -1.0f |
TB_imfilter_top |
sc_clock clk;
sc_signal<bool> reset;
template<int W>
using imread = hwcore::tb::imread_func_fx<W,W/2>;
template<int W>
using imwrite = hwcore::tb::imwrite_func_fx<W,W/2>;
template<int W=TB_IMFILTER_W, int depth=16>
using fifo=hwcore::hf::sc_fifo_template< hwcore::pipes::sc_data_stream_t<W>, depth >;
hwcore::tb::sc_fileread<TB_IMFILTER_W, imread> fr_u1;
fifo<> u1_2_u2;
filter_load filter_loader;
sc_signal<sc_fixed<W_WIDTH,P_DATA> > Wout[3*3];
imfilter filter_u2;
fifo<> u2_2_u3;
hwcore::tb::sc_filewrite<TB_IMFILTER_W, imwrite> fw_u3;
SC_CTOR_DEFAULT(TB_imfilter_top)
:clk("clk",sc_time(10,SC_NS)),fr_u1("in_im_512_x_512.txt"), fw_u3("out_im_512_x_512.txt")
{
SC_MODULE_LINK(filter_u2);
SC_MODULE_LINK(filter_loader);
fr_u1.dout(u1_2_u2);
for(int i = 0; i < 3*3; i++)
{
filter_loader.Wout[i](Wout[i]);
filter_u2.Win[i](Wout[i]);
}
filter_u2.din(u1_2_u2);
filter_u2.dout(u2_2_u3);
fw_u3.din(u2_2_u3);
}
|
ALEXNET |
CONV_RELU_1 m_CONV_RELU_1;
MAX_POOLING_1 m_MAX_POOLING_1;
CONV_RELU_2 m_CONV_RELU_2;
MAX_POOLING_2 m_MAX_POOLING_2;
CONV_RELU_3 m_CONV_RELU_3;
CONV_RELU_4 m_CONV_RELU_4;
CONV_RELU_5 m_CONV_RELU_5;
MAX_POOLING_3 m_MAX_POOLING_3;
LINEAR_RELU_1 m_LINEAR_RELU_1;
LINEAR_RELU_2 m_LINEAR_RELU_2;
LINEAR_3 m_LINEAR_3;
sc_in < bool > clk, rst;
sc_in < bool > in_valid;
sc_fifo < bool > conv1_valid;
sc_fifo < bool > mp1_valid;
sc_fifo < bool > conv2_valid;
sc_fifo < bool > mp2_valid;
sc_fifo < bool > conv3_valid;
sc_fifo < bool > conv4_valid;
sc_fifo < bool > conv5_valid;
sc_fifo < bool > mp3_valid;
sc_fifo < bool > linear1_valid;
sc_fifo < bool > linear2_valid;
sc_out < bool > linear3_valid;
sc_vector < sc_in < sc_fixed_fast<45,17> > > image{"image", 150528 |
HW_Quant |
public:
//constructor
SC_CTOR(HW_Quant) {
//instantiate the Quantize thread
SC_THREAD(Quant_thread);
}
//define the Quantize thread method
void Quant_thread();
//TODO: define the FIFO buffer interfaces
//TODO: name them InBuffer and OutBuffer
sc_fifo_in<Block> InBuffer;
sc_fifo_out<Block> OutBuffer;
//TODO: define the interrupt ports
//TODO: name them int_input_seek, int_output_avail
sc_out<bool> int_input_seek, int_output_avail;
|
lenet |
sc_in_clk clock;
sc_in<bool> reset;
sc_out<bool> rom_rd;
sc_out<bool> ram_wr;
sc_out<sc_uint<16> > rom_addr;
sc_out<sc_uint<16> > ram_addr;
sc_in<TYPE > rom_data_in; // TYPE
sc_in<TYPE > ram_data_in; // TYPE
sc_out<TYPE > ram_data_out; // TYPE
sc_out<TYPE > result; // TYPE
sc_out<bool> valid;
void le();
ifstream fin;
int steps, times, i_ker, i_rom ;
bool readKernel, getBias ;
TYPE pic[28*28] ;
TYPE kernel5x5[5*5] ;
TYPE bias ;
int dir[25][2] ;
TYPE temp ;
int cnt ;
int curPixel ;
int i, j ;
int ramCnt ;
TYPE tempMaxPool ;
int dir2x2[4] ;
TYPE kernel5x5x6[5*5*6] ;
int depth ;
TYPE neuralSum ;
SC_CTOR(lenet)
{
readKernel = true ;
int p = 0 ;
dir2x2[0] = 0 ;
dir2x2[1] = 1 ;
dir2x2[2] = 24 ;
dir2x2[3] = 25 ;
for( p = 0 ; p < 5 ; ++p ) {
dir[p][0] = -2 ;
dir[p][1] = p-2 ;
}
for( ; p < 10 ; ++p ) {
dir[p][0] = -1 ;
dir[p][1] = p-7 ;
}
for( ; p < 15 ; ++p ) {
dir[p][0] = 0 ;
dir[p][1] = p-12 ;
}
for( ; p < 20 ; ++p ) {
dir[p][0] = 1 ;
dir[p][1] = p-17 ;
}
for( ; p < 25 ; ++p ) {
dir[p][0] = 2 ;
dir[p][1] = p-22 ;
}
fin.open(INPUT_FILE);
float f ;
for( p = 0 ; fin >> f ; ++p )
pic[p] = f/255 ;
SC_METHOD(le);
sensitive << clock.neg();
}
|
Sram |
sc_in<uint32_t> i_sram_addr;
sc_in<uint32_t> i_sram_dq;
sc_out<uint32_t> o_sram_dq;
sc_in<bool> i_sram_ce_n;
sc_in<bool> i_sram_we_n;
sc_in<bool> i_sram_oe_n;
sc_in<bool> i_sram_ub_n;
sc_in<bool> i_sram_lb_n;
SC_CTOR(Sram) {
SC_METHOD(process);
sensitive << i_sram_addr << i_sram_dq << i_sram_we_n << i_sram_ce_n << i_sram_oe_n << i_sram_ub_n << i_sram_lb_n;
m_sram = new uint16_t[sram_size >> 1];
dont_initialize();
}
void trace_all(sc_trace_file *tf, const std::string& parent_name);
void load_hex(const std::string& filename);
void load_bin(const std::string& filename);
void dump_mem(procyon::utils::dump_format_t group_fmt = procyon::utils::DUMP_FORMAT_4B, procyon::utils::dump_format_t line_fmt = procyon::utils::DUMP_FORMAT_16B);
~Sram();
private:
uint16_t* m_sram;
void process();
|
xtea_RTL_testbench |
private:
void run();
public:
sc_in_clk clk;
sc_out< bool > rst;
sc_in<sc_uint<1> > dout_rdy; // output from xtea module
sc_in<sc_uint<32> > result0_in;
sc_in<sc_uint<32> > result1_in;
sc_out<sc_uint<1> > din_rdy; // input for xtea module
sc_out<sc_uint<32> > word0_out;
sc_out<sc_uint<32> > word1_out;
sc_out<sc_uint<32> > key0_out;
sc_out<sc_uint<32> > key1_out;
sc_out<sc_uint<32> > key2_out;
sc_out<sc_uint<32> > key3_out;
sc_out< bool > mode_out;
SC_CTOR(xtea_RTL_testbench) {
SC_THREAD(run);
sensitive << clk.pos();
}
|
fetch |
sc_port <mem_if> p_mem;
sc_port <breg_if> p_breg;
sc_fifo_in < contexto*> execute_fetch;
sc_fifo_out < contexto* > fetch_decode;
void fetch_method(){
while(true){
recebimento = execute_fetch.read();
escrita = recebimento;
PC = (p_breg->read(31));
#ifdef RASTREIA_PC
cout << "PC = " << PC << endl;
#endif
escrita->ri = p_mem->read(PC);
//Registrador 31 = PC
p_breg->write(31, PC +1);
//Instrucao que nao faz sentido lw $0, $0
//Interrompe execucao
if(escrita->ri == 0){
p_breg->dump_breg();
sc_stop();
exit(0);
} //if
fetch_decode.write(escrita);
} // while
}
SC_CTOR(fetch){
recebimento = new contexto();
escrita = new contexto();
SC_THREAD(fetch_method);
}
private:
contexto *escrita;
contexto *recebimento;
uint32_t PC;
|
gndemux |
sc_port< sc_signal_out_if<gn_mixed>,0 > pin {"pin" |
sdctrl_crc16 |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<bool> i_clear; // Clear CRC register;
sc_in<bool> i_next; // Shift enable strob
sc_in<bool> i_dat; // Input bit
sc_out<sc_uint<16>> o_crc15; // Computed value
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_crc16);
sdctrl_crc16(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct sdctrl_crc16_registers {
sc_signal<sc_uint<16>> crc16;
} v, r;
void sdctrl_crc16_r_reset(sdctrl_crc16_registers &iv) {
iv.crc16 = 0;
}
|
RegIntBank |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<6>> i_radr1; // Port 1 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata1; // Port 1 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag1; // Port 1 read tag value
sc_in<sc_uint<6>> i_radr2; // Port 2 read address
sc_out<sc_uint<RISCV_ARCH>> o_rdata2; // Port 2 read value
sc_out<sc_uint<CFG_REG_TAG_WIDTH>> o_rtag2; // Port 2 read tag value
sc_in<sc_uint<6>> i_waddr; // Writing value
sc_in<bool> i_wena; // Writing is enabled
sc_in<sc_uint<CFG_REG_TAG_WIDTH>> i_wtag; // Writing register tag
sc_in<sc_uint<RISCV_ARCH>> i_wdata; // Writing value
sc_in<bool> i_inorder; // Writing only if tag sequenced
sc_out<bool> o_ignored; // Sequenced writing is ignored because it was overwritten by executor (need for tracer)
sc_in<sc_uint<6>> i_dport_addr; // Debug port address
sc_in<bool> i_dport_ena; // Debug port is enabled
sc_in<bool> i_dport_write; // Debug port write is enabled
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Debug port write value
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Debug port read value
sc_out<sc_uint<RISCV_ARCH>> o_ra; // Return address for branch predictor
sc_out<sc_uint<RISCV_ARCH>> o_sp; // Stack Pointer for border control
sc_out<sc_uint<RISCV_ARCH>> o_gp;
sc_out<sc_uint<RISCV_ARCH>> o_tp;
sc_out<sc_uint<RISCV_ARCH>> o_t0;
sc_out<sc_uint<RISCV_ARCH>> o_t1;
sc_out<sc_uint<RISCV_ARCH>> o_t2;
sc_out<sc_uint<RISCV_ARCH>> o_fp;
sc_out<sc_uint<RISCV_ARCH>> o_s1;
sc_out<sc_uint<RISCV_ARCH>> o_a0;
sc_out<sc_uint<RISCV_ARCH>> o_a1;
sc_out<sc_uint<RISCV_ARCH>> o_a2;
sc_out<sc_uint<RISCV_ARCH>> o_a3;
sc_out<sc_uint<RISCV_ARCH>> o_a4;
sc_out<sc_uint<RISCV_ARCH>> o_a5;
sc_out<sc_uint<RISCV_ARCH>> o_a6;
sc_out<sc_uint<RISCV_ARCH>> o_a7;
sc_out<sc_uint<RISCV_ARCH>> o_s2;
sc_out<sc_uint<RISCV_ARCH>> o_s3;
sc_out<sc_uint<RISCV_ARCH>> o_s4;
sc_out<sc_uint<RISCV_ARCH>> o_s5;
sc_out<sc_uint<RISCV_ARCH>> o_s6;
sc_out<sc_uint<RISCV_ARCH>> o_s7;
sc_out<sc_uint<RISCV_ARCH>> o_s8;
sc_out<sc_uint<RISCV_ARCH>> o_s9;
sc_out<sc_uint<RISCV_ARCH>> o_s10;
sc_out<sc_uint<RISCV_ARCH>> o_s11;
sc_out<sc_uint<RISCV_ARCH>> o_t3;
sc_out<sc_uint<RISCV_ARCH>> o_t4;
sc_out<sc_uint<RISCV_ARCH>> o_t5;
sc_out<sc_uint<RISCV_ARCH>> o_t6;
void comb();
void registers();
SC_HAS_PROCESS(RegIntBank);
RegIntBank(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
struct RegValueType {
sc_signal<sc_uint<RISCV_ARCH>> val;
sc_signal<sc_uint<CFG_REG_TAG_WIDTH>> tag;
|
_sc_stream_buffer |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
_sc_stream_buffer_not_stream_while_write |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
enum ctrls { newset = 0, reapeat = 1 |
dut |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_out< sc_uint< 6 > > mem_A0;
sc_out< bool > mem_REQ0;
SC_CTOR(dut);
|
dut |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256 > mem;
SC_HAS_PROCESS(dut);
dut_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) );
|
dut_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
cynw::cynw_p2p_base_in <sc_dt::sc_uint <(int)8 >, CYN::cyn_enum <(int)1 > > din;
cynw::cynw_p2p_base_out <sc_dt::sc_uint <(int)11 >, CYN::cyn_enum <(int)1 > > dout;
RAM_64x8::port <CYN::cyn_enum <(int)1 >, sc_dt::sc_uint <(int)8 >, (HLS::HLS_INDEX_MAPPING_OPTIONS)256 > mem;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
enum Representation { BDWRep_None, BDWRep_Behavioral, BDWRep_RTL_C, BDWRep_RTL_HDL, BDWRep_Gates, BDWRep_CYC_HDL |
dut_wrapper_r |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 11 > > dout_data;
sc_out< bool > mem_WE0;
sc_out< sc_uint< 8 > > mem_DIN0;
sc_in< sc_uint< 8 > > mem_DOUT0;
sc_out< sc_uint< 6 > > mem_A0;
sc_out< bool > mem_REQ0;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
enum Representation { BDWRep_None, BDWRep_Behavioral, BDWRep_RTL_C, BDWRep_RTL_HDL, BDWRep_Gates, BDWRep_CYC_HDL |
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
or_gate |
sc_inout<bool> a;
sc_inout<bool> b;
sc_out<bool> c;
void or_process( void )
{
c = a.read() || b.read();
}
void test_process( void )
{
assert( (a.read() || b.read() ) == c.read() );
}
SC_CTOR( or_gate )
{
}
|
top)
//| {
//| sc_process_handle run_proc;
//|
//| SC_CTOR(top |
//| run_proc = sc_spawn(sc_bind(&run_phase,this),"run_phase");
//| |
ic_dport |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// DMI connection
sc_in<sc_uint<CFG_LOG2_CPU_MAX>> i_hartsel; // Selected hart index
sc_in<bool> i_haltreq;
sc_in<bool> i_resumereq;
sc_in<bool> i_resethaltreq; // Halt core after reset request
sc_in<bool> i_hartreset; // Reset currently selected hart
sc_in<bool> i_dport_req_valid; // Debug access from DSU is valid
sc_in<sc_uint<DPortReq_Total>> i_dport_req_type; // Debug access types
sc_in<sc_uint<RISCV_ARCH>> i_dport_addr; // Register index
sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Write value
sc_in<sc_uint<3>> i_dport_size; // 0=1B;1=2B;2=4B;3=8B;4=128B
sc_out<bool> o_dport_req_ready; // Response is ready
sc_in<bool> i_dport_resp_ready; // ready to accept response
sc_out<bool> o_dport_resp_valid; // Response is valid
sc_out<bool> o_dport_resp_error; // Something goes wrong
sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Response value or error code
// To Cores cluster
sc_vector<sc_out<dport_in_type>> o_dporti;
sc_vector<sc_in<dport_out_type>> i_dporto;
void comb();
void registers();
SC_HAS_PROCESS(ic_dport);
ic_dport(sc_module_name name,
bool async_reset);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const uint8_t ALL_CPU_MASK = ((1 << CFG_CPU_MAX) - 1);
struct ic_dport_registers {
sc_signal<sc_uint<CFG_LOG2_CPU_MAX>> hartsel;
} v, r;
void ic_dport_r_reset(ic_dport_registers &iv) {
iv.hartsel = 0;
}
|
RAM |
sc_in_clk CLK;
sc_in<bool> RESET_N;
sc_in<sc_uint<32>> ADR_I;
sc_in<sc_uint<32>> DAT_I;
sc_in<bool> VALID_I;
sc_in<bool> WE_I;
sc_in<sc_uint<2>> MEM_SIZE;
sc_out<sc_uint<32>> DAT_O;
//signals
sc_signal<sc_uint<4>> current_state;
sc_signal<sc_uint<4>> future_state;
std::unordered_map<int,int>* RAM_REGISTERS;
void init_mem(std::unordered_map<int,int>*);
void reponse();
void trace(sc_trace_file*);
SC_CTOR(RAM)
{
SC_METHOD(reponse);
sensitive << CLK.neg();
}
|
dut_type_wrapper |
public:
#if defined ( ioConfig_TLM )
sc_in< bool > clk;
sc_in< bool > rst;
#else
sc_in< bool > clk;
sc_in< bool > rst;
#endif
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
#if defined ( ioConfig_TLM )
#else
#endif
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
#if defined ( ioConfig_TLM )
,clk("clk")
,rst("rst")
#else
,clk("clk")
,rst("rst")
#endif
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
|
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
i2c |
public:
sc_out<bool> scl_en_o {"scl_en_o" |
FIFO |
enum ic_addresses {
ICCONF = 0x18,
ICBUF = 0x1C
|
AESLCFUComp |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp );
AESLFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ if (super) return super->compute(in0, in1);
else return sc_lv<DOUT_WIDTH>(); }
void thread_compute() {
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] input: %llx %llx\n",
din0.read().to_uint64(),
din1.read().to_uint64());
else
printf("[ACMP_ADD] input: %x %x\n",
din0.read().to_uint(),
din1.read().to_uint());
});
sc_lv<DOUT_WIDTH> result = compute(din0.read(), din1.read());
dout.write(result);
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] comb output: %llx\n", result.to_uint64());
else
printf("[ACMP_ADD] comb output: %x\n", result.to_uint());
});
}
|
AESLFUComp |
AESLCFUComp<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
/// Dont use stage_regvec[0].
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
SC_CTOR( AESLFUComp );
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ return sc_lv<DOUT_WIDTH>(); }
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] reg output %llx\n",
stage_regvec[NUM_STAGE-1].read().to_uint64());
else
printf("[ACMP_ADD] reg output %x\n",
stage_regvec[NUM_STAGE-1].read().to_uint());
});
}
|
AESLCFUComp_seq |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR( AESLCFUComp_seq );
AESLFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> *super;
virtual void sanity_check() {}
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ if (super) return super->compute(in0, in1);
else return sc_lv<DOUT_WIDTH>(); }
void thread_compute() {
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] input: %llx %llx\n",
din0.read().to_uint64(),
din1.read().to_uint64());
else
printf("[ACMP_ADD] input: %x %x\n",
din0.read().to_uint(),
din1.read().to_uint());
});
sc_lv<DOUT_WIDTH> result = compute(din0.read(), din1.read());
dout.write(result);
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] comb output: %llx\n", result.to_uint64());
else
printf("[ACMP_ADD] comb output: %x\n", result.to_uint());
});
}
|
AESLFUComp_seq |
AESLCFUComp_seq<NUM_STAGE, DIN0_WIDTH, DIN1_WIDTH, DOUT_WIDTH> core;
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_logic > start;
sc_in< sc_logic > done;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_in< sc_lv<DIN1_WIDTH> > din1;
sc_out< sc_lv<DOUT_WIDTH> > dout;
/// Dont use stage_regvec[0].
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
SC_CTOR( AESLFUComp_seq );
virtual sc_lv<DOUT_WIDTH>
compute(const sc_lv<DIN0_WIDTH>& in0, const sc_lv<DIN1_WIDTH>& in1)
{ return sc_lv<DOUT_WIDTH>(); }
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
{
if (DIN0_WIDTH == 64)
printf("[ACMP_ADD] reg output %llx\n",
stage_regvec[NUM_STAGE-1].read().to_uint64());
else
printf("[ACMP_ADD] reg output %x\n",
stage_regvec[NUM_STAGE-1].read().to_uint());
});
}
|
AESLCFUMOComp |
public:
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLCFUMOComp ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
&& NUM_STAGE == 1);
SC_METHOD( thread_compute );
sensitive << opcode << din;
}
//virtual sc_lv<DOUT_WIDTH>
//compute(const sc_lv<OPC_WIDTH>& opcode, const sc_lv<DIN_WIDTH>& in) {
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* mCore;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* core) {
mCore = core;
}
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* getComputeCore() {
return mCore;
}
public:
void thread_compute() {
DEBUG( cerr << "[ACMP] " << name() << " Input: "
<< din.read() << endl; );
assert(mCore);
sc_lv<DOUT_WIDTH> result;
if (din.read().is_01()) {
result = mCore->compute(opcode.read(), din.read());
}
else {
result = sc_lv<DOUT_WIDTH>();
}
dout.write(result);
DEBUG( cerr << "[ACMP] " << name() << " C-out: "
<< result << endl;);
}
|
AESLFUMultiCycle |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN_WIDTH> > din;
sc_out< sc_lv<DOUT_WIDTH> > dout;
public:
SC_CTOR( AESLFUMultiCycle ) {
assert(OPC_WIDTH > 0 && DIN_WIDTH > 0 && DOUT_WIDTH > 0
&& NUM_STAGE > 0);
SC_METHOD( thread_compute );
sensitive << opcode << din;
sensitive << clk;
if (NUM_STAGE > 1)
{
SC_METHOD( thread_stage );
sensitive << (clk.pos());
}
}
//virtual sc_lv<DOUT_WIDTH>
//compute(const sc_lv<OPC_WIDTH>& opcode, const sc_lv<DIN_WIDTH>& in) {
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* mCore;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* core) {
mCore = core;
}
FUComputeCore<OPC_WIDTH, DIN_WIDTH, DOUT_WIDTH>* getComputeCore() {
return mCore;
}
public:
sc_signal< sc_lv<DOUT_WIDTH> > stage_regvec[NUM_STAGE];
void thread_compute() {
DEBUG( cerr << "[ACMP] " << name() << " Input: "
<< din.read() << endl; );
assert(mCore);
sc_lv<DOUT_WIDTH> result;
if (din.read().is_01() && opcode.read().is_01()) {
result = mCore->compute(opcode.read(), din.read());
}
else {
result = sc_lv<DOUT_WIDTH>();
}
if (NUM_STAGE > 1)
stage_regvec[1].write(result);
else
dout.write(result);
DEBUG( cerr << "[ACMP] " << name() << " C-out: "
<< result << endl;);
}
void thread_stage() {
if (ce.read() == SC_LOGIC_0) return;
dout.write(stage_regvec[NUM_STAGE-1]);
for (unsigned i = NUM_STAGE-1; i > 1; --i) {
stage_regvec[i].write(stage_regvec[i-1].read());
}
DEBUG(
cerr << "[ACMP] " << name() << " R-out: "
<< stage_regvec[NUM_STAGE-1].read() << endl;);
}
|
CFUUnaryOp |
public:
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(CFUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCModule->opcode(sigone);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
}
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<1, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
private:
sc_signal< sc_lv<1> > sigone;
sc_signal< bool > clk;
sc_signal< sc_logic > reset;
sc_signal< sc_logic > ce;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
}
|
FUUnaryOp |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>("u_U");
mMCModule->opcode(sigone);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
SC_METHOD(IOConnection);
sensitive << clk;
}
AESLFUMultiCycle<NUM_STAGE, 1, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<1, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
private:
sc_signal< sc_lv<1> > sigone;
void IOConnection() {
sigone.write(sc_lv<1>("1"));
}
|
FUMOUnaryOp |
public:
sc_in< bool > clk;
sc_in< sc_logic > reset;
sc_in< sc_logic > ce;
sc_in< sc_lv<OPC_WIDTH> > opcode;
sc_in< sc_lv<DIN0_WIDTH> > din0;
sc_out< sc_lv<DOUT_WIDTH> > dout;
SC_CTOR(FUMOUnaryOp) {
mMCModule =
new AESLFUMultiCycle
<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>("mu_U");
mMCModule->opcode(opcode);
mMCModule->din(din0);
mMCModule->dout(dout);
mMCModule->clk(clk);
mMCModule->reset(reset);
mMCModule->ce(ce);
}
AESLFUMultiCycle<NUM_STAGE, OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>* mMCModule;
void setComputeCore(FUComputeCore<OPC_WIDTH, DIN0_WIDTH, DOUT_WIDTH>* core) {
mMCModule->setComputeCore(core);
}
|
Monitor |
sc_in_clk clk;
sc_in < bool > rst;
sc_in < DATA_TYPE > data_in;
sc_in < bool > data_valid;
void monitor();
int x, cycle;
SC_CTOR( Monitor )
{
x = 0;
cycle = 0;
SC_METHOD( monitor );
sensitive << clk.pos();
}
|
Showcase0 |
// ports
sc_in<sc_uint<32>> a;
sc_in<sc_int<32>> b;
sc_out<sc_uint<32>> c;
sc_in_clk clk;
sc_out<sc_uint<1>> cmp_0;
sc_out<sc_uint<1>> cmp_1;
sc_out<sc_uint<1>> cmp_2;
sc_out<sc_uint<1>> cmp_3;
sc_out<sc_uint<1>> cmp_4;
sc_out<sc_uint<1>> cmp_5;
sc_out<sc_uint<32>> contOut;
sc_in<sc_uint<32>> d;
sc_in<sc_uint<1>> e;
sc_out<sc_uint<1>> f;
sc_out<sc_uint<16>> fitted;
sc_out<sc_uint<8>> g;
sc_out<sc_uint<8>> h;
sc_in<sc_uint<2>> i;
sc_out<sc_uint<8>> j;
sc_out<sc_uint<32>> k;
sc_out<sc_uint<1>> out;
sc_out<sc_uint<1>> output;
sc_in<sc_uint<1>> rst_n;
sc_out<sc_uint<8>> sc_signal_0;
// component instances
// internal signals
sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
sc_int<8> fallingEdgeRam[4];
sc_uint<1> r = sc_uint<1>("0b0");
sc_uint<2> r_0 = sc_uint<2>("0b00");
sc_uint<2> r_1 = sc_uint<2>("0b00");
sc_signal<sc_uint<1>> r_next;
sc_signal<sc_uint<2>> r_next_0;
sc_signal<sc_uint<2>> r_next_1;
sc_uint<8> rom[4] = {sc_uint<8>("0x00"),
sc_uint<8>("0x01"),
sc_uint<8>("0x02"),
sc_uint<8>("0x03"),
|
CONV_RELU_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 150528 |
MAX_POOLING_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 193600 |
CONV_RELU_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 46656 |
MAX_POOLING_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 139968 |
CONV_RELU_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 32448 |
CONV_RELU_4 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 64896 |
CONV_RELU_5 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264 |
MAX_POOLING_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 43264 |
LINEAR_RELU_1 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 9216 |
LINEAR_RELU_2 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096 |
LINEAR_3 |
sc_in<bool> clk;
sc_in<bool> rst;
sc_vector<sc_in<sc_fixed_fast<45,17>>> in_feature_map{"in_feature_map", 4096 |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
sdctrl_cache |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Data path:
sc_in<bool> i_req_valid;
sc_in<bool> i_req_write;
sc_in<sc_uint<CFG_SDCACHE_ADDR_BITS>> i_req_addr;
sc_in<sc_uint<64>> i_req_wdata;
sc_in<sc_uint<8>> i_req_wstrb;
sc_out<bool> o_req_ready;
sc_out<bool> o_resp_valid;
sc_out<sc_uint<64>> o_resp_data;
sc_out<bool> o_resp_err;
sc_in<bool> i_resp_ready;
// Memory interface:
sc_in<bool> i_req_mem_ready;
sc_out<bool> o_req_mem_valid;
sc_out<bool> o_req_mem_write;
sc_out<sc_uint<CFG_SDCACHE_ADDR_BITS>> o_req_mem_addr;
sc_out<sc_biguint<SDCACHE_LINE_BITS>> o_req_mem_data;
sc_in<bool> i_mem_data_valid;
sc_in<sc_biguint<SDCACHE_LINE_BITS>> i_mem_data;
sc_in<bool> i_mem_fault;
// Debug interface
sc_in<bool> i_flush_valid;
sc_out<bool> o_flush_end;
void comb();
void registers();
SC_HAS_PROCESS(sdctrl_cache);
sdctrl_cache(sc_module_name name,
bool async_reset);
virtual ~sdctrl_cache();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int abus = CFG_SDCACHE_ADDR_BITS;
static const int ibits = CFG_LOG2_SDCACHE_LINEBITS;
static const int lnbits = CFG_LOG2_SDCACHE_BYTES_PER_LINE;
static const int flbits = SDCACHE_FL_TOTAL;
// State machine states:
static const uint8_t State_Idle = 0;
static const uint8_t State_CheckHit = 2;
static const uint8_t State_TranslateAddress = 3;
static const uint8_t State_WaitGrant = 4;
static const uint8_t State_WaitResp = 5;
static const uint8_t State_CheckResp = 6;
static const uint8_t State_SetupReadAdr = 1;
static const uint8_t State_WriteBus = 7;
static const uint8_t State_FlushAddr = 8;
static const uint8_t State_FlushCheck = 9;
static const uint8_t State_Reset = 10;
static const uint8_t State_ResetWrite = 11;
static const uint64_t LINE_BYTES_MASK = ((1 << CFG_LOG2_SDCACHE_BYTES_PER_LINE) - 1);
static const uint32_t FLUSH_ALL_VALUE = ((1 << ibits) - 1);
struct sdctrl_cache_registers {
sc_signal<bool> req_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> req_addr;
sc_signal<sc_uint<64>> req_wdata;
sc_signal<sc_uint<8>> req_wstrb;
sc_signal<sc_uint<4>> state;
sc_signal<bool> req_mem_valid;
sc_signal<bool> req_mem_write;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> mem_addr;
sc_signal<bool> mem_fault;
sc_signal<bool> write_first;
sc_signal<bool> write_flush;
sc_signal<bool> req_flush;
sc_signal<sc_uint<32>> flush_cnt;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_addr_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_i;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> cache_line_o;
} v, r;
void sdctrl_cache_r_reset(sdctrl_cache_registers &iv) {
iv.req_write = 0;
iv.req_addr = 0;
iv.req_wdata = 0;
iv.req_wstrb = 0;
iv.state = State_Reset;
iv.req_mem_valid = 0;
iv.req_mem_write = 0;
iv.mem_addr = 0;
iv.mem_fault = 0;
iv.write_first = 0;
iv.write_flush = 0;
iv.req_flush = 0;
iv.flush_cnt = 0;
iv.line_addr_i = 0;
iv.cache_line_i = 0;
iv.cache_line_o = 0;
}
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_wdata_i;
sc_signal<sc_uint<SDCACHE_BYTES_PER_LINE>> line_wstrb_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_wflags_i;
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_raddr_o;
sc_signal<sc_biguint<SDCACHE_LINE_BITS>> line_rdata_o;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_rflags_o;
sc_signal<bool> line_hit_o;
// Snoop signals:
sc_signal<sc_uint<CFG_SDCACHE_ADDR_BITS>> line_snoop_addr_i;
sc_signal<sc_uint<SDCACHE_FL_TOTAL>> line_snoop_flags_o;
TagMem<abus, ibits, lnbits, flbits, 0> *mem0;
|
pch_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; //
sc_in<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_lv<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_in<sc_lv<GRF_WIDTH> > even_in[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_in<sc_lv<GRF_WIDTH> > odd_in[CORES_PER_PCH]; // Direct data in/out to the odd banks
sc_in<sc_lv<GRF_WIDTH> > even_out[CORES_PER_PCH];// Direct data in/out to the even banks
sc_in<sc_lv<GRF_WIDTH> > odd_out[CORES_PER_PCH]; // Direct data in/out to the odd banks
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> RD; // DRAM read command
sc_in<bool> WR; // DRAM write command
sc_in<bool> ACT; // DRAM activate command
// sc_in<bool> RSTB; //
sc_in<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<bool> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_uint<DQ_BITS> > DQ; // Data input from DRAM controller (output makes no sense)
sc_inout_rv<GRF_WIDTH> even_buses[CORES_PER_PCH]; // Direct data in/out to the even banks
sc_inout_rv<GRF_WIDTH> odd_buses[CORES_PER_PCH]; // Direct data in/out to the odd banks
#endif
// Internal events
// Internal variables and signals for checking
SC_CTOR(pch_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos() << rst.neg();
}
void monitor_thread(); // Outputs the behavior and automatically checks the functionality
// void mirror_thread(); // Mirror IMC core behavior for checking its functionality
// void out_mirror_thread(); // Mirror IMC core output for checking functionality
|
_sc_stream_stitching |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T din_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T dout_T;
sc_in<bool> clk, reset;
sc_fifo_in<din_T> din_buf;
sc_fifo_in<din_T> din;
sc_fifo_out<dout_T> dout;
sc_fifo_in<sc_uint<16> > ctrl_depth;
sc_fifo_in<sc_uint<16> > ctrl_buf_depth;
SC_CTOR(_sc_stream_stitching) {
SC_CTHREAD(thread, clk.pos());
reset_signal_is(reset, true);
}
void thread() {
din_T tmp_in;
while (true) {
sc_uint<16> depth = ctrl_depth.read();
sc_uint<16> buf_depth = ctrl_buf_depth.read();
sc_uint<16> ptr = 0;
bool last = false;
do {
hls_pipeline(1);
if (ptr < buf_depth) {
tmp_in = din_buf.read();
tmp_in.tlast = 0;
} else {
tmp_in = din.read();
last = (tmp_in.tlast == 1);
}
dout.write(tmp_in);
ptr = (ptr + 1 >= depth ? sc_uint<16>(0) : sc_uint<16>(ptr + 1));
} while (!last);
}
}
|
PowerButton |
//port(s) connected to outside
sc_in<bool> pt_pressed;
//port(s) inside the phone
sc_out<bool> shortPress;
sc_out<bool> longPress;
//internal variables
sc_time lastTimeStamp;
sc_time interval_3S;
//constructor
SC_HAS_PROCESS(PowerButton);
PowerButton(sc_module_name name){
shortPress.initialize(false);
longPress.initialize(false);
interval_3S=sc_time(3,SC_SEC);
lastTimeStamp=sc_time_stamp()-interval_3S;
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("powerButton init");
#endif
SC_METHOD(run);
sensitive<<pt_pressed;
}
void run(){
if(pt_pressed.read()==true){
lastTimeStamp=sc_time_stamp();
longPress.write(false);
shortPress.write(false);
}
else {
sc_time now=sc_time_stamp();
if(now-lastTimeStamp<interval_3S){
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("short press");
#endif
shortPress.write(true);
}else{
#if defined(DEBUG_POWERBUTTON) || defined(DEBUG)
print("long press");
#endif
longPress.write(true);
}
}
}
//print given string on cout
void print(string s){
cout << "[" << sc_time_stamp() << " / " << sc_delta_count() << "](" << name() << "): " << s << endl;
}
|
{project} | {\n"
// " extern int instr_cntr;\n"
" std::ofstream instr_log;\n"
" std::ofstream instr_update_log;\n" // add instruction state update logging
" int GetInstrCntr();\n"
" void IncrementInstrCntr();\n"
" void LogInstrSequence(const std::string& instr_name);\n",
fmt::arg("project", GetProjectName()));
// input
for (auto& var : absknob::GetInp(m_)) {
fmt::format_to(buff,
" sc_in<{var_type}> {var_name}_in;\n"
" {var_type} {var_name |
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
nand_gate |
public:
sc_in<bool> inp_a, inp_b;
sc_out<bool> out;
SC_HAS_PROCESS(nand_gate);
nand_gate(sc_module_name nm);
private:
void nand_main(void);
|
CacheTop |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
// Control path:
sc_in<bool> i_req_ctrl_valid; // Control request from CPU Core is valid
sc_in<sc_uint<RISCV_ARCH>> i_req_ctrl_addr; // Control request address
sc_out<bool> o_req_ctrl_ready; // Control request from CPU Core is accepted
sc_out<bool> o_resp_ctrl_valid; // ICache response is valid and can be accepted
sc_out<sc_uint<RISCV_ARCH>> o_resp_ctrl_addr; // ICache response address
sc_out<sc_uint<64>> o_resp_ctrl_data; // ICache read data
sc_out<bool> o_resp_ctrl_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_in<bool> i_resp_ctrl_ready; // CPU Core is ready to accept ICache response
// Data path:
sc_in<bool> i_req_data_valid; // Data path request from CPU Core is valid
sc_in<sc_uint<MemopType_Total>> i_req_data_type; // Data write memopy operation flag
sc_in<sc_uint<RISCV_ARCH>> i_req_data_addr; // Memory operation address
sc_in<sc_uint<64>> i_req_data_wdata; // Memory operation write value
sc_in<sc_uint<8>> i_req_data_wstrb; // 8-bytes aligned strob
sc_in<sc_uint<2>> i_req_data_size;
sc_out<bool> o_req_data_ready; // Memory operation request accepted by DCache
sc_out<bool> o_resp_data_valid; // DCache response is ready
sc_out<sc_uint<RISCV_ARCH>> o_resp_data_addr; // DCache response address
sc_out<sc_uint<64>> o_resp_data_data; // DCache response read data
sc_out<bool> o_resp_data_load_fault; // Bus response ERRSLV or ERRDEC on read
sc_out<bool> o_resp_data_store_fault; // Bus response ERRSLV or ERRDEC on write
sc_in<bool> i_resp_data_ready; // CPU Core is ready to accept DCache repsonse
// Memory interface:
sc_in<bool> i_req_mem_ready; // System Bus is ready to accept memory operation request
sc_out<bool> o_req_mem_path; // 1=ctrl; 0=data path
sc_out<bool> o_req_mem_valid; // AXI memory request is valid
sc_out<sc_uint<REQ_MEM_TYPE_BITS>> o_req_mem_type; // AXI memory request type
sc_out<sc_uint<3>> o_req_mem_size; // request size: 0=1 B;...; 7=128 B
sc_out<sc_uint<CFG_CPU_ADDR_BITS>> o_req_mem_addr; // AXI memory request address
sc_out<sc_uint<L1CACHE_BYTES_PER_LINE>> o_req_mem_strob;// Writing strob. 1 bit per Byte (uncached only)
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_req_mem_data; // Writing data
sc_in<bool> i_resp_mem_valid; // AXI response is valid
sc_in<bool> i_resp_mem_path; // 0=ctrl; 1=data path
sc_in<sc_biguint<L1CACHE_LINE_BITS>> i_resp_mem_data; // Read data
sc_in<bool> i_resp_mem_load_fault; // data load error
sc_in<bool> i_resp_mem_store_fault; // data store error
// PMP interface:
sc_in<bool> i_pmp_ena; // PMP is active in S or U modes or if L/MPRV bit is set in M-mode
sc_in<bool> i_pmp_we; // write enable into PMP
sc_in<sc_uint<CFG_PMP_TBL_WIDTH>> i_pmp_region; // selected PMP region
sc_in<sc_uint<RISCV_ARCH>> i_pmp_start_addr; // PMP region start address
sc_in<sc_uint<RISCV_ARCH>> i_pmp_end_addr; // PMP region end address (inclusive)
sc_in<sc_uint<CFG_PMP_FL_TOTAL>> i_pmp_flags; // {ena, lock, r, w, x}
// $D Snoop interface:
sc_in<bool> i_req_snoop_valid;
sc_in<sc_uint<SNOOP_REQ_TYPE_BITS>> i_req_snoop_type;
sc_out<bool> o_req_snoop_ready;
sc_in<sc_uint<CFG_CPU_ADDR_BITS>> i_req_snoop_addr;
sc_in<bool> i_resp_snoop_ready;
sc_out<bool> o_resp_snoop_valid;
sc_out<sc_biguint<L1CACHE_LINE_BITS>> o_resp_snoop_data;
sc_out<sc_uint<DTAG_FL_TOTAL>> o_resp_snoop_flags;
// Debug signals:
sc_in<bool> i_flushi_valid; // address to clear icache is valid
sc_in<sc_uint<RISCV_ARCH>> i_flushi_addr; // clear ICache address from debug interface
sc_in<bool> i_flushd_valid;
sc_in<sc_uint<RISCV_ARCH>> i_flushd_addr;
sc_out<bool> o_flushd_end;
void comb();
SC_HAS_PROCESS(CacheTop);
CacheTop(sc_module_name name,
bool async_reset,
bool coherence_ena);
virtual ~CacheTop();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
bool coherence_ena_;
static const int DATA_PATH = 0;
static const int CTRL_PATH = 1;
static const int QUEUE_WIDTH = (CFG_CPU_ADDR_BITS // o_req_mem_addr
+ REQ_MEM_TYPE_BITS // o_req_mem_type
+ 3 // o_req_mem_size
+ 1 // i_resp_mem_path
);
struct CacheOutputType {
sc_signal<bool> req_mem_valid;
sc_signal<sc_uint<REQ_MEM_TYPE_BITS>> req_mem_type;
sc_signal<sc_uint<3>> req_mem_size;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> req_mem_addr;
sc_signal<sc_uint<L1CACHE_BYTES_PER_LINE>> req_mem_strob;
sc_signal<sc_biguint<L1CACHE_LINE_BITS>> req_mem_wdata;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> mpu_addr;
sc_signal<sc_uint<CFG_CPU_ADDR_BITS>> resp_addr;
|
InstrExecute |
sc_in<bool> i_clk;
sc_in<bool> i_nrst; // Reset active LOW
sc_in<bool> i_pipeline_hold; // Hold execution by any reason
sc_in<bool> i_d_valid; // Decoded instruction is valid
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_d_pc; // Instruction pointer on decoded instruction
sc_in<sc_uint<32>> i_d_instr; // Decoded instruction value
sc_in<bool> i_wb_done; // write back done (Used to clear hazardness)
sc_in<bool> i_memop_store; // Store to memory operation
sc_in<bool> i_memop_load; // Load from memoru operation
sc_in<bool> i_memop_sign_ext; // Load memory value with sign extending
sc_in<sc_uint<2>> i_memop_size; // Memory transaction size
sc_in<bool> i_unsigned_op; // Unsigned operands
sc_in<bool> i_rv32; // 32-bits instruction
sc_in<bool> i_compressed; // C-extension (2-bytes length)
sc_in<sc_bv<ISA_Total>> i_isa_type; // Type of the instruction's structure (ISA spec.)
sc_in<sc_bv<Instr_Total>> i_ivec; // One pulse per supported instruction.
sc_in<bool> i_unsup_exception; // Unsupported instruction exception
sc_in<bool> i_dport_npc_write; // Write npc value from debug port
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_dport_npc; // Debug port npc value to write
sc_out<sc_uint<5>> o_radr1; // Integer register index 1
sc_in<sc_uint<RISCV_ARCH>> i_rdata1; // Integer register value 1
sc_out<sc_uint<5>> o_radr2; // Integer register index 2
sc_in<sc_uint<RISCV_ARCH>> i_rdata2; // Integer register value 2
sc_out<sc_uint<5>> o_res_addr; // Address to store result of the instruction (0=do not store)
sc_out<sc_uint<RISCV_ARCH>> o_res_data; // Value to store
sc_out<bool> o_pipeline_hold; // Hold pipeline while 'writeback' not done or multi-clock instruction.
sc_out<sc_uint<12>> o_csr_addr; // CSR address. 0 if not a CSR instruction with xret signals mode switching
sc_out<bool> o_csr_wena; // Write new CSR value
sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // CSR current value
sc_out<sc_uint<RISCV_ARCH>> o_csr_wdata; // CSR new value
sc_in<bool> i_trap_valid; // async trap event
sc_in<sc_uint<BUS_ADDR_WIDTH>> i_trap_pc; // jump to address
// exceptions:
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_ex_npc; // npc on before trap
sc_out<bool> o_ex_illegal_instr;
sc_out<bool> o_ex_unalign_store;
sc_out<bool> o_ex_unalign_load;
sc_out<bool> o_ex_breakpoint;
sc_out<bool> o_ex_ecall;
sc_out<bool> o_memop_sign_ext; // Load data with sign extending
sc_out<bool> o_memop_load; // Load data instruction
sc_out<bool> o_memop_store; // Store data instruction
sc_out<sc_uint<2>> o_memop_size; // 0=1bytes; 1=2bytes; 2=4bytes; 3=8bytes
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_memop_addr;// Memory access address
sc_out<bool> o_pre_valid; // pre-latch of valid
sc_out<bool> o_valid; // Output is valid
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_pc; // Valid instruction pointer
sc_out<sc_uint<BUS_ADDR_WIDTH>> o_npc; // Next instruction pointer. Next decoded pc must match to this value or will be ignored.
sc_out<sc_uint<32>> o_instr; // Valid instruction value
sc_out<bool> o_call; // CALL pseudo instruction detected
sc_out<bool> o_ret; // RET pseudoinstruction detected
sc_out<bool> o_mret; // MRET.
sc_out<bool> o_uret; // MRET.
void comb();
void registers();
SC_HAS_PROCESS(InstrExecute);
InstrExecute(sc_module_name name_);
virtual ~InstrExecute();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
enum EMultiCycleInstruction {
Multi_MUL,
Multi_DIV,
Multi_Total
|
TagMem |
public:
sc_in<bool> i_clk; // CPU clock
sc_in<bool> i_nrst; // Reset: active LOW
sc_in<sc_uint<abus>> i_addr;
sc_in<sc_uint<(1 << lnbits)>> i_wstrb;
sc_in<sc_biguint<(8 * (1 << lnbits))>> i_wdata;
sc_in<sc_uint<flbits>> i_wflags;
sc_out<sc_uint<abus>> o_raddr;
sc_out<sc_biguint<(8 * (1 << lnbits))>> o_rdata;
sc_out<sc_uint<flbits>> o_rflags;
sc_out<bool> o_hit;
// L2 snoop port, active when snoop = 1
sc_in<sc_uint<abus>> i_snoop_addr;
sc_out<sc_uint<flbits>> o_snoop_flags;
void comb();
void registers();
SC_HAS_PROCESS(TagMem);
TagMem(sc_module_name name,
bool async_reset);
virtual ~TagMem();
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
bool async_reset_;
static const int TAG_BITS = ((abus - ibits) - lnbits);
static const int TAG_WITH_FLAGS = (TAG_BITS + flbits);
struct TagMem_registers {
sc_signal<sc_uint<TAG_BITS>> tagaddr;
sc_signal<sc_uint<ibits>> index;
sc_signal<sc_uint<TAG_BITS>> snoop_tagaddr;
} v, r;
void TagMem_r_reset(TagMem_registers &iv) {
iv.tagaddr = 0;
iv.index = 0;
iv.snoop_tagaddr = 0;
}
sc_signal<sc_uint<ibits>> wb_index;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_rdata;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tagi_wdata;
sc_signal<bool> w_tagi_we;
sc_signal<sc_uint<ibits>> wb_snoop_index;
sc_signal<sc_uint<TAG_BITS>> wb_snoop_tagaddr;
sc_signal<sc_uint<TAG_WITH_FLAGS>> wb_tago_snoop_rdata;
ram_cache_bwe_tech<ibits, (8 * (1 << lnbits))> *data0;
ram_tech<ibits, TAG_WITH_FLAGS> *tag0;
ram_tech<ibits, TAG_WITH_FLAGS> *tagsnoop0;
|
ex20_parameter_owner |
public:
/**
* @fn ex20_parameter_owner()
* @brief The class constructor
* @return void
*/
SC_CTOR(ex20_parameter_owner) {
XREPORT("Prior to " << sc_time_stamp());
XREPORT("[OWNER C_TOR] : Creating new integer type cci-parameter with"
" default value 10");
int_param = new cci::cci_param<int>("int_param", 10);
SC_THREAD(run_owner);
}
/**
* @fn void run_owner(void)
* @brief Implementation of SC_THREAD. Sets new value to the int type cci-parameter
* and sets a default value to the float type cci-parameter
* @return void
*/
void run_owner(void) {
while (1) {
XREPORT("@ " << sc_time_stamp());
XREPORT("[OWNER] : Setting new value to the 'int' type param to '15'");
*int_param = 15;
wait(5.0, SC_NS);
XREPORT("@ " << sc_time_stamp());
XREPORT("[OWNER] : Creating new 'double' type cci-parameter with default"
" value : 12.345");
dbl_param = new cci::cci_param<double>("double_param", 12.345);
wait(15.0, SC_NS);
}
}
private:
// Integer-type cci-parameter
cci::cci_param<int>* int_param; ///< An integer cci parameter
// Float-type cci-parameter
cci::cci_param<double>* dbl_param; ///< A double cci parameter
|
SC_FIFO_IN_TRANS |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<W> > data_sink;
sc_signal<sc_logic> data_sink_empty_n;
sc_signal<sc_logic> data_sink_read;
sc_signal<sc_lv<W> > data_sink_0_dout;
sc_signal<sc_lv<1> > data_sink_1_dout;
sc_signal<sc_lv<W / 8> > data_sink_2_dout;
sc_signal<sc_logic> data_sink_1_read, data_sink_2_read;
#define SC_FIFO_IN_TRANS_CONNECT(inst, thisinst, port) \
SC_MODULE_LINK(thisinst); \
thisinst.data_sink(port); \
inst.port##_0_dout(thisinst.data_sink_0_dout); \
inst.port##_0_empty_n(thisinst.data_sink_empty_n); \
inst.port##_0_read(thisinst.data_sink_read); \
inst.port##_1_dout(thisinst.data_sink_1_dout); \
inst.port##_1_empty_n(thisinst.data_sink_empty_n); \
inst.port##_2_dout(thisinst.data_sink_2_dout); \
inst.port##_2_empty_n(thisinst.data_sink_empty_n); \
inst.port##_1_read(thisinst.data_sink_1_read); \
inst.port##_2_read(thisinst.data_sink_2_read);
SC_CTOR(SC_FIFO_IN_TRANS) {
SC_CTHREAD(TRANS_thread, clk);
reset_signal_is(reset, true);
}
void TRANS_thread() {
data_sink_empty_n.write(SC_LOGIC_0);
data_sink_0_dout.write(0);
data_sink_1_dout.write(0);
data_sink_2_dout.write(0);
while (true) {
// wait();
data_sink_empty_n.write(SC_LOGIC_0);
data_sink_0_dout.write(0);
data_sink_1_dout.write(0);
data_sink_2_dout.write(0);
hwcore::pipes::sc_data_stream_t<W> tmp = data_sink.read();
data_sink_0_dout.write(tmp.data);
data_sink_1_dout.write(tmp.tlast);
data_sink_2_dout.write(tmp.tkeep);
data_sink_empty_n.write(SC_LOGIC_1);
wait();
while (data_sink_read.read() == SC_LOGIC_0) {
wait();
}
}
}
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