module_name
stringlengths 1
2.17k
| module_content
stringlengths 6
11.3k
|
|---|---|
SC_FIFO_OUT_TRANS |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<W> > data_source;
sc_signal<sc_logic> data_source_full_n;
sc_signal<sc_logic> data_source_write;
sc_signal<sc_lv<W> > data_source_0_din;
sc_signal<sc_lv<1> > data_source_1_din;
sc_signal<sc_lv<W / 8> > data_source_2_din;
sc_signal<sc_logic> data_source_1_write;
sc_signal<sc_logic> data_source_2_write;
#define SC_FIFO_OUT_TRANS_CONNECT(inst, thisinst, port) \
SC_MODULE_LINK(thisinst); \
thisinst.data_source(port); \
inst.port##_0_full_n(thisinst.data_source_full_n); \
inst.port##_1_full_n(thisinst.data_source_full_n); \
inst.port##_2_full_n(thisinst.data_source_full_n); \
inst.port##_0_write(thisinst.data_source_write); \
inst.port##_0_din(thisinst.data_source_0_din); \
inst.port##_1_din(thisinst.data_source_1_din); \
inst.port##_2_din(thisinst.data_source_2_din); \
inst.port##_1_write(thisinst.data_source_1_write); \
inst.port##_2_write(thisinst.data_source_2_write);
SC_CTOR(SC_FIFO_OUT_TRANS) {
SC_CTHREAD(TRANS_THREAD, clk.pos());
reset_signal_is(reset, true);
}
void TRANS_THREAD() {
data_source_full_n.write(SC_LOGIC_0);
bool full_n = false;
while (true) {
wait();
full_n = !(data_source.num_free() == 0);
if (full_n) {
data_source_full_n.write(SC_LOGIC_1);
if (data_source_write.read() == SC_LOGIC_1) {
hwcore::pipes::sc_data_stream_t<W> tmp;
tmp.data = data_source_0_din.read();
tmp.tlast = data_source_1_din.read();
tmp.tkeep = data_source_2_din.read();
if (data_source.nb_write(tmp)) {
/*full_n = !(data_source.num_free()==0);
data_source_full_n.write(SC_LOGIC_1);*/
}
}
} else {
data_source_full_n.write(SC_LOGIC_0);
}
}
}
|
dut_type_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
sc_signal< input_t > din_data;
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
void thread_din_data();
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
|
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99} |
sc_TOP_SPW |
sc_clock CLOCK;
sc_signal<bool> RESET;
sc_signal<bool> LINK_START;
sc_signal<bool> LINK_DISABLE;
sc_signal<bool> AUTO_START;
sc_signal<sc_uint<4> > FSM_SPW_OUT;
sc_signal<sc_uint<4> > FSM_TX;
sc_signal<sc_uint<10> > CLOCK_GEN;
sc_signal<bool> E_SEND_DATA;
sc_signal<bool> BUFFER_READY;
sc_signal<sc_uint<9> > DATARX_FLAG;
sc_signal<bool> BUFFER_WRITE;
sc_signal<sc_uint<8> > TIME_OUT;
sc_signal<bool> TICK_OUT;
sc_signal<bool> CONTROL_FLAG_OUT;
sc_signal<uint> DOUT;
sc_signal<uint> SOUT;
sc_signal<uint> DIN;
sc_signal<uint> SIN;
sc_TOP DUT;
SC_CTOR(sc_TOP_SPW) :CLOCK("CLOCK",20,SC_NS),
RESET("RESET"),
LINK_DISABLE("LINK_DISABLE"),
LINK_START("LINK_START"),
AUTO_START("AUTO_START"),
FSM_SPW_OUT("FSM_SPW_OUT"),
CLOCK_GEN("CLOCK_GEN"),
E_SEND_DATA("E_SEND_DATA"),
DOUT("DOUT"),
SOUT("SOUT"),
FSM_TX("FSM_TX"),
DIN("DIN"),
SIN("SIN"),
BUFFER_READY("BUFFER_READY"),
DATARX_FLAG("DATARX_FLAG"),
BUFFER_WRITE("BUFFER_WRITE"),
TIME_OUT("TIME_OUT"),
TICK_OUT("TICK_OUT"),
CONTROL_FLAG_OUT("CONTROL_FLAG_OUT"),
DUT("DUT") {
DUT.CLOCK(CLOCK);
DUT.RESET(RESET);
DUT.LINK_DISABLE(LINK_DISABLE);
DUT.AUTO_START(AUTO_START);
DUT.LINK_START(LINK_START);
DUT.FSM_SPW_OUT(FSM_SPW_OUT);
DUT.CLOCK_GEN(CLOCK_GEN);
DUT.E_SEND_DATA(E_SEND_DATA);
DUT.FSM_TX(FSM_TX);
DUT.DOUT(DOUT);
DUT.SOUT(SOUT);
DUT.DIN(DIN);
DUT.SIN(SIN);
DUT.BUFFER_READY(BUFFER_READY);
DUT.DATARX_FLAG(DATARX_FLAG);
DUT.BUFFER_WRITE(BUFFER_WRITE);
DUT.TIME_OUT(TIME_OUT);
DUT.TICK_OUT(TICK_OUT);
DUT.CONTROL_FLAG_OUT(CONTROL_FLAG_OUT);
cout << "SC_CTOR(sc_TOP_SPW)" << endl;
}
|
BitsToBytes |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<1> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(BitsToBytes)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
#if 1
while ( true )
{
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
uint8_t E = e.read();
v = (v << 1) | E;
}
s.write( v );
}
#else
while ( true )
{
uint8_t bits[8];
for( uint32_t q = 0; q < 8 ; q += 1 )
bits[q] = e.read();
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
v = (v << 1) | bits[q];
}
for( uint32_t q = 0; q < 8 ; q += 1 )
printf("%d", bits[q]);
printf(" = 0x%2.2X\n", v);
s.write( v );
}
#endif
}
|
DummyCpu |
public:
sc_out<axi4_l1_out_type> o_msto;
sc_out<dport_out_type> o_dport;
sc_out<bool> o_flush_l2; // Flush L2 after D$ has been finished
sc_out<bool> o_halted; // CPU halted via debug interface
sc_out<bool> o_available; // CPU was instantitated of stubbed
void comb();
SC_HAS_PROCESS(DummyCpu);
DummyCpu(sc_module_name name);
void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
private:
|
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
reset.write(false);
for (int i = 0; i < 20; i++)
wait();
int counter = 1;
int last_count = 1;
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
sc_fixed<DATA_W, DATA_P> Y_golden[16 * 16];
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16; b++) {
sc_fixed<DATA_W, DATA_P> tmp = 0;
for (int wi = 0; wi < 16; wi++) {
tmp += Win[wi + (b * 16)] * Xin[(a * 16) + wi];
}
Y_golden[(a * 16) + b] = tmp;
}
}
sc_fixed<DATA_W, DATA_P> Y[16 * 16];
hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> tmp;
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16 / OUTPUT_BW_N; b++) {
tmp = data_in.read();
sc_fixed<DATA_W, DATA_P> data_in[OUTPUT_BW_N];
tmp.getDataFixed<DATA_W, DATA_P, OUTPUT_BW_N>(data_in);
for (int i = 0; i < OUTPUT_BW_N; i++) {
Y[(a * 16) + (b * OUTPUT_BW_N) + i] = data_in[i];
HLS_DEBUG(1, 1, 0, "got knew value: ")
std::cout << " |--> " << data_in[i].to_float() << " index nr: " << counter << " tlast? "
<< tmp.tlast.to_int() << std::endl
<< std::flush;
counter++;
}
}
}
bool ok = true;
if (tmp.tlast.to_int() != 1) {
ok = false;
std::cout << "error - missing tlast!!!" << std::endl << std::flush;
}
for (int i = 0; i < 16 * 16; i++) {
std::cout << "[ " << i << " ] Y = " << Y[i].to_float() << std::endl
<< std::flush; // " == Y_golden = " << Y_golden[i].to_float() << std::endl << std::flush;
/* if(Y[i]!=Y_golden[i])
{
std::cout << "error not equal!!!" << std::endl << std::flush;
ok = false;
}*/
}
HLS_DEBUG(1, 1, 0, "Simulation done");
if (!ok) {
HLS_DEBUG(1, 1, 0, "Simulation done - with errors!!!");
}
sc_stop();
}
|
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl_depth;
sc_out<sc_uint<16 + 1> > ctrl_stride;
sc_out<sc_uint<16 + 1> > ctrl_replay;
sc_out<sc_uint<1 + 1> > ctrl_channel;
sc_out<sc_uint<16 + 1> > ctrl_row_N;
sc_in<sc_uint<1> > ready;
template <class interface, typename T> void do_cmd(interface & itf, T value) {
while (ready.read() == 0) {
wait();
}
itf.write((value << 1) | 0b01);
while (ready.read() == 1) {
wait();
}
while (ready.read() == 0) {
wait();
}
itf.write(0);
wait();
}
SC_CTOR_DEFAULT(wave_CNN) {
SC_CTHREAD(wave_thread, clk.pos());
SC_CTHREAD(sending_ctrls, clk.pos());
}
void sending_ctrls() {
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 20; i++)
wait();
ctrl_channel.write(0);
ctrl_row_N.write(0);
weight_ctrl.write(0);
// data_ctrl.write(0);
do_cmd(ctrl_channel, 0);
do_cmd(ctrl_row_N, 16 / INPUT_BW_N);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
do_cmd(ctrl_depth, 1);
do_cmd(ctrl_replay, 1);
do_cmd(ctrl_stride, 0);
do_cmd(ctrl_row_size_pkg, 1024);
do_cmd(ctrl_window_size, 1);
for (int a = 0; a < 16; a++) {
do_cmd(ctrl_channel, 1);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
// do_cmd(data_ctrl,hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
}
while (true) {
wait();
}
}
void wave_thread() {
// sending dummy weights.
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 15; i++)
wait();
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
HLS_DEBUG(1, 1, 0, "sending data -- weights!----------------------");
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int a = 0; a < (16 * 16) / INPUT_BW_N; a++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Win[a * INPUT_BW_N]);
tmp.setKeep();
if (a == ((16 * 16) / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
// sending input data
HLS_DEBUG(1, 1, 0, "sending data -- Input!----------------------");
for (int a = 0; a < 16; a++) {
for (int i = 0; i < 16 / INPUT_BW_N; i++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Xin[(i * INPUT_BW_N) + (a * 16)]);
tmp.setKeep();
if (a == (16) - 1 && i == (16 / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending Input data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending Input data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
}
/*HLS_DEBUG(1,1,0,"sending data -- Firing!----------------------");
data_ctrl.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);*/
while (true) {
wait();
}
}
|
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_signal<sc_uint<16 + 1> > ctrl_window_size;
sc_signal<sc_uint<16 + 1> > ctrl_depth;
sc_signal<sc_uint<16 + 1> > ctrl_stride;
sc_signal<sc_uint<16 + 1> > ctrl_replay;
sc_signal<sc_uint<1 + 1> > ctrl_channel;
sc_signal<sc_uint<16 + 1> > ctrl_row_N;
sc_signal<sc_uint<1> > ready;
// sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
::cnn cnn_u1;
// hwcore::cnn::top_cnn<16,8,1,1,16,16> cnn_u1;
sc_fifo<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > u1_2_mon;
mon_CNN mon;
sc_trace_file *tracePtr;
SC_CTOR_DEFAULT(tb_CNN) : SC_INST(wave), SC_INST(cnn_u1), SC_INST(mon), clk("clk", sc_time(10, SC_NS)) {
SC_MODULE_LINK(wave);
SC_MODULE_LINK(mon);
SC_MODULE_LINK(cnn_u1);
wave.ctrl_row_size_pkg(ctrl_row_size_pkg);
wave.ctrl_window_size(ctrl_window_size);
wave.ctrl_depth(ctrl_depth);
wave.ctrl_stride(ctrl_stride);
wave.ctrl_replay(ctrl_replay);
wave.ready(ready);
wave.data_out(wave_2_u1);
// wave.data_ctrl(data_ctrl);
wave.weight_ctrl(weight_ctrl);
wave.ctrl_row_N(ctrl_row_N);
wave.ctrl_channel(ctrl_channel);
cnn_u1.ready(ready);
cnn_u1.ctrl_row_size_pkg(ctrl_row_size_pkg);
cnn_u1.ctrl_window_size(ctrl_window_size);
cnn_u1.ctrl_depth(ctrl_depth);
cnn_u1.ctrl_stride(ctrl_stride);
cnn_u1.ctrl_replay(ctrl_replay);
cnn_u1.ctrl_row_N(ctrl_row_N);
cnn_u1.weight_ctrls(weight_ctrl);
// cnn_u1.data_ctrls(data_ctrl);
cnn_u1.ctrl_channel(ctrl_channel);
cnn_u1.data_sink(wave_2_u1);
cnn_u1.data_source(u1_2_mon);
mon.data_in(u1_2_mon);
tracePtr = sc_create_vcd_trace_file("tb_CNN");
trace(tracePtr);
}
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
SC_TRACE_ADD_MODULE(wave_2_u1);
SC_TRACE_ADD_MODULE(data_ctrl);
SC_TRACE_ADD_MODULE(weight_ctrl);
SC_TRACE_ADD_MODULE(ctrl_row_N);
SC_TRACE_ADD_MODULE(ctrl_channel);
SC_TRACE_ADD_MODULE(cnn_u1);
SC_TRACE_ADD_MODULE(u1_2_mon);
}
virtual ~tb_CNN() { sc_close_vcd_trace_file(tracePtr); }
|
cu_monitor |
#if MIXED_SIM
sc_in<sc_logic> clk;
sc_in<sc_logic> rst;
sc_in<sc_logic> RD; // DRAM read command
sc_in<sc_logic> WR; // DRAM write command
sc_in<sc_logic> ACT; // DRAM activate command
// sc_in<sc_logic> RSTB; //
sc_in<sc_logic> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<sc_logic> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_lv<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_lv<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_lv<COL_BITS> > col_addr; // Address of the bank column
sc_in<sc_lv<64> > DQ; // Data input from DRAM controller (output makes no sense
sc_in<sc_lv<32> > instr; // Instruction input from CRF
sc_in<sc_lv<32> > pc_out; // PC to the CRF
sc_in<sc_lv<GRF_WIDTH> > data_out; // Data to the RFs
// CRF Control
sc_in<sc_logic> crf_wr_en; //Enables writing of a received instruction
sc_in<sc_lv<32> > crf_wr_addr; //Index for writing the received instructions from processor
// SRF Control
sc_in<sc_lv<32> > srf_rd_addr; // Index read
sc_in<sc_logic> srf_rd_a_nm; // Signals if reading from SRF_A (high) or SRF_M (low)
sc_in<sc_logic> srf_wr_en; // Enable writing
sc_in<sc_lv<32> > srf_wr_addr; // Index the address to be written
sc_in<sc_logic> srf_wr_a_nm; // Signals if writing to SRF_A (high) or SRF_M (low)
sc_in<sc_lv<8> > srf_wr_from; // Index the MUX for input data
// GRF_A Control
sc_in<sc_lv<32> > grfa_rd_addr1; // Index read at port 1
sc_in<sc_lv<32> > grfa_rd_addr2; // Index read at port 2
sc_in<sc_logic> grfa_wr_en; // Enables writing
sc_in<sc_logic> grfa_relu_en; // Enable ReLU for the MOV instruction
sc_in<sc_lv<32> > grfa_wr_addr; // Index the address to be written
sc_in<sc_lv<8> > grfa_wr_from; // Index the MUX for input data
// GRF_B Control
sc_in<sc_lv<32> > grfb_rd_addr1; // Index read at port 1
sc_in<sc_lv<32> > grfb_rd_addr2; // Index read at port 2
sc_in<sc_logic> grfb_wr_en; // Enables writing
sc_in<sc_logic> grfb_relu_en; // Enable ReLU for the MOV instruction
sc_in<sc_lv<32> > grfb_wr_addr; // Index the address to be written
sc_in<sc_lv<8> > grfb_wr_from; // Index the MUX for input data
// FPU Control
sc_in<sc_logic> fpu_mult_en; // Signals that a multiplication computation step should be performed
sc_in<sc_logic> fpu_add_en; // Signals that an addition computation step should be performed
sc_in<sc_lv<8> > fpu_mult_in1_sel; // Selects input 1 for multiplication
sc_in<sc_lv<8> > fpu_mult_in2_sel; // Selects input 2 for multiplication
sc_in<sc_lv<8> > fpu_add_in1_sel; // Selects input 1 for addition
sc_in<sc_lv<8> > fpu_add_in2_sel; // Selects input 2 for addition
sc_in<sc_logic> fpu_out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#else
sc_in_clk clk;
sc_in<bool> rst;
sc_in<bool> RD; // DRAM read command
sc_in<bool> WR; // DRAM write command
sc_in<bool> ACT; // DRAM activate command
// sc_in<bool> RSTB; //
sc_in<bool> AB_mode; // Signals if the All-Banks mode is enabled
sc_in<bool> pim_mode; // Signals if the PIM mode is enabled
sc_in<sc_uint<BANK_BITS> > bank_addr; // Address of the bank
sc_in<sc_uint<ROW_BITS> > row_addr; // Address of the bank row
sc_in<sc_uint<COL_BITS> > col_addr; // Address of the bank column
sc_in<uint64_t> DQ; // Data input from DRAM controller (output makes no sense
sc_in<uint32_t> instr; // Instruction input from CRF
sc_in<uint> pc_out; // PC to the CRF
sc_in<sc_biguint<GRF_WIDTH> > data_out; // Data to the RFs
// CRF Control
sc_in<bool> crf_wr_en; // Enables writing of a received instruction
sc_in<uint> crf_wr_addr; // Index for writing the received instructions from processor
// SRF Control
sc_in<uint> srf_rd_addr; // Index read
sc_in<bool> srf_rd_a_nm; // Signals if reading from SRF_A (high) or SRF_M (low)
sc_in<bool> srf_wr_en; // Enable writing
sc_in<uint> srf_wr_addr; // Index the address to be written
sc_in<bool> srf_wr_a_nm; // Signals if writing to SRF_A (high) or SRF_M (low)
sc_in<uint8_t> srf_wr_from; // Index the MUX for input data
// GRF_A Control
sc_in<uint> grfa_rd_addr1; // Index read at port 1
sc_in<uint> grfa_rd_addr2; // Index read at port 2
sc_in<bool> grfa_wr_en; // Enables writing
sc_in<bool> grfa_relu_en; // Enable ReLU for the MOV instruction
sc_in<uint> grfa_wr_addr; // Index the address to be written
sc_in<uint8_t> grfa_wr_from; // Index the MUX for input data
// GRF_B Control
sc_in<uint> grfb_rd_addr1; // Index read at port 1
sc_in<uint> grfb_rd_addr2; // Index read at port 2
sc_in<bool> grfb_wr_en; // Enables writing
sc_in<bool> grfb_relu_en; // Enable ReLU for the MOV instruction
sc_in<uint> grfb_wr_addr; // Index the address to be written
sc_in<uint8_t> grfb_wr_from; // Index the MUX for input data
// FPU Control
sc_in<bool> fpu_mult_en; // Signals that a multiplication computation step should be performed
sc_in<bool> fpu_add_en; // Signals that an addition computation step should be performed
sc_in<uint8_t> fpu_mult_in1_sel; // Selects input 1 for multiplication
sc_in<uint8_t> fpu_mult_in2_sel; // Selects input 2 for multiplication
sc_in<uint8_t> fpu_add_in1_sel; // Selects input 1 for addition
sc_in<uint8_t> fpu_add_in2_sel; // Selects input 2 for addition
sc_in<bool> fpu_out_sel; // Selects the output: 0 for adder output, 1 for multiplier output
#endif
// Internal events
// Internal variables and signals for checking
SC_CTOR(cu_monitor) {
SC_THREAD(monitor_thread);
sensitive << clk.pos() << rst.neg();
}
void monitor_thread(); // Outputs the behavior for the first SIMD rail, and automatically checks the functionality
// void mirror_thread(); // Mirror FPU behavior for checking its functionality
// void out_mirror_thread(); // Mirror FPU output for checking functionality
|
dut_type_wrapper |
public:
sc_in< bool > clk;
sc_in< bool > rst;
sc_out< bool > din_busy;
sc_in< bool > din_vld;
sc_in< sc_uint< 8 > > din_data_a;
sc_in< sc_uint< 8 > > din_data_b;
sc_in< sc_uint< 8 > > din_data_c;
sc_in< sc_uint< 8 > > din_data_d;
sc_in< sc_uint< 8 > > din_data_e;
sc_in< sc_uint< 8 > > din_data_f;
sc_in< sc_uint< 8 > > din_data_g;
sc_in< sc_uint< 8 > > din_data_h;
sc_in< bool > dout_busy;
sc_out< bool > dout_vld;
sc_out< sc_uint< 32 > > dout_data;
// These signals are used to connect structured ports or ports that need
// type conversion to the RTL ports.
sc_signal< input_t > din_data;
// create the netlist
void InitInstances();
void InitThreads();
// delete the netlist
void DeleteInstances();
// The following threads are used to connect structured ports to the actual
// RTL ports.
void thread_din_data();
SC_HAS_PROCESS(dut_type_wrapper);
dut_type_wrapper( sc_module_name name = sc_module_name( sc_gen_unique_name("dut")) )
: sc_module(name)
,clk("clk")
,rst("rst")
,din_busy("din_busy")
,din_vld("din_vld")
,din_data_a("din_data_a"),
din_data_b("din_data_b"),
din_data_c("din_data_c"),
din_data_d("din_data_d"),
din_data_e("din_data_e"),
din_data_f("din_data_f"),
din_data_g("din_data_g"),
din_data_h("din_data_h")
,dout_busy("dout_busy")
,dout_vld("dout_vld")
,dout_data("dout_data")
,dut0(0)
{
InitInstances();
InitThreads();
end_module();
}
// destructor
~dut_type_wrapper()
{
DeleteInstances();
}
protected:
dut* dut0;
|
cpu_sim |
sc_fifo_out<pipes::sc_data_stream_t<16*32> > dma_out;
sc_fifo_in<pipes::sc_data_stream_t<16*32> > dma_in;
//sc_out<uint32_t>
|
tb_cnn_top |
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > cpu_sim_2_u1_dma;
cnn::top_cnn<> cnn_u1;
hf::sc_fifo_template<pipes::sc_data_stream_t<16*32> > u1_2_cpu_sim_dma;
|
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
reset.write(false);
for (int i = 0; i < 20; i++)
wait();
int counter = 1;
int last_count = 1;
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
sc_fixed<DATA_W, DATA_P> Y_golden[16 * 16];
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16; b++) {
sc_fixed<DATA_W, DATA_P> tmp = 0;
for (int wi = 0; wi < 16; wi++) {
tmp += Win[wi + (b * 16)] * Xin[(a * 16) + wi];
}
Y_golden[(a * 16) + b] = tmp;
}
}
sc_fixed<DATA_W, DATA_P> Y[16 * 16];
hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> tmp;
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16 / OUTPUT_BW_N; b++) {
tmp = data_in.read();
sc_fixed<DATA_W, DATA_P> data_in[OUTPUT_BW_N];
tmp.getDataFixed<DATA_W, DATA_P, OUTPUT_BW_N>(data_in);
for (int i = 0; i < OUTPUT_BW_N; i++) {
Y[(a * 16) + (b * OUTPUT_BW_N) + i] = data_in[i];
HLS_DEBUG(1, 1, 0, "got knew value: ")
std::cout << " |--> " << data_in[i].to_float() << " index nr: " << counter << " tlast? "
<< tmp.tlast.to_int() << std::endl
<< std::flush;
counter++;
}
}
}
bool ok = true;
if (tmp.tlast.to_int() != 1) {
ok = false;
std::cout << "error - missing tlast!!!" << std::endl << std::flush;
}
for (int i = 0; i < 16 * 16; i++) {
std::cout << "[ " << i << " ] Y = " << Y[i].to_float() << std::endl
<< std::flush; // " == Y_golden = " << Y_golden[i].to_float() << std::endl << std::flush;
/* if(Y[i]!=Y_golden[i])
{
std::cout << "error not equal!!!" << std::endl << std::flush;
ok = false;
}*/
}
HLS_DEBUG(1, 1, 0, "Simulation done");
if (!ok) {
HLS_DEBUG(1, 1, 0, "Simulation done - with errors!!!");
}
sc_stop();
}
|
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl_depth;
sc_out<sc_uint<16 + 1> > ctrl_stride;
sc_out<sc_uint<16 + 1> > ctrl_replay;
sc_out<sc_uint<1 + 1> > ctrl_channel;
sc_out<sc_uint<16 + 1> > ctrl_row_N;
sc_in<sc_uint<1> > ready;
template <class interface, typename T> void do_cmd(interface & itf, T value) {
while (ready.read() == 0) {
wait();
}
itf.write((value << 1) | 0b01);
while (ready.read() == 1) {
wait();
}
while (ready.read() == 0) {
wait();
}
itf.write(0);
wait();
}
SC_CTOR_DEFAULT(wave_CNN) {
SC_CTHREAD(wave_thread, clk.pos());
SC_CTHREAD(sending_ctrls, clk.pos());
}
void sending_ctrls() {
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 20; i++)
wait();
ctrl_channel.write(0);
ctrl_row_N.write(0);
weight_ctrl.write(0);
// data_ctrl.write(0);
do_cmd(ctrl_channel, 0);
do_cmd(ctrl_row_N, 16 / INPUT_BW_N);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
do_cmd(ctrl_depth, 1);
do_cmd(ctrl_replay, 1);
do_cmd(ctrl_stride, 0);
do_cmd(ctrl_row_size_pkg, 1024);
do_cmd(ctrl_window_size, 1);
for (int a = 0; a < 16; a++) {
do_cmd(ctrl_channel, 1);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
// do_cmd(data_ctrl,hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
}
while (true) {
wait();
}
}
void wave_thread() {
// sending dummy weights.
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 15; i++)
wait();
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
HLS_DEBUG(1, 1, 0, "sending data -- weights!----------------------");
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int a = 0; a < (16 * 16) / INPUT_BW_N; a++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Win[a * INPUT_BW_N]);
tmp.setKeep();
if (a == ((16 * 16) / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
// sending input data
HLS_DEBUG(1, 1, 0, "sending data -- Input!----------------------");
for (int a = 0; a < 16; a++) {
for (int i = 0; i < 16 / INPUT_BW_N; i++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Xin[(i * INPUT_BW_N) + (a * 16)]);
tmp.setKeep();
if (a == (16) - 1 && i == (16 / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending Input data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending Input data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
}
/*HLS_DEBUG(1,1,0,"sending data -- Firing!----------------------");
data_ctrl.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);*/
while (true) {
wait();
}
}
|
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_signal<sc_uint<16 + 1> > ctrl_window_size;
sc_signal<sc_uint<16 + 1> > ctrl_depth;
sc_signal<sc_uint<16 + 1> > ctrl_stride;
sc_signal<sc_uint<16 + 1> > ctrl_replay;
sc_signal<sc_uint<1 + 1> > ctrl_channel;
sc_signal<sc_uint<16 + 1> > ctrl_row_N;
sc_signal<sc_uint<1> > ready;
// sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
::cnn cnn_u1;
// hwcore::cnn::top_cnn<16,8,1,1,16,16> cnn_u1;
sc_fifo<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > u1_2_mon;
mon_CNN mon;
sc_trace_file *tracePtr;
SC_CTOR_DEFAULT(tb_CNN) : SC_INST(wave), SC_INST(cnn_u1), SC_INST(mon), clk("clk", sc_time(10, SC_NS)) {
SC_MODULE_LINK(wave);
SC_MODULE_LINK(mon);
SC_MODULE_LINK(cnn_u1);
wave.ctrl_row_size_pkg(ctrl_row_size_pkg);
wave.ctrl_window_size(ctrl_window_size);
wave.ctrl_depth(ctrl_depth);
wave.ctrl_stride(ctrl_stride);
wave.ctrl_replay(ctrl_replay);
wave.ready(ready);
wave.data_out(wave_2_u1);
// wave.data_ctrl(data_ctrl);
wave.weight_ctrl(weight_ctrl);
wave.ctrl_row_N(ctrl_row_N);
wave.ctrl_channel(ctrl_channel);
cnn_u1.ready(ready);
cnn_u1.ctrl_row_size_pkg(ctrl_row_size_pkg);
cnn_u1.ctrl_window_size(ctrl_window_size);
cnn_u1.ctrl_depth(ctrl_depth);
cnn_u1.ctrl_stride(ctrl_stride);
cnn_u1.ctrl_replay(ctrl_replay);
cnn_u1.ctrl_row_N(ctrl_row_N);
cnn_u1.weight_ctrls(weight_ctrl);
// cnn_u1.data_ctrls(data_ctrl);
cnn_u1.ctrl_channel(ctrl_channel);
cnn_u1.data_sink(wave_2_u1);
cnn_u1.data_source(u1_2_mon);
mon.data_in(u1_2_mon);
tracePtr = sc_create_vcd_trace_file("tb_CNN");
trace(tracePtr);
}
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
SC_TRACE_ADD_MODULE(wave_2_u1);
SC_TRACE_ADD_MODULE(data_ctrl);
SC_TRACE_ADD_MODULE(weight_ctrl);
SC_TRACE_ADD_MODULE(ctrl_row_N);
SC_TRACE_ADD_MODULE(ctrl_channel);
SC_TRACE_ADD_MODULE(cnn_u1);
SC_TRACE_ADD_MODULE(u1_2_mon);
}
virtual ~tb_CNN() { sc_close_vcd_trace_file(tracePtr); }
|
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool > main_start;
// sc_signal < bool > main_end;
// Instruction counters
sc_signal < long int > icount;
sc_signal < long int > j_icount;
sc_signal < long int > b_icount;
sc_signal < long int > m_icount;
sc_signal < long int > o_icount;
// Cache modeled as arryas
sc_uint<XLEN> imem[ICACHE_SIZE];
sc_uint<XLEN> dmem[DCACHE_SIZE];
/* The testbench, DUT, IMEM and DMEM modules. */
tb *m_tb;
hl5_wrapper *m_dut;
SC_CTOR(TOP)
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
{
m_tb = new tb("tb", imem, dmem);
m_dut = new hl5_wrapper("dut", imem, dmem);
// Connect the design module
m_dut->clk(clk);
m_dut->rst(cpu_rst);
m_dut->entry_point(entry_point);
m_dut->program_end(program_end);
m_dut->fetch_en(fetch_en);
// m_dut->main_start(main_start);
// m_dut->main_end(main_end);
m_dut->icount(icount);
m_dut->j_icount(j_icount);
m_dut->b_icount(b_icount);
m_dut->m_icount(m_icount);
m_dut->o_icount(o_icount);
// Connect the testbench
m_tb->clk(clk);
m_tb->rst(rst);
m_tb->cpu_rst(cpu_rst);
m_tb->entry_point(entry_point);
m_tb->program_end(program_end);
m_tb->fetch_en(fetch_en);
// m_tb->main_start(main_start);
// m_tb->main_end(main_end);
m_tb->icount(icount);
m_tb->j_icount(j_icount);
m_tb->b_icount(b_icount);
m_tb->m_icount(m_icount);
m_tb->o_icount(o_icount);
}
~TOP()
{
delete m_tb;
delete m_dut;
delete imem;
delete dmem;
}
|
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_imm_s(sc_bv<12> imm); // Sign extend the S-type immediate field.
sc_bv<XLEN> zero_ext_zimm(sc_bv<ZIMM_SIZE> zimm); // Zero extend the zimm field for CSRRxI instructions.
sc_uint<CSR_IDX_LEN> get_csr_index(sc_bv<CSR_ADDR> csr_addr); // Get csr index given the 12-bit CSR address.
void set_csr_value(sc_uint<CSR_IDX_LEN> csr_index, sc_bv<XLEN> rs1, sc_uint<LOG2_CSR_OP_NUM> operation, sc_bv<2> rw_permission); // Perform requested CSR operation (write/set/clear).
// Divider functions
u_div_res_t udiv_func(sc_uint<XLEN> num, sc_uint<XLEN> den);
div_res_t div_func(sc_int<XLEN> num, sc_int<XLEN> den);
// Constructor
SC_CTOR(execute)
: din("din")
, dout("dout")
, fwd_exe("fwd_exe")
, clk("clk")
, rst("rst")
{
SC_CTHREAD(execute_th, clk.pos());
reset_signal_is(rst, false);
SC_CTHREAD(perf_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
HLS_FLATTEN_ARRAY(csr);
}
// Member variables
de_out_t input;
exe_out_t output;
sc_uint<XLEN> csr[CSR_NUM]; // Control and status registers.
|
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
// sc_in < bool > main_start;
// sc_in < bool > main_end;
// Instruction counters
sc_in < long int > icount;
sc_in < long int > j_icount;
sc_in < long int > b_icount;
sc_in < long int > m_icount;
sc_in < long int > o_icount;
sc_uint<XLEN> *imem;
sc_uint<XLEN> *dmem;
SC_HAS_PROCESS(tb);
tb(sc_module_name name, sc_uint<XLEN> imem[ICACHE_SIZE], sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, icount("icount")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, imem(imem)
, dmem(dmem)
{
SC_CTHREAD(source, clk.pos());
reset_signal_is(rst, 0);
SC_CTHREAD(sink, clk.pos());
reset_signal_is(rst, 0);
}
void source();
void sink();
double exec_start;
// double exec_main_start;
|
tb_pe |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W + 1 * W>::interface_T interface_W_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_out_T;
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
hwcore::cnn::PE<W, P, N> pe;
sc_fifo<interface_T> xin; // in
sc_fifo<interface_W_T> win;
sc_fifo<interface_out_T> dout; // out
sc_fifo<sc_uint<16> > ctrl_acf; // out
SC_CTOR(tb_pe) : clk("clock", sc_time(10, SC_NS)), pe("pe"), xin(1), dout(1), win(1), ctrl_acf(1) {
iclk(clk);
pe.clk(clk);
pe.reset(reset);
pe.Win(win);
pe.Xin(xin);
pe.dout(dout);
pe.ctrl_acf(ctrl_acf);
SC_CTHREAD(waveform, iclk.pos());
SC_CTHREAD(monitor, iclk.pos());
}
int func(int a, int b) {
int tmpSum = (a << 16) + (b << 16);
return tmpSum;
}
void waveform() {
debug_cout << " - [waveform start]" << std::endl;
interface_W_T Wtmp_out;
interface_T Xtmp_out;
interface_T tmp_out;
reset.write(1);
for (int i = 0; i < 5; i++)
wait();
reset.write(0);
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
ctrl_acf.write(0 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1));
for (int a = 0; a < size; a++) {
for (int b = 0; b < size; b++) {
Xtmp_out.data = func(a, b);
Xtmp_out.setKeep();
Xtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
Wtmp_out.data = ((2 << 16) << 32) | (0 << 16);
Wtmp_out.setKeep();
Wtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
debug_cout << "(waveform)[r]=[" << r << "],[a,b]=[" << a << "," << b << "][data]=[" << func(a, b)
<< "]" << std::endl;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
// dout.write(tmp_out);
debug_cout << "(waveform)[EOP]" << std::endl;
wait();
}
Xtmp_out.data = 2 << 29;
Xtmp_out.setKeep();
Wtmp_out.data = (4 << 16) << 32;
Wtmp_out.setKeep();
ctrl_acf.write(1 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1)); // use ReLU
for (int i = 0; i < 20; i++) {
Wtmp_out.tlast = (i == 20 - 1 ? 1 : 0);
Xtmp_out.tlast = Wtmp_out.tlast;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
debug_cout << " - [waveform done]" << std::endl;
while (true) {
wait();
}
}
void monitor() {
debug_cout << " - [waveform monitor]" << std::endl;
sc_int<W> tmp[2];
interface_out_T tmp_in;
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
dout.read(tmp_in);
tmp_in.template getData<sc_int, W, 1>(tmp);
debug_cout << "(monitor)[r]=[" << r << "],[data]=[" << tmp[0].to_int() << "]<=>[expected][" << (200 << 16)
<< "]" << std::endl;
sc_assert((200 << 16) == tmp[0].to_int());
dout.read(tmp_in);
sc_assert(tmp_in.EOP());
debug_cout << "(monitor)[r]=[" << r << "] looking for EOP" << std::endl;
}
dout.read(tmp_in);
sc_assert(!tmp_in.EOP());
for (int i = 0; i < W; i++) {
if (i == W - 1)
sc_assert(tmp_in.data[i] == 0);
else
sc_assert(tmp_in.data[i] == 1);
}
sc_stop();
while (true) {
wait();
}
}
void monitor_vec() {}
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_function;
// PROCESS
void process(void);
// UTIL
float sigmoid(float input);
float relu(float input);
float softmax(float input);
SC_CTOR(processing_engine_module)
{
state_length = 0;
state_activation_function = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset,true);
}
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
sc_in<IN* > img_window;
sc_out<OUT > result;
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter();
|
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99} |
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
|
SwitchStmHwModule |
// ports
sc_in<sc_uint<1>> a;
sc_in<sc_uint<1>> b;
sc_in<sc_uint<1>> c;
sc_out<sc_uint<1>> out;
sc_in<sc_uint<3>> sel;
// component instances
// internal signals
void assig_process_out() {
switch(sel.read()) {
case sc_uint<3>("0b000"): {
out.write(a.read());
break;
}
case sc_uint<3>("0b001"): {
out.write(b.read());
break;
}
case sc_uint<3>("0b010"): {
out.write(c.read());
break;
}
default:
out.write(sc_uint<1>("0b0"));
}
}
SC_CTOR(SwitchStmHwModule) {
SC_METHOD(assig_process_out);
sensitive << a << b << c << sel;
// connect ports
}
|
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
memwb |
// FlexChannel initiators
get_initiator< exe_out_t > din;
put_initiator< mem_out_t > dout;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Enable fetch
sc_in<bool> fetch_en; // Used to synchronize writeback with fetch at reset.
// Instruction cache pointer to external memory
sc_uint<XLEN> *dmem;
// Thread prototype
void memwb_th(void);
// Function prototypes.
sc_bv<XLEN> ext_sign_byte(sc_bv<BYTE> read_data); // Sign extend byte read from memory. For LB
sc_bv<XLEN> ext_unsign_byte(sc_bv<BYTE> read_data); // Zero extend byte read from memory. For LBU
sc_bv<XLEN> ext_sign_halfword(sc_bv<BYTE*2> read_data); // Sign extend half-word read from memory. For LH
sc_bv<XLEN> ext_unsign_halfword(sc_bv<BYTE*2> read_data); // Zero extend half-word read from memory. For LHU
// Constructor
SC_HAS_PROCESS(memwb);
memwb(sc_module_name name, sc_uint<XLEN> _dmem[DCACHE_SIZE])
: din("din")
, dout("dout")
, clk("clk")
, rst("rst")
, fetch_en("fetch_en")
, dmem(_dmem)
{
SC_CTHREAD(memwb_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
MAP_DCACHE;
}
// Member variables
exe_out_t input;
mem_out_t output;
sc_bv<DATA_SIZE> mem_dout; // Temporarily stores the value read from memory with a load instruction
|
communicationInterface |
sc_in<sc_uint<12> > inData;
sc_in<bool> clock , reset , clear;
sc_out<sc_uint<4> > payloadOut;
sc_out<sc_uint<8> > countOut , errorOut;
void validateData();
SC_CTOR(communicationInterface) {
SC_METHOD(validateData);
sensitive<<clock.pos();
}
|
Functional_bus |
//Input Port
sc_core::sc_in <unsigned int> request_address;
sc_core::sc_in <uint8_t*> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <unsigned int> request_size;
sc_core::sc_in <uint8_t*> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <uint8_t*> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> idx_sensor;
sc_core::sc_out <unsigned int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <uint8_t*> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <unsigned int> size_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master"),
idx_sensor("selected_sensor_from_request")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
private:
int selected_sensor = 0;
Functional_bus(){}
|
Functional_bus |
//Input Port
sc_core::sc_in <int> request_address;
sc_core::sc_in <int> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <int> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <int> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <int> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
void Set_Go(bool flag);
void Set_Slave(int address, bool flag);
private:
int selected_slave = 0;
Functional_bus(){}
|
seq_item_ams |
protected:
cv::Mat tx_img;
public:
// Input clock
sc_core::sc_in<bool> clk;
// Counters
sc_core::sc_in<unsigned int> hcount;
sc_core::sc_in<unsigned int> vcount;
// Output pixel
sc_core::sc_out<sc_uint<N> > o_red;
sc_core::sc_out<sc_uint<N> > o_green;
sc_core::sc_out<sc_uint<N> > o_blue;
SC_CTOR(seq_item_ams)
{
// Read image
const std::string img_path = IPS_IMG_PATH_TB;
cv::Mat read_img = cv::imread(img_path, cv::IMREAD_COLOR);
// CV_8UC3 Type: 8-bit unsigned, 3 channels (e.g., for a color image)
read_img.convertTo(this->tx_img, CV_8UC3);
#ifdef IPS_DEBUG_EN
std::cout << "Loading image: " << img_path << std::endl;
#endif // IPS_DEBUG_EN
// Check if the image is loaded successfully
if (this->tx_img.empty())
{
std::cerr << "Error: Could not open or find the image!" << std::endl;
exit(EXIT_FAILURE);
}
#ifdef IPS_DEBUG_EN
std::cout << "TX image info: ";
std::cout << "rows = " << this->tx_img.rows;
std::cout << " cols = " << this->tx_img.cols;
std::cout << " channels = " << this->tx_img.channels() << std::endl;
#endif // IPS_DEBUG_EN
SC_METHOD(run);
sensitive << clk.pos();
}
void run()
{
if (this->clk.read())
{
const int IMG_ROW = static_cast<int>(this->vcount.read()) - (V_SYNC_PULSE + V_BP);
const int IMG_COL = static_cast<int>(this->hcount.read()) - (H_SYNC_PULSE + H_BP);
#ifdef IPS_DEBUG_EN
std::cout << "TX image: ";
std::cout << "row = " << IMG_ROW;
std::cout << " col = " << IMG_COL;
#endif // IPS_DEBUG_EN
if ((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= static_cast<int>(V_ACTIVE)) || (IMG_COL >= static_cast<int>(H_ACTIVE)))
{
this->o_red.write(0);
this->o_green.write(0);
this->o_blue.write(0);
#ifdef IPS_DEBUG_EN
std::cout << " dpixel = (0,0,0) " << std::endl;
#endif // IPS_DEBUG_EN
}
else
{
cv::Vec3b pixel = tx_img.at<cv::Vec3b>(IMG_ROW, IMG_COL, 0);
this->o_red.write(static_cast<sc_uint<8>>(pixel[0]));
this->o_green.write(static_cast<sc_uint<8>>(pixel[1]));
this->o_blue.write(static_cast<sc_uint<8>>(pixel[2]));
#ifdef IPS_DEBUG_EN
std::cout << " ipixel = (" << static_cast<int>(pixel[0]) << ","
<< static_cast<int>(pixel[1]) << "," << static_cast<int>(pixel[2])
<< ")" << std::endl;
#endif // IPS_DEBUG_EN
}
}
}
|
MIPS |
sc_in<bool> clk;
sc_port<readwrite_if> ioController;
uint32_t breg[32];
Bitmap bg;
SC_CTOR(MIPS) {
SC_METHOD(exec);
sensitive << clk.pos();
const char fn[] = "mandrill2.bmp";
const char mode[] = "rb";
breg[4] = (uint32_t)fn; breg[5] = (uint32_t)mode;
fileOpen();
breg[4] = breg[2];
breg[5] = (uint32_t)&bg.magic_number; breg[6] = 54;
fileRead();
bg.buf = malloc(bg.width*bg.height*bg.bpp/8);
breg[5] = (uint32_t)bg.buf; breg[6] = bg.width*bg.height*bg.bpp/8;
fileRead();
fileClose();
}
~MIPS() {
free(bg.buf);
}
void exec() {
uint32_t ioWord;
static bool inited = false;
if (!inited) {
inited = true;
ioController->read(0xFF400104, 4, &ioWord);
int w = ioWord >> 16, h = ioWord & 0xFFFF;
for (int y = 0; y < h && y < int(bg.height); y++) {
for (int x = 0; x < w && x < int(bg.width); x++) {
uint32_t rgbpixel;
if (bg.bpp == 8) {
uint8_t rawpixel = ((uint8_t*)bg.buf)[(bg.height - 1 - y)*bg.width + x];
rgbpixel = rawpixel | (rawpixel << 8) | (rawpixel << 16);
}
else
rgbpixel = ((uint32_t*)bg.buf)[(bg.height - 1 - y)*bg.width + x];
ioController->write(0xFF000000 + ((y*w + x) << 2), 4, &rgbpixel);
}
}
}
ioController->read(0xFF400000 + 'w', 4, &ioWord);
if (ioWord == 1) {
printf("Insert a string: ");
fflush(stdout);
std::string tmp;
ioController->read(0xFF400114, 4, &ioWord);
while (ioWord != '\r') {
tmp += char(ioWord);
printf("%c", char(ioWord));
fflush(stdout);
ioController->read(0xFF400114, 4, &ioWord);
}
printf("\nString inserted: %s\n", tmp.c_str());
fflush(stdout);
}
ioController->read(0xFF400102, 4, &ioWord);
if (ioWord)
exit();
breg[4] = 33;
sleep();
}
// ===========================================================================
// syscalls (code in v0)
// ===========================================================================
// v0: 2
// a0: 4
// a1: 5
// a2: 6
void exit() { // v0 = 10
sc_stop();
}
void fileOpen() { // v0 = 13
breg[2] = (uint32_t)fopen((const char*)breg[4], (const char*)breg[5]);
}
void fileRead() { // v0 = 14
breg[2] = (uint32_t)fread((void*)breg[5], breg[6], 1, (FILE*)breg[4]);
}
void fileWrite() { // v0 = 15
breg[2] = (uint32_t)fwrite((const void*)breg[5], breg[6], 1, (FILE*)breg[4]);
}
void fileClose() { // v0 = 16
fclose((FILE*)breg[4]);
}
void sleep() { // v0 = 32
Thread::sleep(breg[4]);
}
|
waveform |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_out<DATA1024_t > source;
SC_CTOR(waveform)
{
SC_CTHREAD(waveform_thread,clk.pos());
}
void waveform_thread()
{
DATA1024_t tmp;
tmp.data = 0;
tmp.tlast = 0;
reset.write(true);
float numberGen = 0;
while(true)
{
wait();
reset.write(false);
for(int i=0;i<10;i++)
{
wait();
if(i==10-1)
{
tmp.tlast = 1;
cout << "sending TLAST signal" << endl;
}
else
{
tmp.tlast = 0;
}
if(i==0)
monitor_logger::ingressEvent();
source.write(tmp);
//while(source.num_free() != 0) {wait();}
for(int i=0;i<64;i++)
{
sc_fixed<16,8> fx = sin(numberGen)*120.1f;
//sc_signed us_tmp(fx.wl());
//us_tmp = (fx << (fx.wl()-fx.iwl()));
//tmp.data((16-1) + (16*i),16*i) = (sc_bv<16>)us_tmp;
tmp.data((16-1) + (16*i),16*i) = fixed2bv<16,8>(fx);
sc_bv<16> tmpCheckRaw = (sc_bv<16>)tmp.data((16-1) + (16*i),16*i);
sc_fixed<16,8> tmpCheck = bv2fixed<16,8>(tmpCheckRaw);
if(fx != tmpCheck)
{
sc_stop();
std::cout << "(casting error) got: " << fx << " != " << tmpCheck << std::endl ;//<< " (RAW: " << us_tmp << ")" << std::endl;
}
else
{
//std::cout << "(casting OK) got: " << fx << " != " << tmpCheck << std::endl;
}
numberGen += 0.1;
}
}
}
}
|
monitor |
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<DATA32_t > sink;
std::ofstream ofs;
SC_CTOR(monitor)
:ofs("test.txt", std::ofstream::out)
{
SC_CTHREAD(monitor_thread,clk.pos());
reset_signal_is(reset,true);
}
~monitor()
{
ofs.close();
}
void monitor_thread()
{
DATA32_t tmp;
unsigned countdown = 30;
while(true)
{
sink.read(tmp);
monitor_logger::egressEvent();
//std::string tmp_string = "PKGnr is: " + std::to_string((unsigned)count.read().to_uint()) + "TDATA: " + std::to_string((unsigned long)tmp.data.to_uint());// + " @ " + sc_time_stamp();
//ofs << "@" << sc_time_stamp() << "last: " << tmp.tlast;
//SC_REPORT_WARNING(::SC_ID_ASSERTION_FAILED_, tmp_string.c_str());
//sc_report(true);
sc_signed ss_tmp(32);
ss_tmp = tmp.data;
sc_fixed<32,16> tmpCheck = ((sc_fixed<32*2,16*2>)ss_tmp)>>16;
cout << "TDATA: " << tmpCheck << " @ " << sc_time_stamp() << endl;
if(tmp.tlast==1)
{
//clog << "test2" << sc_time_stamp() << endl;
//cerr << "test" << sc_time_stamp() << endl;
cout << "got TLAST signal @ " << sc_time_stamp() << endl;
}
countdown--;
if(countdown==0)
{
cout << "sc_stop signal" << endl;
sc_stop();
monitor_logger::measure_log();
}
}
}
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<24> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Counter |
//------------------------------Module Inputs------------------------------
// Input clock
sc_in_clk clk;
// Reset bar (reset when 1'b0)
sc_in<bool> rstb;
// Starts the counter
sc_in<bool> enable;
// N-bit output of the counter
sc_out<sc_uint<N > > count_out;
//-----------------------------Local Variables-----------------------------
sc_uint<4> count_int;
public:
/**
* @brief Default constructor for Counter.
*/
SC_CTOR(Counter)
{
SC_METHOD(count);
// Sensitive to the clk posedge to carry out the count
sensitive << clk.pos();
// Sensitive to any state change to go in or out of reset
sensitive << rstb;
}
//---------------------------------Methods---------------------------------
/**
* @brief Methods that counts in every posedge of the clock, unless rstb is
* equal to 0, then the output will be always 0. Enable needs to be
* asserted, otherwise it will show latest value of the counter.
*/
void count();
|
tb_cnn_2d |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
typedef sc_fixed<P_data_W, P_data_P> sc_data;
sc_data func(int a, int b, int c, int d) {
int tmp = ((d & 0xFF) << 24) | ((c & 0xFF) << 16) | ((b & 0xFF) << 8) | ((a & 0xFF) << 0);
return (sc_data)tmp;
}
void func_inv(sc_data in, int &a, int &b, int &c, int &d) {
a = (in.to_int() >> 0) & 0xFF;
b = (in.to_int() >> 8) & 0xFF;
c = (in.to_int() >> 16) & 0xFF;
d = (in.to_int() >> 24) & 0xFF;
}
struct dma_pkg : public hwcore::pipes::sc_fifo_base_dummy<dma_pkg> {
typedef sc_bv<P_input_width> sc_data_raw;
sc_data_raw *data_array;
uint64 size;
|
mon_bufferstreamer |
sc_fifo_out<sc_uint<31> > ctrl_out;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_bufferstreamer) { SC_THREAD(mon_thread); }
void mon_thread() {
uint16_t data_gen = 0;
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
std::cout << "(mon) req. newset (done) " << std::endl;
hwcore::pipes::sc_data_stream_t<16> raw_tmp;
for (int a = 0; a < 5; a++) {
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
for (int i = 0; i < test_size; i++) {
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false")
<< std::endl;
sc_assert((i == test_size - 1) == (raw_tmp.tlast == 1));
sc_assert(tmp == i);
if (tmp != i) {
sc_stop();
}
}
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false") << std::endl;
sc_assert(raw_tmp.EOP());
}
std::cout << "(mon) req. newset (start) " << std::endl;
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
std::cout << "(mon) req. newset (done) " << std::endl;
for (int a = 0; a < 5; a++) {
ctrl_out.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
for (int i = 0; i < test_size; i++) {
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false")
<< std::endl;
sc_assert((i == test_size - 1) == (raw_tmp.tlast == 1));
sc_assert(tmp == i + 0xBF);
if (tmp != i + 0xBF) {
sc_stop();
}
}
raw_tmp = data_in.read();
uint16_t tmp = raw_tmp.data.to_uint();
std::cout << "(mon) got new data: " << tmp << ", last? " << (raw_tmp.tlast ? "true" : "false") << std::endl;
sc_assert(raw_tmp.EOP());
}
std::cout << "Test finish no errors" << std::endl;
sc_stop();
}
|
wave_bufferstreamer |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_bufferstreamer) { SC_THREAD(wave_thread); }
void wave_thread() {
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++) {
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep = 0b11;
tmp.tlast = (i == test_size - 1);
std::cout << "(wave) tlast " << (tmp.tlast ? "true" : "false") << std::endl;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
for (int i = 0; i < test_size; i++) {
tmp.data = i + 0xBF;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.tkeep = 0b11;
tmp.tlast = (i == test_size - 1);
std::cout << "(wave) tlast " << (tmp.tlast ? "true" : "false") << std::endl;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
}
|
tb_bufferstreamer |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
hwcore::pipes::sc_stream_buffer_not_stream_while_write<16> bs_u1;
wave_bufferstreamer wave;
mon_bufferstreamer mon;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > bs2mon_data;
sc_fifo<sc_uint<31> > mon2bs_ctrl;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave2bs_data;
SC_CTOR(tb_bufferstreamer) : bs_u1("BS"), wave("wave"), mon("mon"), clk("clock", sc_time(10, SC_NS)) {
bs_u1.clk(clk);
bs_u1.reset(reset);
bs_u1.din(wave2bs_data);
bs_u1.dout(bs2mon_data);
bs_u1.ctrls_in(mon2bs_ctrl);
wave.data_out(wave2bs_data);
mon.ctrl_out(mon2bs_ctrl);
mon.data_in(bs2mon_data);
}
|
vga |
protected:
// Horizontal count
int h_count;
// Vertical count
int v_count;
public:
#ifndef USING_TLM_TB_EN
// Input clock
sc_core::sc_in<bool> clk;
#else
// Compute the clock time in seconds
const double CLK_TIME = 1.0 / static_cast<double>(CLK_FREQ);
// Internal clock
sc_core::sc_clock clk;
#endif // USING_TLM_TB_EN
// Input pixel
sc_core::sc_in<sc_uint<BITS> > red;
sc_core::sc_in<sc_uint<BITS> > green;
sc_core::sc_in<sc_uint<BITS> > blue;
// Counter outputs
sc_core::sc_out<unsigned int> o_h_count;
sc_core::sc_out<unsigned int> o_v_count;
// Output horizontal sync
sc_core::sc_out<bool> o_hsync;
// Output vertical sync
sc_core::sc_out<bool> o_vsync;
#ifndef USING_TLM_TB_EN
// Output pixel
sc_core::sc_out<sc_uint<BITS> > o_red;
sc_core::sc_out<sc_uint<BITS> > o_green;
sc_core::sc_out<sc_uint<BITS> > o_blue;
#else
unsigned char *tmp_img;
bool start;
bool done;
#endif // USING_TLM_TB_EN
SC_CTOR(vga)
: o_hsync("o_hsync"), o_vsync("o_vsync")
#ifdef USING_TLM_TB_EN
, clk("clk", CLK_TIME, sc_core::SC_SEC)
#endif
{
this->h_count = 0;
this->v_count = 0;
SC_METHOD(run);
#ifndef USING_TLM_TB_EN
sensitive << clk.pos();
#else
sensitive << clk;
this->tmp_img = new unsigned char[H_ACTIVE * V_ACTIVE * 3];
this->start = false;
this->done = false;
#endif // USING_TLM_TB_EN
}
/**
* @brief Override method
* Compute the values output of the VGA
*
*/
void run()
{
if (this->clk.read())
{
#ifdef USING_TLM_TB_EN
if (this->start)
{
#endif // USING_TLM_TB_EN
#ifdef IPS_DEBUG_EN
std::cout << "@" << sc_core::sc_time_stamp().to_seconds() * 1e6 << "us" << std::endl;
#endif // IPS_DEBUG_EN
// Increment H counter
this->h_count++;
// HSYNC pulse
if (this->h_count == H_SYNC_PULSE)
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
else if (this->h_count == (H_SYNC_PULSE + H_BP))
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
else if (this->h_count == (H_SYNC_PULSE + H_BP + H_ACTIVE))
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
// End of HSYNC
else if (this->h_count == (H_SYNC_PULSE + H_BP + H_ACTIVE + H_FP))
{
// Restart H counter
this->o_hsync.write(IPS_VGA_INACTIVE);
this->h_count = 0;
// Increment H counter
this->v_count++;
// VSYNC pulse
if (this->v_count == V_SYNC_PULSE)
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// End of V-sync pulse
else if (this->v_count == (V_SYNC_PULSE + V_BP))
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// V front porch
else if (this->v_count == (V_SYNC_PULSE + V_BP + V_ACTIVE))
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// End of VSYNC
else if (this->v_count == (V_SYNC_PULSE + V_BP + V_ACTIVE + V_FP))
{
this->o_vsync.write(IPS_VGA_INACTIVE);
this->v_count = 0;
this->done = true;
this->start = false;
}
}
this->o_v_count.write(this->v_count);
this->o_h_count.write(this->h_count);
#ifndef USING_TLM_TB_EN
this->o_red.write(this->red.read());
this->o_green.write(this->green.read());
this->o_blue.write(this->blue.read());
#else
const int IMG_ROW = this->v_count - (V_SYNC_PULSE + V_BP);
const int IMG_COL = this->h_count - (H_SYNC_PULSE + H_BP);
if (!((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= V_ACTIVE) || (IMG_COL >= H_ACTIVE)))
{
const unsigned int INDEX = IMG_ROW * (3 * H_ACTIVE) + 3 * IMG_COL;
this->tmp_img[INDEX] = this->red.read();
this->tmp_img[INDEX + 1] = this->green.read();
this->tmp_img[INDEX + 2] = this->blue.read();
}
}
#endif // USING_TLM_TB_EN
}
}
|
mon_split_and_merge |
sc_fifo_in<hwcore::pipes::sc_data_stream_t<16> > data_in;
SC_CTOR(mon_split_and_merge)
{
SC_THREAD(mon_thread);
}
void mon_thread()
{
for(int a=0;a<2;a++)
{
uint16_t data_gen = 0;
hwcore::pipes::sc_data_stream_t<16> tmp_in;
do
{
tmp_in = data_in.read();
std::cout << "(mon) got signal." << std::endl;
//for(int i=0;i<split_N;i++)
//{
if(tmp_in.template getKeep<16>(0)==1)
{
int tmp = tmp_in.template getData<sc_uint, 16>(0).to_uint();
std::cout << "(mon) got new data: " <<tmp << std::endl;
sc_assert(tmp == data_gen);
data_gen++;
}
//}
}while(data_gen < test_size);
}
std::cout << "Test finish no errors" << std::endl;
sc_stop();
}
|
wave_split_and_merge |
sc_fifo_out<hwcore::pipes::sc_data_stream_t<16> > data_out;
SC_CTOR(wave_split_and_merge)
{
SC_THREAD(wave_thread);
}
void wave_thread()
{
hwcore::pipes::sc_data_stream_t<16> tmp;
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.setKeep();
tmp.tlast = 1;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
for (int i = 0; i < test_size; i++)
{
tmp.data = i;
std::cout << "(wave) write new data: " << i << std::endl;
tmp.setKeep();
tmp.tlast = 1;
data_out.write(tmp);
}
tmp.setEOP();
data_out.write(tmp);
}
|
tb_split_and_merge |
#if __RTL_SIMULATION__
//DMA_performance_tester_rtl_wrapper u1;
#else
//DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_split_and_merge wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
hwcore::pipes::sc_stream_splitter<16,split_N,false> u1_ss;
hwcore::hf::sc_static_list<sc_fifo<hwcore::pipes::sc_data_stream_t<16> >, split_N> u1_2_u2;
//sc_fifo<hwcore::pipes::DATA_STREAM_t<16> > u1_2_u2[32];
hwcore::pipes::sc_stream_merge_raw<16,split_N> u2_sm;
sc_fifo<hwcore::pipes::sc_data_stream_t<16*split_N> > u2_2_u3;
hwcore::pipes::sc_stream_resize<16*split_N, 16> u3_sr;
sc_fifo<hwcore::pipes::sc_data_stream_t<16> > u3_2_mon;
mon_split_and_merge mon;
SC_CTOR(tb_split_and_merge)
: u1_ss("u1_ss"),u2_sm("u2_sm"), u3_sr("u3_sr"), wave("wave"), mon("mon"),
clk("clock", sc_time(10, SC_NS)),wave_2_u1(64),u2_2_u3(64), u3_2_mon(64),u1_2_u2("fifo",1)
{
wave.data_out(wave_2_u1);
u1_ss.din(wave_2_u1);
u1_ss.clk(clk);
u1_ss.reset(reset);
for(int i=0;i<split_N;i++)
{
u1_ss.dout[i](u1_2_u2.get(i));
u2_sm.din[i](u1_2_u2.get(i));
}
u2_sm.clk(clk);
u2_sm.reset(reset);
u2_sm.dout(u2_2_u3);
u3_sr.din(u2_2_u3);
u3_sr.clk(clk);
u3_sr.reset(reset);
u3_sr.dout(u3_2_mon);
mon.data_in(u3_2_mon);
}
|
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
hl5 |
public:
// Declaration of clock and reset signals
sc_in_clk clk;
sc_in < bool > rst;
//End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out < bool > main_end;
// Instruction counters
sc_out < long int > icount;
sc_out < long int > j_icount;
sc_out < long int > b_icount;
sc_out < long int > m_icount;
sc_out < long int > o_icount;
// Inter-stage Flex Channels.
put_get_channel< de_out_t > de2exe_ch;
put_get_channel< mem_out_t > wb2de_ch; // Writeback loop
put_get_channel< exe_out_t > exe2mem_ch;
// Forwarding
sc_signal< reg_forward_t > fwd_exe_ch;
SC_HAS_PROCESS(hl5);
hl5(sc_module_name name,
sc_uint<XLEN> imem[ICACHE_SIZE],
sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
// , main_start("main_start")
// , main_end("main_end")
, entry_point("entry_point")
, de2exe_ch("de2exe_ch")
, exe2mem_ch("exe2mem_ch")
, wb2de_ch("wb2de_ch")
, fwd_exe_ch("fwd_exe_ch")
, fede("Fedec", imem)
, exe("Execute")
, mewb("Memory", dmem)
{
// FEDEC
fede.clk(clk);
fede.rst(rst);
fede.dout(de2exe_ch);
fede.feed_from_wb(wb2de_ch);
fede.program_end(program_end);
fede.fetch_en(fetch_en);
fede.entry_point(entry_point);
// fede.main_start(main_start);
// fede.main_end(main_end);
fede.fwd_exe(fwd_exe_ch);
fede.icount(icount);
fede.j_icount(j_icount);
fede.b_icount(b_icount);
fede.m_icount(m_icount);
fede.o_icount(o_icount);
// EXE
exe.clk(clk);
exe.rst(rst);
exe.din(de2exe_ch);
exe.dout(exe2mem_ch);
exe.fwd_exe(fwd_exe_ch);
// MEM
mewb.clk(clk);
mewb.rst(rst);
mewb.din(exe2mem_ch);
mewb.dout(wb2de_ch);
mewb.fetch_en(fetch_en);
}
// Instantiate the modules
fedec_wrapper fede;
execute_wrapper exe;
memwb_wrapper mewb;
|
Filter |
//-----------------------------Local Variables-----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
/**
* @brief Default constructor for Filter
*/
SC_CTOR(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
SC_METHOD(init_kernel);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT& result);
void init_kernel();
|
memory |
protected:
int *mem;
public:
sc_core::sc_in<bool> clk;
sc_core::sc_in<bool> we;
sc_core::sc_in<unsigned long long int> address;
sc_core::sc_in<sc_uint<24>> wdata;
sc_core::sc_out<sc_uint<24>> rdata;
// Constructor for memory
SC_CTOR(memory)
{
this->mem = new int[SIZE];
SC_METHOD(run);
sensitive << clk.pos();
}
void run()
{
if (clk.read())
{
const unsigned long long int ADDR = static_cast<unsigned long long int>(this->address.read());
if (we.read())
{
this->mem[ADDR] = this->wdata.read();
}
this->rdata.write(this->mem[ADDR]);
}
}
|
fedec |
public:
// FlexChannel initiators
put_initiator< de_out_t > dout;
get_initiator< mem_out_t > feed_from_wb;
// Forward
sc_in< reg_forward_t > fwd_exe;
// End of simulation signal.
sc_out < bool > program_end;
// Fetch enable signal.
sc_in < bool > fetch_en;
// Entry point
sc_in < unsigned > entry_point;
// Clock and reset signals
sc_in_clk clk;
sc_in< bool > rst;
// TODO: removeme
// sc_out < bool > main_start;
// sc_out < bool > main_end;
// Instruction counters
sc_out < long int > icount;
sc_out < long int > j_icount;
sc_out < long int > b_icount;
sc_out < long int > m_icount;
sc_out < long int > o_icount;
// Trap signals. TODO: not used. Left for future implementations.
sc_signal< bool > trap; //sc_out
sc_signal< sc_uint<LOG2_NUM_CAUSES> > trap_cause; //sc_out
// Instruction cache pointer to external memory
sc_uint<XLEN> *imem;
// Thread prototype
void fedec_th(void);
// Function prototypes.
sc_bv<PC_LEN> sign_extend_jump(sc_bv<21> imm);
sc_bv<PC_LEN> sign_extend_branch(sc_bv<13> imm);
SC_HAS_PROCESS(fedec);
fedec(sc_module_name name, sc_uint<XLEN> _imem[ICACHE_SIZE])
: dout("dout")
, feed_from_wb("feed_from_wb")
, fwd_exe("fwd_exe")
, program_end("program_end")
, fetch_en("fetch_en")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, clk("clk")
, rst("rst")
, trap("trap")
, trap_cause("trap_cause")
, imem(_imem)
{
SC_CTHREAD(fedec_th, clk.pos());
reset_signal_is(rst, false);
dout.clk_rst(clk, rst);
feed_from_wb.clk_rst(clk, rst);
FLAT_REGFILE;
FLAT_SENTINEL;
MAP_ICACHE;
}
sc_uint<PC_LEN> pc; // Init. to -4, then before first insn fetch it will be updated to 0.
sc_bv<INSN_LEN> insn; // Contains full instruction fetched from IMEM. Used in decoding.
fe_in_t self_feed; // Contains branch and jump data.
// Member variables (DECODE)
mem_out_t feedinput;
de_out_t output;
// NB. x0 is included in this regfile so it is not a real hardcoded 0
// constant. The writeback section of fedec has a guard fro writes on
// x0. For double protection, some instructions that want to write into
// x0 will have their regwrite signal forced to false.
sc_bv<XLEN> regfile[REG_NUM];
// Keeps track of in-flight instructions that are going to overwrite a
// register. Implements a primitive stall mechanism for RAW hazards.
sc_uint<TAG_WIDTH> sentinel[REG_NUM];
// TODO: Used for synchronizing with the wb stage and avoid
// 'hiccuping'. It magically works.
sc_uint<2> position;
bool freeze;
sc_uint<TAG_WIDTH> tag;
sc_uint<PC_LEN> return_address;
|
scheduler_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_dma_weight;
sc_fifo_in<float> from_dma_input;
sc_fifo_in< sc_uint<64> > from_dma_instructions;
sc_fifo_out<float> to_dma;
// PROCESSING ENGINES
sc_fifo_out< sc_uint<34> > npu_instructions[CORE];
sc_fifo_out<float> npu_weight[CORE];
sc_fifo_out<float> npu_input[CORE];
sc_fifo_in<float> npu_output[CORE];
// STATES
sc_uint<64> state_instruction_counter;
sc_uint<64> state_instruction_buffer[INSTRUCTION_BUFFER];
float state_input_buffer[INPUT_BUFFER];
float state_output_buffer[INPUT_BUFFER];
// PROCESS
void process(void);
SC_CTOR(scheduler_module)
{
// Init STATES
state_instruction_counter = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset, true);
}
|
sequenceDetectorTB |
sc_signal<bool> clock , reset , clear , input , output , state;
void clockSignal();
void resetSignal();
void clearSignal();
void inputSignal();
sequenceDetector* sd;
SC_CTOR(sequenceDetectorTB) {
sd = new sequenceDetector ("SD");
sd->clock(clock);
sd->reset(reset);
sd->clear(clear);
sd->input(input);
sd->output(output);
sd->state(state);
SC_THREAD(clockSignal);
SC_THREAD(resetSignal);
SC_THREAD(clearSignal);
SC_THREAD(inputSignal);
}
|
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
img_receiver |
//Array for input image
unsigned char* input_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_receiver)
{
input_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_INPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
FrameProcessing |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint< 8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
SC_CTOR(FrameProcessing)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
cout << "(II) RAWReader :: START" << endl;
uint32_t curr_adr;
// uint16_t curr_x;
// uint16_t curr_y;
while(true)
{
// uint8_t type = e.read();
// uint16_t special = e.read();
uint16_t type = e.read(); type |= ((uint16_t)e.read()) << 8;
uint16_t mot1 = e.read(); mot1 |= ((uint16_t)e.read()) << 8;
uint16_t mot2 = e.read(); mot2 |= ((uint16_t)e.read()) << 8;
uint16_t mot3 = e.read(); mot3 |= ((uint16_t)e.read()) << 8;
if( type == FRAME_NEW_IMAGE )
{
cout << "(II) FrameProcessing :: FRAME_NEW_IMAGE" << endl;
curr_adr = 0;
// curr_y = 0;
for(uint16_t i = 0; i < _BYTE_PAYLOAD_; i += 1)
e.read();
}
else if( type == FRAME_END_IMAGE )
{
cout << "(II) FrameProcessing :: FRAME_END_IMAGE" << endl;
#ifdef _SIMULATION_
wait( 10, SC_US );
sc_stop();
#endif
curr_adr = 0;
// curr_y = 0;
for(uint16_t i = 0; i < _BYTE_PAYLOAD_; i += 1)
e.read();
}
// else if( type == FRAME_NEW_LINE )
// {
// sc_uint< 8> r0 = e.read();
// sc_uint< 8> r1 = e.read();
// sc_uint<16> r2 = (r1, r0);
// curr_y = r2;
// curr_adr = _IMAGE_WIDTH_ * curr_y;
//
// for(uint16_t i = 2; i < _BYTE_PAYLOAD_; i += 1)
// e.read();
// cout << "(II) FrameProcessing :: FRAME_NEW_LINE (" << curr_y << ")" << endl;
// }
// else if( type == FRAME_END_LINE )
// {
// sc_uint< 8> r0 = e.read();
// sc_uint< 8> r1 = e.read();
// sc_uint<16> r2 = (r1, r0);
// curr_y = r2;
// curr_adr = _IMAGE_WIDTH_ * curr_y;
//
// for(uint16_t i = 2; i < _BYTE_PAYLOAD_; i += 1)
// e.read();
// }
else if( type == FRAME_INFOS )
{
//
// On utilise les données provenant de la trame pour calculer
// la position du bloc de pixel dans l'image
//
// cout << mot1 << mot2 << endl;
uint32_t curr_off = mot1 + _IMAGE_WIDTH_ * mot2;
// cout << "(II) FrameProcessing :: FRAME_INFOS :: curr_y = " << curr_y << " :: special = " << special << " :: curr_off = " << curr_off << endl;
for(uint16_t i = 0; i < _BYTE_PAYLOAD_; i += 3)
{
sc_uint< 8> R = e.read();
sc_uint< 8> G = e.read();
sc_uint< 8> B = e.read();
sc_uint<24> RGB = (R, G, B);
rgbv.write( RGB );
addr.write( curr_off );
curr_off += 1;
}
}
else
{
//
// Le type de trame n'est pas reconnu, on met directement a la bin les données
//
cout << "(EE) Error detected on frame type :: flusing data to the bin..." << endl;
for(uint16_t i = 0; i < _BYTE_PAYLOAD_ + _BYTE_CRC_; i += 1)
e.read();
}
}
}
|
my_module1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
// sc_fifo_out< bool > detect1;
SC_CTOR(my_module1) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bit"),
byt("byt"),
crc("crc"),
fra("fra"),
mod2dbl("mod2dbl", 1024),
// dbl2det1("dbl2det1", 32),
// dbl2det2("dbl2det2", 32),
det2dow("det2dow", 32),
dow2bit("dow2bit", 32),
bit2byt("bit2byt", 32),
byt2crc("byt2crc", 32),
crc2fra("crc2fra", 32)
{
// cout<<"Modcompute starting "<<endl;
mod.clock( clock );
mod.reset( reset );
mod.e( e );
mod.s(mod2dbl );
// mod.s2(mod2det2 );
// cout<<"Modcompute ending "<<endl;
// cout<<"Modcompute starting "<<endl;
// dbl.clock( clock );
// dbl.reset( reset );
// dbl.e(mod2dbl);
// dbl.s1(dbl2det1);
// dbl.s2(dbl2det2);
// cout<<"Modcompute ending "<<endl;
det.clock( clock );
det.reset( reset );
det.e(mod2dbl);
// det.e2(dbl2det2);
det.s(det2dow);
// det.detect1(detect1);
dow.clock( clock );
dow.reset( reset );
dow.e(det2dow);
dow.s(dow2bit);
bit.clock( clock );
bit.reset( reset );
bit.e(dow2bit);
bit.s(bit2byt);
byt.clock( clock );
byt.reset( reset );
byt.e(bit2byt);
byt.s(byt2crc);
crc.clock( clock );
crc.reset( reset );
crc.e(byt2crc);
crc.s(crc2fra);
fra.clock( clock );
fra.reset( reset );
fra.e(crc2fra);
fra.addr(addr);
fra.rgbv(rgbv);
}
private:
ModuleCompute mod;
// DOUBLEUR_U dbl;
Detecteur1 det;
DownSampling dow;
BitDecider bit;
BitsToBytes byt;
CRCCheck crc;
FrameProcessing fra;
sc_fifo< sc_uint<8> > mod2dbl;
sc_fifo< sc_uint<8> > dbl2det1;
sc_fifo< sc_uint<8> > dbl2det2;
sc_fifo< sc_uint<8> > det2dow;
sc_fifo< sc_uint<8> > dow2bit;
sc_fifo< sc_uint<1> > bit2byt;
sc_fifo< sc_uint<8> > byt2crc;
sc_fifo< sc_uint<8> > crc2fra;
|
BMPWriter_fixed |
public:
sc_fifo_in< sc_uint<32> > addr;
sc_fifo_in< sc_uint<24> > rgbv;
SC_CTOR(BMPWriter_fixed)
{
SC_THREAD(do_gen);
}
~BMPWriter_fixed( )
{
string fn;
fn = "received_image_fixed";
string filename = fn + ".bmp";
if (fopen(filename.c_str(), "rb")== NULL )
bmp->write( filename.c_str() );
else
{
uint32_t k = 1;
filename = fn+std::to_string(k)+".bmp";
while (fopen(filename.c_str(), "rb")!= NULL )
{
filename = fn+std::to_string(k)+".bmp";
k++;
}
// const char* filename = ("received_image"+std::to_string(k)+".bmp").c_str();
bmp->write(filename.c_str());
}
delete bmp;
}
private:
BMP* bmp;
void do_gen( )
{
bmp = new BMP(640, 480);
uint8_t* ptr = bmp->data.data();
//
// On initilise l'image de sortie dans la couleur rouge pour mieux voir
// les defauts
//
for (uint32_t i = 0; i < (3 * 640 * 480); i += 3)
{
ptr[i + 0] = 0xFF;
ptr[i + 0] = 0x00;
ptr[i + 0] = 0x00;
}
while( true )
{
uint32_t adr = addr.read();
sc_uint<24> rgb = rgbv.read();
uint32_t r = rgb.range(23, 16);
uint32_t g = rgb.range(15, 8);
uint32_t b = rgb.range( 7, 0);
if( (3 * adr) >= (3 * 640 *480) )
{
std::cout << "(WW) Address value is out of image bounds !" << std::endl;
continue;
}
ptr[3 * adr + 0 ] = r;
ptr[3 * adr + 1 ] = g;
ptr[3 * adr + 2 ] = b;
}
}
|
vga |
protected:
// Horizontal count
int h_count;
// Vertical count
int v_count;
public:
#ifndef USING_TLM_TB_EN
// Input clock
sc_core::sc_in<bool> clk;
#else
// Compute the clock time in seconds
const double CLK_TIME = 1.0 / static_cast<double>(CLK_FREQ);
// Internal clock
sc_core::sc_clock clk;
#endif // USING_TLM_TB_EN
// Input pixel
sc_core::sc_in<sc_uint<BITS> > red;
sc_core::sc_in<sc_uint<BITS> > green;
sc_core::sc_in<sc_uint<BITS> > blue;
// Counter outputs
sc_core::sc_out<unsigned int> o_h_count;
sc_core::sc_out<unsigned int> o_v_count;
// Output horizontal sync
sc_core::sc_out<bool> o_hsync;
// Output vertical sync
sc_core::sc_out<bool> o_vsync;
#ifndef USING_TLM_TB_EN
// Output pixel
sc_core::sc_out<sc_uint<BITS> > o_red;
sc_core::sc_out<sc_uint<BITS> > o_green;
sc_core::sc_out<sc_uint<BITS> > o_blue;
#else
unsigned char *tmp_img;
bool start;
bool done;
#endif // USING_TLM_TB_EN
SC_CTOR(vga)
: o_hsync("o_hsync"), o_vsync("o_vsync")
#ifdef USING_TLM_TB_EN
, clk("clk", CLK_TIME, sc_core::SC_SEC)
#endif
{
this->h_count = 0;
this->v_count = 0;
SC_METHOD(run);
#ifndef USING_TLM_TB_EN
sensitive << clk.pos();
#else
sensitive << clk;
this->tmp_img = new unsigned char[H_ACTIVE * V_ACTIVE * 3];
this->start = false;
this->done = false;
#endif // USING_TLM_TB_EN
}
/**
* @brief Override method
* Compute the values output of the VGA
*
*/
void run()
{
if (this->clk.read())
{
#ifdef USING_TLM_TB_EN
if (this->start)
{
#endif // USING_TLM_TB_EN
#ifdef IPS_DEBUG_EN
std::cout << "@" << sc_core::sc_time_stamp().to_seconds() * 1e6 << "us" << std::endl;
#endif // IPS_DEBUG_EN
// Increment H counter
this->h_count++;
// HSYNC pulse
if (this->h_count == H_SYNC_PULSE)
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
else if (this->h_count == (H_SYNC_PULSE + H_BP))
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
else if (this->h_count == (H_SYNC_PULSE + H_BP + H_ACTIVE))
{
this->o_hsync.write(IPS_VGA_ACTIVE);
}
// End of HSYNC
else if (this->h_count == (H_SYNC_PULSE + H_BP + H_ACTIVE + H_FP))
{
// Restart H counter
this->o_hsync.write(IPS_VGA_INACTIVE);
this->h_count = 0;
// Increment H counter
this->v_count++;
// VSYNC pulse
if (this->v_count == V_SYNC_PULSE)
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// End of V-sync pulse
else if (this->v_count == (V_SYNC_PULSE + V_BP))
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// V front porch
else if (this->v_count == (V_SYNC_PULSE + V_BP + V_ACTIVE))
{
this->o_vsync.write(IPS_VGA_ACTIVE);
}
// End of VSYNC
else if (this->v_count == (V_SYNC_PULSE + V_BP + V_ACTIVE + V_FP))
{
this->o_vsync.write(IPS_VGA_INACTIVE);
this->v_count = 0;
this->done = true;
this->start = false;
}
}
this->o_v_count.write(this->v_count);
this->o_h_count.write(this->h_count);
#ifndef USING_TLM_TB_EN
this->o_red.write(this->red.read());
this->o_green.write(this->green.read());
this->o_blue.write(this->blue.read());
#else
const int IMG_ROW = this->v_count - (V_SYNC_PULSE + V_BP);
const int IMG_COL = this->h_count - (H_SYNC_PULSE + H_BP);
if (!((IMG_ROW < 0) || (IMG_COL < 0) || (IMG_ROW >= V_ACTIVE) || (IMG_COL >= H_ACTIVE)))
{
const unsigned int INDEX = IMG_ROW * (3 * H_ACTIVE) + 3 * IMG_COL;
this->tmp_img[INDEX] = this->red.read();
this->tmp_img[INDEX + 1] = this->green.read();
this->tmp_img[INDEX + 2] = this->blue.read();
}
}
#endif // USING_TLM_TB_EN
}
}
|
execute |
// FlexChannel initiators
get_initiator< de_out_t > din;
put_initiator< exe_out_t > dout;
// Forward
sc_out< reg_forward_t > fwd_exe;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Thread prototype
void execute_th(void);
void perf_th(void);
// Support functions
sc_bv<XLEN> sign_extend_imm_s(sc_bv<12> imm); // Sign extend the S-type immediate field.
sc_bv<XLEN> zero_ext_zimm(sc_bv<ZIMM_SIZE> zimm); // Zero extend the zimm field for CSRRxI instructions.
sc_uint<CSR_IDX_LEN> get_csr_index(sc_bv<CSR_ADDR> csr_addr); // Get csr index given the 12-bit CSR address.
void set_csr_value(sc_uint<CSR_IDX_LEN> csr_index, sc_bv<XLEN> rs1, sc_uint<LOG2_CSR_OP_NUM> operation, sc_bv<2> rw_permission); // Perform requested CSR operation (write/set/clear).
// Divider functions
u_div_res_t udiv_func(sc_uint<XLEN> num, sc_uint<XLEN> den);
div_res_t div_func(sc_int<XLEN> num, sc_int<XLEN> den);
// Constructor
SC_CTOR(execute)
: din("din")
, dout("dout")
, fwd_exe("fwd_exe")
, clk("clk")
, rst("rst")
{
SC_CTHREAD(execute_th, clk.pos());
reset_signal_is(rst, false);
SC_CTHREAD(perf_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
HLS_FLATTEN_ARRAY(csr);
}
// Member variables
de_out_t input;
exe_out_t output;
sc_uint<XLEN> csr[CSR_NUM]; // Control and status registers.
|
my_module |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
SC_CTOR(my_module) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bit"),
byt("byt"),
crc("crc"),
fra("fra"),
mod2dbl("mod2dbl", 1024),
// dbl2det1("dbl2det1", 32),
// dbl2det2("dbl2det2", 32),
det2dow("det2dow", 32),
dow2bit("dow2bit", 32),
bit2byt("bit2byt", 32),
byt2crc("byt2crc", 32),
crc2fra("crc2fra", 32)
{
// cout<<"Modcompute starting "<<endl;
mod.clock( clock );
mod.reset( reset );
mod.e( e );
mod.s(mod2dbl );
// mod.s2(mod2det2 );
// cout<<"Modcompute ending "<<endl;
// cout<<"Modcompute starting "<<endl;
// dbl.clock( clock );
// dbl.reset( reset );
// dbl.e(mod2dbl);
// dbl.s1(dbl2det1);
// dbl.s2(dbl2det2);
// cout<<"Modcompute ending "<<endl;
det.clock( clock );
det.reset( reset );
det.e(mod2dbl);
// det.e2(dbl2det2);
det.s(det2dow);
dow.clock( clock );
dow.reset( reset );
dow.e(det2dow);
dow.s(dow2bit);
bit.clock( clock );
bit.reset( reset );
bit.e(dow2bit);
bit.s(bit2byt);
byt.clock( clock );
byt.reset( reset );
byt.e(bit2byt);
byt.s(byt2crc);
crc.clock( clock );
crc.reset( reset );
crc.e(byt2crc);
crc.s(crc2fra);
fra.clock( clock );
fra.reset( reset );
fra.e(crc2fra);
fra.addr(addr);
fra.rgbv(rgbv);
}
private:
ModuleCompute mod;
// DOUBLEUR_U dbl;
Detecteur det;
DownSampling dow;
BitDecider bit;
BitsToBytes byt;
CRCCheck crc;
FrameProcessing fra;
sc_fifo< sc_uint<8> > mod2dbl;
sc_fifo< sc_uint<8> > dbl2det1;
sc_fifo< sc_uint<8> > dbl2det2;
sc_fifo< sc_uint<8> > det2dow;
sc_fifo< sc_uint<8> > dow2bit;
sc_fifo< sc_uint<1> > bit2byt;
sc_fifo< sc_uint<8> > byt2crc;
sc_fifo< sc_uint<8> > crc2fra;
|
hello_world |
private int meaning_of_life; // easter egg
//SC_CTOR -- systemC constructor
SC_CTOR(hello_world) {
meaning_of_life=42;
}
void say_hello() {
cout << "Hello Systemc-2.3.1!\n";
}
void open_magic_box() {
cout << meaning_of_life << endl;
}
|
trames_separ1 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_in <bool> detect;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(trames_separ1)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
// uint64_t counter = 0;
// #endif
// sc_uint<8> buffer[32];
//#pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
const uint8_t data = e.read();
const bool valid = detect.read();
if( valid)
{
const int factor = 2 * 2; // PPM modulation + UpSampling(2)
for(uint16_t i = 0; i < factor * _BITS_HEADER_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_PAYLOAD_; i += 1)
{
s.write( e.read() );
detect.read();
}
for(uint16_t i = 0; i < factor * _BITS_CRC_; i += 1)
{
s.write( e.read() );
detect.read();
}
}
}
}
|
DOUBLEUR_U |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s1;
sc_fifo_out< sc_uint<8> > s2;
SC_CTOR(DOUBLEUR_U)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( true )
{
const uint8_t data = e.read();
s1.write( data );
s2.write( data );
}
}
|
processing_engine_module |
// PORTS
sc_in<bool> clk;
sc_in<bool> reset;
sc_fifo_in<float> from_scheduler_weight;
sc_fifo_in<float> from_scheduler_input;
sc_fifo_in< sc_uint<34> > from_scheduler_instructions;
sc_fifo_out<float> to_scheduler;
// STATES
sc_uint<30> state_length;
sc_uint<4> state_activation_function;
// PROCESS
void process(void);
// UTIL
float sigmoid(float input);
float relu(float input);
float softmax(float input);
SC_CTOR(processing_engine_module)
{
state_length = 0;
state_activation_function = 0;
SC_CTHREAD(process, clk.pos());
reset_signal_is(reset,true);
}
|
tb_pe |
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W + 1 * W>::interface_T interface_W_T;
typedef typename hwcore::pipes::SC_DATA_STREAM_T_trait<1 * W>::interface_T interface_out_T;
sc_clock clk;
sc_in<bool> iclk;
sc_signal<bool> reset;
hwcore::cnn::PE<W, P, N> pe;
sc_fifo<interface_T> xin; // in
sc_fifo<interface_W_T> win;
sc_fifo<interface_out_T> dout; // out
sc_fifo<sc_uint<16> > ctrl_acf; // out
SC_CTOR(tb_pe) : clk("clock", sc_time(10, SC_NS)), pe("pe"), xin(1), dout(1), win(1), ctrl_acf(1) {
iclk(clk);
pe.clk(clk);
pe.reset(reset);
pe.Win(win);
pe.Xin(xin);
pe.dout(dout);
pe.ctrl_acf(ctrl_acf);
SC_CTHREAD(waveform, iclk.pos());
SC_CTHREAD(monitor, iclk.pos());
}
int func(int a, int b) {
int tmpSum = (a << 16) + (b << 16);
return tmpSum;
}
void waveform() {
debug_cout << " - [waveform start]" << std::endl;
interface_W_T Wtmp_out;
interface_T Xtmp_out;
interface_T tmp_out;
reset.write(1);
for (int i = 0; i < 5; i++)
wait();
reset.write(0);
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
ctrl_acf.write(0 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1));
for (int a = 0; a < size; a++) {
for (int b = 0; b < size; b++) {
Xtmp_out.data = func(a, b);
Xtmp_out.setKeep();
Xtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
Wtmp_out.data = ((2 << 16) << 32) | (0 << 16);
Wtmp_out.setKeep();
Wtmp_out.tlast = (a == size - 1 && b == size - 1 ? 1 : 0);
debug_cout << "(waveform)[r]=[" << r << "],[a,b]=[" << a << "," << b << "][data]=[" << func(a, b)
<< "]" << std::endl;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
// dout.write(tmp_out);
debug_cout << "(waveform)[EOP]" << std::endl;
wait();
}
Xtmp_out.data = 2 << 29;
Xtmp_out.setKeep();
Wtmp_out.data = (4 << 16) << 32;
Wtmp_out.setKeep();
ctrl_acf.write(1 | (hwcore::hf::ufixed2bv<15, 1>(1.0).to_uint() << 1)); // use ReLU
for (int i = 0; i < 20; i++) {
Wtmp_out.tlast = (i == 20 - 1 ? 1 : 0);
Xtmp_out.tlast = Wtmp_out.tlast;
xin.write(Xtmp_out);
win.write(Wtmp_out);
}
tmp_out.setEOP();
Wtmp_out.setEOP();
xin.write(tmp_out);
win.write(Wtmp_out);
debug_cout << " - [waveform done]" << std::endl;
while (true) {
wait();
}
}
void monitor() {
debug_cout << " - [waveform monitor]" << std::endl;
sc_int<W> tmp[2];
interface_out_T tmp_in;
int size = 5;
int repeat = 7;
for (int r = 0; r < repeat; r++) {
dout.read(tmp_in);
tmp_in.template getData<sc_int, W, 1>(tmp);
debug_cout << "(monitor)[r]=[" << r << "],[data]=[" << tmp[0].to_int() << "]<=>[expected][" << (200 << 16)
<< "]" << std::endl;
sc_assert((200 << 16) == tmp[0].to_int());
dout.read(tmp_in);
sc_assert(tmp_in.EOP());
debug_cout << "(monitor)[r]=[" << r << "] looking for EOP" << std::endl;
}
dout.read(tmp_in);
sc_assert(!tmp_in.EOP());
for (int i = 0; i < W; i++) {
if (i == W - 1)
sc_assert(tmp_in.data[i] == 0);
else
sc_assert(tmp_in.data[i] == 1);
}
sc_stop();
while (true) {
wait();
}
}
void monitor_vec() {}
|
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* kernel;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
sc_in<IN* > img_window;
sc_out<OUT > result;
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter();
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <int> address;
sc_core::sc_in <int> data_in;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <int> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
my_module2 |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<32> > addr;
sc_fifo_out< sc_uint<24> > rgbv;
// sc_fifo_out< bool > detect1;
SC_CTOR(my_module2) :
mod("mod"),
// dbl("dbl"),
det("det"),
dow("dow"),
bit("bit"),
byt("byt"),
crc("crc"),
fra("fra"),
mod2dbl("mod2dbl", 1024),
// dbl2det1("dbl2det1", 32),
// dbl2det2("dbl2det2", 32),
det2dow("det2dow", 32),
dow2bit("dow2bit", 32),
bit2byt("bit2byt", 32),
byt2crc("byt2crc", 32),
crc2fra("crc2fra", 32)
{
// cout<<"Modcompute starting "<<endl;
mod.clock( clock );
mod.reset( reset );
mod.e( e );
mod.s(mod2dbl );
// mod.s2(mod2det2 );
// cout<<"Modcompute ending "<<endl;
// cout<<"Modcompute starting "<<endl;
// dbl.clock( clock );
// dbl.reset( reset );
// dbl.e(mod2dbl);
// dbl.s1(dbl2det1);
// dbl.s2(dbl2det2);
// cout<<"Modcompute ending "<<endl;
det.clock( clock );
det.reset( reset );
det.e(mod2dbl);
// det.e2(dbl2det2);
det.s(det2dow);
// det.detect1(detect1);
dow.clock( clock );
dow.reset( reset );
dow.e(det2dow);
dow.s(dow2bit);
bit.clock( clock );
bit.reset( reset );
bit.e(dow2bit);
bit.s(bit2byt);
byt.clock( clock );
byt.reset( reset );
byt.e(bit2byt);
byt.s(byt2crc);
crc.clock( clock );
crc.reset( reset );
crc.e(byt2crc);
crc.s(crc2fra);
fra.clock( clock );
fra.reset( reset );
fra.e(crc2fra);
fra.addr(addr);
fra.rgbv(rgbv);
}
private:
ModuleCompute mod;
// DOUBLEUR_U dbl;
Detecteur2 det;
DownSampling dow;
BitDecider bit;
BitsToBytes byt;
CRCCheck crc;
FrameProcessing fra;
sc_fifo< sc_uint<8> > mod2dbl;
sc_fifo< sc_uint<8> > dbl2det1;
sc_fifo< sc_uint<8> > dbl2det2;
sc_fifo< sc_uint<8> > det2dow;
sc_fifo< sc_uint<8> > dow2bit;
sc_fifo< sc_uint<1> > bit2byt;
sc_fifo< sc_uint<8> > byt2crc;
sc_fifo< sc_uint<8> > crc2fra;
|
Sensor_${sensor_name}_functional |
Core* core;
//Input Port
sc_core::sc_in <bool> enable;
sc_core::sc_in <unsigned int> address;
sc_core::sc_in <uint8_t*> data_in;
sc_core::sc_in <unsigned int> req_size;
sc_core::sc_in <bool> flag_wr;
sc_core::sc_in <bool> ready;
//Output Port
sc_core::sc_out <uint8_t*> data_out;
sc_core::sc_out <bool> go;
//Power Port
sc_core::sc_out <int> power_signal;
//Thermal Port
//sc_core::sc_out <int> thermal_signal;
SC_CTOR(Sensor_${sensor_name}_functional):
enable("Enable_signal"),
address("Address"),
data_in("Data_in"),
flag_wr("Flag"),
ready("Ready"),
data_out("Data_out"),
go("Go"),
power_signal("Func_to_Power_signal")
{
//printf("SENSOR :: systemc constructor");
register_memory = new uint8_t[${register_memory}];
SC_THREAD(sensor_logic);
sensitive << ready;
}
void sensor_logic();
Sensor_${sensor_name}_functional(){
//printf("SENSOR :: constructor");
}
~Sensor_${sensor_name}_functional(){
delete[]register_memory;
}
//Register Map
private:
uint8_t* register_memory;
int register_memory_size=${register_memory |
img_transmiter |
//Array for input image
unsigned char* output_image;
sc_dt::uint64 address_offset;
SC_CTOR(img_transmiter)
{
output_image = new unsigned char[IMG_INPUT_SIZE];
address_offset = IMG_OUTPUT_ADDRESS_LO;
}
//Backdoor access to memory
void backdoor_write(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
void backdoor_read(unsigned char*&data, unsigned int data_length, sc_dt::uint64 address);
|
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
|
Edge_Detector |
#ifndef USING_TLM_TB_EN
sc_inout<sc_uint<64>> data;
sc_in<sc_uint<24>> address;
#else
sc_uint<64> data;
sc_uint<64> address;
#endif // USING_TLM_TB_EN
const double delay_full_adder_1_bit = 0.361;
const double delay_full_adder = delay_full_adder_1_bit * 16;
const double delay_multiplier = 9.82;
const sc_int<16> sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
Filter |
protected:
//----------------------------Internal Variables----------------------------
#ifdef IPS_DUMP_EN
sc_trace_file* wf;
#endif // IPS_DUMP_EN
OUT* img_window_tmp;
OUT* kernel;
OUT* result_ptr;
// Event to trigger the filter execution
sc_event event;
//-----------------------------Internal Methods-----------------------------
void exec_filter();
void init();
public:
/**
* @brief Default constructor for Filter
*/
SC_HAS_PROCESS(Filter);
#ifdef IPS_DUMP_EN
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
* @param wf - waveform file pointer
*/
Filter(sc_core::sc_module_name name, sc_core::sc_trace_file* wf)
: sc_core::sc_module(name), wf(wf)
#else
/**
* @brief Construct a new Filter object
*
* @param name - name of the module
*/
Filter(sc_core::sc_module_name name) : sc_core::sc_module(name)
#endif // IPS_DUMP_EN
{
// Calling this method by default since it is no time consumer
// It is assumed that this kernel is already loaded in the model
// Kernel does not change after synthesis
SC_METHOD(init);
// Thread waiting for the request
SC_THREAD(exec_filter);
}
//---------------------------------Methods---------------------------------
void filter(IN* img_window, OUT* result);
|
tb |
public:
// Declaration of clock and reset parameters
sc_in < bool > clk;
sc_in < bool > rst;
// End of simulation signal.
sc_in < bool > program_end;
// Fetch enable signal.
sc_out < bool > fetch_en;
// CPU Reset
sc_out < bool > cpu_rst;
// Entry point
sc_out < unsigned > entry_point;
// TODO: removeme
// sc_in < bool > main_start;
// sc_in < bool > main_end;
// Instruction counters
sc_in < long int > icount;
sc_in < long int > j_icount;
sc_in < long int > b_icount;
sc_in < long int > m_icount;
sc_in < long int > o_icount;
sc_uint<XLEN> *imem;
sc_uint<XLEN> *dmem;
SC_HAS_PROCESS(tb);
tb(sc_module_name name, sc_uint<XLEN> imem[ICACHE_SIZE], sc_uint<XLEN> dmem[DCACHE_SIZE])
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
// , main_start("main_start")
// , main_end("main_end")
, icount("icount")
, j_icount("j_icount")
, b_icount("b_icount")
, m_icount("m_icount")
, o_icount("o_icount")
, imem(imem)
, dmem(dmem)
{
SC_CTHREAD(source, clk.pos());
reset_signal_is(rst, 0);
SC_CTHREAD(sink, clk.pos());
reset_signal_is(rst, 0);
}
void source();
void sink();
double exec_start;
// double exec_main_start;
|
Tripleur |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int<8> > e;
sc_fifo_out< sc_int<8> > s1;
sc_fifo_out< sc_int<8> > s2;
sc_fifo_out< sc_int<8> > s3;
SC_CTOR(Tripleur)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( true )
{
const uint8_t data = e.read();
s1.write( data );
s2.write( data );
s3.write( data );
}
}
|
TOP |
public:
// Clock and reset
sc_in<bool> clk;
sc_in<bool> rst;
// End of simulation signal.
sc_signal < bool > program_end;
// Fetch enable signal.
sc_signal < bool > fetch_en;
// CPU Reset
sc_signal < bool > cpu_rst;
// Entry point
sc_signal < unsigned > entry_point;
// TODO: removeme
// sc_signal < bool > main_start;
// sc_signal < bool > main_end;
// Instruction counters
sc_signal < long int > icount;
sc_signal < long int > j_icount;
sc_signal < long int > b_icount;
sc_signal < long int > m_icount;
sc_signal < long int > o_icount;
// Cache modeled as arryas
sc_uint<XLEN> imem[ICACHE_SIZE];
sc_uint<XLEN> dmem[DCACHE_SIZE];
/* The testbench, DUT, IMEM and DMEM modules. */
tb *m_tb;
hl5_wrapper *m_dut;
SC_CTOR(TOP)
: clk("clk")
, rst("rst")
, program_end("program_end")
, fetch_en("fetch_en")
, cpu_rst("cpu_rst")
, entry_point("entry_point")
{
m_tb = new tb("tb", imem, dmem);
m_dut = new hl5_wrapper("dut", imem, dmem);
// Connect the design module
m_dut->clk(clk);
m_dut->rst(cpu_rst);
m_dut->entry_point(entry_point);
m_dut->program_end(program_end);
m_dut->fetch_en(fetch_en);
// m_dut->main_start(main_start);
// m_dut->main_end(main_end);
m_dut->icount(icount);
m_dut->j_icount(j_icount);
m_dut->b_icount(b_icount);
m_dut->m_icount(m_icount);
m_dut->o_icount(o_icount);
// Connect the testbench
m_tb->clk(clk);
m_tb->rst(rst);
m_tb->cpu_rst(cpu_rst);
m_tb->entry_point(entry_point);
m_tb->program_end(program_end);
m_tb->fetch_en(fetch_en);
// m_tb->main_start(main_start);
// m_tb->main_end(main_end);
m_tb->icount(icount);
m_tb->j_icount(j_icount);
m_tb->b_icount(b_icount);
m_tb->m_icount(m_icount);
m_tb->o_icount(o_icount);
}
~TOP()
{
delete m_tb;
delete m_dut;
delete imem;
delete dmem;
}
|
ModuleCompute |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_int <8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(ModuleCompute)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
/*
template< int XW, int OW, bool OS >
void ac_sqrt(
ac_int<XW,false> x,
ac_int<OW,OS> &sqrt
)
{
const int RW = (XW+1)/2;
// masks used only to hint synthesis on precision
ac_int<RW+2, false> mask_d = 0;
ac_int<RW+2, false> d = 0;
ac_int<RW, false> r = 0;
ac_int<2*RW, false> z = x;
// needs to pick 2 bits of z for each iteration starting from
// the 2 MSB bits. Inside loop, z will be shifted left by 2 each
// iteration. The bits of interest are always on the same
// position (z_shift+1 downto z_shift)
unsigned int z_shift = (RW-1)*2;
for (int i = RW-1; i >= 0; i--) {
r <<= 1;
mask_d = (mask_d << 2) | 0x3;
d = mask_d & (d << 2) | ((z >> z_shift) & 0x3 );
ac_int<RW+2, false> t = (ac_int<RW+2, false>)(d - (( ((ac_int<RW+1, false>)r) << 1) | 0x1));
if ( !t[RW+1] ) { // since t is unsigned, look at MSB
r |= 0x1;
d = mask_d & t;
}
z <<= 2;
}
sqrt = r;
}
*/
unsigned short int_sqrt32(unsigned short x)
{
unsigned char res = 0;
unsigned char add = 0x80; // 32b = 0x8000
int i;
for(i = 0; i < 8; i++) // 32b = 16
{
unsigned char temp = res | add;
unsigned short g2 = temp * temp;
if (x >= g2)
{
res = temp;
}
add >>=1;
}
return res;
}
void do_gen( )
{
while ( true )
{
//#pragma HLS PIPELINE enable_flush
#if 0
float breal = e.read();
float bimag = e.read();
float resul = sqrt( breal * breal + bimag * bimag);
s.write( (sc_uint<8>)resul );
#else
const sc_int < 8> breal = e.read();
const sc_int < 8> bimag = e.read();
const sc_uint<16> rr = (breal * breal);
const sc_uint<16> ii = (bimag * bimag);
sc_uint< 8> rc = int_sqrt32( rr + ii);
s.write( rc );
#endif
}
}
|
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
mon_CNN |
sc_in<bool> clk;
sc_out<bool> reset;
sc_fifo_in<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > data_in;
SC_CTOR_DEFAULT(mon_CNN) {
SC_CTHREAD(mon_thread, clk.pos());
// sensitive << clk;
}
void mon_thread() {
reset.write(true);
wait();
wait();
wait();
wait();
wait();
wait();
wait();
reset.write(false);
for (int i = 0; i < 20; i++)
wait();
int counter = 1;
int last_count = 1;
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
sc_fixed<DATA_W, DATA_P> Y_golden[16 * 16];
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16; b++) {
sc_fixed<DATA_W, DATA_P> tmp = 0;
for (int wi = 0; wi < 16; wi++) {
tmp += Win[wi + (b * 16)] * Xin[(a * 16) + wi];
}
Y_golden[(a * 16) + b] = tmp;
}
}
sc_fixed<DATA_W, DATA_P> Y[16 * 16];
hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> tmp;
for (int a = 0; a < 16; a++) {
for (int b = 0; b < 16 / OUTPUT_BW_N; b++) {
tmp = data_in.read();
sc_fixed<DATA_W, DATA_P> data_in[OUTPUT_BW_N];
tmp.getDataFixed<DATA_W, DATA_P, OUTPUT_BW_N>(data_in);
for (int i = 0; i < OUTPUT_BW_N; i++) {
Y[(a * 16) + (b * OUTPUT_BW_N) + i] = data_in[i];
HLS_DEBUG(1, 1, 0, "got knew value: ")
std::cout << " |--> " << data_in[i].to_float() << " index nr: " << counter << " tlast? "
<< tmp.tlast.to_int() << std::endl
<< std::flush;
counter++;
}
}
}
bool ok = true;
if (tmp.tlast.to_int() != 1) {
ok = false;
std::cout << "error - missing tlast!!!" << std::endl << std::flush;
}
for (int i = 0; i < 16 * 16; i++) {
std::cout << "[ " << i << " ] Y = " << Y[i].to_float() << std::endl
<< std::flush; // " == Y_golden = " << Y_golden[i].to_float() << std::endl << std::flush;
/* if(Y[i]!=Y_golden[i])
{
std::cout << "error not equal!!!" << std::endl << std::flush;
ok = false;
}*/
}
HLS_DEBUG(1, 1, 0, "Simulation done");
if (!ok) {
HLS_DEBUG(1, 1, 0, "Simulation done - with errors!!!");
}
sc_stop();
}
|
wave_CNN |
SC_MODULE_CLK_RESET_SIGNAL;
sc_fifo_out<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > data_out;
sc_out<sc_uint<16 + 1> > weight_ctrl; //, data_ctrl;
sc_out<sc_uint<16 + 1> > weight_ctrl_replay;
sc_out<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_out<sc_uint<16 + 1> > ctrl_window_size;
sc_out<sc_uint<16 + 1> > ctrl_depth;
sc_out<sc_uint<16 + 1> > ctrl_stride;
sc_out<sc_uint<16 + 1> > ctrl_replay;
sc_out<sc_uint<1 + 1> > ctrl_channel;
sc_out<sc_uint<16 + 1> > ctrl_row_N;
sc_in<sc_uint<1> > ready;
template <class interface, typename T> void do_cmd(interface & itf, T value) {
while (ready.read() == 0) {
wait();
}
itf.write((value << 1) | 0b01);
while (ready.read() == 1) {
wait();
}
while (ready.read() == 0) {
wait();
}
itf.write(0);
wait();
}
SC_CTOR_DEFAULT(wave_CNN) {
SC_CTHREAD(wave_thread, clk.pos());
SC_CTHREAD(sending_ctrls, clk.pos());
}
void sending_ctrls() {
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 20; i++)
wait();
ctrl_channel.write(0);
ctrl_row_N.write(0);
weight_ctrl.write(0);
// data_ctrl.write(0);
do_cmd(ctrl_channel, 0);
do_cmd(ctrl_row_N, 16 / INPUT_BW_N);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
do_cmd(ctrl_depth, 1);
do_cmd(ctrl_replay, 1);
do_cmd(ctrl_stride, 0);
do_cmd(ctrl_row_size_pkg, 1024);
do_cmd(ctrl_window_size, 1);
for (int a = 0; a < 16; a++) {
do_cmd(ctrl_channel, 1);
do_cmd(weight_ctrl, hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);
// do_cmd(data_ctrl,hwcore::pipes::sc_stream_buffer<>::ctrls::newset);
}
while (true) {
wait();
}
}
void wave_thread() {
// sending dummy weights.
wait();
while (reset.read()) {
wait();
}
for (int i = 0; i < 15; i++)
wait();
sc_fixed<DATA_W, DATA_P> value = -1.0;
sc_fixed<DATA_W, DATA_P> value_inc = 0.123;
HLS_DEBUG(1, 1, 0, "sending data -- weights!----------------------");
sc_fixed<DATA_W, DATA_P> Win[16 * 16];
sc_fixed<DATA_W, DATA_P> Xin[16 * 16];
for (int wIdx = 0; wIdx < 16 * 16; wIdx++) {
Win[wIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int xIdx = 0; xIdx < 16 * 16; xIdx++) {
Xin[xIdx] = value;
value += value_inc;
if (value > 1.0) {
value = -1.0;
}
}
for (int a = 0; a < (16 * 16) / INPUT_BW_N; a++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Win[a * INPUT_BW_N]);
tmp.setKeep();
if (a == ((16 * 16) / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
// sending input data
HLS_DEBUG(1, 1, 0, "sending data -- Input!----------------------");
for (int a = 0; a < 16; a++) {
for (int i = 0; i < 16 / INPUT_BW_N; i++) {
hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> tmp;
tmp.setDataFixed<DATA_W, DATA_P, INPUT_BW_N>(&Xin[(i * INPUT_BW_N) + (a * 16)]);
tmp.setKeep();
if (a == (16) - 1 && i == (16 / INPUT_BW_N) - 1) {
tmp.tlast = 1;
HLS_DEBUG(1, 1, 0, "sending Input data -- TLAST!----------------------");
} else {
tmp.tlast = 0;
}
HLS_DEBUG(1, 1, 5, "sending Input data -- %s", tmp.data.to_string().c_str());
data_out.write(tmp);
}
}
/*HLS_DEBUG(1,1,0,"sending data -- Firing!----------------------");
data_ctrl.write(hwcore::pipes::sc_stream_buffer<>::ctrls::reapeat);*/
while (true) {
wait();
}
}
|
tb_CNN |
#if __RTL_SIMULATION__
// DMA_performance_tester_rtl_wrapper u1;
#else
// DMA_performance_tester u1;
#endif
sc_clock clk;
sc_signal<bool> reset;
wave_CNN wave;
sc_fifo<hwcore::pipes::sc_data_stream_t<INPUT_WIDTH> > wave_2_u1;
sc_signal<sc_uint<31 + 1> > weight_ctrl; //, data_ctrl;
sc_signal<sc_uint<16 + 1> > ctrl_row_size_pkg;
sc_signal<sc_uint<16 + 1> > ctrl_window_size;
sc_signal<sc_uint<16 + 1> > ctrl_depth;
sc_signal<sc_uint<16 + 1> > ctrl_stride;
sc_signal<sc_uint<16 + 1> > ctrl_replay;
sc_signal<sc_uint<1 + 1> > ctrl_channel;
sc_signal<sc_uint<16 + 1> > ctrl_row_N;
sc_signal<sc_uint<1> > ready;
// sc_fifo<hwcore::pipes::sc_data_stream_t<16> > wave_2_u1;
::cnn cnn_u1;
// hwcore::cnn::top_cnn<16,8,1,1,16,16> cnn_u1;
sc_fifo<hwcore::pipes::sc_data_stream_t<OUTPUT_WIDTH> > u1_2_mon;
mon_CNN mon;
sc_trace_file *tracePtr;
SC_CTOR_DEFAULT(tb_CNN) : SC_INST(wave), SC_INST(cnn_u1), SC_INST(mon), clk("clk", sc_time(10, SC_NS)) {
SC_MODULE_LINK(wave);
SC_MODULE_LINK(mon);
SC_MODULE_LINK(cnn_u1);
wave.ctrl_row_size_pkg(ctrl_row_size_pkg);
wave.ctrl_window_size(ctrl_window_size);
wave.ctrl_depth(ctrl_depth);
wave.ctrl_stride(ctrl_stride);
wave.ctrl_replay(ctrl_replay);
wave.ready(ready);
wave.data_out(wave_2_u1);
// wave.data_ctrl(data_ctrl);
wave.weight_ctrl(weight_ctrl);
wave.ctrl_row_N(ctrl_row_N);
wave.ctrl_channel(ctrl_channel);
cnn_u1.ready(ready);
cnn_u1.ctrl_row_size_pkg(ctrl_row_size_pkg);
cnn_u1.ctrl_window_size(ctrl_window_size);
cnn_u1.ctrl_depth(ctrl_depth);
cnn_u1.ctrl_stride(ctrl_stride);
cnn_u1.ctrl_replay(ctrl_replay);
cnn_u1.ctrl_row_N(ctrl_row_N);
cnn_u1.weight_ctrls(weight_ctrl);
// cnn_u1.data_ctrls(data_ctrl);
cnn_u1.ctrl_channel(ctrl_channel);
cnn_u1.data_sink(wave_2_u1);
cnn_u1.data_source(u1_2_mon);
mon.data_in(u1_2_mon);
tracePtr = sc_create_vcd_trace_file("tb_CNN");
trace(tracePtr);
}
inline void trace(sc_trace_file * trace) {
SC_TRACE_ADD(clk);
SC_TRACE_ADD(reset);
SC_TRACE_ADD_MODULE(wave_2_u1);
SC_TRACE_ADD_MODULE(data_ctrl);
SC_TRACE_ADD_MODULE(weight_ctrl);
SC_TRACE_ADD_MODULE(ctrl_row_N);
SC_TRACE_ADD_MODULE(ctrl_channel);
SC_TRACE_ADD_MODULE(cnn_u1);
SC_TRACE_ADD_MODULE(u1_2_mon);
}
virtual ~tb_CNN() { sc_close_vcd_trace_file(tracePtr); }
|
jpg_output |
//-----------Internal variables-------------------
// const int Block_rows = 8;
// const int Block_cols = 8;
double *image;
int image_rows = 480;
int image_cols = 640;
signed char eob = 127; // end of block
int quantificator[8][8] = {// quantization table
{16, 11, 10, 16, 24, 40, 51, 61},
{12, 12, 14, 19, 26, 58, 60, 55},
{14, 13, 16, 24, 40, 57, 69, 56},
{14, 17, 22, 29, 51, 87, 80, 62},
{18, 22, 37, 56, 68, 109, 103, 77},
{24, 35, 55, 64, 81, 104, 113, 92},
{49, 64, 78, 87, 103, 121, 120, 101},
{72, 92, 95, 98, 112, 100, 103, 99} |
Detecteur |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
// sc_fifo_in < sc_uint<8> > e2;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(Detecteur):
s_calc("s_calc"),
t_sep("t_sep"),
dbl("dbl"),
dbl2scalc("dbl2scalc",1024),
dbl2tsep("dbl2tsep",1024),
detect("detect", 1024)
{
dbl.clock(clock);
dbl.reset(reset);
dbl.e(e);
dbl.s1(dbl2scalc);
dbl.s2(dbl2tsep);
s_calc.clock(clock);
s_calc.reset(reset);
s_calc.e(dbl2scalc);
s_calc.detect(detect);
t_sep.clock(clock);
t_sep.reset(reset);
t_sep.e(dbl2tsep);
t_sep.detect(detect);
t_sep.s(s);
}
private:
Seuil_calc s_calc;
trames_separ t_sep;
DOUBLEUR_U dbl;
sc_fifo< sc_uint<8> > dbl2scalc;
sc_fifo< sc_uint<8> > dbl2tsep;
sc_fifo <bool> detect;
|
Rgb2Gray |
unsigned char r;
unsigned char g;
unsigned char b;
unsigned char gray_value;
SC_CTOR(Rgb2Gray)
{
}
void set_rgb_pixel(unsigned char r_val, unsigned char g_val, unsigned char b_val);
void compute_gray_value();
unsigned char obtain_gray_value();
|
DownSampling |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(DownSampling)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
const uint8_t scale = 2;
#if 1
while( true )
{
uint32_t sum = e.read();
for(uint32_t j = 1 ; j < scale; j += 1)
sum += (uint32_t)e.read();
s.write( sum / scale );
}
#else
while( true )
{
uint32_t tab[scale];
for(uint32_t j = 0; j < scale; j += 1)
tab[j] = e.read();
uint32_t sum = 0;
for(uint32_t j = 0 ; j < scale; j += 1)
sum += tab[j];
for(uint32_t j = 0 ; j < scale; j += 1)
printf("%3d ", tab[j]);
printf(" => %3d : %3d\n", sum, sum/scale);
s.write( sum / scale );
}
#endif
}
|
BitsToBytes |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<1> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(BitsToBytes)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
#if 1
while ( true )
{
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
uint8_t E = e.read();
v = (v << 1) | E;
}
s.write( v );
}
#else
while ( true )
{
uint8_t bits[8];
for( uint32_t q = 0; q < 8 ; q += 1 )
bits[q] = e.read();
uint8_t v = 0;
for( uint32_t q = 0; q < 8 ; q += 1 )
{
v = (v << 1) | bits[q];
}
for( uint32_t q = 0; q < 8 ; q += 1 )
printf("%d", bits[q]);
printf(" = 0x%2.2X\n", v);
s.write( v );
}
#endif
}
|
Seuil_calc |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out <bool> detect;
SC_CTOR(Seuil_calc)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
// #ifdef _DEBUG_SYNCHRO_
// uint64_t counter = 0;
// detect.write(false);
// #endif
float buffer[32];
// const int factor = 2 * 2; // PPM modulation + UpSampling(2)
#pragma HLS ARRAY_PARTITION variable=buffer complete dim=0
while( true )
{
#pragma HLS PIPELINE
for (int j = 0; j < 32-1; j += 1)
{
// #pragma HLS PIPELINE
buffer[j] = buffer[j+1];
}
buffer[32-1] = e.read();
const float ps = buffer[ 0] + buffer[ 1] + buffer[ 4] + buffer[ 5] + // 2 bits à 1 en PPM
buffer[14] + buffer[15] + buffer[18] + buffer[19]; // 2 bits à 0 en PPM
float sum = 0.0;
for (int j = 0; j < 32; j += 1)
{
// #pragma HLS PIPELINE
const float temp = buffer[j];
const float sqrv = (temp * temp);
sum += sqrv;
}
sum = 8.0f * sum;
float res = (ps*ps / sum );
detect.write(res>0.80f);
}
}
|
Functional_bus |
//Input Port
sc_core::sc_in <int> request_address;
sc_core::sc_in <int> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <int> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <int> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <int> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
void Set_Go(bool flag);
void Set_Slave(int address, bool flag);
private:
int selected_slave = 0;
Functional_bus(){}
|
BitDecider |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<1> > s;
SC_CTOR(BitDecider)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
while ( true )
{
const uint8_t left = e.read();
const uint8_t right = e.read();
const uint8_t bitv = left > right;
#if 0
printf("%3d ? %3d => %d\n", left, right, bitv);
#endif
s.write( bitv );
}
}
|
Edge_Detector |
int localWindow[3][3];
const int sobelGradientX[3][3] = {{-1, 0, 1},
{-2, 0, 2},
{-1, 0, 1} |
memwb |
// FlexChannel initiators
get_initiator< exe_out_t > din;
put_initiator< mem_out_t > dout;
// Clock and reset signals
sc_in_clk clk;
sc_in<bool> rst;
// Enable fetch
sc_in<bool> fetch_en; // Used to synchronize writeback with fetch at reset.
// Instruction cache pointer to external memory
sc_uint<XLEN> *dmem;
// Thread prototype
void memwb_th(void);
// Function prototypes.
sc_bv<XLEN> ext_sign_byte(sc_bv<BYTE> read_data); // Sign extend byte read from memory. For LB
sc_bv<XLEN> ext_unsign_byte(sc_bv<BYTE> read_data); // Zero extend byte read from memory. For LBU
sc_bv<XLEN> ext_sign_halfword(sc_bv<BYTE*2> read_data); // Sign extend half-word read from memory. For LH
sc_bv<XLEN> ext_unsign_halfword(sc_bv<BYTE*2> read_data); // Zero extend half-word read from memory. For LHU
// Constructor
SC_HAS_PROCESS(memwb);
memwb(sc_module_name name, sc_uint<XLEN> _dmem[DCACHE_SIZE])
: din("din")
, dout("dout")
, clk("clk")
, rst("rst")
, fetch_en("fetch_en")
, dmem(_dmem)
{
SC_CTHREAD(memwb_th, clk.pos());
reset_signal_is(rst, false);
din.clk_rst(clk, rst);
dout.clk_rst(clk, rst);
MAP_DCACHE;
}
// Member variables
exe_out_t input;
mem_out_t output;
sc_bv<DATA_SIZE> mem_dout; // Temporarily stores the value read from memory with a load instruction
|
rbm |
sc_in<bool> clk; // clock
sc_in<bool> rst; // reset
// DMA requests interface from memory to device
sc_out<u32> rd_index; // array index (offset from base address)
sc_out<u32> rd_length; // burst size
sc_out<bool> rd_request; // transaction request
sc_in<bool> rd_grant; // transaction grant
//input data read by load
b_get_initiator<u32> data_in; // input
// DMA requests interface from device to memory
sc_out<u32> wr_index; // array index (offset from base address)
sc_out<u32> wr_length; // burst size (in words)
sc_out<bool> wr_request; // transaction request
sc_in<bool> wr_grant; // transaction grant
//output data wrtten by ourput
put_initiator<u32> data_out; // output
sc_out<bool> done;
sc_in<bool> conf_done;
//input data by config
sc_in<u32> conf_num_hidden;
sc_in<u32> conf_num_visible;
sc_in<u32> conf_num_users;
sc_in<u32> conf_num_loops;
sc_in<u32> conf_num_testusers;
sc_in<u32> conf_num_movies;
void config();
void load();
void store();
void train_rbm();
void predict_rbm();
SC_CTOR(rbm)
: clk("clk")
, rst("rst")
, rd_index("rd_index")
, rd_length("rd_length")
, rd_request("rd_request")
, rd_grant("rd_grant")
, data_in("data_in")
, wr_index("wr_index")
, wr_length("wr_length")
, wr_request("wr_request")
, wr_grant("wr_grant")
, data_out("data_out")
, done("done")
, conf_done("cond_done")
, conf_num_hidden("conf_num_hidden")
, conf_num_visible("conf_num_visible")
, conf_num_users("conf_num_users")
, conf_num_testusers("conf_num_testusers")
, conf_num_loops("conf_num_loops")
, conf_num_movies("conf_num_movies")
{
///config
SC_CTHREAD(config, clk.pos());
reset_signal_is(rst, false);
///load
SC_CTHREAD(load, clk.pos());
reset_signal_is(rst, false);
///compute
SC_CTHREAD(train_rbm, clk.pos());
reset_signal_is(rst, false);
set_stack_size(0x500000);
SC_CTHREAD(predict_rbm, clk.pos());
reset_signal_is(rst, false);
set_stack_size(0x500000);
///store
SC_CTHREAD(store, clk.pos());
reset_signal_is(rst, false);
///data channels
data_in.clk_rst(clk, rst);
data_out.clk_rst(clk, rst);
}
void activateHiddenUnits_train(bool pingpong, u16 nh, u16 nv);
void activateVisibleUnits_train(u16 nh, u16 nv);
void activateHiddenUnits_predict(bool pingpong, u16 nh, u16 nv);
void activateVisibleUnits_predict(u16 nh, u16 nv);
DATA01_D rand_gen();
/// --- memory data structures ---
///input data
u8 data[2][NUM_VISIBLE_MAX + 1];
///temporary
bool visible_unit[NUM_VISIBLE_MAX + 1];
bool hidden_unit[NUM_HIDDEN_MAX + 1];
DATA_edge edges[NUM_VISIBLE_MAX + 1][NUM_HIDDEN_MAX + 1];
bool pos[NUM_VISIBLE_MAX + 1][NUM_HIDDEN_MAX + 1];//u16 0/1
bool neg[NUM_VISIBLE_MAX + 1][NUM_HIDDEN_MAX + 1];
DATA_sum_ visibleEnergies[K]; //TODO: maximum 500 k.1 added together, k>0
///output data
bool predict_vector[NUM_VISIBLE_MAX + 1];
u8 predict_result[2][NUM_MOVIE_MAX];//max movies
///random generator numbers
u32 mt[N];
/// --- signals ---
//Written by config_debayer
sc_signal<u16> num_hidden;
sc_signal<u16> num_visible;
sc_signal<u16> num_users;
sc_signal<u16> num_loops;
sc_signal<u16> num_testusers;
sc_signal<u16> num_movies;
sc_signal<bool> init_done;
//Written by load_input
sc_signal<bool> train_input_done;
sc_signal<bool> predict_input_done;
//Written by train_rbm
sc_signal<bool> train_start;
sc_signal<bool> train_done;
sc_signal<int32> mti_signal;
//Written by predict_rbm
sc_signal<bool> predict_start;
sc_signal<bool> predict_done;
//Written by store_output
sc_signal<bool> output_start;
sc_signal<bool> output_done;
|
CRCCheck |
public:
sc_in < bool > clock;
sc_in < bool > reset;
sc_fifo_in < sc_uint<8> > e;
sc_fifo_out< sc_uint<8> > s;
SC_CTOR(CRCCheck)
{
SC_CTHREAD(do_gen, clock.pos());
reset_signal_is(reset,true);
}
private:
void do_gen( )
{
cout << "(II) CRCCheck :: START" << endl;
sc_uint<8> ibuffer[_BYTE_HEADER_ + _BYTE_PAYLOAD_];
const uint32_t P = 0x82f63b78;
while( true )
{
uint32_t R = 0;
for (uint32_t i = 0; i < _BYTE_HEADER_ + _BYTE_PAYLOAD_; i += 1)
{
#pragma HLS PIPELINE
uint8_t v = e.read();
ibuffer[i] = v;
R ^= v;
for (uint32_t j = 0; j < 8; ++j) {
#pragma HLS UNROLL
R = R & 1 ? (R >> 1) ^ P : R >> 1;
}
}
uint8_t crc_t[4];
for (uint32_t i = 0; i < 4; i += 1)
crc_t[i] = e.read();
uint32_t crc = 0;
for (uint32_t i = 0; i < 4; i += 1)
crc = crc << 8 | crc_t[4-1-i];
#if 0
printf("0x%8.8X != 0x%8.8X\n", R, crc);
#endif
if( crc == R )
{
#if 0
printf("(DD) CRC validé...\n");
#endif
for (uint32_t i = 0; i < _BYTE_HEADER_ + _BYTE_PAYLOAD_; ++i) {
#pragma HLS PIPELINE
s.write( ibuffer[i] );
}
}else{
// printf("(DD) CRC NON validé !!!\n");
#if 0
printf("0x%2.2X | ", ibuffer[0].to_uint());
printf("0x%2.2X | 0x", ibuffer[1].to_uint());
for (uint32_t i = _BYTE_HEADER_; i < _BYTE_HEADER_ + _BYTE_PAYLOAD_; ++i)
printf("%2.2X", ibuffer[i].to_uint());
printf(" | 0x%2.2X%2.2X%2.2X%2.2X ", crc_t[0], crc_t[1], crc_t[2], crc_t[3]);
printf("| 0x%8.8X | 0x%8.8X\n", crc, R);
exit( 0 );
#endif
}
}
}
|
Functional_bus |
//Input Port
sc_core::sc_in <unsigned int> request_address;
sc_core::sc_in <uint8_t*> request_data;
sc_core::sc_in <bool> flag_from_core;
sc_core::sc_in <bool> request_ready;
sc_core::sc_in <unsigned int> request_size;
sc_core::sc_in <uint8_t*> data_input_sensor[NUM_SENSORS];
sc_core::sc_in <bool> go_sensors[NUM_SENSORS];
//Output Port
sc_core::sc_out <uint8_t*> request_value;
sc_core::sc_out <bool> request_go;
sc_core::sc_out <int> idx_sensor;
sc_core::sc_out <unsigned int> address_out_sensor[NUM_SENSORS];
sc_core::sc_out <uint8_t*> data_out_sensor[NUM_SENSORS];
sc_core::sc_out <unsigned int> size_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> flag_out_sensor[NUM_SENSORS];
sc_core::sc_out <bool> ready_sensor[NUM_SENSORS];
SC_CTOR(Functional_bus):
request_address("Address_from_Master_to_Bus"),
request_data("Data_from_Master_to_Bus"),
flag_from_core("Flag_from_Master_to_Bus"),
request_ready("Ready_from_Master_to_Bus"),
request_value("Data_from_Bus_to_Master"),
request_go("Go_from_Bus_to_Master"),
idx_sensor("selected_sensor_from_request")
{
SC_THREAD(processing_data);
sensitive << request_ready;
for (int i = 0; i < NUM_SENSORS; i++){
sensitive << go_sensors[i];
}
}
void processing_data();
void response();
private:
int selected_sensor = 0;
Functional_bus(){}
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.